drivers/net/ethernet/intel/igb/e1000_82575.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* e1000_82575
  29  * e1000_82576
  30  */
  31
  32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34 #include <linux/types.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/i2c.h>
  37
  38 #include "e1000_mac.h"
  39 #include "e1000_82575.h"
  40 #include "e1000_i210.h"
  41
  42 static s32  igb_get_invariants_82575(struct e1000_hw *);
  43 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  44 static void igb_release_phy_82575(struct e1000_hw *);
  45 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  46 static void igb_release_nvm_82575(struct e1000_hw *);
  47 static s32  igb_check_for_link_82575(struct e1000_hw *);
  48 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  49 static s32  igb_init_hw_82575(struct e1000_hw *);
  50 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  51 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  52 static s32  igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
  53 static s32  igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
  54 static s32  igb_reset_hw_82575(struct e1000_hw *);
  55 static s32  igb_reset_hw_82580(struct e1000_hw *);
  56 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  57 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
  58 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
  59 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  60 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
  61 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  62 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  63 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  64 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  65                                                  u16 *);
  66 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  67 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  68 static bool igb_sgmii_active_82575(struct e1000_hw *);
  69 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  70 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  71 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  72 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
  73 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
  74 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
  75 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
  76 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
  77 static const u16 e1000_82580_rxpbs_table[] =
  78         { 36, 72, 144, 1, 2, 4, 8, 16,
  79           35, 70, 140 };
  80 #define E1000_82580_RXPBS_TABLE_SIZE \
  81         (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
  82
  83 /**
  84  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
  85  *  @hw: pointer to the HW structure
  86  *
  87  *  Called to determine if the I2C pins are being used for I2C or as an
  88  *  external MDIO interface since the two options are mutually exclusive.
  89  **/
  90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
  91 {
  92         u32 reg = 0;
  93         bool ext_mdio = false;
  94
  95         switch (hw->mac.type) {
  96         case e1000_82575:
  97         case e1000_82576:
  98                 reg = rd32(E1000_MDIC);
  99                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 100                 break;
 101         case e1000_82580:
 102         case e1000_i350:
 103         case e1000_i210:
 104         case e1000_i211:
 105                 reg = rd32(E1000_MDICNFG);
 106                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 107                 break;
 108         default:
 109                 break;
 110         }
 111         return ext_mdio;
 112 }
 113
 114 /**
 115  *  igb_init_phy_params_82575 - Init PHY func ptrs.
 116  *  @hw: pointer to the HW structure
 117  **/
 118 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
 119 {
 120         struct e1000_phy_info *phy = &hw->phy;
 121         s32 ret_val = 0;
 122         u32 ctrl_ext;
 123
 124         if (hw->phy.media_type != e1000_media_type_copper) {
 125                 phy->type = e1000_phy_none;
 126                 goto out;
 127         }
 128
 129         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 130         phy->reset_delay_us     = 100;
 131
 132         ctrl_ext = rd32(E1000_CTRL_EXT);
 133
 134         if (igb_sgmii_active_82575(hw)) {
 135                 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
 136                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 137         } else {
 138                 phy->ops.reset = igb_phy_hw_reset;
 139                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 140         }
 141
 142         wr32(E1000_CTRL_EXT, ctrl_ext);
 143         igb_reset_mdicnfg_82580(hw);
 144
 145         if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
 146                 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
 147                 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
 148         } else {
 149                 switch (hw->mac.type) {
 150                 case e1000_82580:
 151                 case e1000_i350:
 152                         phy->ops.read_reg = igb_read_phy_reg_82580;
 153                         phy->ops.write_reg = igb_write_phy_reg_82580;
 154                         break;
 155                 case e1000_i210:
 156                 case e1000_i211:
 157                         phy->ops.read_reg = igb_read_phy_reg_gs40g;
 158                         phy->ops.write_reg = igb_write_phy_reg_gs40g;
 159                         break;
 160                 default:
 161                         phy->ops.read_reg = igb_read_phy_reg_igp;
 162                         phy->ops.write_reg = igb_write_phy_reg_igp;
 163                 }
 164         }
 165
 166         /* set lan id */
 167         hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
 168                         E1000_STATUS_FUNC_SHIFT;
 169
 170         /* Set phy->phy_addr and phy->id. */
 171         ret_val = igb_get_phy_id_82575(hw);
 172         if (ret_val)
 173                 return ret_val;
 174
 175         /* Verify phy id and set remaining function pointers */
 176         switch (phy->id) {
 177         case I347AT4_E_PHY_ID:
 178         case M88E1112_E_PHY_ID:
 179         case M88E1111_I_PHY_ID:
 180                 phy->type               = e1000_phy_m88;
 181                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 182                 if (phy->id == I347AT4_E_PHY_ID ||
 183                     phy->id == M88E1112_E_PHY_ID)
 184                         phy->ops.get_cable_length =
 185                                          igb_get_cable_length_m88_gen2;
 186                 else
 187                         phy->ops.get_cable_length = igb_get_cable_length_m88;
 188                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 189                 break;
 190         case IGP03E1000_E_PHY_ID:
 191                 phy->type = e1000_phy_igp_3;
 192                 phy->ops.get_phy_info = igb_get_phy_info_igp;
 193                 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
 194                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 195                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
 196                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
 197                 break;
 198         case I82580_I_PHY_ID:
 199         case I350_I_PHY_ID:
 200                 phy->type = e1000_phy_82580;
 201                 phy->ops.force_speed_duplex =
 202                                          igb_phy_force_speed_duplex_82580;
 203                 phy->ops.get_cable_length = igb_get_cable_length_82580;
 204                 phy->ops.get_phy_info = igb_get_phy_info_82580;
 205                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 206                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 207                 break;
 208         case I210_I_PHY_ID:
 209                 phy->type               = e1000_phy_i210;
 210                 phy->ops.check_polarity = igb_check_polarity_m88;
 211                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 212                 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
 213                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 214                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 215                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 216                 break;
 217         default:
 218                 ret_val = -E1000_ERR_PHY;
 219                 goto out;
 220         }
 221
 222 out:
 223         return ret_val;
 224 }
 225
 226 /**
 227  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
 228  *  @hw: pointer to the HW structure
 229  **/
 230 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
 231 {
 232         struct e1000_nvm_info *nvm = &hw->nvm;
 233         u32 eecd = rd32(E1000_EECD);
 234         u16 size;
 235
 236         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 237                      E1000_EECD_SIZE_EX_SHIFT);
 238         /* Added to a constant, "size" becomes the left-shift value
 239          * for setting word_size.
 240          */
 241         size += NVM_WORD_SIZE_BASE_SHIFT;
 242
 243         /* Just in case size is out of range, cap it to the largest
 244          * EEPROM size supported
 245          */
 246         if (size > 15)
 247                 size = 15;
 248
 249         nvm->word_size = 1 << size;
 250         if (hw->mac.type < e1000_i210) {
 251                 nvm->opcode_bits = 8;
 252                 nvm->delay_usec = 1;
 253
 254                 switch (nvm->override) {
 255                 case e1000_nvm_override_spi_large:
 256                         nvm->page_size = 32;
 257                         nvm->address_bits = 16;
 258                         break;
 259                 case e1000_nvm_override_spi_small:
 260                         nvm->page_size = 8;
 261                         nvm->address_bits = 8;
 262                         break;
 263                 default:
 264                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 265                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 266                                             16 : 8;
 267                         break;
 268                 }
 269                 if (nvm->word_size == (1 << 15))
 270                         nvm->page_size = 128;
 271
 272                 nvm->type = e1000_nvm_eeprom_spi;
 273         } else {
 274                 nvm->type = e1000_nvm_flash_hw;
 275         }
 276
 277         /* NVM Function Pointers */
 278         switch (hw->mac.type) {
 279         case e1000_82580:
 280                 nvm->ops.validate = igb_validate_nvm_checksum_82580;
 281                 nvm->ops.update = igb_update_nvm_checksum_82580;
 282                 nvm->ops.acquire = igb_acquire_nvm_82575;
 283                 nvm->ops.release = igb_release_nvm_82575;
 284                 if (nvm->word_size < (1 << 15))
 285                         nvm->ops.read = igb_read_nvm_eerd;
 286                 else
 287                         nvm->ops.read = igb_read_nvm_spi;
 288                 nvm->ops.write = igb_write_nvm_spi;
 289                 break;
 290         case e1000_i350:
 291                 nvm->ops.validate = igb_validate_nvm_checksum_i350;
 292                 nvm->ops.update = igb_update_nvm_checksum_i350;
 293                 nvm->ops.acquire = igb_acquire_nvm_82575;
 294                 nvm->ops.release = igb_release_nvm_82575;
 295                 if (nvm->word_size < (1 << 15))
 296                         nvm->ops.read = igb_read_nvm_eerd;
 297                 else
 298                         nvm->ops.read = igb_read_nvm_spi;
 299                 nvm->ops.write = igb_write_nvm_spi;
 300                 break;
 301         case e1000_i210:
 302                 nvm->ops.validate = igb_validate_nvm_checksum_i210;
 303                 nvm->ops.update   = igb_update_nvm_checksum_i210;
 304                 nvm->ops.acquire = igb_acquire_nvm_i210;
 305                 nvm->ops.release = igb_release_nvm_i210;
 306                 nvm->ops.read    = igb_read_nvm_srrd_i210;
 307                 nvm->ops.write   = igb_write_nvm_srwr_i210;
 308                 nvm->ops.valid_led_default = igb_valid_led_default_i210;
 309                 break;
 310         case e1000_i211:
 311                 nvm->ops.acquire  = igb_acquire_nvm_i210;
 312                 nvm->ops.release  = igb_release_nvm_i210;
 313                 nvm->ops.read     = igb_read_nvm_i211;
 314                 nvm->ops.valid_led_default = igb_valid_led_default_i210;
 315                 nvm->ops.validate = NULL;
 316                 nvm->ops.update   = NULL;
 317                 nvm->ops.write    = NULL;
 318                 break;
 319         default:
 320                 nvm->ops.validate = igb_validate_nvm_checksum;
 321                 nvm->ops.update = igb_update_nvm_checksum;
 322                 nvm->ops.acquire = igb_acquire_nvm_82575;
 323                 nvm->ops.release = igb_release_nvm_82575;
 324                 if (nvm->word_size < (1 << 15))
 325                         nvm->ops.read = igb_read_nvm_eerd;
 326                 else
 327                         nvm->ops.read = igb_read_nvm_spi;
 328                 nvm->ops.write = igb_write_nvm_spi;
 329                 break;
 330         }
 331
 332         return 0;
 333 }
 334
 335 /**
 336  *  igb_init_mac_params_82575 - Init MAC func ptrs.
 337  *  @hw: pointer to the HW structure
 338  **/
 339 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
 340 {
 341         struct e1000_mac_info *mac = &hw->mac;
 342         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 343
 344         /* Set mta register count */
 345         mac->mta_reg_count = 128;
 346         /* Set rar entry count */
 347         switch (mac->type) {
 348         case e1000_82576:
 349                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 350                 break;
 351         case e1000_82580:
 352                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 353                 break;
 354         case e1000_i350:
 355                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 356                 break;
 357         default:
 358                 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 359                 break;
 360         }
 361         /* reset */
 362         if (mac->type >= e1000_82580)
 363                 mac->ops.reset_hw = igb_reset_hw_82580;
 364         else
 365                 mac->ops.reset_hw = igb_reset_hw_82575;
 366
 367         if (mac->type >= e1000_i210) {
 368                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
 369                 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
 370
 371         } else {
 372                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
 373                 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
 374         }
 375
 376         /* Set if part includes ASF firmware */
 377         mac->asf_firmware_present = true;
 378         /* Set if manageability features are enabled. */
 379         mac->arc_subsystem_valid =
 380                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 381                         ? true : false;
 382         /* enable EEE on i350 parts and later parts */
 383         if (mac->type >= e1000_i350)
 384                 dev_spec->eee_disable = false;
 385         else
 386                 dev_spec->eee_disable = true;
 387         /* physical interface link setup */
 388         mac->ops.setup_physical_interface =
 389                 (hw->phy.media_type == e1000_media_type_copper)
 390                         ? igb_setup_copper_link_82575
 391                         : igb_setup_serdes_link_82575;
 392
 393         return 0;
 394 }
 395
 396 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
 397 {
 398         struct e1000_mac_info *mac = &hw->mac;
 399         struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
 400         s32 ret_val;
 401         u32 ctrl_ext = 0;
 402
 403         switch (hw->device_id) {
 404         case E1000_DEV_ID_82575EB_COPPER:
 405         case E1000_DEV_ID_82575EB_FIBER_SERDES:
 406         case E1000_DEV_ID_82575GB_QUAD_COPPER:
 407                 mac->type = e1000_82575;
 408                 break;
 409         case E1000_DEV_ID_82576:
 410         case E1000_DEV_ID_82576_NS:
 411         case E1000_DEV_ID_82576_NS_SERDES:
 412         case E1000_DEV_ID_82576_FIBER:
 413         case E1000_DEV_ID_82576_SERDES:
 414         case E1000_DEV_ID_82576_QUAD_COPPER:
 415         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
 416         case E1000_DEV_ID_82576_SERDES_QUAD:
 417                 mac->type = e1000_82576;
 418                 break;
 419         case E1000_DEV_ID_82580_COPPER:
 420         case E1000_DEV_ID_82580_FIBER:
 421         case E1000_DEV_ID_82580_QUAD_FIBER:
 422         case E1000_DEV_ID_82580_SERDES:
 423         case E1000_DEV_ID_82580_SGMII:
 424         case E1000_DEV_ID_82580_COPPER_DUAL:
 425         case E1000_DEV_ID_DH89XXCC_SGMII:
 426         case E1000_DEV_ID_DH89XXCC_SERDES:
 427         case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 428         case E1000_DEV_ID_DH89XXCC_SFP:
 429                 mac->type = e1000_82580;
 430                 break;
 431         case E1000_DEV_ID_I350_COPPER:
 432         case E1000_DEV_ID_I350_FIBER:
 433         case E1000_DEV_ID_I350_SERDES:
 434         case E1000_DEV_ID_I350_SGMII:
 435                 mac->type = e1000_i350;
 436                 break;
 437         case E1000_DEV_ID_I210_COPPER:
 438         case E1000_DEV_ID_I210_COPPER_OEM1:
 439         case E1000_DEV_ID_I210_COPPER_IT:
 440         case E1000_DEV_ID_I210_FIBER:
 441         case E1000_DEV_ID_I210_SERDES:
 442         case E1000_DEV_ID_I210_SGMII:
 443                 mac->type = e1000_i210;
 444                 break;
 445         case E1000_DEV_ID_I211_COPPER:
 446                 mac->type = e1000_i211;
 447                 break;
 448         default:
 449                 return -E1000_ERR_MAC_INIT;
 450                 break;
 451         }
 452
 453         /* Set media type */
 454         /* The 82575 uses bits 22:23 for link mode. The mode can be changed
 455          * based on the EEPROM. We cannot rely upon device ID. There
 456          * is no distinguishable difference between fiber and internal
 457          * SerDes mode on the 82575. There can be an external PHY attached
 458          * on the SGMII interface. For this, we'll set sgmii_active to true.
 459          */
 460         hw->phy.media_type = e1000_media_type_copper;
 461         dev_spec->sgmii_active = false;
 462
 463         ctrl_ext = rd32(E1000_CTRL_EXT);
 464         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
 465         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 466                 dev_spec->sgmii_active = true;
 467                 break;
 468         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 469         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 470                 hw->phy.media_type = e1000_media_type_internal_serdes;
 471                 break;
 472         default:
 473                 break;
 474         }
 475
 476         /* mac initialization and operations */
 477         ret_val = igb_init_mac_params_82575(hw);
 478         if (ret_val)
 479                 goto out;
 480
 481         /* NVM initialization */
 482         ret_val = igb_init_nvm_params_82575(hw);
 483         if (ret_val)
 484                 goto out;
 485
 486         /* if part supports SR-IOV then initialize mailbox parameters */
 487         switch (mac->type) {
 488         case e1000_82576:
 489         case e1000_i350:
 490                 igb_init_mbx_params_pf(hw);
 491                 break;
 492         default:
 493                 break;
 494         }
 495
 496         /* setup PHY parameters */
 497         ret_val = igb_init_phy_params_82575(hw);
 498
 499 out:
 500         return ret_val;
 501 }
 502
 503 /**
 504  *  igb_acquire_phy_82575 - Acquire rights to access PHY
 505  *  @hw: pointer to the HW structure
 506  *
 507  *  Acquire access rights to the correct PHY.  This is a
 508  *  function pointer entry point called by the api module.
 509  **/
 510 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 511 {
 512         u16 mask = E1000_SWFW_PHY0_SM;
 513
 514         if (hw->bus.func == E1000_FUNC_1)
 515                 mask = E1000_SWFW_PHY1_SM;
 516         else if (hw->bus.func == E1000_FUNC_2)
 517                 mask = E1000_SWFW_PHY2_SM;
 518         else if (hw->bus.func == E1000_FUNC_3)
 519                 mask = E1000_SWFW_PHY3_SM;
 520
 521         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 522 }
 523
 524 /**
 525  *  igb_release_phy_82575 - Release rights to access PHY
 526  *  @hw: pointer to the HW structure
 527  *
 528  *  A wrapper to release access rights to the correct PHY.  This is a
 529  *  function pointer entry point called by the api module.
 530  **/
 531 static void igb_release_phy_82575(struct e1000_hw *hw)
 532 {
 533         u16 mask = E1000_SWFW_PHY0_SM;
 534
 535         if (hw->bus.func == E1000_FUNC_1)
 536                 mask = E1000_SWFW_PHY1_SM;
 537         else if (hw->bus.func == E1000_FUNC_2)
 538                 mask = E1000_SWFW_PHY2_SM;
 539         else if (hw->bus.func == E1000_FUNC_3)
 540                 mask = E1000_SWFW_PHY3_SM;
 541
 542         hw->mac.ops.release_swfw_sync(hw, mask);
 543 }
 544
 545 /**
 546  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 547  *  @hw: pointer to the HW structure
 548  *  @offset: register offset to be read
 549  *  @data: pointer to the read data
 550  *
 551  *  Reads the PHY register at offset using the serial gigabit media independent
 552  *  interface and stores the retrieved information in data.
 553  **/
 554 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 555                                           u16 *data)
 556 {
 557         s32 ret_val = -E1000_ERR_PARAM;
 558
 559         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 560                 hw_dbg("PHY Address %u is out of range\n", offset);
 561                 goto out;
 562         }
 563
 564         ret_val = hw->phy.ops.acquire(hw);
 565         if (ret_val)
 566                 goto out;
 567
 568         ret_val = igb_read_phy_reg_i2c(hw, offset, data);
 569
 570         hw->phy.ops.release(hw);
 571
 572 out:
 573         return ret_val;
 574 }
 575
 576 /**
 577  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 578  *  @hw: pointer to the HW structure
 579  *  @offset: register offset to write to
 580  *  @data: data to write at register offset
 581  *
 582  *  Writes the data to PHY register at the offset using the serial gigabit
 583  *  media independent interface.
 584  **/
 585 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 586                                            u16 data)
 587 {
 588         s32 ret_val = -E1000_ERR_PARAM;
 589
 590
 591         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 592                 hw_dbg("PHY Address %d is out of range\n", offset);
 593                 goto out;
 594         }
 595
 596         ret_val = hw->phy.ops.acquire(hw);
 597         if (ret_val)
 598                 goto out;
 599
 600         ret_val = igb_write_phy_reg_i2c(hw, offset, data);
 601
 602         hw->phy.ops.release(hw);
 603
 604 out:
 605         return ret_val;
 606 }
 607
 608 /**
 609  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
 610  *  @hw: pointer to the HW structure
 611  *
 612  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 613  *  sgmi interface.
 614  **/
 615 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 616 {
 617         struct e1000_phy_info *phy = &hw->phy;
 618         s32  ret_val = 0;
 619         u16 phy_id;
 620         u32 ctrl_ext;
 621         u32 mdic;
 622
 623         /* For SGMII PHYs, we try the list of possible addresses until
 624          * we find one that works.  For non-SGMII PHYs
 625          * (e.g. integrated copper PHYs), an address of 1 should
 626          * work.  The result of this function should mean phy->phy_addr
 627          * and phy->id are set correctly.
 628          */
 629         if (!(igb_sgmii_active_82575(hw))) {
 630                 phy->addr = 1;
 631                 ret_val = igb_get_phy_id(hw);
 632                 goto out;
 633         }
 634
 635         if (igb_sgmii_uses_mdio_82575(hw)) {
 636                 switch (hw->mac.type) {
 637                 case e1000_82575:
 638                 case e1000_82576:
 639                         mdic = rd32(E1000_MDIC);
 640                         mdic &= E1000_MDIC_PHY_MASK;
 641                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 642                         break;
 643                 case e1000_82580:
 644                 case e1000_i350:
 645                 case e1000_i210:
 646                 case e1000_i211:
 647                         mdic = rd32(E1000_MDICNFG);
 648                         mdic &= E1000_MDICNFG_PHY_MASK;
 649                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 650                         break;
 651                 default:
 652                         ret_val = -E1000_ERR_PHY;
 653                         goto out;
 654                         break;
 655                 }
 656                 ret_val = igb_get_phy_id(hw);
 657                 goto out;
 658         }
 659
 660         /* Power on sgmii phy if it is disabled */
 661         ctrl_ext = rd32(E1000_CTRL_EXT);
 662         wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 663         wrfl();
 664         msleep(300);
 665
 666         /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
 667          * Therefore, we need to test 1-7
 668          */
 669         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 670                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 671                 if (ret_val == 0) {
 672                         hw_dbg("Vendor ID 0x%08X read at address %u\n",
 673                                phy_id, phy->addr);
 674                         /* At the time of this writing, The M88 part is
 675                          * the only supported SGMII PHY product.
 676                          */
 677                         if (phy_id == M88_VENDOR)
 678                                 break;
 679                 } else {
 680                         hw_dbg("PHY address %u was unreadable\n", phy->addr);
 681                 }
 682         }
 683
 684         /* A valid PHY type couldn't be found. */
 685         if (phy->addr == 8) {
 686                 phy->addr = 0;
 687                 ret_val = -E1000_ERR_PHY;
 688                 goto out;
 689         } else {
 690                 ret_val = igb_get_phy_id(hw);
 691         }
 692
 693         /* restore previous sfp cage power state */
 694         wr32(E1000_CTRL_EXT, ctrl_ext);
 695
 696 out:
 697         return ret_val;
 698 }
 699
 700 /**
 701  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 702  *  @hw: pointer to the HW structure
 703  *
 704  *  Resets the PHY using the serial gigabit media independent interface.
 705  **/
 706 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 707 {
 708         s32 ret_val;
 709
 710         /* This isn't a true "hard" reset, but is the only reset
 711          * available to us at this time.
 712          */
 713
 714         hw_dbg("Soft resetting SGMII attached PHY...\n");
 715
 716         /* SFP documentation requires the following to configure the SPF module
 717          * to work on SGMII.  No further documentation is given.
 718          */
 719         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 720         if (ret_val)
 721                 goto out;
 722
 723         ret_val = igb_phy_sw_reset(hw);
 724
 725 out:
 726         return ret_val;
 727 }
 728
 729 /**
 730  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 731  *  @hw: pointer to the HW structure
 732  *  @active: true to enable LPLU, false to disable
 733  *
 734  *  Sets the LPLU D0 state according to the active flag.  When
 735  *  activating LPLU this function also disables smart speed
 736  *  and vice versa.  LPLU will not be activated unless the
 737  *  device autonegotiation advertisement meets standards of
 738  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 739  *  This is a function pointer entry point only called by
 740  *  PHY setup routines.
 741  **/
 742 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 743 {
 744         struct e1000_phy_info *phy = &hw->phy;
 745         s32 ret_val;
 746         u16 data;
 747
 748         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 749         if (ret_val)
 750                 goto out;
 751
 752         if (active) {
 753                 data |= IGP02E1000_PM_D0_LPLU;
 754                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 755                                                  data);
 756                 if (ret_val)
 757                         goto out;
 758
 759                 /* When LPLU is enabled, we should disable SmartSpeed */
 760                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 761                                                 &data);
 762                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 763                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 764                                                  data);
 765                 if (ret_val)
 766                         goto out;
 767         } else {
 768                 data &= ~IGP02E1000_PM_D0_LPLU;
 769                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 770                                                  data);
 771                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 772                  * during Dx states where the power conservation is most
 773                  * important.  During driver activity we should enable
 774                  * SmartSpeed, so performance is maintained.
 775                  */
 776                 if (phy->smart_speed == e1000_smart_speed_on) {
 777                         ret_val = phy->ops.read_reg(hw,
 778                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 779                         if (ret_val)
 780                                 goto out;
 781
 782                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 783                         ret_val = phy->ops.write_reg(hw,
 784                                         IGP01E1000_PHY_PORT_CONFIG, data);
 785                         if (ret_val)
 786                                 goto out;
 787                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 788                         ret_val = phy->ops.read_reg(hw,
 789                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 790                         if (ret_val)
 791                                 goto out;
 792
 793                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 794                         ret_val = phy->ops.write_reg(hw,
 795                                         IGP01E1000_PHY_PORT_CONFIG, data);
 796                         if (ret_val)
 797                                 goto out;
 798                 }
 799         }
 800
 801 out:
 802         return ret_val;
 803 }
 804
 805 /**
 806  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 807  *  @hw: pointer to the HW structure
 808  *  @active: true to enable LPLU, false to disable
 809  *
 810  *  Sets the LPLU D0 state according to the active flag.  When
 811  *  activating LPLU this function also disables smart speed
 812  *  and vice versa.  LPLU will not be activated unless the
 813  *  device autonegotiation advertisement meets standards of
 814  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 815  *  This is a function pointer entry point only called by
 816  *  PHY setup routines.
 817  **/
 818 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 819 {
 820         struct e1000_phy_info *phy = &hw->phy;
 821         s32 ret_val = 0;
 822         u16 data;
 823
 824         data = rd32(E1000_82580_PHY_POWER_MGMT);
 825
 826         if (active) {
 827                 data |= E1000_82580_PM_D0_LPLU;
 828
 829                 /* When LPLU is enabled, we should disable SmartSpeed */
 830                 data &= ~E1000_82580_PM_SPD;
 831         } else {
 832                 data &= ~E1000_82580_PM_D0_LPLU;
 833
 834                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 835                  * during Dx states where the power conservation is most
 836                  * important.  During driver activity we should enable
 837                  * SmartSpeed, so performance is maintained.
 838                  */
 839                 if (phy->smart_speed == e1000_smart_speed_on)
 840                         data |= E1000_82580_PM_SPD;
 841                 else if (phy->smart_speed == e1000_smart_speed_off)
 842                         data &= ~E1000_82580_PM_SPD; }
 843
 844         wr32(E1000_82580_PHY_POWER_MGMT, data);
 845         return ret_val;
 846 }
 847
 848 /**
 849  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
 850  *  @hw: pointer to the HW structure
 851  *  @active: boolean used to enable/disable lplu
 852  *
 853  *  Success returns 0, Failure returns 1
 854  *
 855  *  The low power link up (lplu) state is set to the power management level D3
 856  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 857  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 858  *  is used during Dx states where the power conservation is most important.
 859  *  During driver activity, SmartSpeed should be enabled so performance is
 860  *  maintained.
 861  **/
 862 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 863 {
 864         struct e1000_phy_info *phy = &hw->phy;
 865         s32 ret_val = 0;
 866         u16 data;
 867
 868         data = rd32(E1000_82580_PHY_POWER_MGMT);
 869
 870         if (!active) {
 871                 data &= ~E1000_82580_PM_D3_LPLU;
 872                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 873                  * during Dx states where the power conservation is most
 874                  * important.  During driver activity we should enable
 875                  * SmartSpeed, so performance is maintained.
 876                  */
 877                 if (phy->smart_speed == e1000_smart_speed_on)
 878                         data |= E1000_82580_PM_SPD;
 879                 else if (phy->smart_speed == e1000_smart_speed_off)
 880                         data &= ~E1000_82580_PM_SPD;
 881         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 882                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 883                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 884                 data |= E1000_82580_PM_D3_LPLU;
 885                 /* When LPLU is enabled, we should disable SmartSpeed */
 886                 data &= ~E1000_82580_PM_SPD;
 887         }
 888
 889         wr32(E1000_82580_PHY_POWER_MGMT, data);
 890         return ret_val;
 891 }
 892
 893 /**
 894  *  igb_acquire_nvm_82575 - Request for access to EEPROM
 895  *  @hw: pointer to the HW structure
 896  *
 897  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 898  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 899  *  Return successful if access grant bit set, else clear the request for
 900  *  EEPROM access and return -E1000_ERR_NVM (-1).
 901  **/
 902 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
 903 {
 904         s32 ret_val;
 905
 906         ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
 907         if (ret_val)
 908                 goto out;
 909
 910         ret_val = igb_acquire_nvm(hw);
 911
 912         if (ret_val)
 913                 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
 914
 915 out:
 916         return ret_val;
 917 }
 918
 919 /**
 920  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
 921  *  @hw: pointer to the HW structure
 922  *
 923  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
 924  *  then release the semaphores acquired.
 925  **/
 926 static void igb_release_nvm_82575(struct e1000_hw *hw)
 927 {
 928         igb_release_nvm(hw);
 929         hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
 930 }
 931
 932 /**
 933  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
 934  *  @hw: pointer to the HW structure
 935  *  @mask: specifies which semaphore to acquire
 936  *
 937  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 938  *  will also specify which port we're acquiring the lock for.
 939  **/
 940 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 941 {
 942         u32 swfw_sync;
 943         u32 swmask = mask;
 944         u32 fwmask = mask << 16;
 945         s32 ret_val = 0;
 946         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
 947
 948         while (i < timeout) {
 949                 if (igb_get_hw_semaphore(hw)) {
 950                         ret_val = -E1000_ERR_SWFW_SYNC;
 951                         goto out;
 952                 }
 953
 954                 swfw_sync = rd32(E1000_SW_FW_SYNC);
 955                 if (!(swfw_sync & (fwmask | swmask)))
 956                         break;
 957
 958                 /* Firmware currently using resource (fwmask)
 959                  * or other software thread using resource (swmask)
 960                  */
 961                 igb_put_hw_semaphore(hw);
 962                 mdelay(5);
 963                 i++;
 964         }
 965
 966         if (i == timeout) {
 967                 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 968                 ret_val = -E1000_ERR_SWFW_SYNC;
 969                 goto out;
 970         }
 971
 972         swfw_sync |= swmask;
 973         wr32(E1000_SW_FW_SYNC, swfw_sync);
 974
 975         igb_put_hw_semaphore(hw);
 976
 977 out:
 978         return ret_val;
 979 }
 980
 981 /**
 982  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
 983  *  @hw: pointer to the HW structure
 984  *  @mask: specifies which semaphore to acquire
 985  *
 986  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 987  *  will also specify which port we're releasing the lock for.
 988  **/
 989 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 990 {
 991         u32 swfw_sync;
 992
 993         while (igb_get_hw_semaphore(hw) != 0);
 994         /* Empty */
 995
 996         swfw_sync = rd32(E1000_SW_FW_SYNC);
 997         swfw_sync &= ~mask;
 998         wr32(E1000_SW_FW_SYNC, swfw_sync);
 999
1000         igb_put_hw_semaphore(hw);
1001 }
1002
1003 /**
1004  *  igb_get_cfg_done_82575 - Read config done bit
1005  *  @hw: pointer to the HW structure
1006  *
1007  *  Read the management control register for the config done bit for
1008  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1009  *  to read the config done bit, so an error is *ONLY* logged and returns
1010  *  0.  If we were to return with error, EEPROM-less silicon
1011  *  would not be able to be reset or change link.
1012  **/
1013 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1014 {
1015         s32 timeout = PHY_CFG_TIMEOUT;
1016         s32 ret_val = 0;
1017         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1018
1019         if (hw->bus.func == 1)
1020                 mask = E1000_NVM_CFG_DONE_PORT_1;
1021         else if (hw->bus.func == E1000_FUNC_2)
1022                 mask = E1000_NVM_CFG_DONE_PORT_2;
1023         else if (hw->bus.func == E1000_FUNC_3)
1024                 mask = E1000_NVM_CFG_DONE_PORT_3;
1025
1026         while (timeout) {
1027                 if (rd32(E1000_EEMNGCTL) & mask)
1028                         break;
1029                 msleep(1);
1030                 timeout--;
1031         }
1032         if (!timeout)
1033                 hw_dbg("MNG configuration cycle has not completed.\n");
1034
1035         /* If EEPROM is not marked present, init the PHY manually */
1036         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1037             (hw->phy.type == e1000_phy_igp_3))
1038                 igb_phy_init_script_igp3(hw);
1039
1040         return ret_val;
1041 }
1042
1043 /**
1044  *  igb_check_for_link_82575 - Check for link
1045  *  @hw: pointer to the HW structure
1046  *
1047  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1048  *  use the generic interface for determining link.
1049  **/
1050 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1051 {
1052         s32 ret_val;
1053         u16 speed, duplex;
1054
1055         if (hw->phy.media_type != e1000_media_type_copper) {
1056                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1057                                                              &duplex);
1058                 /* Use this flag to determine if link needs to be checked or
1059                  * not.  If  we have link clear the flag so that we do not
1060                  * continue to check for link.
1061                  */
1062                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1063
1064                 /* Configure Flow Control now that Auto-Neg has completed.
1065                  * First, we need to restore the desired flow control
1066                  * settings because we may have had to re-autoneg with a
1067                  * different link partner.
1068                  */
1069                 ret_val = igb_config_fc_after_link_up(hw);
1070                 if (ret_val)
1071                         hw_dbg("Error configuring flow control\n");
1072         } else {
1073                 ret_val = igb_check_for_copper_link(hw);
1074         }
1075
1076         return ret_val;
1077 }
1078
1079 /**
1080  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1081  *  @hw: pointer to the HW structure
1082  **/
1083 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1084 {
1085         u32 reg;
1086
1087
1088         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1089             !igb_sgmii_active_82575(hw))
1090                 return;
1091
1092         /* Enable PCS to turn on link */
1093         reg = rd32(E1000_PCS_CFG0);
1094         reg |= E1000_PCS_CFG_PCS_EN;
1095         wr32(E1000_PCS_CFG0, reg);
1096
1097         /* Power up the laser */
1098         reg = rd32(E1000_CTRL_EXT);
1099         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1100         wr32(E1000_CTRL_EXT, reg);
1101
1102         /* flush the write to verify completion */
1103         wrfl();
1104         msleep(1);
1105 }
1106
1107 /**
1108  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1109  *  @hw: pointer to the HW structure
1110  *  @speed: stores the current speed
1111  *  @duplex: stores the current duplex
1112  *
1113  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1114  *  duplex, then store the values in the pointers provided.
1115  **/
1116 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1117                                                 u16 *duplex)
1118 {
1119         struct e1000_mac_info *mac = &hw->mac;
1120         u32 pcs;
1121
1122         /* Set up defaults for the return values of this function */
1123         mac->serdes_has_link = false;
1124         *speed = 0;
1125         *duplex = 0;
1126
1127         /* Read the PCS Status register for link state. For non-copper mode,
1128          * the status register is not accurate. The PCS status register is
1129          * used instead.
1130          */
1131         pcs = rd32(E1000_PCS_LSTAT);
1132
1133         /* The link up bit determines when link is up on autoneg. The sync ok
1134          * gets set once both sides sync up and agree upon link. Stable link
1135          * can be determined by checking for both link up and link sync ok
1136          */
1137         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1138                 mac->serdes_has_link = true;
1139
1140                 /* Detect and store PCS speed */
1141                 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1142                         *speed = SPEED_1000;
1143                 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1144                         *speed = SPEED_100;
1145                 } else {
1146                         *speed = SPEED_10;
1147                 }
1148
1149                 /* Detect and store PCS duplex */
1150                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1151                         *duplex = FULL_DUPLEX;
1152                 } else {
1153                         *duplex = HALF_DUPLEX;
1154                 }
1155         }
1156
1157         return 0;
1158 }
1159
1160 /**
1161  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1162  *  @hw: pointer to the HW structure
1163  *
1164  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1165  *  when management pass thru is not enabled.
1166  **/
1167 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1168 {
1169         u32 reg;
1170
1171         if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1172             igb_sgmii_active_82575(hw))
1173                 return;
1174
1175         if (!igb_enable_mng_pass_thru(hw)) {
1176                 /* Disable PCS to turn off link */
1177                 reg = rd32(E1000_PCS_CFG0);
1178                 reg &= ~E1000_PCS_CFG_PCS_EN;
1179                 wr32(E1000_PCS_CFG0, reg);
1180
1181                 /* shutdown the laser */
1182                 reg = rd32(E1000_CTRL_EXT);
1183                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1184                 wr32(E1000_CTRL_EXT, reg);
1185
1186                 /* flush the write to verify completion */
1187                 wrfl();
1188                 msleep(1);
1189         }
1190 }
1191
1192 /**
1193  *  igb_reset_hw_82575 - Reset hardware
1194  *  @hw: pointer to the HW structure
1195  *
1196  *  This resets the hardware into a known state.  This is a
1197  *  function pointer entry point called by the api module.
1198  **/
1199 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1200 {
1201         u32 ctrl, icr;
1202         s32 ret_val;
1203
1204         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1205          * on the last TLP read/write transaction when MAC is reset.
1206          */
1207         ret_val = igb_disable_pcie_master(hw);
1208         if (ret_val)
1209                 hw_dbg("PCI-E Master disable polling has failed.\n");
1210
1211         /* set the completion timeout for interface */
1212         ret_val = igb_set_pcie_completion_timeout(hw);
1213         if (ret_val) {
1214                 hw_dbg("PCI-E Set completion timeout has failed.\n");
1215         }
1216
1217         hw_dbg("Masking off all interrupts\n");
1218         wr32(E1000_IMC, 0xffffffff);
1219
1220         wr32(E1000_RCTL, 0);
1221         wr32(E1000_TCTL, E1000_TCTL_PSP);
1222         wrfl();
1223
1224         msleep(10);
1225
1226         ctrl = rd32(E1000_CTRL);
1227
1228         hw_dbg("Issuing a global reset to MAC\n");
1229         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1230
1231         ret_val = igb_get_auto_rd_done(hw);
1232         if (ret_val) {
1233                 /* When auto config read does not complete, do not
1234                  * return with an error. This can happen in situations
1235                  * where there is no eeprom and prevents getting link.
1236                  */
1237                 hw_dbg("Auto Read Done did not complete\n");
1238         }
1239
1240         /* If EEPROM is not present, run manual init scripts */
1241         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1242                 igb_reset_init_script_82575(hw);
1243
1244         /* Clear any pending interrupt events. */
1245         wr32(E1000_IMC, 0xffffffff);
1246         icr = rd32(E1000_ICR);
1247
1248         /* Install any alternate MAC address into RAR0 */
1249         ret_val = igb_check_alt_mac_addr(hw);
1250
1251         return ret_val;
1252 }
1253
1254 /**
1255  *  igb_init_hw_82575 - Initialize hardware
1256  *  @hw: pointer to the HW structure
1257  *
1258  *  This inits the hardware readying it for operation.
1259  **/
1260 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1261 {
1262         struct e1000_mac_info *mac = &hw->mac;
1263         s32 ret_val;
1264         u16 i, rar_count = mac->rar_entry_count;
1265
1266         /* Initialize identification LED */
1267         ret_val = igb_id_led_init(hw);
1268         if (ret_val) {
1269                 hw_dbg("Error initializing identification LED\n");
1270                 /* This is not fatal and we should not stop init due to this */
1271         }
1272
1273         /* Disabling VLAN filtering */
1274         hw_dbg("Initializing the IEEE VLAN\n");
1275         if (hw->mac.type == e1000_i350)
1276                 igb_clear_vfta_i350(hw);
1277         else
1278                 igb_clear_vfta(hw);
1279
1280         /* Setup the receive address */
1281         igb_init_rx_addrs(hw, rar_count);
1282
1283         /* Zero out the Multicast HASH table */
1284         hw_dbg("Zeroing the MTA\n");
1285         for (i = 0; i < mac->mta_reg_count; i++)
1286                 array_wr32(E1000_MTA, i, 0);
1287
1288         /* Zero out the Unicast HASH table */
1289         hw_dbg("Zeroing the UTA\n");
1290         for (i = 0; i < mac->uta_reg_count; i++)
1291                 array_wr32(E1000_UTA, i, 0);
1292
1293         /* Setup link and flow control */
1294         ret_val = igb_setup_link(hw);
1295
1296         /* Clear all of the statistics registers (clear on read).  It is
1297          * important that we do this after we have tried to establish link
1298          * because the symbol error count will increment wildly if there
1299          * is no link.
1300          */
1301         igb_clear_hw_cntrs_82575(hw);
1302         return ret_val;
1303 }
1304
1305 /**
1306  *  igb_setup_copper_link_82575 - Configure copper link settings
1307  *  @hw: pointer to the HW structure
1308  *
1309  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1310  *  for link, once link is established calls to configure collision distance
1311  *  and flow control are called.
1312  **/
1313 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1314 {
1315         u32 ctrl;
1316         s32  ret_val;
1317         u32 phpm_reg;
1318
1319         ctrl = rd32(E1000_CTRL);
1320         ctrl |= E1000_CTRL_SLU;
1321         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1322         wr32(E1000_CTRL, ctrl);
1323
1324         /* Clear Go Link Disconnect bit */
1325         if (hw->mac.type >= e1000_82580) {
1326                 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1327                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1328                 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1329         }
1330
1331         ret_val = igb_setup_serdes_link_82575(hw);
1332         if (ret_val)
1333                 goto out;
1334
1335         if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1336                 /* allow time for SFP cage time to power up phy */
1337                 msleep(300);
1338
1339                 ret_val = hw->phy.ops.reset(hw);
1340                 if (ret_val) {
1341                         hw_dbg("Error resetting the PHY.\n");
1342                         goto out;
1343                 }
1344         }
1345         switch (hw->phy.type) {
1346         case e1000_phy_i210:
1347         case e1000_phy_m88:
1348                 switch (hw->phy.id) {
1349                 case I347AT4_E_PHY_ID:
1350                 case M88E1112_E_PHY_ID:
1351                 case I210_I_PHY_ID:
1352                         ret_val = igb_copper_link_setup_m88_gen2(hw);
1353                         break;
1354                 default:
1355                         ret_val = igb_copper_link_setup_m88(hw);
1356                         break;
1357                 }
1358                 break;
1359         case e1000_phy_igp_3:
1360                 ret_val = igb_copper_link_setup_igp(hw);
1361                 break;
1362         case e1000_phy_82580:
1363                 ret_val = igb_copper_link_setup_82580(hw);
1364                 break;
1365         default:
1366                 ret_val = -E1000_ERR_PHY;
1367                 break;
1368         }
1369
1370         if (ret_val)
1371                 goto out;
1372
1373         ret_val = igb_setup_copper_link(hw);
1374 out:
1375         return ret_val;
1376 }
1377
1378 /**
1379  *  igb_setup_serdes_link_82575 - Setup link for serdes
1380  *  @hw: pointer to the HW structure
1381  *
1382  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1383  *  used on copper connections where the serialized gigabit media independent
1384  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1385  *  for auto-negotiation or forces speed/duplex.
1386  **/
1387 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1388 {
1389         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1390         bool pcs_autoneg;
1391         s32 ret_val = E1000_SUCCESS;
1392         u16 data;
1393
1394         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1395             !igb_sgmii_active_82575(hw))
1396                 return ret_val;
1397
1398
1399         /* On the 82575, SerDes loopback mode persists until it is
1400          * explicitly turned off or a power cycle is performed.  A read to
1401          * the register does not indicate its status.  Therefore, we ensure
1402          * loopback mode is disabled during initialization.
1403          */
1404         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1405
1406         /* power on the sfp cage if present and turn on I2C */
1407         ctrl_ext = rd32(E1000_CTRL_EXT);
1408         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1409         ctrl_ext |= E1000_CTRL_I2C_ENA;
1410         wr32(E1000_CTRL_EXT, ctrl_ext);
1411
1412         ctrl_reg = rd32(E1000_CTRL);
1413         ctrl_reg |= E1000_CTRL_SLU;
1414
1415         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1416                 /* set both sw defined pins */
1417                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1418
1419                 /* Set switch control to serdes energy detect */
1420                 reg = rd32(E1000_CONNSW);
1421                 reg |= E1000_CONNSW_ENRGSRC;
1422                 wr32(E1000_CONNSW, reg);
1423         }
1424
1425         reg = rd32(E1000_PCS_LCTL);
1426
1427         /* default pcs_autoneg to the same setting as mac autoneg */
1428         pcs_autoneg = hw->mac.autoneg;
1429
1430         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1431         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1432                 /* sgmii mode lets the phy handle forcing speed/duplex */
1433                 pcs_autoneg = true;
1434                 /* autoneg time out should be disabled for SGMII mode */
1435                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1436                 break;
1437         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1438                 /* disable PCS autoneg and support parallel detect only */
1439                 pcs_autoneg = false;
1440         default:
1441                 if (hw->mac.type == e1000_82575 ||
1442                     hw->mac.type == e1000_82576) {
1443                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1444                         if (ret_val) {
1445                                 printk(KERN_DEBUG "NVM Read Error\n\n");
1446                                 return ret_val;
1447                         }
1448
1449                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1450                                 pcs_autoneg = false;
1451                 }
1452
1453                 /* non-SGMII modes only supports a speed of 1000/Full for the
1454                  * link so it is best to just force the MAC and let the pcs
1455                  * link either autoneg or be forced to 1000/Full
1456                  */
1457                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1458                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1459
1460                 /* set speed of 1000/Full if speed/duplex is forced */
1461                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1462                 break;
1463         }
1464
1465         wr32(E1000_CTRL, ctrl_reg);
1466
1467         /* New SerDes mode allows for forcing speed or autonegotiating speed
1468          * at 1gb. Autoneg should be default set by most drivers. This is the
1469          * mode that will be compatible with older link partners and switches.
1470          * However, both are supported by the hardware and some drivers/tools.
1471          */
1472         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1473                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1474
1475         if (pcs_autoneg) {
1476                 /* Set PCS register for autoneg */
1477                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1478                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1479
1480                 /* Disable force flow control for autoneg */
1481                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1482
1483                 /* Configure flow control advertisement for autoneg */
1484                 anadv_reg = rd32(E1000_PCS_ANADV);
1485                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1486                 switch (hw->fc.requested_mode) {
1487                 case e1000_fc_full:
1488                 case e1000_fc_rx_pause:
1489                         anadv_reg |= E1000_TXCW_ASM_DIR;
1490                         anadv_reg |= E1000_TXCW_PAUSE;
1491                         break;
1492                 case e1000_fc_tx_pause:
1493                         anadv_reg |= E1000_TXCW_ASM_DIR;
1494                         break;
1495                 default:
1496                         break;
1497                 }
1498                 wr32(E1000_PCS_ANADV, anadv_reg);
1499
1500                 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1501         } else {
1502                 /* Set PCS register for forced link */
1503                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1504
1505                 /* Force flow control for forced link */
1506                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1507
1508                 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1509         }
1510
1511         wr32(E1000_PCS_LCTL, reg);
1512
1513         if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1514                 igb_force_mac_fc(hw);
1515
1516         return ret_val;
1517 }
1518
1519 /**
1520  *  igb_sgmii_active_82575 - Return sgmii state
1521  *  @hw: pointer to the HW structure
1522  *
1523  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1524  *  which can be enabled for use in the embedded applications.  Simply
1525  *  return the current state of the sgmii interface.
1526  **/
1527 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1528 {
1529         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1530         return dev_spec->sgmii_active;
1531 }
1532
1533 /**
1534  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1535  *  @hw: pointer to the HW structure
1536  *
1537  *  Inits recommended HW defaults after a reset when there is no EEPROM
1538  *  detected. This is only for the 82575.
1539  **/
1540 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1541 {
1542         if (hw->mac.type == e1000_82575) {
1543                 hw_dbg("Running reset init script for 82575\n");
1544                 /* SerDes configuration via SERDESCTRL */
1545                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1546                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1547                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1548                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1549
1550                 /* CCM configuration via CCMCTL register */
1551                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1552                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1553
1554                 /* PCIe lanes configuration */
1555                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1556                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1557                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1558                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1559
1560                 /* PCIe PLL Configuration */
1561                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1562                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1563                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1564         }
1565
1566         return 0;
1567 }
1568
1569 /**
1570  *  igb_read_mac_addr_82575 - Read device MAC address
1571  *  @hw: pointer to the HW structure
1572  **/
1573 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1574 {
1575         s32 ret_val = 0;
1576
1577         /* If there's an alternate MAC address place it in RAR0
1578          * so that it will override the Si installed default perm
1579          * address.
1580          */
1581         ret_val = igb_check_alt_mac_addr(hw);
1582         if (ret_val)
1583                 goto out;
1584
1585         ret_val = igb_read_mac_addr(hw);
1586
1587 out:
1588         return ret_val;
1589 }
1590
1591 /**
1592  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1593  * @hw: pointer to the HW structure
1594  *
1595  * In the case of a PHY power down to save power, or to turn off link during a
1596  * driver unload, or wake on lan is not enabled, remove the link.
1597  **/
1598 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1599 {
1600         /* If the management interface is not enabled, then power down */
1601         if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1602                 igb_power_down_phy_copper(hw);
1603 }
1604
1605 /**
1606  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1607  *  @hw: pointer to the HW structure
1608  *
1609  *  Clears the hardware counters by reading the counter registers.
1610  **/
1611 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1612 {
1613         igb_clear_hw_cntrs_base(hw);
1614
1615         rd32(E1000_PRC64);
1616         rd32(E1000_PRC127);
1617         rd32(E1000_PRC255);
1618         rd32(E1000_PRC511);
1619         rd32(E1000_PRC1023);
1620         rd32(E1000_PRC1522);
1621         rd32(E1000_PTC64);
1622         rd32(E1000_PTC127);
1623         rd32(E1000_PTC255);
1624         rd32(E1000_PTC511);
1625         rd32(E1000_PTC1023);
1626         rd32(E1000_PTC1522);
1627
1628         rd32(E1000_ALGNERRC);
1629         rd32(E1000_RXERRC);
1630         rd32(E1000_TNCRS);
1631         rd32(E1000_CEXTERR);
1632         rd32(E1000_TSCTC);
1633         rd32(E1000_TSCTFC);
1634
1635         rd32(E1000_MGTPRC);
1636         rd32(E1000_MGTPDC);
1637         rd32(E1000_MGTPTC);
1638
1639         rd32(E1000_IAC);
1640         rd32(E1000_ICRXOC);
1641
1642         rd32(E1000_ICRXPTC);
1643         rd32(E1000_ICRXATC);
1644         rd32(E1000_ICTXPTC);
1645         rd32(E1000_ICTXATC);
1646         rd32(E1000_ICTXQEC);
1647         rd32(E1000_ICTXQMTC);
1648         rd32(E1000_ICRXDMTC);
1649
1650         rd32(E1000_CBTMPC);
1651         rd32(E1000_HTDPMC);
1652         rd32(E1000_CBRMPC);
1653         rd32(E1000_RPTHC);
1654         rd32(E1000_HGPTC);
1655         rd32(E1000_HTCBDPC);
1656         rd32(E1000_HGORCL);
1657         rd32(E1000_HGORCH);
1658         rd32(E1000_HGOTCL);
1659         rd32(E1000_HGOTCH);
1660         rd32(E1000_LENERRS);
1661
1662         /* This register should not be read in copper configurations */
1663         if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1664             igb_sgmii_active_82575(hw))
1665                 rd32(E1000_SCVPC);
1666 }
1667
1668 /**
1669  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1670  *  @hw: pointer to the HW structure
1671  *
1672  *  After rx enable if managability is enabled then there is likely some
1673  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
1674  *  function clears the fifos and flushes any packets that came in as rx was
1675  *  being enabled.
1676  **/
1677 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1678 {
1679         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1680         int i, ms_wait;
1681
1682         if (hw->mac.type != e1000_82575 ||
1683             !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1684                 return;
1685
1686         /* Disable all RX queues */
1687         for (i = 0; i < 4; i++) {
1688                 rxdctl[i] = rd32(E1000_RXDCTL(i));
1689                 wr32(E1000_RXDCTL(i),
1690                      rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1691         }
1692         /* Poll all queues to verify they have shut down */
1693         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1694                 msleep(1);
1695                 rx_enabled = 0;
1696                 for (i = 0; i < 4; i++)
1697                         rx_enabled |= rd32(E1000_RXDCTL(i));
1698                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1699                         break;
1700         }
1701
1702         if (ms_wait == 10)
1703                 hw_dbg("Queue disable timed out after 10ms\n");
1704
1705         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1706          * incoming packets are rejected.  Set enable and wait 2ms so that
1707          * any packet that was coming in as RCTL.EN was set is flushed
1708          */
1709         rfctl = rd32(E1000_RFCTL);
1710         wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1711
1712         rlpml = rd32(E1000_RLPML);
1713         wr32(E1000_RLPML, 0);
1714
1715         rctl = rd32(E1000_RCTL);
1716         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1717         temp_rctl |= E1000_RCTL_LPE;
1718
1719         wr32(E1000_RCTL, temp_rctl);
1720         wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1721         wrfl();
1722         msleep(2);
1723
1724         /* Enable RX queues that were previously enabled and restore our
1725          * previous state
1726          */
1727         for (i = 0; i < 4; i++)
1728                 wr32(E1000_RXDCTL(i), rxdctl[i]);
1729         wr32(E1000_RCTL, rctl);
1730         wrfl();
1731
1732         wr32(E1000_RLPML, rlpml);
1733         wr32(E1000_RFCTL, rfctl);
1734
1735         /* Flush receive errors generated by workaround */
1736         rd32(E1000_ROC);
1737         rd32(E1000_RNBC);
1738         rd32(E1000_MPC);
1739 }
1740
1741 /**
1742  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
1743  *  @hw: pointer to the HW structure
1744  *
1745  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1746  *  however the hardware default for these parts is 500us to 1ms which is less
1747  *  than the 10ms recommended by the pci-e spec.  To address this we need to
1748  *  increase the value to either 10ms to 200ms for capability version 1 config,
1749  *  or 16ms to 55ms for version 2.
1750  **/
1751 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1752 {
1753         u32 gcr = rd32(E1000_GCR);
1754         s32 ret_val = 0;
1755         u16 pcie_devctl2;
1756
1757         /* only take action if timeout value is defaulted to 0 */
1758         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1759                 goto out;
1760
1761         /* if capabilities version is type 1 we can write the
1762          * timeout of 10ms to 200ms through the GCR register
1763          */
1764         if (!(gcr & E1000_GCR_CAP_VER2)) {
1765                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1766                 goto out;
1767         }
1768
1769         /* for version 2 capabilities we need to write the config space
1770          * directly in order to set the completion timeout value for
1771          * 16ms to 55ms
1772          */
1773         ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1774                                         &pcie_devctl2);
1775         if (ret_val)
1776                 goto out;
1777
1778         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1779
1780         ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1781                                          &pcie_devctl2);
1782 out:
1783         /* disable completion timeout resend */
1784         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1785
1786         wr32(E1000_GCR, gcr);
1787         return ret_val;
1788 }
1789
1790 /**
1791  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1792  *  @hw: pointer to the hardware struct
1793  *  @enable: state to enter, either enabled or disabled
1794  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
1795  *
1796  *  enables/disables L2 switch anti-spoofing functionality.
1797  **/
1798 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1799 {
1800         u32 reg_val, reg_offset;
1801
1802         switch (hw->mac.type) {
1803         case e1000_82576:
1804                 reg_offset = E1000_DTXSWC;
1805                 break;
1806         case e1000_i350:
1807                 reg_offset = E1000_TXSWC;
1808                 break;
1809         default:
1810                 return;
1811         }
1812
1813         reg_val = rd32(reg_offset);
1814         if (enable) {
1815                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1816                              E1000_DTXSWC_VLAN_SPOOF_MASK);
1817                 /* The PF can spoof - it has to in order to
1818                  * support emulation mode NICs
1819                  */
1820                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1821         } else {
1822                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1823                              E1000_DTXSWC_VLAN_SPOOF_MASK);
1824         }
1825         wr32(reg_offset, reg_val);
1826 }
1827
1828 /**
1829  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1830  *  @hw: pointer to the hardware struct
1831  *  @enable: state to enter, either enabled or disabled
1832  *
1833  *  enables/disables L2 switch loopback functionality.
1834  **/
1835 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1836 {
1837         u32 dtxswc;
1838
1839         switch (hw->mac.type) {
1840         case e1000_82576:
1841                 dtxswc = rd32(E1000_DTXSWC);
1842                 if (enable)
1843                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1844                 else
1845                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1846                 wr32(E1000_DTXSWC, dtxswc);
1847                 break;
1848         case e1000_i350:
1849                 dtxswc = rd32(E1000_TXSWC);
1850                 if (enable)
1851                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1852                 else
1853                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1854                 wr32(E1000_TXSWC, dtxswc);
1855                 break;
1856         default:
1857                 /* Currently no other hardware supports loopback */
1858                 break;
1859         }
1860
1861 }
1862
1863 /**
1864  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
1865  *  @hw: pointer to the hardware struct
1866  *  @enable: state to enter, either enabled or disabled
1867  *
1868  *  enables/disables replication of packets across multiple pools.
1869  **/
1870 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1871 {
1872         u32 vt_ctl = rd32(E1000_VT_CTL);
1873
1874         if (enable)
1875                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1876         else
1877                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1878
1879         wr32(E1000_VT_CTL, vt_ctl);
1880 }
1881
1882 /**
1883  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
1884  *  @hw: pointer to the HW structure
1885  *  @offset: register offset to be read
1886  *  @data: pointer to the read data
1887  *
1888  *  Reads the MDI control register in the PHY at offset and stores the
1889  *  information read to data.
1890  **/
1891 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1892 {
1893         s32 ret_val;
1894
1895         ret_val = hw->phy.ops.acquire(hw);
1896         if (ret_val)
1897                 goto out;
1898
1899         ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1900
1901         hw->phy.ops.release(hw);
1902
1903 out:
1904         return ret_val;
1905 }
1906
1907 /**
1908  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
1909  *  @hw: pointer to the HW structure
1910  *  @offset: register offset to write to
1911  *  @data: data to write to register at offset
1912  *
1913  *  Writes data to MDI control register in the PHY at offset.
1914  **/
1915 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1916 {
1917         s32 ret_val;
1918
1919
1920         ret_val = hw->phy.ops.acquire(hw);
1921         if (ret_val)
1922                 goto out;
1923
1924         ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1925
1926         hw->phy.ops.release(hw);
1927
1928 out:
1929         return ret_val;
1930 }
1931
1932 /**
1933  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1934  *  @hw: pointer to the HW structure
1935  *
1936  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1937  *  the values found in the EEPROM.  This addresses an issue in which these
1938  *  bits are not restored from EEPROM after reset.
1939  **/
1940 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1941 {
1942         s32 ret_val = 0;
1943         u32 mdicnfg;
1944         u16 nvm_data = 0;
1945
1946         if (hw->mac.type != e1000_82580)
1947                 goto out;
1948         if (!igb_sgmii_active_82575(hw))
1949                 goto out;
1950
1951         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1952                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1953                                    &nvm_data);
1954         if (ret_val) {
1955                 hw_dbg("NVM Read Error\n");
1956                 goto out;
1957         }
1958
1959         mdicnfg = rd32(E1000_MDICNFG);
1960         if (nvm_data & NVM_WORD24_EXT_MDIO)
1961                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1962         if (nvm_data & NVM_WORD24_COM_MDIO)
1963                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1964         wr32(E1000_MDICNFG, mdicnfg);
1965 out:
1966         return ret_val;
1967 }
1968
1969 /**
1970  *  igb_reset_hw_82580 - Reset hardware
1971  *  @hw: pointer to the HW structure
1972  *
1973  *  This resets function or entire device (all ports, etc.)
1974  *  to a known state.
1975  **/
1976 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1977 {
1978         s32 ret_val = 0;
1979         /* BH SW mailbox bit in SW_FW_SYNC */
1980         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1981         u32 ctrl, icr;
1982         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1983
1984
1985         hw->dev_spec._82575.global_device_reset = false;
1986
1987         /* due to hw errata, global device reset doesn't always
1988          * work on 82580
1989          */
1990         if (hw->mac.type == e1000_82580)
1991                 global_device_reset = false;
1992
1993         /* Get current control state. */
1994         ctrl = rd32(E1000_CTRL);
1995
1996         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1997          * on the last TLP read/write transaction when MAC is reset.
1998          */
1999         ret_val = igb_disable_pcie_master(hw);
2000         if (ret_val)
2001                 hw_dbg("PCI-E Master disable polling has failed.\n");
2002
2003         hw_dbg("Masking off all interrupts\n");
2004         wr32(E1000_IMC, 0xffffffff);
2005         wr32(E1000_RCTL, 0);
2006         wr32(E1000_TCTL, E1000_TCTL_PSP);
2007         wrfl();
2008
2009         msleep(10);
2010
2011         /* Determine whether or not a global dev reset is requested */
2012         if (global_device_reset &&
2013                 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2014                         global_device_reset = false;
2015
2016         if (global_device_reset &&
2017                 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2018                 ctrl |= E1000_CTRL_DEV_RST;
2019         else
2020                 ctrl |= E1000_CTRL_RST;
2021
2022         wr32(E1000_CTRL, ctrl);
2023         wrfl();
2024
2025         /* Add delay to insure DEV_RST has time to complete */
2026         if (global_device_reset)
2027                 msleep(5);
2028
2029         ret_val = igb_get_auto_rd_done(hw);
2030         if (ret_val) {
2031                 /* When auto config read does not complete, do not
2032                  * return with an error. This can happen in situations
2033                  * where there is no eeprom and prevents getting link.
2034                  */
2035                 hw_dbg("Auto Read Done did not complete\n");
2036         }
2037
2038         /* If EEPROM is not present, run manual init scripts */
2039         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
2040                 igb_reset_init_script_82575(hw);
2041
2042         /* clear global device reset status bit */
2043         wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2044
2045         /* Clear any pending interrupt events. */
2046         wr32(E1000_IMC, 0xffffffff);
2047         icr = rd32(E1000_ICR);
2048
2049         ret_val = igb_reset_mdicnfg_82580(hw);
2050         if (ret_val)
2051                 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2052
2053         /* Install any alternate MAC address into RAR0 */
2054         ret_val = igb_check_alt_mac_addr(hw);
2055
2056         /* Release semaphore */
2057         if (global_device_reset)
2058                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2059
2060         return ret_val;
2061 }
2062
2063 /**
2064  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2065  *  @data: data received by reading RXPBS register
2066  *
2067  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2068  *  This function converts the retrieved value into the correct table value
2069  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2070  *  0x0 36  72 144   1   2   4   8  16
2071  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2072  */
2073 u16 igb_rxpbs_adjust_82580(u32 data)
2074 {
2075         u16 ret_val = 0;
2076
2077         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2078                 ret_val = e1000_82580_rxpbs_table[data];
2079
2080         return ret_val;
2081 }
2082
2083 /**
2084  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2085  *  checksum
2086  *  @hw: pointer to the HW structure
2087  *  @offset: offset in words of the checksum protected region
2088  *
2089  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2090  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2091  **/
2092 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2093                                                  u16 offset)
2094 {
2095         s32 ret_val = 0;
2096         u16 checksum = 0;
2097         u16 i, nvm_data;
2098
2099         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2100                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2101                 if (ret_val) {
2102                         hw_dbg("NVM Read Error\n");
2103                         goto out;
2104                 }
2105                 checksum += nvm_data;
2106         }
2107
2108         if (checksum != (u16) NVM_SUM) {
2109                 hw_dbg("NVM Checksum Invalid\n");
2110                 ret_val = -E1000_ERR_NVM;
2111                 goto out;
2112         }
2113
2114 out:
2115         return ret_val;
2116 }
2117
2118 /**
2119  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2120  *  checksum
2121  *  @hw: pointer to the HW structure
2122  *  @offset: offset in words of the checksum protected region
2123  *
2124  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2125  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2126  *  value to the EEPROM.
2127  **/
2128 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2129 {
2130         s32 ret_val;
2131         u16 checksum = 0;
2132         u16 i, nvm_data;
2133
2134         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2135                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2136                 if (ret_val) {
2137                         hw_dbg("NVM Read Error while updating checksum.\n");
2138                         goto out;
2139                 }
2140                 checksum += nvm_data;
2141         }
2142         checksum = (u16) NVM_SUM - checksum;
2143         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2144                                 &checksum);
2145         if (ret_val)
2146                 hw_dbg("NVM Write Error while updating checksum.\n");
2147
2148 out:
2149         return ret_val;
2150 }
2151
2152 /**
2153  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2154  *  @hw: pointer to the HW structure
2155  *
2156  *  Calculates the EEPROM section checksum by reading/adding each word of
2157  *  the EEPROM and then verifies that the sum of the EEPROM is
2158  *  equal to 0xBABA.
2159  **/
2160 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2161 {
2162         s32 ret_val = 0;
2163         u16 eeprom_regions_count = 1;
2164         u16 j, nvm_data;
2165         u16 nvm_offset;
2166
2167         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2168         if (ret_val) {
2169                 hw_dbg("NVM Read Error\n");
2170                 goto out;
2171         }
2172
2173         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2174                 /* if checksums compatibility bit is set validate checksums
2175                  * for all 4 ports.
2176                  */
2177                 eeprom_regions_count = 4;
2178         }
2179
2180         for (j = 0; j < eeprom_regions_count; j++) {
2181                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2182                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2183                                                                 nvm_offset);
2184                 if (ret_val != 0)
2185                         goto out;
2186         }
2187
2188 out:
2189         return ret_val;
2190 }
2191
2192 /**
2193  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2194  *  @hw: pointer to the HW structure
2195  *
2196  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2197  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2198  *  checksum and writes the value to the EEPROM.
2199  **/
2200 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2201 {
2202         s32 ret_val;
2203         u16 j, nvm_data;
2204         u16 nvm_offset;
2205
2206         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2207         if (ret_val) {
2208                 hw_dbg("NVM Read Error while updating checksum"
2209                         " compatibility bit.\n");
2210                 goto out;
2211         }
2212
2213         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2214                 /* set compatibility bit to validate checksums appropriately */
2215                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2216                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2217                                         &nvm_data);
2218                 if (ret_val) {
2219                         hw_dbg("NVM Write Error while updating checksum"
2220                                 " compatibility bit.\n");
2221                         goto out;
2222                 }
2223         }
2224
2225         for (j = 0; j < 4; j++) {
2226                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2227                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2228                 if (ret_val)
2229                         goto out;
2230         }
2231
2232 out:
2233         return ret_val;
2234 }
2235
2236 /**
2237  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2238  *  @hw: pointer to the HW structure
2239  *
2240  *  Calculates the EEPROM section checksum by reading/adding each word of
2241  *  the EEPROM and then verifies that the sum of the EEPROM is
2242  *  equal to 0xBABA.
2243  **/
2244 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2245 {
2246         s32 ret_val = 0;
2247         u16 j;
2248         u16 nvm_offset;
2249
2250         for (j = 0; j < 4; j++) {
2251                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2252                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2253                                                                 nvm_offset);
2254                 if (ret_val != 0)
2255                         goto out;
2256         }
2257
2258 out:
2259         return ret_val;
2260 }
2261
2262 /**
2263  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2264  *  @hw: pointer to the HW structure
2265  *
2266  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2267  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2268  *  checksum and writes the value to the EEPROM.
2269  **/
2270 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2271 {
2272         s32 ret_val = 0;
2273         u16 j;
2274         u16 nvm_offset;
2275
2276         for (j = 0; j < 4; j++) {
2277                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2278                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2279                 if (ret_val != 0)
2280                         goto out;
2281         }
2282
2283 out:
2284         return ret_val;
2285 }
2286
2287 /**
2288  *  igb_set_eee_i350 - Enable/disable EEE support
2289  *  @hw: pointer to the HW structure
2290  *
2291  *  Enable/disable EEE based on setting in dev_spec structure.
2292  *
2293  **/
2294 s32 igb_set_eee_i350(struct e1000_hw *hw)
2295 {
2296         s32 ret_val = 0;
2297         u32 ipcnfg, eeer;
2298
2299         if ((hw->mac.type < e1000_i350) ||
2300             (hw->phy.media_type != e1000_media_type_copper))
2301                 goto out;
2302         ipcnfg = rd32(E1000_IPCNFG);
2303         eeer = rd32(E1000_EEER);
2304
2305         /* enable or disable per user setting */
2306         if (!(hw->dev_spec._82575.eee_disable)) {
2307                 u32 eee_su = rd32(E1000_EEE_SU);
2308
2309                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2310                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2311                         E1000_EEER_LPI_FC);
2312
2313                 /* This bit should not be set in normal operation. */
2314                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2315                         hw_dbg("LPI Clock Stop Bit should not be set!\n");
2316
2317         } else {
2318                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2319                         E1000_IPCNFG_EEE_100M_AN);
2320                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2321                         E1000_EEER_RX_LPI_EN |
2322                         E1000_EEER_LPI_FC);
2323         }
2324         wr32(E1000_IPCNFG, ipcnfg);
2325         wr32(E1000_EEER, eeer);
2326         rd32(E1000_IPCNFG);
2327         rd32(E1000_EEER);
2328 out:
2329
2330         return ret_val;
2331 }
2332
2333 static const u8 e1000_emc_temp_data[4] = {
2334         E1000_EMC_INTERNAL_DATA,
2335         E1000_EMC_DIODE1_DATA,
2336         E1000_EMC_DIODE2_DATA,
2337         E1000_EMC_DIODE3_DATA
2338 };
2339 static const u8 e1000_emc_therm_limit[4] = {
2340         E1000_EMC_INTERNAL_THERM_LIMIT,
2341         E1000_EMC_DIODE1_THERM_LIMIT,
2342         E1000_EMC_DIODE2_THERM_LIMIT,
2343         E1000_EMC_DIODE3_THERM_LIMIT
2344 };
2345
2346 /**
2347  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2348  *  @hw: pointer to hardware structure
2349  *
2350  *  Updates the temperatures in mac.thermal_sensor_data
2351  **/
2352 s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2353 {
2354         s32 status = E1000_SUCCESS;
2355         u16 ets_offset;
2356         u16 ets_cfg;
2357         u16 ets_sensor;
2358         u8  num_sensors;
2359         u8  sensor_index;
2360         u8  sensor_location;
2361         u8  i;
2362         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2363
2364         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2365                 return E1000_NOT_IMPLEMENTED;
2366
2367         data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2368
2369         /* Return the internal sensor only if ETS is unsupported */
2370         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2371         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2372                 return status;
2373
2374         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2375         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2376             != NVM_ETS_TYPE_EMC)
2377                 return E1000_NOT_IMPLEMENTED;
2378
2379         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2380         if (num_sensors > E1000_MAX_SENSORS)
2381                 num_sensors = E1000_MAX_SENSORS;
2382
2383         for (i = 1; i < num_sensors; i++) {
2384                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2385                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2386                                 NVM_ETS_DATA_INDEX_SHIFT);
2387                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2388                                    NVM_ETS_DATA_LOC_SHIFT);
2389
2390                 if (sensor_location != 0)
2391                         hw->phy.ops.read_i2c_byte(hw,
2392                                         e1000_emc_temp_data[sensor_index],
2393                                         E1000_I2C_THERMAL_SENSOR_ADDR,
2394                                         &data->sensor[i].temp);
2395         }
2396         return status;
2397 }
2398
2399 /**
2400  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2401  *  @hw: pointer to hardware structure
2402  *
2403  *  Sets the thermal sensor thresholds according to the NVM map
2404  *  and save off the threshold and location values into mac.thermal_sensor_data
2405  **/
2406 s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2407 {
2408         s32 status = E1000_SUCCESS;
2409         u16 ets_offset;
2410         u16 ets_cfg;
2411         u16 ets_sensor;
2412         u8  low_thresh_delta;
2413         u8  num_sensors;
2414         u8  sensor_index;
2415         u8  sensor_location;
2416         u8  therm_limit;
2417         u8  i;
2418         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2419
2420         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2421                 return E1000_NOT_IMPLEMENTED;
2422
2423         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2424
2425         data->sensor[0].location = 0x1;
2426         data->sensor[0].caution_thresh =
2427                 (rd32(E1000_THHIGHTC) & 0xFF);
2428         data->sensor[0].max_op_thresh =
2429                 (rd32(E1000_THLOWTC) & 0xFF);
2430
2431         /* Return the internal sensor only if ETS is unsupported */
2432         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2433         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2434                 return status;
2435
2436         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2437         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2438             != NVM_ETS_TYPE_EMC)
2439                 return E1000_NOT_IMPLEMENTED;
2440
2441         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2442                             NVM_ETS_LTHRES_DELTA_SHIFT);
2443         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2444
2445         for (i = 1; i <= num_sensors; i++) {
2446                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2447                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2448                                 NVM_ETS_DATA_INDEX_SHIFT);
2449                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2450                                    NVM_ETS_DATA_LOC_SHIFT);
2451                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2452
2453                 hw->phy.ops.write_i2c_byte(hw,
2454                         e1000_emc_therm_limit[sensor_index],
2455                         E1000_I2C_THERMAL_SENSOR_ADDR,
2456                         therm_limit);
2457
2458                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2459                         data->sensor[i].location = sensor_location;
2460                         data->sensor[i].caution_thresh = therm_limit;
2461                         data->sensor[i].max_op_thresh = therm_limit -
2462                                                         low_thresh_delta;
2463                 }
2464         }
2465         return status;
2466 }
2467
2468 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2469         .init_hw              = igb_init_hw_82575,
2470         .check_for_link       = igb_check_for_link_82575,
2471         .rar_set              = igb_rar_set,
2472         .read_mac_addr        = igb_read_mac_addr_82575,
2473         .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
2474 #ifdef CONFIG_IGB_HWMON
2475         .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2476         .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2477 #endif
2478 };
2479
2480 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2481         .acquire              = igb_acquire_phy_82575,
2482         .get_cfg_done         = igb_get_cfg_done_82575,
2483         .release              = igb_release_phy_82575,
2484         .write_i2c_byte       = igb_write_i2c_byte,
2485         .read_i2c_byte        = igb_read_i2c_byte,
2486 };
2487
2488 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2489         .acquire              = igb_acquire_nvm_82575,
2490         .read                 = igb_read_nvm_eerd,
2491         .release              = igb_release_nvm_82575,
2492         .write                = igb_write_nvm_spi,
2493 };
2494
2495 const struct e1000_info e1000_82575_info = {
2496         .get_invariants = igb_get_invariants_82575,
2497         .mac_ops = &e1000_mac_ops_82575,
2498         .phy_ops = &e1000_phy_ops_82575,
2499         .nvm_ops = &e1000_nvm_ops_82575,
2500 };
2501