1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
42 static s32 igb_get_invariants_82575(struct e1000_hw *);
43 static s32 igb_acquire_phy_82575(struct e1000_hw *);
44 static void igb_release_phy_82575(struct e1000_hw *);
45 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46 static void igb_release_nvm_82575(struct e1000_hw *);
47 static s32 igb_check_for_link_82575(struct e1000_hw *);
48 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49 static s32 igb_init_hw_82575(struct e1000_hw *);
50 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
52 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
54 static s32 igb_reset_hw_82575(struct e1000_hw *);
55 static s32 igb_reset_hw_82580(struct e1000_hw *);
56 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
57 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
59 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
60 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
61 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
64 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
66 static s32 igb_get_phy_id_82575(struct e1000_hw *);
67 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68 static bool igb_sgmii_active_82575(struct e1000_hw *);
69 static s32 igb_reset_init_script_82575(struct e1000_hw *);
70 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
71 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
72 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
73 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
75 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
77 static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
93 bool ext_mdio = false;
95 switch (hw->mac.type) {
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
106 reg = rd32(E1000_MDICNFG);
107 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
116 * igb_init_phy_params_82575 - Init PHY func ptrs.
117 * @hw: pointer to the HW structure
119 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
121 struct e1000_phy_info *phy = &hw->phy;
125 if (hw->phy.media_type != e1000_media_type_copper) {
126 phy->type = e1000_phy_none;
130 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
131 phy->reset_delay_us = 100;
133 ctrl_ext = rd32(E1000_CTRL_EXT);
135 if (igb_sgmii_active_82575(hw)) {
136 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
137 ctrl_ext |= E1000_CTRL_I2C_ENA;
139 phy->ops.reset = igb_phy_hw_reset;
140 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
143 wr32(E1000_CTRL_EXT, ctrl_ext);
144 igb_reset_mdicnfg_82580(hw);
146 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
147 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
148 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
150 switch (hw->mac.type) {
154 phy->ops.read_reg = igb_read_phy_reg_82580;
155 phy->ops.write_reg = igb_write_phy_reg_82580;
159 phy->ops.read_reg = igb_read_phy_reg_gs40g;
160 phy->ops.write_reg = igb_write_phy_reg_gs40g;
163 phy->ops.read_reg = igb_read_phy_reg_igp;
164 phy->ops.write_reg = igb_write_phy_reg_igp;
169 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
170 E1000_STATUS_FUNC_SHIFT;
172 /* Set phy->phy_addr and phy->id. */
173 ret_val = igb_get_phy_id_82575(hw);
177 /* Verify phy id and set remaining function pointers */
179 case M88E1543_E_PHY_ID:
180 case I347AT4_E_PHY_ID:
181 case M88E1112_E_PHY_ID:
182 case M88E1111_I_PHY_ID:
183 phy->type = e1000_phy_m88;
184 phy->ops.check_polarity = igb_check_polarity_m88;
185 phy->ops.get_phy_info = igb_get_phy_info_m88;
186 if (phy->id != M88E1111_I_PHY_ID)
187 phy->ops.get_cable_length =
188 igb_get_cable_length_m88_gen2;
190 phy->ops.get_cable_length = igb_get_cable_length_m88;
191 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
193 case IGP03E1000_E_PHY_ID:
194 phy->type = e1000_phy_igp_3;
195 phy->ops.get_phy_info = igb_get_phy_info_igp;
196 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
197 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
198 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
199 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
201 case I82580_I_PHY_ID:
203 phy->type = e1000_phy_82580;
204 phy->ops.force_speed_duplex =
205 igb_phy_force_speed_duplex_82580;
206 phy->ops.get_cable_length = igb_get_cable_length_82580;
207 phy->ops.get_phy_info = igb_get_phy_info_82580;
208 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
209 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
212 phy->type = e1000_phy_i210;
213 phy->ops.check_polarity = igb_check_polarity_m88;
214 phy->ops.get_phy_info = igb_get_phy_info_m88;
215 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
216 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
217 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
218 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
221 ret_val = -E1000_ERR_PHY;
230 * igb_init_nvm_params_82575 - Init NVM func ptrs.
231 * @hw: pointer to the HW structure
233 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
235 struct e1000_nvm_info *nvm = &hw->nvm;
236 u32 eecd = rd32(E1000_EECD);
239 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
240 E1000_EECD_SIZE_EX_SHIFT);
242 /* Added to a constant, "size" becomes the left-shift value
243 * for setting word_size.
245 size += NVM_WORD_SIZE_BASE_SHIFT;
247 /* Just in case size is out of range, cap it to the largest
248 * EEPROM size supported
253 nvm->word_size = 1 << size;
254 nvm->opcode_bits = 8;
257 switch (nvm->override) {
258 case e1000_nvm_override_spi_large:
260 nvm->address_bits = 16;
262 case e1000_nvm_override_spi_small:
264 nvm->address_bits = 8;
267 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
268 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
272 if (nvm->word_size == (1 << 15))
273 nvm->page_size = 128;
275 nvm->type = e1000_nvm_eeprom_spi;
277 /* NVM Function Pointers */
278 nvm->ops.acquire = igb_acquire_nvm_82575;
279 nvm->ops.release = igb_release_nvm_82575;
280 nvm->ops.write = igb_write_nvm_spi;
281 nvm->ops.validate = igb_validate_nvm_checksum;
282 nvm->ops.update = igb_update_nvm_checksum;
283 if (nvm->word_size < (1 << 15))
284 nvm->ops.read = igb_read_nvm_eerd;
286 nvm->ops.read = igb_read_nvm_spi;
288 /* override generic family function pointers for specific descendants */
289 switch (hw->mac.type) {
291 nvm->ops.validate = igb_validate_nvm_checksum_82580;
292 nvm->ops.update = igb_update_nvm_checksum_82580;
296 nvm->ops.validate = igb_validate_nvm_checksum_i350;
297 nvm->ops.update = igb_update_nvm_checksum_i350;
307 * igb_init_mac_params_82575 - Init MAC func ptrs.
308 * @hw: pointer to the HW structure
310 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
312 struct e1000_mac_info *mac = &hw->mac;
313 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
315 /* Set mta register count */
316 mac->mta_reg_count = 128;
317 /* Set rar entry count */
320 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
323 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
327 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
330 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
334 if (mac->type >= e1000_82580)
335 mac->ops.reset_hw = igb_reset_hw_82580;
337 mac->ops.reset_hw = igb_reset_hw_82575;
339 if (mac->type >= e1000_i210) {
340 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
341 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
344 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
345 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
348 /* Set if part includes ASF firmware */
349 mac->asf_firmware_present = true;
350 /* Set if manageability features are enabled. */
351 mac->arc_subsystem_valid =
352 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
354 /* enable EEE on i350 parts and later parts */
355 if (mac->type >= e1000_i350)
356 dev_spec->eee_disable = false;
358 dev_spec->eee_disable = true;
359 /* Allow a single clear of the SW semaphore on I210 and newer */
360 if (mac->type >= e1000_i210)
361 dev_spec->clear_semaphore_once = true;
362 /* physical interface link setup */
363 mac->ops.setup_physical_interface =
364 (hw->phy.media_type == e1000_media_type_copper)
365 ? igb_setup_copper_link_82575
366 : igb_setup_serdes_link_82575;
372 * igb_set_sfp_media_type_82575 - derives SFP module media type.
373 * @hw: pointer to the HW structure
375 * The media type is chosen based on SFP module.
376 * compatibility flags retrieved from SFP ID EEPROM.
378 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
380 s32 ret_val = E1000_ERR_CONFIG;
382 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
383 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
384 u8 tranceiver_type = 0;
387 /* Turn I2C interface ON and power on sfp cage */
388 ctrl_ext = rd32(E1000_CTRL_EXT);
389 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
390 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
394 /* Read SFP module data */
396 ret_val = igb_read_sfp_data_byte(hw,
397 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
407 ret_val = igb_read_sfp_data_byte(hw,
408 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
413 /* Check if there is some SFP module plugged and powered */
414 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
415 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
416 dev_spec->module_plugged = true;
417 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
418 hw->phy.media_type = e1000_media_type_internal_serdes;
419 } else if (eth_flags->e100_base_fx) {
420 dev_spec->sgmii_active = true;
421 hw->phy.media_type = e1000_media_type_internal_serdes;
422 } else if (eth_flags->e1000_base_t) {
423 dev_spec->sgmii_active = true;
424 hw->phy.media_type = e1000_media_type_copper;
426 hw->phy.media_type = e1000_media_type_unknown;
427 hw_dbg("PHY module has not been recognized\n");
431 hw->phy.media_type = e1000_media_type_unknown;
435 /* Restore I2C interface setting */
436 wr32(E1000_CTRL_EXT, ctrl_ext);
440 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
442 struct e1000_mac_info *mac = &hw->mac;
443 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
448 switch (hw->device_id) {
449 case E1000_DEV_ID_82575EB_COPPER:
450 case E1000_DEV_ID_82575EB_FIBER_SERDES:
451 case E1000_DEV_ID_82575GB_QUAD_COPPER:
452 mac->type = e1000_82575;
454 case E1000_DEV_ID_82576:
455 case E1000_DEV_ID_82576_NS:
456 case E1000_DEV_ID_82576_NS_SERDES:
457 case E1000_DEV_ID_82576_FIBER:
458 case E1000_DEV_ID_82576_SERDES:
459 case E1000_DEV_ID_82576_QUAD_COPPER:
460 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
461 case E1000_DEV_ID_82576_SERDES_QUAD:
462 mac->type = e1000_82576;
464 case E1000_DEV_ID_82580_COPPER:
465 case E1000_DEV_ID_82580_FIBER:
466 case E1000_DEV_ID_82580_QUAD_FIBER:
467 case E1000_DEV_ID_82580_SERDES:
468 case E1000_DEV_ID_82580_SGMII:
469 case E1000_DEV_ID_82580_COPPER_DUAL:
470 case E1000_DEV_ID_DH89XXCC_SGMII:
471 case E1000_DEV_ID_DH89XXCC_SERDES:
472 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
473 case E1000_DEV_ID_DH89XXCC_SFP:
474 mac->type = e1000_82580;
476 case E1000_DEV_ID_I350_COPPER:
477 case E1000_DEV_ID_I350_FIBER:
478 case E1000_DEV_ID_I350_SERDES:
479 case E1000_DEV_ID_I350_SGMII:
480 mac->type = e1000_i350;
482 case E1000_DEV_ID_I210_COPPER:
483 case E1000_DEV_ID_I210_FIBER:
484 case E1000_DEV_ID_I210_SERDES:
485 case E1000_DEV_ID_I210_SGMII:
486 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
487 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
488 mac->type = e1000_i210;
490 case E1000_DEV_ID_I211_COPPER:
491 mac->type = e1000_i211;
493 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
494 case E1000_DEV_ID_I354_SGMII:
495 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
496 mac->type = e1000_i354;
499 return -E1000_ERR_MAC_INIT;
504 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
505 * based on the EEPROM. We cannot rely upon device ID. There
506 * is no distinguishable difference between fiber and internal
507 * SerDes mode on the 82575. There can be an external PHY attached
508 * on the SGMII interface. For this, we'll set sgmii_active to true.
510 hw->phy.media_type = e1000_media_type_copper;
511 dev_spec->sgmii_active = false;
512 dev_spec->module_plugged = false;
514 ctrl_ext = rd32(E1000_CTRL_EXT);
516 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
518 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
519 hw->phy.media_type = e1000_media_type_internal_serdes;
521 case E1000_CTRL_EXT_LINK_MODE_SGMII:
522 /* Get phy control interface type set (MDIO vs. I2C)*/
523 if (igb_sgmii_uses_mdio_82575(hw)) {
524 hw->phy.media_type = e1000_media_type_copper;
525 dev_spec->sgmii_active = true;
528 /* fall through for I2C based SGMII */
529 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
530 /* read media type from SFP EEPROM */
531 ret_val = igb_set_sfp_media_type_82575(hw);
532 if ((ret_val != 0) ||
533 (hw->phy.media_type == e1000_media_type_unknown)) {
534 /* If media type was not identified then return media
535 * type defined by the CTRL_EXT settings.
537 hw->phy.media_type = e1000_media_type_internal_serdes;
539 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
540 hw->phy.media_type = e1000_media_type_copper;
541 dev_spec->sgmii_active = true;
547 /* do not change link mode for 100BaseFX */
548 if (dev_spec->eth_flags.e100_base_fx)
551 /* change current link mode setting */
552 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
554 if (hw->phy.media_type == e1000_media_type_copper)
555 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
557 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
559 wr32(E1000_CTRL_EXT, ctrl_ext);
566 /* mac initialization and operations */
567 ret_val = igb_init_mac_params_82575(hw);
571 /* NVM initialization */
572 ret_val = igb_init_nvm_params_82575(hw);
573 switch (hw->mac.type) {
576 ret_val = igb_init_nvm_params_i210(hw);
585 /* if part supports SR-IOV then initialize mailbox parameters */
589 igb_init_mbx_params_pf(hw);
595 /* setup PHY parameters */
596 ret_val = igb_init_phy_params_82575(hw);
603 * igb_acquire_phy_82575 - Acquire rights to access PHY
604 * @hw: pointer to the HW structure
606 * Acquire access rights to the correct PHY. This is a
607 * function pointer entry point called by the api module.
609 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
611 u16 mask = E1000_SWFW_PHY0_SM;
613 if (hw->bus.func == E1000_FUNC_1)
614 mask = E1000_SWFW_PHY1_SM;
615 else if (hw->bus.func == E1000_FUNC_2)
616 mask = E1000_SWFW_PHY2_SM;
617 else if (hw->bus.func == E1000_FUNC_3)
618 mask = E1000_SWFW_PHY3_SM;
620 return hw->mac.ops.acquire_swfw_sync(hw, mask);
624 * igb_release_phy_82575 - Release rights to access PHY
625 * @hw: pointer to the HW structure
627 * A wrapper to release access rights to the correct PHY. This is a
628 * function pointer entry point called by the api module.
630 static void igb_release_phy_82575(struct e1000_hw *hw)
632 u16 mask = E1000_SWFW_PHY0_SM;
634 if (hw->bus.func == E1000_FUNC_1)
635 mask = E1000_SWFW_PHY1_SM;
636 else if (hw->bus.func == E1000_FUNC_2)
637 mask = E1000_SWFW_PHY2_SM;
638 else if (hw->bus.func == E1000_FUNC_3)
639 mask = E1000_SWFW_PHY3_SM;
641 hw->mac.ops.release_swfw_sync(hw, mask);
645 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
646 * @hw: pointer to the HW structure
647 * @offset: register offset to be read
648 * @data: pointer to the read data
650 * Reads the PHY register at offset using the serial gigabit media independent
651 * interface and stores the retrieved information in data.
653 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
656 s32 ret_val = -E1000_ERR_PARAM;
658 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
659 hw_dbg("PHY Address %u is out of range\n", offset);
663 ret_val = hw->phy.ops.acquire(hw);
667 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
669 hw->phy.ops.release(hw);
676 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
677 * @hw: pointer to the HW structure
678 * @offset: register offset to write to
679 * @data: data to write at register offset
681 * Writes the data to PHY register at the offset using the serial gigabit
682 * media independent interface.
684 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
687 s32 ret_val = -E1000_ERR_PARAM;
690 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
691 hw_dbg("PHY Address %d is out of range\n", offset);
695 ret_val = hw->phy.ops.acquire(hw);
699 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
701 hw->phy.ops.release(hw);
708 * igb_get_phy_id_82575 - Retrieve PHY addr and id
709 * @hw: pointer to the HW structure
711 * Retrieves the PHY address and ID for both PHY's which do and do not use
714 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
716 struct e1000_phy_info *phy = &hw->phy;
722 /* For SGMII PHYs, we try the list of possible addresses until
723 * we find one that works. For non-SGMII PHYs
724 * (e.g. integrated copper PHYs), an address of 1 should
725 * work. The result of this function should mean phy->phy_addr
726 * and phy->id are set correctly.
728 if (!(igb_sgmii_active_82575(hw))) {
730 ret_val = igb_get_phy_id(hw);
734 if (igb_sgmii_uses_mdio_82575(hw)) {
735 switch (hw->mac.type) {
738 mdic = rd32(E1000_MDIC);
739 mdic &= E1000_MDIC_PHY_MASK;
740 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
747 mdic = rd32(E1000_MDICNFG);
748 mdic &= E1000_MDICNFG_PHY_MASK;
749 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
752 ret_val = -E1000_ERR_PHY;
756 ret_val = igb_get_phy_id(hw);
760 /* Power on sgmii phy if it is disabled */
761 ctrl_ext = rd32(E1000_CTRL_EXT);
762 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
766 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
767 * Therefore, we need to test 1-7
769 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
770 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
772 hw_dbg("Vendor ID 0x%08X read at address %u\n",
774 /* At the time of this writing, The M88 part is
775 * the only supported SGMII PHY product.
777 if (phy_id == M88_VENDOR)
780 hw_dbg("PHY address %u was unreadable\n", phy->addr);
784 /* A valid PHY type couldn't be found. */
785 if (phy->addr == 8) {
787 ret_val = -E1000_ERR_PHY;
790 ret_val = igb_get_phy_id(hw);
793 /* restore previous sfp cage power state */
794 wr32(E1000_CTRL_EXT, ctrl_ext);
801 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
802 * @hw: pointer to the HW structure
804 * Resets the PHY using the serial gigabit media independent interface.
806 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
810 /* This isn't a true "hard" reset, but is the only reset
811 * available to us at this time.
814 hw_dbg("Soft resetting SGMII attached PHY...\n");
816 /* SFP documentation requires the following to configure the SPF module
817 * to work on SGMII. No further documentation is given.
819 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
823 ret_val = igb_phy_sw_reset(hw);
830 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
831 * @hw: pointer to the HW structure
832 * @active: true to enable LPLU, false to disable
834 * Sets the LPLU D0 state according to the active flag. When
835 * activating LPLU this function also disables smart speed
836 * and vice versa. LPLU will not be activated unless the
837 * device autonegotiation advertisement meets standards of
838 * either 10 or 10/100 or 10/100/1000 at all duplexes.
839 * This is a function pointer entry point only called by
840 * PHY setup routines.
842 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
844 struct e1000_phy_info *phy = &hw->phy;
848 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
853 data |= IGP02E1000_PM_D0_LPLU;
854 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
859 /* When LPLU is enabled, we should disable SmartSpeed */
860 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
862 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
863 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
868 data &= ~IGP02E1000_PM_D0_LPLU;
869 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
871 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
872 * during Dx states where the power conservation is most
873 * important. During driver activity we should enable
874 * SmartSpeed, so performance is maintained.
876 if (phy->smart_speed == e1000_smart_speed_on) {
877 ret_val = phy->ops.read_reg(hw,
878 IGP01E1000_PHY_PORT_CONFIG, &data);
882 data |= IGP01E1000_PSCFR_SMART_SPEED;
883 ret_val = phy->ops.write_reg(hw,
884 IGP01E1000_PHY_PORT_CONFIG, data);
887 } else if (phy->smart_speed == e1000_smart_speed_off) {
888 ret_val = phy->ops.read_reg(hw,
889 IGP01E1000_PHY_PORT_CONFIG, &data);
893 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
894 ret_val = phy->ops.write_reg(hw,
895 IGP01E1000_PHY_PORT_CONFIG, data);
906 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
907 * @hw: pointer to the HW structure
908 * @active: true to enable LPLU, false to disable
910 * Sets the LPLU D0 state according to the active flag. When
911 * activating LPLU this function also disables smart speed
912 * and vice versa. LPLU will not be activated unless the
913 * device autonegotiation advertisement meets standards of
914 * either 10 or 10/100 or 10/100/1000 at all duplexes.
915 * This is a function pointer entry point only called by
916 * PHY setup routines.
918 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
920 struct e1000_phy_info *phy = &hw->phy;
924 data = rd32(E1000_82580_PHY_POWER_MGMT);
927 data |= E1000_82580_PM_D0_LPLU;
929 /* When LPLU is enabled, we should disable SmartSpeed */
930 data &= ~E1000_82580_PM_SPD;
932 data &= ~E1000_82580_PM_D0_LPLU;
934 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
935 * during Dx states where the power conservation is most
936 * important. During driver activity we should enable
937 * SmartSpeed, so performance is maintained.
939 if (phy->smart_speed == e1000_smart_speed_on)
940 data |= E1000_82580_PM_SPD;
941 else if (phy->smart_speed == e1000_smart_speed_off)
942 data &= ~E1000_82580_PM_SPD; }
944 wr32(E1000_82580_PHY_POWER_MGMT, data);
949 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
950 * @hw: pointer to the HW structure
951 * @active: boolean used to enable/disable lplu
953 * Success returns 0, Failure returns 1
955 * The low power link up (lplu) state is set to the power management level D3
956 * and SmartSpeed is disabled when active is true, else clear lplu for D3
957 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
958 * is used during Dx states where the power conservation is most important.
959 * During driver activity, SmartSpeed should be enabled so performance is
962 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
964 struct e1000_phy_info *phy = &hw->phy;
968 data = rd32(E1000_82580_PHY_POWER_MGMT);
971 data &= ~E1000_82580_PM_D3_LPLU;
972 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
973 * during Dx states where the power conservation is most
974 * important. During driver activity we should enable
975 * SmartSpeed, so performance is maintained.
977 if (phy->smart_speed == e1000_smart_speed_on)
978 data |= E1000_82580_PM_SPD;
979 else if (phy->smart_speed == e1000_smart_speed_off)
980 data &= ~E1000_82580_PM_SPD;
981 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
982 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
983 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
984 data |= E1000_82580_PM_D3_LPLU;
985 /* When LPLU is enabled, we should disable SmartSpeed */
986 data &= ~E1000_82580_PM_SPD;
989 wr32(E1000_82580_PHY_POWER_MGMT, data);
994 * igb_acquire_nvm_82575 - Request for access to EEPROM
995 * @hw: pointer to the HW structure
997 * Acquire the necessary semaphores for exclusive access to the EEPROM.
998 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
999 * Return successful if access grant bit set, else clear the request for
1000 * EEPROM access and return -E1000_ERR_NVM (-1).
1002 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1006 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1010 ret_val = igb_acquire_nvm(hw);
1013 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1020 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1021 * @hw: pointer to the HW structure
1023 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1024 * then release the semaphores acquired.
1026 static void igb_release_nvm_82575(struct e1000_hw *hw)
1028 igb_release_nvm(hw);
1029 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1033 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1034 * @hw: pointer to the HW structure
1035 * @mask: specifies which semaphore to acquire
1037 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1038 * will also specify which port we're acquiring the lock for.
1040 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1044 u32 fwmask = mask << 16;
1046 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1048 while (i < timeout) {
1049 if (igb_get_hw_semaphore(hw)) {
1050 ret_val = -E1000_ERR_SWFW_SYNC;
1054 swfw_sync = rd32(E1000_SW_FW_SYNC);
1055 if (!(swfw_sync & (fwmask | swmask)))
1058 /* Firmware currently using resource (fwmask)
1059 * or other software thread using resource (swmask)
1061 igb_put_hw_semaphore(hw);
1067 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1068 ret_val = -E1000_ERR_SWFW_SYNC;
1072 swfw_sync |= swmask;
1073 wr32(E1000_SW_FW_SYNC, swfw_sync);
1075 igb_put_hw_semaphore(hw);
1082 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1083 * @hw: pointer to the HW structure
1084 * @mask: specifies which semaphore to acquire
1086 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1087 * will also specify which port we're releasing the lock for.
1089 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1093 while (igb_get_hw_semaphore(hw) != 0);
1096 swfw_sync = rd32(E1000_SW_FW_SYNC);
1098 wr32(E1000_SW_FW_SYNC, swfw_sync);
1100 igb_put_hw_semaphore(hw);
1104 * igb_get_cfg_done_82575 - Read config done bit
1105 * @hw: pointer to the HW structure
1107 * Read the management control register for the config done bit for
1108 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1109 * to read the config done bit, so an error is *ONLY* logged and returns
1110 * 0. If we were to return with error, EEPROM-less silicon
1111 * would not be able to be reset or change link.
1113 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1115 s32 timeout = PHY_CFG_TIMEOUT;
1117 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1119 if (hw->bus.func == 1)
1120 mask = E1000_NVM_CFG_DONE_PORT_1;
1121 else if (hw->bus.func == E1000_FUNC_2)
1122 mask = E1000_NVM_CFG_DONE_PORT_2;
1123 else if (hw->bus.func == E1000_FUNC_3)
1124 mask = E1000_NVM_CFG_DONE_PORT_3;
1127 if (rd32(E1000_EEMNGCTL) & mask)
1133 hw_dbg("MNG configuration cycle has not completed.\n");
1135 /* If EEPROM is not marked present, init the PHY manually */
1136 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1137 (hw->phy.type == e1000_phy_igp_3))
1138 igb_phy_init_script_igp3(hw);
1144 * igb_get_link_up_info_82575 - Get link speed/duplex info
1145 * @hw: pointer to the HW structure
1146 * @speed: stores the current speed
1147 * @duplex: stores the current duplex
1149 * This is a wrapper function, if using the serial gigabit media independent
1150 * interface, use PCS to retrieve the link speed and duplex information.
1151 * Otherwise, use the generic function to get the link speed and duplex info.
1153 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1158 if (hw->phy.media_type != e1000_media_type_copper)
1159 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1162 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1169 * igb_check_for_link_82575 - Check for link
1170 * @hw: pointer to the HW structure
1172 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1173 * use the generic interface for determining link.
1175 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1180 if (hw->phy.media_type != e1000_media_type_copper) {
1181 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1183 /* Use this flag to determine if link needs to be checked or
1184 * not. If we have link clear the flag so that we do not
1185 * continue to check for link.
1187 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1189 /* Configure Flow Control now that Auto-Neg has completed.
1190 * First, we need to restore the desired flow control
1191 * settings because we may have had to re-autoneg with a
1192 * different link partner.
1194 ret_val = igb_config_fc_after_link_up(hw);
1196 hw_dbg("Error configuring flow control\n");
1198 ret_val = igb_check_for_copper_link(hw);
1205 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1206 * @hw: pointer to the HW structure
1208 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1213 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1214 !igb_sgmii_active_82575(hw))
1217 /* Enable PCS to turn on link */
1218 reg = rd32(E1000_PCS_CFG0);
1219 reg |= E1000_PCS_CFG_PCS_EN;
1220 wr32(E1000_PCS_CFG0, reg);
1222 /* Power up the laser */
1223 reg = rd32(E1000_CTRL_EXT);
1224 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1225 wr32(E1000_CTRL_EXT, reg);
1227 /* flush the write to verify completion */
1233 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1234 * @hw: pointer to the HW structure
1235 * @speed: stores the current speed
1236 * @duplex: stores the current duplex
1238 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1239 * duplex, then store the values in the pointers provided.
1241 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1244 struct e1000_mac_info *mac = &hw->mac;
1247 /* Set up defaults for the return values of this function */
1248 mac->serdes_has_link = false;
1252 /* Read the PCS Status register for link state. For non-copper mode,
1253 * the status register is not accurate. The PCS status register is
1256 pcs = rd32(E1000_PCS_LSTAT);
1258 /* The link up bit determines when link is up on autoneg. The sync ok
1259 * gets set once both sides sync up and agree upon link. Stable link
1260 * can be determined by checking for both link up and link sync ok
1262 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1263 mac->serdes_has_link = true;
1265 /* Detect and store PCS speed */
1266 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1267 *speed = SPEED_1000;
1268 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1273 /* Detect and store PCS duplex */
1274 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1275 *duplex = FULL_DUPLEX;
1277 *duplex = HALF_DUPLEX;
1279 /* Check if it is an I354 2.5Gb backplane connection. */
1280 if (mac->type == e1000_i354) {
1281 status = rd32(E1000_STATUS);
1282 if ((status & E1000_STATUS_2P5_SKU) &&
1283 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1284 *speed = SPEED_2500;
1285 *duplex = FULL_DUPLEX;
1286 hw_dbg("2500 Mbs, ");
1287 hw_dbg("Full Duplex\n");
1297 * igb_shutdown_serdes_link_82575 - Remove link during power down
1298 * @hw: pointer to the HW structure
1300 * In the case of fiber serdes, shut down optics and PCS on driver unload
1301 * when management pass thru is not enabled.
1303 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1307 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1308 igb_sgmii_active_82575(hw))
1311 if (!igb_enable_mng_pass_thru(hw)) {
1312 /* Disable PCS to turn off link */
1313 reg = rd32(E1000_PCS_CFG0);
1314 reg &= ~E1000_PCS_CFG_PCS_EN;
1315 wr32(E1000_PCS_CFG0, reg);
1317 /* shutdown the laser */
1318 reg = rd32(E1000_CTRL_EXT);
1319 reg |= E1000_CTRL_EXT_SDP3_DATA;
1320 wr32(E1000_CTRL_EXT, reg);
1322 /* flush the write to verify completion */
1329 * igb_reset_hw_82575 - Reset hardware
1330 * @hw: pointer to the HW structure
1332 * This resets the hardware into a known state. This is a
1333 * function pointer entry point called by the api module.
1335 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1340 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1341 * on the last TLP read/write transaction when MAC is reset.
1343 ret_val = igb_disable_pcie_master(hw);
1345 hw_dbg("PCI-E Master disable polling has failed.\n");
1347 /* set the completion timeout for interface */
1348 ret_val = igb_set_pcie_completion_timeout(hw);
1350 hw_dbg("PCI-E Set completion timeout has failed.\n");
1353 hw_dbg("Masking off all interrupts\n");
1354 wr32(E1000_IMC, 0xffffffff);
1356 wr32(E1000_RCTL, 0);
1357 wr32(E1000_TCTL, E1000_TCTL_PSP);
1362 ctrl = rd32(E1000_CTRL);
1364 hw_dbg("Issuing a global reset to MAC\n");
1365 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1367 ret_val = igb_get_auto_rd_done(hw);
1369 /* When auto config read does not complete, do not
1370 * return with an error. This can happen in situations
1371 * where there is no eeprom and prevents getting link.
1373 hw_dbg("Auto Read Done did not complete\n");
1376 /* If EEPROM is not present, run manual init scripts */
1377 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1378 igb_reset_init_script_82575(hw);
1380 /* Clear any pending interrupt events. */
1381 wr32(E1000_IMC, 0xffffffff);
1384 /* Install any alternate MAC address into RAR0 */
1385 ret_val = igb_check_alt_mac_addr(hw);
1391 * igb_init_hw_82575 - Initialize hardware
1392 * @hw: pointer to the HW structure
1394 * This inits the hardware readying it for operation.
1396 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1398 struct e1000_mac_info *mac = &hw->mac;
1400 u16 i, rar_count = mac->rar_entry_count;
1402 /* Initialize identification LED */
1403 ret_val = igb_id_led_init(hw);
1405 hw_dbg("Error initializing identification LED\n");
1406 /* This is not fatal and we should not stop init due to this */
1409 /* Disabling VLAN filtering */
1410 hw_dbg("Initializing the IEEE VLAN\n");
1411 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1412 igb_clear_vfta_i350(hw);
1416 /* Setup the receive address */
1417 igb_init_rx_addrs(hw, rar_count);
1419 /* Zero out the Multicast HASH table */
1420 hw_dbg("Zeroing the MTA\n");
1421 for (i = 0; i < mac->mta_reg_count; i++)
1422 array_wr32(E1000_MTA, i, 0);
1424 /* Zero out the Unicast HASH table */
1425 hw_dbg("Zeroing the UTA\n");
1426 for (i = 0; i < mac->uta_reg_count; i++)
1427 array_wr32(E1000_UTA, i, 0);
1429 /* Setup link and flow control */
1430 ret_val = igb_setup_link(hw);
1432 /* Clear all of the statistics registers (clear on read). It is
1433 * important that we do this after we have tried to establish link
1434 * because the symbol error count will increment wildly if there
1437 igb_clear_hw_cntrs_82575(hw);
1442 * igb_setup_copper_link_82575 - Configure copper link settings
1443 * @hw: pointer to the HW structure
1445 * Configures the link for auto-neg or forced speed and duplex. Then we check
1446 * for link, once link is established calls to configure collision distance
1447 * and flow control are called.
1449 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1455 ctrl = rd32(E1000_CTRL);
1456 ctrl |= E1000_CTRL_SLU;
1457 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1458 wr32(E1000_CTRL, ctrl);
1460 /* Clear Go Link Disconnect bit on supported devices */
1461 switch (hw->mac.type) {
1466 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1467 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1468 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1474 ret_val = igb_setup_serdes_link_82575(hw);
1478 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1479 /* allow time for SFP cage time to power up phy */
1482 ret_val = hw->phy.ops.reset(hw);
1484 hw_dbg("Error resetting the PHY.\n");
1488 switch (hw->phy.type) {
1489 case e1000_phy_i210:
1491 switch (hw->phy.id) {
1492 case I347AT4_E_PHY_ID:
1493 case M88E1112_E_PHY_ID:
1494 case M88E1543_E_PHY_ID:
1496 ret_val = igb_copper_link_setup_m88_gen2(hw);
1499 ret_val = igb_copper_link_setup_m88(hw);
1503 case e1000_phy_igp_3:
1504 ret_val = igb_copper_link_setup_igp(hw);
1506 case e1000_phy_82580:
1507 ret_val = igb_copper_link_setup_82580(hw);
1510 ret_val = -E1000_ERR_PHY;
1517 ret_val = igb_setup_copper_link(hw);
1523 * igb_setup_serdes_link_82575 - Setup link for serdes
1524 * @hw: pointer to the HW structure
1526 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1527 * used on copper connections where the serialized gigabit media independent
1528 * interface (sgmii), or serdes fiber is being used. Configures the link
1529 * for auto-negotiation or forces speed/duplex.
1531 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1533 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1535 s32 ret_val = E1000_SUCCESS;
1538 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1539 !igb_sgmii_active_82575(hw))
1543 /* On the 82575, SerDes loopback mode persists until it is
1544 * explicitly turned off or a power cycle is performed. A read to
1545 * the register does not indicate its status. Therefore, we ensure
1546 * loopback mode is disabled during initialization.
1548 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1550 /* power on the sfp cage if present and turn on I2C */
1551 ctrl_ext = rd32(E1000_CTRL_EXT);
1552 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1553 ctrl_ext |= E1000_CTRL_I2C_ENA;
1554 wr32(E1000_CTRL_EXT, ctrl_ext);
1556 ctrl_reg = rd32(E1000_CTRL);
1557 ctrl_reg |= E1000_CTRL_SLU;
1559 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1560 /* set both sw defined pins */
1561 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1563 /* Set switch control to serdes energy detect */
1564 reg = rd32(E1000_CONNSW);
1565 reg |= E1000_CONNSW_ENRGSRC;
1566 wr32(E1000_CONNSW, reg);
1569 reg = rd32(E1000_PCS_LCTL);
1571 /* default pcs_autoneg to the same setting as mac autoneg */
1572 pcs_autoneg = hw->mac.autoneg;
1574 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1575 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1576 /* sgmii mode lets the phy handle forcing speed/duplex */
1578 /* autoneg time out should be disabled for SGMII mode */
1579 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1581 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1582 /* disable PCS autoneg and support parallel detect only */
1583 pcs_autoneg = false;
1585 if (hw->mac.type == e1000_82575 ||
1586 hw->mac.type == e1000_82576) {
1587 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1589 printk(KERN_DEBUG "NVM Read Error\n\n");
1593 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1594 pcs_autoneg = false;
1597 /* non-SGMII modes only supports a speed of 1000/Full for the
1598 * link so it is best to just force the MAC and let the pcs
1599 * link either autoneg or be forced to 1000/Full
1601 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1602 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1604 /* set speed of 1000/Full if speed/duplex is forced */
1605 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1609 wr32(E1000_CTRL, ctrl_reg);
1611 /* New SerDes mode allows for forcing speed or autonegotiating speed
1612 * at 1gb. Autoneg should be default set by most drivers. This is the
1613 * mode that will be compatible with older link partners and switches.
1614 * However, both are supported by the hardware and some drivers/tools.
1616 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1617 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1620 /* Set PCS register for autoneg */
1621 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1622 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1624 /* Disable force flow control for autoneg */
1625 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1627 /* Configure flow control advertisement for autoneg */
1628 anadv_reg = rd32(E1000_PCS_ANADV);
1629 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1630 switch (hw->fc.requested_mode) {
1632 case e1000_fc_rx_pause:
1633 anadv_reg |= E1000_TXCW_ASM_DIR;
1634 anadv_reg |= E1000_TXCW_PAUSE;
1636 case e1000_fc_tx_pause:
1637 anadv_reg |= E1000_TXCW_ASM_DIR;
1642 wr32(E1000_PCS_ANADV, anadv_reg);
1644 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1646 /* Set PCS register for forced link */
1647 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1649 /* Force flow control for forced link */
1650 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1652 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1655 wr32(E1000_PCS_LCTL, reg);
1657 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1658 igb_force_mac_fc(hw);
1664 * igb_sgmii_active_82575 - Return sgmii state
1665 * @hw: pointer to the HW structure
1667 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1668 * which can be enabled for use in the embedded applications. Simply
1669 * return the current state of the sgmii interface.
1671 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1673 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1674 return dev_spec->sgmii_active;
1678 * igb_reset_init_script_82575 - Inits HW defaults after reset
1679 * @hw: pointer to the HW structure
1681 * Inits recommended HW defaults after a reset when there is no EEPROM
1682 * detected. This is only for the 82575.
1684 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1686 if (hw->mac.type == e1000_82575) {
1687 hw_dbg("Running reset init script for 82575\n");
1688 /* SerDes configuration via SERDESCTRL */
1689 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1690 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1691 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1692 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1694 /* CCM configuration via CCMCTL register */
1695 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1696 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1698 /* PCIe lanes configuration */
1699 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1700 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1701 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1702 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1704 /* PCIe PLL Configuration */
1705 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1706 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1707 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1714 * igb_read_mac_addr_82575 - Read device MAC address
1715 * @hw: pointer to the HW structure
1717 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1721 /* If there's an alternate MAC address place it in RAR0
1722 * so that it will override the Si installed default perm
1725 ret_val = igb_check_alt_mac_addr(hw);
1729 ret_val = igb_read_mac_addr(hw);
1736 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1737 * @hw: pointer to the HW structure
1739 * In the case of a PHY power down to save power, or to turn off link during a
1740 * driver unload, or wake on lan is not enabled, remove the link.
1742 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1744 /* If the management interface is not enabled, then power down */
1745 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1746 igb_power_down_phy_copper(hw);
1750 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1751 * @hw: pointer to the HW structure
1753 * Clears the hardware counters by reading the counter registers.
1755 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1757 igb_clear_hw_cntrs_base(hw);
1763 rd32(E1000_PRC1023);
1764 rd32(E1000_PRC1522);
1769 rd32(E1000_PTC1023);
1770 rd32(E1000_PTC1522);
1772 rd32(E1000_ALGNERRC);
1775 rd32(E1000_CEXTERR);
1786 rd32(E1000_ICRXPTC);
1787 rd32(E1000_ICRXATC);
1788 rd32(E1000_ICTXPTC);
1789 rd32(E1000_ICTXATC);
1790 rd32(E1000_ICTXQEC);
1791 rd32(E1000_ICTXQMTC);
1792 rd32(E1000_ICRXDMTC);
1799 rd32(E1000_HTCBDPC);
1804 rd32(E1000_LENERRS);
1806 /* This register should not be read in copper configurations */
1807 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1808 igb_sgmii_active_82575(hw))
1813 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1814 * @hw: pointer to the HW structure
1816 * After rx enable if managability is enabled then there is likely some
1817 * bad data at the start of the fifo and possibly in the DMA fifo. This
1818 * function clears the fifos and flushes any packets that came in as rx was
1821 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1823 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1826 if (hw->mac.type != e1000_82575 ||
1827 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1830 /* Disable all RX queues */
1831 for (i = 0; i < 4; i++) {
1832 rxdctl[i] = rd32(E1000_RXDCTL(i));
1833 wr32(E1000_RXDCTL(i),
1834 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1836 /* Poll all queues to verify they have shut down */
1837 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1840 for (i = 0; i < 4; i++)
1841 rx_enabled |= rd32(E1000_RXDCTL(i));
1842 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1847 hw_dbg("Queue disable timed out after 10ms\n");
1849 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1850 * incoming packets are rejected. Set enable and wait 2ms so that
1851 * any packet that was coming in as RCTL.EN was set is flushed
1853 rfctl = rd32(E1000_RFCTL);
1854 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1856 rlpml = rd32(E1000_RLPML);
1857 wr32(E1000_RLPML, 0);
1859 rctl = rd32(E1000_RCTL);
1860 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1861 temp_rctl |= E1000_RCTL_LPE;
1863 wr32(E1000_RCTL, temp_rctl);
1864 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1868 /* Enable RX queues that were previously enabled and restore our
1871 for (i = 0; i < 4; i++)
1872 wr32(E1000_RXDCTL(i), rxdctl[i]);
1873 wr32(E1000_RCTL, rctl);
1876 wr32(E1000_RLPML, rlpml);
1877 wr32(E1000_RFCTL, rfctl);
1879 /* Flush receive errors generated by workaround */
1886 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1887 * @hw: pointer to the HW structure
1889 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1890 * however the hardware default for these parts is 500us to 1ms which is less
1891 * than the 10ms recommended by the pci-e spec. To address this we need to
1892 * increase the value to either 10ms to 200ms for capability version 1 config,
1893 * or 16ms to 55ms for version 2.
1895 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1897 u32 gcr = rd32(E1000_GCR);
1901 /* only take action if timeout value is defaulted to 0 */
1902 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1905 /* if capabilities version is type 1 we can write the
1906 * timeout of 10ms to 200ms through the GCR register
1908 if (!(gcr & E1000_GCR_CAP_VER2)) {
1909 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1913 /* for version 2 capabilities we need to write the config space
1914 * directly in order to set the completion timeout value for
1917 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1922 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1924 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1927 /* disable completion timeout resend */
1928 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1930 wr32(E1000_GCR, gcr);
1935 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1936 * @hw: pointer to the hardware struct
1937 * @enable: state to enter, either enabled or disabled
1938 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1940 * enables/disables L2 switch anti-spoofing functionality.
1942 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1944 u32 reg_val, reg_offset;
1946 switch (hw->mac.type) {
1948 reg_offset = E1000_DTXSWC;
1952 reg_offset = E1000_TXSWC;
1958 reg_val = rd32(reg_offset);
1960 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1961 E1000_DTXSWC_VLAN_SPOOF_MASK);
1962 /* The PF can spoof - it has to in order to
1963 * support emulation mode NICs
1965 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1967 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1968 E1000_DTXSWC_VLAN_SPOOF_MASK);
1970 wr32(reg_offset, reg_val);
1974 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1975 * @hw: pointer to the hardware struct
1976 * @enable: state to enter, either enabled or disabled
1978 * enables/disables L2 switch loopback functionality.
1980 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1984 switch (hw->mac.type) {
1986 dtxswc = rd32(E1000_DTXSWC);
1988 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1990 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1991 wr32(E1000_DTXSWC, dtxswc);
1995 dtxswc = rd32(E1000_TXSWC);
1997 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1999 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2000 wr32(E1000_TXSWC, dtxswc);
2003 /* Currently no other hardware supports loopback */
2010 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2011 * @hw: pointer to the hardware struct
2012 * @enable: state to enter, either enabled or disabled
2014 * enables/disables replication of packets across multiple pools.
2016 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2018 u32 vt_ctl = rd32(E1000_VT_CTL);
2021 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2023 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2025 wr32(E1000_VT_CTL, vt_ctl);
2029 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2030 * @hw: pointer to the HW structure
2031 * @offset: register offset to be read
2032 * @data: pointer to the read data
2034 * Reads the MDI control register in the PHY at offset and stores the
2035 * information read to data.
2037 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2041 ret_val = hw->phy.ops.acquire(hw);
2045 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2047 hw->phy.ops.release(hw);
2054 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2055 * @hw: pointer to the HW structure
2056 * @offset: register offset to write to
2057 * @data: data to write to register at offset
2059 * Writes data to MDI control register in the PHY at offset.
2061 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2066 ret_val = hw->phy.ops.acquire(hw);
2070 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2072 hw->phy.ops.release(hw);
2079 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2080 * @hw: pointer to the HW structure
2082 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2083 * the values found in the EEPROM. This addresses an issue in which these
2084 * bits are not restored from EEPROM after reset.
2086 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2092 if (hw->mac.type != e1000_82580)
2094 if (!igb_sgmii_active_82575(hw))
2097 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2098 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2101 hw_dbg("NVM Read Error\n");
2105 mdicnfg = rd32(E1000_MDICNFG);
2106 if (nvm_data & NVM_WORD24_EXT_MDIO)
2107 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2108 if (nvm_data & NVM_WORD24_COM_MDIO)
2109 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2110 wr32(E1000_MDICNFG, mdicnfg);
2116 * igb_reset_hw_82580 - Reset hardware
2117 * @hw: pointer to the HW structure
2119 * This resets function or entire device (all ports, etc.)
2122 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2125 /* BH SW mailbox bit in SW_FW_SYNC */
2126 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2128 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2130 hw->dev_spec._82575.global_device_reset = false;
2132 /* due to hw errata, global device reset doesn't always
2135 if (hw->mac.type == e1000_82580)
2136 global_device_reset = false;
2138 /* Get current control state. */
2139 ctrl = rd32(E1000_CTRL);
2141 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2142 * on the last TLP read/write transaction when MAC is reset.
2144 ret_val = igb_disable_pcie_master(hw);
2146 hw_dbg("PCI-E Master disable polling has failed.\n");
2148 hw_dbg("Masking off all interrupts\n");
2149 wr32(E1000_IMC, 0xffffffff);
2150 wr32(E1000_RCTL, 0);
2151 wr32(E1000_TCTL, E1000_TCTL_PSP);
2156 /* Determine whether or not a global dev reset is requested */
2157 if (global_device_reset &&
2158 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2159 global_device_reset = false;
2161 if (global_device_reset &&
2162 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2163 ctrl |= E1000_CTRL_DEV_RST;
2165 ctrl |= E1000_CTRL_RST;
2167 wr32(E1000_CTRL, ctrl);
2170 /* Add delay to insure DEV_RST has time to complete */
2171 if (global_device_reset)
2174 ret_val = igb_get_auto_rd_done(hw);
2176 /* When auto config read does not complete, do not
2177 * return with an error. This can happen in situations
2178 * where there is no eeprom and prevents getting link.
2180 hw_dbg("Auto Read Done did not complete\n");
2183 /* clear global device reset status bit */
2184 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2186 /* Clear any pending interrupt events. */
2187 wr32(E1000_IMC, 0xffffffff);
2190 ret_val = igb_reset_mdicnfg_82580(hw);
2192 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2194 /* Install any alternate MAC address into RAR0 */
2195 ret_val = igb_check_alt_mac_addr(hw);
2197 /* Release semaphore */
2198 if (global_device_reset)
2199 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2205 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2206 * @data: data received by reading RXPBS register
2208 * The 82580 uses a table based approach for packet buffer allocation sizes.
2209 * This function converts the retrieved value into the correct table value
2210 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2211 * 0x0 36 72 144 1 2 4 8 16
2212 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2214 u16 igb_rxpbs_adjust_82580(u32 data)
2218 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2219 ret_val = e1000_82580_rxpbs_table[data];
2225 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2227 * @hw: pointer to the HW structure
2228 * @offset: offset in words of the checksum protected region
2230 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2231 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2233 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2240 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2241 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2243 hw_dbg("NVM Read Error\n");
2246 checksum += nvm_data;
2249 if (checksum != (u16) NVM_SUM) {
2250 hw_dbg("NVM Checksum Invalid\n");
2251 ret_val = -E1000_ERR_NVM;
2260 * igb_update_nvm_checksum_with_offset - Update EEPROM
2262 * @hw: pointer to the HW structure
2263 * @offset: offset in words of the checksum protected region
2265 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2266 * up to the checksum. Then calculates the EEPROM checksum and writes the
2267 * value to the EEPROM.
2269 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2275 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2276 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2278 hw_dbg("NVM Read Error while updating checksum.\n");
2281 checksum += nvm_data;
2283 checksum = (u16) NVM_SUM - checksum;
2284 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2287 hw_dbg("NVM Write Error while updating checksum.\n");
2294 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2295 * @hw: pointer to the HW structure
2297 * Calculates the EEPROM section checksum by reading/adding each word of
2298 * the EEPROM and then verifies that the sum of the EEPROM is
2301 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2304 u16 eeprom_regions_count = 1;
2308 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2310 hw_dbg("NVM Read Error\n");
2314 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2315 /* if checksums compatibility bit is set validate checksums
2318 eeprom_regions_count = 4;
2321 for (j = 0; j < eeprom_regions_count; j++) {
2322 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2323 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2334 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2335 * @hw: pointer to the HW structure
2337 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2338 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2339 * checksum and writes the value to the EEPROM.
2341 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2347 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2349 hw_dbg("NVM Read Error while updating checksum"
2350 " compatibility bit.\n");
2354 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2355 /* set compatibility bit to validate checksums appropriately */
2356 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2357 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2360 hw_dbg("NVM Write Error while updating checksum"
2361 " compatibility bit.\n");
2366 for (j = 0; j < 4; j++) {
2367 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2368 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2378 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2379 * @hw: pointer to the HW structure
2381 * Calculates the EEPROM section checksum by reading/adding each word of
2382 * the EEPROM and then verifies that the sum of the EEPROM is
2385 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2391 for (j = 0; j < 4; j++) {
2392 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2393 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2404 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2405 * @hw: pointer to the HW structure
2407 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2408 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2409 * checksum and writes the value to the EEPROM.
2411 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2417 for (j = 0; j < 4; j++) {
2418 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2419 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2429 * __igb_access_emi_reg - Read/write EMI register
2430 * @hw: pointer to the HW structure
2431 * @addr: EMI address to program
2432 * @data: pointer to value to read/write from/to the EMI address
2433 * @read: boolean flag to indicate read or write
2435 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2436 u16 *data, bool read)
2438 s32 ret_val = E1000_SUCCESS;
2440 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2445 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2447 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2453 * igb_read_emi_reg - Read Extended Management Interface register
2454 * @hw: pointer to the HW structure
2455 * @addr: EMI address to program
2456 * @data: value to be read from the EMI address
2458 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2460 return __igb_access_emi_reg(hw, addr, data, true);
2464 * igb_set_eee_i350 - Enable/disable EEE support
2465 * @hw: pointer to the HW structure
2467 * Enable/disable EEE based on setting in dev_spec structure.
2470 s32 igb_set_eee_i350(struct e1000_hw *hw)
2475 if ((hw->mac.type < e1000_i350) ||
2476 (hw->phy.media_type != e1000_media_type_copper))
2478 ipcnfg = rd32(E1000_IPCNFG);
2479 eeer = rd32(E1000_EEER);
2481 /* enable or disable per user setting */
2482 if (!(hw->dev_spec._82575.eee_disable)) {
2483 u32 eee_su = rd32(E1000_EEE_SU);
2485 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2486 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2489 /* This bit should not be set in normal operation. */
2490 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2491 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2494 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2495 E1000_IPCNFG_EEE_100M_AN);
2496 eeer &= ~(E1000_EEER_TX_LPI_EN |
2497 E1000_EEER_RX_LPI_EN |
2500 wr32(E1000_IPCNFG, ipcnfg);
2501 wr32(E1000_EEER, eeer);
2510 * igb_set_eee_i354 - Enable/disable EEE support
2511 * @hw: pointer to the HW structure
2513 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2516 s32 igb_set_eee_i354(struct e1000_hw *hw)
2518 struct e1000_phy_info *phy = &hw->phy;
2522 if ((hw->phy.media_type != e1000_media_type_copper) ||
2523 (phy->id != M88E1543_E_PHY_ID))
2526 if (!hw->dev_spec._82575.eee_disable) {
2527 /* Switch to PHY page 18. */
2528 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2532 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2537 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2538 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2543 /* Return the PHY to page 0. */
2544 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2548 /* Turn on EEE advertisement. */
2549 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2550 E1000_EEE_ADV_DEV_I354,
2555 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2556 E1000_EEE_ADV_1000_SUPPORTED;
2557 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2558 E1000_EEE_ADV_DEV_I354,
2561 /* Turn off EEE advertisement. */
2562 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2563 E1000_EEE_ADV_DEV_I354,
2568 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2569 E1000_EEE_ADV_1000_SUPPORTED);
2570 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2571 E1000_EEE_ADV_DEV_I354,
2580 * igb_get_eee_status_i354 - Get EEE status
2581 * @hw: pointer to the HW structure
2582 * @status: EEE status
2584 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2587 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2589 struct e1000_phy_info *phy = &hw->phy;
2593 /* Check if EEE is supported on this device. */
2594 if ((hw->phy.media_type != e1000_media_type_copper) ||
2595 (phy->id != M88E1543_E_PHY_ID))
2598 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2599 E1000_PCS_STATUS_DEV_I354,
2604 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2605 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2611 static const u8 e1000_emc_temp_data[4] = {
2612 E1000_EMC_INTERNAL_DATA,
2613 E1000_EMC_DIODE1_DATA,
2614 E1000_EMC_DIODE2_DATA,
2615 E1000_EMC_DIODE3_DATA
2617 static const u8 e1000_emc_therm_limit[4] = {
2618 E1000_EMC_INTERNAL_THERM_LIMIT,
2619 E1000_EMC_DIODE1_THERM_LIMIT,
2620 E1000_EMC_DIODE2_THERM_LIMIT,
2621 E1000_EMC_DIODE3_THERM_LIMIT
2625 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2626 * @hw: pointer to hardware structure
2628 * Updates the temperatures in mac.thermal_sensor_data
2630 s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2632 s32 status = E1000_SUCCESS;
2640 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2642 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2643 return E1000_NOT_IMPLEMENTED;
2645 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2647 /* Return the internal sensor only if ETS is unsupported */
2648 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2649 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2652 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2653 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2654 != NVM_ETS_TYPE_EMC)
2655 return E1000_NOT_IMPLEMENTED;
2657 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2658 if (num_sensors > E1000_MAX_SENSORS)
2659 num_sensors = E1000_MAX_SENSORS;
2661 for (i = 1; i < num_sensors; i++) {
2662 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2663 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2664 NVM_ETS_DATA_INDEX_SHIFT);
2665 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2666 NVM_ETS_DATA_LOC_SHIFT);
2668 if (sensor_location != 0)
2669 hw->phy.ops.read_i2c_byte(hw,
2670 e1000_emc_temp_data[sensor_index],
2671 E1000_I2C_THERMAL_SENSOR_ADDR,
2672 &data->sensor[i].temp);
2678 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2679 * @hw: pointer to hardware structure
2681 * Sets the thermal sensor thresholds according to the NVM map
2682 * and save off the threshold and location values into mac.thermal_sensor_data
2684 s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2686 s32 status = E1000_SUCCESS;
2690 u8 low_thresh_delta;
2696 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2698 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2699 return E1000_NOT_IMPLEMENTED;
2701 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2703 data->sensor[0].location = 0x1;
2704 data->sensor[0].caution_thresh =
2705 (rd32(E1000_THHIGHTC) & 0xFF);
2706 data->sensor[0].max_op_thresh =
2707 (rd32(E1000_THLOWTC) & 0xFF);
2709 /* Return the internal sensor only if ETS is unsupported */
2710 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2711 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2714 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2715 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2716 != NVM_ETS_TYPE_EMC)
2717 return E1000_NOT_IMPLEMENTED;
2719 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2720 NVM_ETS_LTHRES_DELTA_SHIFT);
2721 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2723 for (i = 1; i <= num_sensors; i++) {
2724 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2725 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2726 NVM_ETS_DATA_INDEX_SHIFT);
2727 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2728 NVM_ETS_DATA_LOC_SHIFT);
2729 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2731 hw->phy.ops.write_i2c_byte(hw,
2732 e1000_emc_therm_limit[sensor_index],
2733 E1000_I2C_THERMAL_SENSOR_ADDR,
2736 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2737 data->sensor[i].location = sensor_location;
2738 data->sensor[i].caution_thresh = therm_limit;
2739 data->sensor[i].max_op_thresh = therm_limit -
2746 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2747 .init_hw = igb_init_hw_82575,
2748 .check_for_link = igb_check_for_link_82575,
2749 .rar_set = igb_rar_set,
2750 .read_mac_addr = igb_read_mac_addr_82575,
2751 .get_speed_and_duplex = igb_get_link_up_info_82575,
2752 #ifdef CONFIG_IGB_HWMON
2753 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2754 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2758 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2759 .acquire = igb_acquire_phy_82575,
2760 .get_cfg_done = igb_get_cfg_done_82575,
2761 .release = igb_release_phy_82575,
2762 .write_i2c_byte = igb_write_i2c_byte,
2763 .read_i2c_byte = igb_read_i2c_byte,
2766 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2767 .acquire = igb_acquire_nvm_82575,
2768 .read = igb_read_nvm_eerd,
2769 .release = igb_release_nvm_82575,
2770 .write = igb_write_nvm_spi,
2773 const struct e1000_info e1000_82575_info = {
2774 .get_invariants = igb_get_invariants_82575,
2775 .mac_ops = &e1000_mac_ops_82575,
2776 .phy_ops = &e1000_phy_ops_82575,
2777 .nvm_ops = &e1000_nvm_ops_82575,