1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 ******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/if_ether.h>
36 #include "e1000_i210.h"
39 * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
40 * @hw: pointer to the HW structure
42 * Acquire the HW semaphore to access the PHY or NVM
44 static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw)
47 s32 ret_val = E1000_SUCCESS;
48 s32 timeout = hw->nvm.word_size + 1;
51 /* Get the FW semaphore. */
52 for (i = 0; i < timeout; i++) {
53 swsm = rd32(E1000_SWSM);
54 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
56 /* Semaphore acquired if bit latched */
57 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
64 /* Release semaphores */
65 igb_put_hw_semaphore(hw);
66 hw_dbg("Driver can't access the NVM\n");
67 ret_val = -E1000_ERR_NVM;
76 * igb_acquire_nvm_i210 - Request for access to EEPROM
77 * @hw: pointer to the HW structure
79 * Acquire the necessary semaphores for exclusive access to the EEPROM.
80 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
81 * Return successful if access grant bit set, else clear the request for
82 * EEPROM access and return -E1000_ERR_NVM (-1).
84 s32 igb_acquire_nvm_i210(struct e1000_hw *hw)
86 return igb_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
90 * igb_release_nvm_i210 - Release exclusive access to EEPROM
91 * @hw: pointer to the HW structure
93 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
94 * then release the semaphores acquired.
96 void igb_release_nvm_i210(struct e1000_hw *hw)
98 igb_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
102 * igb_put_hw_semaphore_i210 - Release hardware semaphore
103 * @hw: pointer to the HW structure
105 * Release hardware semaphore used to access the PHY or NVM
107 static void igb_put_hw_semaphore_i210(struct e1000_hw *hw)
111 swsm = rd32(E1000_SWSM);
113 swsm &= ~E1000_SWSM_SWESMBI;
115 wr32(E1000_SWSM, swsm);
119 * igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
120 * @hw: pointer to the HW structure
121 * @mask: specifies which semaphore to acquire
123 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
124 * will also specify which port we're acquiring the lock for.
126 s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
130 u32 fwmask = mask << 16;
131 s32 ret_val = E1000_SUCCESS;
132 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
134 while (i < timeout) {
135 if (igb_get_hw_semaphore_i210(hw)) {
136 ret_val = -E1000_ERR_SWFW_SYNC;
140 swfw_sync = rd32(E1000_SW_FW_SYNC);
141 if (!(swfw_sync & fwmask))
144 /* Firmware currently using resource (fwmask) */
145 igb_put_hw_semaphore_i210(hw);
151 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
152 ret_val = -E1000_ERR_SWFW_SYNC;
157 wr32(E1000_SW_FW_SYNC, swfw_sync);
159 igb_put_hw_semaphore_i210(hw);
165 * igb_release_swfw_sync_i210 - Release SW/FW semaphore
166 * @hw: pointer to the HW structure
167 * @mask: specifies which semaphore to acquire
169 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
170 * will also specify which port we're releasing the lock for.
172 void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
176 while (igb_get_hw_semaphore_i210(hw) != E1000_SUCCESS)
179 swfw_sync = rd32(E1000_SW_FW_SYNC);
181 wr32(E1000_SW_FW_SYNC, swfw_sync);
183 igb_put_hw_semaphore_i210(hw);
187 * igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
188 * @hw: pointer to the HW structure
189 * @offset: offset of word in the Shadow Ram to read
190 * @words: number of words to read
191 * @data: word read from the Shadow Ram
193 * Reads a 16 bit word from the Shadow Ram using the EERD register.
194 * Uses necessary synchronization semaphores.
196 s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
199 s32 status = E1000_SUCCESS;
202 /* We cannot hold synchronization semaphores for too long,
203 * because of forceful takeover procedure. However it is more efficient
204 * to read in bursts than synchronizing access for each word.
206 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
207 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
208 E1000_EERD_EEWR_MAX_COUNT : (words - i);
209 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
210 status = igb_read_nvm_eerd(hw, offset, count,
212 hw->nvm.ops.release(hw);
214 status = E1000_ERR_SWFW_SYNC;
217 if (status != E1000_SUCCESS)
225 * igb_write_nvm_srwr - Write to Shadow Ram using EEWR
226 * @hw: pointer to the HW structure
227 * @offset: offset within the Shadow Ram to be written to
228 * @words: number of words to write
229 * @data: 16 bit word(s) to be written to the Shadow Ram
231 * Writes data to Shadow Ram at offset using EEWR register.
233 * If igb_update_nvm_checksum is not called after this function , the
234 * Shadow Ram will most likely contain an invalid checksum.
236 static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
239 struct e1000_nvm_info *nvm = &hw->nvm;
241 u32 attempts = 100000;
242 s32 ret_val = E1000_SUCCESS;
244 /* A check for invalid values: offset too large, too many words,
245 * too many words for the offset, and not enough words.
247 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
249 hw_dbg("nvm parameter(s) out of bounds\n");
250 ret_val = -E1000_ERR_NVM;
254 for (i = 0; i < words; i++) {
255 eewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
256 (data[i] << E1000_NVM_RW_REG_DATA) |
257 E1000_NVM_RW_REG_START;
259 wr32(E1000_SRWR, eewr);
261 for (k = 0; k < attempts; k++) {
262 if (E1000_NVM_RW_REG_DONE &
264 ret_val = E1000_SUCCESS;
270 if (ret_val != E1000_SUCCESS) {
271 hw_dbg("Shadow RAM write EEWR timed out\n");
281 * igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
282 * @hw: pointer to the HW structure
283 * @offset: offset within the Shadow RAM to be written to
284 * @words: number of words to write
285 * @data: 16 bit word(s) to be written to the Shadow RAM
287 * Writes data to Shadow RAM at offset using EEWR register.
289 * If e1000_update_nvm_checksum is not called after this function , the
290 * data will not be committed to FLASH and also Shadow RAM will most likely
291 * contain an invalid checksum.
293 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
296 s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
299 s32 status = E1000_SUCCESS;
302 /* We cannot hold synchronization semaphores for too long,
303 * because of forceful takeover procedure. However it is more efficient
304 * to write in bursts than synchronizing access for each word.
306 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
307 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
308 E1000_EERD_EEWR_MAX_COUNT : (words - i);
309 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
310 status = igb_write_nvm_srwr(hw, offset, count,
312 hw->nvm.ops.release(hw);
314 status = E1000_ERR_SWFW_SYNC;
317 if (status != E1000_SUCCESS)
325 * igb_read_nvm_i211 - Read NVM wrapper function for I211
326 * @hw: pointer to the HW structure
327 * @words: number of words to read
328 * @data: pointer to the data read
330 * Wrapper function to return data formerly found in the NVM.
332 s32 igb_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words,
335 s32 ret_val = E1000_SUCCESS;
337 /* Only the MAC addr is required to be present in the iNVM */
340 ret_val = igb_read_invm_i211(hw, offset, &data[0]);
341 ret_val |= igb_read_invm_i211(hw, offset+1, &data[1]);
342 ret_val |= igb_read_invm_i211(hw, offset+2, &data[2]);
343 if (ret_val != E1000_SUCCESS)
344 hw_dbg("MAC Addr not found in iNVM\n");
346 case NVM_INIT_CTRL_2:
347 ret_val = igb_read_invm_i211(hw, (u8)offset, data);
348 if (ret_val != E1000_SUCCESS) {
349 *data = NVM_INIT_CTRL_2_DEFAULT_I211;
350 ret_val = E1000_SUCCESS;
353 case NVM_INIT_CTRL_4:
354 ret_val = igb_read_invm_i211(hw, (u8)offset, data);
355 if (ret_val != E1000_SUCCESS) {
356 *data = NVM_INIT_CTRL_4_DEFAULT_I211;
357 ret_val = E1000_SUCCESS;
361 ret_val = igb_read_invm_i211(hw, (u8)offset, data);
362 if (ret_val != E1000_SUCCESS) {
363 *data = NVM_LED_1_CFG_DEFAULT_I211;
364 ret_val = E1000_SUCCESS;
367 case NVM_LED_0_2_CFG:
368 igb_read_invm_i211(hw, offset, data);
369 if (ret_val != E1000_SUCCESS) {
370 *data = NVM_LED_0_2_CFG_DEFAULT_I211;
371 ret_val = E1000_SUCCESS;
374 case NVM_ID_LED_SETTINGS:
375 ret_val = igb_read_invm_i211(hw, (u8)offset, data);
376 if (ret_val != E1000_SUCCESS) {
377 *data = ID_LED_RESERVED_FFFF;
378 ret_val = E1000_SUCCESS;
381 *data = hw->subsystem_device_id;
384 *data = hw->subsystem_vendor_id;
387 *data = hw->device_id;
390 *data = hw->vendor_id;
393 hw_dbg("NVM word 0x%02x is not mapped.\n", offset);
394 *data = NVM_RESERVED_WORD;
401 * igb_read_invm_i211 - Reads OTP
402 * @hw: pointer to the HW structure
403 * @address: the word address (aka eeprom offset) to read
404 * @data: pointer to the data read
406 * Reads 16-bit words from the OTP. Return error when the word is not
409 s32 igb_read_invm_i211(struct e1000_hw *hw, u16 address, u16 *data)
411 s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
414 u8 record_type, word_address;
416 for (i = 0; i < E1000_INVM_SIZE; i++) {
417 invm_dword = rd32(E1000_INVM_DATA_REG(i));
418 /* Get record type */
419 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
420 if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)
422 if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)
423 i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
424 if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)
425 i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
426 if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {
427 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
428 if (word_address == (u8)address) {
429 *data = INVM_DWORD_TO_WORD_DATA(invm_dword);
430 hw_dbg("Read INVM Word 0x%02x = %x",
432 status = E1000_SUCCESS;
437 if (status != E1000_SUCCESS)
438 hw_dbg("Requested word 0x%02x not found in OTP\n", address);
443 * igb_read_invm_version - Reads iNVM version and image type
444 * @hw: pointer to the HW structure
445 * @invm_ver: version structure for the version read
447 * Reads iNVM version and image type.
449 s32 igb_read_invm_version(struct e1000_hw *hw,
450 struct e1000_fw_version *invm_ver) {
452 u32 *next_record = NULL;
455 u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /
456 E1000_INVM_RECORD_SIZE_IN_BYTES);
457 u32 buffer[E1000_INVM_SIZE];
458 s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
461 /* Read iNVM memory */
462 for (i = 0; i < E1000_INVM_SIZE; i++) {
463 invm_dword = rd32(E1000_INVM_DATA_REG(i));
464 buffer[i] = invm_dword;
467 /* Read version number */
468 for (i = 1; i < invm_blocks; i++) {
469 record = &buffer[invm_blocks - i];
470 next_record = &buffer[invm_blocks - i + 1];
472 /* Check if we have first version location used */
473 if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
475 status = E1000_SUCCESS;
478 /* Check if we have second version location used */
480 ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
481 version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
482 status = E1000_SUCCESS;
485 /* Check if we have odd version location
486 * used and it is the last one used
488 else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&
489 ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&
491 version = (*next_record & E1000_INVM_VER_FIELD_TWO)
493 status = E1000_SUCCESS;
496 /* Check if we have even version location
497 * used and it is the last one used
499 else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
500 ((*record & 0x3) == 0)) {
501 version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
502 status = E1000_SUCCESS;
507 if (status == E1000_SUCCESS) {
508 invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)
509 >> E1000_INVM_MAJOR_SHIFT;
510 invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;
512 /* Read Image Type */
513 for (i = 1; i < invm_blocks; i++) {
514 record = &buffer[invm_blocks - i];
515 next_record = &buffer[invm_blocks - i + 1];
517 /* Check if we have image type in first location used */
518 if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {
519 invm_ver->invm_img_type = 0;
520 status = E1000_SUCCESS;
523 /* Check if we have image type in first location used */
524 else if ((((*record & 0x3) == 0) &&
525 ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||
526 ((((*record & 0x3) != 0) && (i != 1)))) {
527 invm_ver->invm_img_type =
528 (*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;
529 status = E1000_SUCCESS;
537 * igb_validate_nvm_checksum_i210 - Validate EEPROM checksum
538 * @hw: pointer to the HW structure
540 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
541 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
543 s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw)
545 s32 status = E1000_SUCCESS;
546 s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);
548 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
550 /* Replace the read function with semaphore grabbing with
551 * the one that skips this for a while.
552 * We have semaphore taken already here.
554 read_op_ptr = hw->nvm.ops.read;
555 hw->nvm.ops.read = igb_read_nvm_eerd;
557 status = igb_validate_nvm_checksum(hw);
559 /* Revert original read operation. */
560 hw->nvm.ops.read = read_op_ptr;
562 hw->nvm.ops.release(hw);
564 status = E1000_ERR_SWFW_SYNC;
571 * igb_update_nvm_checksum_i210 - Update EEPROM checksum
572 * @hw: pointer to the HW structure
574 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
575 * up to the checksum. Then calculates the EEPROM checksum and writes the
576 * value to the EEPROM. Next commit EEPROM data onto the Flash.
578 s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw)
580 s32 ret_val = E1000_SUCCESS;
584 /* Read the first word from the EEPROM. If this times out or fails, do
585 * not continue or we could be in for a very long wait while every
588 ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data);
589 if (ret_val != E1000_SUCCESS) {
590 hw_dbg("EEPROM read failed\n");
594 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
595 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
596 * because we do not want to take the synchronization
597 * semaphores twice here.
600 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
601 ret_val = igb_read_nvm_eerd(hw, i, 1, &nvm_data);
603 hw->nvm.ops.release(hw);
604 hw_dbg("NVM Read Error while updating checksum.\n");
607 checksum += nvm_data;
609 checksum = (u16) NVM_SUM - checksum;
610 ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
612 if (ret_val != E1000_SUCCESS) {
613 hw->nvm.ops.release(hw);
614 hw_dbg("NVM Write Error while updating checksum.\n");
618 hw->nvm.ops.release(hw);
620 ret_val = igb_update_flash_i210(hw);
622 ret_val = -E1000_ERR_SWFW_SYNC;
629 * igb_pool_flash_update_done_i210 - Pool FLUDONE status.
630 * @hw: pointer to the HW structure
633 static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw)
635 s32 ret_val = -E1000_ERR_NVM;
638 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
639 reg = rd32(E1000_EECD);
640 if (reg & E1000_EECD_FLUDONE_I210) {
641 ret_val = E1000_SUCCESS;
651 * igb_update_flash_i210 - Commit EEPROM to the flash
652 * @hw: pointer to the HW structure
655 s32 igb_update_flash_i210(struct e1000_hw *hw)
657 s32 ret_val = E1000_SUCCESS;
660 ret_val = igb_pool_flash_update_done_i210(hw);
661 if (ret_val == -E1000_ERR_NVM) {
662 hw_dbg("Flash update time out\n");
666 flup = rd32(E1000_EECD) | E1000_EECD_FLUPD_I210;
667 wr32(E1000_EECD, flup);
669 ret_val = igb_pool_flash_update_done_i210(hw);
670 if (ret_val == E1000_SUCCESS)
671 hw_dbg("Flash update complete\n");
673 hw_dbg("Flash update time out\n");
680 * igb_valid_led_default_i210 - Verify a valid default LED config
681 * @hw: pointer to the HW structure
682 * @data: pointer to the NVM (EEPROM)
684 * Read the EEPROM for the current default LED configuration. If the
685 * LED configuration is not valid, set to a valid LED configuration.
687 s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data)
691 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
693 hw_dbg("NVM Read Error\n");
697 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
698 switch (hw->phy.media_type) {
699 case e1000_media_type_internal_serdes:
700 *data = ID_LED_DEFAULT_I210_SERDES;
702 case e1000_media_type_copper:
704 *data = ID_LED_DEFAULT_I210;
713 * __igb_access_xmdio_reg - Read/write XMDIO register
714 * @hw: pointer to the HW structure
715 * @address: XMDIO address to program
716 * @dev_addr: device address to program
717 * @data: pointer to value to read/write from/to the XMDIO address
718 * @read: boolean flag to indicate read or write
720 static s32 __igb_access_xmdio_reg(struct e1000_hw *hw, u16 address,
721 u8 dev_addr, u16 *data, bool read)
723 s32 ret_val = E1000_SUCCESS;
725 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
729 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
733 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
739 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
741 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
745 /* Recalibrate the device back to 0 */
746 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
754 * igb_read_xmdio_reg - Read XMDIO register
755 * @hw: pointer to the HW structure
756 * @addr: XMDIO address to program
757 * @dev_addr: device address to program
758 * @data: value to be read from the EMI address
760 s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
762 return __igb_access_xmdio_reg(hw, addr, dev_addr, data, true);
766 * igb_write_xmdio_reg - Write XMDIO register
767 * @hw: pointer to the HW structure
768 * @addr: XMDIO address to program
769 * @dev_addr: device address to program
770 * @data: value to be written to the XMDIO address
772 s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
774 return __igb_access_xmdio_reg(hw, addr, dev_addr, &data, false);