1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
31 #include "e1000_mac.h"
32 #include "e1000_phy.h"
34 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
35 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
37 static s32 igb_wait_autoneg(struct e1000_hw *hw);
38 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
40 /* Cable length tables */
41 static const u16 e1000_m88_cable_length_table[] = {
42 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
44 (sizeof(e1000_m88_cable_length_table) / \
45 sizeof(e1000_m88_cable_length_table[0]))
47 static const u16 e1000_igp_2_cable_length_table[] = {
48 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
55 104, 109, 114, 118, 121, 124};
56 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
57 (sizeof(e1000_igp_2_cable_length_table) / \
58 sizeof(e1000_igp_2_cable_length_table[0]))
61 * igb_check_reset_block - Check if PHY reset is blocked
62 * @hw: pointer to the HW structure
64 * Read the PHY management control register and check whether a PHY reset
65 * is blocked. If a reset is not blocked return 0, otherwise
66 * return E1000_BLK_PHY_RESET (12).
68 s32 igb_check_reset_block(struct e1000_hw *hw)
72 manc = rd32(E1000_MANC);
74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
78 * igb_get_phy_id - Retrieve the PHY ID and revision
79 * @hw: pointer to the HW structure
81 * Reads the PHY registers and stores the PHY ID and possibly the PHY
82 * revision in the hardware structure.
84 s32 igb_get_phy_id(struct e1000_hw *hw)
86 struct e1000_phy_info *phy = &hw->phy;
90 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
94 phy->id = (u32)(phy_id << 16);
96 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
100 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
101 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
108 * igb_phy_reset_dsp - Reset PHY DSP
109 * @hw: pointer to the HW structure
111 * Reset the digital signal processor.
113 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
117 if (!(hw->phy.ops.write_reg))
120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
131 * igb_read_phy_reg_mdic - Read MDI control register
132 * @hw: pointer to the HW structure
133 * @offset: register offset to be read
134 * @data: pointer to the read data
136 * Reads the MDI control regsiter in the PHY at offset and stores the
137 * information read to data.
139 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
141 struct e1000_phy_info *phy = &hw->phy;
145 if (offset > MAX_PHY_REG_ADDRESS) {
146 hw_dbg("PHY Address %d is out of range\n", offset);
147 ret_val = -E1000_ERR_PARAM;
151 /* Set up Op-code, Phy Address, and register offset in the MDI
152 * Control register. The MAC will take care of interfacing with the
153 * PHY to retrieve the desired data.
155 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
156 (phy->addr << E1000_MDIC_PHY_SHIFT) |
157 (E1000_MDIC_OP_READ));
159 wr32(E1000_MDIC, mdic);
161 /* Poll the ready bit to see if the MDI read completed
162 * Increasing the time out as testing showed failures with
165 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
167 mdic = rd32(E1000_MDIC);
168 if (mdic & E1000_MDIC_READY)
171 if (!(mdic & E1000_MDIC_READY)) {
172 hw_dbg("MDI Read did not complete\n");
173 ret_val = -E1000_ERR_PHY;
176 if (mdic & E1000_MDIC_ERROR) {
177 hw_dbg("MDI Error\n");
178 ret_val = -E1000_ERR_PHY;
188 * igb_write_phy_reg_mdic - Write MDI control register
189 * @hw: pointer to the HW structure
190 * @offset: register offset to write to
191 * @data: data to write to register at offset
193 * Writes data to MDI control register in the PHY at offset.
195 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
197 struct e1000_phy_info *phy = &hw->phy;
201 if (offset > MAX_PHY_REG_ADDRESS) {
202 hw_dbg("PHY Address %d is out of range\n", offset);
203 ret_val = -E1000_ERR_PARAM;
207 /* Set up Op-code, Phy Address, and register offset in the MDI
208 * Control register. The MAC will take care of interfacing with the
209 * PHY to retrieve the desired data.
211 mdic = (((u32)data) |
212 (offset << E1000_MDIC_REG_SHIFT) |
213 (phy->addr << E1000_MDIC_PHY_SHIFT) |
214 (E1000_MDIC_OP_WRITE));
216 wr32(E1000_MDIC, mdic);
218 /* Poll the ready bit to see if the MDI read completed
219 * Increasing the time out as testing showed failures with
222 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
224 mdic = rd32(E1000_MDIC);
225 if (mdic & E1000_MDIC_READY)
228 if (!(mdic & E1000_MDIC_READY)) {
229 hw_dbg("MDI Write did not complete\n");
230 ret_val = -E1000_ERR_PHY;
233 if (mdic & E1000_MDIC_ERROR) {
234 hw_dbg("MDI Error\n");
235 ret_val = -E1000_ERR_PHY;
244 * igb_read_phy_reg_i2c - Read PHY register using i2c
245 * @hw: pointer to the HW structure
246 * @offset: register offset to be read
247 * @data: pointer to the read data
249 * Reads the PHY register at offset using the i2c interface and stores the
250 * retrieved information in data.
252 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
254 struct e1000_phy_info *phy = &hw->phy;
257 /* Set up Op-code, Phy Address, and register address in the I2CCMD
258 * register. The MAC will take care of interfacing with the
259 * PHY to retrieve the desired data.
261 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
262 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
263 (E1000_I2CCMD_OPCODE_READ));
265 wr32(E1000_I2CCMD, i2ccmd);
267 /* Poll the ready bit to see if the I2C read completed */
268 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
270 i2ccmd = rd32(E1000_I2CCMD);
271 if (i2ccmd & E1000_I2CCMD_READY)
274 if (!(i2ccmd & E1000_I2CCMD_READY)) {
275 hw_dbg("I2CCMD Read did not complete\n");
276 return -E1000_ERR_PHY;
278 if (i2ccmd & E1000_I2CCMD_ERROR) {
279 hw_dbg("I2CCMD Error bit set\n");
280 return -E1000_ERR_PHY;
283 /* Need to byte-swap the 16-bit value. */
284 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
290 * igb_write_phy_reg_i2c - Write PHY register using i2c
291 * @hw: pointer to the HW structure
292 * @offset: register offset to write to
293 * @data: data to write at register offset
295 * Writes the data to PHY register at the offset using the i2c interface.
297 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
299 struct e1000_phy_info *phy = &hw->phy;
301 u16 phy_data_swapped;
303 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
304 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
305 hw_dbg("PHY I2C Address %d is out of range.\n",
307 return -E1000_ERR_CONFIG;
310 /* Swap the data bytes for the I2C interface */
311 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
313 /* Set up Op-code, Phy Address, and register address in the I2CCMD
314 * register. The MAC will take care of interfacing with the
315 * PHY to retrieve the desired data.
317 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
318 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
319 E1000_I2CCMD_OPCODE_WRITE |
322 wr32(E1000_I2CCMD, i2ccmd);
324 /* Poll the ready bit to see if the I2C read completed */
325 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
327 i2ccmd = rd32(E1000_I2CCMD);
328 if (i2ccmd & E1000_I2CCMD_READY)
331 if (!(i2ccmd & E1000_I2CCMD_READY)) {
332 hw_dbg("I2CCMD Write did not complete\n");
333 return -E1000_ERR_PHY;
335 if (i2ccmd & E1000_I2CCMD_ERROR) {
336 hw_dbg("I2CCMD Error bit set\n");
337 return -E1000_ERR_PHY;
344 * igb_read_phy_reg_igp - Read igp PHY register
345 * @hw: pointer to the HW structure
346 * @offset: register offset to be read
347 * @data: pointer to the read data
349 * Acquires semaphore, if necessary, then reads the PHY register at offset
350 * and storing the retrieved information in data. Release any acquired
351 * semaphores before exiting.
353 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
357 if (!(hw->phy.ops.acquire))
360 ret_val = hw->phy.ops.acquire(hw);
364 if (offset > MAX_PHY_MULTI_PAGE_REG) {
365 ret_val = igb_write_phy_reg_mdic(hw,
366 IGP01E1000_PHY_PAGE_SELECT,
369 hw->phy.ops.release(hw);
374 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
377 hw->phy.ops.release(hw);
384 * igb_write_phy_reg_igp - Write igp PHY register
385 * @hw: pointer to the HW structure
386 * @offset: register offset to write to
387 * @data: data to write at register offset
389 * Acquires semaphore, if necessary, then writes the data to PHY register
390 * at the offset. Release any acquired semaphores before exiting.
392 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
396 if (!(hw->phy.ops.acquire))
399 ret_val = hw->phy.ops.acquire(hw);
403 if (offset > MAX_PHY_MULTI_PAGE_REG) {
404 ret_val = igb_write_phy_reg_mdic(hw,
405 IGP01E1000_PHY_PAGE_SELECT,
408 hw->phy.ops.release(hw);
413 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
416 hw->phy.ops.release(hw);
423 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
424 * @hw: pointer to the HW structure
426 * Sets up Carrier-sense on Transmit and downshift values.
428 s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
430 struct e1000_phy_info *phy = &hw->phy;
434 if (phy->reset_disable) {
439 if (phy->type == e1000_phy_82580) {
440 ret_val = hw->phy.ops.reset(hw);
442 hw_dbg("Error resetting the PHY.\n");
447 /* Enable CRS on TX. This must be set for half-duplex operation. */
448 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
452 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
454 /* Enable downshift */
455 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
457 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
461 /* Set MDI/MDIX mode */
462 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
465 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
471 switch (hw->phy.mdix) {
475 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
479 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
482 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
489 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
490 * @hw: pointer to the HW structure
492 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
493 * and downshift values are set also.
495 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
497 struct e1000_phy_info *phy = &hw->phy;
501 if (phy->reset_disable) {
506 /* Enable CRS on TX. This must be set for half-duplex operation. */
507 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
511 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
514 * MDI/MDI-X = 0 (default)
515 * 0 - Auto for all speeds
518 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
520 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
524 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
527 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
530 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
534 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
539 * disable_polarity_correction = 0 (default)
540 * Automatic Correction for Reversed Cable Polarity
544 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
545 if (phy->disable_polarity_correction == 1)
546 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
548 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
552 if (phy->revision < E1000_REVISION_4) {
553 /* Force TX_CLK in the Extended PHY Specific Control Register
556 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
561 phy_data |= M88E1000_EPSCR_TX_CLK_25;
563 if ((phy->revision == E1000_REVISION_2) &&
564 (phy->id == M88E1111_I_PHY_ID)) {
565 /* 82573L PHY - set the downshift counter to 5x. */
566 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
567 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
569 /* Configure Master and Slave downshift values */
570 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
571 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
572 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
573 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
575 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
581 /* Commit the changes. */
582 ret_val = igb_phy_sw_reset(hw);
584 hw_dbg("Error committing the PHY changes\n");
587 if (phy->type == e1000_phy_i210) {
588 ret_val = igb_set_master_slave_mode(hw);
598 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
599 * @hw: pointer to the HW structure
601 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
602 * Also enables and sets the downshift parameters.
604 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
606 struct e1000_phy_info *phy = &hw->phy;
610 if (phy->reset_disable) {
615 /* Enable CRS on Tx. This must be set for half-duplex operation. */
616 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
621 * MDI/MDI-X = 0 (default)
622 * 0 - Auto for all speeds
625 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
627 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
631 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
634 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
637 /* M88E1112 does not support this mode) */
638 if (phy->id != M88E1112_E_PHY_ID) {
639 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
644 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
649 * disable_polarity_correction = 0 (default)
650 * Automatic Correction for Reversed Cable Polarity
654 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
655 if (phy->disable_polarity_correction == 1)
656 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
658 /* Enable downshift and setting it to X6 */
659 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
660 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
661 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
663 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
667 /* Commit the changes. */
668 ret_val = igb_phy_sw_reset(hw);
670 hw_dbg("Error committing the PHY changes\n");
679 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
680 * @hw: pointer to the HW structure
682 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
685 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
687 struct e1000_phy_info *phy = &hw->phy;
691 if (phy->reset_disable) {
696 ret_val = phy->ops.reset(hw);
698 hw_dbg("Error resetting the PHY.\n");
702 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
703 * timeout issues when LFS is enabled.
707 /* The NVM settings will configure LPLU in D3 for
710 if (phy->type == e1000_phy_igp) {
711 /* disable lplu d3 during driver init */
712 if (phy->ops.set_d3_lplu_state)
713 ret_val = phy->ops.set_d3_lplu_state(hw, false);
715 hw_dbg("Error Disabling LPLU D3\n");
720 /* disable lplu d0 during driver init */
721 ret_val = phy->ops.set_d0_lplu_state(hw, false);
723 hw_dbg("Error Disabling LPLU D0\n");
726 /* Configure mdi-mdix settings */
727 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
731 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
735 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
738 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
742 data |= IGP01E1000_PSCR_AUTO_MDIX;
745 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
749 /* set auto-master slave resolution settings */
750 if (hw->mac.autoneg) {
751 /* when autonegotiation advertisement is only 1000Mbps then we
752 * should disable SmartSpeed and enable Auto MasterSlave
753 * resolution as hardware default.
755 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
756 /* Disable SmartSpeed */
757 ret_val = phy->ops.read_reg(hw,
758 IGP01E1000_PHY_PORT_CONFIG,
763 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
764 ret_val = phy->ops.write_reg(hw,
765 IGP01E1000_PHY_PORT_CONFIG,
770 /* Set auto Master/Slave resolution process */
771 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
775 data &= ~CR_1000T_MS_ENABLE;
776 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
781 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
785 /* load defaults for future use */
786 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
787 ((data & CR_1000T_MS_VALUE) ?
788 e1000_ms_force_master :
789 e1000_ms_force_slave) :
792 switch (phy->ms_type) {
793 case e1000_ms_force_master:
794 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
796 case e1000_ms_force_slave:
797 data |= CR_1000T_MS_ENABLE;
798 data &= ~(CR_1000T_MS_VALUE);
801 data &= ~CR_1000T_MS_ENABLE;
805 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
815 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
816 * @hw: pointer to the HW structure
818 * Performs initial bounds checking on autoneg advertisement parameter, then
819 * configure to advertise the full capability. Setup the PHY to autoneg
820 * and restart the negotiation process between the link partner. If
821 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
823 static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
825 struct e1000_phy_info *phy = &hw->phy;
829 /* Perform some bounds checking on the autoneg advertisement
832 phy->autoneg_advertised &= phy->autoneg_mask;
834 /* If autoneg_advertised is zero, we assume it was not defaulted
835 * by the calling code so we set to advertise full capability.
837 if (phy->autoneg_advertised == 0)
838 phy->autoneg_advertised = phy->autoneg_mask;
840 hw_dbg("Reconfiguring auto-neg advertisement params\n");
841 ret_val = igb_phy_setup_autoneg(hw);
843 hw_dbg("Error Setting up Auto-Negotiation\n");
846 hw_dbg("Restarting Auto-Neg\n");
848 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
849 * the Auto Neg Restart bit in the PHY control register.
851 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
855 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
856 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
860 /* Does the user want to wait for Auto-Neg to complete here, or
861 * check at a later time (for example, callback routine).
863 if (phy->autoneg_wait_to_complete) {
864 ret_val = igb_wait_autoneg(hw);
866 hw_dbg("Error while waiting for "
867 "autoneg to complete\n");
872 hw->mac.get_link_status = true;
879 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
880 * @hw: pointer to the HW structure
882 * Reads the MII auto-neg advertisement register and/or the 1000T control
883 * register and if the PHY is already setup for auto-negotiation, then
884 * return successful. Otherwise, setup advertisement and flow control to
885 * the appropriate values for the wanted auto-negotiation.
887 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
889 struct e1000_phy_info *phy = &hw->phy;
891 u16 mii_autoneg_adv_reg;
892 u16 mii_1000t_ctrl_reg = 0;
894 phy->autoneg_advertised &= phy->autoneg_mask;
896 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
897 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
901 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
902 /* Read the MII 1000Base-T Control Register (Address 9). */
903 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
904 &mii_1000t_ctrl_reg);
909 /* Need to parse both autoneg_advertised and fc and set up
910 * the appropriate PHY registers. First we will parse for
911 * autoneg_advertised software override. Since we can advertise
912 * a plethora of combinations, we need to check each bit
916 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
917 * Advertisement Register (Address 4) and the 1000 mb speed bits in
918 * the 1000Base-T Control Register (Address 9).
920 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
921 NWAY_AR_100TX_HD_CAPS |
922 NWAY_AR_10T_FD_CAPS |
923 NWAY_AR_10T_HD_CAPS);
924 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
926 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
928 /* Do we want to advertise 10 Mb Half Duplex? */
929 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
930 hw_dbg("Advertise 10mb Half duplex\n");
931 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
934 /* Do we want to advertise 10 Mb Full Duplex? */
935 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
936 hw_dbg("Advertise 10mb Full duplex\n");
937 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
940 /* Do we want to advertise 100 Mb Half Duplex? */
941 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
942 hw_dbg("Advertise 100mb Half duplex\n");
943 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
946 /* Do we want to advertise 100 Mb Full Duplex? */
947 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
948 hw_dbg("Advertise 100mb Full duplex\n");
949 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
952 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
953 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
954 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
956 /* Do we want to advertise 1000 Mb Full Duplex? */
957 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
958 hw_dbg("Advertise 1000mb Full duplex\n");
959 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
962 /* Check for a software override of the flow control settings, and
963 * setup the PHY advertisement registers accordingly. If
964 * auto-negotiation is enabled, then software will have to set the
965 * "PAUSE" bits to the correct value in the Auto-Negotiation
966 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
969 * The possible values of the "fc" parameter are:
970 * 0: Flow control is completely disabled
971 * 1: Rx flow control is enabled (we can receive pause frames
972 * but not send pause frames).
973 * 2: Tx flow control is enabled (we can send pause frames
974 * but we do not support receiving pause frames).
975 * 3: Both Rx and TX flow control (symmetric) are enabled.
976 * other: No software override. The flow control configuration
977 * in the EEPROM is used.
979 switch (hw->fc.current_mode) {
981 /* Flow control (RX & TX) is completely disabled by a
982 * software over-ride.
984 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
986 case e1000_fc_rx_pause:
987 /* RX Flow control is enabled, and TX Flow control is
988 * disabled, by a software over-ride.
990 * Since there really isn't a way to advertise that we are
991 * capable of RX Pause ONLY, we will advertise that we
992 * support both symmetric and asymmetric RX PAUSE. Later
993 * (in e1000_config_fc_after_link_up) we will disable the
994 * hw's ability to send PAUSE frames.
996 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
998 case e1000_fc_tx_pause:
999 /* TX Flow control is enabled, and RX Flow control is
1000 * disabled, by a software over-ride.
1002 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1003 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1006 /* Flow control (both RX and TX) is enabled by a software
1009 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1012 hw_dbg("Flow control param set incorrectly\n");
1013 ret_val = -E1000_ERR_CONFIG;
1017 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1021 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1023 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1024 ret_val = phy->ops.write_reg(hw,
1026 mii_1000t_ctrl_reg);
1036 * igb_setup_copper_link - Configure copper link settings
1037 * @hw: pointer to the HW structure
1039 * Calls the appropriate function to configure the link for auto-neg or forced
1040 * speed and duplex. Then we check for link, once link is established calls
1041 * to configure collision distance and flow control are called. If link is
1042 * not established, we return -E1000_ERR_PHY (-2).
1044 s32 igb_setup_copper_link(struct e1000_hw *hw)
1049 if (hw->mac.autoneg) {
1050 /* Setup autoneg and flow control advertisement and perform
1053 ret_val = igb_copper_link_autoneg(hw);
1057 /* PHY will be set to 10H, 10F, 100H or 100F
1058 * depending on user settings.
1060 hw_dbg("Forcing Speed and Duplex\n");
1061 ret_val = hw->phy.ops.force_speed_duplex(hw);
1063 hw_dbg("Error Forcing Speed and Duplex\n");
1068 /* Check link status. Wait up to 100 microseconds for link to become
1071 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1076 hw_dbg("Valid link established!!!\n");
1077 igb_config_collision_dist(hw);
1078 ret_val = igb_config_fc_after_link_up(hw);
1080 hw_dbg("Unable to establish link!!!\n");
1088 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1089 * @hw: pointer to the HW structure
1091 * Calls the PHY setup function to force speed and duplex. Clears the
1092 * auto-crossover to force MDI manually. Waits for link and returns
1093 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1095 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1097 struct e1000_phy_info *phy = &hw->phy;
1102 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1106 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1108 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1112 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1113 * forced whenever speed and duplex are forced.
1115 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1119 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1120 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1122 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1126 hw_dbg("IGP PSCR: %X\n", phy_data);
1130 if (phy->autoneg_wait_to_complete) {
1131 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1133 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1138 hw_dbg("Link taking longer than expected.\n");
1141 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1151 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1152 * @hw: pointer to the HW structure
1154 * Calls the PHY setup function to force speed and duplex. Clears the
1155 * auto-crossover to force MDI manually. Resets the PHY to commit the
1156 * changes. If time expires while waiting for link up, we reset the DSP.
1157 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1158 * successful completion, else return corresponding error code.
1160 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1162 struct e1000_phy_info *phy = &hw->phy;
1167 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1168 if (phy->type != e1000_phy_i210) {
1169 /* Clear Auto-Crossover to force MDI manually. M88E1000
1170 * requires MDI forced whenever speed and duplex are forced.
1172 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1177 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1178 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1183 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1186 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1190 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1192 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1196 /* Reset the phy to commit changes. */
1197 ret_val = igb_phy_sw_reset(hw);
1201 if (phy->autoneg_wait_to_complete) {
1202 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1204 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1209 bool reset_dsp = true;
1211 switch (hw->phy.id) {
1212 case I347AT4_E_PHY_ID:
1213 case M88E1112_E_PHY_ID:
1218 if (hw->phy.type != e1000_phy_m88)
1223 hw_dbg("Link taking longer than expected.\n");
1225 /* We didn't get link.
1226 * Reset the DSP and cross our fingers.
1228 ret_val = phy->ops.write_reg(hw,
1229 M88E1000_PHY_PAGE_SELECT,
1233 ret_val = igb_phy_reset_dsp(hw);
1240 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1246 if (hw->phy.type != e1000_phy_m88 ||
1247 hw->phy.id == I347AT4_E_PHY_ID ||
1248 hw->phy.id == M88E1112_E_PHY_ID ||
1249 hw->phy.id == I210_I_PHY_ID)
1252 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1256 /* Resetting the phy means we need to re-force TX_CLK in the
1257 * Extended PHY Specific Control Register to 25MHz clock from
1258 * the reset value of 2.5MHz.
1260 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1261 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1265 /* In addition, we must re-enable CRS on Tx for both half and full
1268 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1272 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1273 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1280 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1281 * @hw: pointer to the HW structure
1282 * @phy_ctrl: pointer to current value of PHY_CONTROL
1284 * Forces speed and duplex on the PHY by doing the following: disable flow
1285 * control, force speed/duplex on the MAC, disable auto speed detection,
1286 * disable auto-negotiation, configure duplex, configure speed, configure
1287 * the collision distance, write configuration to CTRL register. The
1288 * caller must write to the PHY_CONTROL register for these settings to
1291 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1294 struct e1000_mac_info *mac = &hw->mac;
1297 /* Turn off flow control when forcing speed/duplex */
1298 hw->fc.current_mode = e1000_fc_none;
1300 /* Force speed/duplex on the mac */
1301 ctrl = rd32(E1000_CTRL);
1302 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1303 ctrl &= ~E1000_CTRL_SPD_SEL;
1305 /* Disable Auto Speed Detection */
1306 ctrl &= ~E1000_CTRL_ASDE;
1308 /* Disable autoneg on the phy */
1309 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1311 /* Forcing Full or Half Duplex? */
1312 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1313 ctrl &= ~E1000_CTRL_FD;
1314 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1315 hw_dbg("Half Duplex\n");
1317 ctrl |= E1000_CTRL_FD;
1318 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1319 hw_dbg("Full Duplex\n");
1322 /* Forcing 10mb or 100mb? */
1323 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1324 ctrl |= E1000_CTRL_SPD_100;
1325 *phy_ctrl |= MII_CR_SPEED_100;
1326 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1327 hw_dbg("Forcing 100mb\n");
1329 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1330 *phy_ctrl |= MII_CR_SPEED_10;
1331 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1332 hw_dbg("Forcing 10mb\n");
1335 igb_config_collision_dist(hw);
1337 wr32(E1000_CTRL, ctrl);
1341 * igb_set_d3_lplu_state - Sets low power link up state for D3
1342 * @hw: pointer to the HW structure
1343 * @active: boolean used to enable/disable lplu
1345 * Success returns 0, Failure returns 1
1347 * The low power link up (lplu) state is set to the power management level D3
1348 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1349 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1350 * is used during Dx states where the power conservation is most important.
1351 * During driver activity, SmartSpeed should be enabled so performance is
1354 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1356 struct e1000_phy_info *phy = &hw->phy;
1360 if (!(hw->phy.ops.read_reg))
1363 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1368 data &= ~IGP02E1000_PM_D3_LPLU;
1369 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1373 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1374 * during Dx states where the power conservation is most
1375 * important. During driver activity we should enable
1376 * SmartSpeed, so performance is maintained.
1378 if (phy->smart_speed == e1000_smart_speed_on) {
1379 ret_val = phy->ops.read_reg(hw,
1380 IGP01E1000_PHY_PORT_CONFIG,
1385 data |= IGP01E1000_PSCFR_SMART_SPEED;
1386 ret_val = phy->ops.write_reg(hw,
1387 IGP01E1000_PHY_PORT_CONFIG,
1391 } else if (phy->smart_speed == e1000_smart_speed_off) {
1392 ret_val = phy->ops.read_reg(hw,
1393 IGP01E1000_PHY_PORT_CONFIG,
1398 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1399 ret_val = phy->ops.write_reg(hw,
1400 IGP01E1000_PHY_PORT_CONFIG,
1405 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1406 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1407 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1408 data |= IGP02E1000_PM_D3_LPLU;
1409 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1414 /* When LPLU is enabled, we should disable SmartSpeed */
1415 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1420 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1421 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1430 * igb_check_downshift - Checks whether a downshift in speed occurred
1431 * @hw: pointer to the HW structure
1433 * Success returns 0, Failure returns 1
1435 * A downshift is detected by querying the PHY link health.
1437 s32 igb_check_downshift(struct e1000_hw *hw)
1439 struct e1000_phy_info *phy = &hw->phy;
1441 u16 phy_data, offset, mask;
1443 switch (phy->type) {
1444 case e1000_phy_i210:
1446 case e1000_phy_gg82563:
1447 offset = M88E1000_PHY_SPEC_STATUS;
1448 mask = M88E1000_PSSR_DOWNSHIFT;
1450 case e1000_phy_igp_2:
1452 case e1000_phy_igp_3:
1453 offset = IGP01E1000_PHY_LINK_HEALTH;
1454 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1457 /* speed downshift not supported */
1458 phy->speed_downgraded = false;
1463 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1466 phy->speed_downgraded = (phy_data & mask) ? true : false;
1473 * igb_check_polarity_m88 - Checks the polarity.
1474 * @hw: pointer to the HW structure
1476 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1478 * Polarity is determined based on the PHY specific status register.
1480 s32 igb_check_polarity_m88(struct e1000_hw *hw)
1482 struct e1000_phy_info *phy = &hw->phy;
1486 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1489 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1490 ? e1000_rev_polarity_reversed
1491 : e1000_rev_polarity_normal;
1497 * igb_check_polarity_igp - Checks the polarity.
1498 * @hw: pointer to the HW structure
1500 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1502 * Polarity is determined based on the PHY port status register, and the
1503 * current speed (since there is no polarity at 100Mbps).
1505 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1507 struct e1000_phy_info *phy = &hw->phy;
1509 u16 data, offset, mask;
1511 /* Polarity is determined based on the speed of
1514 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1518 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1519 IGP01E1000_PSSR_SPEED_1000MBPS) {
1520 offset = IGP01E1000_PHY_PCS_INIT_REG;
1521 mask = IGP01E1000_PHY_POLARITY_MASK;
1523 /* This really only applies to 10Mbps since
1524 * there is no polarity for 100Mbps (always 0).
1526 offset = IGP01E1000_PHY_PORT_STATUS;
1527 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1530 ret_val = phy->ops.read_reg(hw, offset, &data);
1533 phy->cable_polarity = (data & mask)
1534 ? e1000_rev_polarity_reversed
1535 : e1000_rev_polarity_normal;
1542 * igb_wait_autoneg - Wait for auto-neg completion
1543 * @hw: pointer to the HW structure
1545 * Waits for auto-negotiation to complete or for the auto-negotiation time
1546 * limit to expire, which ever happens first.
1548 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1553 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1554 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1555 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1558 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1561 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1566 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1573 * igb_phy_has_link - Polls PHY for link
1574 * @hw: pointer to the HW structure
1575 * @iterations: number of times to poll for link
1576 * @usec_interval: delay between polling attempts
1577 * @success: pointer to whether polling was successful or not
1579 * Polls the PHY status register for link, 'iterations' number of times.
1581 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1582 u32 usec_interval, bool *success)
1587 for (i = 0; i < iterations; i++) {
1588 /* Some PHYs require the PHY_STATUS register to be read
1589 * twice due to the link bit being sticky. No harm doing
1590 * it across the board.
1592 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1594 /* If the first read fails, another entity may have
1595 * ownership of the resources, wait and try again to
1596 * see if they have relinquished the resources yet.
1598 udelay(usec_interval);
1600 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1603 if (phy_status & MII_SR_LINK_STATUS)
1605 if (usec_interval >= 1000)
1606 mdelay(usec_interval/1000);
1608 udelay(usec_interval);
1611 *success = (i < iterations) ? true : false;
1617 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1618 * @hw: pointer to the HW structure
1620 * Reads the PHY specific status register to retrieve the cable length
1621 * information. The cable length is determined by averaging the minimum and
1622 * maximum values to get the "average" cable length. The m88 PHY has four
1623 * possible cable length values, which are:
1624 * Register Value Cable Length
1628 * 3 110 - 140 meters
1631 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1633 struct e1000_phy_info *phy = &hw->phy;
1635 u16 phy_data, index;
1637 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1641 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1642 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1643 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1644 ret_val = -E1000_ERR_PHY;
1648 phy->min_cable_length = e1000_m88_cable_length_table[index];
1649 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1651 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1657 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1659 struct e1000_phy_info *phy = &hw->phy;
1661 u16 phy_data, phy_data2, index, default_page, is_cm;
1663 switch (hw->phy.id) {
1665 /* Get cable length from PHY Cable Diagnostics Control Reg */
1666 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1667 (I347AT4_PCDL + phy->addr),
1672 /* Check if the unit of cable length is meters or cm */
1673 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1674 I347AT4_PCDC, &phy_data2);
1678 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1680 /* Populate the phy structure with cable length in meters */
1681 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1682 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1683 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1685 case M88E1545_E_PHY_ID:
1686 case I347AT4_E_PHY_ID:
1687 /* Remember the original page select and set it to 7 */
1688 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1693 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1697 /* Get cable length from PHY Cable Diagnostics Control Reg */
1698 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1703 /* Check if the unit of cable length is meters or cm */
1704 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1708 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1710 /* Populate the phy structure with cable length in meters */
1711 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1712 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1713 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1715 /* Reset the page selec to its original value */
1716 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1721 case M88E1112_E_PHY_ID:
1722 /* Remember the original page select and set it to 5 */
1723 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1728 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1732 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1737 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1738 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1739 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1740 ret_val = -E1000_ERR_PHY;
1744 phy->min_cable_length = e1000_m88_cable_length_table[index];
1745 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1747 phy->cable_length = (phy->min_cable_length +
1748 phy->max_cable_length) / 2;
1750 /* Reset the page select to its original value */
1751 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1758 ret_val = -E1000_ERR_PHY;
1767 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1768 * @hw: pointer to the HW structure
1770 * The automatic gain control (agc) normalizes the amplitude of the
1771 * received signal, adjusting for the attenuation produced by the
1772 * cable. By reading the AGC registers, which represent the
1773 * combination of coarse and fine gain value, the value can be put
1774 * into a lookup table to obtain the approximate cable length
1777 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1779 struct e1000_phy_info *phy = &hw->phy;
1781 u16 phy_data, i, agc_value = 0;
1782 u16 cur_agc_index, max_agc_index = 0;
1783 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1784 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1785 IGP02E1000_PHY_AGC_A,
1786 IGP02E1000_PHY_AGC_B,
1787 IGP02E1000_PHY_AGC_C,
1788 IGP02E1000_PHY_AGC_D
1791 /* Read the AGC registers for all channels */
1792 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1793 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1797 /* Getting bits 15:9, which represent the combination of
1798 * coarse and fine gain values. The result is a number
1799 * that can be put into the lookup table to obtain the
1800 * approximate cable length.
1802 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1803 IGP02E1000_AGC_LENGTH_MASK;
1805 /* Array index bound check. */
1806 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1807 (cur_agc_index == 0)) {
1808 ret_val = -E1000_ERR_PHY;
1812 /* Remove min & max AGC values from calculation. */
1813 if (e1000_igp_2_cable_length_table[min_agc_index] >
1814 e1000_igp_2_cable_length_table[cur_agc_index])
1815 min_agc_index = cur_agc_index;
1816 if (e1000_igp_2_cable_length_table[max_agc_index] <
1817 e1000_igp_2_cable_length_table[cur_agc_index])
1818 max_agc_index = cur_agc_index;
1820 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1823 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1824 e1000_igp_2_cable_length_table[max_agc_index]);
1825 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1827 /* Calculate cable length with the error range of +/- 10 meters. */
1828 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1829 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1830 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1832 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1839 * igb_get_phy_info_m88 - Retrieve PHY information
1840 * @hw: pointer to the HW structure
1842 * Valid for only copper links. Read the PHY status register (sticky read)
1843 * to verify that link is up. Read the PHY special control register to
1844 * determine the polarity and 10base-T extended distance. Read the PHY
1845 * special status register to determine MDI/MDIx and current speed. If
1846 * speed is 1000, then determine cable length, local and remote receiver.
1848 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1850 struct e1000_phy_info *phy = &hw->phy;
1855 if (phy->media_type != e1000_media_type_copper) {
1856 hw_dbg("Phy info is only valid for copper media\n");
1857 ret_val = -E1000_ERR_CONFIG;
1861 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1866 hw_dbg("Phy info is only valid if link is up\n");
1867 ret_val = -E1000_ERR_CONFIG;
1871 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1875 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1878 ret_val = igb_check_polarity_m88(hw);
1882 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1886 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1888 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1889 ret_val = phy->ops.get_cable_length(hw);
1893 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1897 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1898 ? e1000_1000t_rx_status_ok
1899 : e1000_1000t_rx_status_not_ok;
1901 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1902 ? e1000_1000t_rx_status_ok
1903 : e1000_1000t_rx_status_not_ok;
1905 /* Set values to "undefined" */
1906 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1907 phy->local_rx = e1000_1000t_rx_status_undefined;
1908 phy->remote_rx = e1000_1000t_rx_status_undefined;
1916 * igb_get_phy_info_igp - Retrieve igp PHY information
1917 * @hw: pointer to the HW structure
1919 * Read PHY status to determine if link is up. If link is up, then
1920 * set/determine 10base-T extended distance and polarity correction. Read
1921 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1922 * determine on the cable length, local and remote receiver.
1924 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1926 struct e1000_phy_info *phy = &hw->phy;
1931 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1936 hw_dbg("Phy info is only valid if link is up\n");
1937 ret_val = -E1000_ERR_CONFIG;
1941 phy->polarity_correction = true;
1943 ret_val = igb_check_polarity_igp(hw);
1947 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1951 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
1953 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1954 IGP01E1000_PSSR_SPEED_1000MBPS) {
1955 ret_val = phy->ops.get_cable_length(hw);
1959 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
1963 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1964 ? e1000_1000t_rx_status_ok
1965 : e1000_1000t_rx_status_not_ok;
1967 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1968 ? e1000_1000t_rx_status_ok
1969 : e1000_1000t_rx_status_not_ok;
1971 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1972 phy->local_rx = e1000_1000t_rx_status_undefined;
1973 phy->remote_rx = e1000_1000t_rx_status_undefined;
1981 * igb_phy_sw_reset - PHY software reset
1982 * @hw: pointer to the HW structure
1984 * Does a software reset of the PHY by reading the PHY control register and
1985 * setting/write the control register reset bit to the PHY.
1987 s32 igb_phy_sw_reset(struct e1000_hw *hw)
1992 if (!(hw->phy.ops.read_reg))
1995 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1999 phy_ctrl |= MII_CR_RESET;
2000 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2011 * igb_phy_hw_reset - PHY hardware reset
2012 * @hw: pointer to the HW structure
2014 * Verify the reset block is not blocking us from resetting. Acquire
2015 * semaphore (if necessary) and read/set/write the device control reset
2016 * bit in the PHY. Wait the appropriate delay time for the device to
2017 * reset and relase the semaphore (if necessary).
2019 s32 igb_phy_hw_reset(struct e1000_hw *hw)
2021 struct e1000_phy_info *phy = &hw->phy;
2025 ret_val = igb_check_reset_block(hw);
2031 ret_val = phy->ops.acquire(hw);
2035 ctrl = rd32(E1000_CTRL);
2036 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2039 udelay(phy->reset_delay_us);
2041 wr32(E1000_CTRL, ctrl);
2046 phy->ops.release(hw);
2048 ret_val = phy->ops.get_cfg_done(hw);
2055 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2056 * @hw: pointer to the HW structure
2058 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2060 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2062 hw_dbg("Running IGP 3 PHY init script\n");
2064 /* PHY init IGP 3 */
2065 /* Enable rise/fall, 10-mode work in class-A */
2066 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2067 /* Remove all caps from Replica path filter */
2068 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2069 /* Bias trimming for ADC, AFE and Driver (Default) */
2070 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2071 /* Increase Hybrid poly bias */
2072 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2073 /* Add 4% to TX amplitude in Giga mode */
2074 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2075 /* Disable trimming (TTT) */
2076 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2077 /* Poly DC correction to 94.6% + 2% for all channels */
2078 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2079 /* ABS DC correction to 95.9% */
2080 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2081 /* BG temp curve trim */
2082 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2083 /* Increasing ADC OPAMP stage 1 currents to max */
2084 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2085 /* Force 1000 ( required for enabling PHY regs configuration) */
2086 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2087 /* Set upd_freq to 6 */
2088 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2090 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2091 /* Disable adaptive fixed FFE (Default) */
2092 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2093 /* Enable FFE hysteresis */
2094 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2095 /* Fixed FFE for short cable lengths */
2096 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2097 /* Fixed FFE for medium cable lengths */
2098 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2099 /* Fixed FFE for long cable lengths */
2100 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2101 /* Enable Adaptive Clip Threshold */
2102 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2103 /* AHT reset limit to 1 */
2104 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2105 /* Set AHT master delay to 127 msec */
2106 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2107 /* Set scan bits for AHT */
2108 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2109 /* Set AHT Preset bits */
2110 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2111 /* Change integ_factor of channel A to 3 */
2112 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2113 /* Change prop_factor of channels BCD to 8 */
2114 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2115 /* Change cg_icount + enable integbp for channels BCD */
2116 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2117 /* Change cg_icount + enable integbp + change prop_factor_master
2118 * to 8 for channel A
2120 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2121 /* Disable AHT in Slave mode on channel A */
2122 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2123 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2126 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2127 /* Enable restart AN on an1000_dis change */
2128 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2129 /* Enable wh_fifo read clock in 10/100 modes */
2130 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2131 /* Restart AN, Speed selection is 1000 */
2132 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2138 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2139 * @hw: pointer to the HW structure
2141 * In the case of a PHY power down to save power, or to turn off link during a
2142 * driver unload, restore the link to previous settings.
2144 void igb_power_up_phy_copper(struct e1000_hw *hw)
2149 /* The PHY will retain its settings across a power down/up cycle */
2150 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2151 mii_reg &= ~MII_CR_POWER_DOWN;
2152 if (hw->phy.type == e1000_phy_i210) {
2153 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2154 power_reg &= ~GS40G_CS_POWER_DOWN;
2155 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2157 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2161 * igb_power_down_phy_copper - Power down copper PHY
2162 * @hw: pointer to the HW structure
2164 * Power down PHY to save power when interface is down and wake on lan
2167 void igb_power_down_phy_copper(struct e1000_hw *hw)
2172 /* The PHY will retain its settings across a power down/up cycle */
2173 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2174 mii_reg |= MII_CR_POWER_DOWN;
2176 /* i210 Phy requires an additional bit for power up/down */
2177 if (hw->phy.type == e1000_phy_i210) {
2178 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2179 power_reg |= GS40G_CS_POWER_DOWN;
2180 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2182 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2187 * igb_check_polarity_82580 - Checks the polarity.
2188 * @hw: pointer to the HW structure
2190 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2192 * Polarity is determined based on the PHY specific status register.
2194 static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2196 struct e1000_phy_info *phy = &hw->phy;
2201 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2204 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2205 ? e1000_rev_polarity_reversed
2206 : e1000_rev_polarity_normal;
2212 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2213 * @hw: pointer to the HW structure
2215 * Calls the PHY setup function to force speed and duplex. Clears the
2216 * auto-crossover to force MDI manually. Waits for link and returns
2217 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2219 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2221 struct e1000_phy_info *phy = &hw->phy;
2226 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2230 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2232 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2236 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2237 * forced whenever speed and duplex are forced.
2239 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2243 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2245 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2249 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2253 if (phy->autoneg_wait_to_complete) {
2254 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2256 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2261 hw_dbg("Link taking longer than expected.\n");
2264 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2274 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2275 * @hw: pointer to the HW structure
2277 * Read PHY status to determine if link is up. If link is up, then
2278 * set/determine 10base-T extended distance and polarity correction. Read
2279 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2280 * determine on the cable length, local and remote receiver.
2282 s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2284 struct e1000_phy_info *phy = &hw->phy;
2289 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2294 hw_dbg("Phy info is only valid if link is up\n");
2295 ret_val = -E1000_ERR_CONFIG;
2299 phy->polarity_correction = true;
2301 ret_val = igb_check_polarity_82580(hw);
2305 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2309 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2311 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2312 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2313 ret_val = hw->phy.ops.get_cable_length(hw);
2317 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2321 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2322 ? e1000_1000t_rx_status_ok
2323 : e1000_1000t_rx_status_not_ok;
2325 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2326 ? e1000_1000t_rx_status_ok
2327 : e1000_1000t_rx_status_not_ok;
2329 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2330 phy->local_rx = e1000_1000t_rx_status_undefined;
2331 phy->remote_rx = e1000_1000t_rx_status_undefined;
2339 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2340 * @hw: pointer to the HW structure
2342 * Reads the diagnostic status register and verifies result is valid before
2343 * placing it in the phy_cable_length field.
2345 s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2347 struct e1000_phy_info *phy = &hw->phy;
2349 u16 phy_data, length;
2351 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2355 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2356 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2358 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2359 ret_val = -E1000_ERR_PHY;
2361 phy->cable_length = length;
2368 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2369 * @hw: pointer to the HW structure
2370 * @offset: lower half is register offset to write to
2371 * upper half is page to use.
2372 * @data: data to write at register offset
2374 * Acquires semaphore, if necessary, then writes the data to PHY register
2375 * at the offset. Release any acquired semaphores before exiting.
2377 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2380 u16 page = offset >> GS40G_PAGE_SHIFT;
2382 offset = offset & GS40G_OFFSET_MASK;
2383 ret_val = hw->phy.ops.acquire(hw);
2387 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2390 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2393 hw->phy.ops.release(hw);
2398 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2399 * @hw: pointer to the HW structure
2400 * @offset: lower half is register offset to read to
2401 * upper half is page to use.
2402 * @data: data to read at register offset
2404 * Acquires semaphore, if necessary, then reads the data in the PHY register
2405 * at the offset. Release any acquired semaphores before exiting.
2407 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2410 u16 page = offset >> GS40G_PAGE_SHIFT;
2412 offset = offset & GS40G_OFFSET_MASK;
2413 ret_val = hw->phy.ops.acquire(hw);
2417 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2420 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2423 hw->phy.ops.release(hw);
2428 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2429 * @hw: pointer to the HW structure
2431 * Sets up Master/slave mode
2433 static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2438 /* Resolve Master/Slave mode */
2439 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2443 /* load defaults for future use */
2444 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2445 ((phy_data & CR_1000T_MS_VALUE) ?
2446 e1000_ms_force_master :
2447 e1000_ms_force_slave) : e1000_ms_auto;
2449 switch (hw->phy.ms_type) {
2450 case e1000_ms_force_master:
2451 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2453 case e1000_ms_force_slave:
2454 phy_data |= CR_1000T_MS_ENABLE;
2455 phy_data &= ~(CR_1000T_MS_VALUE);
2458 phy_data &= ~CR_1000T_MS_ENABLE;
2464 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);