1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 /* ethtool support for igb */
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/highmem.h>
45 char stat_string[ETH_GSTRING_LEN];
50 #define IGB_STAT(_name, _stat) { \
51 .stat_string = _name, \
52 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
53 .stat_offset = offsetof(struct igb_adapter, _stat) \
55 static const struct igb_stats igb_gstrings_stats[] = {
56 IGB_STAT("rx_packets", stats.gprc),
57 IGB_STAT("tx_packets", stats.gptc),
58 IGB_STAT("rx_bytes", stats.gorc),
59 IGB_STAT("tx_bytes", stats.gotc),
60 IGB_STAT("rx_broadcast", stats.bprc),
61 IGB_STAT("tx_broadcast", stats.bptc),
62 IGB_STAT("rx_multicast", stats.mprc),
63 IGB_STAT("tx_multicast", stats.mptc),
64 IGB_STAT("multicast", stats.mprc),
65 IGB_STAT("collisions", stats.colc),
66 IGB_STAT("rx_crc_errors", stats.crcerrs),
67 IGB_STAT("rx_no_buffer_count", stats.rnbc),
68 IGB_STAT("rx_missed_errors", stats.mpc),
69 IGB_STAT("tx_aborted_errors", stats.ecol),
70 IGB_STAT("tx_carrier_errors", stats.tncrs),
71 IGB_STAT("tx_window_errors", stats.latecol),
72 IGB_STAT("tx_abort_late_coll", stats.latecol),
73 IGB_STAT("tx_deferred_ok", stats.dc),
74 IGB_STAT("tx_single_coll_ok", stats.scc),
75 IGB_STAT("tx_multi_coll_ok", stats.mcc),
76 IGB_STAT("tx_timeout_count", tx_timeout_count),
77 IGB_STAT("rx_long_length_errors", stats.roc),
78 IGB_STAT("rx_short_length_errors", stats.ruc),
79 IGB_STAT("rx_align_errors", stats.algnerrc),
80 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
81 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
82 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
83 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
84 IGB_STAT("tx_flow_control_xon", stats.xontxc),
85 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
86 IGB_STAT("rx_long_byte_count", stats.gorc),
87 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
88 IGB_STAT("tx_smbus", stats.mgptc),
89 IGB_STAT("rx_smbus", stats.mgprc),
90 IGB_STAT("dropped_smbus", stats.mgpdc),
91 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
92 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
93 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
94 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
95 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
96 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
99 #define IGB_NETDEV_STAT(_net_stat) { \
100 .stat_string = __stringify(_net_stat), \
101 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
102 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
104 static const struct igb_stats igb_gstrings_net_stats[] = {
105 IGB_NETDEV_STAT(rx_errors),
106 IGB_NETDEV_STAT(tx_errors),
107 IGB_NETDEV_STAT(tx_dropped),
108 IGB_NETDEV_STAT(rx_length_errors),
109 IGB_NETDEV_STAT(rx_over_errors),
110 IGB_NETDEV_STAT(rx_frame_errors),
111 IGB_NETDEV_STAT(rx_fifo_errors),
112 IGB_NETDEV_STAT(tx_fifo_errors),
113 IGB_NETDEV_STAT(tx_heartbeat_errors)
116 #define IGB_GLOBAL_STATS_LEN \
117 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
118 #define IGB_NETDEV_STATS_LEN \
119 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
120 #define IGB_RX_QUEUE_STATS_LEN \
121 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
123 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
125 #define IGB_QUEUE_STATS_LEN \
126 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
127 IGB_RX_QUEUE_STATS_LEN) + \
128 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
129 IGB_TX_QUEUE_STATS_LEN))
130 #define IGB_STATS_LEN \
131 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
133 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
134 "Register test (offline)", "Eeprom test (offline)",
135 "Interrupt test (offline)", "Loopback test (offline)",
136 "Link test (on/offline)"
138 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
140 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
142 struct igb_adapter *adapter = netdev_priv(netdev);
143 struct e1000_hw *hw = &adapter->hw;
146 if (hw->phy.media_type == e1000_media_type_copper) {
148 ecmd->supported = (SUPPORTED_10baseT_Half |
149 SUPPORTED_10baseT_Full |
150 SUPPORTED_100baseT_Half |
151 SUPPORTED_100baseT_Full |
152 SUPPORTED_1000baseT_Full|
156 ecmd->advertising = ADVERTISED_TP;
158 if (hw->mac.autoneg == 1) {
159 ecmd->advertising |= ADVERTISED_Autoneg;
160 /* the e1000 autoneg seems to match ethtool nicely */
161 ecmd->advertising |= hw->phy.autoneg_advertised;
164 if (hw->mac.autoneg != 1)
165 ecmd->advertising &= ~(ADVERTISED_Pause |
166 ADVERTISED_Asym_Pause);
168 if (hw->fc.requested_mode == e1000_fc_full)
169 ecmd->advertising |= ADVERTISED_Pause;
170 else if (hw->fc.requested_mode == e1000_fc_rx_pause)
171 ecmd->advertising |= (ADVERTISED_Pause |
172 ADVERTISED_Asym_Pause);
173 else if (hw->fc.requested_mode == e1000_fc_tx_pause)
174 ecmd->advertising |= ADVERTISED_Asym_Pause;
176 ecmd->advertising &= ~(ADVERTISED_Pause |
177 ADVERTISED_Asym_Pause);
179 ecmd->port = PORT_TP;
180 ecmd->phy_address = hw->phy.addr;
182 ecmd->supported = (SUPPORTED_1000baseT_Full |
186 ecmd->advertising = (ADVERTISED_1000baseT_Full |
191 ecmd->port = PORT_FIBRE;
194 ecmd->transceiver = XCVR_INTERNAL;
196 status = rd32(E1000_STATUS);
198 if (status & E1000_STATUS_LU) {
200 if ((status & E1000_STATUS_SPEED_1000) ||
201 hw->phy.media_type != e1000_media_type_copper)
202 ethtool_cmd_speed_set(ecmd, SPEED_1000);
203 else if (status & E1000_STATUS_SPEED_100)
204 ethtool_cmd_speed_set(ecmd, SPEED_100);
206 ethtool_cmd_speed_set(ecmd, SPEED_10);
208 if ((status & E1000_STATUS_FD) ||
209 hw->phy.media_type != e1000_media_type_copper)
210 ecmd->duplex = DUPLEX_FULL;
212 ecmd->duplex = DUPLEX_HALF;
214 ethtool_cmd_speed_set(ecmd, -1);
218 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
220 /* MDI-X => 2; MDI =>1; Invalid =>0 */
221 if (hw->phy.media_type == e1000_media_type_copper)
222 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
225 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
227 if (hw->phy.mdix == AUTO_ALL_MODES)
228 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
230 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
235 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
237 struct igb_adapter *adapter = netdev_priv(netdev);
238 struct e1000_hw *hw = &adapter->hw;
240 /* When SoL/IDER sessions are active, autoneg/speed/duplex
241 * cannot be changed */
242 if (igb_check_reset_block(hw)) {
243 dev_err(&adapter->pdev->dev,
244 "Cannot change link characteristics when SoL/IDER is active.\n");
249 * MDI setting is only allowed when autoneg enabled because
250 * some hardware doesn't allow MDI setting when speed or
253 if (ecmd->eth_tp_mdix_ctrl) {
254 if (hw->phy.media_type != e1000_media_type_copper)
257 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
258 (ecmd->autoneg != AUTONEG_ENABLE)) {
259 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
264 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
267 if (ecmd->autoneg == AUTONEG_ENABLE) {
269 hw->phy.autoneg_advertised = ecmd->advertising |
272 ecmd->advertising = hw->phy.autoneg_advertised;
273 if (adapter->fc_autoneg)
274 hw->fc.requested_mode = e1000_fc_default;
276 u32 speed = ethtool_cmd_speed(ecmd);
277 /* calling this overrides forced MDI setting */
278 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
279 clear_bit(__IGB_RESETTING, &adapter->state);
284 /* MDI-X => 2; MDI => 1; Auto => 3 */
285 if (ecmd->eth_tp_mdix_ctrl) {
287 * fix up the value for auto (3 => 0) as zero is mapped
290 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
291 hw->phy.mdix = AUTO_ALL_MODES;
293 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
297 if (netif_running(adapter->netdev)) {
303 clear_bit(__IGB_RESETTING, &adapter->state);
307 static u32 igb_get_link(struct net_device *netdev)
309 struct igb_adapter *adapter = netdev_priv(netdev);
310 struct e1000_mac_info *mac = &adapter->hw.mac;
313 * If the link is not reported up to netdev, interrupts are disabled,
314 * and so the physical link state may have changed since we last
315 * looked. Set get_link_status to make sure that the true link
316 * state is interrogated, rather than pulling a cached and possibly
317 * stale link state from the driver.
319 if (!netif_carrier_ok(netdev))
320 mac->get_link_status = 1;
322 return igb_has_link(adapter);
325 static void igb_get_pauseparam(struct net_device *netdev,
326 struct ethtool_pauseparam *pause)
328 struct igb_adapter *adapter = netdev_priv(netdev);
329 struct e1000_hw *hw = &adapter->hw;
332 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
334 if (hw->fc.current_mode == e1000_fc_rx_pause)
336 else if (hw->fc.current_mode == e1000_fc_tx_pause)
338 else if (hw->fc.current_mode == e1000_fc_full) {
344 static int igb_set_pauseparam(struct net_device *netdev,
345 struct ethtool_pauseparam *pause)
347 struct igb_adapter *adapter = netdev_priv(netdev);
348 struct e1000_hw *hw = &adapter->hw;
351 adapter->fc_autoneg = pause->autoneg;
353 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
356 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
357 hw->fc.requested_mode = e1000_fc_default;
358 if (netif_running(adapter->netdev)) {
365 if (pause->rx_pause && pause->tx_pause)
366 hw->fc.requested_mode = e1000_fc_full;
367 else if (pause->rx_pause && !pause->tx_pause)
368 hw->fc.requested_mode = e1000_fc_rx_pause;
369 else if (!pause->rx_pause && pause->tx_pause)
370 hw->fc.requested_mode = e1000_fc_tx_pause;
371 else if (!pause->rx_pause && !pause->tx_pause)
372 hw->fc.requested_mode = e1000_fc_none;
374 hw->fc.current_mode = hw->fc.requested_mode;
376 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
377 igb_force_mac_fc(hw) : igb_setup_link(hw));
380 clear_bit(__IGB_RESETTING, &adapter->state);
384 static u32 igb_get_msglevel(struct net_device *netdev)
386 struct igb_adapter *adapter = netdev_priv(netdev);
387 return adapter->msg_enable;
390 static void igb_set_msglevel(struct net_device *netdev, u32 data)
392 struct igb_adapter *adapter = netdev_priv(netdev);
393 adapter->msg_enable = data;
396 static int igb_get_regs_len(struct net_device *netdev)
398 #define IGB_REGS_LEN 739
399 return IGB_REGS_LEN * sizeof(u32);
402 static void igb_get_regs(struct net_device *netdev,
403 struct ethtool_regs *regs, void *p)
405 struct igb_adapter *adapter = netdev_priv(netdev);
406 struct e1000_hw *hw = &adapter->hw;
410 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
412 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
414 /* General Registers */
415 regs_buff[0] = rd32(E1000_CTRL);
416 regs_buff[1] = rd32(E1000_STATUS);
417 regs_buff[2] = rd32(E1000_CTRL_EXT);
418 regs_buff[3] = rd32(E1000_MDIC);
419 regs_buff[4] = rd32(E1000_SCTL);
420 regs_buff[5] = rd32(E1000_CONNSW);
421 regs_buff[6] = rd32(E1000_VET);
422 regs_buff[7] = rd32(E1000_LEDCTL);
423 regs_buff[8] = rd32(E1000_PBA);
424 regs_buff[9] = rd32(E1000_PBS);
425 regs_buff[10] = rd32(E1000_FRTIMER);
426 regs_buff[11] = rd32(E1000_TCPTIMER);
429 regs_buff[12] = rd32(E1000_EECD);
432 /* Reading EICS for EICR because they read the
433 * same but EICS does not clear on read */
434 regs_buff[13] = rd32(E1000_EICS);
435 regs_buff[14] = rd32(E1000_EICS);
436 regs_buff[15] = rd32(E1000_EIMS);
437 regs_buff[16] = rd32(E1000_EIMC);
438 regs_buff[17] = rd32(E1000_EIAC);
439 regs_buff[18] = rd32(E1000_EIAM);
440 /* Reading ICS for ICR because they read the
441 * same but ICS does not clear on read */
442 regs_buff[19] = rd32(E1000_ICS);
443 regs_buff[20] = rd32(E1000_ICS);
444 regs_buff[21] = rd32(E1000_IMS);
445 regs_buff[22] = rd32(E1000_IMC);
446 regs_buff[23] = rd32(E1000_IAC);
447 regs_buff[24] = rd32(E1000_IAM);
448 regs_buff[25] = rd32(E1000_IMIRVP);
451 regs_buff[26] = rd32(E1000_FCAL);
452 regs_buff[27] = rd32(E1000_FCAH);
453 regs_buff[28] = rd32(E1000_FCTTV);
454 regs_buff[29] = rd32(E1000_FCRTL);
455 regs_buff[30] = rd32(E1000_FCRTH);
456 regs_buff[31] = rd32(E1000_FCRTV);
459 regs_buff[32] = rd32(E1000_RCTL);
460 regs_buff[33] = rd32(E1000_RXCSUM);
461 regs_buff[34] = rd32(E1000_RLPML);
462 regs_buff[35] = rd32(E1000_RFCTL);
463 regs_buff[36] = rd32(E1000_MRQC);
464 regs_buff[37] = rd32(E1000_VT_CTL);
467 regs_buff[38] = rd32(E1000_TCTL);
468 regs_buff[39] = rd32(E1000_TCTL_EXT);
469 regs_buff[40] = rd32(E1000_TIPG);
470 regs_buff[41] = rd32(E1000_DTXCTL);
473 regs_buff[42] = rd32(E1000_WUC);
474 regs_buff[43] = rd32(E1000_WUFC);
475 regs_buff[44] = rd32(E1000_WUS);
476 regs_buff[45] = rd32(E1000_IPAV);
477 regs_buff[46] = rd32(E1000_WUPL);
480 regs_buff[47] = rd32(E1000_PCS_CFG0);
481 regs_buff[48] = rd32(E1000_PCS_LCTL);
482 regs_buff[49] = rd32(E1000_PCS_LSTAT);
483 regs_buff[50] = rd32(E1000_PCS_ANADV);
484 regs_buff[51] = rd32(E1000_PCS_LPAB);
485 regs_buff[52] = rd32(E1000_PCS_NPTX);
486 regs_buff[53] = rd32(E1000_PCS_LPABNP);
489 regs_buff[54] = adapter->stats.crcerrs;
490 regs_buff[55] = adapter->stats.algnerrc;
491 regs_buff[56] = adapter->stats.symerrs;
492 regs_buff[57] = adapter->stats.rxerrc;
493 regs_buff[58] = adapter->stats.mpc;
494 regs_buff[59] = adapter->stats.scc;
495 regs_buff[60] = adapter->stats.ecol;
496 regs_buff[61] = adapter->stats.mcc;
497 regs_buff[62] = adapter->stats.latecol;
498 regs_buff[63] = adapter->stats.colc;
499 regs_buff[64] = adapter->stats.dc;
500 regs_buff[65] = adapter->stats.tncrs;
501 regs_buff[66] = adapter->stats.sec;
502 regs_buff[67] = adapter->stats.htdpmc;
503 regs_buff[68] = adapter->stats.rlec;
504 regs_buff[69] = adapter->stats.xonrxc;
505 regs_buff[70] = adapter->stats.xontxc;
506 regs_buff[71] = adapter->stats.xoffrxc;
507 regs_buff[72] = adapter->stats.xofftxc;
508 regs_buff[73] = adapter->stats.fcruc;
509 regs_buff[74] = adapter->stats.prc64;
510 regs_buff[75] = adapter->stats.prc127;
511 regs_buff[76] = adapter->stats.prc255;
512 regs_buff[77] = adapter->stats.prc511;
513 regs_buff[78] = adapter->stats.prc1023;
514 regs_buff[79] = adapter->stats.prc1522;
515 regs_buff[80] = adapter->stats.gprc;
516 regs_buff[81] = adapter->stats.bprc;
517 regs_buff[82] = adapter->stats.mprc;
518 regs_buff[83] = adapter->stats.gptc;
519 regs_buff[84] = adapter->stats.gorc;
520 regs_buff[86] = adapter->stats.gotc;
521 regs_buff[88] = adapter->stats.rnbc;
522 regs_buff[89] = adapter->stats.ruc;
523 regs_buff[90] = adapter->stats.rfc;
524 regs_buff[91] = adapter->stats.roc;
525 regs_buff[92] = adapter->stats.rjc;
526 regs_buff[93] = adapter->stats.mgprc;
527 regs_buff[94] = adapter->stats.mgpdc;
528 regs_buff[95] = adapter->stats.mgptc;
529 regs_buff[96] = adapter->stats.tor;
530 regs_buff[98] = adapter->stats.tot;
531 regs_buff[100] = adapter->stats.tpr;
532 regs_buff[101] = adapter->stats.tpt;
533 regs_buff[102] = adapter->stats.ptc64;
534 regs_buff[103] = adapter->stats.ptc127;
535 regs_buff[104] = adapter->stats.ptc255;
536 regs_buff[105] = adapter->stats.ptc511;
537 regs_buff[106] = adapter->stats.ptc1023;
538 regs_buff[107] = adapter->stats.ptc1522;
539 regs_buff[108] = adapter->stats.mptc;
540 regs_buff[109] = adapter->stats.bptc;
541 regs_buff[110] = adapter->stats.tsctc;
542 regs_buff[111] = adapter->stats.iac;
543 regs_buff[112] = adapter->stats.rpthc;
544 regs_buff[113] = adapter->stats.hgptc;
545 regs_buff[114] = adapter->stats.hgorc;
546 regs_buff[116] = adapter->stats.hgotc;
547 regs_buff[118] = adapter->stats.lenerrs;
548 regs_buff[119] = adapter->stats.scvpc;
549 regs_buff[120] = adapter->stats.hrmpc;
551 for (i = 0; i < 4; i++)
552 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
553 for (i = 0; i < 4; i++)
554 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
555 for (i = 0; i < 4; i++)
556 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
557 for (i = 0; i < 4; i++)
558 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
559 for (i = 0; i < 4; i++)
560 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
561 for (i = 0; i < 4; i++)
562 regs_buff[141 + i] = rd32(E1000_RDH(i));
563 for (i = 0; i < 4; i++)
564 regs_buff[145 + i] = rd32(E1000_RDT(i));
565 for (i = 0; i < 4; i++)
566 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
568 for (i = 0; i < 10; i++)
569 regs_buff[153 + i] = rd32(E1000_EITR(i));
570 for (i = 0; i < 8; i++)
571 regs_buff[163 + i] = rd32(E1000_IMIR(i));
572 for (i = 0; i < 8; i++)
573 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
574 for (i = 0; i < 16; i++)
575 regs_buff[179 + i] = rd32(E1000_RAL(i));
576 for (i = 0; i < 16; i++)
577 regs_buff[195 + i] = rd32(E1000_RAH(i));
579 for (i = 0; i < 4; i++)
580 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
581 for (i = 0; i < 4; i++)
582 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
583 for (i = 0; i < 4; i++)
584 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
585 for (i = 0; i < 4; i++)
586 regs_buff[223 + i] = rd32(E1000_TDH(i));
587 for (i = 0; i < 4; i++)
588 regs_buff[227 + i] = rd32(E1000_TDT(i));
589 for (i = 0; i < 4; i++)
590 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
591 for (i = 0; i < 4; i++)
592 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
593 for (i = 0; i < 4; i++)
594 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
595 for (i = 0; i < 4; i++)
596 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
598 for (i = 0; i < 4; i++)
599 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
600 for (i = 0; i < 4; i++)
601 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
602 for (i = 0; i < 32; i++)
603 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
604 for (i = 0; i < 128; i++)
605 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
606 for (i = 0; i < 128; i++)
607 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
608 for (i = 0; i < 4; i++)
609 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
611 regs_buff[547] = rd32(E1000_TDFH);
612 regs_buff[548] = rd32(E1000_TDFT);
613 regs_buff[549] = rd32(E1000_TDFHS);
614 regs_buff[550] = rd32(E1000_TDFPC);
616 if (hw->mac.type > e1000_82580) {
617 regs_buff[551] = adapter->stats.o2bgptc;
618 regs_buff[552] = adapter->stats.b2ospc;
619 regs_buff[553] = adapter->stats.o2bspc;
620 regs_buff[554] = adapter->stats.b2ogprc;
623 if (hw->mac.type != e1000_82576)
625 for (i = 0; i < 12; i++)
626 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
627 for (i = 0; i < 4; i++)
628 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
629 for (i = 0; i < 12; i++)
630 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
631 for (i = 0; i < 12; i++)
632 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
633 for (i = 0; i < 12; i++)
634 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
635 for (i = 0; i < 12; i++)
636 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
637 for (i = 0; i < 12; i++)
638 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
639 for (i = 0; i < 12; i++)
640 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
642 for (i = 0; i < 12; i++)
643 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
644 for (i = 0; i < 12; i++)
645 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
646 for (i = 0; i < 12; i++)
647 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
648 for (i = 0; i < 12; i++)
649 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
650 for (i = 0; i < 12; i++)
651 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
652 for (i = 0; i < 12; i++)
653 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
654 for (i = 0; i < 12; i++)
655 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
656 for (i = 0; i < 12; i++)
657 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
660 static int igb_get_eeprom_len(struct net_device *netdev)
662 struct igb_adapter *adapter = netdev_priv(netdev);
663 return adapter->hw.nvm.word_size * 2;
666 static int igb_get_eeprom(struct net_device *netdev,
667 struct ethtool_eeprom *eeprom, u8 *bytes)
669 struct igb_adapter *adapter = netdev_priv(netdev);
670 struct e1000_hw *hw = &adapter->hw;
672 int first_word, last_word;
676 if (eeprom->len == 0)
679 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
681 first_word = eeprom->offset >> 1;
682 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
684 eeprom_buff = kmalloc(sizeof(u16) *
685 (last_word - first_word + 1), GFP_KERNEL);
689 if (hw->nvm.type == e1000_nvm_eeprom_spi)
690 ret_val = hw->nvm.ops.read(hw, first_word,
691 last_word - first_word + 1,
694 for (i = 0; i < last_word - first_word + 1; i++) {
695 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
702 /* Device's eeprom is always little-endian, word addressable */
703 for (i = 0; i < last_word - first_word + 1; i++)
704 le16_to_cpus(&eeprom_buff[i]);
706 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
713 static int igb_set_eeprom(struct net_device *netdev,
714 struct ethtool_eeprom *eeprom, u8 *bytes)
716 struct igb_adapter *adapter = netdev_priv(netdev);
717 struct e1000_hw *hw = &adapter->hw;
720 int max_len, first_word, last_word, ret_val = 0;
723 if (eeprom->len == 0)
726 if (hw->mac.type == e1000_i211)
729 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
732 max_len = hw->nvm.word_size * 2;
734 first_word = eeprom->offset >> 1;
735 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
736 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
740 ptr = (void *)eeprom_buff;
742 if (eeprom->offset & 1) {
743 /* need read/modify/write of first changed EEPROM word */
744 /* only the second byte of the word is being modified */
745 ret_val = hw->nvm.ops.read(hw, first_word, 1,
749 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
750 /* need read/modify/write of last changed EEPROM word */
751 /* only the first byte of the word is being modified */
752 ret_val = hw->nvm.ops.read(hw, last_word, 1,
753 &eeprom_buff[last_word - first_word]);
756 /* Device's eeprom is always little-endian, word addressable */
757 for (i = 0; i < last_word - first_word + 1; i++)
758 le16_to_cpus(&eeprom_buff[i]);
760 memcpy(ptr, bytes, eeprom->len);
762 for (i = 0; i < last_word - first_word + 1; i++)
763 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
765 ret_val = hw->nvm.ops.write(hw, first_word,
766 last_word - first_word + 1, eeprom_buff);
768 /* Update the checksum over the first part of the EEPROM if needed
769 * and flush shadow RAM for 82573 controllers */
770 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
771 hw->nvm.ops.update(hw);
773 igb_set_fw_version(adapter);
778 static void igb_get_drvinfo(struct net_device *netdev,
779 struct ethtool_drvinfo *drvinfo)
781 struct igb_adapter *adapter = netdev_priv(netdev);
783 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
784 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
787 * EEPROM image version # is reported as firmware version # for
790 strlcpy(drvinfo->fw_version, adapter->fw_version,
791 sizeof(drvinfo->fw_version));
792 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
793 sizeof(drvinfo->bus_info));
794 drvinfo->n_stats = IGB_STATS_LEN;
795 drvinfo->testinfo_len = IGB_TEST_LEN;
796 drvinfo->regdump_len = igb_get_regs_len(netdev);
797 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
800 static void igb_get_ringparam(struct net_device *netdev,
801 struct ethtool_ringparam *ring)
803 struct igb_adapter *adapter = netdev_priv(netdev);
805 ring->rx_max_pending = IGB_MAX_RXD;
806 ring->tx_max_pending = IGB_MAX_TXD;
807 ring->rx_pending = adapter->rx_ring_count;
808 ring->tx_pending = adapter->tx_ring_count;
811 static int igb_set_ringparam(struct net_device *netdev,
812 struct ethtool_ringparam *ring)
814 struct igb_adapter *adapter = netdev_priv(netdev);
815 struct igb_ring *temp_ring;
817 u16 new_rx_count, new_tx_count;
819 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
822 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
823 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
824 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
826 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
827 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
828 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
830 if ((new_tx_count == adapter->tx_ring_count) &&
831 (new_rx_count == adapter->rx_ring_count)) {
836 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
839 if (!netif_running(adapter->netdev)) {
840 for (i = 0; i < adapter->num_tx_queues; i++)
841 adapter->tx_ring[i]->count = new_tx_count;
842 for (i = 0; i < adapter->num_rx_queues; i++)
843 adapter->rx_ring[i]->count = new_rx_count;
844 adapter->tx_ring_count = new_tx_count;
845 adapter->rx_ring_count = new_rx_count;
849 if (adapter->num_tx_queues > adapter->num_rx_queues)
850 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
852 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
862 * We can't just free everything and then setup again,
863 * because the ISRs in MSI-X mode get passed pointers
864 * to the tx and rx ring structs.
866 if (new_tx_count != adapter->tx_ring_count) {
867 for (i = 0; i < adapter->num_tx_queues; i++) {
868 memcpy(&temp_ring[i], adapter->tx_ring[i],
869 sizeof(struct igb_ring));
871 temp_ring[i].count = new_tx_count;
872 err = igb_setup_tx_resources(&temp_ring[i]);
876 igb_free_tx_resources(&temp_ring[i]);
882 for (i = 0; i < adapter->num_tx_queues; i++) {
883 igb_free_tx_resources(adapter->tx_ring[i]);
885 memcpy(adapter->tx_ring[i], &temp_ring[i],
886 sizeof(struct igb_ring));
889 adapter->tx_ring_count = new_tx_count;
892 if (new_rx_count != adapter->rx_ring_count) {
893 for (i = 0; i < adapter->num_rx_queues; i++) {
894 memcpy(&temp_ring[i], adapter->rx_ring[i],
895 sizeof(struct igb_ring));
897 temp_ring[i].count = new_rx_count;
898 err = igb_setup_rx_resources(&temp_ring[i]);
902 igb_free_rx_resources(&temp_ring[i]);
909 for (i = 0; i < adapter->num_rx_queues; i++) {
910 igb_free_rx_resources(adapter->rx_ring[i]);
912 memcpy(adapter->rx_ring[i], &temp_ring[i],
913 sizeof(struct igb_ring));
916 adapter->rx_ring_count = new_rx_count;
922 clear_bit(__IGB_RESETTING, &adapter->state);
926 /* ethtool register test data */
927 struct igb_reg_test {
936 /* In the hardware, registers are laid out either singly, in arrays
937 * spaced 0x100 bytes apart, or in contiguous tables. We assume
938 * most tests take place on arrays or single registers (handled
939 * as a single-element array) and special-case the tables.
940 * Table tests are always pattern tests.
942 * We also make provision for some required setup steps by specifying
943 * registers to be written without any read-back testing.
946 #define PATTERN_TEST 1
947 #define SET_READ_TEST 2
948 #define WRITE_NO_TEST 3
949 #define TABLE32_TEST 4
950 #define TABLE64_TEST_LO 5
951 #define TABLE64_TEST_HI 6
954 static struct igb_reg_test reg_test_i210[] = {
955 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
956 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
957 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
958 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
959 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
960 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
961 /* RDH is read-only for i210, only test RDT. */
962 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
963 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
964 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
965 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
966 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
967 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
968 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
969 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
970 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
971 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
972 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
973 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
974 { E1000_RA, 0, 16, TABLE64_TEST_LO,
975 0xFFFFFFFF, 0xFFFFFFFF },
976 { E1000_RA, 0, 16, TABLE64_TEST_HI,
977 0x900FFFFF, 0xFFFFFFFF },
978 { E1000_MTA, 0, 128, TABLE32_TEST,
979 0xFFFFFFFF, 0xFFFFFFFF },
984 static struct igb_reg_test reg_test_i350[] = {
985 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
986 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
987 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
988 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
989 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
990 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
991 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
992 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
993 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
994 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
995 /* RDH is read-only for i350, only test RDT. */
996 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
997 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
998 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
999 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1000 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1001 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1002 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1003 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1004 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1005 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1006 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1007 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1008 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1009 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1010 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1011 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1012 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1013 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1014 0xFFFFFFFF, 0xFFFFFFFF },
1015 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1016 0xC3FFFFFF, 0xFFFFFFFF },
1017 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1018 0xFFFFFFFF, 0xFFFFFFFF },
1019 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1020 0xC3FFFFFF, 0xFFFFFFFF },
1021 { E1000_MTA, 0, 128, TABLE32_TEST,
1022 0xFFFFFFFF, 0xFFFFFFFF },
1026 /* 82580 reg test */
1027 static struct igb_reg_test reg_test_82580[] = {
1028 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1029 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1030 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1031 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1032 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1033 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1034 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1035 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1036 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1037 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1038 /* RDH is read-only for 82580, only test RDT. */
1039 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1040 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1041 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1042 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1043 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1044 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1045 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1046 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1047 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1048 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1049 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1050 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1051 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1052 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1053 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1054 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1055 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1056 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1057 0xFFFFFFFF, 0xFFFFFFFF },
1058 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1059 0x83FFFFFF, 0xFFFFFFFF },
1060 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1061 0xFFFFFFFF, 0xFFFFFFFF },
1062 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1063 0x83FFFFFF, 0xFFFFFFFF },
1064 { E1000_MTA, 0, 128, TABLE32_TEST,
1065 0xFFFFFFFF, 0xFFFFFFFF },
1069 /* 82576 reg test */
1070 static struct igb_reg_test reg_test_82576[] = {
1071 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1072 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1073 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1074 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1075 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1076 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1077 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1078 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1079 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1080 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1081 /* Enable all RX queues before testing. */
1082 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1083 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1084 /* RDH is read-only for 82576, only test RDT. */
1085 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1086 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1087 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1088 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1089 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1090 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1091 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1092 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1093 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1094 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1095 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1096 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1097 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1098 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1099 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1100 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1101 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1102 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1103 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1104 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1105 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1106 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1110 /* 82575 register test */
1111 static struct igb_reg_test reg_test_82575[] = {
1112 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1113 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1114 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1115 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1116 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1117 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1118 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1119 /* Enable all four RX queues before testing. */
1120 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1121 /* RDH is read-only for 82575, only test RDT. */
1122 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1123 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1124 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1125 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1126 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1127 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1128 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1129 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1130 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1131 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1132 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1133 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1134 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1135 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1136 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1137 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1141 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1142 int reg, u32 mask, u32 write)
1144 struct e1000_hw *hw = &adapter->hw;
1146 static const u32 _test[] =
1147 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1148 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1149 wr32(reg, (_test[pat] & write));
1150 val = rd32(reg) & mask;
1151 if (val != (_test[pat] & write & mask)) {
1152 dev_err(&adapter->pdev->dev,
1153 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1154 reg, val, (_test[pat] & write & mask));
1163 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1164 int reg, u32 mask, u32 write)
1166 struct e1000_hw *hw = &adapter->hw;
1168 wr32(reg, write & mask);
1170 if ((write & mask) != (val & mask)) {
1171 dev_err(&adapter->pdev->dev,
1172 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg,
1173 (val & mask), (write & mask));
1181 #define REG_PATTERN_TEST(reg, mask, write) \
1183 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1187 #define REG_SET_AND_CHECK(reg, mask, write) \
1189 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1193 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1195 struct e1000_hw *hw = &adapter->hw;
1196 struct igb_reg_test *test;
1197 u32 value, before, after;
1200 switch (adapter->hw.mac.type) {
1202 test = reg_test_i350;
1203 toggle = 0x7FEFF3FF;
1207 test = reg_test_i210;
1208 toggle = 0x7FEFF3FF;
1211 test = reg_test_82580;
1212 toggle = 0x7FEFF3FF;
1215 test = reg_test_82576;
1216 toggle = 0x7FFFF3FF;
1219 test = reg_test_82575;
1220 toggle = 0x7FFFF3FF;
1224 /* Because the status register is such a special case,
1225 * we handle it separately from the rest of the register
1226 * tests. Some bits are read-only, some toggle, and some
1227 * are writable on newer MACs.
1229 before = rd32(E1000_STATUS);
1230 value = (rd32(E1000_STATUS) & toggle);
1231 wr32(E1000_STATUS, toggle);
1232 after = rd32(E1000_STATUS) & toggle;
1233 if (value != after) {
1234 dev_err(&adapter->pdev->dev,
1235 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1240 /* restore previous status */
1241 wr32(E1000_STATUS, before);
1243 /* Perform the remainder of the register test, looping through
1244 * the test table until we either fail or reach the null entry.
1247 for (i = 0; i < test->array_len; i++) {
1248 switch (test->test_type) {
1250 REG_PATTERN_TEST(test->reg +
1251 (i * test->reg_offset),
1256 REG_SET_AND_CHECK(test->reg +
1257 (i * test->reg_offset),
1263 (adapter->hw.hw_addr + test->reg)
1264 + (i * test->reg_offset));
1267 REG_PATTERN_TEST(test->reg + (i * 4),
1271 case TABLE64_TEST_LO:
1272 REG_PATTERN_TEST(test->reg + (i * 8),
1276 case TABLE64_TEST_HI:
1277 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1290 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1294 /* Validate eeprom on all parts but i211 */
1295 if (adapter->hw.mac.type != e1000_i211) {
1296 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1303 static irqreturn_t igb_test_intr(int irq, void *data)
1305 struct igb_adapter *adapter = (struct igb_adapter *) data;
1306 struct e1000_hw *hw = &adapter->hw;
1308 adapter->test_icr |= rd32(E1000_ICR);
1313 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1315 struct e1000_hw *hw = &adapter->hw;
1316 struct net_device *netdev = adapter->netdev;
1317 u32 mask, ics_mask, i = 0, shared_int = true;
1318 u32 irq = adapter->pdev->irq;
1322 /* Hook up test interrupt handler just for this test */
1323 if (adapter->msix_entries) {
1324 if (request_irq(adapter->msix_entries[0].vector,
1325 igb_test_intr, 0, netdev->name, adapter)) {
1329 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1331 if (request_irq(irq,
1332 igb_test_intr, 0, netdev->name, adapter)) {
1336 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1337 netdev->name, adapter)) {
1339 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1340 netdev->name, adapter)) {
1344 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1345 (shared_int ? "shared" : "unshared"));
1347 /* Disable all the interrupts */
1348 wr32(E1000_IMC, ~0);
1352 /* Define all writable bits for ICS */
1353 switch (hw->mac.type) {
1355 ics_mask = 0x37F47EDD;
1358 ics_mask = 0x77D4FBFD;
1361 ics_mask = 0x77DCFED5;
1366 ics_mask = 0x77DCFED5;
1369 ics_mask = 0x7FFFFFFF;
1373 /* Test each interrupt */
1374 for (; i < 31; i++) {
1375 /* Interrupt to test */
1378 if (!(mask & ics_mask))
1382 /* Disable the interrupt to be reported in
1383 * the cause register and then force the same
1384 * interrupt and see if one gets posted. If
1385 * an interrupt was posted to the bus, the
1388 adapter->test_icr = 0;
1390 /* Flush any pending interrupts */
1391 wr32(E1000_ICR, ~0);
1393 wr32(E1000_IMC, mask);
1394 wr32(E1000_ICS, mask);
1398 if (adapter->test_icr & mask) {
1404 /* Enable the interrupt to be reported in
1405 * the cause register and then force the same
1406 * interrupt and see if one gets posted. If
1407 * an interrupt was not posted to the bus, the
1410 adapter->test_icr = 0;
1412 /* Flush any pending interrupts */
1413 wr32(E1000_ICR, ~0);
1415 wr32(E1000_IMS, mask);
1416 wr32(E1000_ICS, mask);
1420 if (!(adapter->test_icr & mask)) {
1426 /* Disable the other interrupts to be reported in
1427 * the cause register and then force the other
1428 * interrupts and see if any get posted. If
1429 * an interrupt was posted to the bus, the
1432 adapter->test_icr = 0;
1434 /* Flush any pending interrupts */
1435 wr32(E1000_ICR, ~0);
1437 wr32(E1000_IMC, ~mask);
1438 wr32(E1000_ICS, ~mask);
1442 if (adapter->test_icr & mask) {
1449 /* Disable all the interrupts */
1450 wr32(E1000_IMC, ~0);
1454 /* Unhook test interrupt handler */
1455 if (adapter->msix_entries)
1456 free_irq(adapter->msix_entries[0].vector, adapter);
1458 free_irq(irq, adapter);
1463 static void igb_free_desc_rings(struct igb_adapter *adapter)
1465 igb_free_tx_resources(&adapter->test_tx_ring);
1466 igb_free_rx_resources(&adapter->test_rx_ring);
1469 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1471 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1472 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1473 struct e1000_hw *hw = &adapter->hw;
1476 /* Setup Tx descriptor ring and Tx buffers */
1477 tx_ring->count = IGB_DEFAULT_TXD;
1478 tx_ring->dev = &adapter->pdev->dev;
1479 tx_ring->netdev = adapter->netdev;
1480 tx_ring->reg_idx = adapter->vfs_allocated_count;
1482 if (igb_setup_tx_resources(tx_ring)) {
1487 igb_setup_tctl(adapter);
1488 igb_configure_tx_ring(adapter, tx_ring);
1490 /* Setup Rx descriptor ring and Rx buffers */
1491 rx_ring->count = IGB_DEFAULT_RXD;
1492 rx_ring->dev = &adapter->pdev->dev;
1493 rx_ring->netdev = adapter->netdev;
1494 rx_ring->reg_idx = adapter->vfs_allocated_count;
1496 if (igb_setup_rx_resources(rx_ring)) {
1501 /* set the default queue to queue 0 of PF */
1502 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1504 /* enable receive ring */
1505 igb_setup_rctl(adapter);
1506 igb_configure_rx_ring(adapter, rx_ring);
1508 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1513 igb_free_desc_rings(adapter);
1517 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1519 struct e1000_hw *hw = &adapter->hw;
1521 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1522 igb_write_phy_reg(hw, 29, 0x001F);
1523 igb_write_phy_reg(hw, 30, 0x8FFC);
1524 igb_write_phy_reg(hw, 29, 0x001A);
1525 igb_write_phy_reg(hw, 30, 0x8FF0);
1528 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1530 struct e1000_hw *hw = &adapter->hw;
1533 hw->mac.autoneg = false;
1535 if (hw->phy.type == e1000_phy_m88) {
1536 if (hw->phy.id != I210_I_PHY_ID) {
1537 /* Auto-MDI/MDIX Off */
1538 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1539 /* reset to update Auto-MDI/MDIX */
1540 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1542 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1544 /* force 1000, set loopback */
1545 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1546 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1550 /* add small delay to avoid loopback test failure */
1553 /* force 1000, set loopback */
1554 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1556 /* Now set up the MAC to the same speed/duplex as the PHY. */
1557 ctrl_reg = rd32(E1000_CTRL);
1558 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1559 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1560 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1561 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1562 E1000_CTRL_FD | /* Force Duplex to FULL */
1563 E1000_CTRL_SLU); /* Set link up enable bit */
1565 if (hw->phy.type == e1000_phy_m88)
1566 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1568 wr32(E1000_CTRL, ctrl_reg);
1570 /* Disable the receiver on the PHY so when a cable is plugged in, the
1571 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1573 if (hw->phy.type == e1000_phy_m88)
1574 igb_phy_disable_receiver(adapter);
1580 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1582 return igb_integrated_phy_loopback(adapter);
1585 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1587 struct e1000_hw *hw = &adapter->hw;
1590 reg = rd32(E1000_CTRL_EXT);
1592 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1593 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1594 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1595 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1596 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1597 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1599 /* Enable DH89xxCC MPHY for near end loopback */
1600 reg = rd32(E1000_MPHY_ADDR_CTL);
1601 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1602 E1000_MPHY_PCS_CLK_REG_OFFSET;
1603 wr32(E1000_MPHY_ADDR_CTL, reg);
1605 reg = rd32(E1000_MPHY_DATA);
1606 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1607 wr32(E1000_MPHY_DATA, reg);
1610 reg = rd32(E1000_RCTL);
1611 reg |= E1000_RCTL_LBM_TCVR;
1612 wr32(E1000_RCTL, reg);
1614 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1616 reg = rd32(E1000_CTRL);
1617 reg &= ~(E1000_CTRL_RFCE |
1620 reg |= E1000_CTRL_SLU |
1622 wr32(E1000_CTRL, reg);
1624 /* Unset switch control to serdes energy detect */
1625 reg = rd32(E1000_CONNSW);
1626 reg &= ~E1000_CONNSW_ENRGSRC;
1627 wr32(E1000_CONNSW, reg);
1629 /* Unset sigdetect for SERDES loopback on
1630 * 82580 and i350 devices.
1632 switch (hw->mac.type) {
1635 reg = rd32(E1000_PCS_CFG0);
1636 reg |= E1000_PCS_CFG_IGN_SD;
1637 wr32(E1000_PCS_CFG0, reg);
1643 /* Set PCS register for forced speed */
1644 reg = rd32(E1000_PCS_LCTL);
1645 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1646 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1647 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1648 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1649 E1000_PCS_LCTL_FSD | /* Force Speed */
1650 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1651 wr32(E1000_PCS_LCTL, reg);
1656 return igb_set_phy_loopback(adapter);
1659 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1661 struct e1000_hw *hw = &adapter->hw;
1665 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1666 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1667 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1668 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1671 /* Disable near end loopback on DH89xxCC */
1672 reg = rd32(E1000_MPHY_ADDR_CTL);
1673 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1674 E1000_MPHY_PCS_CLK_REG_OFFSET;
1675 wr32(E1000_MPHY_ADDR_CTL, reg);
1677 reg = rd32(E1000_MPHY_DATA);
1678 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1679 wr32(E1000_MPHY_DATA, reg);
1682 rctl = rd32(E1000_RCTL);
1683 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1684 wr32(E1000_RCTL, rctl);
1686 hw->mac.autoneg = true;
1687 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1688 if (phy_reg & MII_CR_LOOPBACK) {
1689 phy_reg &= ~MII_CR_LOOPBACK;
1690 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1691 igb_phy_sw_reset(hw);
1695 static void igb_create_lbtest_frame(struct sk_buff *skb,
1696 unsigned int frame_size)
1698 memset(skb->data, 0xFF, frame_size);
1700 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1701 memset(&skb->data[frame_size + 10], 0xBE, 1);
1702 memset(&skb->data[frame_size + 12], 0xAF, 1);
1705 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1706 unsigned int frame_size)
1708 unsigned char *data;
1713 data = kmap(rx_buffer->page);
1715 if (data[3] != 0xFF ||
1716 data[frame_size + 10] != 0xBE ||
1717 data[frame_size + 12] != 0xAF)
1720 kunmap(rx_buffer->page);
1725 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1726 struct igb_ring *tx_ring,
1729 union e1000_adv_rx_desc *rx_desc;
1730 struct igb_rx_buffer *rx_buffer_info;
1731 struct igb_tx_buffer *tx_buffer_info;
1732 u16 rx_ntc, tx_ntc, count = 0;
1734 /* initialize next to clean and descriptor values */
1735 rx_ntc = rx_ring->next_to_clean;
1736 tx_ntc = tx_ring->next_to_clean;
1737 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1739 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
1740 /* check rx buffer */
1741 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1743 /* sync Rx buffer for CPU read */
1744 dma_sync_single_for_cpu(rx_ring->dev,
1745 rx_buffer_info->dma,
1749 /* verify contents of skb */
1750 if (igb_check_lbtest_frame(rx_buffer_info, size))
1753 /* sync Rx buffer for device write */
1754 dma_sync_single_for_device(rx_ring->dev,
1755 rx_buffer_info->dma,
1759 /* unmap buffer on tx side */
1760 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1761 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1763 /* increment rx/tx next to clean counters */
1765 if (rx_ntc == rx_ring->count)
1768 if (tx_ntc == tx_ring->count)
1771 /* fetch next descriptor */
1772 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1775 netdev_tx_reset_queue(txring_txq(tx_ring));
1777 /* re-map buffers to ring, store next to clean values */
1778 igb_alloc_rx_buffers(rx_ring, count);
1779 rx_ring->next_to_clean = rx_ntc;
1780 tx_ring->next_to_clean = tx_ntc;
1785 static int igb_run_loopback_test(struct igb_adapter *adapter)
1787 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1788 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1789 u16 i, j, lc, good_cnt;
1791 unsigned int size = IGB_RX_HDR_LEN;
1792 netdev_tx_t tx_ret_val;
1793 struct sk_buff *skb;
1795 /* allocate test skb */
1796 skb = alloc_skb(size, GFP_KERNEL);
1800 /* place data into test skb */
1801 igb_create_lbtest_frame(skb, size);
1805 * Calculate the loop count based on the largest descriptor ring
1806 * The idea is to wrap the largest ring a number of times using 64
1807 * send/receive pairs during each loop
1810 if (rx_ring->count <= tx_ring->count)
1811 lc = ((tx_ring->count / 64) * 2) + 1;
1813 lc = ((rx_ring->count / 64) * 2) + 1;
1815 for (j = 0; j <= lc; j++) { /* loop count loop */
1816 /* reset count of good packets */
1819 /* place 64 packets on the transmit queue*/
1820 for (i = 0; i < 64; i++) {
1822 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1823 if (tx_ret_val == NETDEV_TX_OK)
1827 if (good_cnt != 64) {
1832 /* allow 200 milliseconds for packets to go from tx to rx */
1835 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1836 if (good_cnt != 64) {
1840 } /* end loop count loop */
1842 /* free the original skb */
1848 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1850 /* PHY loopback cannot be performed if SoL/IDER
1851 * sessions are active */
1852 if (igb_check_reset_block(&adapter->hw)) {
1853 dev_err(&adapter->pdev->dev,
1854 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1858 *data = igb_setup_desc_rings(adapter);
1861 *data = igb_setup_loopback_test(adapter);
1864 *data = igb_run_loopback_test(adapter);
1865 igb_loopback_cleanup(adapter);
1868 igb_free_desc_rings(adapter);
1873 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1875 struct e1000_hw *hw = &adapter->hw;
1877 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1879 hw->mac.serdes_has_link = false;
1881 /* On some blade server designs, link establishment
1882 * could take as long as 2-3 minutes */
1884 hw->mac.ops.check_for_link(&adapter->hw);
1885 if (hw->mac.serdes_has_link)
1888 } while (i++ < 3750);
1892 hw->mac.ops.check_for_link(&adapter->hw);
1893 if (hw->mac.autoneg)
1896 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1902 static void igb_diag_test(struct net_device *netdev,
1903 struct ethtool_test *eth_test, u64 *data)
1905 struct igb_adapter *adapter = netdev_priv(netdev);
1906 u16 autoneg_advertised;
1907 u8 forced_speed_duplex, autoneg;
1908 bool if_running = netif_running(netdev);
1910 set_bit(__IGB_TESTING, &adapter->state);
1911 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1914 /* save speed, duplex, autoneg settings */
1915 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1916 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1917 autoneg = adapter->hw.mac.autoneg;
1919 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1921 /* power up link for link test */
1922 igb_power_up_link(adapter);
1924 /* Link test performed before hardware reset so autoneg doesn't
1925 * interfere with test result */
1926 if (igb_link_test(adapter, &data[4]))
1927 eth_test->flags |= ETH_TEST_FL_FAILED;
1930 /* indicate we're in test mode */
1935 if (igb_reg_test(adapter, &data[0]))
1936 eth_test->flags |= ETH_TEST_FL_FAILED;
1939 if (igb_eeprom_test(adapter, &data[1]))
1940 eth_test->flags |= ETH_TEST_FL_FAILED;
1943 if (igb_intr_test(adapter, &data[2]))
1944 eth_test->flags |= ETH_TEST_FL_FAILED;
1947 /* power up link for loopback test */
1948 igb_power_up_link(adapter);
1949 if (igb_loopback_test(adapter, &data[3]))
1950 eth_test->flags |= ETH_TEST_FL_FAILED;
1952 /* restore speed, duplex, autoneg settings */
1953 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1954 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1955 adapter->hw.mac.autoneg = autoneg;
1957 /* force this routine to wait until autoneg complete/timeout */
1958 adapter->hw.phy.autoneg_wait_to_complete = true;
1960 adapter->hw.phy.autoneg_wait_to_complete = false;
1962 clear_bit(__IGB_TESTING, &adapter->state);
1966 dev_info(&adapter->pdev->dev, "online testing starting\n");
1968 /* PHY is powered down when interface is down */
1969 if (if_running && igb_link_test(adapter, &data[4]))
1970 eth_test->flags |= ETH_TEST_FL_FAILED;
1974 /* Online tests aren't run; pass by default */
1980 clear_bit(__IGB_TESTING, &adapter->state);
1982 msleep_interruptible(4 * 1000);
1985 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1987 struct igb_adapter *adapter = netdev_priv(netdev);
1989 wol->supported = WAKE_UCAST | WAKE_MCAST |
1990 WAKE_BCAST | WAKE_MAGIC |
1994 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
1997 /* apply any specific unsupported masks here */
1998 switch (adapter->hw.device_id) {
2003 if (adapter->wol & E1000_WUFC_EX)
2004 wol->wolopts |= WAKE_UCAST;
2005 if (adapter->wol & E1000_WUFC_MC)
2006 wol->wolopts |= WAKE_MCAST;
2007 if (adapter->wol & E1000_WUFC_BC)
2008 wol->wolopts |= WAKE_BCAST;
2009 if (adapter->wol & E1000_WUFC_MAG)
2010 wol->wolopts |= WAKE_MAGIC;
2011 if (adapter->wol & E1000_WUFC_LNKC)
2012 wol->wolopts |= WAKE_PHY;
2015 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2017 struct igb_adapter *adapter = netdev_priv(netdev);
2019 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2022 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2023 return wol->wolopts ? -EOPNOTSUPP : 0;
2025 /* these settings will always override what we currently have */
2028 if (wol->wolopts & WAKE_UCAST)
2029 adapter->wol |= E1000_WUFC_EX;
2030 if (wol->wolopts & WAKE_MCAST)
2031 adapter->wol |= E1000_WUFC_MC;
2032 if (wol->wolopts & WAKE_BCAST)
2033 adapter->wol |= E1000_WUFC_BC;
2034 if (wol->wolopts & WAKE_MAGIC)
2035 adapter->wol |= E1000_WUFC_MAG;
2036 if (wol->wolopts & WAKE_PHY)
2037 adapter->wol |= E1000_WUFC_LNKC;
2038 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2043 /* bit defines for adapter->led_status */
2044 #define IGB_LED_ON 0
2046 static int igb_set_phys_id(struct net_device *netdev,
2047 enum ethtool_phys_id_state state)
2049 struct igb_adapter *adapter = netdev_priv(netdev);
2050 struct e1000_hw *hw = &adapter->hw;
2053 case ETHTOOL_ID_ACTIVE:
2059 case ETHTOOL_ID_OFF:
2062 case ETHTOOL_ID_INACTIVE:
2064 clear_bit(IGB_LED_ON, &adapter->led_status);
2065 igb_cleanup_led(hw);
2072 static int igb_set_coalesce(struct net_device *netdev,
2073 struct ethtool_coalesce *ec)
2075 struct igb_adapter *adapter = netdev_priv(netdev);
2078 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2079 ((ec->rx_coalesce_usecs > 3) &&
2080 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2081 (ec->rx_coalesce_usecs == 2))
2084 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2085 ((ec->tx_coalesce_usecs > 3) &&
2086 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2087 (ec->tx_coalesce_usecs == 2))
2090 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2093 /* If ITR is disabled, disable DMAC */
2094 if (ec->rx_coalesce_usecs == 0) {
2095 if (adapter->flags & IGB_FLAG_DMAC)
2096 adapter->flags &= ~IGB_FLAG_DMAC;
2099 /* convert to rate of irq's per second */
2100 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2101 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2103 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2105 /* convert to rate of irq's per second */
2106 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2107 adapter->tx_itr_setting = adapter->rx_itr_setting;
2108 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2109 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2111 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2113 for (i = 0; i < adapter->num_q_vectors; i++) {
2114 struct igb_q_vector *q_vector = adapter->q_vector[i];
2115 q_vector->tx.work_limit = adapter->tx_work_limit;
2116 if (q_vector->rx.ring)
2117 q_vector->itr_val = adapter->rx_itr_setting;
2119 q_vector->itr_val = adapter->tx_itr_setting;
2120 if (q_vector->itr_val && q_vector->itr_val <= 3)
2121 q_vector->itr_val = IGB_START_ITR;
2122 q_vector->set_itr = 1;
2128 static int igb_get_coalesce(struct net_device *netdev,
2129 struct ethtool_coalesce *ec)
2131 struct igb_adapter *adapter = netdev_priv(netdev);
2133 if (adapter->rx_itr_setting <= 3)
2134 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2136 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2138 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2139 if (adapter->tx_itr_setting <= 3)
2140 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2142 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2148 static int igb_nway_reset(struct net_device *netdev)
2150 struct igb_adapter *adapter = netdev_priv(netdev);
2151 if (netif_running(netdev))
2152 igb_reinit_locked(adapter);
2156 static int igb_get_sset_count(struct net_device *netdev, int sset)
2160 return IGB_STATS_LEN;
2162 return IGB_TEST_LEN;
2168 static void igb_get_ethtool_stats(struct net_device *netdev,
2169 struct ethtool_stats *stats, u64 *data)
2171 struct igb_adapter *adapter = netdev_priv(netdev);
2172 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2174 struct igb_ring *ring;
2178 spin_lock(&adapter->stats64_lock);
2179 igb_update_stats(adapter, net_stats);
2181 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2182 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2183 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2184 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2186 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2187 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2188 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2189 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2191 for (j = 0; j < adapter->num_tx_queues; j++) {
2194 ring = adapter->tx_ring[j];
2196 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2197 data[i] = ring->tx_stats.packets;
2198 data[i+1] = ring->tx_stats.bytes;
2199 data[i+2] = ring->tx_stats.restart_queue;
2200 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2202 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2203 restart2 = ring->tx_stats.restart_queue2;
2204 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2205 data[i+2] += restart2;
2207 i += IGB_TX_QUEUE_STATS_LEN;
2209 for (j = 0; j < adapter->num_rx_queues; j++) {
2210 ring = adapter->rx_ring[j];
2212 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2213 data[i] = ring->rx_stats.packets;
2214 data[i+1] = ring->rx_stats.bytes;
2215 data[i+2] = ring->rx_stats.drops;
2216 data[i+3] = ring->rx_stats.csum_err;
2217 data[i+4] = ring->rx_stats.alloc_failed;
2218 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2219 i += IGB_RX_QUEUE_STATS_LEN;
2221 spin_unlock(&adapter->stats64_lock);
2224 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2226 struct igb_adapter *adapter = netdev_priv(netdev);
2230 switch (stringset) {
2232 memcpy(data, *igb_gstrings_test,
2233 IGB_TEST_LEN*ETH_GSTRING_LEN);
2236 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2237 memcpy(p, igb_gstrings_stats[i].stat_string,
2239 p += ETH_GSTRING_LEN;
2241 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2242 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2244 p += ETH_GSTRING_LEN;
2246 for (i = 0; i < adapter->num_tx_queues; i++) {
2247 sprintf(p, "tx_queue_%u_packets", i);
2248 p += ETH_GSTRING_LEN;
2249 sprintf(p, "tx_queue_%u_bytes", i);
2250 p += ETH_GSTRING_LEN;
2251 sprintf(p, "tx_queue_%u_restart", i);
2252 p += ETH_GSTRING_LEN;
2254 for (i = 0; i < adapter->num_rx_queues; i++) {
2255 sprintf(p, "rx_queue_%u_packets", i);
2256 p += ETH_GSTRING_LEN;
2257 sprintf(p, "rx_queue_%u_bytes", i);
2258 p += ETH_GSTRING_LEN;
2259 sprintf(p, "rx_queue_%u_drops", i);
2260 p += ETH_GSTRING_LEN;
2261 sprintf(p, "rx_queue_%u_csum_err", i);
2262 p += ETH_GSTRING_LEN;
2263 sprintf(p, "rx_queue_%u_alloc_failed", i);
2264 p += ETH_GSTRING_LEN;
2266 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2271 static int igb_get_ts_info(struct net_device *dev,
2272 struct ethtool_ts_info *info)
2274 struct igb_adapter *adapter = netdev_priv(dev);
2276 switch (adapter->hw.mac.type) {
2278 info->so_timestamping =
2279 SOF_TIMESTAMPING_TX_SOFTWARE |
2280 SOF_TIMESTAMPING_RX_SOFTWARE |
2281 SOF_TIMESTAMPING_SOFTWARE;
2288 info->so_timestamping =
2289 SOF_TIMESTAMPING_TX_SOFTWARE |
2290 SOF_TIMESTAMPING_RX_SOFTWARE |
2291 SOF_TIMESTAMPING_SOFTWARE |
2292 SOF_TIMESTAMPING_TX_HARDWARE |
2293 SOF_TIMESTAMPING_RX_HARDWARE |
2294 SOF_TIMESTAMPING_RAW_HARDWARE;
2296 if (adapter->ptp_clock)
2297 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2299 info->phc_index = -1;
2302 (1 << HWTSTAMP_TX_OFF) |
2303 (1 << HWTSTAMP_TX_ON);
2305 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
2307 /* 82576 does not support timestamping all packets. */
2308 if (adapter->hw.mac.type >= e1000_82580)
2309 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2312 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2313 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2314 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2315 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2316 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2317 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2318 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2326 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2327 struct ethtool_rxnfc *cmd)
2331 /* Report default options for RSS on igb */
2332 switch (cmd->flow_type) {
2334 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2336 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2337 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2339 case AH_ESP_V4_FLOW:
2343 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2346 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2348 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2349 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2351 case AH_ESP_V6_FLOW:
2355 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2364 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2367 struct igb_adapter *adapter = netdev_priv(dev);
2368 int ret = -EOPNOTSUPP;
2371 case ETHTOOL_GRXRINGS:
2372 cmd->data = adapter->num_rx_queues;
2376 ret = igb_get_rss_hash_opts(adapter, cmd);
2385 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2386 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2387 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2388 struct ethtool_rxnfc *nfc)
2390 u32 flags = adapter->flags;
2392 /* RSS does not support anything other than hashing
2393 * to queues on src and dst IPs and ports
2395 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2396 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2399 switch (nfc->flow_type) {
2402 if (!(nfc->data & RXH_IP_SRC) ||
2403 !(nfc->data & RXH_IP_DST) ||
2404 !(nfc->data & RXH_L4_B_0_1) ||
2405 !(nfc->data & RXH_L4_B_2_3))
2409 if (!(nfc->data & RXH_IP_SRC) ||
2410 !(nfc->data & RXH_IP_DST))
2412 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2414 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2416 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2417 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2424 if (!(nfc->data & RXH_IP_SRC) ||
2425 !(nfc->data & RXH_IP_DST))
2427 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2429 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2431 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2432 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2438 case AH_ESP_V4_FLOW:
2442 case AH_ESP_V6_FLOW:
2446 if (!(nfc->data & RXH_IP_SRC) ||
2447 !(nfc->data & RXH_IP_DST) ||
2448 (nfc->data & RXH_L4_B_0_1) ||
2449 (nfc->data & RXH_L4_B_2_3))
2456 /* if we changed something we need to update flags */
2457 if (flags != adapter->flags) {
2458 struct e1000_hw *hw = &adapter->hw;
2459 u32 mrqc = rd32(E1000_MRQC);
2461 if ((flags & UDP_RSS_FLAGS) &&
2462 !(adapter->flags & UDP_RSS_FLAGS))
2463 dev_err(&adapter->pdev->dev,
2464 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2466 adapter->flags = flags;
2468 /* Perform hash on these packet types */
2469 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2470 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2471 E1000_MRQC_RSS_FIELD_IPV6 |
2472 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2474 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2475 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2477 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2478 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2480 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2481 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2483 wr32(E1000_MRQC, mrqc);
2489 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2491 struct igb_adapter *adapter = netdev_priv(dev);
2492 int ret = -EOPNOTSUPP;
2496 ret = igb_set_rss_hash_opt(adapter, cmd);
2505 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2507 struct igb_adapter *adapter = netdev_priv(netdev);
2508 struct e1000_hw *hw = &adapter->hw;
2511 if ((hw->mac.type < e1000_i350) ||
2512 (hw->phy.media_type != e1000_media_type_copper))
2515 edata->supported = (SUPPORTED_1000baseT_Full |
2516 SUPPORTED_100baseT_Full);
2518 ipcnfg = rd32(E1000_IPCNFG);
2519 eeer = rd32(E1000_EEER);
2521 /* EEE status on negotiated link */
2522 if (ipcnfg & E1000_IPCNFG_EEE_1G_AN)
2523 edata->advertised = ADVERTISED_1000baseT_Full;
2525 if (ipcnfg & E1000_IPCNFG_EEE_100M_AN)
2526 edata->advertised |= ADVERTISED_100baseT_Full;
2528 if (eeer & E1000_EEER_EEE_NEG)
2529 edata->eee_active = true;
2531 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2533 if (eeer & E1000_EEER_TX_LPI_EN)
2534 edata->tx_lpi_enabled = true;
2536 /* Report correct negotiated EEE status for devices that
2537 * wrongly report EEE at half-duplex
2539 if (adapter->link_duplex == HALF_DUPLEX) {
2540 edata->eee_enabled = false;
2541 edata->eee_active = false;
2542 edata->tx_lpi_enabled = false;
2543 edata->advertised &= ~edata->advertised;
2549 static int igb_set_eee(struct net_device *netdev,
2550 struct ethtool_eee *edata)
2552 struct igb_adapter *adapter = netdev_priv(netdev);
2553 struct e1000_hw *hw = &adapter->hw;
2554 struct ethtool_eee eee_curr;
2557 if ((hw->mac.type < e1000_i350) ||
2558 (hw->phy.media_type != e1000_media_type_copper))
2561 ret_val = igb_get_eee(netdev, &eee_curr);
2565 if (eee_curr.eee_enabled) {
2566 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2567 dev_err(&adapter->pdev->dev,
2568 "Setting EEE tx-lpi is not supported\n");
2572 /* Tx LPI timer is not implemented currently */
2573 if (edata->tx_lpi_timer) {
2574 dev_err(&adapter->pdev->dev,
2575 "Setting EEE Tx LPI timer is not supported\n");
2579 if (eee_curr.advertised != edata->advertised) {
2580 dev_err(&adapter->pdev->dev,
2581 "Setting EEE Advertisement is not supported\n");
2585 } else if (!edata->eee_enabled) {
2586 dev_err(&adapter->pdev->dev,
2587 "Setting EEE options are not supported with EEE disabled\n");
2591 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2592 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2593 igb_set_eee_i350(hw);
2596 if (!netif_running(netdev))
2603 static int igb_ethtool_begin(struct net_device *netdev)
2605 struct igb_adapter *adapter = netdev_priv(netdev);
2606 pm_runtime_get_sync(&adapter->pdev->dev);
2610 static void igb_ethtool_complete(struct net_device *netdev)
2612 struct igb_adapter *adapter = netdev_priv(netdev);
2613 pm_runtime_put(&adapter->pdev->dev);
2616 static const struct ethtool_ops igb_ethtool_ops = {
2617 .get_settings = igb_get_settings,
2618 .set_settings = igb_set_settings,
2619 .get_drvinfo = igb_get_drvinfo,
2620 .get_regs_len = igb_get_regs_len,
2621 .get_regs = igb_get_regs,
2622 .get_wol = igb_get_wol,
2623 .set_wol = igb_set_wol,
2624 .get_msglevel = igb_get_msglevel,
2625 .set_msglevel = igb_set_msglevel,
2626 .nway_reset = igb_nway_reset,
2627 .get_link = igb_get_link,
2628 .get_eeprom_len = igb_get_eeprom_len,
2629 .get_eeprom = igb_get_eeprom,
2630 .set_eeprom = igb_set_eeprom,
2631 .get_ringparam = igb_get_ringparam,
2632 .set_ringparam = igb_set_ringparam,
2633 .get_pauseparam = igb_get_pauseparam,
2634 .set_pauseparam = igb_set_pauseparam,
2635 .self_test = igb_diag_test,
2636 .get_strings = igb_get_strings,
2637 .set_phys_id = igb_set_phys_id,
2638 .get_sset_count = igb_get_sset_count,
2639 .get_ethtool_stats = igb_get_ethtool_stats,
2640 .get_coalesce = igb_get_coalesce,
2641 .set_coalesce = igb_set_coalesce,
2642 .get_ts_info = igb_get_ts_info,
2643 .get_rxnfc = igb_get_rxnfc,
2644 .set_rxnfc = igb_set_rxnfc,
2645 .get_eee = igb_get_eee,
2646 .set_eee = igb_set_eee,
2647 .begin = igb_ethtool_begin,
2648 .complete = igb_ethtool_complete,
2651 void igb_set_ethtool_ops(struct net_device *netdev)
2653 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);