drivers/net/ethernet/intel/igb/igb_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for igb */
  29
  30 #include <linux/vmalloc.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/pm_runtime.h>
  40
  41 #include "igb.h"
  42
  43 struct igb_stats {
  44         char stat_string[ETH_GSTRING_LEN];
  45         int sizeof_stat;
  46         int stat_offset;
  47 };
  48
  49 #define IGB_STAT(_name, _stat) { \
  50         .stat_string = _name, \
  51         .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
  52         .stat_offset = offsetof(struct igb_adapter, _stat) \
  53 }
  54 static const struct igb_stats igb_gstrings_stats[] = {
  55         IGB_STAT("rx_packets", stats.gprc),
  56         IGB_STAT("tx_packets", stats.gptc),
  57         IGB_STAT("rx_bytes", stats.gorc),
  58         IGB_STAT("tx_bytes", stats.gotc),
  59         IGB_STAT("rx_broadcast", stats.bprc),
  60         IGB_STAT("tx_broadcast", stats.bptc),
  61         IGB_STAT("rx_multicast", stats.mprc),
  62         IGB_STAT("tx_multicast", stats.mptc),
  63         IGB_STAT("multicast", stats.mprc),
  64         IGB_STAT("collisions", stats.colc),
  65         IGB_STAT("rx_crc_errors", stats.crcerrs),
  66         IGB_STAT("rx_no_buffer_count", stats.rnbc),
  67         IGB_STAT("rx_missed_errors", stats.mpc),
  68         IGB_STAT("tx_aborted_errors", stats.ecol),
  69         IGB_STAT("tx_carrier_errors", stats.tncrs),
  70         IGB_STAT("tx_window_errors", stats.latecol),
  71         IGB_STAT("tx_abort_late_coll", stats.latecol),
  72         IGB_STAT("tx_deferred_ok", stats.dc),
  73         IGB_STAT("tx_single_coll_ok", stats.scc),
  74         IGB_STAT("tx_multi_coll_ok", stats.mcc),
  75         IGB_STAT("tx_timeout_count", tx_timeout_count),
  76         IGB_STAT("rx_long_length_errors", stats.roc),
  77         IGB_STAT("rx_short_length_errors", stats.ruc),
  78         IGB_STAT("rx_align_errors", stats.algnerrc),
  79         IGB_STAT("tx_tcp_seg_good", stats.tsctc),
  80         IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
  81         IGB_STAT("rx_flow_control_xon", stats.xonrxc),
  82         IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
  83         IGB_STAT("tx_flow_control_xon", stats.xontxc),
  84         IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
  85         IGB_STAT("rx_long_byte_count", stats.gorc),
  86         IGB_STAT("tx_dma_out_of_sync", stats.doosync),
  87         IGB_STAT("tx_smbus", stats.mgptc),
  88         IGB_STAT("rx_smbus", stats.mgprc),
  89         IGB_STAT("dropped_smbus", stats.mgpdc),
  90         IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
  91         IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
  92         IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
  93         IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
  94 };
  95
  96 #define IGB_NETDEV_STAT(_net_stat) { \
  97         .stat_string = __stringify(_net_stat), \
  98         .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
  99         .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
 100 }
 101 static const struct igb_stats igb_gstrings_net_stats[] = {
 102         IGB_NETDEV_STAT(rx_errors),
 103         IGB_NETDEV_STAT(tx_errors),
 104         IGB_NETDEV_STAT(tx_dropped),
 105         IGB_NETDEV_STAT(rx_length_errors),
 106         IGB_NETDEV_STAT(rx_over_errors),
 107         IGB_NETDEV_STAT(rx_frame_errors),
 108         IGB_NETDEV_STAT(rx_fifo_errors),
 109         IGB_NETDEV_STAT(tx_fifo_errors),
 110         IGB_NETDEV_STAT(tx_heartbeat_errors)
 111 };
 112
 113 #define IGB_GLOBAL_STATS_LEN    \
 114         (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
 115 #define IGB_NETDEV_STATS_LEN    \
 116         (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
 117 #define IGB_RX_QUEUE_STATS_LEN \
 118         (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
 119
 120 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
 121
 122 #define IGB_QUEUE_STATS_LEN \
 123         ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
 124           IGB_RX_QUEUE_STATS_LEN) + \
 125          (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
 126           IGB_TX_QUEUE_STATS_LEN))
 127 #define IGB_STATS_LEN \
 128         (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
 129
 130 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 131         "Register test  (offline)", "Eeprom test    (offline)",
 132         "Interrupt test (offline)", "Loopback test  (offline)",
 133         "Link test   (on/offline)"
 134 };
 135 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
 136
 137 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 138 {
 139         struct igb_adapter *adapter = netdev_priv(netdev);
 140         struct e1000_hw *hw = &adapter->hw;
 141         u32 status;
 142
 143         if (hw->phy.media_type == e1000_media_type_copper) {
 144
 145                 ecmd->supported = (SUPPORTED_10baseT_Half |
 146                                    SUPPORTED_10baseT_Full |
 147                                    SUPPORTED_100baseT_Half |
 148                                    SUPPORTED_100baseT_Full |
 149                                    SUPPORTED_1000baseT_Full|
 150                                    SUPPORTED_Autoneg |
 151                                    SUPPORTED_TP);
 152                 ecmd->advertising = (ADVERTISED_TP |
 153                                      ADVERTISED_Pause);
 154
 155                 if (hw->mac.autoneg == 1) {
 156                         ecmd->advertising |= ADVERTISED_Autoneg;
 157                         /* the e1000 autoneg seems to match ethtool nicely */
 158                         ecmd->advertising |= hw->phy.autoneg_advertised;
 159                 }
 160
 161                 ecmd->port = PORT_TP;
 162                 ecmd->phy_address = hw->phy.addr;
 163         } else {
 164                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
 165                                      SUPPORTED_FIBRE |
 166                                      SUPPORTED_Autoneg);
 167
 168                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
 169                                      ADVERTISED_FIBRE |
 170                                      ADVERTISED_Autoneg |
 171                                      ADVERTISED_Pause);
 172
 173                 ecmd->port = PORT_FIBRE;
 174         }
 175
 176         ecmd->transceiver = XCVR_INTERNAL;
 177
 178         status = rd32(E1000_STATUS);
 179
 180         if (status & E1000_STATUS_LU) {
 181
 182                 if ((status & E1000_STATUS_SPEED_1000) ||
 183                     hw->phy.media_type != e1000_media_type_copper)
 184                         ethtool_cmd_speed_set(ecmd, SPEED_1000);
 185                 else if (status & E1000_STATUS_SPEED_100)
 186                         ethtool_cmd_speed_set(ecmd, SPEED_100);
 187                 else
 188                         ethtool_cmd_speed_set(ecmd, SPEED_10);
 189
 190                 if ((status & E1000_STATUS_FD) ||
 191                     hw->phy.media_type != e1000_media_type_copper)
 192                         ecmd->duplex = DUPLEX_FULL;
 193                 else
 194                         ecmd->duplex = DUPLEX_HALF;
 195         } else {
 196                 ethtool_cmd_speed_set(ecmd, -1);
 197                 ecmd->duplex = -1;
 198         }
 199
 200         ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 201
 202         /* MDI-X => 2; MDI =>1; Invalid =>0 */
 203         if (hw->phy.media_type == e1000_media_type_copper)
 204                 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
 205                                                       ETH_TP_MDI;
 206         else
 207                 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
 208
 209         if (hw->phy.mdix == AUTO_ALL_MODES)
 210                 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
 211         else
 212                 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
 213
 214         return 0;
 215 }
 216
 217 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 218 {
 219         struct igb_adapter *adapter = netdev_priv(netdev);
 220         struct e1000_hw *hw = &adapter->hw;
 221
 222         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 223          * cannot be changed */
 224         if (igb_check_reset_block(hw)) {
 225                 dev_err(&adapter->pdev->dev,
 226                         "Cannot change link characteristics when SoL/IDER is active.\n");
 227                 return -EINVAL;
 228         }
 229
 230         /*
 231          * MDI setting is only allowed when autoneg enabled because
 232          * some hardware doesn't allow MDI setting when speed or
 233          * duplex is forced.
 234          */
 235         if (ecmd->eth_tp_mdix_ctrl) {
 236                 if (hw->phy.media_type != e1000_media_type_copper)
 237                         return -EOPNOTSUPP;
 238
 239                 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
 240                     (ecmd->autoneg != AUTONEG_ENABLE)) {
 241                         dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
 242                         return -EINVAL;
 243                 }
 244         }
 245
 246         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 247                 msleep(1);
 248
 249         if (ecmd->autoneg == AUTONEG_ENABLE) {
 250                 hw->mac.autoneg = 1;
 251                 hw->phy.autoneg_advertised = ecmd->advertising |
 252                                              ADVERTISED_TP |
 253                                              ADVERTISED_Autoneg;
 254                 ecmd->advertising = hw->phy.autoneg_advertised;
 255                 if (adapter->fc_autoneg)
 256                         hw->fc.requested_mode = e1000_fc_default;
 257         } else {
 258                 u32 speed = ethtool_cmd_speed(ecmd);
 259                 /* calling this overrides forced MDI setting */
 260                 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
 261                         clear_bit(__IGB_RESETTING, &adapter->state);
 262                         return -EINVAL;
 263                 }
 264         }
 265
 266         /* MDI-X => 2; MDI => 1; Auto => 3 */
 267         if (ecmd->eth_tp_mdix_ctrl) {
 268                 /*
 269                  * fix up the value for auto (3 => 0) as zero is mapped
 270                  * internally to auto
 271                  */
 272                 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
 273                         hw->phy.mdix = AUTO_ALL_MODES;
 274                 else
 275                         hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
 276         }
 277
 278         /* reset the link */
 279         if (netif_running(adapter->netdev)) {
 280                 igb_down(adapter);
 281                 igb_up(adapter);
 282         } else
 283                 igb_reset(adapter);
 284
 285         clear_bit(__IGB_RESETTING, &adapter->state);
 286         return 0;
 287 }
 288
 289 static u32 igb_get_link(struct net_device *netdev)
 290 {
 291         struct igb_adapter *adapter = netdev_priv(netdev);
 292         struct e1000_mac_info *mac = &adapter->hw.mac;
 293
 294         /*
 295          * If the link is not reported up to netdev, interrupts are disabled,
 296          * and so the physical link state may have changed since we last
 297          * looked. Set get_link_status to make sure that the true link
 298          * state is interrogated, rather than pulling a cached and possibly
 299          * stale link state from the driver.
 300          */
 301         if (!netif_carrier_ok(netdev))
 302                 mac->get_link_status = 1;
 303
 304         return igb_has_link(adapter);
 305 }
 306
 307 static void igb_get_pauseparam(struct net_device *netdev,
 308                                struct ethtool_pauseparam *pause)
 309 {
 310         struct igb_adapter *adapter = netdev_priv(netdev);
 311         struct e1000_hw *hw = &adapter->hw;
 312
 313         pause->autoneg =
 314                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 315
 316         if (hw->fc.current_mode == e1000_fc_rx_pause)
 317                 pause->rx_pause = 1;
 318         else if (hw->fc.current_mode == e1000_fc_tx_pause)
 319                 pause->tx_pause = 1;
 320         else if (hw->fc.current_mode == e1000_fc_full) {
 321                 pause->rx_pause = 1;
 322                 pause->tx_pause = 1;
 323         }
 324 }
 325
 326 static int igb_set_pauseparam(struct net_device *netdev,
 327                               struct ethtool_pauseparam *pause)
 328 {
 329         struct igb_adapter *adapter = netdev_priv(netdev);
 330         struct e1000_hw *hw = &adapter->hw;
 331         int retval = 0;
 332
 333         adapter->fc_autoneg = pause->autoneg;
 334
 335         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 336                 msleep(1);
 337
 338         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 339                 hw->fc.requested_mode = e1000_fc_default;
 340                 if (netif_running(adapter->netdev)) {
 341                         igb_down(adapter);
 342                         igb_up(adapter);
 343                 } else {
 344                         igb_reset(adapter);
 345                 }
 346         } else {
 347                 if (pause->rx_pause && pause->tx_pause)
 348                         hw->fc.requested_mode = e1000_fc_full;
 349                 else if (pause->rx_pause && !pause->tx_pause)
 350                         hw->fc.requested_mode = e1000_fc_rx_pause;
 351                 else if (!pause->rx_pause && pause->tx_pause)
 352                         hw->fc.requested_mode = e1000_fc_tx_pause;
 353                 else if (!pause->rx_pause && !pause->tx_pause)
 354                         hw->fc.requested_mode = e1000_fc_none;
 355
 356                 hw->fc.current_mode = hw->fc.requested_mode;
 357
 358                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
 359                           igb_force_mac_fc(hw) : igb_setup_link(hw));
 360         }
 361
 362         clear_bit(__IGB_RESETTING, &adapter->state);
 363         return retval;
 364 }
 365
 366 static u32 igb_get_msglevel(struct net_device *netdev)
 367 {
 368         struct igb_adapter *adapter = netdev_priv(netdev);
 369         return adapter->msg_enable;
 370 }
 371
 372 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 373 {
 374         struct igb_adapter *adapter = netdev_priv(netdev);
 375         adapter->msg_enable = data;
 376 }
 377
 378 static int igb_get_regs_len(struct net_device *netdev)
 379 {
 380 #define IGB_REGS_LEN 739
 381         return IGB_REGS_LEN * sizeof(u32);
 382 }
 383
 384 static void igb_get_regs(struct net_device *netdev,
 385                          struct ethtool_regs *regs, void *p)
 386 {
 387         struct igb_adapter *adapter = netdev_priv(netdev);
 388         struct e1000_hw *hw = &adapter->hw;
 389         u32 *regs_buff = p;
 390         u8 i;
 391
 392         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 393
 394         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 395
 396         /* General Registers */
 397         regs_buff[0] = rd32(E1000_CTRL);
 398         regs_buff[1] = rd32(E1000_STATUS);
 399         regs_buff[2] = rd32(E1000_CTRL_EXT);
 400         regs_buff[3] = rd32(E1000_MDIC);
 401         regs_buff[4] = rd32(E1000_SCTL);
 402         regs_buff[5] = rd32(E1000_CONNSW);
 403         regs_buff[6] = rd32(E1000_VET);
 404         regs_buff[7] = rd32(E1000_LEDCTL);
 405         regs_buff[8] = rd32(E1000_PBA);
 406         regs_buff[9] = rd32(E1000_PBS);
 407         regs_buff[10] = rd32(E1000_FRTIMER);
 408         regs_buff[11] = rd32(E1000_TCPTIMER);
 409
 410         /* NVM Register */
 411         regs_buff[12] = rd32(E1000_EECD);
 412
 413         /* Interrupt */
 414         /* Reading EICS for EICR because they read the
 415          * same but EICS does not clear on read */
 416         regs_buff[13] = rd32(E1000_EICS);
 417         regs_buff[14] = rd32(E1000_EICS);
 418         regs_buff[15] = rd32(E1000_EIMS);
 419         regs_buff[16] = rd32(E1000_EIMC);
 420         regs_buff[17] = rd32(E1000_EIAC);
 421         regs_buff[18] = rd32(E1000_EIAM);
 422         /* Reading ICS for ICR because they read the
 423          * same but ICS does not clear on read */
 424         regs_buff[19] = rd32(E1000_ICS);
 425         regs_buff[20] = rd32(E1000_ICS);
 426         regs_buff[21] = rd32(E1000_IMS);
 427         regs_buff[22] = rd32(E1000_IMC);
 428         regs_buff[23] = rd32(E1000_IAC);
 429         regs_buff[24] = rd32(E1000_IAM);
 430         regs_buff[25] = rd32(E1000_IMIRVP);
 431
 432         /* Flow Control */
 433         regs_buff[26] = rd32(E1000_FCAL);
 434         regs_buff[27] = rd32(E1000_FCAH);
 435         regs_buff[28] = rd32(E1000_FCTTV);
 436         regs_buff[29] = rd32(E1000_FCRTL);
 437         regs_buff[30] = rd32(E1000_FCRTH);
 438         regs_buff[31] = rd32(E1000_FCRTV);
 439
 440         /* Receive */
 441         regs_buff[32] = rd32(E1000_RCTL);
 442         regs_buff[33] = rd32(E1000_RXCSUM);
 443         regs_buff[34] = rd32(E1000_RLPML);
 444         regs_buff[35] = rd32(E1000_RFCTL);
 445         regs_buff[36] = rd32(E1000_MRQC);
 446         regs_buff[37] = rd32(E1000_VT_CTL);
 447
 448         /* Transmit */
 449         regs_buff[38] = rd32(E1000_TCTL);
 450         regs_buff[39] = rd32(E1000_TCTL_EXT);
 451         regs_buff[40] = rd32(E1000_TIPG);
 452         regs_buff[41] = rd32(E1000_DTXCTL);
 453
 454         /* Wake Up */
 455         regs_buff[42] = rd32(E1000_WUC);
 456         regs_buff[43] = rd32(E1000_WUFC);
 457         regs_buff[44] = rd32(E1000_WUS);
 458         regs_buff[45] = rd32(E1000_IPAV);
 459         regs_buff[46] = rd32(E1000_WUPL);
 460
 461         /* MAC */
 462         regs_buff[47] = rd32(E1000_PCS_CFG0);
 463         regs_buff[48] = rd32(E1000_PCS_LCTL);
 464         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 465         regs_buff[50] = rd32(E1000_PCS_ANADV);
 466         regs_buff[51] = rd32(E1000_PCS_LPAB);
 467         regs_buff[52] = rd32(E1000_PCS_NPTX);
 468         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 469
 470         /* Statistics */
 471         regs_buff[54] = adapter->stats.crcerrs;
 472         regs_buff[55] = adapter->stats.algnerrc;
 473         regs_buff[56] = adapter->stats.symerrs;
 474         regs_buff[57] = adapter->stats.rxerrc;
 475         regs_buff[58] = adapter->stats.mpc;
 476         regs_buff[59] = adapter->stats.scc;
 477         regs_buff[60] = adapter->stats.ecol;
 478         regs_buff[61] = adapter->stats.mcc;
 479         regs_buff[62] = adapter->stats.latecol;
 480         regs_buff[63] = adapter->stats.colc;
 481         regs_buff[64] = adapter->stats.dc;
 482         regs_buff[65] = adapter->stats.tncrs;
 483         regs_buff[66] = adapter->stats.sec;
 484         regs_buff[67] = adapter->stats.htdpmc;
 485         regs_buff[68] = adapter->stats.rlec;
 486         regs_buff[69] = adapter->stats.xonrxc;
 487         regs_buff[70] = adapter->stats.xontxc;
 488         regs_buff[71] = adapter->stats.xoffrxc;
 489         regs_buff[72] = adapter->stats.xofftxc;
 490         regs_buff[73] = adapter->stats.fcruc;
 491         regs_buff[74] = adapter->stats.prc64;
 492         regs_buff[75] = adapter->stats.prc127;
 493         regs_buff[76] = adapter->stats.prc255;
 494         regs_buff[77] = adapter->stats.prc511;
 495         regs_buff[78] = adapter->stats.prc1023;
 496         regs_buff[79] = adapter->stats.prc1522;
 497         regs_buff[80] = adapter->stats.gprc;
 498         regs_buff[81] = adapter->stats.bprc;
 499         regs_buff[82] = adapter->stats.mprc;
 500         regs_buff[83] = adapter->stats.gptc;
 501         regs_buff[84] = adapter->stats.gorc;
 502         regs_buff[86] = adapter->stats.gotc;
 503         regs_buff[88] = adapter->stats.rnbc;
 504         regs_buff[89] = adapter->stats.ruc;
 505         regs_buff[90] = adapter->stats.rfc;
 506         regs_buff[91] = adapter->stats.roc;
 507         regs_buff[92] = adapter->stats.rjc;
 508         regs_buff[93] = adapter->stats.mgprc;
 509         regs_buff[94] = adapter->stats.mgpdc;
 510         regs_buff[95] = adapter->stats.mgptc;
 511         regs_buff[96] = adapter->stats.tor;
 512         regs_buff[98] = adapter->stats.tot;
 513         regs_buff[100] = adapter->stats.tpr;
 514         regs_buff[101] = adapter->stats.tpt;
 515         regs_buff[102] = adapter->stats.ptc64;
 516         regs_buff[103] = adapter->stats.ptc127;
 517         regs_buff[104] = adapter->stats.ptc255;
 518         regs_buff[105] = adapter->stats.ptc511;
 519         regs_buff[106] = adapter->stats.ptc1023;
 520         regs_buff[107] = adapter->stats.ptc1522;
 521         regs_buff[108] = adapter->stats.mptc;
 522         regs_buff[109] = adapter->stats.bptc;
 523         regs_buff[110] = adapter->stats.tsctc;
 524         regs_buff[111] = adapter->stats.iac;
 525         regs_buff[112] = adapter->stats.rpthc;
 526         regs_buff[113] = adapter->stats.hgptc;
 527         regs_buff[114] = adapter->stats.hgorc;
 528         regs_buff[116] = adapter->stats.hgotc;
 529         regs_buff[118] = adapter->stats.lenerrs;
 530         regs_buff[119] = adapter->stats.scvpc;
 531         regs_buff[120] = adapter->stats.hrmpc;
 532
 533         for (i = 0; i < 4; i++)
 534                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 535         for (i = 0; i < 4; i++)
 536                 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
 537         for (i = 0; i < 4; i++)
 538                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 539         for (i = 0; i < 4; i++)
 540                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 541         for (i = 0; i < 4; i++)
 542                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 543         for (i = 0; i < 4; i++)
 544                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 545         for (i = 0; i < 4; i++)
 546                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 547         for (i = 0; i < 4; i++)
 548                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 549
 550         for (i = 0; i < 10; i++)
 551                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 552         for (i = 0; i < 8; i++)
 553                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 554         for (i = 0; i < 8; i++)
 555                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 556         for (i = 0; i < 16; i++)
 557                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 558         for (i = 0; i < 16; i++)
 559                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 560
 561         for (i = 0; i < 4; i++)
 562                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 563         for (i = 0; i < 4; i++)
 564                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 565         for (i = 0; i < 4; i++)
 566                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 567         for (i = 0; i < 4; i++)
 568                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 569         for (i = 0; i < 4; i++)
 570                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 571         for (i = 0; i < 4; i++)
 572                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 573         for (i = 0; i < 4; i++)
 574                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 575         for (i = 0; i < 4; i++)
 576                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 577         for (i = 0; i < 4; i++)
 578                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 579
 580         for (i = 0; i < 4; i++)
 581                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 582         for (i = 0; i < 4; i++)
 583                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 584         for (i = 0; i < 32; i++)
 585                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 586         for (i = 0; i < 128; i++)
 587                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 588         for (i = 0; i < 128; i++)
 589                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 590         for (i = 0; i < 4; i++)
 591                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 592
 593         regs_buff[547] = rd32(E1000_TDFH);
 594         regs_buff[548] = rd32(E1000_TDFT);
 595         regs_buff[549] = rd32(E1000_TDFHS);
 596         regs_buff[550] = rd32(E1000_TDFPC);
 597
 598         if (hw->mac.type > e1000_82580) {
 599                 regs_buff[551] = adapter->stats.o2bgptc;
 600                 regs_buff[552] = adapter->stats.b2ospc;
 601                 regs_buff[553] = adapter->stats.o2bspc;
 602                 regs_buff[554] = adapter->stats.b2ogprc;
 603         }
 604
 605         if (hw->mac.type != e1000_82576)
 606                 return;
 607         for (i = 0; i < 12; i++)
 608                 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
 609         for (i = 0; i < 4; i++)
 610                 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
 611         for (i = 0; i < 12; i++)
 612                 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
 613         for (i = 0; i < 12; i++)
 614                 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
 615         for (i = 0; i < 12; i++)
 616                 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
 617         for (i = 0; i < 12; i++)
 618                 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
 619         for (i = 0; i < 12; i++)
 620                 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
 621         for (i = 0; i < 12; i++)
 622                 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
 623
 624         for (i = 0; i < 12; i++)
 625                 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
 626         for (i = 0; i < 12; i++)
 627                 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
 628         for (i = 0; i < 12; i++)
 629                 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
 630         for (i = 0; i < 12; i++)
 631                 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
 632         for (i = 0; i < 12; i++)
 633                 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
 634         for (i = 0; i < 12; i++)
 635                 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
 636         for (i = 0; i < 12; i++)
 637                 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
 638         for (i = 0; i < 12; i++)
 639                 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
 640 }
 641
 642 static int igb_get_eeprom_len(struct net_device *netdev)
 643 {
 644         struct igb_adapter *adapter = netdev_priv(netdev);
 645         return adapter->hw.nvm.word_size * 2;
 646 }
 647
 648 static int igb_get_eeprom(struct net_device *netdev,
 649                           struct ethtool_eeprom *eeprom, u8 *bytes)
 650 {
 651         struct igb_adapter *adapter = netdev_priv(netdev);
 652         struct e1000_hw *hw = &adapter->hw;
 653         u16 *eeprom_buff;
 654         int first_word, last_word;
 655         int ret_val = 0;
 656         u16 i;
 657
 658         if (eeprom->len == 0)
 659                 return -EINVAL;
 660
 661         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 662
 663         first_word = eeprom->offset >> 1;
 664         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 665
 666         eeprom_buff = kmalloc(sizeof(u16) *
 667                         (last_word - first_word + 1), GFP_KERNEL);
 668         if (!eeprom_buff)
 669                 return -ENOMEM;
 670
 671         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 672                 ret_val = hw->nvm.ops.read(hw, first_word,
 673                                             last_word - first_word + 1,
 674                                             eeprom_buff);
 675         else {
 676                 for (i = 0; i < last_word - first_word + 1; i++) {
 677                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 678                                                     &eeprom_buff[i]);
 679                         if (ret_val)
 680                                 break;
 681                 }
 682         }
 683
 684         /* Device's eeprom is always little-endian, word addressable */
 685         for (i = 0; i < last_word - first_word + 1; i++)
 686                 le16_to_cpus(&eeprom_buff[i]);
 687
 688         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 689                         eeprom->len);
 690         kfree(eeprom_buff);
 691
 692         return ret_val;
 693 }
 694
 695 static int igb_set_eeprom(struct net_device *netdev,
 696                           struct ethtool_eeprom *eeprom, u8 *bytes)
 697 {
 698         struct igb_adapter *adapter = netdev_priv(netdev);
 699         struct e1000_hw *hw = &adapter->hw;
 700         u16 *eeprom_buff;
 701         void *ptr;
 702         int max_len, first_word, last_word, ret_val = 0;
 703         u16 i;
 704
 705         if (eeprom->len == 0)
 706                 return -EOPNOTSUPP;
 707
 708         if (hw->mac.type == e1000_i211)
 709                 return -EOPNOTSUPP;
 710
 711         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 712                 return -EFAULT;
 713
 714         max_len = hw->nvm.word_size * 2;
 715
 716         first_word = eeprom->offset >> 1;
 717         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 718         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 719         if (!eeprom_buff)
 720                 return -ENOMEM;
 721
 722         ptr = (void *)eeprom_buff;
 723
 724         if (eeprom->offset & 1) {
 725                 /* need read/modify/write of first changed EEPROM word */
 726                 /* only the second byte of the word is being modified */
 727                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 728                                             &eeprom_buff[0]);
 729                 ptr++;
 730         }
 731         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 732                 /* need read/modify/write of last changed EEPROM word */
 733                 /* only the first byte of the word is being modified */
 734                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 735                                    &eeprom_buff[last_word - first_word]);
 736         }
 737
 738         /* Device's eeprom is always little-endian, word addressable */
 739         for (i = 0; i < last_word - first_word + 1; i++)
 740                 le16_to_cpus(&eeprom_buff[i]);
 741
 742         memcpy(ptr, bytes, eeprom->len);
 743
 744         for (i = 0; i < last_word - first_word + 1; i++)
 745                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 746
 747         ret_val = hw->nvm.ops.write(hw, first_word,
 748                                      last_word - first_word + 1, eeprom_buff);
 749
 750         /* Update the checksum over the first part of the EEPROM if needed
 751          * and flush shadow RAM for 82573 controllers */
 752         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
 753                 hw->nvm.ops.update(hw);
 754
 755         igb_set_fw_version(adapter);
 756         kfree(eeprom_buff);
 757         return ret_val;
 758 }
 759
 760 static void igb_get_drvinfo(struct net_device *netdev,
 761                             struct ethtool_drvinfo *drvinfo)
 762 {
 763         struct igb_adapter *adapter = netdev_priv(netdev);
 764
 765         strlcpy(drvinfo->driver,  igb_driver_name, sizeof(drvinfo->driver));
 766         strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
 767
 768         /*
 769          * EEPROM image version # is reported as firmware version # for
 770          * 82575 controllers
 771          */
 772         strlcpy(drvinfo->fw_version, adapter->fw_version,
 773                 sizeof(drvinfo->fw_version));
 774         strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
 775                 sizeof(drvinfo->bus_info));
 776         drvinfo->n_stats = IGB_STATS_LEN;
 777         drvinfo->testinfo_len = IGB_TEST_LEN;
 778         drvinfo->regdump_len = igb_get_regs_len(netdev);
 779         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 780 }
 781
 782 static void igb_get_ringparam(struct net_device *netdev,
 783                               struct ethtool_ringparam *ring)
 784 {
 785         struct igb_adapter *adapter = netdev_priv(netdev);
 786
 787         ring->rx_max_pending = IGB_MAX_RXD;
 788         ring->tx_max_pending = IGB_MAX_TXD;
 789         ring->rx_pending = adapter->rx_ring_count;
 790         ring->tx_pending = adapter->tx_ring_count;
 791 }
 792
 793 static int igb_set_ringparam(struct net_device *netdev,
 794                              struct ethtool_ringparam *ring)
 795 {
 796         struct igb_adapter *adapter = netdev_priv(netdev);
 797         struct igb_ring *temp_ring;
 798         int i, err = 0;
 799         u16 new_rx_count, new_tx_count;
 800
 801         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 802                 return -EINVAL;
 803
 804         new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
 805         new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
 806         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 807
 808         new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
 809         new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
 810         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 811
 812         if ((new_tx_count == adapter->tx_ring_count) &&
 813             (new_rx_count == adapter->rx_ring_count)) {
 814                 /* nothing to do */
 815                 return 0;
 816         }
 817
 818         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 819                 msleep(1);
 820
 821         if (!netif_running(adapter->netdev)) {
 822                 for (i = 0; i < adapter->num_tx_queues; i++)
 823                         adapter->tx_ring[i]->count = new_tx_count;
 824                 for (i = 0; i < adapter->num_rx_queues; i++)
 825                         adapter->rx_ring[i]->count = new_rx_count;
 826                 adapter->tx_ring_count = new_tx_count;
 827                 adapter->rx_ring_count = new_rx_count;
 828                 goto clear_reset;
 829         }
 830
 831         if (adapter->num_tx_queues > adapter->num_rx_queues)
 832                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
 833         else
 834                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
 835
 836         if (!temp_ring) {
 837                 err = -ENOMEM;
 838                 goto clear_reset;
 839         }
 840
 841         igb_down(adapter);
 842
 843         /*
 844          * We can't just free everything and then setup again,
 845          * because the ISRs in MSI-X mode get passed pointers
 846          * to the tx and rx ring structs.
 847          */
 848         if (new_tx_count != adapter->tx_ring_count) {
 849                 for (i = 0; i < adapter->num_tx_queues; i++) {
 850                         memcpy(&temp_ring[i], adapter->tx_ring[i],
 851                                sizeof(struct igb_ring));
 852
 853                         temp_ring[i].count = new_tx_count;
 854                         err = igb_setup_tx_resources(&temp_ring[i]);
 855                         if (err) {
 856                                 while (i) {
 857                                         i--;
 858                                         igb_free_tx_resources(&temp_ring[i]);
 859                                 }
 860                                 goto err_setup;
 861                         }
 862                 }
 863
 864                 for (i = 0; i < adapter->num_tx_queues; i++) {
 865                         igb_free_tx_resources(adapter->tx_ring[i]);
 866
 867                         memcpy(adapter->tx_ring[i], &temp_ring[i],
 868                                sizeof(struct igb_ring));
 869                 }
 870
 871                 adapter->tx_ring_count = new_tx_count;
 872         }
 873
 874         if (new_rx_count != adapter->rx_ring_count) {
 875                 for (i = 0; i < adapter->num_rx_queues; i++) {
 876                         memcpy(&temp_ring[i], adapter->rx_ring[i],
 877                                sizeof(struct igb_ring));
 878
 879                         temp_ring[i].count = new_rx_count;
 880                         err = igb_setup_rx_resources(&temp_ring[i]);
 881                         if (err) {
 882                                 while (i) {
 883                                         i--;
 884                                         igb_free_rx_resources(&temp_ring[i]);
 885                                 }
 886                                 goto err_setup;
 887                         }
 888
 889                 }
 890
 891                 for (i = 0; i < adapter->num_rx_queues; i++) {
 892                         igb_free_rx_resources(adapter->rx_ring[i]);
 893
 894                         memcpy(adapter->rx_ring[i], &temp_ring[i],
 895                                sizeof(struct igb_ring));
 896                 }
 897
 898                 adapter->rx_ring_count = new_rx_count;
 899         }
 900 err_setup:
 901         igb_up(adapter);
 902         vfree(temp_ring);
 903 clear_reset:
 904         clear_bit(__IGB_RESETTING, &adapter->state);
 905         return err;
 906 }
 907
 908 /* ethtool register test data */
 909 struct igb_reg_test {
 910         u16 reg;
 911         u16 reg_offset;
 912         u16 array_len;
 913         u16 test_type;
 914         u32 mask;
 915         u32 write;
 916 };
 917
 918 /* In the hardware, registers are laid out either singly, in arrays
 919  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 920  * most tests take place on arrays or single registers (handled
 921  * as a single-element array) and special-case the tables.
 922  * Table tests are always pattern tests.
 923  *
 924  * We also make provision for some required setup steps by specifying
 925  * registers to be written without any read-back testing.
 926  */
 927
 928 #define PATTERN_TEST    1
 929 #define SET_READ_TEST   2
 930 #define WRITE_NO_TEST   3
 931 #define TABLE32_TEST    4
 932 #define TABLE64_TEST_LO 5
 933 #define TABLE64_TEST_HI 6
 934
 935 /* i210 reg test */
 936 static struct igb_reg_test reg_test_i210[] = {
 937         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 938         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 939         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 940         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 941         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 942         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 943         /* RDH is read-only for i210, only test RDT. */
 944         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 945         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 946         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 947         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 948         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 949         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 950         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 951         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 952         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 953         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 954         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 955         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 956         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 957                                                 0xFFFFFFFF, 0xFFFFFFFF },
 958         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 959                                                 0x900FFFFF, 0xFFFFFFFF },
 960         { E1000_MTA,       0, 128, TABLE32_TEST,
 961                                                 0xFFFFFFFF, 0xFFFFFFFF },
 962         { 0, 0, 0, 0, 0 }
 963 };
 964
 965 /* i350 reg test */
 966 static struct igb_reg_test reg_test_i350[] = {
 967         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 968         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 969         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 970         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
 971         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 972         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 973         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 974         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 975         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 976         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 977         /* RDH is read-only for i350, only test RDT. */
 978         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 979         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 980         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 981         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 982         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 983         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 984         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 985         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 986         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 987         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 988         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 989         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 990         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 991         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 992         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 993         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 994         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 995         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 996                                                 0xFFFFFFFF, 0xFFFFFFFF },
 997         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 998                                                 0xC3FFFFFF, 0xFFFFFFFF },
 999         { E1000_RA2,       0, 16, TABLE64_TEST_LO,
1000                                                 0xFFFFFFFF, 0xFFFFFFFF },
1001         { E1000_RA2,       0, 16, TABLE64_TEST_HI,
1002                                                 0xC3FFFFFF, 0xFFFFFFFF },
1003         { E1000_MTA,       0, 128, TABLE32_TEST,
1004                                                 0xFFFFFFFF, 0xFFFFFFFF },
1005         { 0, 0, 0, 0 }
1006 };
1007
1008 /* 82580 reg test */
1009 static struct igb_reg_test reg_test_82580[] = {
1010         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1011         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1012         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1013         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1014         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1015         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1016         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1017         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1018         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1019         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1020         /* RDH is read-only for 82580, only test RDT. */
1021         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1022         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1023         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1024         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1025         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1026         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1027         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1028         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1029         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1030         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1031         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1032         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1033         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1034         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1035         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1036         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1037         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1038         { E1000_RA,        0, 16, TABLE64_TEST_LO,
1039                                                 0xFFFFFFFF, 0xFFFFFFFF },
1040         { E1000_RA,        0, 16, TABLE64_TEST_HI,
1041                                                 0x83FFFFFF, 0xFFFFFFFF },
1042         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
1043                                                 0xFFFFFFFF, 0xFFFFFFFF },
1044         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
1045                                                 0x83FFFFFF, 0xFFFFFFFF },
1046         { E1000_MTA,       0, 128, TABLE32_TEST,
1047                                                 0xFFFFFFFF, 0xFFFFFFFF },
1048         { 0, 0, 0, 0 }
1049 };
1050
1051 /* 82576 reg test */
1052 static struct igb_reg_test reg_test_82576[] = {
1053         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1054         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1055         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1056         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1057         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1058         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1059         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1060         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1061         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1062         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1063         /* Enable all RX queues before testing. */
1064         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1065         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1066         /* RDH is read-only for 82576, only test RDT. */
1067         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1068         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1069         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
1070         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
1071         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1072         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1073         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1074         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1075         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1076         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1077         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1078         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1079         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1080         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1081         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1082         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1083         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1084         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1085         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1086         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1087         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1088         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1089         { 0, 0, 0, 0 }
1090 };
1091
1092 /* 82575 register test */
1093 static struct igb_reg_test reg_test_82575[] = {
1094         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1095         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1096         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1097         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1098         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1099         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1100         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1101         /* Enable all four RX queues before testing. */
1102         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1103         /* RDH is read-only for 82575, only test RDT. */
1104         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1105         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1106         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1107         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1108         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1109         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1110         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1111         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1112         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1113         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1114         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1115         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1116         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1117         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1118         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1119         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1120         { 0, 0, 0, 0 }
1121 };
1122
1123 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1124                              int reg, u32 mask, u32 write)
1125 {
1126         struct e1000_hw *hw = &adapter->hw;
1127         u32 pat, val;
1128         static const u32 _test[] =
1129                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1130         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1131                 wr32(reg, (_test[pat] & write));
1132                 val = rd32(reg) & mask;
1133                 if (val != (_test[pat] & write & mask)) {
1134                         dev_err(&adapter->pdev->dev,
1135                                 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1136                                 reg, val, (_test[pat] & write & mask));
1137                         *data = reg;
1138                         return 1;
1139                 }
1140         }
1141
1142         return 0;
1143 }
1144
1145 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1146                               int reg, u32 mask, u32 write)
1147 {
1148         struct e1000_hw *hw = &adapter->hw;
1149         u32 val;
1150         wr32(reg, write & mask);
1151         val = rd32(reg);
1152         if ((write & mask) != (val & mask)) {
1153                 dev_err(&adapter->pdev->dev,
1154                         "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg,
1155                         (val & mask), (write & mask));
1156                 *data = reg;
1157                 return 1;
1158         }
1159
1160         return 0;
1161 }
1162
1163 #define REG_PATTERN_TEST(reg, mask, write) \
1164         do { \
1165                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1166                         return 1; \
1167         } while (0)
1168
1169 #define REG_SET_AND_CHECK(reg, mask, write) \
1170         do { \
1171                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1172                         return 1; \
1173         } while (0)
1174
1175 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1176 {
1177         struct e1000_hw *hw = &adapter->hw;
1178         struct igb_reg_test *test;
1179         u32 value, before, after;
1180         u32 i, toggle;
1181
1182         switch (adapter->hw.mac.type) {
1183         case e1000_i350:
1184                 test = reg_test_i350;
1185                 toggle = 0x7FEFF3FF;
1186                 break;
1187         case e1000_i210:
1188         case e1000_i211:
1189                 test = reg_test_i210;
1190                 toggle = 0x7FEFF3FF;
1191                 break;
1192         case e1000_82580:
1193                 test = reg_test_82580;
1194                 toggle = 0x7FEFF3FF;
1195                 break;
1196         case e1000_82576:
1197                 test = reg_test_82576;
1198                 toggle = 0x7FFFF3FF;
1199                 break;
1200         default:
1201                 test = reg_test_82575;
1202                 toggle = 0x7FFFF3FF;
1203                 break;
1204         }
1205
1206         /* Because the status register is such a special case,
1207          * we handle it separately from the rest of the register
1208          * tests.  Some bits are read-only, some toggle, and some
1209          * are writable on newer MACs.
1210          */
1211         before = rd32(E1000_STATUS);
1212         value = (rd32(E1000_STATUS) & toggle);
1213         wr32(E1000_STATUS, toggle);
1214         after = rd32(E1000_STATUS) & toggle;
1215         if (value != after) {
1216                 dev_err(&adapter->pdev->dev,
1217                         "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1218                         after, value);
1219                 *data = 1;
1220                 return 1;
1221         }
1222         /* restore previous status */
1223         wr32(E1000_STATUS, before);
1224
1225         /* Perform the remainder of the register test, looping through
1226          * the test table until we either fail or reach the null entry.
1227          */
1228         while (test->reg) {
1229                 for (i = 0; i < test->array_len; i++) {
1230                         switch (test->test_type) {
1231                         case PATTERN_TEST:
1232                                 REG_PATTERN_TEST(test->reg +
1233                                                 (i * test->reg_offset),
1234                                                 test->mask,
1235                                                 test->write);
1236                                 break;
1237                         case SET_READ_TEST:
1238                                 REG_SET_AND_CHECK(test->reg +
1239                                                 (i * test->reg_offset),
1240                                                 test->mask,
1241                                                 test->write);
1242                                 break;
1243                         case WRITE_NO_TEST:
1244                                 writel(test->write,
1245                                     (adapter->hw.hw_addr + test->reg)
1246                                         + (i * test->reg_offset));
1247                                 break;
1248                         case TABLE32_TEST:
1249                                 REG_PATTERN_TEST(test->reg + (i * 4),
1250                                                 test->mask,
1251                                                 test->write);
1252                                 break;
1253                         case TABLE64_TEST_LO:
1254                                 REG_PATTERN_TEST(test->reg + (i * 8),
1255                                                 test->mask,
1256                                                 test->write);
1257                                 break;
1258                         case TABLE64_TEST_HI:
1259                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1260                                                 test->mask,
1261                                                 test->write);
1262                                 break;
1263                         }
1264                 }
1265                 test++;
1266         }
1267
1268         *data = 0;
1269         return 0;
1270 }
1271
1272 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1273 {
1274         *data = 0;
1275
1276         /* Validate eeprom on all parts but i211 */
1277         if (adapter->hw.mac.type != e1000_i211) {
1278                 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1279                         *data = 2;
1280         }
1281
1282         return *data;
1283 }
1284
1285 static irqreturn_t igb_test_intr(int irq, void *data)
1286 {
1287         struct igb_adapter *adapter = (struct igb_adapter *) data;
1288         struct e1000_hw *hw = &adapter->hw;
1289
1290         adapter->test_icr |= rd32(E1000_ICR);
1291
1292         return IRQ_HANDLED;
1293 }
1294
1295 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1296 {
1297         struct e1000_hw *hw = &adapter->hw;
1298         struct net_device *netdev = adapter->netdev;
1299         u32 mask, ics_mask, i = 0, shared_int = true;
1300         u32 irq = adapter->pdev->irq;
1301
1302         *data = 0;
1303
1304         /* Hook up test interrupt handler just for this test */
1305         if (adapter->msix_entries) {
1306                 if (request_irq(adapter->msix_entries[0].vector,
1307                                 igb_test_intr, 0, netdev->name, adapter)) {
1308                         *data = 1;
1309                         return -1;
1310                 }
1311         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1312                 shared_int = false;
1313                 if (request_irq(irq,
1314                                 igb_test_intr, 0, netdev->name, adapter)) {
1315                         *data = 1;
1316                         return -1;
1317                 }
1318         } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1319                                 netdev->name, adapter)) {
1320                 shared_int = false;
1321         } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1322                  netdev->name, adapter)) {
1323                 *data = 1;
1324                 return -1;
1325         }
1326         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1327                 (shared_int ? "shared" : "unshared"));
1328
1329         /* Disable all the interrupts */
1330         wr32(E1000_IMC, ~0);
1331         wrfl();
1332         msleep(10);
1333
1334         /* Define all writable bits for ICS */
1335         switch (hw->mac.type) {
1336         case e1000_82575:
1337                 ics_mask = 0x37F47EDD;
1338                 break;
1339         case e1000_82576:
1340                 ics_mask = 0x77D4FBFD;
1341                 break;
1342         case e1000_82580:
1343                 ics_mask = 0x77DCFED5;
1344                 break;
1345         case e1000_i350:
1346         case e1000_i210:
1347         case e1000_i211:
1348                 ics_mask = 0x77DCFED5;
1349                 break;
1350         default:
1351                 ics_mask = 0x7FFFFFFF;
1352                 break;
1353         }
1354
1355         /* Test each interrupt */
1356         for (; i < 31; i++) {
1357                 /* Interrupt to test */
1358                 mask = 1 << i;
1359
1360                 if (!(mask & ics_mask))
1361                         continue;
1362
1363                 if (!shared_int) {
1364                         /* Disable the interrupt to be reported in
1365                          * the cause register and then force the same
1366                          * interrupt and see if one gets posted.  If
1367                          * an interrupt was posted to the bus, the
1368                          * test failed.
1369                          */
1370                         adapter->test_icr = 0;
1371
1372                         /* Flush any pending interrupts */
1373                         wr32(E1000_ICR, ~0);
1374
1375                         wr32(E1000_IMC, mask);
1376                         wr32(E1000_ICS, mask);
1377                         wrfl();
1378                         msleep(10);
1379
1380                         if (adapter->test_icr & mask) {
1381                                 *data = 3;
1382                                 break;
1383                         }
1384                 }
1385
1386                 /* Enable the interrupt to be reported in
1387                  * the cause register and then force the same
1388                  * interrupt and see if one gets posted.  If
1389                  * an interrupt was not posted to the bus, the
1390                  * test failed.
1391                  */
1392                 adapter->test_icr = 0;
1393
1394                 /* Flush any pending interrupts */
1395                 wr32(E1000_ICR, ~0);
1396
1397                 wr32(E1000_IMS, mask);
1398                 wr32(E1000_ICS, mask);
1399                 wrfl();
1400                 msleep(10);
1401
1402                 if (!(adapter->test_icr & mask)) {
1403                         *data = 4;
1404                         break;
1405                 }
1406
1407                 if (!shared_int) {
1408                         /* Disable the other interrupts to be reported in
1409                          * the cause register and then force the other
1410                          * interrupts and see if any get posted.  If
1411                          * an interrupt was posted to the bus, the
1412                          * test failed.
1413                          */
1414                         adapter->test_icr = 0;
1415
1416                         /* Flush any pending interrupts */
1417                         wr32(E1000_ICR, ~0);
1418
1419                         wr32(E1000_IMC, ~mask);
1420                         wr32(E1000_ICS, ~mask);
1421                         wrfl();
1422                         msleep(10);
1423
1424                         if (adapter->test_icr & mask) {
1425                                 *data = 5;
1426                                 break;
1427                         }
1428                 }
1429         }
1430
1431         /* Disable all the interrupts */
1432         wr32(E1000_IMC, ~0);
1433         wrfl();
1434         msleep(10);
1435
1436         /* Unhook test interrupt handler */
1437         if (adapter->msix_entries)
1438                 free_irq(adapter->msix_entries[0].vector, adapter);
1439         else
1440                 free_irq(irq, adapter);
1441
1442         return *data;
1443 }
1444
1445 static void igb_free_desc_rings(struct igb_adapter *adapter)
1446 {
1447         igb_free_tx_resources(&adapter->test_tx_ring);
1448         igb_free_rx_resources(&adapter->test_rx_ring);
1449 }
1450
1451 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1452 {
1453         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1454         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1455         struct e1000_hw *hw = &adapter->hw;
1456         int ret_val;
1457
1458         /* Setup Tx descriptor ring and Tx buffers */
1459         tx_ring->count = IGB_DEFAULT_TXD;
1460         tx_ring->dev = &adapter->pdev->dev;
1461         tx_ring->netdev = adapter->netdev;
1462         tx_ring->reg_idx = adapter->vfs_allocated_count;
1463
1464         if (igb_setup_tx_resources(tx_ring)) {
1465                 ret_val = 1;
1466                 goto err_nomem;
1467         }
1468
1469         igb_setup_tctl(adapter);
1470         igb_configure_tx_ring(adapter, tx_ring);
1471
1472         /* Setup Rx descriptor ring and Rx buffers */
1473         rx_ring->count = IGB_DEFAULT_RXD;
1474         rx_ring->dev = &adapter->pdev->dev;
1475         rx_ring->netdev = adapter->netdev;
1476         rx_ring->reg_idx = adapter->vfs_allocated_count;
1477
1478         if (igb_setup_rx_resources(rx_ring)) {
1479                 ret_val = 3;
1480                 goto err_nomem;
1481         }
1482
1483         /* set the default queue to queue 0 of PF */
1484         wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1485
1486         /* enable receive ring */
1487         igb_setup_rctl(adapter);
1488         igb_configure_rx_ring(adapter, rx_ring);
1489
1490         igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1491
1492         return 0;
1493
1494 err_nomem:
1495         igb_free_desc_rings(adapter);
1496         return ret_val;
1497 }
1498
1499 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1500 {
1501         struct e1000_hw *hw = &adapter->hw;
1502
1503         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1504         igb_write_phy_reg(hw, 29, 0x001F);
1505         igb_write_phy_reg(hw, 30, 0x8FFC);
1506         igb_write_phy_reg(hw, 29, 0x001A);
1507         igb_write_phy_reg(hw, 30, 0x8FF0);
1508 }
1509
1510 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1511 {
1512         struct e1000_hw *hw = &adapter->hw;
1513         u32 ctrl_reg = 0;
1514         u16 phy_reg = 0;
1515
1516         hw->mac.autoneg = false;
1517
1518         switch (hw->phy.type) {
1519         case e1000_phy_m88:
1520                 /* Auto-MDI/MDIX Off */
1521                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1522                 /* reset to update Auto-MDI/MDIX */
1523                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1524                 /* autoneg off */
1525                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1526                 break;
1527         case e1000_phy_82580:
1528                 /* enable MII loopback */
1529                 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1530                 break;
1531         case e1000_phy_i210:
1532                 /* set loopback speed in PHY */
1533                 igb_read_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2),
1534                                         &phy_reg);
1535                 phy_reg |= GS40G_MAC_SPEED_1G;
1536                 igb_write_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2),
1537                                         phy_reg);
1538                 ctrl_reg = rd32(E1000_CTRL_EXT);
1539         default:
1540                 break;
1541         }
1542
1543         /* add small delay to avoid loopback test failure */
1544         msleep(50);
1545
1546         /* force 1000, set loopback */
1547         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1548
1549         /* Now set up the MAC to the same speed/duplex as the PHY. */
1550         ctrl_reg = rd32(E1000_CTRL);
1551         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1552         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1553                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1554                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1555                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1556                      E1000_CTRL_SLU);    /* Set link up enable bit */
1557
1558         if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210))
1559                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1560
1561         wr32(E1000_CTRL, ctrl_reg);
1562
1563         /* Disable the receiver on the PHY so when a cable is plugged in, the
1564          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1565          */
1566         if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210))
1567                 igb_phy_disable_receiver(adapter);
1568
1569         udelay(500);
1570
1571         return 0;
1572 }
1573
1574 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1575 {
1576         return igb_integrated_phy_loopback(adapter);
1577 }
1578
1579 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1580 {
1581         struct e1000_hw *hw = &adapter->hw;
1582         u32 reg;
1583
1584         reg = rd32(E1000_CTRL_EXT);
1585
1586         /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1587         if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1588                 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1589                 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1590                 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1591                 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1592
1593                         /* Enable DH89xxCC MPHY for near end loopback */
1594                         reg = rd32(E1000_MPHY_ADDR_CTL);
1595                         reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1596                         E1000_MPHY_PCS_CLK_REG_OFFSET;
1597                         wr32(E1000_MPHY_ADDR_CTL, reg);
1598
1599                         reg = rd32(E1000_MPHY_DATA);
1600                         reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1601                         wr32(E1000_MPHY_DATA, reg);
1602                 }
1603
1604                 reg = rd32(E1000_RCTL);
1605                 reg |= E1000_RCTL_LBM_TCVR;
1606                 wr32(E1000_RCTL, reg);
1607
1608                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1609
1610                 reg = rd32(E1000_CTRL);
1611                 reg &= ~(E1000_CTRL_RFCE |
1612                          E1000_CTRL_TFCE |
1613                          E1000_CTRL_LRST);
1614                 reg |= E1000_CTRL_SLU |
1615                        E1000_CTRL_FD;
1616                 wr32(E1000_CTRL, reg);
1617
1618                 /* Unset switch control to serdes energy detect */
1619                 reg = rd32(E1000_CONNSW);
1620                 reg &= ~E1000_CONNSW_ENRGSRC;
1621                 wr32(E1000_CONNSW, reg);
1622
1623                 /* Set PCS register for forced speed */
1624                 reg = rd32(E1000_PCS_LCTL);
1625                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1626                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1627                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1628                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1629                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1630                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1631                 wr32(E1000_PCS_LCTL, reg);
1632
1633                 return 0;
1634         }
1635
1636         return igb_set_phy_loopback(adapter);
1637 }
1638
1639 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1640 {
1641         struct e1000_hw *hw = &adapter->hw;
1642         u32 rctl;
1643         u16 phy_reg;
1644
1645         if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1646         (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1647         (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1648         (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1649                 u32 reg;
1650
1651                 /* Disable near end loopback on DH89xxCC */
1652                 reg = rd32(E1000_MPHY_ADDR_CTL);
1653                 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1654                 E1000_MPHY_PCS_CLK_REG_OFFSET;
1655                 wr32(E1000_MPHY_ADDR_CTL, reg);
1656
1657                 reg = rd32(E1000_MPHY_DATA);
1658                 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1659                 wr32(E1000_MPHY_DATA, reg);
1660         }
1661
1662         rctl = rd32(E1000_RCTL);
1663         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1664         wr32(E1000_RCTL, rctl);
1665
1666         hw->mac.autoneg = true;
1667         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1668         if (phy_reg & MII_CR_LOOPBACK) {
1669                 phy_reg &= ~MII_CR_LOOPBACK;
1670                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1671                 igb_phy_sw_reset(hw);
1672         }
1673 }
1674
1675 static void igb_create_lbtest_frame(struct sk_buff *skb,
1676                                     unsigned int frame_size)
1677 {
1678         memset(skb->data, 0xFF, frame_size);
1679         frame_size /= 2;
1680         memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1681         memset(&skb->data[frame_size + 10], 0xBE, 1);
1682         memset(&skb->data[frame_size + 12], 0xAF, 1);
1683 }
1684
1685 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1686 {
1687         frame_size /= 2;
1688         if (*(skb->data + 3) == 0xFF) {
1689                 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1690                    (*(skb->data + frame_size + 12) == 0xAF)) {
1691                         return 0;
1692                 }
1693         }
1694         return 13;
1695 }
1696
1697 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1698                                 struct igb_ring *tx_ring,
1699                                 unsigned int size)
1700 {
1701         union e1000_adv_rx_desc *rx_desc;
1702         struct igb_rx_buffer *rx_buffer_info;
1703         struct igb_tx_buffer *tx_buffer_info;
1704         struct netdev_queue *txq;
1705         u16 rx_ntc, tx_ntc, count = 0;
1706         unsigned int total_bytes = 0, total_packets = 0;
1707
1708         /* initialize next to clean and descriptor values */
1709         rx_ntc = rx_ring->next_to_clean;
1710         tx_ntc = tx_ring->next_to_clean;
1711         rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1712
1713         while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
1714                 /* check rx buffer */
1715                 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1716
1717                 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
1718                 dma_unmap_single(rx_ring->dev,
1719                                  rx_buffer_info->dma,
1720                                  IGB_RX_HDR_LEN,
1721                                  DMA_FROM_DEVICE);
1722                 rx_buffer_info->dma = 0;
1723
1724                 /* verify contents of skb */
1725                 if (!igb_check_lbtest_frame(rx_buffer_info->skb, size))
1726                         count++;
1727
1728                 /* unmap buffer on tx side */
1729                 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1730                 total_bytes += tx_buffer_info->bytecount;
1731                 total_packets += tx_buffer_info->gso_segs;
1732                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1733
1734                 /* increment rx/tx next to clean counters */
1735                 rx_ntc++;
1736                 if (rx_ntc == rx_ring->count)
1737                         rx_ntc = 0;
1738                 tx_ntc++;
1739                 if (tx_ntc == tx_ring->count)
1740                         tx_ntc = 0;
1741
1742                 /* fetch next descriptor */
1743                 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1744         }
1745
1746         txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
1747         netdev_tx_completed_queue(txq, total_packets, total_bytes);
1748
1749         /* re-map buffers to ring, store next to clean values */
1750         igb_alloc_rx_buffers(rx_ring, count);
1751         rx_ring->next_to_clean = rx_ntc;
1752         tx_ring->next_to_clean = tx_ntc;
1753
1754         return count;
1755 }
1756
1757 static int igb_run_loopback_test(struct igb_adapter *adapter)
1758 {
1759         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1760         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1761         u16 i, j, lc, good_cnt;
1762         int ret_val = 0;
1763         unsigned int size = IGB_RX_HDR_LEN;
1764         netdev_tx_t tx_ret_val;
1765         struct sk_buff *skb;
1766
1767         /* allocate test skb */
1768         skb = alloc_skb(size, GFP_KERNEL);
1769         if (!skb)
1770                 return 11;
1771
1772         /* place data into test skb */
1773         igb_create_lbtest_frame(skb, size);
1774         skb_put(skb, size);
1775
1776         /*
1777          * Calculate the loop count based on the largest descriptor ring
1778          * The idea is to wrap the largest ring a number of times using 64
1779          * send/receive pairs during each loop
1780          */
1781
1782         if (rx_ring->count <= tx_ring->count)
1783                 lc = ((tx_ring->count / 64) * 2) + 1;
1784         else
1785                 lc = ((rx_ring->count / 64) * 2) + 1;
1786
1787         for (j = 0; j <= lc; j++) { /* loop count loop */
1788                 /* reset count of good packets */
1789                 good_cnt = 0;
1790
1791                 /* place 64 packets on the transmit queue*/
1792                 for (i = 0; i < 64; i++) {
1793                         skb_get(skb);
1794                         tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1795                         if (tx_ret_val == NETDEV_TX_OK)
1796                                 good_cnt++;
1797                 }
1798
1799                 if (good_cnt != 64) {
1800                         ret_val = 12;
1801                         break;
1802                 }
1803
1804                 /* allow 200 milliseconds for packets to go from tx to rx */
1805                 msleep(200);
1806
1807                 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1808                 if (good_cnt != 64) {
1809                         ret_val = 13;
1810                         break;
1811                 }
1812         } /* end loop count loop */
1813
1814         /* free the original skb */
1815         kfree_skb(skb);
1816
1817         return ret_val;
1818 }
1819
1820 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1821 {
1822         /* PHY loopback cannot be performed if SoL/IDER
1823          * sessions are active */
1824         if (igb_check_reset_block(&adapter->hw)) {
1825                 dev_err(&adapter->pdev->dev,
1826                         "Cannot do PHY loopback test when SoL/IDER is active.\n");
1827                 *data = 0;
1828                 goto out;
1829         }
1830         if ((adapter->hw.mac.type == e1000_i210)
1831                 || (adapter->hw.mac.type == e1000_i211)) {
1832                 dev_err(&adapter->pdev->dev,
1833                         "Loopback test not supported on this part at this time.\n");
1834                 *data = 0;
1835                 goto out;
1836         }
1837         *data = igb_setup_desc_rings(adapter);
1838         if (*data)
1839                 goto out;
1840         *data = igb_setup_loopback_test(adapter);
1841         if (*data)
1842                 goto err_loopback;
1843         *data = igb_run_loopback_test(adapter);
1844         igb_loopback_cleanup(adapter);
1845
1846 err_loopback:
1847         igb_free_desc_rings(adapter);
1848 out:
1849         return *data;
1850 }
1851
1852 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1853 {
1854         struct e1000_hw *hw = &adapter->hw;
1855         *data = 0;
1856         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1857                 int i = 0;
1858                 hw->mac.serdes_has_link = false;
1859
1860                 /* On some blade server designs, link establishment
1861                  * could take as long as 2-3 minutes */
1862                 do {
1863                         hw->mac.ops.check_for_link(&adapter->hw);
1864                         if (hw->mac.serdes_has_link)
1865                                 return *data;
1866                         msleep(20);
1867                 } while (i++ < 3750);
1868
1869                 *data = 1;
1870         } else {
1871                 hw->mac.ops.check_for_link(&adapter->hw);
1872                 if (hw->mac.autoneg)
1873                         msleep(4000);
1874
1875                 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1876                         *data = 1;
1877         }
1878         return *data;
1879 }
1880
1881 static void igb_diag_test(struct net_device *netdev,
1882                           struct ethtool_test *eth_test, u64 *data)
1883 {
1884         struct igb_adapter *adapter = netdev_priv(netdev);
1885         u16 autoneg_advertised;
1886         u8 forced_speed_duplex, autoneg;
1887         bool if_running = netif_running(netdev);
1888
1889         set_bit(__IGB_TESTING, &adapter->state);
1890         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1891                 /* Offline tests */
1892
1893                 /* save speed, duplex, autoneg settings */
1894                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1895                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1896                 autoneg = adapter->hw.mac.autoneg;
1897
1898                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1899
1900                 /* power up link for link test */
1901                 igb_power_up_link(adapter);
1902
1903                 /* Link test performed before hardware reset so autoneg doesn't
1904                  * interfere with test result */
1905                 if (igb_link_test(adapter, &data[4]))
1906                         eth_test->flags |= ETH_TEST_FL_FAILED;
1907
1908                 if (if_running)
1909                         /* indicate we're in test mode */
1910                         dev_close(netdev);
1911                 else
1912                         igb_reset(adapter);
1913
1914                 if (igb_reg_test(adapter, &data[0]))
1915                         eth_test->flags |= ETH_TEST_FL_FAILED;
1916
1917                 igb_reset(adapter);
1918                 if (igb_eeprom_test(adapter, &data[1]))
1919                         eth_test->flags |= ETH_TEST_FL_FAILED;
1920
1921                 igb_reset(adapter);
1922                 if (igb_intr_test(adapter, &data[2]))
1923                         eth_test->flags |= ETH_TEST_FL_FAILED;
1924
1925                 igb_reset(adapter);
1926                 /* power up link for loopback test */
1927                 igb_power_up_link(adapter);
1928                 if (igb_loopback_test(adapter, &data[3]))
1929                         eth_test->flags |= ETH_TEST_FL_FAILED;
1930
1931                 /* restore speed, duplex, autoneg settings */
1932                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1933                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1934                 adapter->hw.mac.autoneg = autoneg;
1935
1936                 /* force this routine to wait until autoneg complete/timeout */
1937                 adapter->hw.phy.autoneg_wait_to_complete = true;
1938                 igb_reset(adapter);
1939                 adapter->hw.phy.autoneg_wait_to_complete = false;
1940
1941                 clear_bit(__IGB_TESTING, &adapter->state);
1942                 if (if_running)
1943                         dev_open(netdev);
1944         } else {
1945                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1946
1947                 /* PHY is powered down when interface is down */
1948                 if (if_running && igb_link_test(adapter, &data[4]))
1949                         eth_test->flags |= ETH_TEST_FL_FAILED;
1950                 else
1951                         data[4] = 0;
1952
1953                 /* Online tests aren't run; pass by default */
1954                 data[0] = 0;
1955                 data[1] = 0;
1956                 data[2] = 0;
1957                 data[3] = 0;
1958
1959                 clear_bit(__IGB_TESTING, &adapter->state);
1960         }
1961         msleep_interruptible(4 * 1000);
1962 }
1963
1964 static int igb_wol_exclusion(struct igb_adapter *adapter,
1965                              struct ethtool_wolinfo *wol)
1966 {
1967         struct e1000_hw *hw = &adapter->hw;
1968         int retval = 1; /* fail by default */
1969
1970         switch (hw->device_id) {
1971         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1972                 /* WoL not supported */
1973                 wol->supported = 0;
1974                 break;
1975         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1976         case E1000_DEV_ID_82576_FIBER:
1977         case E1000_DEV_ID_82576_SERDES:
1978                 /* Wake events not supported on port B */
1979                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1980                         wol->supported = 0;
1981                         break;
1982                 }
1983                 /* return success for non excluded adapter ports */
1984                 retval = 0;
1985                 break;
1986         case E1000_DEV_ID_82576_QUAD_COPPER:
1987         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
1988                 /* quad port adapters only support WoL on port A */
1989                 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1990                         wol->supported = 0;
1991                         break;
1992                 }
1993                 /* return success for non excluded adapter ports */
1994                 retval = 0;
1995                 break;
1996         default:
1997                 /* dual port cards only support WoL on port A from now on
1998                  * unless it was enabled in the eeprom for port B
1999                  * so exclude FUNC_1 ports from having WoL enabled */
2000                 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
2001                     !adapter->eeprom_wol) {
2002                         wol->supported = 0;
2003                         break;
2004                 }
2005
2006                 retval = 0;
2007         }
2008
2009         return retval;
2010 }
2011
2012 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2013 {
2014         struct igb_adapter *adapter = netdev_priv(netdev);
2015
2016         wol->supported = WAKE_UCAST | WAKE_MCAST |
2017                          WAKE_BCAST | WAKE_MAGIC |
2018                          WAKE_PHY;
2019         wol->wolopts = 0;
2020
2021         /* this function will set ->supported = 0 and return 1 if wol is not
2022          * supported by this hardware */
2023         if (igb_wol_exclusion(adapter, wol) ||
2024             !device_can_wakeup(&adapter->pdev->dev))
2025                 return;
2026
2027         /* apply any specific unsupported masks here */
2028         switch (adapter->hw.device_id) {
2029         default:
2030                 break;
2031         }
2032
2033         if (adapter->wol & E1000_WUFC_EX)
2034                 wol->wolopts |= WAKE_UCAST;
2035         if (adapter->wol & E1000_WUFC_MC)
2036                 wol->wolopts |= WAKE_MCAST;
2037         if (adapter->wol & E1000_WUFC_BC)
2038                 wol->wolopts |= WAKE_BCAST;
2039         if (adapter->wol & E1000_WUFC_MAG)
2040                 wol->wolopts |= WAKE_MAGIC;
2041         if (adapter->wol & E1000_WUFC_LNKC)
2042                 wol->wolopts |= WAKE_PHY;
2043 }
2044
2045 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2046 {
2047         struct igb_adapter *adapter = netdev_priv(netdev);
2048
2049         if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2050                 return -EOPNOTSUPP;
2051
2052         if (igb_wol_exclusion(adapter, wol) ||
2053             !device_can_wakeup(&adapter->pdev->dev))
2054                 return wol->wolopts ? -EOPNOTSUPP : 0;
2055
2056         /* these settings will always override what we currently have */
2057         adapter->wol = 0;
2058
2059         if (wol->wolopts & WAKE_UCAST)
2060                 adapter->wol |= E1000_WUFC_EX;
2061         if (wol->wolopts & WAKE_MCAST)
2062                 adapter->wol |= E1000_WUFC_MC;
2063         if (wol->wolopts & WAKE_BCAST)
2064                 adapter->wol |= E1000_WUFC_BC;
2065         if (wol->wolopts & WAKE_MAGIC)
2066                 adapter->wol |= E1000_WUFC_MAG;
2067         if (wol->wolopts & WAKE_PHY)
2068                 adapter->wol |= E1000_WUFC_LNKC;
2069         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2070
2071         return 0;
2072 }
2073
2074 /* bit defines for adapter->led_status */
2075 #define IGB_LED_ON              0
2076
2077 static int igb_set_phys_id(struct net_device *netdev,
2078                            enum ethtool_phys_id_state state)
2079 {
2080         struct igb_adapter *adapter = netdev_priv(netdev);
2081         struct e1000_hw *hw = &adapter->hw;
2082
2083         switch (state) {
2084         case ETHTOOL_ID_ACTIVE:
2085                 igb_blink_led(hw);
2086                 return 2;
2087         case ETHTOOL_ID_ON:
2088                 igb_blink_led(hw);
2089                 break;
2090         case ETHTOOL_ID_OFF:
2091                 igb_led_off(hw);
2092                 break;
2093         case ETHTOOL_ID_INACTIVE:
2094                 igb_led_off(hw);
2095                 clear_bit(IGB_LED_ON, &adapter->led_status);
2096                 igb_cleanup_led(hw);
2097                 break;
2098         }
2099
2100         return 0;
2101 }
2102
2103 static int igb_set_coalesce(struct net_device *netdev,
2104                             struct ethtool_coalesce *ec)
2105 {
2106         struct igb_adapter *adapter = netdev_priv(netdev);
2107         int i;
2108
2109         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2110             ((ec->rx_coalesce_usecs > 3) &&
2111              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2112             (ec->rx_coalesce_usecs == 2))
2113                 return -EINVAL;
2114
2115         if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2116             ((ec->tx_coalesce_usecs > 3) &&
2117              (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2118             (ec->tx_coalesce_usecs == 2))
2119                 return -EINVAL;
2120
2121         if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2122                 return -EINVAL;
2123
2124         /* If ITR is disabled, disable DMAC */
2125         if (ec->rx_coalesce_usecs == 0) {
2126                 if (adapter->flags & IGB_FLAG_DMAC)
2127                         adapter->flags &= ~IGB_FLAG_DMAC;
2128         }
2129
2130         /* convert to rate of irq's per second */
2131         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2132                 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2133         else
2134                 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2135
2136         /* convert to rate of irq's per second */
2137         if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2138                 adapter->tx_itr_setting = adapter->rx_itr_setting;
2139         else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2140                 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2141         else
2142                 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2143
2144         for (i = 0; i < adapter->num_q_vectors; i++) {
2145                 struct igb_q_vector *q_vector = adapter->q_vector[i];
2146                 q_vector->tx.work_limit = adapter->tx_work_limit;
2147                 if (q_vector->rx.ring)
2148                         q_vector->itr_val = adapter->rx_itr_setting;
2149                 else
2150                         q_vector->itr_val = adapter->tx_itr_setting;
2151                 if (q_vector->itr_val && q_vector->itr_val <= 3)
2152                         q_vector->itr_val = IGB_START_ITR;
2153                 q_vector->set_itr = 1;
2154         }
2155
2156         return 0;
2157 }
2158
2159 static int igb_get_coalesce(struct net_device *netdev,
2160                             struct ethtool_coalesce *ec)
2161 {
2162         struct igb_adapter *adapter = netdev_priv(netdev);
2163
2164         if (adapter->rx_itr_setting <= 3)
2165                 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2166         else
2167                 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2168
2169         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2170                 if (adapter->tx_itr_setting <= 3)
2171                         ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2172                 else
2173                         ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2174         }
2175
2176         return 0;
2177 }
2178
2179 static int igb_nway_reset(struct net_device *netdev)
2180 {
2181         struct igb_adapter *adapter = netdev_priv(netdev);
2182         if (netif_running(netdev))
2183                 igb_reinit_locked(adapter);
2184         return 0;
2185 }
2186
2187 static int igb_get_sset_count(struct net_device *netdev, int sset)
2188 {
2189         switch (sset) {
2190         case ETH_SS_STATS:
2191                 return IGB_STATS_LEN;
2192         case ETH_SS_TEST:
2193                 return IGB_TEST_LEN;
2194         default:
2195                 return -ENOTSUPP;
2196         }
2197 }
2198
2199 static void igb_get_ethtool_stats(struct net_device *netdev,
2200                                   struct ethtool_stats *stats, u64 *data)
2201 {
2202         struct igb_adapter *adapter = netdev_priv(netdev);
2203         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2204         unsigned int start;
2205         struct igb_ring *ring;
2206         int i, j;
2207         char *p;
2208
2209         spin_lock(&adapter->stats64_lock);
2210         igb_update_stats(adapter, net_stats);
2211
2212         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2213                 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2214                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2215                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2216         }
2217         for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2218                 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2219                 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2220                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2221         }
2222         for (j = 0; j < adapter->num_tx_queues; j++) {
2223                 u64     restart2;
2224
2225                 ring = adapter->tx_ring[j];
2226                 do {
2227                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2228                         data[i]   = ring->tx_stats.packets;
2229                         data[i+1] = ring->tx_stats.bytes;
2230                         data[i+2] = ring->tx_stats.restart_queue;
2231                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2232                 do {
2233                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2234                         restart2  = ring->tx_stats.restart_queue2;
2235                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2236                 data[i+2] += restart2;
2237
2238                 i += IGB_TX_QUEUE_STATS_LEN;
2239         }
2240         for (j = 0; j < adapter->num_rx_queues; j++) {
2241                 ring = adapter->rx_ring[j];
2242                 do {
2243                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2244                         data[i]   = ring->rx_stats.packets;
2245                         data[i+1] = ring->rx_stats.bytes;
2246                         data[i+2] = ring->rx_stats.drops;
2247                         data[i+3] = ring->rx_stats.csum_err;
2248                         data[i+4] = ring->rx_stats.alloc_failed;
2249                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2250                 i += IGB_RX_QUEUE_STATS_LEN;
2251         }
2252         spin_unlock(&adapter->stats64_lock);
2253 }
2254
2255 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2256 {
2257         struct igb_adapter *adapter = netdev_priv(netdev);
2258         u8 *p = data;
2259         int i;
2260
2261         switch (stringset) {
2262         case ETH_SS_TEST:
2263                 memcpy(data, *igb_gstrings_test,
2264                         IGB_TEST_LEN*ETH_GSTRING_LEN);
2265                 break;
2266         case ETH_SS_STATS:
2267                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2268                         memcpy(p, igb_gstrings_stats[i].stat_string,
2269                                ETH_GSTRING_LEN);
2270                         p += ETH_GSTRING_LEN;
2271                 }
2272                 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2273                         memcpy(p, igb_gstrings_net_stats[i].stat_string,
2274                                ETH_GSTRING_LEN);
2275                         p += ETH_GSTRING_LEN;
2276                 }
2277                 for (i = 0; i < adapter->num_tx_queues; i++) {
2278                         sprintf(p, "tx_queue_%u_packets", i);
2279                         p += ETH_GSTRING_LEN;
2280                         sprintf(p, "tx_queue_%u_bytes", i);
2281                         p += ETH_GSTRING_LEN;
2282                         sprintf(p, "tx_queue_%u_restart", i);
2283                         p += ETH_GSTRING_LEN;
2284                 }
2285                 for (i = 0; i < adapter->num_rx_queues; i++) {
2286                         sprintf(p, "rx_queue_%u_packets", i);
2287                         p += ETH_GSTRING_LEN;
2288                         sprintf(p, "rx_queue_%u_bytes", i);
2289                         p += ETH_GSTRING_LEN;
2290                         sprintf(p, "rx_queue_%u_drops", i);
2291                         p += ETH_GSTRING_LEN;
2292                         sprintf(p, "rx_queue_%u_csum_err", i);
2293                         p += ETH_GSTRING_LEN;
2294                         sprintf(p, "rx_queue_%u_alloc_failed", i);
2295                         p += ETH_GSTRING_LEN;
2296                 }
2297 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2298                 break;
2299         }
2300 }
2301
2302 static int igb_ethtool_begin(struct net_device *netdev)
2303 {
2304         struct igb_adapter *adapter = netdev_priv(netdev);
2305         pm_runtime_get_sync(&adapter->pdev->dev);
2306         return 0;
2307 }
2308
2309 static void igb_ethtool_complete(struct net_device *netdev)
2310 {
2311         struct igb_adapter *adapter = netdev_priv(netdev);
2312         pm_runtime_put(&adapter->pdev->dev);
2313 }
2314
2315 #ifdef CONFIG_IGB_PTP
2316 static int igb_ethtool_get_ts_info(struct net_device *dev,
2317                                    struct ethtool_ts_info *info)
2318 {
2319         struct igb_adapter *adapter = netdev_priv(dev);
2320
2321         info->so_timestamping =
2322                 SOF_TIMESTAMPING_TX_HARDWARE |
2323                 SOF_TIMESTAMPING_RX_HARDWARE |
2324                 SOF_TIMESTAMPING_RAW_HARDWARE;
2325
2326         if (adapter->ptp_clock)
2327                 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2328         else
2329                 info->phc_index = -1;
2330
2331         info->tx_types =
2332                 (1 << HWTSTAMP_TX_OFF) |
2333                 (1 << HWTSTAMP_TX_ON);
2334
2335         info->rx_filters =
2336                 (1 << HWTSTAMP_FILTER_NONE) |
2337                 (1 << HWTSTAMP_FILTER_ALL) |
2338                 (1 << HWTSTAMP_FILTER_SOME) |
2339                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2340                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2341                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2342
2343         return 0;
2344 }
2345
2346 #endif
2347 static const struct ethtool_ops igb_ethtool_ops = {
2348         .get_settings           = igb_get_settings,
2349         .set_settings           = igb_set_settings,
2350         .get_drvinfo            = igb_get_drvinfo,
2351         .get_regs_len           = igb_get_regs_len,
2352         .get_regs               = igb_get_regs,
2353         .get_wol                = igb_get_wol,
2354         .set_wol                = igb_set_wol,
2355         .get_msglevel           = igb_get_msglevel,
2356         .set_msglevel           = igb_set_msglevel,
2357         .nway_reset             = igb_nway_reset,
2358         .get_link               = igb_get_link,
2359         .get_eeprom_len         = igb_get_eeprom_len,
2360         .get_eeprom             = igb_get_eeprom,
2361         .set_eeprom             = igb_set_eeprom,
2362         .get_ringparam          = igb_get_ringparam,
2363         .set_ringparam          = igb_set_ringparam,
2364         .get_pauseparam         = igb_get_pauseparam,
2365         .set_pauseparam         = igb_set_pauseparam,
2366         .self_test              = igb_diag_test,
2367         .get_strings            = igb_get_strings,
2368         .set_phys_id            = igb_set_phys_id,
2369         .get_sset_count         = igb_get_sset_count,
2370         .get_ethtool_stats      = igb_get_ethtool_stats,
2371         .get_coalesce           = igb_get_coalesce,
2372         .set_coalesce           = igb_set_coalesce,
2373         .begin                  = igb_ethtool_begin,
2374         .complete               = igb_ethtool_complete,
2375 #ifdef CONFIG_IGB_PTP
2376         .get_ts_info            = igb_ethtool_get_ts_info,
2377 #endif
2378 };
2379
2380 void igb_set_ethtool_ops(struct net_device *netdev)
2381 {
2382         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2383 }