1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/init.h>
33 #include <linux/bitops.h>
34 #include <linux/vmalloc.h>
35 #include <linux/pagemap.h>
36 #include <linux/netdevice.h>
37 #include <linux/ipv6.h>
38 #include <linux/slab.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/net_tstamp.h>
42 #include <linux/mii.h>
43 #include <linux/ethtool.h>
45 #include <linux/if_vlan.h>
46 #include <linux/pci.h>
47 #include <linux/pci-aspm.h>
48 #include <linux/delay.h>
49 #include <linux/interrupt.h>
51 #include <linux/tcp.h>
52 #include <linux/sctp.h>
53 #include <linux/if_ether.h>
54 #include <linux/aer.h>
55 #include <linux/prefetch.h>
56 #include <linux/pm_runtime.h>
58 #include <linux/dca.h>
60 #include <linux/i2c.h>
66 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
67 __stringify(BUILD) "-k"
68 char igb_driver_name[] = "igb";
69 char igb_driver_version[] = DRV_VERSION;
70 static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
72 static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
75 static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
79 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
110 /* required last entry */
114 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116 void igb_reset(struct igb_adapter *);
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
159 static int igb_vlan_rx_add_vid(struct net_device *, u16);
160 static int igb_vlan_rx_kill_vid(struct net_device *, u16);
161 static void igb_restore_vlan(struct igb_adapter *);
162 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
163 static void igb_ping_all_vfs(struct igb_adapter *);
164 static void igb_msg_task(struct igb_adapter *);
165 static void igb_vmm_control(struct igb_adapter *);
166 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
167 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
168 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
169 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
170 int vf, u16 vlan, u8 qos);
171 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
172 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
173 struct ifla_vf_info *ivi);
174 static void igb_check_vf_rate_limit(struct igb_adapter *);
176 #ifdef CONFIG_PCI_IOV
177 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
178 static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
182 #ifdef CONFIG_PM_SLEEP
183 static int igb_suspend(struct device *);
185 static int igb_resume(struct device *);
186 #ifdef CONFIG_PM_RUNTIME
187 static int igb_runtime_suspend(struct device *dev);
188 static int igb_runtime_resume(struct device *dev);
189 static int igb_runtime_idle(struct device *dev);
191 static const struct dev_pm_ops igb_pm_ops = {
192 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
193 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 static void igb_shutdown(struct pci_dev *);
198 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
199 #ifdef CONFIG_IGB_DCA
200 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
201 static struct notifier_block dca_notifier = {
202 .notifier_call = igb_notify_dca,
207 #ifdef CONFIG_NET_POLL_CONTROLLER
208 /* for netdump / net console */
209 static void igb_netpoll(struct net_device *);
211 #ifdef CONFIG_PCI_IOV
212 static unsigned int max_vfs = 0;
213 module_param(max_vfs, uint, 0);
214 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
215 "per physical function");
216 #endif /* CONFIG_PCI_IOV */
218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221 static void igb_io_resume(struct pci_dev *);
223 static const struct pci_error_handlers igb_err_handler = {
224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
231 static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
235 .remove = igb_remove,
237 .driver.pm = &igb_pm_ops,
239 .shutdown = igb_shutdown,
240 .sriov_configure = igb_pci_sriov_configure,
241 .err_handler = &igb_err_handler
244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246 MODULE_LICENSE("GPL");
247 MODULE_VERSION(DRV_VERSION);
249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250 static int debug = -1;
251 module_param(debug, int, 0);
252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
254 struct igb_reg_info {
259 static const struct igb_reg_info igb_reg_info_tbl[] = {
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
266 /* Interrupt Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
291 /* List Terminator */
296 * igb_regdump - register printout routine
298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
304 switch (reginfo->ofs) {
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 * igb_dump - Print registers, tx-rings and rx-rings
366 static void igb_dump(struct igb_adapter *adapter)
368 struct net_device *netdev = adapter->netdev;
369 struct e1000_hw *hw = &adapter->hw;
370 struct igb_reg_info *reginfo;
371 struct igb_ring *tx_ring;
372 union e1000_adv_tx_desc *tx_desc;
373 struct my_u0 { u64 a; u64 b; } *u0;
374 struct igb_ring *rx_ring;
375 union e1000_adv_rx_desc *rx_desc;
379 if (!netif_msg_hw(adapter))
382 /* Print netdevice Info */
384 dev_info(&adapter->pdev->dev, "Net device Info\n");
385 pr_info("Device Name state trans_start "
387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
388 netdev->state, netdev->trans_start, netdev->last_rx);
391 /* Print Registers */
392 dev_info(&adapter->pdev->dev, "Register Dump\n");
393 pr_info(" Register Name Value\n");
394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
395 reginfo->name; reginfo++) {
396 igb_regdump(hw, reginfo);
399 /* Print TX Ring Summary */
400 if (!netdev || !netif_running(netdev))
403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
405 for (n = 0; n < adapter->num_tx_queues; n++) {
406 struct igb_tx_buffer *buffer_info;
407 tx_ring = adapter->tx_ring[n];
408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
410 n, tx_ring->next_to_use, tx_ring->next_to_clean,
411 (u64)dma_unmap_addr(buffer_info, dma),
412 dma_unmap_len(buffer_info, len),
413 buffer_info->next_to_watch,
414 (u64)buffer_info->time_stamp);
418 if (!netif_msg_tx_done(adapter))
419 goto rx_ring_summary;
421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
423 /* Transmit Descriptor Formats
425 * Advanced Transmit Descriptor
426 * +--------------------------------------------------------------+
427 * 0 | Buffer Address [63:0] |
428 * +--------------------------------------------------------------+
429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
430 * +--------------------------------------------------------------+
431 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 for (n = 0; n < adapter->num_tx_queues; n++) {
435 tx_ring = adapter->tx_ring[n];
436 pr_info("------------------------------------\n");
437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
438 pr_info("------------------------------------\n");
439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
440 "[bi->dma ] leng ntw timestamp "
443 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
444 const char *next_desc;
445 struct igb_tx_buffer *buffer_info;
446 tx_desc = IGB_TX_DESC(tx_ring, i);
447 buffer_info = &tx_ring->tx_buffer_info[i];
448 u0 = (struct my_u0 *)tx_desc;
449 if (i == tx_ring->next_to_use &&
450 i == tx_ring->next_to_clean)
451 next_desc = " NTC/U";
452 else if (i == tx_ring->next_to_use)
454 else if (i == tx_ring->next_to_clean)
459 pr_info("T [0x%03X] %016llX %016llX %016llX"
460 " %04X %p %016llX %p%s\n", i,
463 (u64)dma_unmap_addr(buffer_info, dma),
464 dma_unmap_len(buffer_info, len),
465 buffer_info->next_to_watch,
466 (u64)buffer_info->time_stamp,
467 buffer_info->skb, next_desc);
469 if (netif_msg_pktdata(adapter) && buffer_info->skb)
470 print_hex_dump(KERN_INFO, "",
472 16, 1, buffer_info->skb->data,
473 dma_unmap_len(buffer_info, len),
478 /* Print RX Rings Summary */
480 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
481 pr_info("Queue [NTU] [NTC]\n");
482 for (n = 0; n < adapter->num_rx_queues; n++) {
483 rx_ring = adapter->rx_ring[n];
484 pr_info(" %5d %5X %5X\n",
485 n, rx_ring->next_to_use, rx_ring->next_to_clean);
489 if (!netif_msg_rx_status(adapter))
492 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
494 /* Advanced Receive Descriptor (Read) Format
496 * +-----------------------------------------------------+
497 * 0 | Packet Buffer Address [63:1] |A0/NSE|
498 * +----------------------------------------------+------+
499 * 8 | Header Buffer Address [63:1] | DD |
500 * +-----------------------------------------------------+
503 * Advanced Receive Descriptor (Write-Back) Format
505 * 63 48 47 32 31 30 21 20 17 16 4 3 0
506 * +------------------------------------------------------+
507 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
508 * | Checksum Ident | | | | Type | Type |
509 * +------------------------------------------------------+
510 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
511 * +------------------------------------------------------+
512 * 63 48 47 32 31 20 19 0
515 for (n = 0; n < adapter->num_rx_queues; n++) {
516 rx_ring = adapter->rx_ring[n];
517 pr_info("------------------------------------\n");
518 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
519 pr_info("------------------------------------\n");
520 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
521 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
522 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
523 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
525 for (i = 0; i < rx_ring->count; i++) {
526 const char *next_desc;
527 struct igb_rx_buffer *buffer_info;
528 buffer_info = &rx_ring->rx_buffer_info[i];
529 rx_desc = IGB_RX_DESC(rx_ring, i);
530 u0 = (struct my_u0 *)rx_desc;
531 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
533 if (i == rx_ring->next_to_use)
535 else if (i == rx_ring->next_to_clean)
540 if (staterr & E1000_RXD_STAT_DD) {
541 /* Descriptor Done */
542 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
548 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
552 (u64)buffer_info->dma,
555 if (netif_msg_pktdata(adapter) &&
556 buffer_info->dma && buffer_info->page) {
557 print_hex_dump(KERN_INFO, "",
560 page_address(buffer_info->page) +
561 buffer_info->page_offset,
572 /* igb_get_i2c_data - Reads the I2C SDA data bit
573 * @hw: pointer to hardware structure
574 * @i2cctl: Current value of I2CCTL register
576 * Returns the I2C data bit value
578 static int igb_get_i2c_data(void *data)
580 struct igb_adapter *adapter = (struct igb_adapter *)data;
581 struct e1000_hw *hw = &adapter->hw;
582 s32 i2cctl = rd32(E1000_I2CPARAMS);
584 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
587 /* igb_set_i2c_data - Sets the I2C data bit
588 * @data: pointer to hardware structure
589 * @state: I2C data value (0 or 1) to set
591 * Sets the I2C data bit
593 static void igb_set_i2c_data(void *data, int state)
595 struct igb_adapter *adapter = (struct igb_adapter *)data;
596 struct e1000_hw *hw = &adapter->hw;
597 s32 i2cctl = rd32(E1000_I2CPARAMS);
600 i2cctl |= E1000_I2C_DATA_OUT;
602 i2cctl &= ~E1000_I2C_DATA_OUT;
604 i2cctl &= ~E1000_I2C_DATA_OE_N;
605 i2cctl |= E1000_I2C_CLK_OE_N;
606 wr32(E1000_I2CPARAMS, i2cctl);
611 /* igb_set_i2c_clk - Sets the I2C SCL clock
612 * @data: pointer to hardware structure
613 * @state: state to set clock
615 * Sets the I2C clock line to state
617 static void igb_set_i2c_clk(void *data, int state)
619 struct igb_adapter *adapter = (struct igb_adapter *)data;
620 struct e1000_hw *hw = &adapter->hw;
621 s32 i2cctl = rd32(E1000_I2CPARAMS);
624 i2cctl |= E1000_I2C_CLK_OUT;
625 i2cctl &= ~E1000_I2C_CLK_OE_N;
627 i2cctl &= ~E1000_I2C_CLK_OUT;
628 i2cctl &= ~E1000_I2C_CLK_OE_N;
630 wr32(E1000_I2CPARAMS, i2cctl);
634 /* igb_get_i2c_clk - Gets the I2C SCL clock state
635 * @data: pointer to hardware structure
637 * Gets the I2C clock state
639 static int igb_get_i2c_clk(void *data)
641 struct igb_adapter *adapter = (struct igb_adapter *)data;
642 struct e1000_hw *hw = &adapter->hw;
643 s32 i2cctl = rd32(E1000_I2CPARAMS);
645 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
648 static const struct i2c_algo_bit_data igb_i2c_algo = {
649 .setsda = igb_set_i2c_data,
650 .setscl = igb_set_i2c_clk,
651 .getsda = igb_get_i2c_data,
652 .getscl = igb_get_i2c_clk,
658 * igb_get_hw_dev - return device
659 * used by hardware layer to print debugging information
661 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
663 struct igb_adapter *adapter = hw->back;
664 return adapter->netdev;
668 * igb_init_module - Driver Registration Routine
670 * igb_init_module is the first routine called when the driver is
671 * loaded. All it does is register with the PCI subsystem.
673 static int __init igb_init_module(void)
676 pr_info("%s - version %s\n",
677 igb_driver_string, igb_driver_version);
679 pr_info("%s\n", igb_copyright);
681 #ifdef CONFIG_IGB_DCA
682 dca_register_notify(&dca_notifier);
684 ret = pci_register_driver(&igb_driver);
688 module_init(igb_init_module);
691 * igb_exit_module - Driver Exit Cleanup Routine
693 * igb_exit_module is called just before the driver is removed
696 static void __exit igb_exit_module(void)
698 #ifdef CONFIG_IGB_DCA
699 dca_unregister_notify(&dca_notifier);
701 pci_unregister_driver(&igb_driver);
704 module_exit(igb_exit_module);
706 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
708 * igb_cache_ring_register - Descriptor ring to register mapping
709 * @adapter: board private structure to initialize
711 * Once we know the feature-set enabled for the device, we'll cache
712 * the register offset the descriptor ring is assigned to.
714 static void igb_cache_ring_register(struct igb_adapter *adapter)
717 u32 rbase_offset = adapter->vfs_allocated_count;
719 switch (adapter->hw.mac.type) {
721 /* The queues are allocated for virtualization such that VF 0
722 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
723 * In order to avoid collision we start at the first free queue
724 * and continue consuming queues in the same sequence
726 if (adapter->vfs_allocated_count) {
727 for (; i < adapter->rss_queues; i++)
728 adapter->rx_ring[i]->reg_idx = rbase_offset +
737 for (; i < adapter->num_rx_queues; i++)
738 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
739 for (; j < adapter->num_tx_queues; j++)
740 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
746 * igb_write_ivar - configure ivar for given MSI-X vector
747 * @hw: pointer to the HW structure
748 * @msix_vector: vector number we are allocating to a given ring
749 * @index: row index of IVAR register to write within IVAR table
750 * @offset: column offset of in IVAR, should be multiple of 8
752 * This function is intended to handle the writing of the IVAR register
753 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
754 * each containing an cause allocation for an Rx and Tx ring, and a
755 * variable number of rows depending on the number of queues supported.
757 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
758 int index, int offset)
760 u32 ivar = array_rd32(E1000_IVAR0, index);
762 /* clear any bits that are currently set */
763 ivar &= ~((u32)0xFF << offset);
765 /* write vector and valid bit */
766 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
768 array_wr32(E1000_IVAR0, index, ivar);
771 #define IGB_N0_QUEUE -1
772 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
774 struct igb_adapter *adapter = q_vector->adapter;
775 struct e1000_hw *hw = &adapter->hw;
776 int rx_queue = IGB_N0_QUEUE;
777 int tx_queue = IGB_N0_QUEUE;
780 if (q_vector->rx.ring)
781 rx_queue = q_vector->rx.ring->reg_idx;
782 if (q_vector->tx.ring)
783 tx_queue = q_vector->tx.ring->reg_idx;
785 switch (hw->mac.type) {
787 /* The 82575 assigns vectors using a bitmask, which matches the
788 bitmask for the EICR/EIMS/EIMC registers. To assign one
789 or more queues to a vector, we write the appropriate bits
790 into the MSIXBM register for that vector. */
791 if (rx_queue > IGB_N0_QUEUE)
792 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
793 if (tx_queue > IGB_N0_QUEUE)
794 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
795 if (!adapter->msix_entries && msix_vector == 0)
796 msixbm |= E1000_EIMS_OTHER;
797 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
798 q_vector->eims_value = msixbm;
802 * 82576 uses a table that essentially consists of 2 columns
803 * with 8 rows. The ordering is column-major so we use the
804 * lower 3 bits as the row index, and the 4th bit as the
807 if (rx_queue > IGB_N0_QUEUE)
808 igb_write_ivar(hw, msix_vector,
810 (rx_queue & 0x8) << 1);
811 if (tx_queue > IGB_N0_QUEUE)
812 igb_write_ivar(hw, msix_vector,
814 ((tx_queue & 0x8) << 1) + 8);
815 q_vector->eims_value = 1 << msix_vector;
822 * On 82580 and newer adapters the scheme is similar to 82576
823 * however instead of ordering column-major we have things
824 * ordered row-major. So we traverse the table by using
825 * bit 0 as the column offset, and the remaining bits as the
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
831 (rx_queue & 0x1) << 4);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
835 ((tx_queue & 0x1) << 4) + 8);
836 q_vector->eims_value = 1 << msix_vector;
843 /* add q_vector eims value to global eims_enable_mask */
844 adapter->eims_enable_mask |= q_vector->eims_value;
846 /* configure q_vector to set itr on first interrupt */
847 q_vector->set_itr = 1;
851 * igb_configure_msix - Configure MSI-X hardware
853 * igb_configure_msix sets up the hardware to properly
854 * generate MSI-X interrupts.
856 static void igb_configure_msix(struct igb_adapter *adapter)
860 struct e1000_hw *hw = &adapter->hw;
862 adapter->eims_enable_mask = 0;
864 /* set vector for other causes, i.e. link changes */
865 switch (hw->mac.type) {
867 tmp = rd32(E1000_CTRL_EXT);
868 /* enable MSI-X PBA support*/
869 tmp |= E1000_CTRL_EXT_PBA_CLR;
871 /* Auto-Mask interrupts upon ICR read. */
872 tmp |= E1000_CTRL_EXT_EIAME;
873 tmp |= E1000_CTRL_EXT_IRCA;
875 wr32(E1000_CTRL_EXT, tmp);
877 /* enable msix_other interrupt */
878 array_wr32(E1000_MSIXBM(0), vector++,
880 adapter->eims_other = E1000_EIMS_OTHER;
889 /* Turn on MSI-X capability first, or our settings
890 * won't stick. And it will take days to debug. */
891 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
892 E1000_GPIE_PBA | E1000_GPIE_EIAME |
895 /* enable msix_other interrupt */
896 adapter->eims_other = 1 << vector;
897 tmp = (vector++ | E1000_IVAR_VALID) << 8;
899 wr32(E1000_IVAR_MISC, tmp);
902 /* do nothing, since nothing else supports MSI-X */
904 } /* switch (hw->mac.type) */
906 adapter->eims_enable_mask |= adapter->eims_other;
908 for (i = 0; i < adapter->num_q_vectors; i++)
909 igb_assign_vector(adapter->q_vector[i], vector++);
915 * igb_request_msix - Initialize MSI-X interrupts
917 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
920 static int igb_request_msix(struct igb_adapter *adapter)
922 struct net_device *netdev = adapter->netdev;
923 struct e1000_hw *hw = &adapter->hw;
924 int i, err = 0, vector = 0, free_vector = 0;
926 err = request_irq(adapter->msix_entries[vector].vector,
927 igb_msix_other, 0, netdev->name, adapter);
931 for (i = 0; i < adapter->num_q_vectors; i++) {
932 struct igb_q_vector *q_vector = adapter->q_vector[i];
936 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
938 if (q_vector->rx.ring && q_vector->tx.ring)
939 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
940 q_vector->rx.ring->queue_index);
941 else if (q_vector->tx.ring)
942 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
943 q_vector->tx.ring->queue_index);
944 else if (q_vector->rx.ring)
945 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
946 q_vector->rx.ring->queue_index);
948 sprintf(q_vector->name, "%s-unused", netdev->name);
950 err = request_irq(adapter->msix_entries[vector].vector,
951 igb_msix_ring, 0, q_vector->name,
957 igb_configure_msix(adapter);
961 /* free already assigned IRQs */
962 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
965 for (i = 0; i < vector; i++) {
966 free_irq(adapter->msix_entries[free_vector++].vector,
967 adapter->q_vector[i]);
973 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
975 if (adapter->msix_entries) {
976 pci_disable_msix(adapter->pdev);
977 kfree(adapter->msix_entries);
978 adapter->msix_entries = NULL;
979 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
980 pci_disable_msi(adapter->pdev);
985 * igb_free_q_vector - Free memory allocated for specific interrupt vector
986 * @adapter: board private structure to initialize
987 * @v_idx: Index of vector to be freed
989 * This function frees the memory allocated to the q_vector. In addition if
990 * NAPI is enabled it will delete any references to the NAPI struct prior
991 * to freeing the q_vector.
993 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
995 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
997 if (q_vector->tx.ring)
998 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1000 if (q_vector->rx.ring)
1001 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1003 adapter->q_vector[v_idx] = NULL;
1004 netif_napi_del(&q_vector->napi);
1007 * ixgbe_get_stats64() might access the rings on this vector,
1008 * we must wait a grace period before freeing it.
1010 kfree_rcu(q_vector, rcu);
1014 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1015 * @adapter: board private structure to initialize
1017 * This function frees the memory allocated to the q_vectors. In addition if
1018 * NAPI is enabled it will delete any references to the NAPI struct prior
1019 * to freeing the q_vector.
1021 static void igb_free_q_vectors(struct igb_adapter *adapter)
1023 int v_idx = adapter->num_q_vectors;
1025 adapter->num_tx_queues = 0;
1026 adapter->num_rx_queues = 0;
1027 adapter->num_q_vectors = 0;
1030 igb_free_q_vector(adapter, v_idx);
1034 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1036 * This function resets the device so that it has 0 rx queues, tx queues, and
1037 * MSI-X interrupts allocated.
1039 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1041 igb_free_q_vectors(adapter);
1042 igb_reset_interrupt_capability(adapter);
1046 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1048 * Attempt to configure interrupts using the best available
1049 * capabilities of the hardware and kernel.
1051 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1059 /* Number of supported queues. */
1060 adapter->num_rx_queues = adapter->rss_queues;
1061 if (adapter->vfs_allocated_count)
1062 adapter->num_tx_queues = 1;
1064 adapter->num_tx_queues = adapter->rss_queues;
1066 /* start with one vector for every rx queue */
1067 numvecs = adapter->num_rx_queues;
1069 /* if tx handler is separate add 1 for every tx queue */
1070 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1071 numvecs += adapter->num_tx_queues;
1073 /* store the number of vectors reserved for queues */
1074 adapter->num_q_vectors = numvecs;
1076 /* add 1 vector for link status interrupts */
1078 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1081 if (!adapter->msix_entries)
1084 for (i = 0; i < numvecs; i++)
1085 adapter->msix_entries[i].entry = i;
1087 err = pci_enable_msix(adapter->pdev,
1088 adapter->msix_entries,
1093 igb_reset_interrupt_capability(adapter);
1095 /* If we can't do MSI-X, try MSI */
1097 #ifdef CONFIG_PCI_IOV
1098 /* disable SR-IOV for non MSI-X configurations */
1099 if (adapter->vf_data) {
1100 struct e1000_hw *hw = &adapter->hw;
1101 /* disable iov and allow time for transactions to clear */
1102 pci_disable_sriov(adapter->pdev);
1105 kfree(adapter->vf_data);
1106 adapter->vf_data = NULL;
1107 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1110 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1113 adapter->vfs_allocated_count = 0;
1114 adapter->rss_queues = 1;
1115 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1116 adapter->num_rx_queues = 1;
1117 adapter->num_tx_queues = 1;
1118 adapter->num_q_vectors = 1;
1119 if (!pci_enable_msi(adapter->pdev))
1120 adapter->flags |= IGB_FLAG_HAS_MSI;
1123 static void igb_add_ring(struct igb_ring *ring,
1124 struct igb_ring_container *head)
1131 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1132 * @adapter: board private structure to initialize
1133 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1134 * @v_idx: index of vector in adapter struct
1135 * @txr_count: total number of Tx rings to allocate
1136 * @txr_idx: index of first Tx ring to allocate
1137 * @rxr_count: total number of Rx rings to allocate
1138 * @rxr_idx: index of first Rx ring to allocate
1140 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1142 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1143 int v_count, int v_idx,
1144 int txr_count, int txr_idx,
1145 int rxr_count, int rxr_idx)
1147 struct igb_q_vector *q_vector;
1148 struct igb_ring *ring;
1149 int ring_count, size;
1151 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1152 if (txr_count > 1 || rxr_count > 1)
1155 ring_count = txr_count + rxr_count;
1156 size = sizeof(struct igb_q_vector) +
1157 (sizeof(struct igb_ring) * ring_count);
1159 /* allocate q_vector and rings */
1160 q_vector = kzalloc(size, GFP_KERNEL);
1164 /* initialize NAPI */
1165 netif_napi_add(adapter->netdev, &q_vector->napi,
1168 /* tie q_vector and adapter together */
1169 adapter->q_vector[v_idx] = q_vector;
1170 q_vector->adapter = adapter;
1172 /* initialize work limits */
1173 q_vector->tx.work_limit = adapter->tx_work_limit;
1175 /* initialize ITR configuration */
1176 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1177 q_vector->itr_val = IGB_START_ITR;
1179 /* initialize pointer to rings */
1180 ring = q_vector->ring;
1183 /* assign generic ring traits */
1184 ring->dev = &adapter->pdev->dev;
1185 ring->netdev = adapter->netdev;
1187 /* configure backlink on ring */
1188 ring->q_vector = q_vector;
1190 /* update q_vector Tx values */
1191 igb_add_ring(ring, &q_vector->tx);
1193 /* For 82575, context index must be unique per ring. */
1194 if (adapter->hw.mac.type == e1000_82575)
1195 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1197 /* apply Tx specific ring traits */
1198 ring->count = adapter->tx_ring_count;
1199 ring->queue_index = txr_idx;
1201 /* assign ring to adapter */
1202 adapter->tx_ring[txr_idx] = ring;
1204 /* push pointer to next ring */
1209 /* assign generic ring traits */
1210 ring->dev = &adapter->pdev->dev;
1211 ring->netdev = adapter->netdev;
1213 /* configure backlink on ring */
1214 ring->q_vector = q_vector;
1216 /* update q_vector Rx values */
1217 igb_add_ring(ring, &q_vector->rx);
1219 /* set flag indicating ring supports SCTP checksum offload */
1220 if (adapter->hw.mac.type >= e1000_82576)
1221 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1224 * On i350, i210, and i211, loopback VLAN packets
1225 * have the tag byte-swapped.
1227 if (adapter->hw.mac.type >= e1000_i350)
1228 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1230 /* apply Rx specific ring traits */
1231 ring->count = adapter->rx_ring_count;
1232 ring->queue_index = rxr_idx;
1234 /* assign ring to adapter */
1235 adapter->rx_ring[rxr_idx] = ring;
1243 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1244 * @adapter: board private structure to initialize
1246 * We allocate one q_vector per queue interrupt. If allocation fails we
1249 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1251 int q_vectors = adapter->num_q_vectors;
1252 int rxr_remaining = adapter->num_rx_queues;
1253 int txr_remaining = adapter->num_tx_queues;
1254 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1257 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1258 for (; rxr_remaining; v_idx++) {
1259 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1265 /* update counts and index */
1271 for (; v_idx < q_vectors; v_idx++) {
1272 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1273 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1274 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1275 tqpv, txr_idx, rqpv, rxr_idx);
1280 /* update counts and index */
1281 rxr_remaining -= rqpv;
1282 txr_remaining -= tqpv;
1290 adapter->num_tx_queues = 0;
1291 adapter->num_rx_queues = 0;
1292 adapter->num_q_vectors = 0;
1295 igb_free_q_vector(adapter, v_idx);
1301 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1303 * This function initializes the interrupts and allocates all of the queues.
1305 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1307 struct pci_dev *pdev = adapter->pdev;
1310 igb_set_interrupt_capability(adapter, msix);
1312 err = igb_alloc_q_vectors(adapter);
1314 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1315 goto err_alloc_q_vectors;
1318 igb_cache_ring_register(adapter);
1322 err_alloc_q_vectors:
1323 igb_reset_interrupt_capability(adapter);
1328 * igb_request_irq - initialize interrupts
1330 * Attempts to configure interrupts using the best available
1331 * capabilities of the hardware and kernel.
1333 static int igb_request_irq(struct igb_adapter *adapter)
1335 struct net_device *netdev = adapter->netdev;
1336 struct pci_dev *pdev = adapter->pdev;
1339 if (adapter->msix_entries) {
1340 err = igb_request_msix(adapter);
1343 /* fall back to MSI */
1344 igb_free_all_tx_resources(adapter);
1345 igb_free_all_rx_resources(adapter);
1347 igb_clear_interrupt_scheme(adapter);
1348 err = igb_init_interrupt_scheme(adapter, false);
1352 igb_setup_all_tx_resources(adapter);
1353 igb_setup_all_rx_resources(adapter);
1354 igb_configure(adapter);
1357 igb_assign_vector(adapter->q_vector[0], 0);
1359 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1360 err = request_irq(pdev->irq, igb_intr_msi, 0,
1361 netdev->name, adapter);
1365 /* fall back to legacy interrupts */
1366 igb_reset_interrupt_capability(adapter);
1367 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1370 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1371 netdev->name, adapter);
1374 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1381 static void igb_free_irq(struct igb_adapter *adapter)
1383 if (adapter->msix_entries) {
1386 free_irq(adapter->msix_entries[vector++].vector, adapter);
1388 for (i = 0; i < adapter->num_q_vectors; i++)
1389 free_irq(adapter->msix_entries[vector++].vector,
1390 adapter->q_vector[i]);
1392 free_irq(adapter->pdev->irq, adapter);
1397 * igb_irq_disable - Mask off interrupt generation on the NIC
1398 * @adapter: board private structure
1400 static void igb_irq_disable(struct igb_adapter *adapter)
1402 struct e1000_hw *hw = &adapter->hw;
1405 * we need to be careful when disabling interrupts. The VFs are also
1406 * mapped into these registers and so clearing the bits can cause
1407 * issues on the VF drivers so we only need to clear what we set
1409 if (adapter->msix_entries) {
1410 u32 regval = rd32(E1000_EIAM);
1411 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1412 wr32(E1000_EIMC, adapter->eims_enable_mask);
1413 regval = rd32(E1000_EIAC);
1414 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1418 wr32(E1000_IMC, ~0);
1420 if (adapter->msix_entries) {
1422 for (i = 0; i < adapter->num_q_vectors; i++)
1423 synchronize_irq(adapter->msix_entries[i].vector);
1425 synchronize_irq(adapter->pdev->irq);
1430 * igb_irq_enable - Enable default interrupt generation settings
1431 * @adapter: board private structure
1433 static void igb_irq_enable(struct igb_adapter *adapter)
1435 struct e1000_hw *hw = &adapter->hw;
1437 if (adapter->msix_entries) {
1438 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1439 u32 regval = rd32(E1000_EIAC);
1440 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1441 regval = rd32(E1000_EIAM);
1442 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1443 wr32(E1000_EIMS, adapter->eims_enable_mask);
1444 if (adapter->vfs_allocated_count) {
1445 wr32(E1000_MBVFIMR, 0xFF);
1446 ims |= E1000_IMS_VMMB;
1448 wr32(E1000_IMS, ims);
1450 wr32(E1000_IMS, IMS_ENABLE_MASK |
1452 wr32(E1000_IAM, IMS_ENABLE_MASK |
1457 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1459 struct e1000_hw *hw = &adapter->hw;
1460 u16 vid = adapter->hw.mng_cookie.vlan_id;
1461 u16 old_vid = adapter->mng_vlan_id;
1463 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1464 /* add VID to filter table */
1465 igb_vfta_set(hw, vid, true);
1466 adapter->mng_vlan_id = vid;
1468 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1471 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1473 !test_bit(old_vid, adapter->active_vlans)) {
1474 /* remove VID from filter table */
1475 igb_vfta_set(hw, old_vid, false);
1480 * igb_release_hw_control - release control of the h/w to f/w
1481 * @adapter: address of board private structure
1483 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1484 * For ASF and Pass Through versions of f/w this means that the
1485 * driver is no longer loaded.
1488 static void igb_release_hw_control(struct igb_adapter *adapter)
1490 struct e1000_hw *hw = &adapter->hw;
1493 /* Let firmware take over control of h/w */
1494 ctrl_ext = rd32(E1000_CTRL_EXT);
1495 wr32(E1000_CTRL_EXT,
1496 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1500 * igb_get_hw_control - get control of the h/w from f/w
1501 * @adapter: address of board private structure
1503 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1504 * For ASF and Pass Through versions of f/w this means that
1505 * the driver is loaded.
1508 static void igb_get_hw_control(struct igb_adapter *adapter)
1510 struct e1000_hw *hw = &adapter->hw;
1513 /* Let firmware know the driver has taken over */
1514 ctrl_ext = rd32(E1000_CTRL_EXT);
1515 wr32(E1000_CTRL_EXT,
1516 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1520 * igb_configure - configure the hardware for RX and TX
1521 * @adapter: private board structure
1523 static void igb_configure(struct igb_adapter *adapter)
1525 struct net_device *netdev = adapter->netdev;
1528 igb_get_hw_control(adapter);
1529 igb_set_rx_mode(netdev);
1531 igb_restore_vlan(adapter);
1533 igb_setup_tctl(adapter);
1534 igb_setup_mrqc(adapter);
1535 igb_setup_rctl(adapter);
1537 igb_configure_tx(adapter);
1538 igb_configure_rx(adapter);
1540 igb_rx_fifo_flush_82575(&adapter->hw);
1542 /* call igb_desc_unused which always leaves
1543 * at least 1 descriptor unused to make sure
1544 * next_to_use != next_to_clean */
1545 for (i = 0; i < adapter->num_rx_queues; i++) {
1546 struct igb_ring *ring = adapter->rx_ring[i];
1547 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1552 * igb_power_up_link - Power up the phy/serdes link
1553 * @adapter: address of board private structure
1555 void igb_power_up_link(struct igb_adapter *adapter)
1557 igb_reset_phy(&adapter->hw);
1559 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1560 igb_power_up_phy_copper(&adapter->hw);
1562 igb_power_up_serdes_link_82575(&adapter->hw);
1566 * igb_power_down_link - Power down the phy/serdes link
1567 * @adapter: address of board private structure
1569 static void igb_power_down_link(struct igb_adapter *adapter)
1571 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1572 igb_power_down_phy_copper_82575(&adapter->hw);
1574 igb_shutdown_serdes_link_82575(&adapter->hw);
1578 * igb_up - Open the interface and prepare it to handle traffic
1579 * @adapter: board private structure
1581 int igb_up(struct igb_adapter *adapter)
1583 struct e1000_hw *hw = &adapter->hw;
1586 /* hardware has been reset, we need to reload some things */
1587 igb_configure(adapter);
1589 clear_bit(__IGB_DOWN, &adapter->state);
1591 for (i = 0; i < adapter->num_q_vectors; i++)
1592 napi_enable(&(adapter->q_vector[i]->napi));
1594 if (adapter->msix_entries)
1595 igb_configure_msix(adapter);
1597 igb_assign_vector(adapter->q_vector[0], 0);
1599 /* Clear any pending interrupts. */
1601 igb_irq_enable(adapter);
1603 /* notify VFs that reset has been completed */
1604 if (adapter->vfs_allocated_count) {
1605 u32 reg_data = rd32(E1000_CTRL_EXT);
1606 reg_data |= E1000_CTRL_EXT_PFRSTD;
1607 wr32(E1000_CTRL_EXT, reg_data);
1610 netif_tx_start_all_queues(adapter->netdev);
1612 /* start the watchdog. */
1613 hw->mac.get_link_status = 1;
1614 schedule_work(&adapter->watchdog_task);
1619 void igb_down(struct igb_adapter *adapter)
1621 struct net_device *netdev = adapter->netdev;
1622 struct e1000_hw *hw = &adapter->hw;
1626 /* signal that we're down so the interrupt handler does not
1627 * reschedule our watchdog timer */
1628 set_bit(__IGB_DOWN, &adapter->state);
1630 /* disable receives in the hardware */
1631 rctl = rd32(E1000_RCTL);
1632 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1633 /* flush and sleep below */
1635 netif_tx_stop_all_queues(netdev);
1637 /* disable transmits in the hardware */
1638 tctl = rd32(E1000_TCTL);
1639 tctl &= ~E1000_TCTL_EN;
1640 wr32(E1000_TCTL, tctl);
1641 /* flush both disables and wait for them to finish */
1645 for (i = 0; i < adapter->num_q_vectors; i++)
1646 napi_disable(&(adapter->q_vector[i]->napi));
1648 igb_irq_disable(adapter);
1650 del_timer_sync(&adapter->watchdog_timer);
1651 del_timer_sync(&adapter->phy_info_timer);
1653 netif_carrier_off(netdev);
1655 /* record the stats before reset*/
1656 spin_lock(&adapter->stats64_lock);
1657 igb_update_stats(adapter, &adapter->stats64);
1658 spin_unlock(&adapter->stats64_lock);
1660 adapter->link_speed = 0;
1661 adapter->link_duplex = 0;
1663 if (!pci_channel_offline(adapter->pdev))
1665 igb_clean_all_tx_rings(adapter);
1666 igb_clean_all_rx_rings(adapter);
1667 #ifdef CONFIG_IGB_DCA
1669 /* since we reset the hardware DCA settings were cleared */
1670 igb_setup_dca(adapter);
1674 void igb_reinit_locked(struct igb_adapter *adapter)
1676 WARN_ON(in_interrupt());
1677 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1681 clear_bit(__IGB_RESETTING, &adapter->state);
1684 void igb_reset(struct igb_adapter *adapter)
1686 struct pci_dev *pdev = adapter->pdev;
1687 struct e1000_hw *hw = &adapter->hw;
1688 struct e1000_mac_info *mac = &hw->mac;
1689 struct e1000_fc_info *fc = &hw->fc;
1690 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1692 /* Repartition Pba for greater than 9k mtu
1693 * To take effect CTRL.RST is required.
1695 switch (mac->type) {
1698 pba = rd32(E1000_RXPBS);
1699 pba = igb_rxpbs_adjust_82580(pba);
1702 pba = rd32(E1000_RXPBS);
1703 pba &= E1000_RXPBS_SIZE_MASK_82576;
1709 pba = E1000_PBA_34K;
1713 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1714 (mac->type < e1000_82576)) {
1715 /* adjust PBA for jumbo frames */
1716 wr32(E1000_PBA, pba);
1718 /* To maintain wire speed transmits, the Tx FIFO should be
1719 * large enough to accommodate two full transmit packets,
1720 * rounded up to the next 1KB and expressed in KB. Likewise,
1721 * the Rx FIFO should be large enough to accommodate at least
1722 * one full receive packet and is similarly rounded up and
1723 * expressed in KB. */
1724 pba = rd32(E1000_PBA);
1725 /* upper 16 bits has Tx packet buffer allocation size in KB */
1726 tx_space = pba >> 16;
1727 /* lower 16 bits has Rx packet buffer allocation size in KB */
1729 /* the tx fifo also stores 16 bytes of information about the tx
1730 * but don't include ethernet FCS because hardware appends it */
1731 min_tx_space = (adapter->max_frame_size +
1732 sizeof(union e1000_adv_tx_desc) -
1734 min_tx_space = ALIGN(min_tx_space, 1024);
1735 min_tx_space >>= 10;
1736 /* software strips receive CRC, so leave room for it */
1737 min_rx_space = adapter->max_frame_size;
1738 min_rx_space = ALIGN(min_rx_space, 1024);
1739 min_rx_space >>= 10;
1741 /* If current Tx allocation is less than the min Tx FIFO size,
1742 * and the min Tx FIFO size is less than the current Rx FIFO
1743 * allocation, take space away from current Rx allocation */
1744 if (tx_space < min_tx_space &&
1745 ((min_tx_space - tx_space) < pba)) {
1746 pba = pba - (min_tx_space - tx_space);
1748 /* if short on rx space, rx wins and must trump tx
1750 if (pba < min_rx_space)
1753 wr32(E1000_PBA, pba);
1756 /* flow control settings */
1757 /* The high water mark must be low enough to fit one full frame
1758 * (or the size used for early receive) above it in the Rx FIFO.
1759 * Set it to the lower of:
1760 * - 90% of the Rx FIFO size, or
1761 * - the full Rx FIFO size minus one full frame */
1762 hwm = min(((pba << 10) * 9 / 10),
1763 ((pba << 10) - 2 * adapter->max_frame_size));
1765 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1766 fc->low_water = fc->high_water - 16;
1767 fc->pause_time = 0xFFFF;
1769 fc->current_mode = fc->requested_mode;
1771 /* disable receive for all VFs and wait one second */
1772 if (adapter->vfs_allocated_count) {
1774 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1775 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1777 /* ping all the active vfs to let them know we are going down */
1778 igb_ping_all_vfs(adapter);
1780 /* disable transmits and receives */
1781 wr32(E1000_VFRE, 0);
1782 wr32(E1000_VFTE, 0);
1785 /* Allow time for pending master requests to run */
1786 hw->mac.ops.reset_hw(hw);
1789 if (hw->mac.ops.init_hw(hw))
1790 dev_err(&pdev->dev, "Hardware Error\n");
1793 * Flow control settings reset on hardware reset, so guarantee flow
1794 * control is off when forcing speed.
1796 if (!hw->mac.autoneg)
1797 igb_force_mac_fc(hw);
1799 igb_init_dmac(adapter, pba);
1800 #ifdef CONFIG_IGB_HWMON
1801 /* Re-initialize the thermal sensor on i350 devices. */
1802 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1803 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1804 /* If present, re-initialize the external thermal sensor
1808 mac->ops.init_thermal_sensor_thresh(hw);
1812 if (!netif_running(adapter->netdev))
1813 igb_power_down_link(adapter);
1815 igb_update_mng_vlan(adapter);
1817 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1818 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1820 /* Re-enable PTP, where applicable. */
1821 igb_ptp_reset(adapter);
1823 igb_get_phy_info(hw);
1826 static netdev_features_t igb_fix_features(struct net_device *netdev,
1827 netdev_features_t features)
1830 * Since there is no support for separate rx/tx vlan accel
1831 * enable/disable make sure tx flag is always in same state as rx.
1833 if (features & NETIF_F_HW_VLAN_RX)
1834 features |= NETIF_F_HW_VLAN_TX;
1836 features &= ~NETIF_F_HW_VLAN_TX;
1841 static int igb_set_features(struct net_device *netdev,
1842 netdev_features_t features)
1844 netdev_features_t changed = netdev->features ^ features;
1845 struct igb_adapter *adapter = netdev_priv(netdev);
1847 if (changed & NETIF_F_HW_VLAN_RX)
1848 igb_vlan_mode(netdev, features);
1850 if (!(changed & NETIF_F_RXALL))
1853 netdev->features = features;
1855 if (netif_running(netdev))
1856 igb_reinit_locked(adapter);
1863 static const struct net_device_ops igb_netdev_ops = {
1864 .ndo_open = igb_open,
1865 .ndo_stop = igb_close,
1866 .ndo_start_xmit = igb_xmit_frame,
1867 .ndo_get_stats64 = igb_get_stats64,
1868 .ndo_set_rx_mode = igb_set_rx_mode,
1869 .ndo_set_mac_address = igb_set_mac,
1870 .ndo_change_mtu = igb_change_mtu,
1871 .ndo_do_ioctl = igb_ioctl,
1872 .ndo_tx_timeout = igb_tx_timeout,
1873 .ndo_validate_addr = eth_validate_addr,
1874 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1875 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1876 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1877 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1878 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1879 .ndo_get_vf_config = igb_ndo_get_vf_config,
1880 #ifdef CONFIG_NET_POLL_CONTROLLER
1881 .ndo_poll_controller = igb_netpoll,
1883 .ndo_fix_features = igb_fix_features,
1884 .ndo_set_features = igb_set_features,
1888 * igb_set_fw_version - Configure version string for ethtool
1889 * @adapter: adapter struct
1892 void igb_set_fw_version(struct igb_adapter *adapter)
1894 struct e1000_hw *hw = &adapter->hw;
1895 struct e1000_fw_version fw;
1897 igb_get_fw_version(hw, &fw);
1899 switch (hw->mac.type) {
1901 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1903 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1907 /* if option is rom valid, display its version too */
1909 snprintf(adapter->fw_version,
1910 sizeof(adapter->fw_version),
1911 "%d.%d, 0x%08x, %d.%d.%d",
1912 fw.eep_major, fw.eep_minor, fw.etrack_id,
1913 fw.or_major, fw.or_build, fw.or_patch);
1916 snprintf(adapter->fw_version,
1917 sizeof(adapter->fw_version),
1919 fw.eep_major, fw.eep_minor, fw.etrack_id);
1926 /* igb_init_i2c - Init I2C interface
1927 * @adapter: pointer to adapter structure
1930 static s32 igb_init_i2c(struct igb_adapter *adapter)
1932 s32 status = E1000_SUCCESS;
1934 /* I2C interface supported on i350 devices */
1935 if (adapter->hw.mac.type != e1000_i350)
1936 return E1000_SUCCESS;
1938 /* Initialize the i2c bus which is controlled by the registers.
1939 * This bus will use the i2c_algo_bit structue that implements
1940 * the protocol through toggling of the 4 bits in the register.
1942 adapter->i2c_adap.owner = THIS_MODULE;
1943 adapter->i2c_algo = igb_i2c_algo;
1944 adapter->i2c_algo.data = adapter;
1945 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1946 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1947 strlcpy(adapter->i2c_adap.name, "igb BB",
1948 sizeof(adapter->i2c_adap.name));
1949 status = i2c_bit_add_bus(&adapter->i2c_adap);
1954 * igb_probe - Device Initialization Routine
1955 * @pdev: PCI device information struct
1956 * @ent: entry in igb_pci_tbl
1958 * Returns 0 on success, negative on failure
1960 * igb_probe initializes an adapter identified by a pci_dev structure.
1961 * The OS initialization, configuring of the adapter private structure,
1962 * and a hardware reset occur.
1964 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1966 struct net_device *netdev;
1967 struct igb_adapter *adapter;
1968 struct e1000_hw *hw;
1969 u16 eeprom_data = 0;
1971 static int global_quad_port_a; /* global quad port a indication */
1972 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1973 unsigned long mmio_start, mmio_len;
1974 int err, pci_using_dac;
1975 u8 part_str[E1000_PBANUM_LENGTH];
1977 /* Catch broken hardware that put the wrong VF device ID in
1978 * the PCIe SR-IOV capability.
1980 if (pdev->is_virtfn) {
1981 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1982 pci_name(pdev), pdev->vendor, pdev->device);
1986 err = pci_enable_device_mem(pdev);
1991 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1993 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1997 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1999 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
2001 dev_err(&pdev->dev, "No usable DMA "
2002 "configuration, aborting\n");
2008 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2014 pci_enable_pcie_error_reporting(pdev);
2016 pci_set_master(pdev);
2017 pci_save_state(pdev);
2020 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2023 goto err_alloc_etherdev;
2025 SET_NETDEV_DEV(netdev, &pdev->dev);
2027 pci_set_drvdata(pdev, netdev);
2028 adapter = netdev_priv(netdev);
2029 adapter->netdev = netdev;
2030 adapter->pdev = pdev;
2033 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2035 mmio_start = pci_resource_start(pdev, 0);
2036 mmio_len = pci_resource_len(pdev, 0);
2039 hw->hw_addr = ioremap(mmio_start, mmio_len);
2043 netdev->netdev_ops = &igb_netdev_ops;
2044 igb_set_ethtool_ops(netdev);
2045 netdev->watchdog_timeo = 5 * HZ;
2047 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2049 netdev->mem_start = mmio_start;
2050 netdev->mem_end = mmio_start + mmio_len;
2052 /* PCI config space info */
2053 hw->vendor_id = pdev->vendor;
2054 hw->device_id = pdev->device;
2055 hw->revision_id = pdev->revision;
2056 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2057 hw->subsystem_device_id = pdev->subsystem_device;
2059 /* Copy the default MAC, PHY and NVM function pointers */
2060 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2061 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2062 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2063 /* Initialize skew-specific constants */
2064 err = ei->get_invariants(hw);
2068 /* setup the private structure */
2069 err = igb_sw_init(adapter);
2073 igb_get_bus_info_pcie(hw);
2075 hw->phy.autoneg_wait_to_complete = false;
2077 /* Copper options */
2078 if (hw->phy.media_type == e1000_media_type_copper) {
2079 hw->phy.mdix = AUTO_ALL_MODES;
2080 hw->phy.disable_polarity_correction = false;
2081 hw->phy.ms_type = e1000_ms_hw_default;
2084 if (igb_check_reset_block(hw))
2085 dev_info(&pdev->dev,
2086 "PHY reset is blocked due to SOL/IDER session.\n");
2089 * features is initialized to 0 in allocation, it might have bits
2090 * set by igb_sw_init so we should use an or instead of an
2093 netdev->features |= NETIF_F_SG |
2100 NETIF_F_HW_VLAN_RX |
2103 /* copy netdev features into list of user selectable features */
2104 netdev->hw_features |= netdev->features;
2105 netdev->hw_features |= NETIF_F_RXALL;
2107 /* set this bit last since it cannot be part of hw_features */
2108 netdev->features |= NETIF_F_HW_VLAN_FILTER;
2110 netdev->vlan_features |= NETIF_F_TSO |
2116 netdev->priv_flags |= IFF_SUPP_NOFCS;
2118 if (pci_using_dac) {
2119 netdev->features |= NETIF_F_HIGHDMA;
2120 netdev->vlan_features |= NETIF_F_HIGHDMA;
2123 if (hw->mac.type >= e1000_82576) {
2124 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2125 netdev->features |= NETIF_F_SCTP_CSUM;
2128 netdev->priv_flags |= IFF_UNICAST_FLT;
2130 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2132 /* before reading the NVM, reset the controller to put the device in a
2133 * known good starting state */
2134 hw->mac.ops.reset_hw(hw);
2137 * make sure the NVM is good , i211 parts have special NVM that
2138 * doesn't contain a checksum
2140 if (hw->mac.type != e1000_i211) {
2141 if (hw->nvm.ops.validate(hw) < 0) {
2142 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2148 /* copy the MAC address out of the NVM */
2149 if (hw->mac.ops.read_mac_addr(hw))
2150 dev_err(&pdev->dev, "NVM Read Error\n");
2152 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2154 if (!is_valid_ether_addr(netdev->dev_addr)) {
2155 dev_err(&pdev->dev, "Invalid MAC Address\n");
2160 /* get firmware version for ethtool -i */
2161 igb_set_fw_version(adapter);
2163 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2164 (unsigned long) adapter);
2165 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2166 (unsigned long) adapter);
2168 INIT_WORK(&adapter->reset_task, igb_reset_task);
2169 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2171 /* Initialize link properties that are user-changeable */
2172 adapter->fc_autoneg = true;
2173 hw->mac.autoneg = true;
2174 hw->phy.autoneg_advertised = 0x2f;
2176 hw->fc.requested_mode = e1000_fc_default;
2177 hw->fc.current_mode = e1000_fc_default;
2179 igb_validate_mdi_setting(hw);
2181 /* By default, support wake on port A */
2182 if (hw->bus.func == 0)
2183 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2185 /* Check the NVM for wake support on non-port A ports */
2186 if (hw->mac.type >= e1000_82580)
2187 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2188 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2190 else if (hw->bus.func == 1)
2191 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2193 if (eeprom_data & IGB_EEPROM_APME)
2194 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2196 /* now that we have the eeprom settings, apply the special cases where
2197 * the eeprom may be wrong or the board simply won't support wake on
2198 * lan on a particular port */
2199 switch (pdev->device) {
2200 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2201 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2203 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2204 case E1000_DEV_ID_82576_FIBER:
2205 case E1000_DEV_ID_82576_SERDES:
2206 /* Wake events only supported on port A for dual fiber
2207 * regardless of eeprom setting */
2208 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2209 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2211 case E1000_DEV_ID_82576_QUAD_COPPER:
2212 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2213 /* if quad port adapter, disable WoL on all but port A */
2214 if (global_quad_port_a != 0)
2215 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2217 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2218 /* Reset for multiple quad port adapters */
2219 if (++global_quad_port_a == 4)
2220 global_quad_port_a = 0;
2223 /* If the device can't wake, don't set software support */
2224 if (!device_can_wakeup(&adapter->pdev->dev))
2225 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2228 /* initialize the wol settings based on the eeprom settings */
2229 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2230 adapter->wol |= E1000_WUFC_MAG;
2232 /* Some vendors want WoL disabled by default, but still supported */
2233 if ((hw->mac.type == e1000_i350) &&
2234 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2235 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2239 device_set_wakeup_enable(&adapter->pdev->dev,
2240 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2242 /* reset the hardware with the new settings */
2245 /* Init the I2C interface */
2246 err = igb_init_i2c(adapter);
2248 dev_err(&pdev->dev, "failed to init i2c interface\n");
2252 /* let the f/w know that the h/w is now under the control of the
2254 igb_get_hw_control(adapter);
2256 strcpy(netdev->name, "eth%d");
2257 err = register_netdev(netdev);
2261 /* carrier off reporting is important to ethtool even BEFORE open */
2262 netif_carrier_off(netdev);
2264 #ifdef CONFIG_IGB_DCA
2265 if (dca_add_requester(&pdev->dev) == 0) {
2266 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2267 dev_info(&pdev->dev, "DCA enabled\n");
2268 igb_setup_dca(adapter);
2272 #ifdef CONFIG_IGB_HWMON
2273 /* Initialize the thermal sensor on i350 devices. */
2274 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2278 * Read the NVM to determine if this i350 device supports an
2279 * external thermal sensor.
2281 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2282 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2283 adapter->ets = true;
2285 adapter->ets = false;
2286 if (igb_sysfs_init(adapter))
2288 "failed to allocate sysfs resources\n");
2290 adapter->ets = false;
2293 /* do hw tstamp init after resetting */
2294 igb_ptp_init(adapter);
2296 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2297 /* print bus type/speed/width info */
2298 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2300 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2301 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2303 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2304 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2305 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2309 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2311 strcpy(part_str, "Unknown");
2312 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2313 dev_info(&pdev->dev,
2314 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2315 adapter->msix_entries ? "MSI-X" :
2316 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2317 adapter->num_rx_queues, adapter->num_tx_queues);
2318 switch (hw->mac.type) {
2322 igb_set_eee_i350(hw);
2328 pm_runtime_put_noidle(&pdev->dev);
2332 igb_release_hw_control(adapter);
2333 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2335 if (!igb_check_reset_block(hw))
2338 if (hw->flash_address)
2339 iounmap(hw->flash_address);
2341 igb_clear_interrupt_scheme(adapter);
2342 iounmap(hw->hw_addr);
2344 free_netdev(netdev);
2346 pci_release_selected_regions(pdev,
2347 pci_select_bars(pdev, IORESOURCE_MEM));
2350 pci_disable_device(pdev);
2354 #ifdef CONFIG_PCI_IOV
2355 static int igb_disable_sriov(struct pci_dev *pdev)
2357 struct net_device *netdev = pci_get_drvdata(pdev);
2358 struct igb_adapter *adapter = netdev_priv(netdev);
2359 struct e1000_hw *hw = &adapter->hw;
2361 /* reclaim resources allocated to VFs */
2362 if (adapter->vf_data) {
2363 /* disable iov and allow time for transactions to clear */
2364 if (igb_vfs_are_assigned(adapter)) {
2365 dev_warn(&pdev->dev,
2366 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2369 pci_disable_sriov(pdev);
2373 kfree(adapter->vf_data);
2374 adapter->vf_data = NULL;
2375 adapter->vfs_allocated_count = 0;
2376 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2379 dev_info(&pdev->dev, "IOV Disabled\n");
2381 /* Re-enable DMA Coalescing flag since IOV is turned off */
2382 adapter->flags |= IGB_FLAG_DMAC;
2388 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2390 struct net_device *netdev = pci_get_drvdata(pdev);
2391 struct igb_adapter *adapter = netdev_priv(netdev);
2392 int old_vfs = pci_num_vf(pdev);
2398 else if (old_vfs && old_vfs == num_vfs)
2400 else if (old_vfs && old_vfs != num_vfs)
2401 err = igb_disable_sriov(pdev);
2411 adapter->vfs_allocated_count = num_vfs;
2413 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2414 sizeof(struct vf_data_storage), GFP_KERNEL);
2416 /* if allocation failed then we do not support SR-IOV */
2417 if (!adapter->vf_data) {
2418 adapter->vfs_allocated_count = 0;
2420 "Unable to allocate memory for VF Data Storage\n");
2425 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2429 dev_info(&pdev->dev, "%d VFs allocated\n",
2430 adapter->vfs_allocated_count);
2431 for (i = 0; i < adapter->vfs_allocated_count; i++)
2432 igb_vf_configure(adapter, i);
2434 /* DMA Coalescing is not supported in IOV mode. */
2435 adapter->flags &= ~IGB_FLAG_DMAC;
2439 kfree(adapter->vf_data);
2440 adapter->vf_data = NULL;
2441 adapter->vfs_allocated_count = 0;
2448 * igb_remove_i2c - Cleanup I2C interface
2449 * @adapter: pointer to adapter structure
2452 static void igb_remove_i2c(struct igb_adapter *adapter)
2455 /* free the adapter bus structure */
2456 i2c_del_adapter(&adapter->i2c_adap);
2460 * igb_remove - Device Removal Routine
2461 * @pdev: PCI device information struct
2463 * igb_remove is called by the PCI subsystem to alert the driver
2464 * that it should release a PCI device. The could be caused by a
2465 * Hot-Plug event, or because the driver is going to be removed from
2468 static void igb_remove(struct pci_dev *pdev)
2470 struct net_device *netdev = pci_get_drvdata(pdev);
2471 struct igb_adapter *adapter = netdev_priv(netdev);
2472 struct e1000_hw *hw = &adapter->hw;
2474 pm_runtime_get_noresume(&pdev->dev);
2475 #ifdef CONFIG_IGB_HWMON
2476 igb_sysfs_exit(adapter);
2478 igb_remove_i2c(adapter);
2479 igb_ptp_stop(adapter);
2481 * The watchdog timer may be rescheduled, so explicitly
2482 * disable watchdog from being rescheduled.
2484 set_bit(__IGB_DOWN, &adapter->state);
2485 del_timer_sync(&adapter->watchdog_timer);
2486 del_timer_sync(&adapter->phy_info_timer);
2488 cancel_work_sync(&adapter->reset_task);
2489 cancel_work_sync(&adapter->watchdog_task);
2491 #ifdef CONFIG_IGB_DCA
2492 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2493 dev_info(&pdev->dev, "DCA disabled\n");
2494 dca_remove_requester(&pdev->dev);
2495 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2496 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2500 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2501 * would have already happened in close and is redundant. */
2502 igb_release_hw_control(adapter);
2504 unregister_netdev(netdev);
2506 igb_clear_interrupt_scheme(adapter);
2508 #ifdef CONFIG_PCI_IOV
2509 igb_disable_sriov(pdev);
2512 iounmap(hw->hw_addr);
2513 if (hw->flash_address)
2514 iounmap(hw->flash_address);
2515 pci_release_selected_regions(pdev,
2516 pci_select_bars(pdev, IORESOURCE_MEM));
2518 kfree(adapter->shadow_vfta);
2519 free_netdev(netdev);
2521 pci_disable_pcie_error_reporting(pdev);
2523 pci_disable_device(pdev);
2527 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2528 * @adapter: board private structure to initialize
2530 * This function initializes the vf specific data storage and then attempts to
2531 * allocate the VFs. The reason for ordering it this way is because it is much
2532 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2533 * the memory for the VFs.
2535 static void igb_probe_vfs(struct igb_adapter *adapter)
2537 #ifdef CONFIG_PCI_IOV
2538 struct pci_dev *pdev = adapter->pdev;
2539 struct e1000_hw *hw = &adapter->hw;
2541 /* Virtualization features not supported on i210 family. */
2542 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2545 pci_sriov_set_totalvfs(pdev, 7);
2546 igb_enable_sriov(pdev, max_vfs);
2548 #endif /* CONFIG_PCI_IOV */
2551 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2553 struct e1000_hw *hw = &adapter->hw;
2556 /* Determine the maximum number of RSS queues supported. */
2557 switch (hw->mac.type) {
2559 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2563 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2566 /* I350 cannot do RSS and SR-IOV at the same time */
2567 if (!!adapter->vfs_allocated_count) {
2573 if (!!adapter->vfs_allocated_count) {
2580 max_rss_queues = IGB_MAX_RX_QUEUES;
2584 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2586 /* Determine if we need to pair queues. */
2587 switch (hw->mac.type) {
2590 /* Device supports enough interrupts without queue pairing. */
2594 * If VFs are going to be allocated with RSS queues then we
2595 * should pair the queues in order to conserve interrupts due
2596 * to limited supply.
2598 if ((adapter->rss_queues > 1) &&
2599 (adapter->vfs_allocated_count > 6))
2600 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2607 * If rss_queues > half of max_rss_queues, pair the queues in
2608 * order to conserve interrupts due to limited supply.
2610 if (adapter->rss_queues > (max_rss_queues / 2))
2611 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2617 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2618 * @adapter: board private structure to initialize
2620 * igb_sw_init initializes the Adapter private data structure.
2621 * Fields are initialized based on PCI device information and
2622 * OS network device settings (MTU size).
2624 static int igb_sw_init(struct igb_adapter *adapter)
2626 struct e1000_hw *hw = &adapter->hw;
2627 struct net_device *netdev = adapter->netdev;
2628 struct pci_dev *pdev = adapter->pdev;
2630 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2632 /* set default ring sizes */
2633 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2634 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2636 /* set default ITR values */
2637 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2638 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2640 /* set default work limits */
2641 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2643 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2645 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2647 spin_lock_init(&adapter->stats64_lock);
2648 #ifdef CONFIG_PCI_IOV
2649 switch (hw->mac.type) {
2653 dev_warn(&pdev->dev,
2654 "Maximum of 7 VFs per PF, using max\n");
2655 max_vfs = adapter->vfs_allocated_count = 7;
2657 adapter->vfs_allocated_count = max_vfs;
2658 if (adapter->vfs_allocated_count)
2659 dev_warn(&pdev->dev,
2660 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2665 #endif /* CONFIG_PCI_IOV */
2667 igb_init_queue_configuration(adapter);
2669 /* Setup and initialize a copy of the hw vlan table array */
2670 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2673 /* This call may decrease the number of queues */
2674 if (igb_init_interrupt_scheme(adapter, true)) {
2675 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2679 igb_probe_vfs(adapter);
2681 /* Explicitly disable IRQ since the NIC can be in any state. */
2682 igb_irq_disable(adapter);
2684 if (hw->mac.type >= e1000_i350)
2685 adapter->flags &= ~IGB_FLAG_DMAC;
2687 set_bit(__IGB_DOWN, &adapter->state);
2692 * igb_open - Called when a network interface is made active
2693 * @netdev: network interface device structure
2695 * Returns 0 on success, negative value on failure
2697 * The open entry point is called when a network interface is made
2698 * active by the system (IFF_UP). At this point all resources needed
2699 * for transmit and receive operations are allocated, the interrupt
2700 * handler is registered with the OS, the watchdog timer is started,
2701 * and the stack is notified that the interface is ready.
2703 static int __igb_open(struct net_device *netdev, bool resuming)
2705 struct igb_adapter *adapter = netdev_priv(netdev);
2706 struct e1000_hw *hw = &adapter->hw;
2707 struct pci_dev *pdev = adapter->pdev;
2711 /* disallow open during test */
2712 if (test_bit(__IGB_TESTING, &adapter->state)) {
2718 pm_runtime_get_sync(&pdev->dev);
2720 netif_carrier_off(netdev);
2722 /* allocate transmit descriptors */
2723 err = igb_setup_all_tx_resources(adapter);
2727 /* allocate receive descriptors */
2728 err = igb_setup_all_rx_resources(adapter);
2732 igb_power_up_link(adapter);
2734 /* before we allocate an interrupt, we must be ready to handle it.
2735 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2736 * as soon as we call pci_request_irq, so we have to setup our
2737 * clean_rx handler before we do so. */
2738 igb_configure(adapter);
2740 err = igb_request_irq(adapter);
2744 /* Notify the stack of the actual queue counts. */
2745 err = netif_set_real_num_tx_queues(adapter->netdev,
2746 adapter->num_tx_queues);
2748 goto err_set_queues;
2750 err = netif_set_real_num_rx_queues(adapter->netdev,
2751 adapter->num_rx_queues);
2753 goto err_set_queues;
2755 /* From here on the code is the same as igb_up() */
2756 clear_bit(__IGB_DOWN, &adapter->state);
2758 for (i = 0; i < adapter->num_q_vectors; i++)
2759 napi_enable(&(adapter->q_vector[i]->napi));
2761 /* Clear any pending interrupts. */
2764 igb_irq_enable(adapter);
2766 /* notify VFs that reset has been completed */
2767 if (adapter->vfs_allocated_count) {
2768 u32 reg_data = rd32(E1000_CTRL_EXT);
2769 reg_data |= E1000_CTRL_EXT_PFRSTD;
2770 wr32(E1000_CTRL_EXT, reg_data);
2773 netif_tx_start_all_queues(netdev);
2776 pm_runtime_put(&pdev->dev);
2778 /* start the watchdog. */
2779 hw->mac.get_link_status = 1;
2780 schedule_work(&adapter->watchdog_task);
2785 igb_free_irq(adapter);
2787 igb_release_hw_control(adapter);
2788 igb_power_down_link(adapter);
2789 igb_free_all_rx_resources(adapter);
2791 igb_free_all_tx_resources(adapter);
2795 pm_runtime_put(&pdev->dev);
2800 static int igb_open(struct net_device *netdev)
2802 return __igb_open(netdev, false);
2806 * igb_close - Disables a network interface
2807 * @netdev: network interface device structure
2809 * Returns 0, this is not allowed to fail
2811 * The close entry point is called when an interface is de-activated
2812 * by the OS. The hardware is still under the driver's control, but
2813 * needs to be disabled. A global MAC reset is issued to stop the
2814 * hardware, and all transmit and receive resources are freed.
2816 static int __igb_close(struct net_device *netdev, bool suspending)
2818 struct igb_adapter *adapter = netdev_priv(netdev);
2819 struct pci_dev *pdev = adapter->pdev;
2821 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2824 pm_runtime_get_sync(&pdev->dev);
2827 igb_free_irq(adapter);
2829 igb_free_all_tx_resources(adapter);
2830 igb_free_all_rx_resources(adapter);
2833 pm_runtime_put_sync(&pdev->dev);
2837 static int igb_close(struct net_device *netdev)
2839 return __igb_close(netdev, false);
2843 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2844 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2846 * Return 0 on success, negative on failure
2848 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2850 struct device *dev = tx_ring->dev;
2853 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2855 tx_ring->tx_buffer_info = vzalloc(size);
2856 if (!tx_ring->tx_buffer_info)
2859 /* round up to nearest 4K */
2860 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2861 tx_ring->size = ALIGN(tx_ring->size, 4096);
2863 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2864 &tx_ring->dma, GFP_KERNEL);
2868 tx_ring->next_to_use = 0;
2869 tx_ring->next_to_clean = 0;
2874 vfree(tx_ring->tx_buffer_info);
2875 tx_ring->tx_buffer_info = NULL;
2876 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2881 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2882 * (Descriptors) for all queues
2883 * @adapter: board private structure
2885 * Return 0 on success, negative on failure
2887 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2889 struct pci_dev *pdev = adapter->pdev;
2892 for (i = 0; i < adapter->num_tx_queues; i++) {
2893 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2896 "Allocation for Tx Queue %u failed\n", i);
2897 for (i--; i >= 0; i--)
2898 igb_free_tx_resources(adapter->tx_ring[i]);
2907 * igb_setup_tctl - configure the transmit control registers
2908 * @adapter: Board private structure
2910 void igb_setup_tctl(struct igb_adapter *adapter)
2912 struct e1000_hw *hw = &adapter->hw;
2915 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2916 wr32(E1000_TXDCTL(0), 0);
2918 /* Program the Transmit Control Register */
2919 tctl = rd32(E1000_TCTL);
2920 tctl &= ~E1000_TCTL_CT;
2921 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2922 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2924 igb_config_collision_dist(hw);
2926 /* Enable transmits */
2927 tctl |= E1000_TCTL_EN;
2929 wr32(E1000_TCTL, tctl);
2933 * igb_configure_tx_ring - Configure transmit ring after Reset
2934 * @adapter: board private structure
2935 * @ring: tx ring to configure
2937 * Configure a transmit ring after a reset.
2939 void igb_configure_tx_ring(struct igb_adapter *adapter,
2940 struct igb_ring *ring)
2942 struct e1000_hw *hw = &adapter->hw;
2944 u64 tdba = ring->dma;
2945 int reg_idx = ring->reg_idx;
2947 /* disable the queue */
2948 wr32(E1000_TXDCTL(reg_idx), 0);
2952 wr32(E1000_TDLEN(reg_idx),
2953 ring->count * sizeof(union e1000_adv_tx_desc));
2954 wr32(E1000_TDBAL(reg_idx),
2955 tdba & 0x00000000ffffffffULL);
2956 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2958 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2959 wr32(E1000_TDH(reg_idx), 0);
2960 writel(0, ring->tail);
2962 txdctl |= IGB_TX_PTHRESH;
2963 txdctl |= IGB_TX_HTHRESH << 8;
2964 txdctl |= IGB_TX_WTHRESH << 16;
2966 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2967 wr32(E1000_TXDCTL(reg_idx), txdctl);
2971 * igb_configure_tx - Configure transmit Unit after Reset
2972 * @adapter: board private structure
2974 * Configure the Tx unit of the MAC after a reset.
2976 static void igb_configure_tx(struct igb_adapter *adapter)
2980 for (i = 0; i < adapter->num_tx_queues; i++)
2981 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2985 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2986 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2988 * Returns 0 on success, negative on failure
2990 int igb_setup_rx_resources(struct igb_ring *rx_ring)
2992 struct device *dev = rx_ring->dev;
2995 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
2997 rx_ring->rx_buffer_info = vzalloc(size);
2998 if (!rx_ring->rx_buffer_info)
3001 /* Round up to nearest 4K */
3002 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3003 rx_ring->size = ALIGN(rx_ring->size, 4096);
3005 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3006 &rx_ring->dma, GFP_KERNEL);
3010 rx_ring->next_to_alloc = 0;
3011 rx_ring->next_to_clean = 0;
3012 rx_ring->next_to_use = 0;
3017 vfree(rx_ring->rx_buffer_info);
3018 rx_ring->rx_buffer_info = NULL;
3019 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3024 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3025 * (Descriptors) for all queues
3026 * @adapter: board private structure
3028 * Return 0 on success, negative on failure
3030 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3032 struct pci_dev *pdev = adapter->pdev;
3035 for (i = 0; i < adapter->num_rx_queues; i++) {
3036 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3039 "Allocation for Rx Queue %u failed\n", i);
3040 for (i--; i >= 0; i--)
3041 igb_free_rx_resources(adapter->rx_ring[i]);
3050 * igb_setup_mrqc - configure the multiple receive queue control registers
3051 * @adapter: Board private structure
3053 static void igb_setup_mrqc(struct igb_adapter *adapter)
3055 struct e1000_hw *hw = &adapter->hw;
3057 u32 j, num_rx_queues, shift = 0;
3058 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3059 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3060 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3063 /* Fill out hash function seeds */
3064 for (j = 0; j < 10; j++)
3065 wr32(E1000_RSSRK(j), rsskey[j]);
3067 num_rx_queues = adapter->rss_queues;
3069 switch (hw->mac.type) {
3074 /* 82576 supports 2 RSS queues for SR-IOV */
3075 if (adapter->vfs_allocated_count) {
3085 * Populate the indirection table 4 entries at a time. To do this
3086 * we are generating the results for n and n+2 and then interleaving
3087 * those with the results with n+1 and n+3.
3089 for (j = 0; j < 32; j++) {
3090 /* first pass generates n and n+2 */
3091 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3092 u32 reta = (base & 0x07800780) >> (7 - shift);
3094 /* second pass generates n+1 and n+3 */
3095 base += 0x00010001 * num_rx_queues;
3096 reta |= (base & 0x07800780) << (1 + shift);
3098 wr32(E1000_RETA(j), reta);
3102 * Disable raw packet checksumming so that RSS hash is placed in
3103 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3104 * offloads as they are enabled by default
3106 rxcsum = rd32(E1000_RXCSUM);
3107 rxcsum |= E1000_RXCSUM_PCSD;
3109 if (adapter->hw.mac.type >= e1000_82576)
3110 /* Enable Receive Checksum Offload for SCTP */
3111 rxcsum |= E1000_RXCSUM_CRCOFL;
3113 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3114 wr32(E1000_RXCSUM, rxcsum);
3116 /* Generate RSS hash based on packet types, TCP/UDP
3117 * port numbers and/or IPv4/v6 src and dst addresses
3119 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3120 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3121 E1000_MRQC_RSS_FIELD_IPV6 |
3122 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3123 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3125 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3126 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3127 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3128 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3130 /* If VMDq is enabled then we set the appropriate mode for that, else
3131 * we default to RSS so that an RSS hash is calculated per packet even
3132 * if we are only using one queue */
3133 if (adapter->vfs_allocated_count) {
3134 if (hw->mac.type > e1000_82575) {
3135 /* Set the default pool for the PF's first queue */
3136 u32 vtctl = rd32(E1000_VT_CTL);
3137 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3138 E1000_VT_CTL_DISABLE_DEF_POOL);
3139 vtctl |= adapter->vfs_allocated_count <<
3140 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3141 wr32(E1000_VT_CTL, vtctl);
3143 if (adapter->rss_queues > 1)
3144 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3146 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3148 if (hw->mac.type != e1000_i211)
3149 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3151 igb_vmm_control(adapter);
3153 wr32(E1000_MRQC, mrqc);
3157 * igb_setup_rctl - configure the receive control registers
3158 * @adapter: Board private structure
3160 void igb_setup_rctl(struct igb_adapter *adapter)
3162 struct e1000_hw *hw = &adapter->hw;
3165 rctl = rd32(E1000_RCTL);
3167 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3168 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3170 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3171 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3174 * enable stripping of CRC. It's unlikely this will break BMC
3175 * redirection as it did with e1000. Newer features require
3176 * that the HW strips the CRC.
3178 rctl |= E1000_RCTL_SECRC;
3180 /* disable store bad packets and clear size bits. */
3181 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3183 /* enable LPE to prevent packets larger than max_frame_size */
3184 rctl |= E1000_RCTL_LPE;
3186 /* disable queue 0 to prevent tail write w/o re-config */
3187 wr32(E1000_RXDCTL(0), 0);
3189 /* Attention!!! For SR-IOV PF driver operations you must enable
3190 * queue drop for all VF and PF queues to prevent head of line blocking
3191 * if an un-trusted VF does not provide descriptors to hardware.
3193 if (adapter->vfs_allocated_count) {
3194 /* set all queue drop enable bits */
3195 wr32(E1000_QDE, ALL_QUEUES);
3198 /* This is useful for sniffing bad packets. */
3199 if (adapter->netdev->features & NETIF_F_RXALL) {
3200 /* UPE and MPE will be handled by normal PROMISC logic
3201 * in e1000e_set_rx_mode */
3202 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3203 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3204 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3206 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3207 E1000_RCTL_DPF | /* Allow filtered pause */
3208 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3209 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3210 * and that breaks VLANs.
3214 wr32(E1000_RCTL, rctl);
3217 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3220 struct e1000_hw *hw = &adapter->hw;
3223 /* if it isn't the PF check to see if VFs are enabled and
3224 * increase the size to support vlan tags */
3225 if (vfn < adapter->vfs_allocated_count &&
3226 adapter->vf_data[vfn].vlans_enabled)
3227 size += VLAN_TAG_SIZE;
3229 vmolr = rd32(E1000_VMOLR(vfn));
3230 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3231 vmolr |= size | E1000_VMOLR_LPE;
3232 wr32(E1000_VMOLR(vfn), vmolr);
3238 * igb_rlpml_set - set maximum receive packet size
3239 * @adapter: board private structure
3241 * Configure maximum receivable packet size.
3243 static void igb_rlpml_set(struct igb_adapter *adapter)
3245 u32 max_frame_size = adapter->max_frame_size;
3246 struct e1000_hw *hw = &adapter->hw;
3247 u16 pf_id = adapter->vfs_allocated_count;
3250 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3252 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3253 * to our max jumbo frame size, in case we need to enable
3254 * jumbo frames on one of the rings later.
3255 * This will not pass over-length frames into the default
3256 * queue because it's gated by the VMOLR.RLPML.
3258 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3261 wr32(E1000_RLPML, max_frame_size);
3264 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3267 struct e1000_hw *hw = &adapter->hw;
3271 * This register exists only on 82576 and newer so if we are older then
3272 * we should exit and do nothing
3274 if (hw->mac.type < e1000_82576)
3277 vmolr = rd32(E1000_VMOLR(vfn));
3278 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3280 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3282 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3284 /* clear all bits that might not be set */
3285 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3287 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3288 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3290 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3293 if (vfn <= adapter->vfs_allocated_count)
3294 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3296 wr32(E1000_VMOLR(vfn), vmolr);
3300 * igb_configure_rx_ring - Configure a receive ring after Reset
3301 * @adapter: board private structure
3302 * @ring: receive ring to be configured
3304 * Configure the Rx unit of the MAC after a reset.
3306 void igb_configure_rx_ring(struct igb_adapter *adapter,
3307 struct igb_ring *ring)
3309 struct e1000_hw *hw = &adapter->hw;
3310 u64 rdba = ring->dma;
3311 int reg_idx = ring->reg_idx;
3312 u32 srrctl = 0, rxdctl = 0;
3314 /* disable the queue */
3315 wr32(E1000_RXDCTL(reg_idx), 0);
3317 /* Set DMA base address registers */
3318 wr32(E1000_RDBAL(reg_idx),
3319 rdba & 0x00000000ffffffffULL);
3320 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3321 wr32(E1000_RDLEN(reg_idx),
3322 ring->count * sizeof(union e1000_adv_rx_desc));
3324 /* initialize head and tail */
3325 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3326 wr32(E1000_RDH(reg_idx), 0);
3327 writel(0, ring->tail);
3329 /* set descriptor configuration */
3330 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3331 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3332 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3333 if (hw->mac.type >= e1000_82580)
3334 srrctl |= E1000_SRRCTL_TIMESTAMP;
3335 /* Only set Drop Enable if we are supporting multiple queues */
3336 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3337 srrctl |= E1000_SRRCTL_DROP_EN;
3339 wr32(E1000_SRRCTL(reg_idx), srrctl);
3341 /* set filtering for VMDQ pools */
3342 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3344 rxdctl |= IGB_RX_PTHRESH;
3345 rxdctl |= IGB_RX_HTHRESH << 8;
3346 rxdctl |= IGB_RX_WTHRESH << 16;
3348 /* enable receive descriptor fetching */
3349 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3350 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3353 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
3354 struct igb_ring *rx_ring)
3356 #define IGB_MAX_BUILD_SKB_SIZE \
3357 (SKB_WITH_OVERHEAD(IGB_RX_BUFSZ) - \
3358 (NET_SKB_PAD + NET_IP_ALIGN + IGB_TS_HDR_LEN))
3360 /* set build_skb flag */
3361 if (adapter->max_frame_size <= IGB_MAX_BUILD_SKB_SIZE)
3362 set_ring_build_skb_enabled(rx_ring);
3364 clear_ring_build_skb_enabled(rx_ring);
3368 * igb_configure_rx - Configure receive Unit after Reset
3369 * @adapter: board private structure
3371 * Configure the Rx unit of the MAC after a reset.
3373 static void igb_configure_rx(struct igb_adapter *adapter)
3377 /* set UTA to appropriate mode */
3378 igb_set_uta(adapter);
3380 /* set the correct pool for the PF default MAC address in entry 0 */
3381 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3382 adapter->vfs_allocated_count);
3384 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3385 * the Base and Length of the Rx Descriptor Ring */
3386 for (i = 0; i < adapter->num_rx_queues; i++) {
3387 struct igb_ring *rx_ring = adapter->rx_ring[i];
3388 igb_set_rx_buffer_len(adapter, rx_ring);
3389 igb_configure_rx_ring(adapter, rx_ring);
3394 * igb_free_tx_resources - Free Tx Resources per Queue
3395 * @tx_ring: Tx descriptor ring for a specific queue
3397 * Free all transmit software resources
3399 void igb_free_tx_resources(struct igb_ring *tx_ring)
3401 igb_clean_tx_ring(tx_ring);
3403 vfree(tx_ring->tx_buffer_info);
3404 tx_ring->tx_buffer_info = NULL;
3406 /* if not set, then don't free */
3410 dma_free_coherent(tx_ring->dev, tx_ring->size,
3411 tx_ring->desc, tx_ring->dma);
3413 tx_ring->desc = NULL;
3417 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3418 * @adapter: board private structure
3420 * Free all transmit software resources
3422 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3426 for (i = 0; i < adapter->num_tx_queues; i++)
3427 igb_free_tx_resources(adapter->tx_ring[i]);
3430 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3431 struct igb_tx_buffer *tx_buffer)
3433 if (tx_buffer->skb) {
3434 dev_kfree_skb_any(tx_buffer->skb);
3435 if (dma_unmap_len(tx_buffer, len))
3436 dma_unmap_single(ring->dev,
3437 dma_unmap_addr(tx_buffer, dma),
3438 dma_unmap_len(tx_buffer, len),
3440 } else if (dma_unmap_len(tx_buffer, len)) {
3441 dma_unmap_page(ring->dev,
3442 dma_unmap_addr(tx_buffer, dma),
3443 dma_unmap_len(tx_buffer, len),
3446 tx_buffer->next_to_watch = NULL;
3447 tx_buffer->skb = NULL;
3448 dma_unmap_len_set(tx_buffer, len, 0);
3449 /* buffer_info must be completely set up in the transmit path */
3453 * igb_clean_tx_ring - Free Tx Buffers
3454 * @tx_ring: ring to be cleaned
3456 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3458 struct igb_tx_buffer *buffer_info;
3462 if (!tx_ring->tx_buffer_info)
3464 /* Free all the Tx ring sk_buffs */
3466 for (i = 0; i < tx_ring->count; i++) {
3467 buffer_info = &tx_ring->tx_buffer_info[i];
3468 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3471 netdev_tx_reset_queue(txring_txq(tx_ring));
3473 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3474 memset(tx_ring->tx_buffer_info, 0, size);
3476 /* Zero out the descriptor ring */
3477 memset(tx_ring->desc, 0, tx_ring->size);
3479 tx_ring->next_to_use = 0;
3480 tx_ring->next_to_clean = 0;
3484 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3485 * @adapter: board private structure
3487 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3491 for (i = 0; i < adapter->num_tx_queues; i++)
3492 igb_clean_tx_ring(adapter->tx_ring[i]);
3496 * igb_free_rx_resources - Free Rx Resources
3497 * @rx_ring: ring to clean the resources from
3499 * Free all receive software resources
3501 void igb_free_rx_resources(struct igb_ring *rx_ring)
3503 igb_clean_rx_ring(rx_ring);
3505 vfree(rx_ring->rx_buffer_info);
3506 rx_ring->rx_buffer_info = NULL;
3508 /* if not set, then don't free */
3512 dma_free_coherent(rx_ring->dev, rx_ring->size,
3513 rx_ring->desc, rx_ring->dma);
3515 rx_ring->desc = NULL;
3519 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3520 * @adapter: board private structure
3522 * Free all receive software resources
3524 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3528 for (i = 0; i < adapter->num_rx_queues; i++)
3529 igb_free_rx_resources(adapter->rx_ring[i]);
3533 * igb_clean_rx_ring - Free Rx Buffers per Queue
3534 * @rx_ring: ring to free buffers from
3536 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3542 dev_kfree_skb(rx_ring->skb);
3543 rx_ring->skb = NULL;
3545 if (!rx_ring->rx_buffer_info)
3548 /* Free all the Rx ring sk_buffs */
3549 for (i = 0; i < rx_ring->count; i++) {
3550 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3552 if (!buffer_info->page)
3555 dma_unmap_page(rx_ring->dev,
3559 __free_page(buffer_info->page);
3561 buffer_info->page = NULL;
3564 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3565 memset(rx_ring->rx_buffer_info, 0, size);
3567 /* Zero out the descriptor ring */
3568 memset(rx_ring->desc, 0, rx_ring->size);
3570 rx_ring->next_to_alloc = 0;
3571 rx_ring->next_to_clean = 0;
3572 rx_ring->next_to_use = 0;
3576 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3577 * @adapter: board private structure
3579 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3583 for (i = 0; i < adapter->num_rx_queues; i++)
3584 igb_clean_rx_ring(adapter->rx_ring[i]);
3588 * igb_set_mac - Change the Ethernet Address of the NIC
3589 * @netdev: network interface device structure
3590 * @p: pointer to an address structure
3592 * Returns 0 on success, negative on failure
3594 static int igb_set_mac(struct net_device *netdev, void *p)
3596 struct igb_adapter *adapter = netdev_priv(netdev);
3597 struct e1000_hw *hw = &adapter->hw;
3598 struct sockaddr *addr = p;
3600 if (!is_valid_ether_addr(addr->sa_data))
3601 return -EADDRNOTAVAIL;
3603 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3604 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3606 /* set the correct pool for the new PF MAC address in entry 0 */
3607 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3608 adapter->vfs_allocated_count);
3614 * igb_write_mc_addr_list - write multicast addresses to MTA
3615 * @netdev: network interface device structure
3617 * Writes multicast address list to the MTA hash table.
3618 * Returns: -ENOMEM on failure
3619 * 0 on no addresses written
3620 * X on writing X addresses to MTA
3622 static int igb_write_mc_addr_list(struct net_device *netdev)
3624 struct igb_adapter *adapter = netdev_priv(netdev);
3625 struct e1000_hw *hw = &adapter->hw;
3626 struct netdev_hw_addr *ha;
3630 if (netdev_mc_empty(netdev)) {
3631 /* nothing to program, so clear mc list */
3632 igb_update_mc_addr_list(hw, NULL, 0);
3633 igb_restore_vf_multicasts(adapter);
3637 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3641 /* The shared function expects a packed array of only addresses. */
3643 netdev_for_each_mc_addr(ha, netdev)
3644 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3646 igb_update_mc_addr_list(hw, mta_list, i);
3649 return netdev_mc_count(netdev);
3653 * igb_write_uc_addr_list - write unicast addresses to RAR table
3654 * @netdev: network interface device structure
3656 * Writes unicast address list to the RAR table.
3657 * Returns: -ENOMEM on failure/insufficient address space
3658 * 0 on no addresses written
3659 * X on writing X addresses to the RAR table
3661 static int igb_write_uc_addr_list(struct net_device *netdev)
3663 struct igb_adapter *adapter = netdev_priv(netdev);
3664 struct e1000_hw *hw = &adapter->hw;
3665 unsigned int vfn = adapter->vfs_allocated_count;
3666 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3669 /* return ENOMEM indicating insufficient memory for addresses */
3670 if (netdev_uc_count(netdev) > rar_entries)
3673 if (!netdev_uc_empty(netdev) && rar_entries) {
3674 struct netdev_hw_addr *ha;
3676 netdev_for_each_uc_addr(ha, netdev) {
3679 igb_rar_set_qsel(adapter, ha->addr,
3685 /* write the addresses in reverse order to avoid write combining */
3686 for (; rar_entries > 0 ; rar_entries--) {
3687 wr32(E1000_RAH(rar_entries), 0);
3688 wr32(E1000_RAL(rar_entries), 0);
3696 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3697 * @netdev: network interface device structure
3699 * The set_rx_mode entry point is called whenever the unicast or multicast
3700 * address lists or the network interface flags are updated. This routine is
3701 * responsible for configuring the hardware for proper unicast, multicast,
3702 * promiscuous mode, and all-multi behavior.
3704 static void igb_set_rx_mode(struct net_device *netdev)
3706 struct igb_adapter *adapter = netdev_priv(netdev);
3707 struct e1000_hw *hw = &adapter->hw;
3708 unsigned int vfn = adapter->vfs_allocated_count;
3709 u32 rctl, vmolr = 0;
3712 /* Check for Promiscuous and All Multicast modes */
3713 rctl = rd32(E1000_RCTL);
3715 /* clear the effected bits */
3716 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3718 if (netdev->flags & IFF_PROMISC) {
3719 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3720 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3722 if (netdev->flags & IFF_ALLMULTI) {
3723 rctl |= E1000_RCTL_MPE;
3724 vmolr |= E1000_VMOLR_MPME;
3727 * Write addresses to the MTA, if the attempt fails
3728 * then we should just turn on promiscuous mode so
3729 * that we can at least receive multicast traffic
3731 count = igb_write_mc_addr_list(netdev);
3733 rctl |= E1000_RCTL_MPE;
3734 vmolr |= E1000_VMOLR_MPME;
3736 vmolr |= E1000_VMOLR_ROMPE;
3740 * Write addresses to available RAR registers, if there is not
3741 * sufficient space to store all the addresses then enable
3742 * unicast promiscuous mode
3744 count = igb_write_uc_addr_list(netdev);
3746 rctl |= E1000_RCTL_UPE;
3747 vmolr |= E1000_VMOLR_ROPE;
3749 rctl |= E1000_RCTL_VFE;
3751 wr32(E1000_RCTL, rctl);
3754 * In order to support SR-IOV and eventually VMDq it is necessary to set
3755 * the VMOLR to enable the appropriate modes. Without this workaround
3756 * we will have issues with VLAN tag stripping not being done for frames
3757 * that are only arriving because we are the default pool
3759 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3762 vmolr |= rd32(E1000_VMOLR(vfn)) &
3763 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3764 wr32(E1000_VMOLR(vfn), vmolr);
3765 igb_restore_vf_multicasts(adapter);
3768 static void igb_check_wvbr(struct igb_adapter *adapter)
3770 struct e1000_hw *hw = &adapter->hw;
3773 switch (hw->mac.type) {
3776 if (!(wvbr = rd32(E1000_WVBR)))
3783 adapter->wvbr |= wvbr;
3786 #define IGB_STAGGERED_QUEUE_OFFSET 8
3788 static void igb_spoof_check(struct igb_adapter *adapter)
3795 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3796 if (adapter->wvbr & (1 << j) ||
3797 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3798 dev_warn(&adapter->pdev->dev,
3799 "Spoof event(s) detected on VF %d\n", j);
3802 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3807 /* Need to wait a few seconds after link up to get diagnostic information from
3809 static void igb_update_phy_info(unsigned long data)
3811 struct igb_adapter *adapter = (struct igb_adapter *) data;
3812 igb_get_phy_info(&adapter->hw);
3816 * igb_has_link - check shared code for link and determine up/down
3817 * @adapter: pointer to driver private info
3819 bool igb_has_link(struct igb_adapter *adapter)
3821 struct e1000_hw *hw = &adapter->hw;
3822 bool link_active = false;
3825 /* get_link_status is set on LSC (link status) interrupt or
3826 * rx sequence error interrupt. get_link_status will stay
3827 * false until the e1000_check_for_link establishes link
3828 * for copper adapters ONLY
3830 switch (hw->phy.media_type) {
3831 case e1000_media_type_copper:
3832 if (hw->mac.get_link_status) {
3833 ret_val = hw->mac.ops.check_for_link(hw);
3834 link_active = !hw->mac.get_link_status;
3839 case e1000_media_type_internal_serdes:
3840 ret_val = hw->mac.ops.check_for_link(hw);
3841 link_active = hw->mac.serdes_has_link;
3844 case e1000_media_type_unknown:
3851 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3854 u32 ctrl_ext, thstat;
3856 /* check for thermal sensor event on i350 copper only */
3857 if (hw->mac.type == e1000_i350) {
3858 thstat = rd32(E1000_THSTAT);
3859 ctrl_ext = rd32(E1000_CTRL_EXT);
3861 if ((hw->phy.media_type == e1000_media_type_copper) &&
3862 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
3863 ret = !!(thstat & event);
3870 * igb_watchdog - Timer Call-back
3871 * @data: pointer to adapter cast into an unsigned long
3873 static void igb_watchdog(unsigned long data)
3875 struct igb_adapter *adapter = (struct igb_adapter *)data;
3876 /* Do the rest outside of interrupt context */
3877 schedule_work(&adapter->watchdog_task);
3880 static void igb_watchdog_task(struct work_struct *work)
3882 struct igb_adapter *adapter = container_of(work,
3885 struct e1000_hw *hw = &adapter->hw;
3886 struct net_device *netdev = adapter->netdev;
3890 link = igb_has_link(adapter);
3892 /* Cancel scheduled suspend requests. */
3893 pm_runtime_resume(netdev->dev.parent);
3895 if (!netif_carrier_ok(netdev)) {
3897 hw->mac.ops.get_speed_and_duplex(hw,
3898 &adapter->link_speed,
3899 &adapter->link_duplex);
3901 ctrl = rd32(E1000_CTRL);
3902 /* Links status message must follow this format */
3903 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3904 "Duplex, Flow Control: %s\n",
3906 adapter->link_speed,
3907 adapter->link_duplex == FULL_DUPLEX ?
3909 (ctrl & E1000_CTRL_TFCE) &&
3910 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3911 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3912 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
3914 /* check for thermal sensor event */
3915 if (igb_thermal_sensor_event(hw,
3916 E1000_THSTAT_LINK_THROTTLE)) {
3917 netdev_info(netdev, "The network adapter link "
3918 "speed was downshifted because it "
3922 /* adjust timeout factor according to speed/duplex */
3923 adapter->tx_timeout_factor = 1;
3924 switch (adapter->link_speed) {
3926 adapter->tx_timeout_factor = 14;
3929 /* maybe add some timeout factor ? */
3933 netif_carrier_on(netdev);
3935 igb_ping_all_vfs(adapter);
3936 igb_check_vf_rate_limit(adapter);
3938 /* link state has changed, schedule phy info update */
3939 if (!test_bit(__IGB_DOWN, &adapter->state))
3940 mod_timer(&adapter->phy_info_timer,
3941 round_jiffies(jiffies + 2 * HZ));
3944 if (netif_carrier_ok(netdev)) {
3945 adapter->link_speed = 0;
3946 adapter->link_duplex = 0;
3948 /* check for thermal sensor event */
3949 if (igb_thermal_sensor_event(hw,
3950 E1000_THSTAT_PWR_DOWN)) {
3951 netdev_err(netdev, "The network adapter was "
3952 "stopped because it overheated\n");
3955 /* Links status message must follow this format */
3956 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3958 netif_carrier_off(netdev);
3960 igb_ping_all_vfs(adapter);
3962 /* link state has changed, schedule phy info update */
3963 if (!test_bit(__IGB_DOWN, &adapter->state))
3964 mod_timer(&adapter->phy_info_timer,
3965 round_jiffies(jiffies + 2 * HZ));
3967 pm_schedule_suspend(netdev->dev.parent,
3972 spin_lock(&adapter->stats64_lock);
3973 igb_update_stats(adapter, &adapter->stats64);
3974 spin_unlock(&adapter->stats64_lock);
3976 for (i = 0; i < adapter->num_tx_queues; i++) {
3977 struct igb_ring *tx_ring = adapter->tx_ring[i];
3978 if (!netif_carrier_ok(netdev)) {
3979 /* We've lost link, so the controller stops DMA,
3980 * but we've got queued Tx work that's never going
3981 * to get done, so reset controller to flush Tx.
3982 * (Do the reset outside of interrupt context). */
3983 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3984 adapter->tx_timeout_count++;
3985 schedule_work(&adapter->reset_task);
3986 /* return immediately since reset is imminent */
3991 /* Force detection of hung controller every watchdog period */
3992 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3995 /* Cause software interrupt to ensure rx ring is cleaned */
3996 if (adapter->msix_entries) {
3998 for (i = 0; i < adapter->num_q_vectors; i++)
3999 eics |= adapter->q_vector[i]->eims_value;
4000 wr32(E1000_EICS, eics);
4002 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4005 igb_spoof_check(adapter);
4006 igb_ptp_rx_hang(adapter);
4008 /* Reset the timer */
4009 if (!test_bit(__IGB_DOWN, &adapter->state))
4010 mod_timer(&adapter->watchdog_timer,
4011 round_jiffies(jiffies + 2 * HZ));
4014 enum latency_range {
4018 latency_invalid = 255
4022 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4024 * Stores a new ITR value based on strictly on packet size. This
4025 * algorithm is less sophisticated than that used in igb_update_itr,
4026 * due to the difficulty of synchronizing statistics across multiple
4027 * receive rings. The divisors and thresholds used by this function
4028 * were determined based on theoretical maximum wire speed and testing
4029 * data, in order to minimize response time while increasing bulk
4031 * This functionality is controlled by the InterruptThrottleRate module
4032 * parameter (see igb_param.c)
4033 * NOTE: This function is called only when operating in a multiqueue
4034 * receive environment.
4035 * @q_vector: pointer to q_vector
4037 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4039 int new_val = q_vector->itr_val;
4040 int avg_wire_size = 0;
4041 struct igb_adapter *adapter = q_vector->adapter;
4042 unsigned int packets;
4044 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4045 * ints/sec - ITR timer value of 120 ticks.
4047 if (adapter->link_speed != SPEED_1000) {
4048 new_val = IGB_4K_ITR;
4052 packets = q_vector->rx.total_packets;
4054 avg_wire_size = q_vector->rx.total_bytes / packets;
4056 packets = q_vector->tx.total_packets;
4058 avg_wire_size = max_t(u32, avg_wire_size,
4059 q_vector->tx.total_bytes / packets);
4061 /* if avg_wire_size isn't set no work was done */
4065 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4066 avg_wire_size += 24;
4068 /* Don't starve jumbo frames */
4069 avg_wire_size = min(avg_wire_size, 3000);
4071 /* Give a little boost to mid-size frames */
4072 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4073 new_val = avg_wire_size / 3;
4075 new_val = avg_wire_size / 2;
4077 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4078 if (new_val < IGB_20K_ITR &&
4079 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4080 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4081 new_val = IGB_20K_ITR;
4084 if (new_val != q_vector->itr_val) {
4085 q_vector->itr_val = new_val;
4086 q_vector->set_itr = 1;
4089 q_vector->rx.total_bytes = 0;
4090 q_vector->rx.total_packets = 0;
4091 q_vector->tx.total_bytes = 0;
4092 q_vector->tx.total_packets = 0;
4096 * igb_update_itr - update the dynamic ITR value based on statistics
4097 * Stores a new ITR value based on packets and byte
4098 * counts during the last interrupt. The advantage of per interrupt
4099 * computation is faster updates and more accurate ITR for the current
4100 * traffic pattern. Constants in this function were computed
4101 * based on theoretical maximum wire speed and thresholds were set based
4102 * on testing data as well as attempting to minimize response time
4103 * while increasing bulk throughput.
4104 * this functionality is controlled by the InterruptThrottleRate module
4105 * parameter (see igb_param.c)
4106 * NOTE: These calculations are only valid when operating in a single-
4107 * queue environment.
4108 * @q_vector: pointer to q_vector
4109 * @ring_container: ring info to update the itr for
4111 static void igb_update_itr(struct igb_q_vector *q_vector,
4112 struct igb_ring_container *ring_container)
4114 unsigned int packets = ring_container->total_packets;
4115 unsigned int bytes = ring_container->total_bytes;
4116 u8 itrval = ring_container->itr;
4118 /* no packets, exit with status unchanged */
4123 case lowest_latency:
4124 /* handle TSO and jumbo frames */
4125 if (bytes/packets > 8000)
4126 itrval = bulk_latency;
4127 else if ((packets < 5) && (bytes > 512))
4128 itrval = low_latency;
4130 case low_latency: /* 50 usec aka 20000 ints/s */
4131 if (bytes > 10000) {
4132 /* this if handles the TSO accounting */
4133 if (bytes/packets > 8000) {
4134 itrval = bulk_latency;
4135 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
4136 itrval = bulk_latency;
4137 } else if ((packets > 35)) {
4138 itrval = lowest_latency;
4140 } else if (bytes/packets > 2000) {
4141 itrval = bulk_latency;
4142 } else if (packets <= 2 && bytes < 512) {
4143 itrval = lowest_latency;
4146 case bulk_latency: /* 250 usec aka 4000 ints/s */
4147 if (bytes > 25000) {
4149 itrval = low_latency;
4150 } else if (bytes < 1500) {
4151 itrval = low_latency;
4156 /* clear work counters since we have the values we need */
4157 ring_container->total_bytes = 0;
4158 ring_container->total_packets = 0;
4160 /* write updated itr to ring container */
4161 ring_container->itr = itrval;
4164 static void igb_set_itr(struct igb_q_vector *q_vector)
4166 struct igb_adapter *adapter = q_vector->adapter;
4167 u32 new_itr = q_vector->itr_val;
4170 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4171 if (adapter->link_speed != SPEED_1000) {
4173 new_itr = IGB_4K_ITR;
4177 igb_update_itr(q_vector, &q_vector->tx);
4178 igb_update_itr(q_vector, &q_vector->rx);
4180 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4182 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4183 if (current_itr == lowest_latency &&
4184 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4185 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4186 current_itr = low_latency;
4188 switch (current_itr) {
4189 /* counts and packets in update_itr are dependent on these numbers */
4190 case lowest_latency:
4191 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4194 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4197 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4204 if (new_itr != q_vector->itr_val) {
4205 /* this attempts to bias the interrupt rate towards Bulk
4206 * by adding intermediate steps when interrupt rate is
4208 new_itr = new_itr > q_vector->itr_val ?
4209 max((new_itr * q_vector->itr_val) /
4210 (new_itr + (q_vector->itr_val >> 2)),
4213 /* Don't write the value here; it resets the adapter's
4214 * internal timer, and causes us to delay far longer than
4215 * we should between interrupts. Instead, we write the ITR
4216 * value at the beginning of the next interrupt so the timing
4217 * ends up being correct.
4219 q_vector->itr_val = new_itr;
4220 q_vector->set_itr = 1;
4224 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4225 u32 type_tucmd, u32 mss_l4len_idx)
4227 struct e1000_adv_tx_context_desc *context_desc;
4228 u16 i = tx_ring->next_to_use;
4230 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4233 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4235 /* set bits to identify this as an advanced context descriptor */
4236 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4238 /* For 82575, context index must be unique per ring. */
4239 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4240 mss_l4len_idx |= tx_ring->reg_idx << 4;
4242 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4243 context_desc->seqnum_seed = 0;
4244 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4245 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4248 static int igb_tso(struct igb_ring *tx_ring,
4249 struct igb_tx_buffer *first,
4252 struct sk_buff *skb = first->skb;
4253 u32 vlan_macip_lens, type_tucmd;
4254 u32 mss_l4len_idx, l4len;
4256 if (skb->ip_summed != CHECKSUM_PARTIAL)
4259 if (!skb_is_gso(skb))
4262 if (skb_header_cloned(skb)) {
4263 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4268 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4269 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4271 if (first->protocol == __constant_htons(ETH_P_IP)) {
4272 struct iphdr *iph = ip_hdr(skb);
4275 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4279 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4280 first->tx_flags |= IGB_TX_FLAGS_TSO |
4283 } else if (skb_is_gso_v6(skb)) {
4284 ipv6_hdr(skb)->payload_len = 0;
4285 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4286 &ipv6_hdr(skb)->daddr,
4288 first->tx_flags |= IGB_TX_FLAGS_TSO |
4292 /* compute header lengths */
4293 l4len = tcp_hdrlen(skb);
4294 *hdr_len = skb_transport_offset(skb) + l4len;
4296 /* update gso size and bytecount with header size */
4297 first->gso_segs = skb_shinfo(skb)->gso_segs;
4298 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4301 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4302 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4304 /* VLAN MACLEN IPLEN */
4305 vlan_macip_lens = skb_network_header_len(skb);
4306 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4307 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4309 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4314 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4316 struct sk_buff *skb = first->skb;
4317 u32 vlan_macip_lens = 0;
4318 u32 mss_l4len_idx = 0;
4321 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4322 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4326 switch (first->protocol) {
4327 case __constant_htons(ETH_P_IP):
4328 vlan_macip_lens |= skb_network_header_len(skb);
4329 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4330 l4_hdr = ip_hdr(skb)->protocol;
4332 case __constant_htons(ETH_P_IPV6):
4333 vlan_macip_lens |= skb_network_header_len(skb);
4334 l4_hdr = ipv6_hdr(skb)->nexthdr;
4337 if (unlikely(net_ratelimit())) {
4338 dev_warn(tx_ring->dev,
4339 "partial checksum but proto=%x!\n",
4347 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4348 mss_l4len_idx = tcp_hdrlen(skb) <<
4349 E1000_ADVTXD_L4LEN_SHIFT;
4352 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4353 mss_l4len_idx = sizeof(struct sctphdr) <<
4354 E1000_ADVTXD_L4LEN_SHIFT;
4357 mss_l4len_idx = sizeof(struct udphdr) <<
4358 E1000_ADVTXD_L4LEN_SHIFT;
4361 if (unlikely(net_ratelimit())) {
4362 dev_warn(tx_ring->dev,
4363 "partial checksum but l4 proto=%x!\n",
4369 /* update TX checksum flag */
4370 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4373 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4374 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4376 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4379 #define IGB_SET_FLAG(_input, _flag, _result) \
4380 ((_flag <= _result) ? \
4381 ((u32)(_input & _flag) * (_result / _flag)) : \
4382 ((u32)(_input & _flag) / (_flag / _result)))
4384 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4386 /* set type for advanced descriptor with frame checksum insertion */
4387 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4388 E1000_ADVTXD_DCMD_DEXT |
4389 E1000_ADVTXD_DCMD_IFCS;
4391 /* set HW vlan bit if vlan is present */
4392 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4393 (E1000_ADVTXD_DCMD_VLE));
4395 /* set segmentation bits for TSO */
4396 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4397 (E1000_ADVTXD_DCMD_TSE));
4399 /* set timestamp bit if present */
4400 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4401 (E1000_ADVTXD_MAC_TSTAMP));
4403 /* insert frame checksum */
4404 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4409 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4410 union e1000_adv_tx_desc *tx_desc,
4411 u32 tx_flags, unsigned int paylen)
4413 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4415 /* 82575 requires a unique index per ring */
4416 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4417 olinfo_status |= tx_ring->reg_idx << 4;
4419 /* insert L4 checksum */
4420 olinfo_status |= IGB_SET_FLAG(tx_flags,
4422 (E1000_TXD_POPTS_TXSM << 8));
4424 /* insert IPv4 checksum */
4425 olinfo_status |= IGB_SET_FLAG(tx_flags,
4427 (E1000_TXD_POPTS_IXSM << 8));
4429 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4432 static void igb_tx_map(struct igb_ring *tx_ring,
4433 struct igb_tx_buffer *first,
4436 struct sk_buff *skb = first->skb;
4437 struct igb_tx_buffer *tx_buffer;
4438 union e1000_adv_tx_desc *tx_desc;
4439 struct skb_frag_struct *frag;
4441 unsigned int data_len, size;
4442 u32 tx_flags = first->tx_flags;
4443 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4444 u16 i = tx_ring->next_to_use;
4446 tx_desc = IGB_TX_DESC(tx_ring, i);
4448 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4450 size = skb_headlen(skb);
4451 data_len = skb->data_len;
4453 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4457 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4458 if (dma_mapping_error(tx_ring->dev, dma))
4461 /* record length, and DMA address */
4462 dma_unmap_len_set(tx_buffer, len, size);
4463 dma_unmap_addr_set(tx_buffer, dma, dma);
4465 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4467 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4468 tx_desc->read.cmd_type_len =
4469 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4473 if (i == tx_ring->count) {
4474 tx_desc = IGB_TX_DESC(tx_ring, 0);
4477 tx_desc->read.olinfo_status = 0;
4479 dma += IGB_MAX_DATA_PER_TXD;
4480 size -= IGB_MAX_DATA_PER_TXD;
4482 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4485 if (likely(!data_len))
4488 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4492 if (i == tx_ring->count) {
4493 tx_desc = IGB_TX_DESC(tx_ring, 0);
4496 tx_desc->read.olinfo_status = 0;
4498 size = skb_frag_size(frag);
4501 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4502 size, DMA_TO_DEVICE);
4504 tx_buffer = &tx_ring->tx_buffer_info[i];
4507 /* write last descriptor with RS and EOP bits */
4508 cmd_type |= size | IGB_TXD_DCMD;
4509 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4511 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4513 /* set the timestamp */
4514 first->time_stamp = jiffies;
4517 * Force memory writes to complete before letting h/w know there
4518 * are new descriptors to fetch. (Only applicable for weak-ordered
4519 * memory model archs, such as IA-64).
4521 * We also need this memory barrier to make certain all of the
4522 * status bits have been updated before next_to_watch is written.
4526 /* set next_to_watch value indicating a packet is present */
4527 first->next_to_watch = tx_desc;
4530 if (i == tx_ring->count)
4533 tx_ring->next_to_use = i;
4535 writel(i, tx_ring->tail);
4537 /* we need this if more than one processor can write to our tail
4538 * at a time, it syncronizes IO on IA64/Altix systems */
4544 dev_err(tx_ring->dev, "TX DMA map failed\n");
4546 /* clear dma mappings for failed tx_buffer_info map */
4548 tx_buffer = &tx_ring->tx_buffer_info[i];
4549 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4550 if (tx_buffer == first)
4557 tx_ring->next_to_use = i;
4560 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4562 struct net_device *netdev = tx_ring->netdev;
4564 netif_stop_subqueue(netdev, tx_ring->queue_index);
4566 /* Herbert's original patch had:
4567 * smp_mb__after_netif_stop_queue();
4568 * but since that doesn't exist yet, just open code it. */
4571 /* We need to check again in a case another CPU has just
4572 * made room available. */
4573 if (igb_desc_unused(tx_ring) < size)
4577 netif_wake_subqueue(netdev, tx_ring->queue_index);
4579 u64_stats_update_begin(&tx_ring->tx_syncp2);
4580 tx_ring->tx_stats.restart_queue2++;
4581 u64_stats_update_end(&tx_ring->tx_syncp2);
4586 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4588 if (igb_desc_unused(tx_ring) >= size)
4590 return __igb_maybe_stop_tx(tx_ring, size);
4593 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4594 struct igb_ring *tx_ring)
4596 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4597 struct igb_tx_buffer *first;
4600 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4601 __be16 protocol = vlan_get_protocol(skb);
4604 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4605 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4606 * + 2 desc gap to keep tail from touching head,
4607 * + 1 desc for context descriptor,
4608 * otherwise try next time
4610 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4612 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4613 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4615 count += skb_shinfo(skb)->nr_frags;
4618 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4619 /* this is a hard error */
4620 return NETDEV_TX_BUSY;
4623 /* record the location of the first descriptor for this packet */
4624 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4626 first->bytecount = skb->len;
4627 first->gso_segs = 1;
4629 skb_tx_timestamp(skb);
4631 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4632 !(adapter->ptp_tx_skb))) {
4633 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4634 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4636 adapter->ptp_tx_skb = skb_get(skb);
4637 adapter->ptp_tx_start = jiffies;
4638 if (adapter->hw.mac.type == e1000_82576)
4639 schedule_work(&adapter->ptp_tx_work);
4642 if (vlan_tx_tag_present(skb)) {
4643 tx_flags |= IGB_TX_FLAGS_VLAN;
4644 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4647 /* record initial flags and protocol */
4648 first->tx_flags = tx_flags;
4649 first->protocol = protocol;
4651 tso = igb_tso(tx_ring, first, &hdr_len);
4655 igb_tx_csum(tx_ring, first);
4657 igb_tx_map(tx_ring, first, hdr_len);
4659 /* Make sure there is space in the ring for the next send. */
4660 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4662 return NETDEV_TX_OK;
4665 igb_unmap_and_free_tx_resource(tx_ring, first);
4667 return NETDEV_TX_OK;
4670 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4671 struct sk_buff *skb)
4673 unsigned int r_idx = skb->queue_mapping;
4675 if (r_idx >= adapter->num_tx_queues)
4676 r_idx = r_idx % adapter->num_tx_queues;
4678 return adapter->tx_ring[r_idx];
4681 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4682 struct net_device *netdev)
4684 struct igb_adapter *adapter = netdev_priv(netdev);
4686 if (test_bit(__IGB_DOWN, &adapter->state)) {
4687 dev_kfree_skb_any(skb);
4688 return NETDEV_TX_OK;
4691 if (skb->len <= 0) {
4692 dev_kfree_skb_any(skb);
4693 return NETDEV_TX_OK;
4697 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4698 * in order to meet this minimum size requirement.
4700 if (unlikely(skb->len < 17)) {
4701 if (skb_pad(skb, 17 - skb->len))
4702 return NETDEV_TX_OK;
4704 skb_set_tail_pointer(skb, 17);
4707 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4711 * igb_tx_timeout - Respond to a Tx Hang
4712 * @netdev: network interface device structure
4714 static void igb_tx_timeout(struct net_device *netdev)
4716 struct igb_adapter *adapter = netdev_priv(netdev);
4717 struct e1000_hw *hw = &adapter->hw;
4719 /* Do the reset outside of interrupt context */
4720 adapter->tx_timeout_count++;
4722 if (hw->mac.type >= e1000_82580)
4723 hw->dev_spec._82575.global_device_reset = true;
4725 schedule_work(&adapter->reset_task);
4727 (adapter->eims_enable_mask & ~adapter->eims_other));
4730 static void igb_reset_task(struct work_struct *work)
4732 struct igb_adapter *adapter;
4733 adapter = container_of(work, struct igb_adapter, reset_task);
4736 netdev_err(adapter->netdev, "Reset adapter\n");
4737 igb_reinit_locked(adapter);
4741 * igb_get_stats64 - Get System Network Statistics
4742 * @netdev: network interface device structure
4743 * @stats: rtnl_link_stats64 pointer
4746 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4747 struct rtnl_link_stats64 *stats)
4749 struct igb_adapter *adapter = netdev_priv(netdev);
4751 spin_lock(&adapter->stats64_lock);
4752 igb_update_stats(adapter, &adapter->stats64);
4753 memcpy(stats, &adapter->stats64, sizeof(*stats));
4754 spin_unlock(&adapter->stats64_lock);
4760 * igb_change_mtu - Change the Maximum Transfer Unit
4761 * @netdev: network interface device structure
4762 * @new_mtu: new value for maximum frame size
4764 * Returns 0 on success, negative on failure
4766 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4768 struct igb_adapter *adapter = netdev_priv(netdev);
4769 struct pci_dev *pdev = adapter->pdev;
4770 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4772 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4773 dev_err(&pdev->dev, "Invalid MTU setting\n");
4777 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4778 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4779 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4783 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4786 /* igb_down has a dependency on max_frame_size */
4787 adapter->max_frame_size = max_frame;
4789 if (netif_running(netdev))
4792 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4793 netdev->mtu, new_mtu);
4794 netdev->mtu = new_mtu;
4796 if (netif_running(netdev))
4801 clear_bit(__IGB_RESETTING, &adapter->state);
4807 * igb_update_stats - Update the board statistics counters
4808 * @adapter: board private structure
4811 void igb_update_stats(struct igb_adapter *adapter,
4812 struct rtnl_link_stats64 *net_stats)
4814 struct e1000_hw *hw = &adapter->hw;
4815 struct pci_dev *pdev = adapter->pdev;
4821 u64 _bytes, _packets;
4823 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4826 * Prevent stats update while adapter is being reset, or if the pci
4827 * connection is down.
4829 if (adapter->link_speed == 0)
4831 if (pci_channel_offline(pdev))
4836 for (i = 0; i < adapter->num_rx_queues; i++) {
4837 u32 rqdpc = rd32(E1000_RQDPC(i));
4838 struct igb_ring *ring = adapter->rx_ring[i];
4841 ring->rx_stats.drops += rqdpc;
4842 net_stats->rx_fifo_errors += rqdpc;
4846 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4847 _bytes = ring->rx_stats.bytes;
4848 _packets = ring->rx_stats.packets;
4849 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4851 packets += _packets;
4854 net_stats->rx_bytes = bytes;
4855 net_stats->rx_packets = packets;
4859 for (i = 0; i < adapter->num_tx_queues; i++) {
4860 struct igb_ring *ring = adapter->tx_ring[i];
4862 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4863 _bytes = ring->tx_stats.bytes;
4864 _packets = ring->tx_stats.packets;
4865 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4867 packets += _packets;
4869 net_stats->tx_bytes = bytes;
4870 net_stats->tx_packets = packets;
4872 /* read stats registers */
4873 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4874 adapter->stats.gprc += rd32(E1000_GPRC);
4875 adapter->stats.gorc += rd32(E1000_GORCL);
4876 rd32(E1000_GORCH); /* clear GORCL */
4877 adapter->stats.bprc += rd32(E1000_BPRC);
4878 adapter->stats.mprc += rd32(E1000_MPRC);
4879 adapter->stats.roc += rd32(E1000_ROC);
4881 adapter->stats.prc64 += rd32(E1000_PRC64);
4882 adapter->stats.prc127 += rd32(E1000_PRC127);
4883 adapter->stats.prc255 += rd32(E1000_PRC255);
4884 adapter->stats.prc511 += rd32(E1000_PRC511);
4885 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4886 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4887 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4888 adapter->stats.sec += rd32(E1000_SEC);
4890 mpc = rd32(E1000_MPC);
4891 adapter->stats.mpc += mpc;
4892 net_stats->rx_fifo_errors += mpc;
4893 adapter->stats.scc += rd32(E1000_SCC);
4894 adapter->stats.ecol += rd32(E1000_ECOL);
4895 adapter->stats.mcc += rd32(E1000_MCC);
4896 adapter->stats.latecol += rd32(E1000_LATECOL);
4897 adapter->stats.dc += rd32(E1000_DC);
4898 adapter->stats.rlec += rd32(E1000_RLEC);
4899 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4900 adapter->stats.xontxc += rd32(E1000_XONTXC);
4901 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4902 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4903 adapter->stats.fcruc += rd32(E1000_FCRUC);
4904 adapter->stats.gptc += rd32(E1000_GPTC);
4905 adapter->stats.gotc += rd32(E1000_GOTCL);
4906 rd32(E1000_GOTCH); /* clear GOTCL */
4907 adapter->stats.rnbc += rd32(E1000_RNBC);
4908 adapter->stats.ruc += rd32(E1000_RUC);
4909 adapter->stats.rfc += rd32(E1000_RFC);
4910 adapter->stats.rjc += rd32(E1000_RJC);
4911 adapter->stats.tor += rd32(E1000_TORH);
4912 adapter->stats.tot += rd32(E1000_TOTH);
4913 adapter->stats.tpr += rd32(E1000_TPR);
4915 adapter->stats.ptc64 += rd32(E1000_PTC64);
4916 adapter->stats.ptc127 += rd32(E1000_PTC127);
4917 adapter->stats.ptc255 += rd32(E1000_PTC255);
4918 adapter->stats.ptc511 += rd32(E1000_PTC511);
4919 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4920 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4922 adapter->stats.mptc += rd32(E1000_MPTC);
4923 adapter->stats.bptc += rd32(E1000_BPTC);
4925 adapter->stats.tpt += rd32(E1000_TPT);
4926 adapter->stats.colc += rd32(E1000_COLC);
4928 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4929 /* read internal phy specific stats */
4930 reg = rd32(E1000_CTRL_EXT);
4931 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4932 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4934 /* this stat has invalid values on i210/i211 */
4935 if ((hw->mac.type != e1000_i210) &&
4936 (hw->mac.type != e1000_i211))
4937 adapter->stats.tncrs += rd32(E1000_TNCRS);
4940 adapter->stats.tsctc += rd32(E1000_TSCTC);
4941 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4943 adapter->stats.iac += rd32(E1000_IAC);
4944 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4945 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4946 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4947 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4948 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4949 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4950 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4951 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4953 /* Fill out the OS statistics structure */
4954 net_stats->multicast = adapter->stats.mprc;
4955 net_stats->collisions = adapter->stats.colc;
4959 /* RLEC on some newer hardware can be incorrect so build
4960 * our own version based on RUC and ROC */
4961 net_stats->rx_errors = adapter->stats.rxerrc +
4962 adapter->stats.crcerrs + adapter->stats.algnerrc +
4963 adapter->stats.ruc + adapter->stats.roc +
4964 adapter->stats.cexterr;
4965 net_stats->rx_length_errors = adapter->stats.ruc +
4967 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4968 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4969 net_stats->rx_missed_errors = adapter->stats.mpc;
4972 net_stats->tx_errors = adapter->stats.ecol +
4973 adapter->stats.latecol;
4974 net_stats->tx_aborted_errors = adapter->stats.ecol;
4975 net_stats->tx_window_errors = adapter->stats.latecol;
4976 net_stats->tx_carrier_errors = adapter->stats.tncrs;
4978 /* Tx Dropped needs to be maintained elsewhere */
4981 if (hw->phy.media_type == e1000_media_type_copper) {
4982 if ((adapter->link_speed == SPEED_1000) &&
4983 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4984 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4985 adapter->phy_stats.idle_errors += phy_tmp;
4989 /* Management Stats */
4990 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4991 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4992 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4995 reg = rd32(E1000_MANC);
4996 if (reg & E1000_MANC_EN_BMC2OS) {
4997 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4998 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4999 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5000 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5004 static irqreturn_t igb_msix_other(int irq, void *data)
5006 struct igb_adapter *adapter = data;
5007 struct e1000_hw *hw = &adapter->hw;
5008 u32 icr = rd32(E1000_ICR);
5009 /* reading ICR causes bit 31 of EICR to be cleared */
5011 if (icr & E1000_ICR_DRSTA)
5012 schedule_work(&adapter->reset_task);
5014 if (icr & E1000_ICR_DOUTSYNC) {
5015 /* HW is reporting DMA is out of sync */
5016 adapter->stats.doosync++;
5017 /* The DMA Out of Sync is also indication of a spoof event
5018 * in IOV mode. Check the Wrong VM Behavior register to
5019 * see if it is really a spoof event. */
5020 igb_check_wvbr(adapter);
5023 /* Check for a mailbox event */
5024 if (icr & E1000_ICR_VMMB)
5025 igb_msg_task(adapter);
5027 if (icr & E1000_ICR_LSC) {
5028 hw->mac.get_link_status = 1;
5029 /* guard against interrupt when we're going down */
5030 if (!test_bit(__IGB_DOWN, &adapter->state))
5031 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5034 if (icr & E1000_ICR_TS) {
5035 u32 tsicr = rd32(E1000_TSICR);
5037 if (tsicr & E1000_TSICR_TXTS) {
5038 /* acknowledge the interrupt */
5039 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5040 /* retrieve hardware timestamp */
5041 schedule_work(&adapter->ptp_tx_work);
5045 wr32(E1000_EIMS, adapter->eims_other);
5050 static void igb_write_itr(struct igb_q_vector *q_vector)
5052 struct igb_adapter *adapter = q_vector->adapter;
5053 u32 itr_val = q_vector->itr_val & 0x7FFC;
5055 if (!q_vector->set_itr)
5061 if (adapter->hw.mac.type == e1000_82575)
5062 itr_val |= itr_val << 16;
5064 itr_val |= E1000_EITR_CNT_IGNR;
5066 writel(itr_val, q_vector->itr_register);
5067 q_vector->set_itr = 0;
5070 static irqreturn_t igb_msix_ring(int irq, void *data)
5072 struct igb_q_vector *q_vector = data;
5074 /* Write the ITR value calculated from the previous interrupt. */
5075 igb_write_itr(q_vector);
5077 napi_schedule(&q_vector->napi);
5082 #ifdef CONFIG_IGB_DCA
5083 static void igb_update_tx_dca(struct igb_adapter *adapter,
5084 struct igb_ring *tx_ring,
5087 struct e1000_hw *hw = &adapter->hw;
5088 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5090 if (hw->mac.type != e1000_82575)
5091 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5094 * We can enable relaxed ordering for reads, but not writes when
5095 * DCA is enabled. This is due to a known issue in some chipsets
5096 * which will cause the DCA tag to be cleared.
5098 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5099 E1000_DCA_TXCTRL_DATA_RRO_EN |
5100 E1000_DCA_TXCTRL_DESC_DCA_EN;
5102 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5105 static void igb_update_rx_dca(struct igb_adapter *adapter,
5106 struct igb_ring *rx_ring,
5109 struct e1000_hw *hw = &adapter->hw;
5110 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5112 if (hw->mac.type != e1000_82575)
5113 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5116 * We can enable relaxed ordering for reads, but not writes when
5117 * DCA is enabled. This is due to a known issue in some chipsets
5118 * which will cause the DCA tag to be cleared.
5120 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5121 E1000_DCA_RXCTRL_DESC_DCA_EN;
5123 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5126 static void igb_update_dca(struct igb_q_vector *q_vector)
5128 struct igb_adapter *adapter = q_vector->adapter;
5129 int cpu = get_cpu();
5131 if (q_vector->cpu == cpu)
5134 if (q_vector->tx.ring)
5135 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5137 if (q_vector->rx.ring)
5138 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5140 q_vector->cpu = cpu;
5145 static void igb_setup_dca(struct igb_adapter *adapter)
5147 struct e1000_hw *hw = &adapter->hw;
5150 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5153 /* Always use CB2 mode, difference is masked in the CB driver. */
5154 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5156 for (i = 0; i < adapter->num_q_vectors; i++) {
5157 adapter->q_vector[i]->cpu = -1;
5158 igb_update_dca(adapter->q_vector[i]);
5162 static int __igb_notify_dca(struct device *dev, void *data)
5164 struct net_device *netdev = dev_get_drvdata(dev);
5165 struct igb_adapter *adapter = netdev_priv(netdev);
5166 struct pci_dev *pdev = adapter->pdev;
5167 struct e1000_hw *hw = &adapter->hw;
5168 unsigned long event = *(unsigned long *)data;
5171 case DCA_PROVIDER_ADD:
5172 /* if already enabled, don't do it again */
5173 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5175 if (dca_add_requester(dev) == 0) {
5176 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5177 dev_info(&pdev->dev, "DCA enabled\n");
5178 igb_setup_dca(adapter);
5181 /* Fall Through since DCA is disabled. */
5182 case DCA_PROVIDER_REMOVE:
5183 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5184 /* without this a class_device is left
5185 * hanging around in the sysfs model */
5186 dca_remove_requester(dev);
5187 dev_info(&pdev->dev, "DCA disabled\n");
5188 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5189 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5197 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5202 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5205 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5207 #endif /* CONFIG_IGB_DCA */
5209 #ifdef CONFIG_PCI_IOV
5210 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5212 unsigned char mac_addr[ETH_ALEN];
5214 eth_zero_addr(mac_addr);
5215 igb_set_vf_mac(adapter, vf, mac_addr);
5220 static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
5222 struct pci_dev *pdev = adapter->pdev;
5223 struct pci_dev *vfdev;
5226 switch (adapter->hw.mac.type) {
5228 dev_id = IGB_82576_VF_DEV_ID;
5231 dev_id = IGB_I350_VF_DEV_ID;
5237 /* loop through all the VFs to see if we own any that are assigned */
5238 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5240 /* if we don't own it we don't care */
5241 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5242 /* if it is assigned we cannot release it */
5243 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
5247 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
5254 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5256 struct e1000_hw *hw = &adapter->hw;
5260 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5261 ping = E1000_PF_CONTROL_MSG;
5262 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5263 ping |= E1000_VT_MSGTYPE_CTS;
5264 igb_write_mbx(hw, &ping, 1, i);
5268 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5270 struct e1000_hw *hw = &adapter->hw;
5271 u32 vmolr = rd32(E1000_VMOLR(vf));
5272 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5274 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5275 IGB_VF_FLAG_MULTI_PROMISC);
5276 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5278 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5279 vmolr |= E1000_VMOLR_MPME;
5280 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5281 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5284 * if we have hashes and we are clearing a multicast promisc
5285 * flag we need to write the hashes to the MTA as this step
5286 * was previously skipped
5288 if (vf_data->num_vf_mc_hashes > 30) {
5289 vmolr |= E1000_VMOLR_MPME;
5290 } else if (vf_data->num_vf_mc_hashes) {
5292 vmolr |= E1000_VMOLR_ROMPE;
5293 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5294 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5298 wr32(E1000_VMOLR(vf), vmolr);
5300 /* there are flags left unprocessed, likely not supported */
5301 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5308 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5309 u32 *msgbuf, u32 vf)
5311 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5312 u16 *hash_list = (u16 *)&msgbuf[1];
5313 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5316 /* salt away the number of multicast addresses assigned
5317 * to this VF for later use to restore when the PF multi cast
5320 vf_data->num_vf_mc_hashes = n;
5322 /* only up to 30 hash values supported */
5326 /* store the hashes for later use */
5327 for (i = 0; i < n; i++)
5328 vf_data->vf_mc_hashes[i] = hash_list[i];
5330 /* Flush and reset the mta with the new values */
5331 igb_set_rx_mode(adapter->netdev);
5336 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5338 struct e1000_hw *hw = &adapter->hw;
5339 struct vf_data_storage *vf_data;
5342 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5343 u32 vmolr = rd32(E1000_VMOLR(i));
5344 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5346 vf_data = &adapter->vf_data[i];
5348 if ((vf_data->num_vf_mc_hashes > 30) ||
5349 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5350 vmolr |= E1000_VMOLR_MPME;
5351 } else if (vf_data->num_vf_mc_hashes) {
5352 vmolr |= E1000_VMOLR_ROMPE;
5353 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5354 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5356 wr32(E1000_VMOLR(i), vmolr);
5360 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5362 struct e1000_hw *hw = &adapter->hw;
5363 u32 pool_mask, reg, vid;
5366 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5368 /* Find the vlan filter for this id */
5369 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5370 reg = rd32(E1000_VLVF(i));
5372 /* remove the vf from the pool */
5375 /* if pool is empty then remove entry from vfta */
5376 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5377 (reg & E1000_VLVF_VLANID_ENABLE)) {
5379 vid = reg & E1000_VLVF_VLANID_MASK;
5380 igb_vfta_set(hw, vid, false);
5383 wr32(E1000_VLVF(i), reg);
5386 adapter->vf_data[vf].vlans_enabled = 0;
5389 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5391 struct e1000_hw *hw = &adapter->hw;
5394 /* The vlvf table only exists on 82576 hardware and newer */
5395 if (hw->mac.type < e1000_82576)
5398 /* we only need to do this if VMDq is enabled */
5399 if (!adapter->vfs_allocated_count)
5402 /* Find the vlan filter for this id */
5403 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5404 reg = rd32(E1000_VLVF(i));
5405 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5406 vid == (reg & E1000_VLVF_VLANID_MASK))
5411 if (i == E1000_VLVF_ARRAY_SIZE) {
5412 /* Did not find a matching VLAN ID entry that was
5413 * enabled. Search for a free filter entry, i.e.
5414 * one without the enable bit set
5416 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5417 reg = rd32(E1000_VLVF(i));
5418 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5422 if (i < E1000_VLVF_ARRAY_SIZE) {
5423 /* Found an enabled/available entry */
5424 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5426 /* if !enabled we need to set this up in vfta */
5427 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5428 /* add VID to filter table */
5429 igb_vfta_set(hw, vid, true);
5430 reg |= E1000_VLVF_VLANID_ENABLE;
5432 reg &= ~E1000_VLVF_VLANID_MASK;
5434 wr32(E1000_VLVF(i), reg);
5436 /* do not modify RLPML for PF devices */
5437 if (vf >= adapter->vfs_allocated_count)
5440 if (!adapter->vf_data[vf].vlans_enabled) {
5442 reg = rd32(E1000_VMOLR(vf));
5443 size = reg & E1000_VMOLR_RLPML_MASK;
5445 reg &= ~E1000_VMOLR_RLPML_MASK;
5447 wr32(E1000_VMOLR(vf), reg);
5450 adapter->vf_data[vf].vlans_enabled++;
5453 if (i < E1000_VLVF_ARRAY_SIZE) {
5454 /* remove vf from the pool */
5455 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5456 /* if pool is empty then remove entry from vfta */
5457 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5459 igb_vfta_set(hw, vid, false);
5461 wr32(E1000_VLVF(i), reg);
5463 /* do not modify RLPML for PF devices */
5464 if (vf >= adapter->vfs_allocated_count)
5467 adapter->vf_data[vf].vlans_enabled--;
5468 if (!adapter->vf_data[vf].vlans_enabled) {
5470 reg = rd32(E1000_VMOLR(vf));
5471 size = reg & E1000_VMOLR_RLPML_MASK;
5473 reg &= ~E1000_VMOLR_RLPML_MASK;
5475 wr32(E1000_VMOLR(vf), reg);
5482 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5484 struct e1000_hw *hw = &adapter->hw;
5487 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5489 wr32(E1000_VMVIR(vf), 0);
5492 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5493 int vf, u16 vlan, u8 qos)
5496 struct igb_adapter *adapter = netdev_priv(netdev);
5498 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5501 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5504 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5505 igb_set_vmolr(adapter, vf, !vlan);
5506 adapter->vf_data[vf].pf_vlan = vlan;
5507 adapter->vf_data[vf].pf_qos = qos;
5508 dev_info(&adapter->pdev->dev,
5509 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5510 if (test_bit(__IGB_DOWN, &adapter->state)) {
5511 dev_warn(&adapter->pdev->dev,
5512 "The VF VLAN has been set,"
5513 " but the PF device is not up.\n");
5514 dev_warn(&adapter->pdev->dev,
5515 "Bring the PF device up before"
5516 " attempting to use the VF device.\n");
5519 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5521 igb_set_vmvir(adapter, vlan, vf);
5522 igb_set_vmolr(adapter, vf, true);
5523 adapter->vf_data[vf].pf_vlan = 0;
5524 adapter->vf_data[vf].pf_qos = 0;
5530 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5532 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5533 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5535 return igb_vlvf_set(adapter, vid, add, vf);
5538 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5540 /* clear flags - except flag that indicates PF has set the MAC */
5541 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5542 adapter->vf_data[vf].last_nack = jiffies;
5544 /* reset offloads to defaults */
5545 igb_set_vmolr(adapter, vf, true);
5547 /* reset vlans for device */
5548 igb_clear_vf_vfta(adapter, vf);
5549 if (adapter->vf_data[vf].pf_vlan)
5550 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5551 adapter->vf_data[vf].pf_vlan,
5552 adapter->vf_data[vf].pf_qos);
5554 igb_clear_vf_vfta(adapter, vf);
5556 /* reset multicast table array for vf */
5557 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5559 /* Flush and reset the mta with the new values */
5560 igb_set_rx_mode(adapter->netdev);
5563 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5565 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5567 /* clear mac address as we were hotplug removed/added */
5568 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5569 eth_zero_addr(vf_mac);
5571 /* process remaining reset events */
5572 igb_vf_reset(adapter, vf);
5575 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5577 struct e1000_hw *hw = &adapter->hw;
5578 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5579 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5581 u8 *addr = (u8 *)(&msgbuf[1]);
5583 /* process all the same items cleared in a function level reset */
5584 igb_vf_reset(adapter, vf);
5586 /* set vf mac address */
5587 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5589 /* enable transmit and receive for vf */
5590 reg = rd32(E1000_VFTE);
5591 wr32(E1000_VFTE, reg | (1 << vf));
5592 reg = rd32(E1000_VFRE);
5593 wr32(E1000_VFRE, reg | (1 << vf));
5595 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5597 /* reply to reset with ack and vf mac address */
5598 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5599 memcpy(addr, vf_mac, 6);
5600 igb_write_mbx(hw, msgbuf, 3, vf);
5603 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5606 * The VF MAC Address is stored in a packed array of bytes
5607 * starting at the second 32 bit word of the msg array
5609 unsigned char *addr = (char *)&msg[1];
5612 if (is_valid_ether_addr(addr))
5613 err = igb_set_vf_mac(adapter, vf, addr);
5618 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5620 struct e1000_hw *hw = &adapter->hw;
5621 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5622 u32 msg = E1000_VT_MSGTYPE_NACK;
5624 /* if device isn't clear to send it shouldn't be reading either */
5625 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5626 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5627 igb_write_mbx(hw, &msg, 1, vf);
5628 vf_data->last_nack = jiffies;
5632 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5634 struct pci_dev *pdev = adapter->pdev;
5635 u32 msgbuf[E1000_VFMAILBOX_SIZE];
5636 struct e1000_hw *hw = &adapter->hw;
5637 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5640 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5643 /* if receive failed revoke VF CTS stats and restart init */
5644 dev_err(&pdev->dev, "Error receiving message from VF\n");
5645 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5646 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5651 /* this is a message we already processed, do nothing */
5652 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5656 * until the vf completes a reset it should not be
5657 * allowed to start any configuration.
5660 if (msgbuf[0] == E1000_VF_RESET) {
5661 igb_vf_reset_msg(adapter, vf);
5665 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5666 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5672 switch ((msgbuf[0] & 0xFFFF)) {
5673 case E1000_VF_SET_MAC_ADDR:
5675 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5676 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5678 dev_warn(&pdev->dev,
5679 "VF %d attempted to override administratively "
5680 "set MAC address\nReload the VF driver to "
5681 "resume operations\n", vf);
5683 case E1000_VF_SET_PROMISC:
5684 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5686 case E1000_VF_SET_MULTICAST:
5687 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5689 case E1000_VF_SET_LPE:
5690 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5692 case E1000_VF_SET_VLAN:
5694 if (vf_data->pf_vlan)
5695 dev_warn(&pdev->dev,
5696 "VF %d attempted to override administratively "
5697 "set VLAN tag\nReload the VF driver to "
5698 "resume operations\n", vf);
5700 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5703 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5708 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5710 /* notify the VF of the results of what it sent us */
5712 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5714 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5716 igb_write_mbx(hw, msgbuf, 1, vf);
5719 static void igb_msg_task(struct igb_adapter *adapter)
5721 struct e1000_hw *hw = &adapter->hw;
5724 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5725 /* process any reset requests */
5726 if (!igb_check_for_rst(hw, vf))
5727 igb_vf_reset_event(adapter, vf);
5729 /* process any messages pending */
5730 if (!igb_check_for_msg(hw, vf))
5731 igb_rcv_msg_from_vf(adapter, vf);
5733 /* process any acks */
5734 if (!igb_check_for_ack(hw, vf))
5735 igb_rcv_ack_from_vf(adapter, vf);
5740 * igb_set_uta - Set unicast filter table address
5741 * @adapter: board private structure
5743 * The unicast table address is a register array of 32-bit registers.
5744 * The table is meant to be used in a way similar to how the MTA is used
5745 * however due to certain limitations in the hardware it is necessary to
5746 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5747 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
5749 static void igb_set_uta(struct igb_adapter *adapter)
5751 struct e1000_hw *hw = &adapter->hw;
5754 /* The UTA table only exists on 82576 hardware and newer */
5755 if (hw->mac.type < e1000_82576)
5758 /* we only need to do this if VMDq is enabled */
5759 if (!adapter->vfs_allocated_count)
5762 for (i = 0; i < hw->mac.uta_reg_count; i++)
5763 array_wr32(E1000_UTA, i, ~0);
5767 * igb_intr_msi - Interrupt Handler
5768 * @irq: interrupt number
5769 * @data: pointer to a network interface device structure
5771 static irqreturn_t igb_intr_msi(int irq, void *data)
5773 struct igb_adapter *adapter = data;
5774 struct igb_q_vector *q_vector = adapter->q_vector[0];
5775 struct e1000_hw *hw = &adapter->hw;
5776 /* read ICR disables interrupts using IAM */
5777 u32 icr = rd32(E1000_ICR);
5779 igb_write_itr(q_vector);
5781 if (icr & E1000_ICR_DRSTA)
5782 schedule_work(&adapter->reset_task);
5784 if (icr & E1000_ICR_DOUTSYNC) {
5785 /* HW is reporting DMA is out of sync */
5786 adapter->stats.doosync++;
5789 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5790 hw->mac.get_link_status = 1;
5791 if (!test_bit(__IGB_DOWN, &adapter->state))
5792 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5795 if (icr & E1000_ICR_TS) {
5796 u32 tsicr = rd32(E1000_TSICR);
5798 if (tsicr & E1000_TSICR_TXTS) {
5799 /* acknowledge the interrupt */
5800 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5801 /* retrieve hardware timestamp */
5802 schedule_work(&adapter->ptp_tx_work);
5806 napi_schedule(&q_vector->napi);
5812 * igb_intr - Legacy Interrupt Handler
5813 * @irq: interrupt number
5814 * @data: pointer to a network interface device structure
5816 static irqreturn_t igb_intr(int irq, void *data)
5818 struct igb_adapter *adapter = data;
5819 struct igb_q_vector *q_vector = adapter->q_vector[0];
5820 struct e1000_hw *hw = &adapter->hw;
5821 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5822 * need for the IMC write */
5823 u32 icr = rd32(E1000_ICR);
5825 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5826 * not set, then the adapter didn't send an interrupt */
5827 if (!(icr & E1000_ICR_INT_ASSERTED))
5830 igb_write_itr(q_vector);
5832 if (icr & E1000_ICR_DRSTA)
5833 schedule_work(&adapter->reset_task);
5835 if (icr & E1000_ICR_DOUTSYNC) {
5836 /* HW is reporting DMA is out of sync */
5837 adapter->stats.doosync++;
5840 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5841 hw->mac.get_link_status = 1;
5842 /* guard against interrupt when we're going down */
5843 if (!test_bit(__IGB_DOWN, &adapter->state))
5844 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5847 if (icr & E1000_ICR_TS) {
5848 u32 tsicr = rd32(E1000_TSICR);
5850 if (tsicr & E1000_TSICR_TXTS) {
5851 /* acknowledge the interrupt */
5852 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5853 /* retrieve hardware timestamp */
5854 schedule_work(&adapter->ptp_tx_work);
5858 napi_schedule(&q_vector->napi);
5863 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5865 struct igb_adapter *adapter = q_vector->adapter;
5866 struct e1000_hw *hw = &adapter->hw;
5868 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5869 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5870 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5871 igb_set_itr(q_vector);
5873 igb_update_ring_itr(q_vector);
5876 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5877 if (adapter->msix_entries)
5878 wr32(E1000_EIMS, q_vector->eims_value);
5880 igb_irq_enable(adapter);
5885 * igb_poll - NAPI Rx polling callback
5886 * @napi: napi polling structure
5887 * @budget: count of how many packets we should handle
5889 static int igb_poll(struct napi_struct *napi, int budget)
5891 struct igb_q_vector *q_vector = container_of(napi,
5892 struct igb_q_vector,
5894 bool clean_complete = true;
5896 #ifdef CONFIG_IGB_DCA
5897 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5898 igb_update_dca(q_vector);
5900 if (q_vector->tx.ring)
5901 clean_complete = igb_clean_tx_irq(q_vector);
5903 if (q_vector->rx.ring)
5904 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5906 /* If all work not completed, return budget and keep polling */
5907 if (!clean_complete)
5910 /* If not enough Rx work done, exit the polling mode */
5911 napi_complete(napi);
5912 igb_ring_irq_enable(q_vector);
5918 * igb_clean_tx_irq - Reclaim resources after transmit completes
5919 * @q_vector: pointer to q_vector containing needed info
5921 * returns true if ring is completely cleaned
5923 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5925 struct igb_adapter *adapter = q_vector->adapter;
5926 struct igb_ring *tx_ring = q_vector->tx.ring;
5927 struct igb_tx_buffer *tx_buffer;
5928 union e1000_adv_tx_desc *tx_desc;
5929 unsigned int total_bytes = 0, total_packets = 0;
5930 unsigned int budget = q_vector->tx.work_limit;
5931 unsigned int i = tx_ring->next_to_clean;
5933 if (test_bit(__IGB_DOWN, &adapter->state))
5936 tx_buffer = &tx_ring->tx_buffer_info[i];
5937 tx_desc = IGB_TX_DESC(tx_ring, i);
5938 i -= tx_ring->count;
5941 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
5943 /* if next_to_watch is not set then there is no work pending */
5947 /* prevent any other reads prior to eop_desc */
5948 read_barrier_depends();
5950 /* if DD is not set pending work has not been completed */
5951 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5954 /* clear next_to_watch to prevent false hangs */
5955 tx_buffer->next_to_watch = NULL;
5957 /* update the statistics for this packet */
5958 total_bytes += tx_buffer->bytecount;
5959 total_packets += tx_buffer->gso_segs;
5962 dev_kfree_skb_any(tx_buffer->skb);
5964 /* unmap skb header data */
5965 dma_unmap_single(tx_ring->dev,
5966 dma_unmap_addr(tx_buffer, dma),
5967 dma_unmap_len(tx_buffer, len),
5970 /* clear tx_buffer data */
5971 tx_buffer->skb = NULL;
5972 dma_unmap_len_set(tx_buffer, len, 0);
5974 /* clear last DMA location and unmap remaining buffers */
5975 while (tx_desc != eop_desc) {
5980 i -= tx_ring->count;
5981 tx_buffer = tx_ring->tx_buffer_info;
5982 tx_desc = IGB_TX_DESC(tx_ring, 0);
5985 /* unmap any remaining paged data */
5986 if (dma_unmap_len(tx_buffer, len)) {
5987 dma_unmap_page(tx_ring->dev,
5988 dma_unmap_addr(tx_buffer, dma),
5989 dma_unmap_len(tx_buffer, len),
5991 dma_unmap_len_set(tx_buffer, len, 0);
5995 /* move us one more past the eop_desc for start of next pkt */
6000 i -= tx_ring->count;
6001 tx_buffer = tx_ring->tx_buffer_info;
6002 tx_desc = IGB_TX_DESC(tx_ring, 0);
6005 /* issue prefetch for next Tx descriptor */
6008 /* update budget accounting */
6010 } while (likely(budget));
6012 netdev_tx_completed_queue(txring_txq(tx_ring),
6013 total_packets, total_bytes);
6014 i += tx_ring->count;
6015 tx_ring->next_to_clean = i;
6016 u64_stats_update_begin(&tx_ring->tx_syncp);
6017 tx_ring->tx_stats.bytes += total_bytes;
6018 tx_ring->tx_stats.packets += total_packets;
6019 u64_stats_update_end(&tx_ring->tx_syncp);
6020 q_vector->tx.total_bytes += total_bytes;
6021 q_vector->tx.total_packets += total_packets;
6023 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6024 struct e1000_hw *hw = &adapter->hw;
6026 /* Detect a transmit hang in hardware, this serializes the
6027 * check with the clearing of time_stamp and movement of i */
6028 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6029 if (tx_buffer->next_to_watch &&
6030 time_after(jiffies, tx_buffer->time_stamp +
6031 (adapter->tx_timeout_factor * HZ)) &&
6032 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6034 /* detected Tx unit hang */
6035 dev_err(tx_ring->dev,
6036 "Detected Tx Unit Hang\n"
6040 " next_to_use <%x>\n"
6041 " next_to_clean <%x>\n"
6042 "buffer_info[next_to_clean]\n"
6043 " time_stamp <%lx>\n"
6044 " next_to_watch <%p>\n"
6046 " desc.status <%x>\n",
6047 tx_ring->queue_index,
6048 rd32(E1000_TDH(tx_ring->reg_idx)),
6049 readl(tx_ring->tail),
6050 tx_ring->next_to_use,
6051 tx_ring->next_to_clean,
6052 tx_buffer->time_stamp,
6053 tx_buffer->next_to_watch,
6055 tx_buffer->next_to_watch->wb.status);
6056 netif_stop_subqueue(tx_ring->netdev,
6057 tx_ring->queue_index);
6059 /* we are about to reset, no point in enabling stuff */
6064 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6065 if (unlikely(total_packets &&
6066 netif_carrier_ok(tx_ring->netdev) &&
6067 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6068 /* Make sure that anybody stopping the queue after this
6069 * sees the new next_to_clean.
6072 if (__netif_subqueue_stopped(tx_ring->netdev,
6073 tx_ring->queue_index) &&
6074 !(test_bit(__IGB_DOWN, &adapter->state))) {
6075 netif_wake_subqueue(tx_ring->netdev,
6076 tx_ring->queue_index);
6078 u64_stats_update_begin(&tx_ring->tx_syncp);
6079 tx_ring->tx_stats.restart_queue++;
6080 u64_stats_update_end(&tx_ring->tx_syncp);
6088 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6089 * @rx_ring: rx descriptor ring to store buffers on
6090 * @old_buff: donor buffer to have page reused
6092 * Synchronizes page for reuse by the adapter
6094 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6095 struct igb_rx_buffer *old_buff)
6097 struct igb_rx_buffer *new_buff;
6098 u16 nta = rx_ring->next_to_alloc;
6100 new_buff = &rx_ring->rx_buffer_info[nta];
6102 /* update, and store next to alloc */
6104 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6106 /* transfer page from old buffer to new buffer */
6107 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6109 /* sync the buffer for use by the device */
6110 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6111 old_buff->page_offset,
6116 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6118 unsigned int truesize)
6120 /* avoid re-using remote pages */
6121 if (unlikely(page_to_nid(page) != numa_node_id()))
6124 #if (PAGE_SIZE < 8192)
6125 /* if we are only owner of page we can reuse it */
6126 if (unlikely(page_count(page) != 1))
6129 /* flip page offset to other buffer */
6130 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6132 /* since we are the only owner of the page and we need to
6133 * increment it, just set the value to 2 in order to avoid
6134 * an unnecessary locked operation
6136 atomic_set(&page->_count, 2);
6138 /* move offset up to the next cache line */
6139 rx_buffer->page_offset += truesize;
6141 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6144 /* bump ref count on page before it is given to the stack */
6152 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6153 * @rx_ring: rx descriptor ring to transact packets on
6154 * @rx_buffer: buffer containing page to add
6155 * @rx_desc: descriptor containing length of buffer written by hardware
6156 * @skb: sk_buff to place the data into
6158 * This function will add the data contained in rx_buffer->page to the skb.
6159 * This is done either through a direct copy if the data in the buffer is
6160 * less than the skb header size, otherwise it will just attach the page as
6161 * a frag to the skb.
6163 * The function will then update the page offset if necessary and return
6164 * true if the buffer can be reused by the adapter.
6166 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6167 struct igb_rx_buffer *rx_buffer,
6168 union e1000_adv_rx_desc *rx_desc,
6169 struct sk_buff *skb)
6171 struct page *page = rx_buffer->page;
6172 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6173 #if (PAGE_SIZE < 8192)
6174 unsigned int truesize = IGB_RX_BUFSZ;
6176 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6179 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6180 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6182 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6183 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6184 va += IGB_TS_HDR_LEN;
6185 size -= IGB_TS_HDR_LEN;
6188 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6190 /* we can reuse buffer as-is, just make sure it is local */
6191 if (likely(page_to_nid(page) == numa_node_id()))
6194 /* this page cannot be reused so discard it */
6199 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6200 rx_buffer->page_offset, size, truesize);
6202 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6205 static struct sk_buff *igb_build_rx_buffer(struct igb_ring *rx_ring,
6206 union e1000_adv_rx_desc *rx_desc)
6208 struct igb_rx_buffer *rx_buffer;
6209 struct sk_buff *skb;
6212 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6213 #if (PAGE_SIZE < 8192)
6214 unsigned int truesize = IGB_RX_BUFSZ;
6216 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
6217 SKB_DATA_ALIGN(NET_SKB_PAD +
6222 /* If we spanned a buffer we have a huge mess so test for it */
6223 BUG_ON(unlikely(!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)));
6225 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6226 page = rx_buffer->page;
6229 page_addr = page_address(page) + rx_buffer->page_offset;
6231 /* prefetch first cache line of first page */
6232 prefetch(page_addr + NET_SKB_PAD + NET_IP_ALIGN);
6233 #if L1_CACHE_BYTES < 128
6234 prefetch(page_addr + L1_CACHE_BYTES + NET_SKB_PAD + NET_IP_ALIGN);
6237 /* build an skb to around the page buffer */
6238 skb = build_skb(page_addr, truesize);
6239 if (unlikely(!skb)) {
6240 rx_ring->rx_stats.alloc_failed++;
6244 /* we are reusing so sync this buffer for CPU use */
6245 dma_sync_single_range_for_cpu(rx_ring->dev,
6247 rx_buffer->page_offset,
6251 /* update pointers within the skb to store the data */
6252 skb_reserve(skb, NET_IP_ALIGN + NET_SKB_PAD);
6253 __skb_put(skb, size);
6255 /* pull timestamp out of packet data */
6256 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6257 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb);
6258 __skb_pull(skb, IGB_TS_HDR_LEN);
6261 if (igb_can_reuse_rx_page(rx_buffer, page, truesize)) {
6262 /* hand second half of page back to the ring */
6263 igb_reuse_rx_page(rx_ring, rx_buffer);
6265 /* we are not reusing the buffer so unmap it */
6266 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6267 PAGE_SIZE, DMA_FROM_DEVICE);
6270 /* clear contents of buffer_info */
6272 rx_buffer->page = NULL;
6277 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6278 union e1000_adv_rx_desc *rx_desc,
6279 struct sk_buff *skb)
6281 struct igb_rx_buffer *rx_buffer;
6284 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6286 page = rx_buffer->page;
6290 void *page_addr = page_address(page) +
6291 rx_buffer->page_offset;
6293 /* prefetch first cache line of first page */
6294 prefetch(page_addr);
6295 #if L1_CACHE_BYTES < 128
6296 prefetch(page_addr + L1_CACHE_BYTES);
6299 /* allocate a skb to store the frags */
6300 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6302 if (unlikely(!skb)) {
6303 rx_ring->rx_stats.alloc_failed++;
6308 * we will be copying header into skb->data in
6309 * pskb_may_pull so it is in our interest to prefetch
6310 * it now to avoid a possible cache miss
6312 prefetchw(skb->data);
6315 /* we are reusing so sync this buffer for CPU use */
6316 dma_sync_single_range_for_cpu(rx_ring->dev,
6318 rx_buffer->page_offset,
6322 /* pull page into skb */
6323 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6324 /* hand second half of page back to the ring */
6325 igb_reuse_rx_page(rx_ring, rx_buffer);
6327 /* we are not reusing the buffer so unmap it */
6328 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6329 PAGE_SIZE, DMA_FROM_DEVICE);
6332 /* clear contents of rx_buffer */
6333 rx_buffer->page = NULL;
6338 static inline void igb_rx_checksum(struct igb_ring *ring,
6339 union e1000_adv_rx_desc *rx_desc,
6340 struct sk_buff *skb)
6342 skb_checksum_none_assert(skb);
6344 /* Ignore Checksum bit is set */
6345 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6348 /* Rx checksum disabled via ethtool */
6349 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6352 /* TCP/UDP checksum error bit is set */
6353 if (igb_test_staterr(rx_desc,
6354 E1000_RXDEXT_STATERR_TCPE |
6355 E1000_RXDEXT_STATERR_IPE)) {
6357 * work around errata with sctp packets where the TCPE aka
6358 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6359 * packets, (aka let the stack check the crc32c)
6361 if (!((skb->len == 60) &&
6362 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6363 u64_stats_update_begin(&ring->rx_syncp);
6364 ring->rx_stats.csum_err++;
6365 u64_stats_update_end(&ring->rx_syncp);
6367 /* let the stack verify checksum errors */
6370 /* It must be a TCP or UDP packet with a valid checksum */
6371 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6372 E1000_RXD_STAT_UDPCS))
6373 skb->ip_summed = CHECKSUM_UNNECESSARY;
6375 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6376 le32_to_cpu(rx_desc->wb.upper.status_error));
6379 static inline void igb_rx_hash(struct igb_ring *ring,
6380 union e1000_adv_rx_desc *rx_desc,
6381 struct sk_buff *skb)
6383 if (ring->netdev->features & NETIF_F_RXHASH)
6384 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6388 * igb_is_non_eop - process handling of non-EOP buffers
6389 * @rx_ring: Rx ring being processed
6390 * @rx_desc: Rx descriptor for current buffer
6391 * @skb: current socket buffer containing buffer in progress
6393 * This function updates next to clean. If the buffer is an EOP buffer
6394 * this function exits returning false, otherwise it will place the
6395 * sk_buff in the next buffer to be chained and return true indicating
6396 * that this is in fact a non-EOP buffer.
6398 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6399 union e1000_adv_rx_desc *rx_desc)
6401 u32 ntc = rx_ring->next_to_clean + 1;
6403 /* fetch, update, and store next to clean */
6404 ntc = (ntc < rx_ring->count) ? ntc : 0;
6405 rx_ring->next_to_clean = ntc;
6407 prefetch(IGB_RX_DESC(rx_ring, ntc));
6409 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6416 * igb_get_headlen - determine size of header for LRO/GRO
6417 * @data: pointer to the start of the headers
6418 * @max_len: total length of section to find headers in
6420 * This function is meant to determine the length of headers that will
6421 * be recognized by hardware for LRO, and GRO offloads. The main
6422 * motivation of doing this is to only perform one pull for IPv4 TCP
6423 * packets so that we can do basic things like calculating the gso_size
6424 * based on the average data per packet.
6426 static unsigned int igb_get_headlen(unsigned char *data,
6427 unsigned int max_len)
6430 unsigned char *network;
6433 struct vlan_hdr *vlan;
6436 struct ipv6hdr *ipv6;
6439 u8 nexthdr = 0; /* default to not TCP */
6442 /* this should never happen, but better safe than sorry */
6443 if (max_len < ETH_HLEN)
6446 /* initialize network frame pointer */
6449 /* set first protocol and move network header forward */
6450 protocol = hdr.eth->h_proto;
6451 hdr.network += ETH_HLEN;
6453 /* handle any vlan tag if present */
6454 if (protocol == __constant_htons(ETH_P_8021Q)) {
6455 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6458 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6459 hdr.network += VLAN_HLEN;
6462 /* handle L3 protocols */
6463 if (protocol == __constant_htons(ETH_P_IP)) {
6464 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6467 /* access ihl as a u8 to avoid unaligned access on ia64 */
6468 hlen = (hdr.network[0] & 0x0F) << 2;
6470 /* verify hlen meets minimum size requirements */
6471 if (hlen < sizeof(struct iphdr))
6472 return hdr.network - data;
6474 /* record next protocol if header is present */
6475 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
6476 nexthdr = hdr.ipv4->protocol;
6477 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6478 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6481 /* record next protocol */
6482 nexthdr = hdr.ipv6->nexthdr;
6483 hlen = sizeof(struct ipv6hdr);
6485 return hdr.network - data;
6488 /* relocate pointer to start of L4 header */
6489 hdr.network += hlen;
6491 /* finally sort out TCP */
6492 if (nexthdr == IPPROTO_TCP) {
6493 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6496 /* access doff as a u8 to avoid unaligned access on ia64 */
6497 hlen = (hdr.network[12] & 0xF0) >> 2;
6499 /* verify hlen meets minimum size requirements */
6500 if (hlen < sizeof(struct tcphdr))
6501 return hdr.network - data;
6503 hdr.network += hlen;
6504 } else if (nexthdr == IPPROTO_UDP) {
6505 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6508 hdr.network += sizeof(struct udphdr);
6512 * If everything has gone correctly hdr.network should be the
6513 * data section of the packet and will be the end of the header.
6514 * If not then it probably represents the end of the last recognized
6517 if ((hdr.network - data) < max_len)
6518 return hdr.network - data;
6524 * igb_pull_tail - igb specific version of skb_pull_tail
6525 * @rx_ring: rx descriptor ring packet is being transacted on
6526 * @rx_desc: pointer to the EOP Rx descriptor
6527 * @skb: pointer to current skb being adjusted
6529 * This function is an igb specific version of __pskb_pull_tail. The
6530 * main difference between this version and the original function is that
6531 * this function can make several assumptions about the state of things
6532 * that allow for significant optimizations versus the standard function.
6533 * As a result we can do things like drop a frag and maintain an accurate
6534 * truesize for the skb.
6536 static void igb_pull_tail(struct igb_ring *rx_ring,
6537 union e1000_adv_rx_desc *rx_desc,
6538 struct sk_buff *skb)
6540 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6542 unsigned int pull_len;
6545 * it is valid to use page_address instead of kmap since we are
6546 * working with pages allocated out of the lomem pool per
6547 * alloc_page(GFP_ATOMIC)
6549 va = skb_frag_address(frag);
6551 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6552 /* retrieve timestamp from buffer */
6553 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6555 /* update pointers to remove timestamp header */
6556 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6557 frag->page_offset += IGB_TS_HDR_LEN;
6558 skb->data_len -= IGB_TS_HDR_LEN;
6559 skb->len -= IGB_TS_HDR_LEN;
6561 /* move va to start of packet data */
6562 va += IGB_TS_HDR_LEN;
6566 * we need the header to contain the greater of either ETH_HLEN or
6567 * 60 bytes if the skb->len is less than 60 for skb_pad.
6569 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6571 /* align pull length to size of long to optimize memcpy performance */
6572 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6574 /* update all of the pointers */
6575 skb_frag_size_sub(frag, pull_len);
6576 frag->page_offset += pull_len;
6577 skb->data_len -= pull_len;
6578 skb->tail += pull_len;
6582 * igb_cleanup_headers - Correct corrupted or empty headers
6583 * @rx_ring: rx descriptor ring packet is being transacted on
6584 * @rx_desc: pointer to the EOP Rx descriptor
6585 * @skb: pointer to current skb being fixed
6587 * Address the case where we are pulling data in on pages only
6588 * and as such no data is present in the skb header.
6590 * In addition if skb is not at least 60 bytes we need to pad it so that
6591 * it is large enough to qualify as a valid Ethernet frame.
6593 * Returns true if an error was encountered and skb was freed.
6595 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6596 union e1000_adv_rx_desc *rx_desc,
6597 struct sk_buff *skb)
6600 if (unlikely((igb_test_staterr(rx_desc,
6601 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6602 struct net_device *netdev = rx_ring->netdev;
6603 if (!(netdev->features & NETIF_F_RXALL)) {
6604 dev_kfree_skb_any(skb);
6609 /* place header in linear portion of buffer */
6610 if (skb_is_nonlinear(skb))
6611 igb_pull_tail(rx_ring, rx_desc, skb);
6613 /* if skb_pad returns an error the skb was freed */
6614 if (unlikely(skb->len < 60)) {
6615 int pad_len = 60 - skb->len;
6617 if (skb_pad(skb, pad_len))
6619 __skb_put(skb, pad_len);
6626 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6627 * @rx_ring: rx descriptor ring packet is being transacted on
6628 * @rx_desc: pointer to the EOP Rx descriptor
6629 * @skb: pointer to current skb being populated
6631 * This function checks the ring, descriptor, and packet information in
6632 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6633 * other fields within the skb.
6635 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6636 union e1000_adv_rx_desc *rx_desc,
6637 struct sk_buff *skb)
6639 struct net_device *dev = rx_ring->netdev;
6641 igb_rx_hash(rx_ring, rx_desc, skb);
6643 igb_rx_checksum(rx_ring, rx_desc, skb);
6645 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
6647 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6648 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6650 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6651 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6652 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6654 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6656 __vlan_hwaccel_put_tag(skb, vid);
6659 skb_record_rx_queue(skb, rx_ring->queue_index);
6661 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6664 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6666 struct igb_ring *rx_ring = q_vector->rx.ring;
6667 struct sk_buff *skb = rx_ring->skb;
6668 unsigned int total_bytes = 0, total_packets = 0;
6669 u16 cleaned_count = igb_desc_unused(rx_ring);
6672 union e1000_adv_rx_desc *rx_desc;
6674 /* return some buffers to hardware, one at a time is too slow */
6675 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6676 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6680 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6682 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6685 /* This memory barrier is needed to keep us from reading
6686 * any other fields out of the rx_desc until we know the
6687 * RXD_STAT_DD bit is set
6691 /* retrieve a buffer from the ring */
6692 if (ring_uses_build_skb(rx_ring))
6693 skb = igb_build_rx_buffer(rx_ring, rx_desc);
6695 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6697 /* exit if we failed to retrieve a buffer */
6703 /* fetch next buffer in frame if non-eop */
6704 if (igb_is_non_eop(rx_ring, rx_desc))
6707 /* verify the packet layout is correct */
6708 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6713 /* probably a little skewed due to removing CRC */
6714 total_bytes += skb->len;
6716 /* populate checksum, timestamp, VLAN, and protocol */
6717 igb_process_skb_fields(rx_ring, rx_desc, skb);
6719 napi_gro_receive(&q_vector->napi, skb);
6721 /* reset skb pointer */
6724 /* update budget accounting */
6726 } while (likely(total_packets < budget));
6728 /* place incomplete frames back on ring for completion */
6731 u64_stats_update_begin(&rx_ring->rx_syncp);
6732 rx_ring->rx_stats.packets += total_packets;
6733 rx_ring->rx_stats.bytes += total_bytes;
6734 u64_stats_update_end(&rx_ring->rx_syncp);
6735 q_vector->rx.total_packets += total_packets;
6736 q_vector->rx.total_bytes += total_bytes;
6739 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6741 return (total_packets < budget);
6744 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6745 struct igb_rx_buffer *bi)
6747 struct page *page = bi->page;
6750 /* since we are recycling buffers we should seldom need to alloc */
6754 /* alloc new page for storage */
6755 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6756 if (unlikely(!page)) {
6757 rx_ring->rx_stats.alloc_failed++;
6761 /* map page for use */
6762 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6765 * if mapping failed free memory back to system since
6766 * there isn't much point in holding memory we can't use
6768 if (dma_mapping_error(rx_ring->dev, dma)) {
6771 rx_ring->rx_stats.alloc_failed++;
6777 bi->page_offset = 0;
6782 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring)
6784 if (ring_uses_build_skb(rx_ring))
6785 return NET_SKB_PAD + NET_IP_ALIGN;
6791 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6792 * @adapter: address of board private structure
6794 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6796 union e1000_adv_rx_desc *rx_desc;
6797 struct igb_rx_buffer *bi;
6798 u16 i = rx_ring->next_to_use;
6804 rx_desc = IGB_RX_DESC(rx_ring, i);
6805 bi = &rx_ring->rx_buffer_info[i];
6806 i -= rx_ring->count;
6809 if (!igb_alloc_mapped_page(rx_ring, bi))
6813 * Refresh the desc even if buffer_addrs didn't change
6814 * because each write-back erases this info.
6816 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma +
6818 igb_rx_offset(rx_ring));
6824 rx_desc = IGB_RX_DESC(rx_ring, 0);
6825 bi = rx_ring->rx_buffer_info;
6826 i -= rx_ring->count;
6829 /* clear the hdr_addr for the next_to_use descriptor */
6830 rx_desc->read.hdr_addr = 0;
6833 } while (cleaned_count);
6835 i += rx_ring->count;
6837 if (rx_ring->next_to_use != i) {
6838 /* record the next descriptor to use */
6839 rx_ring->next_to_use = i;
6841 /* update next to alloc since we have filled the ring */
6842 rx_ring->next_to_alloc = i;
6845 * Force memory writes to complete before letting h/w
6846 * know there are new descriptors to fetch. (Only
6847 * applicable for weak-ordered memory model archs,
6851 writel(i, rx_ring->tail);
6861 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6863 struct igb_adapter *adapter = netdev_priv(netdev);
6864 struct mii_ioctl_data *data = if_mii(ifr);
6866 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6871 data->phy_id = adapter->hw.phy.addr;
6874 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6891 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6897 return igb_mii_ioctl(netdev, ifr, cmd);
6899 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6905 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6907 struct igb_adapter *adapter = hw->back;
6909 if (pcie_capability_read_word(adapter->pdev, reg, value))
6910 return -E1000_ERR_CONFIG;
6915 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6917 struct igb_adapter *adapter = hw->back;
6919 if (pcie_capability_write_word(adapter->pdev, reg, *value))
6920 return -E1000_ERR_CONFIG;
6925 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6927 struct igb_adapter *adapter = netdev_priv(netdev);
6928 struct e1000_hw *hw = &adapter->hw;
6930 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
6933 /* enable VLAN tag insert/strip */
6934 ctrl = rd32(E1000_CTRL);
6935 ctrl |= E1000_CTRL_VME;
6936 wr32(E1000_CTRL, ctrl);
6938 /* Disable CFI check */
6939 rctl = rd32(E1000_RCTL);
6940 rctl &= ~E1000_RCTL_CFIEN;
6941 wr32(E1000_RCTL, rctl);
6943 /* disable VLAN tag insert/strip */
6944 ctrl = rd32(E1000_CTRL);
6945 ctrl &= ~E1000_CTRL_VME;
6946 wr32(E1000_CTRL, ctrl);
6949 igb_rlpml_set(adapter);
6952 static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6954 struct igb_adapter *adapter = netdev_priv(netdev);
6955 struct e1000_hw *hw = &adapter->hw;
6956 int pf_id = adapter->vfs_allocated_count;
6958 /* attempt to add filter to vlvf array */
6959 igb_vlvf_set(adapter, vid, true, pf_id);
6961 /* add the filter since PF can receive vlans w/o entry in vlvf */
6962 igb_vfta_set(hw, vid, true);
6964 set_bit(vid, adapter->active_vlans);
6969 static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6971 struct igb_adapter *adapter = netdev_priv(netdev);
6972 struct e1000_hw *hw = &adapter->hw;
6973 int pf_id = adapter->vfs_allocated_count;
6976 /* remove vlan from VLVF table array */
6977 err = igb_vlvf_set(adapter, vid, false, pf_id);
6979 /* if vid was not present in VLVF just remove it from table */
6981 igb_vfta_set(hw, vid, false);
6983 clear_bit(vid, adapter->active_vlans);
6988 static void igb_restore_vlan(struct igb_adapter *adapter)
6992 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6994 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6995 igb_vlan_rx_add_vid(adapter->netdev, vid);
6998 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7000 struct pci_dev *pdev = adapter->pdev;
7001 struct e1000_mac_info *mac = &adapter->hw.mac;
7005 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7006 * for the switch() below to work */
7007 if ((spd & 1) || (dplx & ~1))
7010 /* Fiber NIC's only allow 1000 gbps Full duplex
7011 * and 100Mbps Full duplex for 100baseFx sfp
7013 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7014 switch (spd + dplx) {
7015 case SPEED_10 + DUPLEX_HALF:
7016 case SPEED_10 + DUPLEX_FULL:
7017 case SPEED_100 + DUPLEX_HALF:
7024 switch (spd + dplx) {
7025 case SPEED_10 + DUPLEX_HALF:
7026 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7028 case SPEED_10 + DUPLEX_FULL:
7029 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7031 case SPEED_100 + DUPLEX_HALF:
7032 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7034 case SPEED_100 + DUPLEX_FULL:
7035 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7037 case SPEED_1000 + DUPLEX_FULL:
7039 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7041 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7046 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7047 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7052 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7056 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7059 struct net_device *netdev = pci_get_drvdata(pdev);
7060 struct igb_adapter *adapter = netdev_priv(netdev);
7061 struct e1000_hw *hw = &adapter->hw;
7062 u32 ctrl, rctl, status;
7063 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7068 netif_device_detach(netdev);
7070 if (netif_running(netdev))
7071 __igb_close(netdev, true);
7073 igb_clear_interrupt_scheme(adapter);
7076 retval = pci_save_state(pdev);
7081 status = rd32(E1000_STATUS);
7082 if (status & E1000_STATUS_LU)
7083 wufc &= ~E1000_WUFC_LNKC;
7086 igb_setup_rctl(adapter);
7087 igb_set_rx_mode(netdev);
7089 /* turn on all-multi mode if wake on multicast is enabled */
7090 if (wufc & E1000_WUFC_MC) {
7091 rctl = rd32(E1000_RCTL);
7092 rctl |= E1000_RCTL_MPE;
7093 wr32(E1000_RCTL, rctl);
7096 ctrl = rd32(E1000_CTRL);
7097 /* advertise wake from D3Cold */
7098 #define E1000_CTRL_ADVD3WUC 0x00100000
7099 /* phy power management enable */
7100 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7101 ctrl |= E1000_CTRL_ADVD3WUC;
7102 wr32(E1000_CTRL, ctrl);
7104 /* Allow time for pending master requests to run */
7105 igb_disable_pcie_master(hw);
7107 wr32(E1000_WUC, E1000_WUC_PME_EN);
7108 wr32(E1000_WUFC, wufc);
7111 wr32(E1000_WUFC, 0);
7114 *enable_wake = wufc || adapter->en_mng_pt;
7116 igb_power_down_link(adapter);
7118 igb_power_up_link(adapter);
7120 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7121 * would have already happened in close and is redundant. */
7122 igb_release_hw_control(adapter);
7124 pci_disable_device(pdev);
7130 #ifdef CONFIG_PM_SLEEP
7131 static int igb_suspend(struct device *dev)
7135 struct pci_dev *pdev = to_pci_dev(dev);
7137 retval = __igb_shutdown(pdev, &wake, 0);
7142 pci_prepare_to_sleep(pdev);
7144 pci_wake_from_d3(pdev, false);
7145 pci_set_power_state(pdev, PCI_D3hot);
7150 #endif /* CONFIG_PM_SLEEP */
7152 static int igb_resume(struct device *dev)
7154 struct pci_dev *pdev = to_pci_dev(dev);
7155 struct net_device *netdev = pci_get_drvdata(pdev);
7156 struct igb_adapter *adapter = netdev_priv(netdev);
7157 struct e1000_hw *hw = &adapter->hw;
7160 pci_set_power_state(pdev, PCI_D0);
7161 pci_restore_state(pdev);
7162 pci_save_state(pdev);
7164 err = pci_enable_device_mem(pdev);
7167 "igb: Cannot enable PCI device from suspend\n");
7170 pci_set_master(pdev);
7172 pci_enable_wake(pdev, PCI_D3hot, 0);
7173 pci_enable_wake(pdev, PCI_D3cold, 0);
7175 if (igb_init_interrupt_scheme(adapter, true)) {
7176 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7182 /* let the f/w know that the h/w is now under the control of the
7184 igb_get_hw_control(adapter);
7186 wr32(E1000_WUS, ~0);
7188 if (netdev->flags & IFF_UP) {
7190 err = __igb_open(netdev, true);
7196 netif_device_attach(netdev);
7200 #ifdef CONFIG_PM_RUNTIME
7201 static int igb_runtime_idle(struct device *dev)
7203 struct pci_dev *pdev = to_pci_dev(dev);
7204 struct net_device *netdev = pci_get_drvdata(pdev);
7205 struct igb_adapter *adapter = netdev_priv(netdev);
7207 if (!igb_has_link(adapter))
7208 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7213 static int igb_runtime_suspend(struct device *dev)
7215 struct pci_dev *pdev = to_pci_dev(dev);
7219 retval = __igb_shutdown(pdev, &wake, 1);
7224 pci_prepare_to_sleep(pdev);
7226 pci_wake_from_d3(pdev, false);
7227 pci_set_power_state(pdev, PCI_D3hot);
7233 static int igb_runtime_resume(struct device *dev)
7235 return igb_resume(dev);
7237 #endif /* CONFIG_PM_RUNTIME */
7240 static void igb_shutdown(struct pci_dev *pdev)
7244 __igb_shutdown(pdev, &wake, 0);
7246 if (system_state == SYSTEM_POWER_OFF) {
7247 pci_wake_from_d3(pdev, wake);
7248 pci_set_power_state(pdev, PCI_D3hot);
7252 #ifdef CONFIG_PCI_IOV
7253 static int igb_sriov_reinit(struct pci_dev *dev)
7255 struct net_device *netdev = pci_get_drvdata(dev);
7256 struct igb_adapter *adapter = netdev_priv(netdev);
7257 struct pci_dev *pdev = adapter->pdev;
7261 if (netif_running(netdev))
7264 igb_clear_interrupt_scheme(adapter);
7266 igb_init_queue_configuration(adapter);
7268 if (igb_init_interrupt_scheme(adapter, true)) {
7269 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7273 if (netif_running(netdev))
7281 static int igb_pci_disable_sriov(struct pci_dev *dev)
7283 int err = igb_disable_sriov(dev);
7286 err = igb_sriov_reinit(dev);
7291 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7293 int err = igb_enable_sriov(dev, num_vfs);
7298 err = igb_sriov_reinit(dev);
7307 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7309 #ifdef CONFIG_PCI_IOV
7311 return igb_pci_disable_sriov(dev);
7313 return igb_pci_enable_sriov(dev, num_vfs);
7318 #ifdef CONFIG_NET_POLL_CONTROLLER
7320 * Polling 'interrupt' - used by things like netconsole to send skbs
7321 * without having to re-enable interrupts. It's not called while
7322 * the interrupt routine is executing.
7324 static void igb_netpoll(struct net_device *netdev)
7326 struct igb_adapter *adapter = netdev_priv(netdev);
7327 struct e1000_hw *hw = &adapter->hw;
7328 struct igb_q_vector *q_vector;
7331 for (i = 0; i < adapter->num_q_vectors; i++) {
7332 q_vector = adapter->q_vector[i];
7333 if (adapter->msix_entries)
7334 wr32(E1000_EIMC, q_vector->eims_value);
7336 igb_irq_disable(adapter);
7337 napi_schedule(&q_vector->napi);
7340 #endif /* CONFIG_NET_POLL_CONTROLLER */
7343 * igb_io_error_detected - called when PCI error is detected
7344 * @pdev: Pointer to PCI device
7345 * @state: The current pci connection state
7347 * This function is called after a PCI bus error affecting
7348 * this device has been detected.
7350 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7351 pci_channel_state_t state)
7353 struct net_device *netdev = pci_get_drvdata(pdev);
7354 struct igb_adapter *adapter = netdev_priv(netdev);
7356 netif_device_detach(netdev);
7358 if (state == pci_channel_io_perm_failure)
7359 return PCI_ERS_RESULT_DISCONNECT;
7361 if (netif_running(netdev))
7363 pci_disable_device(pdev);
7365 /* Request a slot slot reset. */
7366 return PCI_ERS_RESULT_NEED_RESET;
7370 * igb_io_slot_reset - called after the pci bus has been reset.
7371 * @pdev: Pointer to PCI device
7373 * Restart the card from scratch, as if from a cold-boot. Implementation
7374 * resembles the first-half of the igb_resume routine.
7376 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7378 struct net_device *netdev = pci_get_drvdata(pdev);
7379 struct igb_adapter *adapter = netdev_priv(netdev);
7380 struct e1000_hw *hw = &adapter->hw;
7381 pci_ers_result_t result;
7384 if (pci_enable_device_mem(pdev)) {
7386 "Cannot re-enable PCI device after reset.\n");
7387 result = PCI_ERS_RESULT_DISCONNECT;
7389 pci_set_master(pdev);
7390 pci_restore_state(pdev);
7391 pci_save_state(pdev);
7393 pci_enable_wake(pdev, PCI_D3hot, 0);
7394 pci_enable_wake(pdev, PCI_D3cold, 0);
7397 wr32(E1000_WUS, ~0);
7398 result = PCI_ERS_RESULT_RECOVERED;
7401 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7403 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7404 "failed 0x%0x\n", err);
7405 /* non-fatal, continue */
7412 * igb_io_resume - called when traffic can start flowing again.
7413 * @pdev: Pointer to PCI device
7415 * This callback is called when the error recovery driver tells us that
7416 * its OK to resume normal operation. Implementation resembles the
7417 * second-half of the igb_resume routine.
7419 static void igb_io_resume(struct pci_dev *pdev)
7421 struct net_device *netdev = pci_get_drvdata(pdev);
7422 struct igb_adapter *adapter = netdev_priv(netdev);
7424 if (netif_running(netdev)) {
7425 if (igb_up(adapter)) {
7426 dev_err(&pdev->dev, "igb_up failed after reset\n");
7431 netif_device_attach(netdev);
7433 /* let the f/w know that the h/w is now under the control of the
7435 igb_get_hw_control(adapter);
7438 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7441 u32 rar_low, rar_high;
7442 struct e1000_hw *hw = &adapter->hw;
7444 /* HW expects these in little endian so we reverse the byte order
7445 * from network order (big endian) to little endian
7447 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7448 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7449 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7451 /* Indicate to hardware the Address is Valid. */
7452 rar_high |= E1000_RAH_AV;
7454 if (hw->mac.type == e1000_82575)
7455 rar_high |= E1000_RAH_POOL_1 * qsel;
7457 rar_high |= E1000_RAH_POOL_1 << qsel;
7459 wr32(E1000_RAL(index), rar_low);
7461 wr32(E1000_RAH(index), rar_high);
7465 static int igb_set_vf_mac(struct igb_adapter *adapter,
7466 int vf, unsigned char *mac_addr)
7468 struct e1000_hw *hw = &adapter->hw;
7469 /* VF MAC addresses start at end of receive addresses and moves
7470 * torwards the first, as a result a collision should not be possible */
7471 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7473 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7475 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7480 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7482 struct igb_adapter *adapter = netdev_priv(netdev);
7483 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7485 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7486 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7487 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7488 " change effective.");
7489 if (test_bit(__IGB_DOWN, &adapter->state)) {
7490 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7491 " but the PF device is not up.\n");
7492 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7493 " attempting to use the VF device.\n");
7495 return igb_set_vf_mac(adapter, vf, mac);
7498 static int igb_link_mbps(int internal_link_speed)
7500 switch (internal_link_speed) {
7510 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7517 /* Calculate the rate factor values to set */
7518 rf_int = link_speed / tx_rate;
7519 rf_dec = (link_speed - (rf_int * tx_rate));
7520 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7522 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7523 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7524 E1000_RTTBCNRC_RF_INT_MASK);
7525 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7530 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7532 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7533 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7535 wr32(E1000_RTTBCNRM, 0x14);
7536 wr32(E1000_RTTBCNRC, bcnrc_val);
7539 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7541 int actual_link_speed, i;
7542 bool reset_rate = false;
7544 /* VF TX rate limit was not set or not supported */
7545 if ((adapter->vf_rate_link_speed == 0) ||
7546 (adapter->hw.mac.type != e1000_82576))
7549 actual_link_speed = igb_link_mbps(adapter->link_speed);
7550 if (actual_link_speed != adapter->vf_rate_link_speed) {
7552 adapter->vf_rate_link_speed = 0;
7553 dev_info(&adapter->pdev->dev,
7554 "Link speed has been changed. VF Transmit "
7555 "rate is disabled\n");
7558 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7560 adapter->vf_data[i].tx_rate = 0;
7562 igb_set_vf_rate_limit(&adapter->hw, i,
7563 adapter->vf_data[i].tx_rate,
7568 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7570 struct igb_adapter *adapter = netdev_priv(netdev);
7571 struct e1000_hw *hw = &adapter->hw;
7572 int actual_link_speed;
7574 if (hw->mac.type != e1000_82576)
7577 actual_link_speed = igb_link_mbps(adapter->link_speed);
7578 if ((vf >= adapter->vfs_allocated_count) ||
7579 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7580 (tx_rate < 0) || (tx_rate > actual_link_speed))
7583 adapter->vf_rate_link_speed = actual_link_speed;
7584 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7585 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7590 static int igb_ndo_get_vf_config(struct net_device *netdev,
7591 int vf, struct ifla_vf_info *ivi)
7593 struct igb_adapter *adapter = netdev_priv(netdev);
7594 if (vf >= adapter->vfs_allocated_count)
7597 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7598 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7599 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7600 ivi->qos = adapter->vf_data[vf].pf_qos;
7604 static void igb_vmm_control(struct igb_adapter *adapter)
7606 struct e1000_hw *hw = &adapter->hw;
7609 switch (hw->mac.type) {
7614 /* replication is not supported for 82575 */
7617 /* notify HW that the MAC is adding vlan tags */
7618 reg = rd32(E1000_DTXCTL);
7619 reg |= E1000_DTXCTL_VLAN_ADDED;
7620 wr32(E1000_DTXCTL, reg);
7622 /* enable replication vlan tag stripping */
7623 reg = rd32(E1000_RPLOLR);
7624 reg |= E1000_RPLOLR_STRVLAN;
7625 wr32(E1000_RPLOLR, reg);
7627 /* none of the above registers are supported by i350 */
7631 if (adapter->vfs_allocated_count) {
7632 igb_vmdq_set_loopback_pf(hw, true);
7633 igb_vmdq_set_replication_pf(hw, true);
7634 igb_vmdq_set_anti_spoofing_pf(hw, true,
7635 adapter->vfs_allocated_count);
7637 igb_vmdq_set_loopback_pf(hw, false);
7638 igb_vmdq_set_replication_pf(hw, false);
7642 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7644 struct e1000_hw *hw = &adapter->hw;
7648 if (hw->mac.type > e1000_82580) {
7649 if (adapter->flags & IGB_FLAG_DMAC) {
7652 /* force threshold to 0. */
7653 wr32(E1000_DMCTXTH, 0);
7656 * DMA Coalescing high water mark needs to be greater
7657 * than the Rx threshold. Set hwm to PBA - max frame
7658 * size in 16B units, capping it at PBA - 6KB.
7660 hwm = 64 * pba - adapter->max_frame_size / 16;
7661 if (hwm < 64 * (pba - 6))
7662 hwm = 64 * (pba - 6);
7663 reg = rd32(E1000_FCRTC);
7664 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7665 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7666 & E1000_FCRTC_RTH_COAL_MASK);
7667 wr32(E1000_FCRTC, reg);
7670 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7671 * frame size, capping it at PBA - 10KB.
7673 dmac_thr = pba - adapter->max_frame_size / 512;
7674 if (dmac_thr < pba - 10)
7675 dmac_thr = pba - 10;
7676 reg = rd32(E1000_DMACR);
7677 reg &= ~E1000_DMACR_DMACTHR_MASK;
7678 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7679 & E1000_DMACR_DMACTHR_MASK);
7681 /* transition to L0x or L1 if available..*/
7682 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7684 /* watchdog timer= +-1000 usec in 32usec intervals */
7687 /* Disable BMC-to-OS Watchdog Enable */
7688 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7689 wr32(E1000_DMACR, reg);
7692 * no lower threshold to disable
7693 * coalescing(smart fifb)-UTRESH=0
7695 wr32(E1000_DMCRTRH, 0);
7697 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7699 wr32(E1000_DMCTLX, reg);
7702 * free space in tx packet buffer to wake from
7705 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7706 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7709 * make low power state decision controlled
7712 reg = rd32(E1000_PCIEMISC);
7713 reg &= ~E1000_PCIEMISC_LX_DECISION;
7714 wr32(E1000_PCIEMISC, reg);
7715 } /* endif adapter->dmac is not disabled */
7716 } else if (hw->mac.type == e1000_82580) {
7717 u32 reg = rd32(E1000_PCIEMISC);
7718 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7719 wr32(E1000_DMACR, 0);
7723 /* igb_read_i2c_byte - Reads 8 bit word over I2C
7724 * @hw: pointer to hardware structure
7725 * @byte_offset: byte offset to read
7726 * @dev_addr: device address
7729 * Performs byte read operation over I2C interface at
7730 * a specified device address.
7732 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7733 u8 dev_addr, u8 *data)
7735 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7736 struct i2c_client *this_client = adapter->i2c_client;
7741 return E1000_ERR_I2C;
7743 swfw_mask = E1000_SWFW_PHY0_SM;
7745 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7747 return E1000_ERR_SWFW_SYNC;
7749 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7750 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7753 return E1000_ERR_I2C;
7756 return E1000_SUCCESS;
7760 /* igb_write_i2c_byte - Writes 8 bit word over I2C
7761 * @hw: pointer to hardware structure
7762 * @byte_offset: byte offset to write
7763 * @dev_addr: device address
7764 * @data: value to write
7766 * Performs byte write operation over I2C interface at
7767 * a specified device address.
7769 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7770 u8 dev_addr, u8 data)
7772 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7773 struct i2c_client *this_client = adapter->i2c_client;
7775 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7778 return E1000_ERR_I2C;
7780 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7781 return E1000_ERR_SWFW_SYNC;
7782 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7783 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7786 return E1000_ERR_I2C;
7788 return E1000_SUCCESS;