1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
54 #include <linux/dca.h>
56 #include <linux/i2c.h>
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
71 static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
75 static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static int igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 static int igb_disable_sriov(struct pci_dev *dev);
183 static int igb_pci_disable_sriov(struct pci_dev *dev);
187 #ifdef CONFIG_PM_SLEEP
188 static int igb_suspend(struct device *);
190 static int igb_resume(struct device *);
191 static int igb_runtime_suspend(struct device *dev);
192 static int igb_runtime_resume(struct device *dev);
193 static int igb_runtime_idle(struct device *dev);
194 static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 static void igb_shutdown(struct pci_dev *);
201 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
202 #ifdef CONFIG_IGB_DCA
203 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204 static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
210 #ifdef CONFIG_NET_POLL_CONTROLLER
211 /* for netdump / net console */
212 static void igb_netpoll(struct net_device *);
214 #ifdef CONFIG_PCI_IOV
215 static unsigned int max_vfs;
216 module_param(max_vfs, uint, 0);
217 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
218 #endif /* CONFIG_PCI_IOV */
220 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223 static void igb_io_resume(struct pci_dev *);
225 static const struct pci_error_handlers igb_err_handler = {
226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
231 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
233 static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
237 .remove = igb_remove,
239 .driver.pm = &igb_pm_ops,
241 .shutdown = igb_shutdown,
242 .sriov_configure = igb_pci_sriov_configure,
243 .err_handler = &igb_err_handler
246 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248 MODULE_LICENSE("GPL");
249 MODULE_VERSION(DRV_VERSION);
251 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252 static int debug = -1;
253 module_param(debug, int, 0);
254 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
256 struct igb_reg_info {
261 static const struct igb_reg_info igb_reg_info_tbl[] = {
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
268 /* Interrupt Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
293 /* List Terminator */
297 /* igb_regdump - register printout routine */
298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
304 switch (reginfo->ofs) {
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
363 /* igb_dump - Print registers, Tx-rings and Rx-rings */
364 static void igb_dump(struct igb_adapter *adapter)
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
377 if (!netif_msg_hw(adapter))
380 /* Print netdevice Info */
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
383 pr_info("Device Name state trans_start last_rx\n");
384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
390 pr_info(" Register Name Value\n");
391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
402 for (n = 0; n < adapter->num_tx_queues; n++) {
403 struct igb_tx_buffer *buffer_info;
404 tx_ring = adapter->tx_ring[n];
405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
420 /* Transmit Descriptor Formats
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
439 const char *next_desc;
440 struct igb_tx_buffer *buffer_info;
441 tx_desc = IGB_TX_DESC(tx_ring, i);
442 buffer_info = &tx_ring->tx_buffer_info[i];
443 u0 = (struct my_u0 *)tx_desc;
444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
449 else if (i == tx_ring->next_to_clean)
454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
461 buffer_info->skb, next_desc);
463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
464 print_hex_dump(KERN_INFO, "",
466 16, 1, buffer_info->skb->data,
467 dma_unmap_len(buffer_info, len),
472 /* Print RX Rings Summary */
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
475 pr_info("Queue [NTU] [NTC]\n");
476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
483 if (!netif_msg_rx_status(adapter))
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488 /* Advanced Receive Descriptor (Read) Format
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
497 * Advanced Receive Descriptor (Write-Back) Format
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
517 for (i = 0; i < rx_ring->count; i++) {
518 const char *next_desc;
519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
521 rx_desc = IGB_RX_DESC(rx_ring, i);
522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
525 if (i == rx_ring->next_to_use)
527 else if (i == rx_ring->next_to_clean)
532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
544 (u64)buffer_info->dma,
547 if (netif_msg_pktdata(adapter) &&
548 buffer_info->dma && buffer_info->page) {
549 print_hex_dump(KERN_INFO, "",
552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
565 * igb_get_i2c_data - Reads the I2C SDA data bit
566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
569 * Returns the I2C data bit value
571 static int igb_get_i2c_data(void *data)
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
577 return !!(i2cctl & E1000_I2C_DATA_IN);
581 * igb_set_i2c_data - Sets the I2C data bit
582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
585 * Sets the I2C data bit
587 static void igb_set_i2c_data(void *data, int state)
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
594 i2cctl |= E1000_I2C_DATA_OUT;
596 i2cctl &= ~E1000_I2C_DATA_OUT;
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
606 * igb_set_i2c_clk - Sets the I2C SCL clock
607 * @data: pointer to hardware structure
608 * @state: state to set clock
610 * Sets the I2C clock line to state
612 static void igb_set_i2c_clk(void *data, int state)
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 wr32(E1000_I2CPARAMS, i2cctl);
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
631 * @data: pointer to hardware structure
633 * Gets the I2C clock state
635 static int igb_get_i2c_clk(void *data)
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
641 return !!(i2cctl & E1000_I2C_CLK_IN);
644 static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
657 * used by hardware layer to print debugging information
659 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
661 struct igb_adapter *adapter = hw->back;
662 return adapter->netdev;
666 * igb_init_module - Driver Registration Routine
668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
671 static int __init igb_init_module(void)
675 pr_info("%s - version %s\n",
676 igb_driver_string, igb_driver_version);
677 pr_info("%s\n", igb_copyright);
679 #ifdef CONFIG_IGB_DCA
680 dca_register_notify(&dca_notifier);
682 ret = pci_register_driver(&igb_driver);
686 module_init(igb_init_module);
689 * igb_exit_module - Driver Exit Cleanup Routine
691 * igb_exit_module is called just before the driver is removed
694 static void __exit igb_exit_module(void)
696 #ifdef CONFIG_IGB_DCA
697 dca_unregister_notify(&dca_notifier);
699 pci_unregister_driver(&igb_driver);
702 module_exit(igb_exit_module);
704 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
712 static void igb_cache_ring_register(struct igb_adapter *adapter)
715 u32 rbase_offset = adapter->vfs_allocated_count;
717 switch (adapter->hw.mac.type) {
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
724 if (adapter->vfs_allocated_count) {
725 for (; i < adapter->rss_queues; i++)
726 adapter->rx_ring[i]->reg_idx = rbase_offset +
738 for (; i < adapter->num_rx_queues; i++)
739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
740 for (; j < adapter->num_tx_queues; j++)
741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
746 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
752 if (E1000_REMOVED(hw_addr))
755 value = readl(&hw_addr[reg]);
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
780 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
783 u32 ivar = array_rd32(E1000_IVAR0, index);
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
791 array_wr32(E1000_IVAR0, index, ivar);
794 #define IGB_N0_QUEUE -1
795 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
797 struct igb_adapter *adapter = q_vector->adapter;
798 struct e1000_hw *hw = &adapter->hw;
799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
808 switch (hw->mac.type) {
810 /* The 82575 assigns vectors using a bitmask, which matches the
811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
815 if (rx_queue > IGB_N0_QUEUE)
816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
817 if (tx_queue > IGB_N0_QUEUE)
818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
820 msixbm |= E1000_EIMS_OTHER;
821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
822 q_vector->eims_value = msixbm;
825 /* 82576 uses a table that essentially consists of 2 columns
826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
837 ((tx_queue & 0x8) << 1) + 8);
838 q_vector->eims_value = 1 << msix_vector;
845 /* On 82580 and newer adapters the scheme is similar to 82576
846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
858 ((tx_queue & 0x1) << 4) + 8);
859 q_vector->eims_value = 1 << msix_vector;
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
880 static void igb_configure_msix(struct igb_adapter *adapter)
884 struct e1000_hw *hw = &adapter->hw;
886 adapter->eims_enable_mask = 0;
888 /* set vector for other causes, i.e. link changes */
889 switch (hw->mac.type) {
891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
899 wr32(E1000_CTRL_EXT, tmp);
901 /* enable msix_other interrupt */
902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
903 adapter->eims_other = E1000_EIMS_OTHER;
913 /* Turn on MSI-X capability first, or our settings
914 * won't stick. And it will take days to debug.
916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
924 wr32(E1000_IVAR_MISC, tmp);
927 /* do nothing, since nothing else supports MSI-X */
929 } /* switch (hw->mac.type) */
931 adapter->eims_enable_mask |= adapter->eims_other;
933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
946 static int igb_request_msix(struct igb_adapter *adapter)
948 struct net_device *netdev = adapter->netdev;
949 struct e1000_hw *hw = &adapter->hw;
950 int i, err = 0, vector = 0, free_vector = 0;
952 err = request_irq(adapter->msix_entries[vector].vector,
953 igb_msix_other, 0, netdev->name, adapter);
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
964 if (q_vector->rx.ring && q_vector->tx.ring)
965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
972 q_vector->rx.ring->queue_index);
974 sprintf(q_vector->name, "%s-unused", netdev->name);
976 err = request_irq(adapter->msix_entries[vector].vector,
977 igb_msix_ring, 0, q_vector->name,
983 igb_configure_msix(adapter);
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
1004 * This function frees the memory allocated to the q_vector.
1006 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1010 adapter->q_vector[v_idx] = NULL;
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1016 kfree_rcu(q_vector, rcu);
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1027 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1040 if (q_vector->rx.ring)
1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1043 netif_napi_del(&q_vector->napi);
1047 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1049 int v_idx = adapter->num_q_vectors;
1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1052 pci_disable_msix(adapter->pdev);
1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1054 pci_disable_msi(adapter->pdev);
1057 igb_reset_q_vector(adapter, v_idx);
1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
1068 static void igb_free_q_vectors(struct igb_adapter *adapter)
1070 int v_idx = adapter->num_q_vectors;
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
1074 adapter->num_q_vectors = 0;
1077 igb_reset_q_vector(adapter, v_idx);
1078 igb_free_q_vector(adapter, v_idx);
1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
1089 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
1103 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
1112 /* Number of supported queues. */
1113 adapter->num_rx_queues = adapter->rss_queues;
1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1117 adapter->num_tx_queues = adapter->rss_queues;
1119 /* start with one vector for every Rx queue */
1120 numvecs = adapter->num_rx_queues;
1122 /* if Tx handler is separate add 1 for every Tx queue */
1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1129 /* add 1 vector for link status interrupts */
1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1141 igb_reset_interrupt_capability(adapter);
1143 /* If we can't do MSI-X, try MSI */
1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1146 #ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1162 adapter->vfs_allocated_count = 0;
1163 adapter->rss_queues = 1;
1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1165 adapter->num_rx_queues = 1;
1166 adapter->num_tx_queues = 1;
1167 adapter->num_q_vectors = 1;
1168 if (!pci_enable_msi(adapter->pdev))
1169 adapter->flags |= IGB_FLAG_HAS_MSI;
1172 static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1191 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
1196 struct igb_q_vector *q_vector;
1197 struct igb_ring *ring;
1198 int ring_count, size;
1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1208 /* allocate q_vector and rings */
1209 q_vector = adapter->q_vector[v_idx];
1211 q_vector = kzalloc(size, GFP_KERNEL);
1212 } else if (size > ksize(q_vector)) {
1213 kfree_rcu(q_vector, rcu);
1214 q_vector = kzalloc(size, GFP_KERNEL);
1216 memset(q_vector, 0, size);
1221 /* initialize NAPI */
1222 netif_napi_add(adapter->netdev, &q_vector->napi,
1225 /* tie q_vector and adapter together */
1226 adapter->q_vector[v_idx] = q_vector;
1227 q_vector->adapter = adapter;
1229 /* initialize work limits */
1230 q_vector->tx.work_limit = adapter->tx_work_limit;
1232 /* initialize ITR configuration */
1233 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1234 q_vector->itr_val = IGB_START_ITR;
1236 /* initialize pointer to rings */
1237 ring = q_vector->ring;
1241 /* rx or rx/tx vector */
1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 q_vector->itr_val = adapter->rx_itr_setting;
1245 /* tx only vector */
1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 q_vector->itr_val = adapter->tx_itr_setting;
1251 /* assign generic ring traits */
1252 ring->dev = &adapter->pdev->dev;
1253 ring->netdev = adapter->netdev;
1255 /* configure backlink on ring */
1256 ring->q_vector = q_vector;
1258 /* update q_vector Tx values */
1259 igb_add_ring(ring, &q_vector->tx);
1261 /* For 82575, context index must be unique per ring. */
1262 if (adapter->hw.mac.type == e1000_82575)
1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1265 /* apply Tx specific ring traits */
1266 ring->count = adapter->tx_ring_count;
1267 ring->queue_index = txr_idx;
1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1275 /* push pointer to next ring */
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1294 /* On i350, i354, i210, and i211, loopback VLAN packets
1295 * have the tag byte-swapped.
1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1300 /* apply Rx specific ring traits */
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1304 u64_stats_init(&ring->rx_syncp);
1306 /* assign ring to adapter */
1307 adapter->rx_ring[rxr_idx] = ring;
1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316 * @adapter: board private structure to initialize
1318 * We allocate one q_vector per queue interrupt. If allocation fails we
1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1337 /* update counts and index */
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1368 igb_free_q_vector(adapter, v_idx);
1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
1378 * This function initializes the interrupts and allocates all of the queues.
1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1382 struct pci_dev *pdev = adapter->pdev;
1385 igb_set_interrupt_capability(adapter, msix);
1387 err = igb_alloc_q_vectors(adapter);
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1393 igb_cache_ring_register(adapter);
1397 err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
1409 static int igb_request_irq(struct igb_adapter *adapter)
1411 struct net_device *netdev = adapter->netdev;
1412 struct pci_dev *pdev = adapter->pdev;
1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416 err = igb_request_msix(adapter);
1419 /* fall back to MSI */
1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
1423 igb_clear_interrupt_scheme(adapter);
1424 err = igb_init_interrupt_scheme(adapter, false);
1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
1430 igb_configure(adapter);
1433 igb_assign_vector(adapter->q_vector[0], 0);
1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
1437 netdev->name, adapter);
1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447 netdev->name, adapter);
1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1457 static void igb_free_irq(struct igb_adapter *adapter)
1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
1464 for (i = 0; i < adapter->num_q_vectors; i++)
1465 free_irq(adapter->msix_entries[vector++].vector,
1466 adapter->q_vector[i]);
1468 free_irq(adapter->pdev->irq, adapter);
1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
1476 static void igb_irq_disable(struct igb_adapter *adapter)
1478 struct e1000_hw *hw = &adapter->hw;
1480 /* we need to be careful when disabling interrupts. The VFs are also
1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485 u32 regval = rd32(E1000_EIAM);
1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1494 wr32(E1000_IMC, ~0);
1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1502 synchronize_irq(adapter->pdev->irq);
1507 * igb_irq_enable - Enable default interrupt generation settings
1508 * @adapter: board private structure
1510 static void igb_irq_enable(struct igb_adapter *adapter)
1512 struct e1000_hw *hw = &adapter->hw;
1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516 u32 regval = rd32(E1000_EIAC);
1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
1522 if (adapter->vfs_allocated_count) {
1523 wr32(E1000_MBVFIMR, 0xFF);
1524 ims |= E1000_IMS_VMMB;
1526 wr32(E1000_IMS, ims);
1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1535 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1537 struct e1000_hw *hw = &adapter->hw;
1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
1543 igb_vfta_set(hw, vid, true);
1544 adapter->mng_vlan_id = vid;
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1551 !test_bit(old_vid, adapter->active_vlans)) {
1552 /* remove VID from filter table */
1553 igb_vfta_set(hw, old_vid, false);
1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
1565 static void igb_release_hw_control(struct igb_adapter *adapter)
1567 struct e1000_hw *hw = &adapter->hw;
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
1584 static void igb_get_hw_control(struct igb_adapter *adapter)
1586 struct e1000_hw *hw = &adapter->hw;
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
1599 static void igb_configure(struct igb_adapter *adapter)
1601 struct net_device *netdev = adapter->netdev;
1604 igb_get_hw_control(adapter);
1605 igb_set_rx_mode(netdev);
1607 igb_restore_vlan(adapter);
1609 igb_setup_tctl(adapter);
1610 igb_setup_mrqc(adapter);
1611 igb_setup_rctl(adapter);
1613 igb_configure_tx(adapter);
1614 igb_configure_rx(adapter);
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1618 /* call igb_desc_unused which always leaves
1619 * at least 1 descriptor unused to make sure
1620 * next_to_use != next_to_clean
1622 for (i = 0; i < adapter->num_rx_queues; i++) {
1623 struct igb_ring *ring = adapter->rx_ring[i];
1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
1632 void igb_power_up_link(struct igb_adapter *adapter)
1634 igb_reset_phy(&adapter->hw);
1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1639 igb_power_up_serdes_link_82575(&adapter->hw);
1641 igb_setup_link(&adapter->hw);
1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
1648 static void igb_power_down_link(struct igb_adapter *adapter)
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1660 static void igb_check_swap_media(struct igb_adapter *adapter)
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1669 /* need to live swap if current media is copper and we have fiber/serdes
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
1727 int igb_up(struct igb_adapter *adapter)
1729 struct e1000_hw *hw = &adapter->hw;
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1735 clear_bit(__IGB_DOWN, &adapter->state);
1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1741 igb_configure_msix(adapter);
1743 igb_assign_vector(adapter->q_vector[0], 0);
1745 /* Clear any pending interrupts. */
1747 igb_irq_enable(adapter);
1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1757 netif_tx_start_all_queues(adapter->netdev);
1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1770 void igb_down(struct igb_adapter *adapter)
1772 struct net_device *netdev = adapter->netdev;
1773 struct e1000_hw *hw = &adapter->hw;
1777 /* signal that we're down so the interrupt handler does not
1778 * reschedule our watchdog timer
1780 set_bit(__IGB_DOWN, &adapter->state);
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1787 netif_carrier_off(netdev);
1788 netif_tx_stop_all_queues(netdev);
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1796 usleep_range(10000, 11000);
1798 igb_irq_disable(adapter);
1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1802 for (i = 0; i < adapter->num_q_vectors; i++) {
1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1812 /* record the stats before reset*/
1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1820 if (!pci_channel_offline(adapter->pdev))
1822 igb_clean_all_tx_rings(adapter);
1823 igb_clean_all_rx_rings(adapter);
1824 #ifdef CONFIG_IGB_DCA
1826 /* since we reset the hardware DCA settings were cleared */
1827 igb_setup_dca(adapter);
1831 void igb_reinit_locked(struct igb_adapter *adapter)
1833 WARN_ON(in_interrupt());
1834 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1835 usleep_range(1000, 2000);
1838 clear_bit(__IGB_RESETTING, &adapter->state);
1841 /** igb_enable_mas - Media Autosense re-enable after swap
1843 * @adapter: adapter struct
1845 static void igb_enable_mas(struct igb_adapter *adapter)
1847 struct e1000_hw *hw = &adapter->hw;
1848 u32 connsw = rd32(E1000_CONNSW);
1850 /* configure for SerDes media detect */
1851 if ((hw->phy.media_type == e1000_media_type_copper) &&
1852 (!(connsw & E1000_CONNSW_SERDESD))) {
1853 connsw |= E1000_CONNSW_ENRGSRC;
1854 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1855 wr32(E1000_CONNSW, connsw);
1860 void igb_reset(struct igb_adapter *adapter)
1862 struct pci_dev *pdev = adapter->pdev;
1863 struct e1000_hw *hw = &adapter->hw;
1864 struct e1000_mac_info *mac = &hw->mac;
1865 struct e1000_fc_info *fc = &hw->fc;
1866 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1868 /* Repartition Pba for greater than 9k mtu
1869 * To take effect CTRL.RST is required.
1871 switch (mac->type) {
1875 pba = rd32(E1000_RXPBS);
1876 pba = igb_rxpbs_adjust_82580(pba);
1879 pba = rd32(E1000_RXPBS);
1880 pba &= E1000_RXPBS_SIZE_MASK_82576;
1886 pba = E1000_PBA_34K;
1890 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1891 (mac->type < e1000_82576)) {
1892 /* adjust PBA for jumbo frames */
1893 wr32(E1000_PBA, pba);
1895 /* To maintain wire speed transmits, the Tx FIFO should be
1896 * large enough to accommodate two full transmit packets,
1897 * rounded up to the next 1KB and expressed in KB. Likewise,
1898 * the Rx FIFO should be large enough to accommodate at least
1899 * one full receive packet and is similarly rounded up and
1902 pba = rd32(E1000_PBA);
1903 /* upper 16 bits has Tx packet buffer allocation size in KB */
1904 tx_space = pba >> 16;
1905 /* lower 16 bits has Rx packet buffer allocation size in KB */
1907 /* the Tx fifo also stores 16 bytes of information about the Tx
1908 * but don't include ethernet FCS because hardware appends it
1910 min_tx_space = (adapter->max_frame_size +
1911 sizeof(union e1000_adv_tx_desc) -
1913 min_tx_space = ALIGN(min_tx_space, 1024);
1914 min_tx_space >>= 10;
1915 /* software strips receive CRC, so leave room for it */
1916 min_rx_space = adapter->max_frame_size;
1917 min_rx_space = ALIGN(min_rx_space, 1024);
1918 min_rx_space >>= 10;
1920 /* If current Tx allocation is less than the min Tx FIFO size,
1921 * and the min Tx FIFO size is less than the current Rx FIFO
1922 * allocation, take space away from current Rx allocation
1924 if (tx_space < min_tx_space &&
1925 ((min_tx_space - tx_space) < pba)) {
1926 pba = pba - (min_tx_space - tx_space);
1928 /* if short on Rx space, Rx wins and must trump Tx
1931 if (pba < min_rx_space)
1934 wr32(E1000_PBA, pba);
1937 /* flow control settings */
1938 /* The high water mark must be low enough to fit one full frame
1939 * (or the size used for early receive) above it in the Rx FIFO.
1940 * Set it to the lower of:
1941 * - 90% of the Rx FIFO size, or
1942 * - the full Rx FIFO size minus one full frame
1944 hwm = min(((pba << 10) * 9 / 10),
1945 ((pba << 10) - 2 * adapter->max_frame_size));
1947 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1948 fc->low_water = fc->high_water - 16;
1949 fc->pause_time = 0xFFFF;
1951 fc->current_mode = fc->requested_mode;
1953 /* disable receive for all VFs and wait one second */
1954 if (adapter->vfs_allocated_count) {
1957 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1958 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1960 /* ping all the active vfs to let them know we are going down */
1961 igb_ping_all_vfs(adapter);
1963 /* disable transmits and receives */
1964 wr32(E1000_VFRE, 0);
1965 wr32(E1000_VFTE, 0);
1968 /* Allow time for pending master requests to run */
1969 hw->mac.ops.reset_hw(hw);
1972 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1973 /* need to resetup here after media swap */
1974 adapter->ei.get_invariants(hw);
1975 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1977 if ((mac->type == e1000_82575) &&
1978 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1979 igb_enable_mas(adapter);
1981 if (hw->mac.ops.init_hw(hw))
1982 dev_err(&pdev->dev, "Hardware Error\n");
1984 /* Flow control settings reset on hardware reset, so guarantee flow
1985 * control is off when forcing speed.
1987 if (!hw->mac.autoneg)
1988 igb_force_mac_fc(hw);
1990 igb_init_dmac(adapter, pba);
1991 #ifdef CONFIG_IGB_HWMON
1992 /* Re-initialize the thermal sensor on i350 devices. */
1993 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1994 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1995 /* If present, re-initialize the external thermal sensor
1999 mac->ops.init_thermal_sensor_thresh(hw);
2003 /* Re-establish EEE setting */
2004 if (hw->phy.media_type == e1000_media_type_copper) {
2005 switch (mac->type) {
2009 igb_set_eee_i350(hw, true, true);
2012 igb_set_eee_i354(hw, true, true);
2018 if (!netif_running(adapter->netdev))
2019 igb_power_down_link(adapter);
2021 igb_update_mng_vlan(adapter);
2023 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2024 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2026 /* Re-enable PTP, where applicable. */
2027 igb_ptp_reset(adapter);
2029 igb_get_phy_info(hw);
2032 static netdev_features_t igb_fix_features(struct net_device *netdev,
2033 netdev_features_t features)
2035 /* Since there is no support for separate Rx/Tx vlan accel
2036 * enable/disable make sure Tx flag is always in same state as Rx.
2038 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2039 features |= NETIF_F_HW_VLAN_CTAG_TX;
2041 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2046 static int igb_set_features(struct net_device *netdev,
2047 netdev_features_t features)
2049 netdev_features_t changed = netdev->features ^ features;
2050 struct igb_adapter *adapter = netdev_priv(netdev);
2052 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2053 igb_vlan_mode(netdev, features);
2055 if (!(changed & NETIF_F_RXALL))
2058 netdev->features = features;
2060 if (netif_running(netdev))
2061 igb_reinit_locked(adapter);
2068 static const struct net_device_ops igb_netdev_ops = {
2069 .ndo_open = igb_open,
2070 .ndo_stop = igb_close,
2071 .ndo_start_xmit = igb_xmit_frame,
2072 .ndo_get_stats64 = igb_get_stats64,
2073 .ndo_set_rx_mode = igb_set_rx_mode,
2074 .ndo_set_mac_address = igb_set_mac,
2075 .ndo_change_mtu = igb_change_mtu,
2076 .ndo_do_ioctl = igb_ioctl,
2077 .ndo_tx_timeout = igb_tx_timeout,
2078 .ndo_validate_addr = eth_validate_addr,
2079 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2080 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2081 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2082 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2083 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2084 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2085 .ndo_get_vf_config = igb_ndo_get_vf_config,
2086 #ifdef CONFIG_NET_POLL_CONTROLLER
2087 .ndo_poll_controller = igb_netpoll,
2089 .ndo_fix_features = igb_fix_features,
2090 .ndo_set_features = igb_set_features,
2091 .ndo_features_check = passthru_features_check,
2095 * igb_set_fw_version - Configure version string for ethtool
2096 * @adapter: adapter struct
2098 void igb_set_fw_version(struct igb_adapter *adapter)
2100 struct e1000_hw *hw = &adapter->hw;
2101 struct e1000_fw_version fw;
2103 igb_get_fw_version(hw, &fw);
2105 switch (hw->mac.type) {
2108 if (!(igb_get_flash_presence_i210(hw))) {
2109 snprintf(adapter->fw_version,
2110 sizeof(adapter->fw_version),
2112 fw.invm_major, fw.invm_minor,
2118 /* if option is rom valid, display its version too */
2120 snprintf(adapter->fw_version,
2121 sizeof(adapter->fw_version),
2122 "%d.%d, 0x%08x, %d.%d.%d",
2123 fw.eep_major, fw.eep_minor, fw.etrack_id,
2124 fw.or_major, fw.or_build, fw.or_patch);
2126 } else if (fw.etrack_id != 0X0000) {
2127 snprintf(adapter->fw_version,
2128 sizeof(adapter->fw_version),
2130 fw.eep_major, fw.eep_minor, fw.etrack_id);
2132 snprintf(adapter->fw_version,
2133 sizeof(adapter->fw_version),
2135 fw.eep_major, fw.eep_minor, fw.eep_build);
2142 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2144 * @adapter: adapter struct
2146 static void igb_init_mas(struct igb_adapter *adapter)
2148 struct e1000_hw *hw = &adapter->hw;
2151 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2152 switch (hw->bus.func) {
2154 if (eeprom_data & IGB_MAS_ENABLE_0) {
2155 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2156 netdev_info(adapter->netdev,
2157 "MAS: Enabling Media Autosense for port %d\n",
2162 if (eeprom_data & IGB_MAS_ENABLE_1) {
2163 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2164 netdev_info(adapter->netdev,
2165 "MAS: Enabling Media Autosense for port %d\n",
2170 if (eeprom_data & IGB_MAS_ENABLE_2) {
2171 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2172 netdev_info(adapter->netdev,
2173 "MAS: Enabling Media Autosense for port %d\n",
2178 if (eeprom_data & IGB_MAS_ENABLE_3) {
2179 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2180 netdev_info(adapter->netdev,
2181 "MAS: Enabling Media Autosense for port %d\n",
2186 /* Shouldn't get here */
2187 netdev_err(adapter->netdev,
2188 "MAS: Invalid port configuration, returning\n");
2194 * igb_init_i2c - Init I2C interface
2195 * @adapter: pointer to adapter structure
2197 static s32 igb_init_i2c(struct igb_adapter *adapter)
2201 /* I2C interface supported on i350 devices */
2202 if (adapter->hw.mac.type != e1000_i350)
2205 /* Initialize the i2c bus which is controlled by the registers.
2206 * This bus will use the i2c_algo_bit structue that implements
2207 * the protocol through toggling of the 4 bits in the register.
2209 adapter->i2c_adap.owner = THIS_MODULE;
2210 adapter->i2c_algo = igb_i2c_algo;
2211 adapter->i2c_algo.data = adapter;
2212 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2213 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2214 strlcpy(adapter->i2c_adap.name, "igb BB",
2215 sizeof(adapter->i2c_adap.name));
2216 status = i2c_bit_add_bus(&adapter->i2c_adap);
2221 * igb_probe - Device Initialization Routine
2222 * @pdev: PCI device information struct
2223 * @ent: entry in igb_pci_tbl
2225 * Returns 0 on success, negative on failure
2227 * igb_probe initializes an adapter identified by a pci_dev structure.
2228 * The OS initialization, configuring of the adapter private structure,
2229 * and a hardware reset occur.
2231 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2233 struct net_device *netdev;
2234 struct igb_adapter *adapter;
2235 struct e1000_hw *hw;
2236 u16 eeprom_data = 0;
2238 static int global_quad_port_a; /* global quad port a indication */
2239 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2240 int err, pci_using_dac;
2241 u8 part_str[E1000_PBANUM_LENGTH];
2243 /* Catch broken hardware that put the wrong VF device ID in
2244 * the PCIe SR-IOV capability.
2246 if (pdev->is_virtfn) {
2247 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2248 pci_name(pdev), pdev->vendor, pdev->device);
2252 err = pci_enable_device_mem(pdev);
2257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2264 "No usable DMA configuration, aborting\n");
2269 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2275 pci_enable_pcie_error_reporting(pdev);
2277 pci_set_master(pdev);
2278 pci_save_state(pdev);
2281 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2284 goto err_alloc_etherdev;
2286 SET_NETDEV_DEV(netdev, &pdev->dev);
2288 pci_set_drvdata(pdev, netdev);
2289 adapter = netdev_priv(netdev);
2290 adapter->netdev = netdev;
2291 adapter->pdev = pdev;
2294 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2297 adapter->io_addr = pci_iomap(pdev, 0, 0);
2298 if (!adapter->io_addr)
2300 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2301 hw->hw_addr = adapter->io_addr;
2303 netdev->netdev_ops = &igb_netdev_ops;
2304 igb_set_ethtool_ops(netdev);
2305 netdev->watchdog_timeo = 5 * HZ;
2307 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2309 netdev->mem_start = pci_resource_start(pdev, 0);
2310 netdev->mem_end = pci_resource_end(pdev, 0);
2312 /* PCI config space info */
2313 hw->vendor_id = pdev->vendor;
2314 hw->device_id = pdev->device;
2315 hw->revision_id = pdev->revision;
2316 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2317 hw->subsystem_device_id = pdev->subsystem_device;
2319 /* Copy the default MAC, PHY and NVM function pointers */
2320 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2321 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2322 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2323 /* Initialize skew-specific constants */
2324 err = ei->get_invariants(hw);
2328 /* setup the private structure */
2329 err = igb_sw_init(adapter);
2333 igb_get_bus_info_pcie(hw);
2335 hw->phy.autoneg_wait_to_complete = false;
2337 /* Copper options */
2338 if (hw->phy.media_type == e1000_media_type_copper) {
2339 hw->phy.mdix = AUTO_ALL_MODES;
2340 hw->phy.disable_polarity_correction = false;
2341 hw->phy.ms_type = e1000_ms_hw_default;
2344 if (igb_check_reset_block(hw))
2345 dev_info(&pdev->dev,
2346 "PHY reset is blocked due to SOL/IDER session.\n");
2348 /* features is initialized to 0 in allocation, it might have bits
2349 * set by igb_sw_init so we should use an or instead of an
2352 netdev->features |= NETIF_F_SG |
2359 NETIF_F_HW_VLAN_CTAG_RX |
2360 NETIF_F_HW_VLAN_CTAG_TX;
2362 /* copy netdev features into list of user selectable features */
2363 netdev->hw_features |= netdev->features;
2364 netdev->hw_features |= NETIF_F_RXALL;
2366 /* set this bit last since it cannot be part of hw_features */
2367 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2369 netdev->vlan_features |= NETIF_F_TSO |
2375 netdev->priv_flags |= IFF_SUPP_NOFCS;
2377 if (pci_using_dac) {
2378 netdev->features |= NETIF_F_HIGHDMA;
2379 netdev->vlan_features |= NETIF_F_HIGHDMA;
2382 if (hw->mac.type >= e1000_82576) {
2383 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2384 netdev->features |= NETIF_F_SCTP_CSUM;
2387 netdev->priv_flags |= IFF_UNICAST_FLT;
2389 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2391 /* before reading the NVM, reset the controller to put the device in a
2392 * known good starting state
2394 hw->mac.ops.reset_hw(hw);
2396 /* make sure the NVM is good , i211/i210 parts can have special NVM
2397 * that doesn't contain a checksum
2399 switch (hw->mac.type) {
2402 if (igb_get_flash_presence_i210(hw)) {
2403 if (hw->nvm.ops.validate(hw) < 0) {
2405 "The NVM Checksum Is Not Valid\n");
2412 if (hw->nvm.ops.validate(hw) < 0) {
2413 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2420 /* copy the MAC address out of the NVM */
2421 if (hw->mac.ops.read_mac_addr(hw))
2422 dev_err(&pdev->dev, "NVM Read Error\n");
2424 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2426 if (!is_valid_ether_addr(netdev->dev_addr)) {
2427 dev_err(&pdev->dev, "Invalid MAC Address\n");
2432 /* get firmware version for ethtool -i */
2433 igb_set_fw_version(adapter);
2435 /* configure RXPBSIZE and TXPBSIZE */
2436 if (hw->mac.type == e1000_i210) {
2437 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2438 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2441 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2442 (unsigned long) adapter);
2443 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2444 (unsigned long) adapter);
2446 INIT_WORK(&adapter->reset_task, igb_reset_task);
2447 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2449 /* Initialize link properties that are user-changeable */
2450 adapter->fc_autoneg = true;
2451 hw->mac.autoneg = true;
2452 hw->phy.autoneg_advertised = 0x2f;
2454 hw->fc.requested_mode = e1000_fc_default;
2455 hw->fc.current_mode = e1000_fc_default;
2457 igb_validate_mdi_setting(hw);
2459 /* By default, support wake on port A */
2460 if (hw->bus.func == 0)
2461 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2463 /* Check the NVM for wake support on non-port A ports */
2464 if (hw->mac.type >= e1000_82580)
2465 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2466 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2468 else if (hw->bus.func == 1)
2469 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2471 if (eeprom_data & IGB_EEPROM_APME)
2472 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2474 /* now that we have the eeprom settings, apply the special cases where
2475 * the eeprom may be wrong or the board simply won't support wake on
2476 * lan on a particular port
2478 switch (pdev->device) {
2479 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2480 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2482 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2483 case E1000_DEV_ID_82576_FIBER:
2484 case E1000_DEV_ID_82576_SERDES:
2485 /* Wake events only supported on port A for dual fiber
2486 * regardless of eeprom setting
2488 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2489 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2491 case E1000_DEV_ID_82576_QUAD_COPPER:
2492 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2493 /* if quad port adapter, disable WoL on all but port A */
2494 if (global_quad_port_a != 0)
2495 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2497 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2498 /* Reset for multiple quad port adapters */
2499 if (++global_quad_port_a == 4)
2500 global_quad_port_a = 0;
2503 /* If the device can't wake, don't set software support */
2504 if (!device_can_wakeup(&adapter->pdev->dev))
2505 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2508 /* initialize the wol settings based on the eeprom settings */
2509 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2510 adapter->wol |= E1000_WUFC_MAG;
2512 /* Some vendors want WoL disabled by default, but still supported */
2513 if ((hw->mac.type == e1000_i350) &&
2514 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2515 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2519 device_set_wakeup_enable(&adapter->pdev->dev,
2520 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2522 /* reset the hardware with the new settings */
2525 /* Init the I2C interface */
2526 err = igb_init_i2c(adapter);
2528 dev_err(&pdev->dev, "failed to init i2c interface\n");
2532 /* let the f/w know that the h/w is now under the control of the
2535 igb_get_hw_control(adapter);
2537 strcpy(netdev->name, "eth%d");
2538 err = register_netdev(netdev);
2542 /* carrier off reporting is important to ethtool even BEFORE open */
2543 netif_carrier_off(netdev);
2545 #ifdef CONFIG_IGB_DCA
2546 if (dca_add_requester(&pdev->dev) == 0) {
2547 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2548 dev_info(&pdev->dev, "DCA enabled\n");
2549 igb_setup_dca(adapter);
2553 #ifdef CONFIG_IGB_HWMON
2554 /* Initialize the thermal sensor on i350 devices. */
2555 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2558 /* Read the NVM to determine if this i350 device supports an
2559 * external thermal sensor.
2561 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2562 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2563 adapter->ets = true;
2565 adapter->ets = false;
2566 if (igb_sysfs_init(adapter))
2568 "failed to allocate sysfs resources\n");
2570 adapter->ets = false;
2573 /* Check if Media Autosense is enabled */
2575 if (hw->dev_spec._82575.mas_capable)
2576 igb_init_mas(adapter);
2578 /* do hw tstamp init after resetting */
2579 igb_ptp_init(adapter);
2581 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2582 /* print bus type/speed/width info, not applicable to i354 */
2583 if (hw->mac.type != e1000_i354) {
2584 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2586 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2587 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2589 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2591 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2593 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2594 "Width x1" : "unknown"), netdev->dev_addr);
2597 if ((hw->mac.type >= e1000_i210 ||
2598 igb_get_flash_presence_i210(hw))) {
2599 ret_val = igb_read_part_string(hw, part_str,
2600 E1000_PBANUM_LENGTH);
2602 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2606 strcpy(part_str, "Unknown");
2607 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2608 dev_info(&pdev->dev,
2609 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2610 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2611 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2612 adapter->num_rx_queues, adapter->num_tx_queues);
2613 if (hw->phy.media_type == e1000_media_type_copper) {
2614 switch (hw->mac.type) {
2618 /* Enable EEE for internal copper PHY devices */
2619 err = igb_set_eee_i350(hw, true, true);
2621 (!hw->dev_spec._82575.eee_disable)) {
2622 adapter->eee_advert =
2623 MDIO_EEE_100TX | MDIO_EEE_1000T;
2624 adapter->flags |= IGB_FLAG_EEE;
2628 if ((rd32(E1000_CTRL_EXT) &
2629 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2630 err = igb_set_eee_i354(hw, true, true);
2632 (!hw->dev_spec._82575.eee_disable)) {
2633 adapter->eee_advert =
2634 MDIO_EEE_100TX | MDIO_EEE_1000T;
2635 adapter->flags |= IGB_FLAG_EEE;
2643 pm_runtime_put_noidle(&pdev->dev);
2647 igb_release_hw_control(adapter);
2648 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2650 if (!igb_check_reset_block(hw))
2653 if (hw->flash_address)
2654 iounmap(hw->flash_address);
2656 kfree(adapter->shadow_vfta);
2657 igb_clear_interrupt_scheme(adapter);
2658 #ifdef CONFIG_PCI_IOV
2659 igb_disable_sriov(pdev);
2661 pci_iounmap(pdev, adapter->io_addr);
2663 free_netdev(netdev);
2665 pci_release_selected_regions(pdev,
2666 pci_select_bars(pdev, IORESOURCE_MEM));
2669 pci_disable_device(pdev);
2673 #ifdef CONFIG_PCI_IOV
2674 static int igb_disable_sriov(struct pci_dev *pdev)
2676 struct net_device *netdev = pci_get_drvdata(pdev);
2677 struct igb_adapter *adapter = netdev_priv(netdev);
2678 struct e1000_hw *hw = &adapter->hw;
2680 /* reclaim resources allocated to VFs */
2681 if (adapter->vf_data) {
2682 /* disable iov and allow time for transactions to clear */
2683 if (pci_vfs_assigned(pdev)) {
2684 dev_warn(&pdev->dev,
2685 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2688 pci_disable_sriov(pdev);
2692 kfree(adapter->vf_data);
2693 adapter->vf_data = NULL;
2694 adapter->vfs_allocated_count = 0;
2695 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2698 dev_info(&pdev->dev, "IOV Disabled\n");
2700 /* Re-enable DMA Coalescing flag since IOV is turned off */
2701 adapter->flags |= IGB_FLAG_DMAC;
2707 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2709 struct net_device *netdev = pci_get_drvdata(pdev);
2710 struct igb_adapter *adapter = netdev_priv(netdev);
2711 int old_vfs = pci_num_vf(pdev);
2715 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2723 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2725 adapter->vfs_allocated_count = old_vfs;
2727 adapter->vfs_allocated_count = num_vfs;
2729 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2730 sizeof(struct vf_data_storage), GFP_KERNEL);
2732 /* if allocation failed then we do not support SR-IOV */
2733 if (!adapter->vf_data) {
2734 adapter->vfs_allocated_count = 0;
2736 "Unable to allocate memory for VF Data Storage\n");
2741 /* only call pci_enable_sriov() if no VFs are allocated already */
2743 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2747 dev_info(&pdev->dev, "%d VFs allocated\n",
2748 adapter->vfs_allocated_count);
2749 for (i = 0; i < adapter->vfs_allocated_count; i++)
2750 igb_vf_configure(adapter, i);
2752 /* DMA Coalescing is not supported in IOV mode. */
2753 adapter->flags &= ~IGB_FLAG_DMAC;
2757 kfree(adapter->vf_data);
2758 adapter->vf_data = NULL;
2759 adapter->vfs_allocated_count = 0;
2766 * igb_remove_i2c - Cleanup I2C interface
2767 * @adapter: pointer to adapter structure
2769 static void igb_remove_i2c(struct igb_adapter *adapter)
2771 /* free the adapter bus structure */
2772 i2c_del_adapter(&adapter->i2c_adap);
2776 * igb_remove - Device Removal Routine
2777 * @pdev: PCI device information struct
2779 * igb_remove is called by the PCI subsystem to alert the driver
2780 * that it should release a PCI device. The could be caused by a
2781 * Hot-Plug event, or because the driver is going to be removed from
2784 static void igb_remove(struct pci_dev *pdev)
2786 struct net_device *netdev = pci_get_drvdata(pdev);
2787 struct igb_adapter *adapter = netdev_priv(netdev);
2788 struct e1000_hw *hw = &adapter->hw;
2790 pm_runtime_get_noresume(&pdev->dev);
2791 #ifdef CONFIG_IGB_HWMON
2792 igb_sysfs_exit(adapter);
2794 igb_remove_i2c(adapter);
2795 igb_ptp_stop(adapter);
2796 /* The watchdog timer may be rescheduled, so explicitly
2797 * disable watchdog from being rescheduled.
2799 set_bit(__IGB_DOWN, &adapter->state);
2800 del_timer_sync(&adapter->watchdog_timer);
2801 del_timer_sync(&adapter->phy_info_timer);
2803 cancel_work_sync(&adapter->reset_task);
2804 cancel_work_sync(&adapter->watchdog_task);
2806 #ifdef CONFIG_IGB_DCA
2807 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2808 dev_info(&pdev->dev, "DCA disabled\n");
2809 dca_remove_requester(&pdev->dev);
2810 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2811 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2815 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2816 * would have already happened in close and is redundant.
2818 igb_release_hw_control(adapter);
2820 #ifdef CONFIG_PCI_IOV
2821 igb_disable_sriov(pdev);
2824 unregister_netdev(netdev);
2826 igb_clear_interrupt_scheme(adapter);
2828 pci_iounmap(pdev, adapter->io_addr);
2829 if (hw->flash_address)
2830 iounmap(hw->flash_address);
2831 pci_release_selected_regions(pdev,
2832 pci_select_bars(pdev, IORESOURCE_MEM));
2834 kfree(adapter->shadow_vfta);
2835 free_netdev(netdev);
2837 pci_disable_pcie_error_reporting(pdev);
2839 pci_disable_device(pdev);
2843 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2844 * @adapter: board private structure to initialize
2846 * This function initializes the vf specific data storage and then attempts to
2847 * allocate the VFs. The reason for ordering it this way is because it is much
2848 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2849 * the memory for the VFs.
2851 static void igb_probe_vfs(struct igb_adapter *adapter)
2853 #ifdef CONFIG_PCI_IOV
2854 struct pci_dev *pdev = adapter->pdev;
2855 struct e1000_hw *hw = &adapter->hw;
2857 /* Virtualization features not supported on i210 family. */
2858 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2861 /* Of the below we really only want the effect of getting
2862 * IGB_FLAG_HAS_MSIX set (if available), without which
2863 * igb_enable_sriov() has no effect.
2865 igb_set_interrupt_capability(adapter, true);
2866 igb_reset_interrupt_capability(adapter);
2868 pci_sriov_set_totalvfs(pdev, 7);
2869 igb_enable_sriov(pdev, max_vfs);
2871 #endif /* CONFIG_PCI_IOV */
2874 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2876 struct e1000_hw *hw = &adapter->hw;
2879 /* Determine the maximum number of RSS queues supported. */
2880 switch (hw->mac.type) {
2882 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2886 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2889 /* I350 cannot do RSS and SR-IOV at the same time */
2890 if (!!adapter->vfs_allocated_count) {
2896 if (!!adapter->vfs_allocated_count) {
2904 max_rss_queues = IGB_MAX_RX_QUEUES;
2908 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2910 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2913 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2914 const u32 max_rss_queues)
2916 struct e1000_hw *hw = &adapter->hw;
2918 /* Determine if we need to pair queues. */
2919 switch (hw->mac.type) {
2922 /* Device supports enough interrupts without queue pairing. */
2925 /* If VFs are going to be allocated with RSS queues then we
2926 * should pair the queues in order to conserve interrupts due
2927 * to limited supply.
2929 if ((adapter->rss_queues > 1) &&
2930 (adapter->vfs_allocated_count > 6))
2931 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2938 /* If rss_queues > half of max_rss_queues, pair the queues in
2939 * order to conserve interrupts due to limited supply.
2941 if (adapter->rss_queues > (max_rss_queues / 2))
2942 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2948 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2949 * @adapter: board private structure to initialize
2951 * igb_sw_init initializes the Adapter private data structure.
2952 * Fields are initialized based on PCI device information and
2953 * OS network device settings (MTU size).
2955 static int igb_sw_init(struct igb_adapter *adapter)
2957 struct e1000_hw *hw = &adapter->hw;
2958 struct net_device *netdev = adapter->netdev;
2959 struct pci_dev *pdev = adapter->pdev;
2961 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2963 /* set default ring sizes */
2964 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2965 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2967 /* set default ITR values */
2968 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2969 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2971 /* set default work limits */
2972 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2974 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2976 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2978 spin_lock_init(&adapter->stats64_lock);
2979 #ifdef CONFIG_PCI_IOV
2980 switch (hw->mac.type) {
2984 dev_warn(&pdev->dev,
2985 "Maximum of 7 VFs per PF, using max\n");
2986 max_vfs = adapter->vfs_allocated_count = 7;
2988 adapter->vfs_allocated_count = max_vfs;
2989 if (adapter->vfs_allocated_count)
2990 dev_warn(&pdev->dev,
2991 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2996 #endif /* CONFIG_PCI_IOV */
2998 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
2999 adapter->flags |= IGB_FLAG_HAS_MSIX;
3001 igb_probe_vfs(adapter);
3003 igb_init_queue_configuration(adapter);
3005 /* Setup and initialize a copy of the hw vlan table array */
3006 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3009 /* This call may decrease the number of queues */
3010 if (igb_init_interrupt_scheme(adapter, true)) {
3011 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3015 /* Explicitly disable IRQ since the NIC can be in any state. */
3016 igb_irq_disable(adapter);
3018 if (hw->mac.type >= e1000_i350)
3019 adapter->flags &= ~IGB_FLAG_DMAC;
3021 set_bit(__IGB_DOWN, &adapter->state);
3026 * igb_open - Called when a network interface is made active
3027 * @netdev: network interface device structure
3029 * Returns 0 on success, negative value on failure
3031 * The open entry point is called when a network interface is made
3032 * active by the system (IFF_UP). At this point all resources needed
3033 * for transmit and receive operations are allocated, the interrupt
3034 * handler is registered with the OS, the watchdog timer is started,
3035 * and the stack is notified that the interface is ready.
3037 static int __igb_open(struct net_device *netdev, bool resuming)
3039 struct igb_adapter *adapter = netdev_priv(netdev);
3040 struct e1000_hw *hw = &adapter->hw;
3041 struct pci_dev *pdev = adapter->pdev;
3045 /* disallow open during test */
3046 if (test_bit(__IGB_TESTING, &adapter->state)) {
3052 pm_runtime_get_sync(&pdev->dev);
3054 netif_carrier_off(netdev);
3056 /* allocate transmit descriptors */
3057 err = igb_setup_all_tx_resources(adapter);
3061 /* allocate receive descriptors */
3062 err = igb_setup_all_rx_resources(adapter);
3066 igb_power_up_link(adapter);
3068 /* before we allocate an interrupt, we must be ready to handle it.
3069 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3070 * as soon as we call pci_request_irq, so we have to setup our
3071 * clean_rx handler before we do so.
3073 igb_configure(adapter);
3075 err = igb_request_irq(adapter);
3079 /* Notify the stack of the actual queue counts. */
3080 err = netif_set_real_num_tx_queues(adapter->netdev,
3081 adapter->num_tx_queues);
3083 goto err_set_queues;
3085 err = netif_set_real_num_rx_queues(adapter->netdev,
3086 adapter->num_rx_queues);
3088 goto err_set_queues;
3090 /* From here on the code is the same as igb_up() */
3091 clear_bit(__IGB_DOWN, &adapter->state);
3093 for (i = 0; i < adapter->num_q_vectors; i++)
3094 napi_enable(&(adapter->q_vector[i]->napi));
3096 /* Clear any pending interrupts. */
3099 igb_irq_enable(adapter);
3101 /* notify VFs that reset has been completed */
3102 if (adapter->vfs_allocated_count) {
3103 u32 reg_data = rd32(E1000_CTRL_EXT);
3105 reg_data |= E1000_CTRL_EXT_PFRSTD;
3106 wr32(E1000_CTRL_EXT, reg_data);
3109 netif_tx_start_all_queues(netdev);
3112 pm_runtime_put(&pdev->dev);
3114 /* start the watchdog. */
3115 hw->mac.get_link_status = 1;
3116 schedule_work(&adapter->watchdog_task);
3121 igb_free_irq(adapter);
3123 igb_release_hw_control(adapter);
3124 igb_power_down_link(adapter);
3125 igb_free_all_rx_resources(adapter);
3127 igb_free_all_tx_resources(adapter);
3131 pm_runtime_put(&pdev->dev);
3136 static int igb_open(struct net_device *netdev)
3138 return __igb_open(netdev, false);
3142 * igb_close - Disables a network interface
3143 * @netdev: network interface device structure
3145 * Returns 0, this is not allowed to fail
3147 * The close entry point is called when an interface is de-activated
3148 * by the OS. The hardware is still under the driver's control, but
3149 * needs to be disabled. A global MAC reset is issued to stop the
3150 * hardware, and all transmit and receive resources are freed.
3152 static int __igb_close(struct net_device *netdev, bool suspending)
3154 struct igb_adapter *adapter = netdev_priv(netdev);
3155 struct pci_dev *pdev = adapter->pdev;
3157 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3160 pm_runtime_get_sync(&pdev->dev);
3163 igb_free_irq(adapter);
3165 igb_free_all_tx_resources(adapter);
3166 igb_free_all_rx_resources(adapter);
3169 pm_runtime_put_sync(&pdev->dev);
3173 static int igb_close(struct net_device *netdev)
3175 return __igb_close(netdev, false);
3179 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3180 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3182 * Return 0 on success, negative on failure
3184 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3186 struct device *dev = tx_ring->dev;
3189 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3191 tx_ring->tx_buffer_info = vzalloc(size);
3192 if (!tx_ring->tx_buffer_info)
3195 /* round up to nearest 4K */
3196 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3197 tx_ring->size = ALIGN(tx_ring->size, 4096);
3199 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3200 &tx_ring->dma, GFP_KERNEL);
3204 tx_ring->next_to_use = 0;
3205 tx_ring->next_to_clean = 0;
3210 vfree(tx_ring->tx_buffer_info);
3211 tx_ring->tx_buffer_info = NULL;
3212 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3217 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3218 * (Descriptors) for all queues
3219 * @adapter: board private structure
3221 * Return 0 on success, negative on failure
3223 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3225 struct pci_dev *pdev = adapter->pdev;
3228 for (i = 0; i < adapter->num_tx_queues; i++) {
3229 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3232 "Allocation for Tx Queue %u failed\n", i);
3233 for (i--; i >= 0; i--)
3234 igb_free_tx_resources(adapter->tx_ring[i]);
3243 * igb_setup_tctl - configure the transmit control registers
3244 * @adapter: Board private structure
3246 void igb_setup_tctl(struct igb_adapter *adapter)
3248 struct e1000_hw *hw = &adapter->hw;
3251 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3252 wr32(E1000_TXDCTL(0), 0);
3254 /* Program the Transmit Control Register */
3255 tctl = rd32(E1000_TCTL);
3256 tctl &= ~E1000_TCTL_CT;
3257 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3258 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3260 igb_config_collision_dist(hw);
3262 /* Enable transmits */
3263 tctl |= E1000_TCTL_EN;
3265 wr32(E1000_TCTL, tctl);
3269 * igb_configure_tx_ring - Configure transmit ring after Reset
3270 * @adapter: board private structure
3271 * @ring: tx ring to configure
3273 * Configure a transmit ring after a reset.
3275 void igb_configure_tx_ring(struct igb_adapter *adapter,
3276 struct igb_ring *ring)
3278 struct e1000_hw *hw = &adapter->hw;
3280 u64 tdba = ring->dma;
3281 int reg_idx = ring->reg_idx;
3283 /* disable the queue */
3284 wr32(E1000_TXDCTL(reg_idx), 0);
3288 wr32(E1000_TDLEN(reg_idx),
3289 ring->count * sizeof(union e1000_adv_tx_desc));
3290 wr32(E1000_TDBAL(reg_idx),
3291 tdba & 0x00000000ffffffffULL);
3292 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3294 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3295 wr32(E1000_TDH(reg_idx), 0);
3296 writel(0, ring->tail);
3298 txdctl |= IGB_TX_PTHRESH;
3299 txdctl |= IGB_TX_HTHRESH << 8;
3300 txdctl |= IGB_TX_WTHRESH << 16;
3302 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3303 wr32(E1000_TXDCTL(reg_idx), txdctl);
3307 * igb_configure_tx - Configure transmit Unit after Reset
3308 * @adapter: board private structure
3310 * Configure the Tx unit of the MAC after a reset.
3312 static void igb_configure_tx(struct igb_adapter *adapter)
3316 for (i = 0; i < adapter->num_tx_queues; i++)
3317 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3321 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3322 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3324 * Returns 0 on success, negative on failure
3326 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3328 struct device *dev = rx_ring->dev;
3331 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3333 rx_ring->rx_buffer_info = vzalloc(size);
3334 if (!rx_ring->rx_buffer_info)
3337 /* Round up to nearest 4K */
3338 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3339 rx_ring->size = ALIGN(rx_ring->size, 4096);
3341 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3342 &rx_ring->dma, GFP_KERNEL);
3346 rx_ring->next_to_alloc = 0;
3347 rx_ring->next_to_clean = 0;
3348 rx_ring->next_to_use = 0;
3353 vfree(rx_ring->rx_buffer_info);
3354 rx_ring->rx_buffer_info = NULL;
3355 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3360 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3361 * (Descriptors) for all queues
3362 * @adapter: board private structure
3364 * Return 0 on success, negative on failure
3366 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3368 struct pci_dev *pdev = adapter->pdev;
3371 for (i = 0; i < adapter->num_rx_queues; i++) {
3372 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3375 "Allocation for Rx Queue %u failed\n", i);
3376 for (i--; i >= 0; i--)
3377 igb_free_rx_resources(adapter->rx_ring[i]);
3386 * igb_setup_mrqc - configure the multiple receive queue control registers
3387 * @adapter: Board private structure
3389 static void igb_setup_mrqc(struct igb_adapter *adapter)
3391 struct e1000_hw *hw = &adapter->hw;
3393 u32 j, num_rx_queues;
3396 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3397 for (j = 0; j < 10; j++)
3398 wr32(E1000_RSSRK(j), rss_key[j]);
3400 num_rx_queues = adapter->rss_queues;
3402 switch (hw->mac.type) {
3404 /* 82576 supports 2 RSS queues for SR-IOV */
3405 if (adapter->vfs_allocated_count)
3412 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3413 for (j = 0; j < IGB_RETA_SIZE; j++)
3414 adapter->rss_indir_tbl[j] =
3415 (j * num_rx_queues) / IGB_RETA_SIZE;
3416 adapter->rss_indir_tbl_init = num_rx_queues;
3418 igb_write_rss_indir_tbl(adapter);
3420 /* Disable raw packet checksumming so that RSS hash is placed in
3421 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3422 * offloads as they are enabled by default
3424 rxcsum = rd32(E1000_RXCSUM);
3425 rxcsum |= E1000_RXCSUM_PCSD;
3427 if (adapter->hw.mac.type >= e1000_82576)
3428 /* Enable Receive Checksum Offload for SCTP */
3429 rxcsum |= E1000_RXCSUM_CRCOFL;
3431 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3432 wr32(E1000_RXCSUM, rxcsum);
3434 /* Generate RSS hash based on packet types, TCP/UDP
3435 * port numbers and/or IPv4/v6 src and dst addresses
3437 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3438 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3439 E1000_MRQC_RSS_FIELD_IPV6 |
3440 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3441 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3443 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3444 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3445 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3446 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3448 /* If VMDq is enabled then we set the appropriate mode for that, else
3449 * we default to RSS so that an RSS hash is calculated per packet even
3450 * if we are only using one queue
3452 if (adapter->vfs_allocated_count) {
3453 if (hw->mac.type > e1000_82575) {
3454 /* Set the default pool for the PF's first queue */
3455 u32 vtctl = rd32(E1000_VT_CTL);
3457 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3458 E1000_VT_CTL_DISABLE_DEF_POOL);
3459 vtctl |= adapter->vfs_allocated_count <<
3460 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3461 wr32(E1000_VT_CTL, vtctl);
3463 if (adapter->rss_queues > 1)
3464 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3466 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3468 if (hw->mac.type != e1000_i211)
3469 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3471 igb_vmm_control(adapter);
3473 wr32(E1000_MRQC, mrqc);
3477 * igb_setup_rctl - configure the receive control registers
3478 * @adapter: Board private structure
3480 void igb_setup_rctl(struct igb_adapter *adapter)
3482 struct e1000_hw *hw = &adapter->hw;
3485 rctl = rd32(E1000_RCTL);
3487 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3488 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3490 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3491 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3493 /* enable stripping of CRC. It's unlikely this will break BMC
3494 * redirection as it did with e1000. Newer features require
3495 * that the HW strips the CRC.
3497 rctl |= E1000_RCTL_SECRC;
3499 /* disable store bad packets and clear size bits. */
3500 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3502 /* enable LPE to prevent packets larger than max_frame_size */
3503 rctl |= E1000_RCTL_LPE;
3505 /* disable queue 0 to prevent tail write w/o re-config */
3506 wr32(E1000_RXDCTL(0), 0);
3508 /* Attention!!! For SR-IOV PF driver operations you must enable
3509 * queue drop for all VF and PF queues to prevent head of line blocking
3510 * if an un-trusted VF does not provide descriptors to hardware.
3512 if (adapter->vfs_allocated_count) {
3513 /* set all queue drop enable bits */
3514 wr32(E1000_QDE, ALL_QUEUES);
3517 /* This is useful for sniffing bad packets. */
3518 if (adapter->netdev->features & NETIF_F_RXALL) {
3519 /* UPE and MPE will be handled by normal PROMISC logic
3520 * in e1000e_set_rx_mode
3522 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3523 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3524 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3526 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3527 E1000_RCTL_DPF | /* Allow filtered pause */
3528 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3529 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3530 * and that breaks VLANs.
3534 wr32(E1000_RCTL, rctl);
3537 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3540 struct e1000_hw *hw = &adapter->hw;
3543 /* if it isn't the PF check to see if VFs are enabled and
3544 * increase the size to support vlan tags
3546 if (vfn < adapter->vfs_allocated_count &&
3547 adapter->vf_data[vfn].vlans_enabled)
3548 size += VLAN_TAG_SIZE;
3550 vmolr = rd32(E1000_VMOLR(vfn));
3551 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3552 vmolr |= size | E1000_VMOLR_LPE;
3553 wr32(E1000_VMOLR(vfn), vmolr);
3559 * igb_rlpml_set - set maximum receive packet size
3560 * @adapter: board private structure
3562 * Configure maximum receivable packet size.
3564 static void igb_rlpml_set(struct igb_adapter *adapter)
3566 u32 max_frame_size = adapter->max_frame_size;
3567 struct e1000_hw *hw = &adapter->hw;
3568 u16 pf_id = adapter->vfs_allocated_count;
3571 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3572 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3573 * to our max jumbo frame size, in case we need to enable
3574 * jumbo frames on one of the rings later.
3575 * This will not pass over-length frames into the default
3576 * queue because it's gated by the VMOLR.RLPML.
3578 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3581 wr32(E1000_RLPML, max_frame_size);
3584 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3587 struct e1000_hw *hw = &adapter->hw;
3590 /* This register exists only on 82576 and newer so if we are older then
3591 * we should exit and do nothing
3593 if (hw->mac.type < e1000_82576)
3596 vmolr = rd32(E1000_VMOLR(vfn));
3597 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3598 if (hw->mac.type == e1000_i350) {
3601 dvmolr = rd32(E1000_DVMOLR(vfn));
3602 dvmolr |= E1000_DVMOLR_STRVLAN;
3603 wr32(E1000_DVMOLR(vfn), dvmolr);
3606 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3608 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3610 /* clear all bits that might not be set */
3611 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3613 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3614 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3615 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3618 if (vfn <= adapter->vfs_allocated_count)
3619 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3621 wr32(E1000_VMOLR(vfn), vmolr);
3625 * igb_configure_rx_ring - Configure a receive ring after Reset
3626 * @adapter: board private structure
3627 * @ring: receive ring to be configured
3629 * Configure the Rx unit of the MAC after a reset.
3631 void igb_configure_rx_ring(struct igb_adapter *adapter,
3632 struct igb_ring *ring)
3634 struct e1000_hw *hw = &adapter->hw;
3635 u64 rdba = ring->dma;
3636 int reg_idx = ring->reg_idx;
3637 u32 srrctl = 0, rxdctl = 0;
3639 /* disable the queue */
3640 wr32(E1000_RXDCTL(reg_idx), 0);
3642 /* Set DMA base address registers */
3643 wr32(E1000_RDBAL(reg_idx),
3644 rdba & 0x00000000ffffffffULL);
3645 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3646 wr32(E1000_RDLEN(reg_idx),
3647 ring->count * sizeof(union e1000_adv_rx_desc));
3649 /* initialize head and tail */
3650 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3651 wr32(E1000_RDH(reg_idx), 0);
3652 writel(0, ring->tail);
3654 /* set descriptor configuration */
3655 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3656 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3657 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3658 if (hw->mac.type >= e1000_82580)
3659 srrctl |= E1000_SRRCTL_TIMESTAMP;
3660 /* Only set Drop Enable if we are supporting multiple queues */
3661 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3662 srrctl |= E1000_SRRCTL_DROP_EN;
3664 wr32(E1000_SRRCTL(reg_idx), srrctl);
3666 /* set filtering for VMDQ pools */
3667 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3669 rxdctl |= IGB_RX_PTHRESH;
3670 rxdctl |= IGB_RX_HTHRESH << 8;
3671 rxdctl |= IGB_RX_WTHRESH << 16;
3673 /* enable receive descriptor fetching */
3674 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3675 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3679 * igb_configure_rx - Configure receive Unit after Reset
3680 * @adapter: board private structure
3682 * Configure the Rx unit of the MAC after a reset.
3684 static void igb_configure_rx(struct igb_adapter *adapter)
3688 /* set UTA to appropriate mode */
3689 igb_set_uta(adapter);
3691 /* set the correct pool for the PF default MAC address in entry 0 */
3692 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3693 adapter->vfs_allocated_count);
3695 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3696 * the Base and Length of the Rx Descriptor Ring
3698 for (i = 0; i < adapter->num_rx_queues; i++)
3699 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3703 * igb_free_tx_resources - Free Tx Resources per Queue
3704 * @tx_ring: Tx descriptor ring for a specific queue
3706 * Free all transmit software resources
3708 void igb_free_tx_resources(struct igb_ring *tx_ring)
3710 igb_clean_tx_ring(tx_ring);
3712 vfree(tx_ring->tx_buffer_info);
3713 tx_ring->tx_buffer_info = NULL;
3715 /* if not set, then don't free */
3719 dma_free_coherent(tx_ring->dev, tx_ring->size,
3720 tx_ring->desc, tx_ring->dma);
3722 tx_ring->desc = NULL;
3726 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3727 * @adapter: board private structure
3729 * Free all transmit software resources
3731 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3735 for (i = 0; i < adapter->num_tx_queues; i++)
3736 if (adapter->tx_ring[i])
3737 igb_free_tx_resources(adapter->tx_ring[i]);
3740 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3741 struct igb_tx_buffer *tx_buffer)
3743 if (tx_buffer->skb) {
3744 dev_kfree_skb_any(tx_buffer->skb);
3745 if (dma_unmap_len(tx_buffer, len))
3746 dma_unmap_single(ring->dev,
3747 dma_unmap_addr(tx_buffer, dma),
3748 dma_unmap_len(tx_buffer, len),
3750 } else if (dma_unmap_len(tx_buffer, len)) {
3751 dma_unmap_page(ring->dev,
3752 dma_unmap_addr(tx_buffer, dma),
3753 dma_unmap_len(tx_buffer, len),
3756 tx_buffer->next_to_watch = NULL;
3757 tx_buffer->skb = NULL;
3758 dma_unmap_len_set(tx_buffer, len, 0);
3759 /* buffer_info must be completely set up in the transmit path */
3763 * igb_clean_tx_ring - Free Tx Buffers
3764 * @tx_ring: ring to be cleaned
3766 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3768 struct igb_tx_buffer *buffer_info;
3772 if (!tx_ring->tx_buffer_info)
3774 /* Free all the Tx ring sk_buffs */
3776 for (i = 0; i < tx_ring->count; i++) {
3777 buffer_info = &tx_ring->tx_buffer_info[i];
3778 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3781 netdev_tx_reset_queue(txring_txq(tx_ring));
3783 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3784 memset(tx_ring->tx_buffer_info, 0, size);
3786 /* Zero out the descriptor ring */
3787 memset(tx_ring->desc, 0, tx_ring->size);
3789 tx_ring->next_to_use = 0;
3790 tx_ring->next_to_clean = 0;
3794 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3795 * @adapter: board private structure
3797 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3801 for (i = 0; i < adapter->num_tx_queues; i++)
3802 if (adapter->tx_ring[i])
3803 igb_clean_tx_ring(adapter->tx_ring[i]);
3807 * igb_free_rx_resources - Free Rx Resources
3808 * @rx_ring: ring to clean the resources from
3810 * Free all receive software resources
3812 void igb_free_rx_resources(struct igb_ring *rx_ring)
3814 igb_clean_rx_ring(rx_ring);
3816 vfree(rx_ring->rx_buffer_info);
3817 rx_ring->rx_buffer_info = NULL;
3819 /* if not set, then don't free */
3823 dma_free_coherent(rx_ring->dev, rx_ring->size,
3824 rx_ring->desc, rx_ring->dma);
3826 rx_ring->desc = NULL;
3830 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3831 * @adapter: board private structure
3833 * Free all receive software resources
3835 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3839 for (i = 0; i < adapter->num_rx_queues; i++)
3840 if (adapter->rx_ring[i])
3841 igb_free_rx_resources(adapter->rx_ring[i]);
3845 * igb_clean_rx_ring - Free Rx Buffers per Queue
3846 * @rx_ring: ring to free buffers from
3848 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3854 dev_kfree_skb(rx_ring->skb);
3855 rx_ring->skb = NULL;
3857 if (!rx_ring->rx_buffer_info)
3860 /* Free all the Rx ring sk_buffs */
3861 for (i = 0; i < rx_ring->count; i++) {
3862 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3864 if (!buffer_info->page)
3867 dma_unmap_page(rx_ring->dev,
3871 __free_page(buffer_info->page);
3873 buffer_info->page = NULL;
3876 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3877 memset(rx_ring->rx_buffer_info, 0, size);
3879 /* Zero out the descriptor ring */
3880 memset(rx_ring->desc, 0, rx_ring->size);
3882 rx_ring->next_to_alloc = 0;
3883 rx_ring->next_to_clean = 0;
3884 rx_ring->next_to_use = 0;
3888 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3889 * @adapter: board private structure
3891 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3895 for (i = 0; i < adapter->num_rx_queues; i++)
3896 if (adapter->rx_ring[i])
3897 igb_clean_rx_ring(adapter->rx_ring[i]);
3901 * igb_set_mac - Change the Ethernet Address of the NIC
3902 * @netdev: network interface device structure
3903 * @p: pointer to an address structure
3905 * Returns 0 on success, negative on failure
3907 static int igb_set_mac(struct net_device *netdev, void *p)
3909 struct igb_adapter *adapter = netdev_priv(netdev);
3910 struct e1000_hw *hw = &adapter->hw;
3911 struct sockaddr *addr = p;
3913 if (!is_valid_ether_addr(addr->sa_data))
3914 return -EADDRNOTAVAIL;
3916 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3917 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3919 /* set the correct pool for the new PF MAC address in entry 0 */
3920 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3921 adapter->vfs_allocated_count);
3927 * igb_write_mc_addr_list - write multicast addresses to MTA
3928 * @netdev: network interface device structure
3930 * Writes multicast address list to the MTA hash table.
3931 * Returns: -ENOMEM on failure
3932 * 0 on no addresses written
3933 * X on writing X addresses to MTA
3935 static int igb_write_mc_addr_list(struct net_device *netdev)
3937 struct igb_adapter *adapter = netdev_priv(netdev);
3938 struct e1000_hw *hw = &adapter->hw;
3939 struct netdev_hw_addr *ha;
3943 if (netdev_mc_empty(netdev)) {
3944 /* nothing to program, so clear mc list */
3945 igb_update_mc_addr_list(hw, NULL, 0);
3946 igb_restore_vf_multicasts(adapter);
3950 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3954 /* The shared function expects a packed array of only addresses. */
3956 netdev_for_each_mc_addr(ha, netdev)
3957 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3959 igb_update_mc_addr_list(hw, mta_list, i);
3962 return netdev_mc_count(netdev);
3966 * igb_write_uc_addr_list - write unicast addresses to RAR table
3967 * @netdev: network interface device structure
3969 * Writes unicast address list to the RAR table.
3970 * Returns: -ENOMEM on failure/insufficient address space
3971 * 0 on no addresses written
3972 * X on writing X addresses to the RAR table
3974 static int igb_write_uc_addr_list(struct net_device *netdev)
3976 struct igb_adapter *adapter = netdev_priv(netdev);
3977 struct e1000_hw *hw = &adapter->hw;
3978 unsigned int vfn = adapter->vfs_allocated_count;
3979 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3982 /* return ENOMEM indicating insufficient memory for addresses */
3983 if (netdev_uc_count(netdev) > rar_entries)
3986 if (!netdev_uc_empty(netdev) && rar_entries) {
3987 struct netdev_hw_addr *ha;
3989 netdev_for_each_uc_addr(ha, netdev) {
3992 igb_rar_set_qsel(adapter, ha->addr,
3998 /* write the addresses in reverse order to avoid write combining */
3999 for (; rar_entries > 0 ; rar_entries--) {
4000 wr32(E1000_RAH(rar_entries), 0);
4001 wr32(E1000_RAL(rar_entries), 0);
4009 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4010 * @netdev: network interface device structure
4012 * The set_rx_mode entry point is called whenever the unicast or multicast
4013 * address lists or the network interface flags are updated. This routine is
4014 * responsible for configuring the hardware for proper unicast, multicast,
4015 * promiscuous mode, and all-multi behavior.
4017 static void igb_set_rx_mode(struct net_device *netdev)
4019 struct igb_adapter *adapter = netdev_priv(netdev);
4020 struct e1000_hw *hw = &adapter->hw;
4021 unsigned int vfn = adapter->vfs_allocated_count;
4022 u32 rctl, vmolr = 0;
4025 /* Check for Promiscuous and All Multicast modes */
4026 rctl = rd32(E1000_RCTL);
4028 /* clear the effected bits */
4029 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4031 if (netdev->flags & IFF_PROMISC) {
4032 /* retain VLAN HW filtering if in VT mode */
4033 if (adapter->vfs_allocated_count)
4034 rctl |= E1000_RCTL_VFE;
4035 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4036 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4038 if (netdev->flags & IFF_ALLMULTI) {
4039 rctl |= E1000_RCTL_MPE;
4040 vmolr |= E1000_VMOLR_MPME;
4042 /* Write addresses to the MTA, if the attempt fails
4043 * then we should just turn on promiscuous mode so
4044 * that we can at least receive multicast traffic
4046 count = igb_write_mc_addr_list(netdev);
4048 rctl |= E1000_RCTL_MPE;
4049 vmolr |= E1000_VMOLR_MPME;
4051 vmolr |= E1000_VMOLR_ROMPE;
4054 /* Write addresses to available RAR registers, if there is not
4055 * sufficient space to store all the addresses then enable
4056 * unicast promiscuous mode
4058 count = igb_write_uc_addr_list(netdev);
4060 rctl |= E1000_RCTL_UPE;
4061 vmolr |= E1000_VMOLR_ROPE;
4063 rctl |= E1000_RCTL_VFE;
4065 wr32(E1000_RCTL, rctl);
4067 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4068 * the VMOLR to enable the appropriate modes. Without this workaround
4069 * we will have issues with VLAN tag stripping not being done for frames
4070 * that are only arriving because we are the default pool
4072 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4075 vmolr |= rd32(E1000_VMOLR(vfn)) &
4076 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4077 wr32(E1000_VMOLR(vfn), vmolr);
4078 igb_restore_vf_multicasts(adapter);
4081 static void igb_check_wvbr(struct igb_adapter *adapter)
4083 struct e1000_hw *hw = &adapter->hw;
4086 switch (hw->mac.type) {
4089 wvbr = rd32(E1000_WVBR);
4097 adapter->wvbr |= wvbr;
4100 #define IGB_STAGGERED_QUEUE_OFFSET 8
4102 static void igb_spoof_check(struct igb_adapter *adapter)
4109 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4110 if (adapter->wvbr & (1 << j) ||
4111 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4112 dev_warn(&adapter->pdev->dev,
4113 "Spoof event(s) detected on VF %d\n", j);
4116 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4121 /* Need to wait a few seconds after link up to get diagnostic information from
4124 static void igb_update_phy_info(unsigned long data)
4126 struct igb_adapter *adapter = (struct igb_adapter *) data;
4127 igb_get_phy_info(&adapter->hw);
4131 * igb_has_link - check shared code for link and determine up/down
4132 * @adapter: pointer to driver private info
4134 bool igb_has_link(struct igb_adapter *adapter)
4136 struct e1000_hw *hw = &adapter->hw;
4137 bool link_active = false;
4139 /* get_link_status is set on LSC (link status) interrupt or
4140 * rx sequence error interrupt. get_link_status will stay
4141 * false until the e1000_check_for_link establishes link
4142 * for copper adapters ONLY
4144 switch (hw->phy.media_type) {
4145 case e1000_media_type_copper:
4146 if (!hw->mac.get_link_status)
4148 case e1000_media_type_internal_serdes:
4149 hw->mac.ops.check_for_link(hw);
4150 link_active = !hw->mac.get_link_status;
4153 case e1000_media_type_unknown:
4157 if (((hw->mac.type == e1000_i210) ||
4158 (hw->mac.type == e1000_i211)) &&
4159 (hw->phy.id == I210_I_PHY_ID)) {
4160 if (!netif_carrier_ok(adapter->netdev)) {
4161 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4162 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4163 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4164 adapter->link_check_timeout = jiffies;
4171 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4174 u32 ctrl_ext, thstat;
4176 /* check for thermal sensor event on i350 copper only */
4177 if (hw->mac.type == e1000_i350) {
4178 thstat = rd32(E1000_THSTAT);
4179 ctrl_ext = rd32(E1000_CTRL_EXT);
4181 if ((hw->phy.media_type == e1000_media_type_copper) &&
4182 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4183 ret = !!(thstat & event);
4190 * igb_check_lvmmc - check for malformed packets received
4191 * and indicated in LVMMC register
4192 * @adapter: pointer to adapter
4194 static void igb_check_lvmmc(struct igb_adapter *adapter)
4196 struct e1000_hw *hw = &adapter->hw;
4199 lvmmc = rd32(E1000_LVMMC);
4201 if (unlikely(net_ratelimit())) {
4202 netdev_warn(adapter->netdev,
4203 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4210 * igb_watchdog - Timer Call-back
4211 * @data: pointer to adapter cast into an unsigned long
4213 static void igb_watchdog(unsigned long data)
4215 struct igb_adapter *adapter = (struct igb_adapter *)data;
4216 /* Do the rest outside of interrupt context */
4217 schedule_work(&adapter->watchdog_task);
4220 static void igb_watchdog_task(struct work_struct *work)
4222 struct igb_adapter *adapter = container_of(work,
4225 struct e1000_hw *hw = &adapter->hw;
4226 struct e1000_phy_info *phy = &hw->phy;
4227 struct net_device *netdev = adapter->netdev;
4232 link = igb_has_link(adapter);
4234 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4235 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4236 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4241 /* Force link down if we have fiber to swap to */
4242 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4243 if (hw->phy.media_type == e1000_media_type_copper) {
4244 connsw = rd32(E1000_CONNSW);
4245 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4250 /* Perform a reset if the media type changed. */
4251 if (hw->dev_spec._82575.media_changed) {
4252 hw->dev_spec._82575.media_changed = false;
4253 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4256 /* Cancel scheduled suspend requests. */
4257 pm_runtime_resume(netdev->dev.parent);
4259 if (!netif_carrier_ok(netdev)) {
4262 hw->mac.ops.get_speed_and_duplex(hw,
4263 &adapter->link_speed,
4264 &adapter->link_duplex);
4266 ctrl = rd32(E1000_CTRL);
4267 /* Links status message must follow this format */
4269 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4271 adapter->link_speed,
4272 adapter->link_duplex == FULL_DUPLEX ?
4274 (ctrl & E1000_CTRL_TFCE) &&
4275 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4276 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4277 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4279 /* disable EEE if enabled */
4280 if ((adapter->flags & IGB_FLAG_EEE) &&
4281 (adapter->link_duplex == HALF_DUPLEX)) {
4282 dev_info(&adapter->pdev->dev,
4283 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4284 adapter->hw.dev_spec._82575.eee_disable = true;
4285 adapter->flags &= ~IGB_FLAG_EEE;
4288 /* check if SmartSpeed worked */
4289 igb_check_downshift(hw);
4290 if (phy->speed_downgraded)
4291 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4293 /* check for thermal sensor event */
4294 if (igb_thermal_sensor_event(hw,
4295 E1000_THSTAT_LINK_THROTTLE))
4296 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4298 /* adjust timeout factor according to speed/duplex */
4299 adapter->tx_timeout_factor = 1;
4300 switch (adapter->link_speed) {
4302 adapter->tx_timeout_factor = 14;
4305 /* maybe add some timeout factor ? */
4309 netif_carrier_on(netdev);
4311 igb_ping_all_vfs(adapter);
4312 igb_check_vf_rate_limit(adapter);
4314 /* link state has changed, schedule phy info update */
4315 if (!test_bit(__IGB_DOWN, &adapter->state))
4316 mod_timer(&adapter->phy_info_timer,
4317 round_jiffies(jiffies + 2 * HZ));
4320 if (netif_carrier_ok(netdev)) {
4321 adapter->link_speed = 0;
4322 adapter->link_duplex = 0;
4324 /* check for thermal sensor event */
4325 if (igb_thermal_sensor_event(hw,
4326 E1000_THSTAT_PWR_DOWN)) {
4327 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4330 /* Links status message must follow this format */
4331 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4333 netif_carrier_off(netdev);
4335 igb_ping_all_vfs(adapter);
4337 /* link state has changed, schedule phy info update */
4338 if (!test_bit(__IGB_DOWN, &adapter->state))
4339 mod_timer(&adapter->phy_info_timer,
4340 round_jiffies(jiffies + 2 * HZ));
4342 /* link is down, time to check for alternate media */
4343 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4344 igb_check_swap_media(adapter);
4345 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4346 schedule_work(&adapter->reset_task);
4347 /* return immediately */
4351 pm_schedule_suspend(netdev->dev.parent,
4354 /* also check for alternate media here */
4355 } else if (!netif_carrier_ok(netdev) &&
4356 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4357 igb_check_swap_media(adapter);
4358 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4359 schedule_work(&adapter->reset_task);
4360 /* return immediately */
4366 spin_lock(&adapter->stats64_lock);
4367 igb_update_stats(adapter, &adapter->stats64);
4368 spin_unlock(&adapter->stats64_lock);
4370 for (i = 0; i < adapter->num_tx_queues; i++) {
4371 struct igb_ring *tx_ring = adapter->tx_ring[i];
4372 if (!netif_carrier_ok(netdev)) {
4373 /* We've lost link, so the controller stops DMA,
4374 * but we've got queued Tx work that's never going
4375 * to get done, so reset controller to flush Tx.
4376 * (Do the reset outside of interrupt context).
4378 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4379 adapter->tx_timeout_count++;
4380 schedule_work(&adapter->reset_task);
4381 /* return immediately since reset is imminent */
4386 /* Force detection of hung controller every watchdog period */
4387 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4390 /* Cause software interrupt to ensure Rx ring is cleaned */
4391 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4394 for (i = 0; i < adapter->num_q_vectors; i++)
4395 eics |= adapter->q_vector[i]->eims_value;
4396 wr32(E1000_EICS, eics);
4398 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4401 igb_spoof_check(adapter);
4402 igb_ptp_rx_hang(adapter);
4404 /* Check LVMMC register on i350/i354 only */
4405 if ((adapter->hw.mac.type == e1000_i350) ||
4406 (adapter->hw.mac.type == e1000_i354))
4407 igb_check_lvmmc(adapter);
4409 /* Reset the timer */
4410 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4411 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4412 mod_timer(&adapter->watchdog_timer,
4413 round_jiffies(jiffies + HZ));
4415 mod_timer(&adapter->watchdog_timer,
4416 round_jiffies(jiffies + 2 * HZ));
4420 enum latency_range {
4424 latency_invalid = 255
4428 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4429 * @q_vector: pointer to q_vector
4431 * Stores a new ITR value based on strictly on packet size. This
4432 * algorithm is less sophisticated than that used in igb_update_itr,
4433 * due to the difficulty of synchronizing statistics across multiple
4434 * receive rings. The divisors and thresholds used by this function
4435 * were determined based on theoretical maximum wire speed and testing
4436 * data, in order to minimize response time while increasing bulk
4438 * This functionality is controlled by ethtool's coalescing settings.
4439 * NOTE: This function is called only when operating in a multiqueue
4440 * receive environment.
4442 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4444 int new_val = q_vector->itr_val;
4445 int avg_wire_size = 0;
4446 struct igb_adapter *adapter = q_vector->adapter;
4447 unsigned int packets;
4449 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4450 * ints/sec - ITR timer value of 120 ticks.
4452 if (adapter->link_speed != SPEED_1000) {
4453 new_val = IGB_4K_ITR;
4457 packets = q_vector->rx.total_packets;
4459 avg_wire_size = q_vector->rx.total_bytes / packets;
4461 packets = q_vector->tx.total_packets;
4463 avg_wire_size = max_t(u32, avg_wire_size,
4464 q_vector->tx.total_bytes / packets);
4466 /* if avg_wire_size isn't set no work was done */
4470 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4471 avg_wire_size += 24;
4473 /* Don't starve jumbo frames */
4474 avg_wire_size = min(avg_wire_size, 3000);
4476 /* Give a little boost to mid-size frames */
4477 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4478 new_val = avg_wire_size / 3;
4480 new_val = avg_wire_size / 2;
4482 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4483 if (new_val < IGB_20K_ITR &&
4484 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4485 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4486 new_val = IGB_20K_ITR;
4489 if (new_val != q_vector->itr_val) {
4490 q_vector->itr_val = new_val;
4491 q_vector->set_itr = 1;
4494 q_vector->rx.total_bytes = 0;
4495 q_vector->rx.total_packets = 0;
4496 q_vector->tx.total_bytes = 0;
4497 q_vector->tx.total_packets = 0;
4501 * igb_update_itr - update the dynamic ITR value based on statistics
4502 * @q_vector: pointer to q_vector
4503 * @ring_container: ring info to update the itr for
4505 * Stores a new ITR value based on packets and byte
4506 * counts during the last interrupt. The advantage of per interrupt
4507 * computation is faster updates and more accurate ITR for the current
4508 * traffic pattern. Constants in this function were computed
4509 * based on theoretical maximum wire speed and thresholds were set based
4510 * on testing data as well as attempting to minimize response time
4511 * while increasing bulk throughput.
4512 * This functionality is controlled by ethtool's coalescing settings.
4513 * NOTE: These calculations are only valid when operating in a single-
4514 * queue environment.
4516 static void igb_update_itr(struct igb_q_vector *q_vector,
4517 struct igb_ring_container *ring_container)
4519 unsigned int packets = ring_container->total_packets;
4520 unsigned int bytes = ring_container->total_bytes;
4521 u8 itrval = ring_container->itr;
4523 /* no packets, exit with status unchanged */
4528 case lowest_latency:
4529 /* handle TSO and jumbo frames */
4530 if (bytes/packets > 8000)
4531 itrval = bulk_latency;
4532 else if ((packets < 5) && (bytes > 512))
4533 itrval = low_latency;
4535 case low_latency: /* 50 usec aka 20000 ints/s */
4536 if (bytes > 10000) {
4537 /* this if handles the TSO accounting */
4538 if (bytes/packets > 8000)
4539 itrval = bulk_latency;
4540 else if ((packets < 10) || ((bytes/packets) > 1200))
4541 itrval = bulk_latency;
4542 else if ((packets > 35))
4543 itrval = lowest_latency;
4544 } else if (bytes/packets > 2000) {
4545 itrval = bulk_latency;
4546 } else if (packets <= 2 && bytes < 512) {
4547 itrval = lowest_latency;
4550 case bulk_latency: /* 250 usec aka 4000 ints/s */
4551 if (bytes > 25000) {
4553 itrval = low_latency;
4554 } else if (bytes < 1500) {
4555 itrval = low_latency;
4560 /* clear work counters since we have the values we need */
4561 ring_container->total_bytes = 0;
4562 ring_container->total_packets = 0;
4564 /* write updated itr to ring container */
4565 ring_container->itr = itrval;
4568 static void igb_set_itr(struct igb_q_vector *q_vector)
4570 struct igb_adapter *adapter = q_vector->adapter;
4571 u32 new_itr = q_vector->itr_val;
4574 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4575 if (adapter->link_speed != SPEED_1000) {
4577 new_itr = IGB_4K_ITR;
4581 igb_update_itr(q_vector, &q_vector->tx);
4582 igb_update_itr(q_vector, &q_vector->rx);
4584 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4586 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4587 if (current_itr == lowest_latency &&
4588 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4589 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4590 current_itr = low_latency;
4592 switch (current_itr) {
4593 /* counts and packets in update_itr are dependent on these numbers */
4594 case lowest_latency:
4595 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4598 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4601 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4608 if (new_itr != q_vector->itr_val) {
4609 /* this attempts to bias the interrupt rate towards Bulk
4610 * by adding intermediate steps when interrupt rate is
4613 new_itr = new_itr > q_vector->itr_val ?
4614 max((new_itr * q_vector->itr_val) /
4615 (new_itr + (q_vector->itr_val >> 2)),
4617 /* Don't write the value here; it resets the adapter's
4618 * internal timer, and causes us to delay far longer than
4619 * we should between interrupts. Instead, we write the ITR
4620 * value at the beginning of the next interrupt so the timing
4621 * ends up being correct.
4623 q_vector->itr_val = new_itr;
4624 q_vector->set_itr = 1;
4628 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4629 u32 type_tucmd, u32 mss_l4len_idx)
4631 struct e1000_adv_tx_context_desc *context_desc;
4632 u16 i = tx_ring->next_to_use;
4634 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4637 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4639 /* set bits to identify this as an advanced context descriptor */
4640 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4642 /* For 82575, context index must be unique per ring. */
4643 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4644 mss_l4len_idx |= tx_ring->reg_idx << 4;
4646 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4647 context_desc->seqnum_seed = 0;
4648 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4649 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4652 static int igb_tso(struct igb_ring *tx_ring,
4653 struct igb_tx_buffer *first,
4656 struct sk_buff *skb = first->skb;
4657 u32 vlan_macip_lens, type_tucmd;
4658 u32 mss_l4len_idx, l4len;
4661 if (skb->ip_summed != CHECKSUM_PARTIAL)
4664 if (!skb_is_gso(skb))
4667 err = skb_cow_head(skb, 0);
4671 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4672 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4674 if (first->protocol == htons(ETH_P_IP)) {
4675 struct iphdr *iph = ip_hdr(skb);
4678 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4682 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4683 first->tx_flags |= IGB_TX_FLAGS_TSO |
4686 } else if (skb_is_gso_v6(skb)) {
4687 ipv6_hdr(skb)->payload_len = 0;
4688 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4689 &ipv6_hdr(skb)->daddr,
4691 first->tx_flags |= IGB_TX_FLAGS_TSO |
4695 /* compute header lengths */
4696 l4len = tcp_hdrlen(skb);
4697 *hdr_len = skb_transport_offset(skb) + l4len;
4699 /* update gso size and bytecount with header size */
4700 first->gso_segs = skb_shinfo(skb)->gso_segs;
4701 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4704 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4705 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4707 /* VLAN MACLEN IPLEN */
4708 vlan_macip_lens = skb_network_header_len(skb);
4709 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4710 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4712 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4717 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4719 struct sk_buff *skb = first->skb;
4720 u32 vlan_macip_lens = 0;
4721 u32 mss_l4len_idx = 0;
4724 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4725 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4730 switch (first->protocol) {
4731 case htons(ETH_P_IP):
4732 vlan_macip_lens |= skb_network_header_len(skb);
4733 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4734 l4_hdr = ip_hdr(skb)->protocol;
4736 case htons(ETH_P_IPV6):
4737 vlan_macip_lens |= skb_network_header_len(skb);
4738 l4_hdr = ipv6_hdr(skb)->nexthdr;
4741 if (unlikely(net_ratelimit())) {
4742 dev_warn(tx_ring->dev,
4743 "partial checksum but proto=%x!\n",
4751 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4752 mss_l4len_idx = tcp_hdrlen(skb) <<
4753 E1000_ADVTXD_L4LEN_SHIFT;
4756 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4757 mss_l4len_idx = sizeof(struct sctphdr) <<
4758 E1000_ADVTXD_L4LEN_SHIFT;
4761 mss_l4len_idx = sizeof(struct udphdr) <<
4762 E1000_ADVTXD_L4LEN_SHIFT;
4765 if (unlikely(net_ratelimit())) {
4766 dev_warn(tx_ring->dev,
4767 "partial checksum but l4 proto=%x!\n",
4773 /* update TX checksum flag */
4774 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4777 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4778 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4780 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4783 #define IGB_SET_FLAG(_input, _flag, _result) \
4784 ((_flag <= _result) ? \
4785 ((u32)(_input & _flag) * (_result / _flag)) : \
4786 ((u32)(_input & _flag) / (_flag / _result)))
4788 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4790 /* set type for advanced descriptor with frame checksum insertion */
4791 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4792 E1000_ADVTXD_DCMD_DEXT |
4793 E1000_ADVTXD_DCMD_IFCS;
4795 /* set HW vlan bit if vlan is present */
4796 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4797 (E1000_ADVTXD_DCMD_VLE));
4799 /* set segmentation bits for TSO */
4800 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4801 (E1000_ADVTXD_DCMD_TSE));
4803 /* set timestamp bit if present */
4804 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4805 (E1000_ADVTXD_MAC_TSTAMP));
4807 /* insert frame checksum */
4808 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4813 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4814 union e1000_adv_tx_desc *tx_desc,
4815 u32 tx_flags, unsigned int paylen)
4817 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4819 /* 82575 requires a unique index per ring */
4820 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4821 olinfo_status |= tx_ring->reg_idx << 4;
4823 /* insert L4 checksum */
4824 olinfo_status |= IGB_SET_FLAG(tx_flags,
4826 (E1000_TXD_POPTS_TXSM << 8));
4828 /* insert IPv4 checksum */
4829 olinfo_status |= IGB_SET_FLAG(tx_flags,
4831 (E1000_TXD_POPTS_IXSM << 8));
4833 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4836 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4838 struct net_device *netdev = tx_ring->netdev;
4840 netif_stop_subqueue(netdev, tx_ring->queue_index);
4842 /* Herbert's original patch had:
4843 * smp_mb__after_netif_stop_queue();
4844 * but since that doesn't exist yet, just open code it.
4848 /* We need to check again in a case another CPU has just
4849 * made room available.
4851 if (igb_desc_unused(tx_ring) < size)
4855 netif_wake_subqueue(netdev, tx_ring->queue_index);
4857 u64_stats_update_begin(&tx_ring->tx_syncp2);
4858 tx_ring->tx_stats.restart_queue2++;
4859 u64_stats_update_end(&tx_ring->tx_syncp2);
4864 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4866 if (igb_desc_unused(tx_ring) >= size)
4868 return __igb_maybe_stop_tx(tx_ring, size);
4871 static void igb_tx_map(struct igb_ring *tx_ring,
4872 struct igb_tx_buffer *first,
4875 struct sk_buff *skb = first->skb;
4876 struct igb_tx_buffer *tx_buffer;
4877 union e1000_adv_tx_desc *tx_desc;
4878 struct skb_frag_struct *frag;
4880 unsigned int data_len, size;
4881 u32 tx_flags = first->tx_flags;
4882 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4883 u16 i = tx_ring->next_to_use;
4885 tx_desc = IGB_TX_DESC(tx_ring, i);
4887 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4889 size = skb_headlen(skb);
4890 data_len = skb->data_len;
4892 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4896 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4897 if (dma_mapping_error(tx_ring->dev, dma))
4900 /* record length, and DMA address */
4901 dma_unmap_len_set(tx_buffer, len, size);
4902 dma_unmap_addr_set(tx_buffer, dma, dma);
4904 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4906 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4907 tx_desc->read.cmd_type_len =
4908 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4912 if (i == tx_ring->count) {
4913 tx_desc = IGB_TX_DESC(tx_ring, 0);
4916 tx_desc->read.olinfo_status = 0;
4918 dma += IGB_MAX_DATA_PER_TXD;
4919 size -= IGB_MAX_DATA_PER_TXD;
4921 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4924 if (likely(!data_len))
4927 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4931 if (i == tx_ring->count) {
4932 tx_desc = IGB_TX_DESC(tx_ring, 0);
4935 tx_desc->read.olinfo_status = 0;
4937 size = skb_frag_size(frag);
4940 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4941 size, DMA_TO_DEVICE);
4943 tx_buffer = &tx_ring->tx_buffer_info[i];
4946 /* write last descriptor with RS and EOP bits */
4947 cmd_type |= size | IGB_TXD_DCMD;
4948 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4950 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4952 /* set the timestamp */
4953 first->time_stamp = jiffies;
4955 /* Force memory writes to complete before letting h/w know there
4956 * are new descriptors to fetch. (Only applicable for weak-ordered
4957 * memory model archs, such as IA-64).
4959 * We also need this memory barrier to make certain all of the
4960 * status bits have been updated before next_to_watch is written.
4964 /* set next_to_watch value indicating a packet is present */
4965 first->next_to_watch = tx_desc;
4968 if (i == tx_ring->count)
4971 tx_ring->next_to_use = i;
4973 /* Make sure there is space in the ring for the next send. */
4974 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4976 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4977 writel(i, tx_ring->tail);
4979 /* we need this if more than one processor can write to our tail
4980 * at a time, it synchronizes IO on IA64/Altix systems
4987 dev_err(tx_ring->dev, "TX DMA map failed\n");
4989 /* clear dma mappings for failed tx_buffer_info map */
4991 tx_buffer = &tx_ring->tx_buffer_info[i];
4992 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4993 if (tx_buffer == first)
5000 tx_ring->next_to_use = i;
5003 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5004 struct igb_ring *tx_ring)
5006 struct igb_tx_buffer *first;
5010 u16 count = TXD_USE_COUNT(skb_headlen(skb));
5011 __be16 protocol = vlan_get_protocol(skb);
5014 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5015 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
5016 * + 2 desc gap to keep tail from touching head,
5017 * + 1 desc for context descriptor,
5018 * otherwise try next time
5020 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5021 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5023 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5024 /* this is a hard error */
5025 return NETDEV_TX_BUSY;
5028 /* record the location of the first descriptor for this packet */
5029 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5031 first->bytecount = skb->len;
5032 first->gso_segs = 1;
5034 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5035 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5037 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5039 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5040 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5042 adapter->ptp_tx_skb = skb_get(skb);
5043 adapter->ptp_tx_start = jiffies;
5044 if (adapter->hw.mac.type == e1000_82576)
5045 schedule_work(&adapter->ptp_tx_work);
5049 skb_tx_timestamp(skb);
5051 if (skb_vlan_tag_present(skb)) {
5052 tx_flags |= IGB_TX_FLAGS_VLAN;
5053 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5056 /* record initial flags and protocol */
5057 first->tx_flags = tx_flags;
5058 first->protocol = protocol;
5060 tso = igb_tso(tx_ring, first, &hdr_len);
5064 igb_tx_csum(tx_ring, first);
5066 igb_tx_map(tx_ring, first, hdr_len);
5068 return NETDEV_TX_OK;
5071 igb_unmap_and_free_tx_resource(tx_ring, first);
5073 return NETDEV_TX_OK;
5076 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5077 struct sk_buff *skb)
5079 unsigned int r_idx = skb->queue_mapping;
5081 if (r_idx >= adapter->num_tx_queues)
5082 r_idx = r_idx % adapter->num_tx_queues;
5084 return adapter->tx_ring[r_idx];
5087 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5088 struct net_device *netdev)
5090 struct igb_adapter *adapter = netdev_priv(netdev);
5092 if (test_bit(__IGB_DOWN, &adapter->state)) {
5093 dev_kfree_skb_any(skb);
5094 return NETDEV_TX_OK;
5097 if (skb->len <= 0) {
5098 dev_kfree_skb_any(skb);
5099 return NETDEV_TX_OK;
5102 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5103 * in order to meet this minimum size requirement.
5105 if (skb_put_padto(skb, 17))
5106 return NETDEV_TX_OK;
5108 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5112 * igb_tx_timeout - Respond to a Tx Hang
5113 * @netdev: network interface device structure
5115 static void igb_tx_timeout(struct net_device *netdev)
5117 struct igb_adapter *adapter = netdev_priv(netdev);
5118 struct e1000_hw *hw = &adapter->hw;
5120 /* Do the reset outside of interrupt context */
5121 adapter->tx_timeout_count++;
5123 if (hw->mac.type >= e1000_82580)
5124 hw->dev_spec._82575.global_device_reset = true;
5126 schedule_work(&adapter->reset_task);
5128 (adapter->eims_enable_mask & ~adapter->eims_other));
5131 static void igb_reset_task(struct work_struct *work)
5133 struct igb_adapter *adapter;
5134 adapter = container_of(work, struct igb_adapter, reset_task);
5137 netdev_err(adapter->netdev, "Reset adapter\n");
5138 igb_reinit_locked(adapter);
5142 * igb_get_stats64 - Get System Network Statistics
5143 * @netdev: network interface device structure
5144 * @stats: rtnl_link_stats64 pointer
5146 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5147 struct rtnl_link_stats64 *stats)
5149 struct igb_adapter *adapter = netdev_priv(netdev);
5151 spin_lock(&adapter->stats64_lock);
5152 igb_update_stats(adapter, &adapter->stats64);
5153 memcpy(stats, &adapter->stats64, sizeof(*stats));
5154 spin_unlock(&adapter->stats64_lock);
5160 * igb_change_mtu - Change the Maximum Transfer Unit
5161 * @netdev: network interface device structure
5162 * @new_mtu: new value for maximum frame size
5164 * Returns 0 on success, negative on failure
5166 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5168 struct igb_adapter *adapter = netdev_priv(netdev);
5169 struct pci_dev *pdev = adapter->pdev;
5170 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5172 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5173 dev_err(&pdev->dev, "Invalid MTU setting\n");
5177 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5178 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5179 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5183 /* adjust max frame to be at least the size of a standard frame */
5184 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5185 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5187 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5188 usleep_range(1000, 2000);
5190 /* igb_down has a dependency on max_frame_size */
5191 adapter->max_frame_size = max_frame;
5193 if (netif_running(netdev))
5196 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5197 netdev->mtu, new_mtu);
5198 netdev->mtu = new_mtu;
5200 if (netif_running(netdev))
5205 clear_bit(__IGB_RESETTING, &adapter->state);
5211 * igb_update_stats - Update the board statistics counters
5212 * @adapter: board private structure
5214 void igb_update_stats(struct igb_adapter *adapter,
5215 struct rtnl_link_stats64 *net_stats)
5217 struct e1000_hw *hw = &adapter->hw;
5218 struct pci_dev *pdev = adapter->pdev;
5223 u64 _bytes, _packets;
5225 /* Prevent stats update while adapter is being reset, or if the pci
5226 * connection is down.
5228 if (adapter->link_speed == 0)
5230 if (pci_channel_offline(pdev))
5237 for (i = 0; i < adapter->num_rx_queues; i++) {
5238 struct igb_ring *ring = adapter->rx_ring[i];
5239 u32 rqdpc = rd32(E1000_RQDPC(i));
5240 if (hw->mac.type >= e1000_i210)
5241 wr32(E1000_RQDPC(i), 0);
5244 ring->rx_stats.drops += rqdpc;
5245 net_stats->rx_fifo_errors += rqdpc;
5249 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5250 _bytes = ring->rx_stats.bytes;
5251 _packets = ring->rx_stats.packets;
5252 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5254 packets += _packets;
5257 net_stats->rx_bytes = bytes;
5258 net_stats->rx_packets = packets;
5262 for (i = 0; i < adapter->num_tx_queues; i++) {
5263 struct igb_ring *ring = adapter->tx_ring[i];
5265 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5266 _bytes = ring->tx_stats.bytes;
5267 _packets = ring->tx_stats.packets;
5268 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5270 packets += _packets;
5272 net_stats->tx_bytes = bytes;
5273 net_stats->tx_packets = packets;
5276 /* read stats registers */
5277 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5278 adapter->stats.gprc += rd32(E1000_GPRC);
5279 adapter->stats.gorc += rd32(E1000_GORCL);
5280 rd32(E1000_GORCH); /* clear GORCL */
5281 adapter->stats.bprc += rd32(E1000_BPRC);
5282 adapter->stats.mprc += rd32(E1000_MPRC);
5283 adapter->stats.roc += rd32(E1000_ROC);
5285 adapter->stats.prc64 += rd32(E1000_PRC64);
5286 adapter->stats.prc127 += rd32(E1000_PRC127);
5287 adapter->stats.prc255 += rd32(E1000_PRC255);
5288 adapter->stats.prc511 += rd32(E1000_PRC511);
5289 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5290 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5291 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5292 adapter->stats.sec += rd32(E1000_SEC);
5294 mpc = rd32(E1000_MPC);
5295 adapter->stats.mpc += mpc;
5296 net_stats->rx_fifo_errors += mpc;
5297 adapter->stats.scc += rd32(E1000_SCC);
5298 adapter->stats.ecol += rd32(E1000_ECOL);
5299 adapter->stats.mcc += rd32(E1000_MCC);
5300 adapter->stats.latecol += rd32(E1000_LATECOL);
5301 adapter->stats.dc += rd32(E1000_DC);
5302 adapter->stats.rlec += rd32(E1000_RLEC);
5303 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5304 adapter->stats.xontxc += rd32(E1000_XONTXC);
5305 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5306 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5307 adapter->stats.fcruc += rd32(E1000_FCRUC);
5308 adapter->stats.gptc += rd32(E1000_GPTC);
5309 adapter->stats.gotc += rd32(E1000_GOTCL);
5310 rd32(E1000_GOTCH); /* clear GOTCL */
5311 adapter->stats.rnbc += rd32(E1000_RNBC);
5312 adapter->stats.ruc += rd32(E1000_RUC);
5313 adapter->stats.rfc += rd32(E1000_RFC);
5314 adapter->stats.rjc += rd32(E1000_RJC);
5315 adapter->stats.tor += rd32(E1000_TORH);
5316 adapter->stats.tot += rd32(E1000_TOTH);
5317 adapter->stats.tpr += rd32(E1000_TPR);
5319 adapter->stats.ptc64 += rd32(E1000_PTC64);
5320 adapter->stats.ptc127 += rd32(E1000_PTC127);
5321 adapter->stats.ptc255 += rd32(E1000_PTC255);
5322 adapter->stats.ptc511 += rd32(E1000_PTC511);
5323 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5324 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5326 adapter->stats.mptc += rd32(E1000_MPTC);
5327 adapter->stats.bptc += rd32(E1000_BPTC);
5329 adapter->stats.tpt += rd32(E1000_TPT);
5330 adapter->stats.colc += rd32(E1000_COLC);
5332 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5333 /* read internal phy specific stats */
5334 reg = rd32(E1000_CTRL_EXT);
5335 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5336 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5338 /* this stat has invalid values on i210/i211 */
5339 if ((hw->mac.type != e1000_i210) &&
5340 (hw->mac.type != e1000_i211))
5341 adapter->stats.tncrs += rd32(E1000_TNCRS);
5344 adapter->stats.tsctc += rd32(E1000_TSCTC);
5345 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5347 adapter->stats.iac += rd32(E1000_IAC);
5348 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5349 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5350 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5351 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5352 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5353 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5354 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5355 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5357 /* Fill out the OS statistics structure */
5358 net_stats->multicast = adapter->stats.mprc;
5359 net_stats->collisions = adapter->stats.colc;
5363 /* RLEC on some newer hardware can be incorrect so build
5364 * our own version based on RUC and ROC
5366 net_stats->rx_errors = adapter->stats.rxerrc +
5367 adapter->stats.crcerrs + adapter->stats.algnerrc +
5368 adapter->stats.ruc + adapter->stats.roc +
5369 adapter->stats.cexterr;
5370 net_stats->rx_length_errors = adapter->stats.ruc +
5372 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5373 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5374 net_stats->rx_missed_errors = adapter->stats.mpc;
5377 net_stats->tx_errors = adapter->stats.ecol +
5378 adapter->stats.latecol;
5379 net_stats->tx_aborted_errors = adapter->stats.ecol;
5380 net_stats->tx_window_errors = adapter->stats.latecol;
5381 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5383 /* Tx Dropped needs to be maintained elsewhere */
5385 /* Management Stats */
5386 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5387 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5388 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5391 reg = rd32(E1000_MANC);
5392 if (reg & E1000_MANC_EN_BMC2OS) {
5393 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5394 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5395 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5396 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5400 static void igb_tsync_interrupt(struct igb_adapter *adapter)
5402 struct e1000_hw *hw = &adapter->hw;
5403 struct ptp_clock_event event;
5404 struct timespec64 ts;
5405 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5407 if (tsicr & TSINTR_SYS_WRAP) {
5408 event.type = PTP_CLOCK_PPS;
5409 if (adapter->ptp_caps.pps)
5410 ptp_clock_event(adapter->ptp_clock, &event);
5412 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5413 ack |= TSINTR_SYS_WRAP;
5416 if (tsicr & E1000_TSICR_TXTS) {
5417 /* retrieve hardware timestamp */
5418 schedule_work(&adapter->ptp_tx_work);
5419 ack |= E1000_TSICR_TXTS;
5422 if (tsicr & TSINTR_TT0) {
5423 spin_lock(&adapter->tmreg_lock);
5424 ts = timespec64_add(adapter->perout[0].start,
5425 adapter->perout[0].period);
5426 /* u32 conversion of tv_sec is safe until y2106 */
5427 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5428 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
5429 tsauxc = rd32(E1000_TSAUXC);
5430 tsauxc |= TSAUXC_EN_TT0;
5431 wr32(E1000_TSAUXC, tsauxc);
5432 adapter->perout[0].start = ts;
5433 spin_unlock(&adapter->tmreg_lock);
5437 if (tsicr & TSINTR_TT1) {
5438 spin_lock(&adapter->tmreg_lock);
5439 ts = timespec64_add(adapter->perout[1].start,
5440 adapter->perout[1].period);
5441 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5442 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
5443 tsauxc = rd32(E1000_TSAUXC);
5444 tsauxc |= TSAUXC_EN_TT1;
5445 wr32(E1000_TSAUXC, tsauxc);
5446 adapter->perout[1].start = ts;
5447 spin_unlock(&adapter->tmreg_lock);
5451 if (tsicr & TSINTR_AUTT0) {
5452 nsec = rd32(E1000_AUXSTMPL0);
5453 sec = rd32(E1000_AUXSTMPH0);
5454 event.type = PTP_CLOCK_EXTTS;
5456 event.timestamp = sec * 1000000000ULL + nsec;
5457 ptp_clock_event(adapter->ptp_clock, &event);
5458 ack |= TSINTR_AUTT0;
5461 if (tsicr & TSINTR_AUTT1) {
5462 nsec = rd32(E1000_AUXSTMPL1);
5463 sec = rd32(E1000_AUXSTMPH1);
5464 event.type = PTP_CLOCK_EXTTS;
5466 event.timestamp = sec * 1000000000ULL + nsec;
5467 ptp_clock_event(adapter->ptp_clock, &event);
5468 ack |= TSINTR_AUTT1;
5471 /* acknowledge the interrupts */
5472 wr32(E1000_TSICR, ack);
5475 static irqreturn_t igb_msix_other(int irq, void *data)
5477 struct igb_adapter *adapter = data;
5478 struct e1000_hw *hw = &adapter->hw;
5479 u32 icr = rd32(E1000_ICR);
5480 /* reading ICR causes bit 31 of EICR to be cleared */
5482 if (icr & E1000_ICR_DRSTA)
5483 schedule_work(&adapter->reset_task);
5485 if (icr & E1000_ICR_DOUTSYNC) {
5486 /* HW is reporting DMA is out of sync */
5487 adapter->stats.doosync++;
5488 /* The DMA Out of Sync is also indication of a spoof event
5489 * in IOV mode. Check the Wrong VM Behavior register to
5490 * see if it is really a spoof event.
5492 igb_check_wvbr(adapter);
5495 /* Check for a mailbox event */
5496 if (icr & E1000_ICR_VMMB)
5497 igb_msg_task(adapter);
5499 if (icr & E1000_ICR_LSC) {
5500 hw->mac.get_link_status = 1;
5501 /* guard against interrupt when we're going down */
5502 if (!test_bit(__IGB_DOWN, &adapter->state))
5503 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5506 if (icr & E1000_ICR_TS)
5507 igb_tsync_interrupt(adapter);
5509 wr32(E1000_EIMS, adapter->eims_other);
5514 static void igb_write_itr(struct igb_q_vector *q_vector)
5516 struct igb_adapter *adapter = q_vector->adapter;
5517 u32 itr_val = q_vector->itr_val & 0x7FFC;
5519 if (!q_vector->set_itr)
5525 if (adapter->hw.mac.type == e1000_82575)
5526 itr_val |= itr_val << 16;
5528 itr_val |= E1000_EITR_CNT_IGNR;
5530 writel(itr_val, q_vector->itr_register);
5531 q_vector->set_itr = 0;
5534 static irqreturn_t igb_msix_ring(int irq, void *data)
5536 struct igb_q_vector *q_vector = data;
5538 /* Write the ITR value calculated from the previous interrupt. */
5539 igb_write_itr(q_vector);
5541 napi_schedule(&q_vector->napi);
5546 #ifdef CONFIG_IGB_DCA
5547 static void igb_update_tx_dca(struct igb_adapter *adapter,
5548 struct igb_ring *tx_ring,
5551 struct e1000_hw *hw = &adapter->hw;
5552 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5554 if (hw->mac.type != e1000_82575)
5555 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5557 /* We can enable relaxed ordering for reads, but not writes when
5558 * DCA is enabled. This is due to a known issue in some chipsets
5559 * which will cause the DCA tag to be cleared.
5561 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5562 E1000_DCA_TXCTRL_DATA_RRO_EN |
5563 E1000_DCA_TXCTRL_DESC_DCA_EN;
5565 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5568 static void igb_update_rx_dca(struct igb_adapter *adapter,
5569 struct igb_ring *rx_ring,
5572 struct e1000_hw *hw = &adapter->hw;
5573 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5575 if (hw->mac.type != e1000_82575)
5576 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5578 /* We can enable relaxed ordering for reads, but not writes when
5579 * DCA is enabled. This is due to a known issue in some chipsets
5580 * which will cause the DCA tag to be cleared.
5582 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5583 E1000_DCA_RXCTRL_DESC_DCA_EN;
5585 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5588 static void igb_update_dca(struct igb_q_vector *q_vector)
5590 struct igb_adapter *adapter = q_vector->adapter;
5591 int cpu = get_cpu();
5593 if (q_vector->cpu == cpu)
5596 if (q_vector->tx.ring)
5597 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5599 if (q_vector->rx.ring)
5600 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5602 q_vector->cpu = cpu;
5607 static void igb_setup_dca(struct igb_adapter *adapter)
5609 struct e1000_hw *hw = &adapter->hw;
5612 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5615 /* Always use CB2 mode, difference is masked in the CB driver. */
5616 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5618 for (i = 0; i < adapter->num_q_vectors; i++) {
5619 adapter->q_vector[i]->cpu = -1;
5620 igb_update_dca(adapter->q_vector[i]);
5624 static int __igb_notify_dca(struct device *dev, void *data)
5626 struct net_device *netdev = dev_get_drvdata(dev);
5627 struct igb_adapter *adapter = netdev_priv(netdev);
5628 struct pci_dev *pdev = adapter->pdev;
5629 struct e1000_hw *hw = &adapter->hw;
5630 unsigned long event = *(unsigned long *)data;
5633 case DCA_PROVIDER_ADD:
5634 /* if already enabled, don't do it again */
5635 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5637 if (dca_add_requester(dev) == 0) {
5638 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5639 dev_info(&pdev->dev, "DCA enabled\n");
5640 igb_setup_dca(adapter);
5643 /* Fall Through since DCA is disabled. */
5644 case DCA_PROVIDER_REMOVE:
5645 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5646 /* without this a class_device is left
5647 * hanging around in the sysfs model
5649 dca_remove_requester(dev);
5650 dev_info(&pdev->dev, "DCA disabled\n");
5651 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5652 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5660 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5665 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5668 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5670 #endif /* CONFIG_IGB_DCA */
5672 #ifdef CONFIG_PCI_IOV
5673 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5675 unsigned char mac_addr[ETH_ALEN];
5677 eth_zero_addr(mac_addr);
5678 igb_set_vf_mac(adapter, vf, mac_addr);
5680 /* By default spoof check is enabled for all VFs */
5681 adapter->vf_data[vf].spoofchk_enabled = true;
5687 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5689 struct e1000_hw *hw = &adapter->hw;
5693 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5694 ping = E1000_PF_CONTROL_MSG;
5695 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5696 ping |= E1000_VT_MSGTYPE_CTS;
5697 igb_write_mbx(hw, &ping, 1, i);
5701 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5703 struct e1000_hw *hw = &adapter->hw;
5704 u32 vmolr = rd32(E1000_VMOLR(vf));
5705 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5707 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5708 IGB_VF_FLAG_MULTI_PROMISC);
5709 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5711 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5712 vmolr |= E1000_VMOLR_MPME;
5713 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5714 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5716 /* if we have hashes and we are clearing a multicast promisc
5717 * flag we need to write the hashes to the MTA as this step
5718 * was previously skipped
5720 if (vf_data->num_vf_mc_hashes > 30) {
5721 vmolr |= E1000_VMOLR_MPME;
5722 } else if (vf_data->num_vf_mc_hashes) {
5725 vmolr |= E1000_VMOLR_ROMPE;
5726 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5727 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5731 wr32(E1000_VMOLR(vf), vmolr);
5733 /* there are flags left unprocessed, likely not supported */
5734 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5740 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5741 u32 *msgbuf, u32 vf)
5743 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5744 u16 *hash_list = (u16 *)&msgbuf[1];
5745 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5748 /* salt away the number of multicast addresses assigned
5749 * to this VF for later use to restore when the PF multi cast
5752 vf_data->num_vf_mc_hashes = n;
5754 /* only up to 30 hash values supported */
5758 /* store the hashes for later use */
5759 for (i = 0; i < n; i++)
5760 vf_data->vf_mc_hashes[i] = hash_list[i];
5762 /* Flush and reset the mta with the new values */
5763 igb_set_rx_mode(adapter->netdev);
5768 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5770 struct e1000_hw *hw = &adapter->hw;
5771 struct vf_data_storage *vf_data;
5774 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5775 u32 vmolr = rd32(E1000_VMOLR(i));
5777 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5779 vf_data = &adapter->vf_data[i];
5781 if ((vf_data->num_vf_mc_hashes > 30) ||
5782 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5783 vmolr |= E1000_VMOLR_MPME;
5784 } else if (vf_data->num_vf_mc_hashes) {
5785 vmolr |= E1000_VMOLR_ROMPE;
5786 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5787 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5789 wr32(E1000_VMOLR(i), vmolr);
5793 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5795 struct e1000_hw *hw = &adapter->hw;
5796 u32 pool_mask, reg, vid;
5799 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5801 /* Find the vlan filter for this id */
5802 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5803 reg = rd32(E1000_VLVF(i));
5805 /* remove the vf from the pool */
5808 /* if pool is empty then remove entry from vfta */
5809 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5810 (reg & E1000_VLVF_VLANID_ENABLE)) {
5812 vid = reg & E1000_VLVF_VLANID_MASK;
5813 igb_vfta_set(hw, vid, false);
5816 wr32(E1000_VLVF(i), reg);
5819 adapter->vf_data[vf].vlans_enabled = 0;
5822 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5824 struct e1000_hw *hw = &adapter->hw;
5827 /* The vlvf table only exists on 82576 hardware and newer */
5828 if (hw->mac.type < e1000_82576)
5831 /* we only need to do this if VMDq is enabled */
5832 if (!adapter->vfs_allocated_count)
5835 /* Find the vlan filter for this id */
5836 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5837 reg = rd32(E1000_VLVF(i));
5838 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5839 vid == (reg & E1000_VLVF_VLANID_MASK))
5844 if (i == E1000_VLVF_ARRAY_SIZE) {
5845 /* Did not find a matching VLAN ID entry that was
5846 * enabled. Search for a free filter entry, i.e.
5847 * one without the enable bit set
5849 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5850 reg = rd32(E1000_VLVF(i));
5851 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5855 if (i < E1000_VLVF_ARRAY_SIZE) {
5856 /* Found an enabled/available entry */
5857 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5859 /* if !enabled we need to set this up in vfta */
5860 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5861 /* add VID to filter table */
5862 igb_vfta_set(hw, vid, true);
5863 reg |= E1000_VLVF_VLANID_ENABLE;
5865 reg &= ~E1000_VLVF_VLANID_MASK;
5867 wr32(E1000_VLVF(i), reg);
5869 /* do not modify RLPML for PF devices */
5870 if (vf >= adapter->vfs_allocated_count)
5873 if (!adapter->vf_data[vf].vlans_enabled) {
5876 reg = rd32(E1000_VMOLR(vf));
5877 size = reg & E1000_VMOLR_RLPML_MASK;
5879 reg &= ~E1000_VMOLR_RLPML_MASK;
5881 wr32(E1000_VMOLR(vf), reg);
5884 adapter->vf_data[vf].vlans_enabled++;
5887 if (i < E1000_VLVF_ARRAY_SIZE) {
5888 /* remove vf from the pool */
5889 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5890 /* if pool is empty then remove entry from vfta */
5891 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5893 igb_vfta_set(hw, vid, false);
5895 wr32(E1000_VLVF(i), reg);
5897 /* do not modify RLPML for PF devices */
5898 if (vf >= adapter->vfs_allocated_count)
5901 adapter->vf_data[vf].vlans_enabled--;
5902 if (!adapter->vf_data[vf].vlans_enabled) {
5905 reg = rd32(E1000_VMOLR(vf));
5906 size = reg & E1000_VMOLR_RLPML_MASK;
5908 reg &= ~E1000_VMOLR_RLPML_MASK;
5910 wr32(E1000_VMOLR(vf), reg);
5917 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5919 struct e1000_hw *hw = &adapter->hw;
5922 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5924 wr32(E1000_VMVIR(vf), 0);
5927 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5928 int vf, u16 vlan, u8 qos)
5931 struct igb_adapter *adapter = netdev_priv(netdev);
5933 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5936 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5939 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5940 igb_set_vmolr(adapter, vf, !vlan);
5941 adapter->vf_data[vf].pf_vlan = vlan;
5942 adapter->vf_data[vf].pf_qos = qos;
5943 dev_info(&adapter->pdev->dev,
5944 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5945 if (test_bit(__IGB_DOWN, &adapter->state)) {
5946 dev_warn(&adapter->pdev->dev,
5947 "The VF VLAN has been set, but the PF device is not up.\n");
5948 dev_warn(&adapter->pdev->dev,
5949 "Bring the PF device up before attempting to use the VF device.\n");
5952 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5954 igb_set_vmvir(adapter, vlan, vf);
5955 igb_set_vmolr(adapter, vf, true);
5956 adapter->vf_data[vf].pf_vlan = 0;
5957 adapter->vf_data[vf].pf_qos = 0;
5963 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5965 struct e1000_hw *hw = &adapter->hw;
5969 /* Find the vlan filter for this id */
5970 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5971 reg = rd32(E1000_VLVF(i));
5972 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5973 vid == (reg & E1000_VLVF_VLANID_MASK))
5977 if (i >= E1000_VLVF_ARRAY_SIZE)
5983 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5985 struct e1000_hw *hw = &adapter->hw;
5986 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5987 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5990 /* If in promiscuous mode we need to make sure the PF also has
5991 * the VLAN filter set.
5993 if (add && (adapter->netdev->flags & IFF_PROMISC))
5994 err = igb_vlvf_set(adapter, vid, add,
5995 adapter->vfs_allocated_count);
5999 err = igb_vlvf_set(adapter, vid, add, vf);
6004 /* Go through all the checks to see if the VLAN filter should
6005 * be wiped completely.
6007 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
6009 int regndx = igb_find_vlvf_entry(adapter, vid);
6013 /* See if any other pools are set for this VLAN filter
6014 * entry other than the PF.
6016 vlvf = bits = rd32(E1000_VLVF(regndx));
6017 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6018 adapter->vfs_allocated_count);
6019 /* If the filter was removed then ensure PF pool bit
6020 * is cleared if the PF only added itself to the pool
6021 * because the PF is in promiscuous mode.
6023 if ((vlvf & VLAN_VID_MASK) == vid &&
6024 !test_bit(vid, adapter->active_vlans) &&
6026 igb_vlvf_set(adapter, vid, add,
6027 adapter->vfs_allocated_count);
6034 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6036 /* clear flags - except flag that indicates PF has set the MAC */
6037 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
6038 adapter->vf_data[vf].last_nack = jiffies;
6040 /* reset offloads to defaults */
6041 igb_set_vmolr(adapter, vf, true);
6043 /* reset vlans for device */
6044 igb_clear_vf_vfta(adapter, vf);
6045 if (adapter->vf_data[vf].pf_vlan)
6046 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6047 adapter->vf_data[vf].pf_vlan,
6048 adapter->vf_data[vf].pf_qos);
6050 igb_clear_vf_vfta(adapter, vf);
6052 /* reset multicast table array for vf */
6053 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6055 /* Flush and reset the mta with the new values */
6056 igb_set_rx_mode(adapter->netdev);
6059 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6061 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6063 /* clear mac address as we were hotplug removed/added */
6064 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6065 eth_zero_addr(vf_mac);
6067 /* process remaining reset events */
6068 igb_vf_reset(adapter, vf);
6071 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6073 struct e1000_hw *hw = &adapter->hw;
6074 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6075 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6077 u8 *addr = (u8 *)(&msgbuf[1]);
6079 /* process all the same items cleared in a function level reset */
6080 igb_vf_reset(adapter, vf);
6082 /* set vf mac address */
6083 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6085 /* enable transmit and receive for vf */
6086 reg = rd32(E1000_VFTE);
6087 wr32(E1000_VFTE, reg | (1 << vf));
6088 reg = rd32(E1000_VFRE);
6089 wr32(E1000_VFRE, reg | (1 << vf));
6091 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6093 /* reply to reset with ack and vf mac address */
6094 if (!is_zero_ether_addr(vf_mac)) {
6095 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6096 memcpy(addr, vf_mac, ETH_ALEN);
6098 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6100 igb_write_mbx(hw, msgbuf, 3, vf);
6103 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6105 /* The VF MAC Address is stored in a packed array of bytes
6106 * starting at the second 32 bit word of the msg array
6108 unsigned char *addr = (char *)&msg[1];
6111 if (is_valid_ether_addr(addr))
6112 err = igb_set_vf_mac(adapter, vf, addr);
6117 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6119 struct e1000_hw *hw = &adapter->hw;
6120 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6121 u32 msg = E1000_VT_MSGTYPE_NACK;
6123 /* if device isn't clear to send it shouldn't be reading either */
6124 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6125 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6126 igb_write_mbx(hw, &msg, 1, vf);
6127 vf_data->last_nack = jiffies;
6131 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6133 struct pci_dev *pdev = adapter->pdev;
6134 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6135 struct e1000_hw *hw = &adapter->hw;
6136 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6139 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6142 /* if receive failed revoke VF CTS stats and restart init */
6143 dev_err(&pdev->dev, "Error receiving message from VF\n");
6144 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6145 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6150 /* this is a message we already processed, do nothing */
6151 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6154 /* until the vf completes a reset it should not be
6155 * allowed to start any configuration.
6157 if (msgbuf[0] == E1000_VF_RESET) {
6158 igb_vf_reset_msg(adapter, vf);
6162 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6163 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6169 switch ((msgbuf[0] & 0xFFFF)) {
6170 case E1000_VF_SET_MAC_ADDR:
6172 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6173 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6175 dev_warn(&pdev->dev,
6176 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6179 case E1000_VF_SET_PROMISC:
6180 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6182 case E1000_VF_SET_MULTICAST:
6183 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6185 case E1000_VF_SET_LPE:
6186 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6188 case E1000_VF_SET_VLAN:
6190 if (vf_data->pf_vlan)
6191 dev_warn(&pdev->dev,
6192 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6195 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6198 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6203 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6205 /* notify the VF of the results of what it sent us */
6207 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6209 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6211 igb_write_mbx(hw, msgbuf, 1, vf);
6214 static void igb_msg_task(struct igb_adapter *adapter)
6216 struct e1000_hw *hw = &adapter->hw;
6219 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6220 /* process any reset requests */
6221 if (!igb_check_for_rst(hw, vf))
6222 igb_vf_reset_event(adapter, vf);
6224 /* process any messages pending */
6225 if (!igb_check_for_msg(hw, vf))
6226 igb_rcv_msg_from_vf(adapter, vf);
6228 /* process any acks */
6229 if (!igb_check_for_ack(hw, vf))
6230 igb_rcv_ack_from_vf(adapter, vf);
6235 * igb_set_uta - Set unicast filter table address
6236 * @adapter: board private structure
6238 * The unicast table address is a register array of 32-bit registers.
6239 * The table is meant to be used in a way similar to how the MTA is used
6240 * however due to certain limitations in the hardware it is necessary to
6241 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6242 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6244 static void igb_set_uta(struct igb_adapter *adapter)
6246 struct e1000_hw *hw = &adapter->hw;
6249 /* The UTA table only exists on 82576 hardware and newer */
6250 if (hw->mac.type < e1000_82576)
6253 /* we only need to do this if VMDq is enabled */
6254 if (!adapter->vfs_allocated_count)
6257 for (i = 0; i < hw->mac.uta_reg_count; i++)
6258 array_wr32(E1000_UTA, i, ~0);
6262 * igb_intr_msi - Interrupt Handler
6263 * @irq: interrupt number
6264 * @data: pointer to a network interface device structure
6266 static irqreturn_t igb_intr_msi(int irq, void *data)
6268 struct igb_adapter *adapter = data;
6269 struct igb_q_vector *q_vector = adapter->q_vector[0];
6270 struct e1000_hw *hw = &adapter->hw;
6271 /* read ICR disables interrupts using IAM */
6272 u32 icr = rd32(E1000_ICR);
6274 igb_write_itr(q_vector);
6276 if (icr & E1000_ICR_DRSTA)
6277 schedule_work(&adapter->reset_task);
6279 if (icr & E1000_ICR_DOUTSYNC) {
6280 /* HW is reporting DMA is out of sync */
6281 adapter->stats.doosync++;
6284 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6285 hw->mac.get_link_status = 1;
6286 if (!test_bit(__IGB_DOWN, &adapter->state))
6287 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6290 if (icr & E1000_ICR_TS)
6291 igb_tsync_interrupt(adapter);
6293 napi_schedule(&q_vector->napi);
6299 * igb_intr - Legacy Interrupt Handler
6300 * @irq: interrupt number
6301 * @data: pointer to a network interface device structure
6303 static irqreturn_t igb_intr(int irq, void *data)
6305 struct igb_adapter *adapter = data;
6306 struct igb_q_vector *q_vector = adapter->q_vector[0];
6307 struct e1000_hw *hw = &adapter->hw;
6308 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6309 * need for the IMC write
6311 u32 icr = rd32(E1000_ICR);
6313 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6314 * not set, then the adapter didn't send an interrupt
6316 if (!(icr & E1000_ICR_INT_ASSERTED))
6319 igb_write_itr(q_vector);
6321 if (icr & E1000_ICR_DRSTA)
6322 schedule_work(&adapter->reset_task);
6324 if (icr & E1000_ICR_DOUTSYNC) {
6325 /* HW is reporting DMA is out of sync */
6326 adapter->stats.doosync++;
6329 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6330 hw->mac.get_link_status = 1;
6331 /* guard against interrupt when we're going down */
6332 if (!test_bit(__IGB_DOWN, &adapter->state))
6333 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6336 if (icr & E1000_ICR_TS)
6337 igb_tsync_interrupt(adapter);
6339 napi_schedule(&q_vector->napi);
6344 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6346 struct igb_adapter *adapter = q_vector->adapter;
6347 struct e1000_hw *hw = &adapter->hw;
6349 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6350 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6351 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6352 igb_set_itr(q_vector);
6354 igb_update_ring_itr(q_vector);
6357 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6358 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6359 wr32(E1000_EIMS, q_vector->eims_value);
6361 igb_irq_enable(adapter);
6366 * igb_poll - NAPI Rx polling callback
6367 * @napi: napi polling structure
6368 * @budget: count of how many packets we should handle
6370 static int igb_poll(struct napi_struct *napi, int budget)
6372 struct igb_q_vector *q_vector = container_of(napi,
6373 struct igb_q_vector,
6375 bool clean_complete = true;
6378 #ifdef CONFIG_IGB_DCA
6379 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6380 igb_update_dca(q_vector);
6382 if (q_vector->tx.ring)
6383 clean_complete = igb_clean_tx_irq(q_vector);
6385 if (q_vector->rx.ring) {
6386 int cleaned = igb_clean_rx_irq(q_vector, budget);
6388 work_done += cleaned;
6389 clean_complete &= (cleaned < budget);
6392 /* If all work not completed, return budget and keep polling */
6393 if (!clean_complete)
6396 /* If not enough Rx work done, exit the polling mode */
6397 napi_complete_done(napi, work_done);
6398 igb_ring_irq_enable(q_vector);
6404 * igb_clean_tx_irq - Reclaim resources after transmit completes
6405 * @q_vector: pointer to q_vector containing needed info
6407 * returns true if ring is completely cleaned
6409 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6411 struct igb_adapter *adapter = q_vector->adapter;
6412 struct igb_ring *tx_ring = q_vector->tx.ring;
6413 struct igb_tx_buffer *tx_buffer;
6414 union e1000_adv_tx_desc *tx_desc;
6415 unsigned int total_bytes = 0, total_packets = 0;
6416 unsigned int budget = q_vector->tx.work_limit;
6417 unsigned int i = tx_ring->next_to_clean;
6419 if (test_bit(__IGB_DOWN, &adapter->state))
6422 tx_buffer = &tx_ring->tx_buffer_info[i];
6423 tx_desc = IGB_TX_DESC(tx_ring, i);
6424 i -= tx_ring->count;
6427 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6429 /* if next_to_watch is not set then there is no work pending */
6433 /* prevent any other reads prior to eop_desc */
6434 read_barrier_depends();
6436 /* if DD is not set pending work has not been completed */
6437 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6440 /* clear next_to_watch to prevent false hangs */
6441 tx_buffer->next_to_watch = NULL;
6443 /* update the statistics for this packet */
6444 total_bytes += tx_buffer->bytecount;
6445 total_packets += tx_buffer->gso_segs;
6448 dev_consume_skb_any(tx_buffer->skb);
6450 /* unmap skb header data */
6451 dma_unmap_single(tx_ring->dev,
6452 dma_unmap_addr(tx_buffer, dma),
6453 dma_unmap_len(tx_buffer, len),
6456 /* clear tx_buffer data */
6457 tx_buffer->skb = NULL;
6458 dma_unmap_len_set(tx_buffer, len, 0);
6460 /* clear last DMA location and unmap remaining buffers */
6461 while (tx_desc != eop_desc) {
6466 i -= tx_ring->count;
6467 tx_buffer = tx_ring->tx_buffer_info;
6468 tx_desc = IGB_TX_DESC(tx_ring, 0);
6471 /* unmap any remaining paged data */
6472 if (dma_unmap_len(tx_buffer, len)) {
6473 dma_unmap_page(tx_ring->dev,
6474 dma_unmap_addr(tx_buffer, dma),
6475 dma_unmap_len(tx_buffer, len),
6477 dma_unmap_len_set(tx_buffer, len, 0);
6481 /* move us one more past the eop_desc for start of next pkt */
6486 i -= tx_ring->count;
6487 tx_buffer = tx_ring->tx_buffer_info;
6488 tx_desc = IGB_TX_DESC(tx_ring, 0);
6491 /* issue prefetch for next Tx descriptor */
6494 /* update budget accounting */
6496 } while (likely(budget));
6498 netdev_tx_completed_queue(txring_txq(tx_ring),
6499 total_packets, total_bytes);
6500 i += tx_ring->count;
6501 tx_ring->next_to_clean = i;
6502 u64_stats_update_begin(&tx_ring->tx_syncp);
6503 tx_ring->tx_stats.bytes += total_bytes;
6504 tx_ring->tx_stats.packets += total_packets;
6505 u64_stats_update_end(&tx_ring->tx_syncp);
6506 q_vector->tx.total_bytes += total_bytes;
6507 q_vector->tx.total_packets += total_packets;
6509 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6510 struct e1000_hw *hw = &adapter->hw;
6512 /* Detect a transmit hang in hardware, this serializes the
6513 * check with the clearing of time_stamp and movement of i
6515 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6516 if (tx_buffer->next_to_watch &&
6517 time_after(jiffies, tx_buffer->time_stamp +
6518 (adapter->tx_timeout_factor * HZ)) &&
6519 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6521 /* detected Tx unit hang */
6522 dev_err(tx_ring->dev,
6523 "Detected Tx Unit Hang\n"
6527 " next_to_use <%x>\n"
6528 " next_to_clean <%x>\n"
6529 "buffer_info[next_to_clean]\n"
6530 " time_stamp <%lx>\n"
6531 " next_to_watch <%p>\n"
6533 " desc.status <%x>\n",
6534 tx_ring->queue_index,
6535 rd32(E1000_TDH(tx_ring->reg_idx)),
6536 readl(tx_ring->tail),
6537 tx_ring->next_to_use,
6538 tx_ring->next_to_clean,
6539 tx_buffer->time_stamp,
6540 tx_buffer->next_to_watch,
6542 tx_buffer->next_to_watch->wb.status);
6543 netif_stop_subqueue(tx_ring->netdev,
6544 tx_ring->queue_index);
6546 /* we are about to reset, no point in enabling stuff */
6551 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6552 if (unlikely(total_packets &&
6553 netif_carrier_ok(tx_ring->netdev) &&
6554 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6555 /* Make sure that anybody stopping the queue after this
6556 * sees the new next_to_clean.
6559 if (__netif_subqueue_stopped(tx_ring->netdev,
6560 tx_ring->queue_index) &&
6561 !(test_bit(__IGB_DOWN, &adapter->state))) {
6562 netif_wake_subqueue(tx_ring->netdev,
6563 tx_ring->queue_index);
6565 u64_stats_update_begin(&tx_ring->tx_syncp);
6566 tx_ring->tx_stats.restart_queue++;
6567 u64_stats_update_end(&tx_ring->tx_syncp);
6575 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6576 * @rx_ring: rx descriptor ring to store buffers on
6577 * @old_buff: donor buffer to have page reused
6579 * Synchronizes page for reuse by the adapter
6581 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6582 struct igb_rx_buffer *old_buff)
6584 struct igb_rx_buffer *new_buff;
6585 u16 nta = rx_ring->next_to_alloc;
6587 new_buff = &rx_ring->rx_buffer_info[nta];
6589 /* update, and store next to alloc */
6591 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6593 /* transfer page from old buffer to new buffer */
6594 *new_buff = *old_buff;
6596 /* sync the buffer for use by the device */
6597 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6598 old_buff->page_offset,
6603 static inline bool igb_page_is_reserved(struct page *page)
6605 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
6608 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6610 unsigned int truesize)
6612 /* avoid re-using remote pages */
6613 if (unlikely(igb_page_is_reserved(page)))
6616 #if (PAGE_SIZE < 8192)
6617 /* if we are only owner of page we can reuse it */
6618 if (unlikely(page_count(page) != 1))
6621 /* flip page offset to other buffer */
6622 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6624 /* move offset up to the next cache line */
6625 rx_buffer->page_offset += truesize;
6627 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6631 /* Even if we own the page, we are not allowed to use atomic_set()
6632 * This would break get_page_unless_zero() users.
6634 atomic_inc(&page->_count);
6640 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6641 * @rx_ring: rx descriptor ring to transact packets on
6642 * @rx_buffer: buffer containing page to add
6643 * @rx_desc: descriptor containing length of buffer written by hardware
6644 * @skb: sk_buff to place the data into
6646 * This function will add the data contained in rx_buffer->page to the skb.
6647 * This is done either through a direct copy if the data in the buffer is
6648 * less than the skb header size, otherwise it will just attach the page as
6649 * a frag to the skb.
6651 * The function will then update the page offset if necessary and return
6652 * true if the buffer can be reused by the adapter.
6654 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6655 struct igb_rx_buffer *rx_buffer,
6656 union e1000_adv_rx_desc *rx_desc,
6657 struct sk_buff *skb)
6659 struct page *page = rx_buffer->page;
6660 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6661 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6662 #if (PAGE_SIZE < 8192)
6663 unsigned int truesize = IGB_RX_BUFSZ;
6665 unsigned int truesize = SKB_DATA_ALIGN(size);
6667 unsigned int pull_len;
6669 if (unlikely(skb_is_nonlinear(skb)))
6672 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6673 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6674 va += IGB_TS_HDR_LEN;
6675 size -= IGB_TS_HDR_LEN;
6678 if (likely(size <= IGB_RX_HDR_LEN)) {
6679 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6681 /* page is not reserved, we can reuse buffer as-is */
6682 if (likely(!igb_page_is_reserved(page)))
6685 /* this page cannot be reused so discard it */
6690 /* we need the header to contain the greater of either ETH_HLEN or
6691 * 60 bytes if the skb->len is less than 60 for skb_pad.
6693 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6695 /* align pull length to size of long to optimize memcpy performance */
6696 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6698 /* update all of the pointers */
6703 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6704 (unsigned long)va & ~PAGE_MASK, size, truesize);
6706 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6709 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6710 union e1000_adv_rx_desc *rx_desc,
6711 struct sk_buff *skb)
6713 struct igb_rx_buffer *rx_buffer;
6716 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6717 page = rx_buffer->page;
6721 void *page_addr = page_address(page) +
6722 rx_buffer->page_offset;
6724 /* prefetch first cache line of first page */
6725 prefetch(page_addr);
6726 #if L1_CACHE_BYTES < 128
6727 prefetch(page_addr + L1_CACHE_BYTES);
6730 /* allocate a skb to store the frags */
6731 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6732 if (unlikely(!skb)) {
6733 rx_ring->rx_stats.alloc_failed++;
6737 /* we will be copying header into skb->data in
6738 * pskb_may_pull so it is in our interest to prefetch
6739 * it now to avoid a possible cache miss
6741 prefetchw(skb->data);
6744 /* we are reusing so sync this buffer for CPU use */
6745 dma_sync_single_range_for_cpu(rx_ring->dev,
6747 rx_buffer->page_offset,
6751 /* pull page into skb */
6752 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6753 /* hand second half of page back to the ring */
6754 igb_reuse_rx_page(rx_ring, rx_buffer);
6756 /* we are not reusing the buffer so unmap it */
6757 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6758 PAGE_SIZE, DMA_FROM_DEVICE);
6761 /* clear contents of rx_buffer */
6762 rx_buffer->page = NULL;
6767 static inline void igb_rx_checksum(struct igb_ring *ring,
6768 union e1000_adv_rx_desc *rx_desc,
6769 struct sk_buff *skb)
6771 skb_checksum_none_assert(skb);
6773 /* Ignore Checksum bit is set */
6774 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6777 /* Rx checksum disabled via ethtool */
6778 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6781 /* TCP/UDP checksum error bit is set */
6782 if (igb_test_staterr(rx_desc,
6783 E1000_RXDEXT_STATERR_TCPE |
6784 E1000_RXDEXT_STATERR_IPE)) {
6785 /* work around errata with sctp packets where the TCPE aka
6786 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6787 * packets, (aka let the stack check the crc32c)
6789 if (!((skb->len == 60) &&
6790 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6791 u64_stats_update_begin(&ring->rx_syncp);
6792 ring->rx_stats.csum_err++;
6793 u64_stats_update_end(&ring->rx_syncp);
6795 /* let the stack verify checksum errors */
6798 /* It must be a TCP or UDP packet with a valid checksum */
6799 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6800 E1000_RXD_STAT_UDPCS))
6801 skb->ip_summed = CHECKSUM_UNNECESSARY;
6803 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6804 le32_to_cpu(rx_desc->wb.upper.status_error));
6807 static inline void igb_rx_hash(struct igb_ring *ring,
6808 union e1000_adv_rx_desc *rx_desc,
6809 struct sk_buff *skb)
6811 if (ring->netdev->features & NETIF_F_RXHASH)
6813 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6818 * igb_is_non_eop - process handling of non-EOP buffers
6819 * @rx_ring: Rx ring being processed
6820 * @rx_desc: Rx descriptor for current buffer
6821 * @skb: current socket buffer containing buffer in progress
6823 * This function updates next to clean. If the buffer is an EOP buffer
6824 * this function exits returning false, otherwise it will place the
6825 * sk_buff in the next buffer to be chained and return true indicating
6826 * that this is in fact a non-EOP buffer.
6828 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6829 union e1000_adv_rx_desc *rx_desc)
6831 u32 ntc = rx_ring->next_to_clean + 1;
6833 /* fetch, update, and store next to clean */
6834 ntc = (ntc < rx_ring->count) ? ntc : 0;
6835 rx_ring->next_to_clean = ntc;
6837 prefetch(IGB_RX_DESC(rx_ring, ntc));
6839 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6846 * igb_cleanup_headers - Correct corrupted or empty headers
6847 * @rx_ring: rx descriptor ring packet is being transacted on
6848 * @rx_desc: pointer to the EOP Rx descriptor
6849 * @skb: pointer to current skb being fixed
6851 * Address the case where we are pulling data in on pages only
6852 * and as such no data is present in the skb header.
6854 * In addition if skb is not at least 60 bytes we need to pad it so that
6855 * it is large enough to qualify as a valid Ethernet frame.
6857 * Returns true if an error was encountered and skb was freed.
6859 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6860 union e1000_adv_rx_desc *rx_desc,
6861 struct sk_buff *skb)
6863 if (unlikely((igb_test_staterr(rx_desc,
6864 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6865 struct net_device *netdev = rx_ring->netdev;
6866 if (!(netdev->features & NETIF_F_RXALL)) {
6867 dev_kfree_skb_any(skb);
6872 /* if eth_skb_pad returns an error the skb was freed */
6873 if (eth_skb_pad(skb))
6880 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6881 * @rx_ring: rx descriptor ring packet is being transacted on
6882 * @rx_desc: pointer to the EOP Rx descriptor
6883 * @skb: pointer to current skb being populated
6885 * This function checks the ring, descriptor, and packet information in
6886 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6887 * other fields within the skb.
6889 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6890 union e1000_adv_rx_desc *rx_desc,
6891 struct sk_buff *skb)
6893 struct net_device *dev = rx_ring->netdev;
6895 igb_rx_hash(rx_ring, rx_desc, skb);
6897 igb_rx_checksum(rx_ring, rx_desc, skb);
6899 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6900 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6901 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6903 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6904 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6907 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6908 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6909 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6911 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6913 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6916 skb_record_rx_queue(skb, rx_ring->queue_index);
6918 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6921 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6923 struct igb_ring *rx_ring = q_vector->rx.ring;
6924 struct sk_buff *skb = rx_ring->skb;
6925 unsigned int total_bytes = 0, total_packets = 0;
6926 u16 cleaned_count = igb_desc_unused(rx_ring);
6928 while (likely(total_packets < budget)) {
6929 union e1000_adv_rx_desc *rx_desc;
6931 /* return some buffers to hardware, one at a time is too slow */
6932 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6933 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6937 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6939 if (!rx_desc->wb.upper.status_error)
6942 /* This memory barrier is needed to keep us from reading
6943 * any other fields out of the rx_desc until we know the
6944 * descriptor has been written back
6948 /* retrieve a buffer from the ring */
6949 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6951 /* exit if we failed to retrieve a buffer */
6957 /* fetch next buffer in frame if non-eop */
6958 if (igb_is_non_eop(rx_ring, rx_desc))
6961 /* verify the packet layout is correct */
6962 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6967 /* probably a little skewed due to removing CRC */
6968 total_bytes += skb->len;
6970 /* populate checksum, timestamp, VLAN, and protocol */
6971 igb_process_skb_fields(rx_ring, rx_desc, skb);
6973 napi_gro_receive(&q_vector->napi, skb);
6975 /* reset skb pointer */
6978 /* update budget accounting */
6982 /* place incomplete frames back on ring for completion */
6985 u64_stats_update_begin(&rx_ring->rx_syncp);
6986 rx_ring->rx_stats.packets += total_packets;
6987 rx_ring->rx_stats.bytes += total_bytes;
6988 u64_stats_update_end(&rx_ring->rx_syncp);
6989 q_vector->rx.total_packets += total_packets;
6990 q_vector->rx.total_bytes += total_bytes;
6993 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6995 return total_packets;
6998 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6999 struct igb_rx_buffer *bi)
7001 struct page *page = bi->page;
7004 /* since we are recycling buffers we should seldom need to alloc */
7008 /* alloc new page for storage */
7009 page = dev_alloc_page();
7010 if (unlikely(!page)) {
7011 rx_ring->rx_stats.alloc_failed++;
7015 /* map page for use */
7016 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7018 /* if mapping failed free memory back to system since
7019 * there isn't much point in holding memory we can't use
7021 if (dma_mapping_error(rx_ring->dev, dma)) {
7024 rx_ring->rx_stats.alloc_failed++;
7030 bi->page_offset = 0;
7036 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7037 * @adapter: address of board private structure
7039 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7041 union e1000_adv_rx_desc *rx_desc;
7042 struct igb_rx_buffer *bi;
7043 u16 i = rx_ring->next_to_use;
7049 rx_desc = IGB_RX_DESC(rx_ring, i);
7050 bi = &rx_ring->rx_buffer_info[i];
7051 i -= rx_ring->count;
7054 if (!igb_alloc_mapped_page(rx_ring, bi))
7057 /* Refresh the desc even if buffer_addrs didn't change
7058 * because each write-back erases this info.
7060 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7066 rx_desc = IGB_RX_DESC(rx_ring, 0);
7067 bi = rx_ring->rx_buffer_info;
7068 i -= rx_ring->count;
7071 /* clear the status bits for the next_to_use descriptor */
7072 rx_desc->wb.upper.status_error = 0;
7075 } while (cleaned_count);
7077 i += rx_ring->count;
7079 if (rx_ring->next_to_use != i) {
7080 /* record the next descriptor to use */
7081 rx_ring->next_to_use = i;
7083 /* update next to alloc since we have filled the ring */
7084 rx_ring->next_to_alloc = i;
7086 /* Force memory writes to complete before letting h/w
7087 * know there are new descriptors to fetch. (Only
7088 * applicable for weak-ordered memory model archs,
7092 writel(i, rx_ring->tail);
7102 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7104 struct igb_adapter *adapter = netdev_priv(netdev);
7105 struct mii_ioctl_data *data = if_mii(ifr);
7107 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7112 data->phy_id = adapter->hw.phy.addr;
7115 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7132 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7138 return igb_mii_ioctl(netdev, ifr, cmd);
7140 return igb_ptp_get_ts_config(netdev, ifr);
7142 return igb_ptp_set_ts_config(netdev, ifr);
7148 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7150 struct igb_adapter *adapter = hw->back;
7152 pci_read_config_word(adapter->pdev, reg, value);
7155 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7157 struct igb_adapter *adapter = hw->back;
7159 pci_write_config_word(adapter->pdev, reg, *value);
7162 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7164 struct igb_adapter *adapter = hw->back;
7166 if (pcie_capability_read_word(adapter->pdev, reg, value))
7167 return -E1000_ERR_CONFIG;
7172 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7174 struct igb_adapter *adapter = hw->back;
7176 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7177 return -E1000_ERR_CONFIG;
7182 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7184 struct igb_adapter *adapter = netdev_priv(netdev);
7185 struct e1000_hw *hw = &adapter->hw;
7187 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7190 /* enable VLAN tag insert/strip */
7191 ctrl = rd32(E1000_CTRL);
7192 ctrl |= E1000_CTRL_VME;
7193 wr32(E1000_CTRL, ctrl);
7195 /* Disable CFI check */
7196 rctl = rd32(E1000_RCTL);
7197 rctl &= ~E1000_RCTL_CFIEN;
7198 wr32(E1000_RCTL, rctl);
7200 /* disable VLAN tag insert/strip */
7201 ctrl = rd32(E1000_CTRL);
7202 ctrl &= ~E1000_CTRL_VME;
7203 wr32(E1000_CTRL, ctrl);
7206 igb_rlpml_set(adapter);
7209 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7210 __be16 proto, u16 vid)
7212 struct igb_adapter *adapter = netdev_priv(netdev);
7213 struct e1000_hw *hw = &adapter->hw;
7214 int pf_id = adapter->vfs_allocated_count;
7216 /* attempt to add filter to vlvf array */
7217 igb_vlvf_set(adapter, vid, true, pf_id);
7219 /* add the filter since PF can receive vlans w/o entry in vlvf */
7220 igb_vfta_set(hw, vid, true);
7222 set_bit(vid, adapter->active_vlans);
7227 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7228 __be16 proto, u16 vid)
7230 struct igb_adapter *adapter = netdev_priv(netdev);
7231 struct e1000_hw *hw = &adapter->hw;
7232 int pf_id = adapter->vfs_allocated_count;
7235 /* remove vlan from VLVF table array */
7236 err = igb_vlvf_set(adapter, vid, false, pf_id);
7238 /* if vid was not present in VLVF just remove it from table */
7240 igb_vfta_set(hw, vid, false);
7242 clear_bit(vid, adapter->active_vlans);
7247 static void igb_restore_vlan(struct igb_adapter *adapter)
7251 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7253 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7254 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7257 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7259 struct pci_dev *pdev = adapter->pdev;
7260 struct e1000_mac_info *mac = &adapter->hw.mac;
7264 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7265 * for the switch() below to work
7267 if ((spd & 1) || (dplx & ~1))
7270 /* Fiber NIC's only allow 1000 gbps Full duplex
7271 * and 100Mbps Full duplex for 100baseFx sfp
7273 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7274 switch (spd + dplx) {
7275 case SPEED_10 + DUPLEX_HALF:
7276 case SPEED_10 + DUPLEX_FULL:
7277 case SPEED_100 + DUPLEX_HALF:
7284 switch (spd + dplx) {
7285 case SPEED_10 + DUPLEX_HALF:
7286 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7288 case SPEED_10 + DUPLEX_FULL:
7289 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7291 case SPEED_100 + DUPLEX_HALF:
7292 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7294 case SPEED_100 + DUPLEX_FULL:
7295 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7297 case SPEED_1000 + DUPLEX_FULL:
7299 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7301 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7306 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7307 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7312 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7316 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7319 struct net_device *netdev = pci_get_drvdata(pdev);
7320 struct igb_adapter *adapter = netdev_priv(netdev);
7321 struct e1000_hw *hw = &adapter->hw;
7322 u32 ctrl, rctl, status;
7323 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7328 netif_device_detach(netdev);
7330 if (netif_running(netdev))
7331 __igb_close(netdev, true);
7333 igb_clear_interrupt_scheme(adapter);
7336 retval = pci_save_state(pdev);
7341 status = rd32(E1000_STATUS);
7342 if (status & E1000_STATUS_LU)
7343 wufc &= ~E1000_WUFC_LNKC;
7346 igb_setup_rctl(adapter);
7347 igb_set_rx_mode(netdev);
7349 /* turn on all-multi mode if wake on multicast is enabled */
7350 if (wufc & E1000_WUFC_MC) {
7351 rctl = rd32(E1000_RCTL);
7352 rctl |= E1000_RCTL_MPE;
7353 wr32(E1000_RCTL, rctl);
7356 ctrl = rd32(E1000_CTRL);
7357 /* advertise wake from D3Cold */
7358 #define E1000_CTRL_ADVD3WUC 0x00100000
7359 /* phy power management enable */
7360 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7361 ctrl |= E1000_CTRL_ADVD3WUC;
7362 wr32(E1000_CTRL, ctrl);
7364 /* Allow time for pending master requests to run */
7365 igb_disable_pcie_master(hw);
7367 wr32(E1000_WUC, E1000_WUC_PME_EN);
7368 wr32(E1000_WUFC, wufc);
7371 wr32(E1000_WUFC, 0);
7374 *enable_wake = wufc || adapter->en_mng_pt;
7376 igb_power_down_link(adapter);
7378 igb_power_up_link(adapter);
7380 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7381 * would have already happened in close and is redundant.
7383 igb_release_hw_control(adapter);
7385 pci_disable_device(pdev);
7391 #ifdef CONFIG_PM_SLEEP
7392 static int igb_suspend(struct device *dev)
7396 struct pci_dev *pdev = to_pci_dev(dev);
7398 retval = __igb_shutdown(pdev, &wake, 0);
7403 pci_prepare_to_sleep(pdev);
7405 pci_wake_from_d3(pdev, false);
7406 pci_set_power_state(pdev, PCI_D3hot);
7411 #endif /* CONFIG_PM_SLEEP */
7413 static int igb_resume(struct device *dev)
7415 struct pci_dev *pdev = to_pci_dev(dev);
7416 struct net_device *netdev = pci_get_drvdata(pdev);
7417 struct igb_adapter *adapter = netdev_priv(netdev);
7418 struct e1000_hw *hw = &adapter->hw;
7421 pci_set_power_state(pdev, PCI_D0);
7422 pci_restore_state(pdev);
7423 pci_save_state(pdev);
7425 if (!pci_device_is_present(pdev))
7427 err = pci_enable_device_mem(pdev);
7430 "igb: Cannot enable PCI device from suspend\n");
7433 pci_set_master(pdev);
7435 pci_enable_wake(pdev, PCI_D3hot, 0);
7436 pci_enable_wake(pdev, PCI_D3cold, 0);
7438 if (igb_init_interrupt_scheme(adapter, true)) {
7439 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7446 /* let the f/w know that the h/w is now under the control of the
7449 igb_get_hw_control(adapter);
7451 wr32(E1000_WUS, ~0);
7453 if (netdev->flags & IFF_UP) {
7455 err = __igb_open(netdev, true);
7461 netif_device_attach(netdev);
7465 static int igb_runtime_idle(struct device *dev)
7467 struct pci_dev *pdev = to_pci_dev(dev);
7468 struct net_device *netdev = pci_get_drvdata(pdev);
7469 struct igb_adapter *adapter = netdev_priv(netdev);
7471 if (!igb_has_link(adapter))
7472 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7477 static int igb_runtime_suspend(struct device *dev)
7479 struct pci_dev *pdev = to_pci_dev(dev);
7483 retval = __igb_shutdown(pdev, &wake, 1);
7488 pci_prepare_to_sleep(pdev);
7490 pci_wake_from_d3(pdev, false);
7491 pci_set_power_state(pdev, PCI_D3hot);
7497 static int igb_runtime_resume(struct device *dev)
7499 return igb_resume(dev);
7501 #endif /* CONFIG_PM */
7503 static void igb_shutdown(struct pci_dev *pdev)
7507 __igb_shutdown(pdev, &wake, 0);
7509 if (system_state == SYSTEM_POWER_OFF) {
7510 pci_wake_from_d3(pdev, wake);
7511 pci_set_power_state(pdev, PCI_D3hot);
7515 #ifdef CONFIG_PCI_IOV
7516 static int igb_sriov_reinit(struct pci_dev *dev)
7518 struct net_device *netdev = pci_get_drvdata(dev);
7519 struct igb_adapter *adapter = netdev_priv(netdev);
7520 struct pci_dev *pdev = adapter->pdev;
7524 if (netif_running(netdev))
7529 igb_clear_interrupt_scheme(adapter);
7531 igb_init_queue_configuration(adapter);
7533 if (igb_init_interrupt_scheme(adapter, true)) {
7535 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7539 if (netif_running(netdev))
7547 static int igb_pci_disable_sriov(struct pci_dev *dev)
7549 int err = igb_disable_sriov(dev);
7552 err = igb_sriov_reinit(dev);
7557 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7559 int err = igb_enable_sriov(dev, num_vfs);
7564 err = igb_sriov_reinit(dev);
7573 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7575 #ifdef CONFIG_PCI_IOV
7577 return igb_pci_disable_sriov(dev);
7579 return igb_pci_enable_sriov(dev, num_vfs);
7584 #ifdef CONFIG_NET_POLL_CONTROLLER
7585 /* Polling 'interrupt' - used by things like netconsole to send skbs
7586 * without having to re-enable interrupts. It's not called while
7587 * the interrupt routine is executing.
7589 static void igb_netpoll(struct net_device *netdev)
7591 struct igb_adapter *adapter = netdev_priv(netdev);
7592 struct e1000_hw *hw = &adapter->hw;
7593 struct igb_q_vector *q_vector;
7596 for (i = 0; i < adapter->num_q_vectors; i++) {
7597 q_vector = adapter->q_vector[i];
7598 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7599 wr32(E1000_EIMC, q_vector->eims_value);
7601 igb_irq_disable(adapter);
7602 napi_schedule(&q_vector->napi);
7605 #endif /* CONFIG_NET_POLL_CONTROLLER */
7608 * igb_io_error_detected - called when PCI error is detected
7609 * @pdev: Pointer to PCI device
7610 * @state: The current pci connection state
7612 * This function is called after a PCI bus error affecting
7613 * this device has been detected.
7615 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7616 pci_channel_state_t state)
7618 struct net_device *netdev = pci_get_drvdata(pdev);
7619 struct igb_adapter *adapter = netdev_priv(netdev);
7621 netif_device_detach(netdev);
7623 if (state == pci_channel_io_perm_failure)
7624 return PCI_ERS_RESULT_DISCONNECT;
7626 if (netif_running(netdev))
7628 pci_disable_device(pdev);
7630 /* Request a slot slot reset. */
7631 return PCI_ERS_RESULT_NEED_RESET;
7635 * igb_io_slot_reset - called after the pci bus has been reset.
7636 * @pdev: Pointer to PCI device
7638 * Restart the card from scratch, as if from a cold-boot. Implementation
7639 * resembles the first-half of the igb_resume routine.
7641 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7643 struct net_device *netdev = pci_get_drvdata(pdev);
7644 struct igb_adapter *adapter = netdev_priv(netdev);
7645 struct e1000_hw *hw = &adapter->hw;
7646 pci_ers_result_t result;
7649 if (pci_enable_device_mem(pdev)) {
7651 "Cannot re-enable PCI device after reset.\n");
7652 result = PCI_ERS_RESULT_DISCONNECT;
7654 pci_set_master(pdev);
7655 pci_restore_state(pdev);
7656 pci_save_state(pdev);
7658 pci_enable_wake(pdev, PCI_D3hot, 0);
7659 pci_enable_wake(pdev, PCI_D3cold, 0);
7662 wr32(E1000_WUS, ~0);
7663 result = PCI_ERS_RESULT_RECOVERED;
7666 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7669 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7671 /* non-fatal, continue */
7678 * igb_io_resume - called when traffic can start flowing again.
7679 * @pdev: Pointer to PCI device
7681 * This callback is called when the error recovery driver tells us that
7682 * its OK to resume normal operation. Implementation resembles the
7683 * second-half of the igb_resume routine.
7685 static void igb_io_resume(struct pci_dev *pdev)
7687 struct net_device *netdev = pci_get_drvdata(pdev);
7688 struct igb_adapter *adapter = netdev_priv(netdev);
7690 if (netif_running(netdev)) {
7691 if (igb_up(adapter)) {
7692 dev_err(&pdev->dev, "igb_up failed after reset\n");
7697 netif_device_attach(netdev);
7699 /* let the f/w know that the h/w is now under the control of the
7702 igb_get_hw_control(adapter);
7705 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7708 u32 rar_low, rar_high;
7709 struct e1000_hw *hw = &adapter->hw;
7711 /* HW expects these in little endian so we reverse the byte order
7712 * from network order (big endian) to little endian
7714 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7715 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7716 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7718 /* Indicate to hardware the Address is Valid. */
7719 rar_high |= E1000_RAH_AV;
7721 if (hw->mac.type == e1000_82575)
7722 rar_high |= E1000_RAH_POOL_1 * qsel;
7724 rar_high |= E1000_RAH_POOL_1 << qsel;
7726 wr32(E1000_RAL(index), rar_low);
7728 wr32(E1000_RAH(index), rar_high);
7732 static int igb_set_vf_mac(struct igb_adapter *adapter,
7733 int vf, unsigned char *mac_addr)
7735 struct e1000_hw *hw = &adapter->hw;
7736 /* VF MAC addresses start at end of receive addresses and moves
7737 * towards the first, as a result a collision should not be possible
7739 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7741 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7743 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7748 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7750 struct igb_adapter *adapter = netdev_priv(netdev);
7751 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7753 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7754 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7755 dev_info(&adapter->pdev->dev,
7756 "Reload the VF driver to make this change effective.");
7757 if (test_bit(__IGB_DOWN, &adapter->state)) {
7758 dev_warn(&adapter->pdev->dev,
7759 "The VF MAC address has been set, but the PF device is not up.\n");
7760 dev_warn(&adapter->pdev->dev,
7761 "Bring the PF device up before attempting to use the VF device.\n");
7763 return igb_set_vf_mac(adapter, vf, mac);
7766 static int igb_link_mbps(int internal_link_speed)
7768 switch (internal_link_speed) {
7778 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7785 /* Calculate the rate factor values to set */
7786 rf_int = link_speed / tx_rate;
7787 rf_dec = (link_speed - (rf_int * tx_rate));
7788 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7791 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7792 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7793 E1000_RTTBCNRC_RF_INT_MASK);
7794 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7799 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7800 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7801 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7803 wr32(E1000_RTTBCNRM, 0x14);
7804 wr32(E1000_RTTBCNRC, bcnrc_val);
7807 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7809 int actual_link_speed, i;
7810 bool reset_rate = false;
7812 /* VF TX rate limit was not set or not supported */
7813 if ((adapter->vf_rate_link_speed == 0) ||
7814 (adapter->hw.mac.type != e1000_82576))
7817 actual_link_speed = igb_link_mbps(adapter->link_speed);
7818 if (actual_link_speed != adapter->vf_rate_link_speed) {
7820 adapter->vf_rate_link_speed = 0;
7821 dev_info(&adapter->pdev->dev,
7822 "Link speed has been changed. VF Transmit rate is disabled\n");
7825 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7827 adapter->vf_data[i].tx_rate = 0;
7829 igb_set_vf_rate_limit(&adapter->hw, i,
7830 adapter->vf_data[i].tx_rate,
7835 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7836 int min_tx_rate, int max_tx_rate)
7838 struct igb_adapter *adapter = netdev_priv(netdev);
7839 struct e1000_hw *hw = &adapter->hw;
7840 int actual_link_speed;
7842 if (hw->mac.type != e1000_82576)
7848 actual_link_speed = igb_link_mbps(adapter->link_speed);
7849 if ((vf >= adapter->vfs_allocated_count) ||
7850 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7851 (max_tx_rate < 0) ||
7852 (max_tx_rate > actual_link_speed))
7855 adapter->vf_rate_link_speed = actual_link_speed;
7856 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7857 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7862 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7865 struct igb_adapter *adapter = netdev_priv(netdev);
7866 struct e1000_hw *hw = &adapter->hw;
7867 u32 reg_val, reg_offset;
7869 if (!adapter->vfs_allocated_count)
7872 if (vf >= adapter->vfs_allocated_count)
7875 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7876 reg_val = rd32(reg_offset);
7878 reg_val |= ((1 << vf) |
7879 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7881 reg_val &= ~((1 << vf) |
7882 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7883 wr32(reg_offset, reg_val);
7885 adapter->vf_data[vf].spoofchk_enabled = setting;
7889 static int igb_ndo_get_vf_config(struct net_device *netdev,
7890 int vf, struct ifla_vf_info *ivi)
7892 struct igb_adapter *adapter = netdev_priv(netdev);
7893 if (vf >= adapter->vfs_allocated_count)
7896 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7897 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7898 ivi->min_tx_rate = 0;
7899 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7900 ivi->qos = adapter->vf_data[vf].pf_qos;
7901 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7905 static void igb_vmm_control(struct igb_adapter *adapter)
7907 struct e1000_hw *hw = &adapter->hw;
7910 switch (hw->mac.type) {
7916 /* replication is not supported for 82575 */
7919 /* notify HW that the MAC is adding vlan tags */
7920 reg = rd32(E1000_DTXCTL);
7921 reg |= E1000_DTXCTL_VLAN_ADDED;
7922 wr32(E1000_DTXCTL, reg);
7925 /* enable replication vlan tag stripping */
7926 reg = rd32(E1000_RPLOLR);
7927 reg |= E1000_RPLOLR_STRVLAN;
7928 wr32(E1000_RPLOLR, reg);
7931 /* none of the above registers are supported by i350 */
7935 if (adapter->vfs_allocated_count) {
7936 igb_vmdq_set_loopback_pf(hw, true);
7937 igb_vmdq_set_replication_pf(hw, true);
7938 igb_vmdq_set_anti_spoofing_pf(hw, true,
7939 adapter->vfs_allocated_count);
7941 igb_vmdq_set_loopback_pf(hw, false);
7942 igb_vmdq_set_replication_pf(hw, false);
7946 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7948 struct e1000_hw *hw = &adapter->hw;
7952 if (hw->mac.type > e1000_82580) {
7953 if (adapter->flags & IGB_FLAG_DMAC) {
7956 /* force threshold to 0. */
7957 wr32(E1000_DMCTXTH, 0);
7959 /* DMA Coalescing high water mark needs to be greater
7960 * than the Rx threshold. Set hwm to PBA - max frame
7961 * size in 16B units, capping it at PBA - 6KB.
7963 hwm = 64 * pba - adapter->max_frame_size / 16;
7964 if (hwm < 64 * (pba - 6))
7965 hwm = 64 * (pba - 6);
7966 reg = rd32(E1000_FCRTC);
7967 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7968 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7969 & E1000_FCRTC_RTH_COAL_MASK);
7970 wr32(E1000_FCRTC, reg);
7972 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7973 * frame size, capping it at PBA - 10KB.
7975 dmac_thr = pba - adapter->max_frame_size / 512;
7976 if (dmac_thr < pba - 10)
7977 dmac_thr = pba - 10;
7978 reg = rd32(E1000_DMACR);
7979 reg &= ~E1000_DMACR_DMACTHR_MASK;
7980 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7981 & E1000_DMACR_DMACTHR_MASK);
7983 /* transition to L0x or L1 if available..*/
7984 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7986 /* watchdog timer= +-1000 usec in 32usec intervals */
7989 /* Disable BMC-to-OS Watchdog Enable */
7990 if (hw->mac.type != e1000_i354)
7991 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7993 wr32(E1000_DMACR, reg);
7995 /* no lower threshold to disable
7996 * coalescing(smart fifb)-UTRESH=0
7998 wr32(E1000_DMCRTRH, 0);
8000 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8002 wr32(E1000_DMCTLX, reg);
8004 /* free space in tx packet buffer to wake from
8007 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8008 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8010 /* make low power state decision controlled
8013 reg = rd32(E1000_PCIEMISC);
8014 reg &= ~E1000_PCIEMISC_LX_DECISION;
8015 wr32(E1000_PCIEMISC, reg);
8016 } /* endif adapter->dmac is not disabled */
8017 } else if (hw->mac.type == e1000_82580) {
8018 u32 reg = rd32(E1000_PCIEMISC);
8020 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8021 wr32(E1000_DMACR, 0);
8026 * igb_read_i2c_byte - Reads 8 bit word over I2C
8027 * @hw: pointer to hardware structure
8028 * @byte_offset: byte offset to read
8029 * @dev_addr: device address
8032 * Performs byte read operation over I2C interface at
8033 * a specified device address.
8035 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8036 u8 dev_addr, u8 *data)
8038 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8039 struct i2c_client *this_client = adapter->i2c_client;
8044 return E1000_ERR_I2C;
8046 swfw_mask = E1000_SWFW_PHY0_SM;
8048 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8049 return E1000_ERR_SWFW_SYNC;
8051 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8052 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8055 return E1000_ERR_I2C;
8063 * igb_write_i2c_byte - Writes 8 bit word over I2C
8064 * @hw: pointer to hardware structure
8065 * @byte_offset: byte offset to write
8066 * @dev_addr: device address
8067 * @data: value to write
8069 * Performs byte write operation over I2C interface at
8070 * a specified device address.
8072 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8073 u8 dev_addr, u8 data)
8075 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8076 struct i2c_client *this_client = adapter->i2c_client;
8078 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8081 return E1000_ERR_I2C;
8083 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8084 return E1000_ERR_SWFW_SYNC;
8085 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8086 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8089 return E1000_ERR_I2C;
8095 int igb_reinit_queues(struct igb_adapter *adapter)
8097 struct net_device *netdev = adapter->netdev;
8098 struct pci_dev *pdev = adapter->pdev;
8101 if (netif_running(netdev))
8104 igb_reset_interrupt_capability(adapter);
8106 if (igb_init_interrupt_scheme(adapter, true)) {
8107 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8111 if (netif_running(netdev))
8112 err = igb_open(netdev);