1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include <linux/bitops.h>
33 #include <linux/types.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/cpumask.h>
37 #include <linux/aer.h>
38 #include <linux/if_vlan.h>
39 #include <linux/jiffies.h>
41 #include <linux/clocksource.h>
42 #include <linux/net_tstamp.h>
43 #include <linux/ptp_clock_kernel.h>
45 #include "ixgbe_type.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb.h"
48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
50 #include "ixgbe_fcoe.h"
51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
52 #ifdef CONFIG_IXGBE_DCA
53 #include <linux/dca.h>
56 #include <net/busy_poll.h>
58 #ifdef CONFIG_NET_RX_BUSY_POLL
59 #define BP_EXTENDED_STATS
61 /* common prefix used by pr_<> macros */
63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65 /* TX/RX descriptor defines */
66 #define IXGBE_DEFAULT_TXD 512
67 #define IXGBE_DEFAULT_TX_WORK 256
68 #define IXGBE_MAX_TXD 4096
69 #define IXGBE_MIN_TXD 64
71 #if (PAGE_SIZE < 8192)
72 #define IXGBE_DEFAULT_RXD 512
74 #define IXGBE_DEFAULT_RXD 128
76 #define IXGBE_MAX_RXD 4096
77 #define IXGBE_MIN_RXD 64
80 #define IXGBE_MIN_FCRTL 0x40
81 #define IXGBE_MAX_FCRTL 0x7FF80
82 #define IXGBE_MIN_FCRTH 0x600
83 #define IXGBE_MAX_FCRTH 0x7FFF0
84 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
85 #define IXGBE_MIN_FCPAUSE 0
86 #define IXGBE_MAX_FCPAUSE 0xFFFF
88 /* Supported Rx Buffer Sizes */
89 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
90 #define IXGBE_RXBUFFER_2K 2048
91 #define IXGBE_RXBUFFER_3K 3072
92 #define IXGBE_RXBUFFER_4K 4096
93 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
96 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
97 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
98 * this adds up to 448 bytes of extra data.
100 * Since netdev_alloc_skb now allocates a page fragment we can use a value
101 * of 256 and the resultant skb will have a truesize of 960 or less.
103 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
105 /* How many Rx Buffers do we bundle into one write to the hardware ? */
106 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
108 enum ixgbe_tx_flags {
110 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
111 IXGBE_TX_FLAGS_TSO = 0x02,
112 IXGBE_TX_FLAGS_TSTAMP = 0x04,
115 IXGBE_TX_FLAGS_CC = 0x08,
116 IXGBE_TX_FLAGS_IPV4 = 0x10,
117 IXGBE_TX_FLAGS_CSUM = 0x20,
119 /* software defined flags */
120 IXGBE_TX_FLAGS_SW_VLAN = 0x40,
121 IXGBE_TX_FLAGS_FCOE = 0x80,
125 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
126 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
127 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
128 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
130 #define IXGBE_MAX_VF_MC_ENTRIES 30
131 #define IXGBE_MAX_VF_FUNCTIONS 64
132 #define IXGBE_MAX_VFTA_ENTRIES 128
133 #define MAX_EMULATION_MAC_ADDRS 16
134 #define IXGBE_MAX_PF_MACVLANS 15
135 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
136 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
137 #define IXGBE_X540_VF_DEVICE_ID 0x1515
139 struct vf_data_storage {
140 unsigned char vf_mac_addresses[ETH_ALEN];
141 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
142 u16 num_vf_mc_hashes;
143 u16 default_vf_vlan_id;
147 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
160 u8 vf_macvlan[ETH_ALEN];
163 #define IXGBE_MAX_TXD_PWR 14
164 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
166 /* Tx Descriptors needed, worst case */
167 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
168 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
170 /* wrapper around a pointer to a socket buffer,
171 * so a DMA handle can be stored along with the buffer */
172 struct ixgbe_tx_buffer {
173 union ixgbe_adv_tx_desc *next_to_watch;
174 unsigned long time_stamp;
176 unsigned int bytecount;
177 unsigned short gso_segs;
179 DEFINE_DMA_UNMAP_ADDR(dma);
180 DEFINE_DMA_UNMAP_LEN(len);
184 struct ixgbe_rx_buffer {
188 unsigned int page_offset;
191 struct ixgbe_queue_stats {
194 #ifdef BP_EXTENDED_STATS
198 #endif /* BP_EXTENDED_STATS */
201 struct ixgbe_tx_queue_stats {
207 struct ixgbe_rx_queue_stats {
211 u64 alloc_rx_page_failed;
212 u64 alloc_rx_buff_failed;
216 enum ixgbe_ring_state_t {
217 __IXGBE_TX_FDIR_INIT_DONE,
218 __IXGBE_TX_XPS_INIT_DONE,
219 __IXGBE_TX_DETECT_HANG,
220 __IXGBE_HANG_CHECK_ARMED,
221 __IXGBE_RX_RSC_ENABLED,
222 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
226 struct ixgbe_fwd_adapter {
227 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
228 struct net_device *netdev;
229 struct ixgbe_adapter *real_adapter;
230 unsigned int tx_base_queue;
231 unsigned int rx_base_queue;
235 #define check_for_tx_hang(ring) \
236 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
237 #define set_check_for_tx_hang(ring) \
238 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
239 #define clear_check_for_tx_hang(ring) \
240 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
241 #define ring_is_rsc_enabled(ring) \
242 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
243 #define set_ring_rsc_enabled(ring) \
244 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
245 #define clear_ring_rsc_enabled(ring) \
246 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
248 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
249 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
250 struct net_device *netdev; /* netdev ring belongs to */
251 struct device *dev; /* device for DMA mapping */
252 struct ixgbe_fwd_adapter *l2_accel_priv;
253 void *desc; /* descriptor ring memory */
255 struct ixgbe_tx_buffer *tx_buffer_info;
256 struct ixgbe_rx_buffer *rx_buffer_info;
258 unsigned long last_rx_timestamp;
261 dma_addr_t dma; /* phys. address of descriptor ring */
262 unsigned int size; /* length in bytes */
264 u16 count; /* amount of descriptors */
266 u8 queue_index; /* needed for multiqueue queue management */
267 u8 reg_idx; /* holds the special value that gets
268 * the hardware register offset
269 * associated with this ring, which is
270 * different for DCB and RSS modes
284 struct ixgbe_queue_stats stats;
285 struct u64_stats_sync syncp;
287 struct ixgbe_tx_queue_stats tx_stats;
288 struct ixgbe_rx_queue_stats rx_stats;
290 } ____cacheline_internodealigned_in_smp;
292 enum ixgbe_ring_f_enum {
294 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
299 #endif /* IXGBE_FCOE */
301 RING_F_ARRAY_SIZE /* must be last in enum set */
304 #define IXGBE_MAX_RSS_INDICES 16
305 #define IXGBE_MAX_VMDQ_INDICES 64
306 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
307 #define IXGBE_MAX_FCOE_INDICES 8
308 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
309 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
310 #define IXGBE_MAX_L2A_QUEUES 4
311 #define IXGBE_MAX_L2A_QUEUES 4
312 #define IXGBE_BAD_L2A_QUEUE 3
313 #define IXGBE_MAX_MACVLANS 31
314 #define IXGBE_MAX_DCBMACVLANS 8
316 struct ixgbe_ring_feature {
317 u16 limit; /* upper limit on feature indices */
318 u16 indices; /* current value of indices */
319 u16 mask; /* Mask used for feature to ring mapping */
320 u16 offset; /* offset to start of feature */
321 } ____cacheline_internodealigned_in_smp;
323 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
324 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
325 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
328 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
329 * this is twice the size of a half page we need to double the page order
330 * for FCoE enabled Rx queues.
332 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
335 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
336 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
339 return IXGBE_RXBUFFER_2K;
342 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
345 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
346 return (PAGE_SIZE < 8192) ? 1 : 0;
350 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
352 struct ixgbe_ring_container {
353 struct ixgbe_ring *ring; /* pointer to linked list of rings */
354 unsigned int total_bytes; /* total bytes processed this int */
355 unsigned int total_packets; /* total packets processed this int */
356 u16 work_limit; /* total work allowed per interrupt */
357 u8 count; /* total number of rings in vector */
358 u8 itr; /* current ITR setting for ring */
361 /* iterator for handling rings in ring container */
362 #define ixgbe_for_each_ring(pos, head) \
363 for (pos = (head).ring; pos != NULL; pos = pos->next)
365 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
367 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
369 /* MAX_Q_VECTORS of these are allocated,
370 * but we only use one per queue-specific vector.
372 struct ixgbe_q_vector {
373 struct ixgbe_adapter *adapter;
374 #ifdef CONFIG_IXGBE_DCA
375 int cpu; /* CPU for DCA */
377 u16 v_idx; /* index of q_vector within array, also used for
378 * finding the bit in EICR and friends that
379 * represents the vector for this ring */
380 u16 itr; /* Interrupt throttle rate written to EITR */
381 struct ixgbe_ring_container rx, tx;
383 struct napi_struct napi;
384 cpumask_t affinity_mask;
386 struct rcu_head rcu; /* to avoid race with update stats on free */
387 char name[IFNAMSIZ + 9];
389 #ifdef CONFIG_NET_RX_BUSY_POLL
391 #define IXGBE_QV_STATE_IDLE 0
392 #define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */
393 #define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */
394 #define IXGBE_QV_STATE_DISABLED 4 /* QV is disabled */
395 #define IXGBE_QV_OWNED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL)
396 #define IXGBE_QV_LOCKED (IXGBE_QV_OWNED | IXGBE_QV_STATE_DISABLED)
397 #define IXGBE_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
398 #define IXGBE_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
399 #define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD)
400 #define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD)
402 #endif /* CONFIG_NET_RX_BUSY_POLL */
404 /* for dynamic allocation of rings associated with this q_vector */
405 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
407 #ifdef CONFIG_NET_RX_BUSY_POLL
408 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
411 spin_lock_init(&q_vector->lock);
412 q_vector->state = IXGBE_QV_STATE_IDLE;
415 /* called from the device poll routine to get ownership of a q_vector */
416 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
419 spin_lock_bh(&q_vector->lock);
420 if (q_vector->state & IXGBE_QV_LOCKED) {
421 WARN_ON(q_vector->state & IXGBE_QV_STATE_NAPI);
422 q_vector->state |= IXGBE_QV_STATE_NAPI_YIELD;
424 #ifdef BP_EXTENDED_STATS
425 q_vector->tx.ring->stats.yields++;
428 /* we don't care if someone yielded */
429 q_vector->state = IXGBE_QV_STATE_NAPI;
431 spin_unlock_bh(&q_vector->lock);
435 /* returns true is someone tried to get the qv while napi had it */
436 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
439 spin_lock_bh(&q_vector->lock);
440 WARN_ON(q_vector->state & (IXGBE_QV_STATE_POLL |
441 IXGBE_QV_STATE_NAPI_YIELD));
443 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD)
445 /* will reset state to idle, unless QV is disabled */
446 q_vector->state &= IXGBE_QV_STATE_DISABLED;
447 spin_unlock_bh(&q_vector->lock);
451 /* called from ixgbe_low_latency_poll() */
452 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
455 spin_lock_bh(&q_vector->lock);
456 if ((q_vector->state & IXGBE_QV_LOCKED)) {
457 q_vector->state |= IXGBE_QV_STATE_POLL_YIELD;
459 #ifdef BP_EXTENDED_STATS
460 q_vector->rx.ring->stats.yields++;
463 /* preserve yield marks */
464 q_vector->state |= IXGBE_QV_STATE_POLL;
466 spin_unlock_bh(&q_vector->lock);
470 /* returns true if someone tried to get the qv while it was locked */
471 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
474 spin_lock_bh(&q_vector->lock);
475 WARN_ON(q_vector->state & (IXGBE_QV_STATE_NAPI));
477 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD)
479 /* will reset state to idle, unless QV is disabled */
480 q_vector->state &= IXGBE_QV_STATE_DISABLED;
481 spin_unlock_bh(&q_vector->lock);
485 /* true if a socket is polling, even if it did not get the lock */
486 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
488 WARN_ON(!(q_vector->state & IXGBE_QV_OWNED));
489 return q_vector->state & IXGBE_QV_USER_PEND;
492 /* false if QV is currently owned */
493 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
496 spin_lock_bh(&q_vector->lock);
497 if (q_vector->state & IXGBE_QV_OWNED)
499 q_vector->state |= IXGBE_QV_STATE_DISABLED;
500 spin_unlock_bh(&q_vector->lock);
505 #else /* CONFIG_NET_RX_BUSY_POLL */
506 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
510 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
515 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
520 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
525 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
530 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
535 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
540 #endif /* CONFIG_NET_RX_BUSY_POLL */
542 #ifdef CONFIG_IXGBE_HWMON
544 #define IXGBE_HWMON_TYPE_LOC 0
545 #define IXGBE_HWMON_TYPE_TEMP 1
546 #define IXGBE_HWMON_TYPE_CAUTION 2
547 #define IXGBE_HWMON_TYPE_MAX 3
550 struct device_attribute dev_attr;
552 struct ixgbe_thermal_diode_data *sensor;
557 struct attribute_group group;
558 const struct attribute_group *groups[2];
559 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
560 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
561 unsigned int n_hwmon;
563 #endif /* CONFIG_IXGBE_HWMON */
566 * microsecond values for various ITR rates shifted by 2 to fit itr register
567 * with the first 3 bits reserved 0
569 #define IXGBE_MIN_RSC_ITR 24
570 #define IXGBE_100K_ITR 40
571 #define IXGBE_20K_ITR 200
572 #define IXGBE_10K_ITR 400
573 #define IXGBE_8K_ITR 500
575 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
576 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
577 const u32 stat_err_bits)
579 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
582 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
584 u16 ntc = ring->next_to_clean;
585 u16 ntu = ring->next_to_use;
587 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
590 static inline void ixgbe_write_tail(struct ixgbe_ring *ring, u32 value)
592 writel(value, ring->tail);
595 #define IXGBE_RX_DESC(R, i) \
596 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
597 #define IXGBE_TX_DESC(R, i) \
598 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
599 #define IXGBE_TX_CTXTDESC(R, i) \
600 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
602 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
604 /* Use 3K as the baby jumbo frame size for FCoE */
605 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
606 #endif /* IXGBE_FCOE */
608 #define OTHER_VECTOR 1
609 #define NON_Q_VECTORS (OTHER_VECTOR)
611 #define MAX_MSIX_VECTORS_82599 64
612 #define MAX_Q_VECTORS_82599 64
613 #define MAX_MSIX_VECTORS_82598 18
614 #define MAX_Q_VECTORS_82598 16
616 struct ixgbe_mac_addr {
619 u16 state; /* bitmask */
621 #define IXGBE_MAC_STATE_DEFAULT 0x1
622 #define IXGBE_MAC_STATE_MODIFIED 0x2
623 #define IXGBE_MAC_STATE_IN_USE 0x4
625 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
626 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
628 #define MIN_MSIX_Q_VECTORS 1
629 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
631 /* default to trying for four seconds */
632 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
634 /* board specific private data structure */
635 struct ixgbe_adapter {
636 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
637 /* OS defined structs */
638 struct net_device *netdev;
639 struct pci_dev *pdev;
643 /* Some features need tri-state capability,
644 * thus the additional *_CAPABLE flags.
647 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0)
648 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
649 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2)
650 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
651 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
652 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
653 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
654 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7)
655 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
656 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
657 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
658 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
659 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
660 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
661 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
662 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
663 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
664 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
665 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
666 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
667 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
668 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
669 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
670 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
673 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
674 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
675 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
676 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
677 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
678 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
679 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
680 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
681 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
682 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
683 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
684 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11)
686 /* Tx fast path data */
691 /* Rx fast path data */
696 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
700 u32 tx_timeout_count;
703 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
704 int num_rx_pools; /* == num_rx_queues in 82598 */
705 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
706 u64 hw_csum_rx_error;
707 u64 hw_rx_no_dma_resources;
711 u32 alloc_rx_page_failed;
712 u32 alloc_rx_buff_failed;
714 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
717 struct ieee_pfc *ixgbe_ieee_pfc;
718 struct ieee_ets *ixgbe_ieee_ets;
719 struct ixgbe_dcb_config dcb_cfg;
720 struct ixgbe_dcb_config temp_dcb_cfg;
723 enum ixgbe_fc_mode last_lfc_mode;
725 int num_q_vectors; /* current number of q_vectors for device */
726 int max_q_vectors; /* true count of q_vectors for device */
727 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
728 struct msix_entry *msix_entries;
731 struct ixgbe_ring test_tx_ring;
732 struct ixgbe_ring test_rx_ring;
734 /* structs defined in ixgbe_hw.h */
737 struct ixgbe_hw_stats stats;
740 unsigned int tx_ring_count;
741 unsigned int rx_ring_count;
745 unsigned long link_check_timeout;
747 struct timer_list service_timer;
748 struct work_struct service_task;
750 struct hlist_head fdir_filter_list;
751 unsigned long fdir_overflow; /* number of times ATR was backed off */
752 union ixgbe_atr_input fdir_mask;
753 int fdir_filter_count;
756 spinlock_t fdir_perfect_lock;
759 struct ixgbe_fcoe fcoe;
760 #endif /* IXGBE_FCOE */
761 u8 __iomem *io_addr; /* Mainly for iounmap use */
773 struct ptp_clock *ptp_clock;
774 struct ptp_clock_info ptp_caps;
775 struct work_struct ptp_tx_work;
776 struct sk_buff *ptp_tx_skb;
777 struct hwtstamp_config tstamp_config;
778 unsigned long ptp_tx_start;
779 unsigned long last_overflow_check;
780 unsigned long last_rx_ptp_check;
781 spinlock_t tmreg_lock;
782 struct cyclecounter cc;
783 struct timecounter tc;
787 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
788 unsigned int num_vfs;
789 struct vf_data_storage *vfinfo;
790 int vf_rate_link_speed;
791 struct vf_macvlans vf_mvs;
792 struct vf_macvlans *mv_list;
794 u32 timer_event_accumulator;
796 struct ixgbe_mac_addr *mac_table;
797 struct kobject *info_kobj;
798 #ifdef CONFIG_IXGBE_HWMON
799 struct hwmon_buff *ixgbe_hwmon_buff;
800 #endif /* CONFIG_IXGBE_HWMON */
801 #ifdef CONFIG_DEBUG_FS
802 struct dentry *ixgbe_dbg_adapter;
803 #endif /*CONFIG_DEBUG_FS*/
806 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */
809 struct ixgbe_fdir_filter {
810 struct hlist_node fdir_node;
811 union ixgbe_atr_input filter;
822 __IXGBE_SERVICE_SCHED,
823 __IXGBE_SERVICE_INITED,
826 __IXGBE_PTP_TX_IN_PROGRESS,
830 union { /* Union defining head/tail partner */
831 struct sk_buff *head;
832 struct sk_buff *tail;
838 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
846 extern struct ixgbe_info ixgbe_82598_info;
847 extern struct ixgbe_info ixgbe_82599_info;
848 extern struct ixgbe_info ixgbe_X540_info;
849 #ifdef CONFIG_IXGBE_DCB
850 extern const struct dcbnl_rtnl_ops dcbnl_ops;
853 extern char ixgbe_driver_name[];
854 extern const char ixgbe_driver_version[];
856 extern char ixgbe_default_device_descr[];
857 #endif /* IXGBE_FCOE */
859 void ixgbe_up(struct ixgbe_adapter *adapter);
860 void ixgbe_down(struct ixgbe_adapter *adapter);
861 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
862 void ixgbe_reset(struct ixgbe_adapter *adapter);
863 void ixgbe_set_ethtool_ops(struct net_device *netdev);
864 int ixgbe_setup_rx_resources(struct ixgbe_ring *);
865 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
866 void ixgbe_free_rx_resources(struct ixgbe_ring *);
867 void ixgbe_free_tx_resources(struct ixgbe_ring *);
868 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
869 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
870 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
871 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
872 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
873 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
875 #ifdef CONFIG_PCI_IOV
876 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
878 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
879 u8 *addr, u16 queue);
880 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
881 u8 *addr, u16 queue);
882 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
883 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
884 struct ixgbe_ring *);
885 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
886 struct ixgbe_tx_buffer *);
887 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
888 void ixgbe_write_eitr(struct ixgbe_q_vector *);
889 int ixgbe_poll(struct napi_struct *napi, int budget);
890 int ethtool_ioctl(struct ifreq *ifr);
891 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
892 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
893 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
894 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
895 union ixgbe_atr_hash_dword input,
896 union ixgbe_atr_hash_dword common,
898 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
899 union ixgbe_atr_input *input_mask);
900 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
901 union ixgbe_atr_input *input,
902 u16 soft_id, u8 queue);
903 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
904 union ixgbe_atr_input *input,
906 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
907 union ixgbe_atr_input *mask);
908 void ixgbe_set_rx_mode(struct net_device *netdev);
909 #ifdef CONFIG_IXGBE_DCB
910 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
912 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
913 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
914 void ixgbe_do_reset(struct net_device *netdev);
915 #ifdef CONFIG_IXGBE_HWMON
916 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
917 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
918 #endif /* CONFIG_IXGBE_HWMON */
920 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
921 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
923 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
924 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
925 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
926 struct scatterlist *sgl, unsigned int sgc);
927 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
928 struct scatterlist *sgl, unsigned int sgc);
929 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
930 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
931 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
932 int ixgbe_fcoe_enable(struct net_device *netdev);
933 int ixgbe_fcoe_disable(struct net_device *netdev);
934 #ifdef CONFIG_IXGBE_DCB
935 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
936 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
937 #endif /* CONFIG_IXGBE_DCB */
938 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
939 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
940 struct netdev_fcoe_hbainfo *info);
941 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
942 #endif /* IXGBE_FCOE */
943 #ifdef CONFIG_DEBUG_FS
944 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
945 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
946 void ixgbe_dbg_init(void);
947 void ixgbe_dbg_exit(void);
949 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
950 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
951 static inline void ixgbe_dbg_init(void) {}
952 static inline void ixgbe_dbg_exit(void) {}
953 #endif /* CONFIG_DEBUG_FS */
954 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
956 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
959 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
960 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
961 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
962 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
963 void __ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
964 struct sk_buff *skb);
965 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
966 union ixgbe_adv_rx_desc *rx_desc,
969 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
972 __ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, skb);
975 * Update the last_rx_timestamp timer in order to enable watchdog check
976 * for error case of latched timestamp on a dropped packet.
978 rx_ring->last_rx_timestamp = jiffies;
981 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
982 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
983 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
984 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
985 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
986 #ifdef CONFIG_PCI_IOV
987 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
990 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
991 struct ixgbe_adapter *adapter,
992 struct ixgbe_ring *tx_ring);
993 #endif /* _IXGBE_H_ */