1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include <linux/bitops.h>
33 #include <linux/types.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/cpumask.h>
37 #include <linux/aer.h>
38 #include <linux/if_vlan.h>
39 #include <linux/jiffies.h>
41 #include <linux/timecounter.h>
42 #include <linux/net_tstamp.h>
43 #include <linux/ptp_clock_kernel.h>
45 #include "ixgbe_type.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb.h"
48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
50 #include "ixgbe_fcoe.h"
51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
52 #ifdef CONFIG_IXGBE_DCA
53 #include <linux/dca.h>
56 #include <net/busy_poll.h>
58 #ifdef CONFIG_NET_RX_BUSY_POLL
59 #define BP_EXTENDED_STATS
61 /* common prefix used by pr_<> macros */
63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65 /* TX/RX descriptor defines */
66 #define IXGBE_DEFAULT_TXD 512
67 #define IXGBE_DEFAULT_TX_WORK 256
68 #define IXGBE_MAX_TXD 4096
69 #define IXGBE_MIN_TXD 64
71 #if (PAGE_SIZE < 8192)
72 #define IXGBE_DEFAULT_RXD 512
74 #define IXGBE_DEFAULT_RXD 128
76 #define IXGBE_MAX_RXD 4096
77 #define IXGBE_MIN_RXD 64
79 #define IXGBE_ETH_P_LLDP 0x88CC
82 #define IXGBE_MIN_FCRTL 0x40
83 #define IXGBE_MAX_FCRTL 0x7FF80
84 #define IXGBE_MIN_FCRTH 0x600
85 #define IXGBE_MAX_FCRTH 0x7FFF0
86 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
87 #define IXGBE_MIN_FCPAUSE 0
88 #define IXGBE_MAX_FCPAUSE 0xFFFF
90 /* Supported Rx Buffer Sizes */
91 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
92 #define IXGBE_RXBUFFER_2K 2048
93 #define IXGBE_RXBUFFER_3K 3072
94 #define IXGBE_RXBUFFER_4K 4096
95 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
98 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
99 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
100 * this adds up to 448 bytes of extra data.
102 * Since netdev_alloc_skb now allocates a page fragment we can use a value
103 * of 256 and the resultant skb will have a truesize of 960 or less.
105 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
107 /* How many Rx Buffers do we bundle into one write to the hardware ? */
108 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
110 enum ixgbe_tx_flags {
112 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
113 IXGBE_TX_FLAGS_TSO = 0x02,
114 IXGBE_TX_FLAGS_TSTAMP = 0x04,
117 IXGBE_TX_FLAGS_CC = 0x08,
118 IXGBE_TX_FLAGS_IPV4 = 0x10,
119 IXGBE_TX_FLAGS_CSUM = 0x20,
121 /* software defined flags */
122 IXGBE_TX_FLAGS_SW_VLAN = 0x40,
123 IXGBE_TX_FLAGS_FCOE = 0x80,
127 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
128 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
129 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
130 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
132 #define IXGBE_MAX_VF_MC_ENTRIES 30
133 #define IXGBE_MAX_VF_FUNCTIONS 64
134 #define IXGBE_MAX_VFTA_ENTRIES 128
135 #define MAX_EMULATION_MAC_ADDRS 16
136 #define IXGBE_MAX_PF_MACVLANS 15
137 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
138 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
139 #define IXGBE_X540_VF_DEVICE_ID 0x1515
141 struct vf_data_storage {
142 unsigned char vf_mac_addresses[ETH_ALEN];
143 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
144 u16 num_vf_mc_hashes;
145 u16 default_vf_vlan_id;
149 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
154 bool rss_query_enabled;
163 u8 vf_macvlan[ETH_ALEN];
166 #define IXGBE_MAX_TXD_PWR 14
167 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
169 /* Tx Descriptors needed, worst case */
170 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
171 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
173 /* wrapper around a pointer to a socket buffer,
174 * so a DMA handle can be stored along with the buffer */
175 struct ixgbe_tx_buffer {
176 union ixgbe_adv_tx_desc *next_to_watch;
177 unsigned long time_stamp;
179 unsigned int bytecount;
180 unsigned short gso_segs;
182 DEFINE_DMA_UNMAP_ADDR(dma);
183 DEFINE_DMA_UNMAP_LEN(len);
187 struct ixgbe_rx_buffer {
191 unsigned int page_offset;
194 struct ixgbe_queue_stats {
197 #ifdef BP_EXTENDED_STATS
201 #endif /* BP_EXTENDED_STATS */
204 struct ixgbe_tx_queue_stats {
210 struct ixgbe_rx_queue_stats {
214 u64 alloc_rx_page_failed;
215 u64 alloc_rx_buff_failed;
219 enum ixgbe_ring_state_t {
220 __IXGBE_TX_FDIR_INIT_DONE,
221 __IXGBE_TX_XPS_INIT_DONE,
222 __IXGBE_TX_DETECT_HANG,
223 __IXGBE_HANG_CHECK_ARMED,
224 __IXGBE_RX_RSC_ENABLED,
225 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
229 struct ixgbe_fwd_adapter {
230 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
231 struct net_device *netdev;
232 struct ixgbe_adapter *real_adapter;
233 unsigned int tx_base_queue;
234 unsigned int rx_base_queue;
238 #define check_for_tx_hang(ring) \
239 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
240 #define set_check_for_tx_hang(ring) \
241 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
242 #define clear_check_for_tx_hang(ring) \
243 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
244 #define ring_is_rsc_enabled(ring) \
245 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
246 #define set_ring_rsc_enabled(ring) \
247 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
248 #define clear_ring_rsc_enabled(ring) \
249 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
251 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
252 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
253 struct net_device *netdev; /* netdev ring belongs to */
254 struct device *dev; /* device for DMA mapping */
255 struct ixgbe_fwd_adapter *l2_accel_priv;
256 void *desc; /* descriptor ring memory */
258 struct ixgbe_tx_buffer *tx_buffer_info;
259 struct ixgbe_rx_buffer *rx_buffer_info;
263 dma_addr_t dma; /* phys. address of descriptor ring */
264 unsigned int size; /* length in bytes */
266 u16 count; /* amount of descriptors */
268 u8 queue_index; /* needed for multiqueue queue management */
269 u8 reg_idx; /* holds the special value that gets
270 * the hardware register offset
271 * associated with this ring, which is
272 * different for DCB and RSS modes
286 struct ixgbe_queue_stats stats;
287 struct u64_stats_sync syncp;
289 struct ixgbe_tx_queue_stats tx_stats;
290 struct ixgbe_rx_queue_stats rx_stats;
292 } ____cacheline_internodealigned_in_smp;
294 enum ixgbe_ring_f_enum {
296 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
301 #endif /* IXGBE_FCOE */
303 RING_F_ARRAY_SIZE /* must be last in enum set */
306 #define IXGBE_MAX_RSS_INDICES 16
307 #define IXGBE_MAX_RSS_INDICES_X550 64
308 #define IXGBE_MAX_VMDQ_INDICES 64
309 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
310 #define IXGBE_MAX_FCOE_INDICES 8
311 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
312 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
313 #define IXGBE_MAX_L2A_QUEUES 4
314 #define IXGBE_BAD_L2A_QUEUE 3
315 #define IXGBE_MAX_MACVLANS 31
316 #define IXGBE_MAX_DCBMACVLANS 8
318 struct ixgbe_ring_feature {
319 u16 limit; /* upper limit on feature indices */
320 u16 indices; /* current value of indices */
321 u16 mask; /* Mask used for feature to ring mapping */
322 u16 offset; /* offset to start of feature */
323 } ____cacheline_internodealigned_in_smp;
325 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
326 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
327 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
330 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
331 * this is twice the size of a half page we need to double the page order
332 * for FCoE enabled Rx queues.
334 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
337 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
338 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
341 return IXGBE_RXBUFFER_2K;
344 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
347 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
348 return (PAGE_SIZE < 8192) ? 1 : 0;
352 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
354 struct ixgbe_ring_container {
355 struct ixgbe_ring *ring; /* pointer to linked list of rings */
356 unsigned int total_bytes; /* total bytes processed this int */
357 unsigned int total_packets; /* total packets processed this int */
358 u16 work_limit; /* total work allowed per interrupt */
359 u8 count; /* total number of rings in vector */
360 u8 itr; /* current ITR setting for ring */
363 /* iterator for handling rings in ring container */
364 #define ixgbe_for_each_ring(pos, head) \
365 for (pos = (head).ring; pos != NULL; pos = pos->next)
367 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
369 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
371 /* MAX_Q_VECTORS of these are allocated,
372 * but we only use one per queue-specific vector.
374 struct ixgbe_q_vector {
375 struct ixgbe_adapter *adapter;
376 #ifdef CONFIG_IXGBE_DCA
377 int cpu; /* CPU for DCA */
379 u16 v_idx; /* index of q_vector within array, also used for
380 * finding the bit in EICR and friends that
381 * represents the vector for this ring */
382 u16 itr; /* Interrupt throttle rate written to EITR */
383 struct ixgbe_ring_container rx, tx;
385 struct napi_struct napi;
386 cpumask_t affinity_mask;
388 struct rcu_head rcu; /* to avoid race with update stats on free */
389 char name[IFNAMSIZ + 9];
391 #ifdef CONFIG_NET_RX_BUSY_POLL
393 #endif /* CONFIG_NET_RX_BUSY_POLL */
395 /* for dynamic allocation of rings associated with this q_vector */
396 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
399 #ifdef CONFIG_NET_RX_BUSY_POLL
400 enum ixgbe_qv_state_t {
401 IXGBE_QV_STATE_IDLE = 0,
404 IXGBE_QV_STATE_DISABLE
407 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
409 /* reset state to idle */
410 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
413 /* called from the device poll routine to get ownership of a q_vector */
414 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
416 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
417 IXGBE_QV_STATE_NAPI);
418 #ifdef BP_EXTENDED_STATS
419 if (rc != IXGBE_QV_STATE_IDLE)
420 q_vector->tx.ring->stats.yields++;
423 return rc == IXGBE_QV_STATE_IDLE;
426 /* returns true is someone tried to get the qv while napi had it */
427 static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
429 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI);
431 /* flush any outstanding Rx frames */
432 if (q_vector->napi.gro_list)
433 napi_gro_flush(&q_vector->napi, false);
435 /* reset state to idle */
436 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
439 /* called from ixgbe_low_latency_poll() */
440 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
442 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
443 IXGBE_QV_STATE_POLL);
444 #ifdef BP_EXTENDED_STATS
445 if (rc != IXGBE_QV_STATE_IDLE)
446 q_vector->tx.ring->stats.yields++;
448 return rc == IXGBE_QV_STATE_IDLE;
451 /* returns true if someone tried to get the qv while it was locked */
452 static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
454 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL);
456 /* reset state to idle */
457 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
460 /* true if a socket is polling, even if it did not get the lock */
461 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
463 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL;
466 /* false if QV is currently owned */
467 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
469 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
470 IXGBE_QV_STATE_DISABLE);
472 return rc == IXGBE_QV_STATE_IDLE;
475 #else /* CONFIG_NET_RX_BUSY_POLL */
476 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
480 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
485 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
490 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
495 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
500 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
505 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
510 #endif /* CONFIG_NET_RX_BUSY_POLL */
512 #ifdef CONFIG_IXGBE_HWMON
514 #define IXGBE_HWMON_TYPE_LOC 0
515 #define IXGBE_HWMON_TYPE_TEMP 1
516 #define IXGBE_HWMON_TYPE_CAUTION 2
517 #define IXGBE_HWMON_TYPE_MAX 3
520 struct device_attribute dev_attr;
522 struct ixgbe_thermal_diode_data *sensor;
527 struct attribute_group group;
528 const struct attribute_group *groups[2];
529 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
530 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
531 unsigned int n_hwmon;
533 #endif /* CONFIG_IXGBE_HWMON */
536 * microsecond values for various ITR rates shifted by 2 to fit itr register
537 * with the first 3 bits reserved 0
539 #define IXGBE_MIN_RSC_ITR 24
540 #define IXGBE_100K_ITR 40
541 #define IXGBE_20K_ITR 200
542 #define IXGBE_12K_ITR 336
544 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
545 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
546 const u32 stat_err_bits)
548 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
551 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
553 u16 ntc = ring->next_to_clean;
554 u16 ntu = ring->next_to_use;
556 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
559 #define IXGBE_RX_DESC(R, i) \
560 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
561 #define IXGBE_TX_DESC(R, i) \
562 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
563 #define IXGBE_TX_CTXTDESC(R, i) \
564 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
566 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
568 /* Use 3K as the baby jumbo frame size for FCoE */
569 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
570 #endif /* IXGBE_FCOE */
572 #define OTHER_VECTOR 1
573 #define NON_Q_VECTORS (OTHER_VECTOR)
575 #define MAX_MSIX_VECTORS_82599 64
576 #define MAX_Q_VECTORS_82599 64
577 #define MAX_MSIX_VECTORS_82598 18
578 #define MAX_Q_VECTORS_82598 16
580 struct ixgbe_mac_addr {
583 u16 state; /* bitmask */
585 #define IXGBE_MAC_STATE_DEFAULT 0x1
586 #define IXGBE_MAC_STATE_MODIFIED 0x2
587 #define IXGBE_MAC_STATE_IN_USE 0x4
589 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
590 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
592 #define MIN_MSIX_Q_VECTORS 1
593 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
595 /* default to trying for four seconds */
596 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
598 /* board specific private data structure */
599 struct ixgbe_adapter {
600 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
601 /* OS defined structs */
602 struct net_device *netdev;
603 struct pci_dev *pdev;
607 /* Some features need tri-state capability,
608 * thus the additional *_CAPABLE flags.
611 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
612 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
613 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
614 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
615 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
616 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
617 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
618 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
619 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
620 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
621 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
622 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
623 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
624 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
625 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
626 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
627 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
628 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
629 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
630 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
631 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
632 #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24)
635 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
636 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
637 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
638 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
639 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
640 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
641 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
642 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
643 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
644 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
645 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
646 #define IXGBE_FLAG2_PHY_INTERRUPT (u32)(1 << 11)
647 #ifdef CONFIG_IXGBE_VXLAN
648 #define IXGBE_FLAG2_VXLAN_REREG_NEEDED BIT(12)
651 /* Tx fast path data */
656 /* Rx fast path data */
661 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
665 u32 tx_timeout_count;
668 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
669 int num_rx_pools; /* == num_rx_queues in 82598 */
670 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
671 u64 hw_csum_rx_error;
672 u64 hw_rx_no_dma_resources;
676 u32 alloc_rx_page_failed;
677 u32 alloc_rx_buff_failed;
679 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
682 struct ieee_pfc *ixgbe_ieee_pfc;
683 struct ieee_ets *ixgbe_ieee_ets;
684 struct ixgbe_dcb_config dcb_cfg;
685 struct ixgbe_dcb_config temp_dcb_cfg;
688 enum ixgbe_fc_mode last_lfc_mode;
690 int num_q_vectors; /* current number of q_vectors for device */
691 int max_q_vectors; /* true count of q_vectors for device */
692 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
693 struct msix_entry *msix_entries;
696 struct ixgbe_ring test_tx_ring;
697 struct ixgbe_ring test_rx_ring;
699 /* structs defined in ixgbe_hw.h */
702 struct ixgbe_hw_stats stats;
705 unsigned int tx_ring_count;
706 unsigned int rx_ring_count;
710 unsigned long link_check_timeout;
712 struct timer_list service_timer;
713 struct work_struct service_task;
715 struct hlist_head fdir_filter_list;
716 unsigned long fdir_overflow; /* number of times ATR was backed off */
717 union ixgbe_atr_input fdir_mask;
718 int fdir_filter_count;
721 spinlock_t fdir_perfect_lock;
724 struct ixgbe_fcoe fcoe;
725 #endif /* IXGBE_FCOE */
726 u8 __iomem *io_addr; /* Mainly for iounmap use */
738 struct ptp_clock *ptp_clock;
739 struct ptp_clock_info ptp_caps;
740 struct work_struct ptp_tx_work;
741 struct sk_buff *ptp_tx_skb;
742 struct hwtstamp_config tstamp_config;
743 unsigned long ptp_tx_start;
744 unsigned long last_overflow_check;
745 unsigned long last_rx_ptp_check;
746 unsigned long last_rx_timestamp;
747 spinlock_t tmreg_lock;
748 struct cyclecounter cc;
749 struct timecounter tc;
753 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
754 unsigned int num_vfs;
755 struct vf_data_storage *vfinfo;
756 int vf_rate_link_speed;
757 struct vf_macvlans vf_mvs;
758 struct vf_macvlans *mv_list;
760 u32 timer_event_accumulator;
762 struct ixgbe_mac_addr *mac_table;
763 #ifdef CONFIG_IXGBE_VXLAN
766 struct kobject *info_kobj;
767 #ifdef CONFIG_IXGBE_HWMON
768 struct hwmon_buff *ixgbe_hwmon_buff;
769 #endif /* CONFIG_IXGBE_HWMON */
770 #ifdef CONFIG_DEBUG_FS
771 struct dentry *ixgbe_dbg_adapter;
772 #endif /*CONFIG_DEBUG_FS*/
775 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */
777 /* maximum number of RETA entries among all devices supported by ixgbe
778 * driver: currently it's x550 device in non-SRIOV mode
780 #define IXGBE_MAX_RETA_ENTRIES 512
781 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
783 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
784 u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)];
787 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
789 switch (adapter->hw.mac.type) {
790 case ixgbe_mac_82598EB:
791 case ixgbe_mac_82599EB:
793 return IXGBE_MAX_RSS_INDICES;
795 case ixgbe_mac_X550EM_x:
796 return IXGBE_MAX_RSS_INDICES_X550;
802 struct ixgbe_fdir_filter {
803 struct hlist_node fdir_node;
804 union ixgbe_atr_input filter;
815 __IXGBE_SERVICE_SCHED,
816 __IXGBE_SERVICE_INITED,
819 __IXGBE_PTP_TX_IN_PROGRESS,
823 union { /* Union defining head/tail partner */
824 struct sk_buff *head;
825 struct sk_buff *tail;
831 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
841 extern struct ixgbe_info ixgbe_82598_info;
842 extern struct ixgbe_info ixgbe_82599_info;
843 extern struct ixgbe_info ixgbe_X540_info;
844 extern struct ixgbe_info ixgbe_X550_info;
845 extern struct ixgbe_info ixgbe_X550EM_x_info;
846 #ifdef CONFIG_IXGBE_DCB
847 extern const struct dcbnl_rtnl_ops dcbnl_ops;
850 extern char ixgbe_driver_name[];
851 extern const char ixgbe_driver_version[];
853 extern char ixgbe_default_device_descr[];
854 #endif /* IXGBE_FCOE */
856 void ixgbe_up(struct ixgbe_adapter *adapter);
857 void ixgbe_down(struct ixgbe_adapter *adapter);
858 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
859 void ixgbe_reset(struct ixgbe_adapter *adapter);
860 void ixgbe_set_ethtool_ops(struct net_device *netdev);
861 int ixgbe_setup_rx_resources(struct ixgbe_ring *);
862 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
863 void ixgbe_free_rx_resources(struct ixgbe_ring *);
864 void ixgbe_free_tx_resources(struct ixgbe_ring *);
865 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
866 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
867 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
868 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
869 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
870 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
872 #ifdef CONFIG_PCI_IOV
873 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
875 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
876 u8 *addr, u16 queue);
877 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
878 u8 *addr, u16 queue);
879 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
880 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
881 struct ixgbe_ring *);
882 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
883 struct ixgbe_tx_buffer *);
884 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
885 void ixgbe_write_eitr(struct ixgbe_q_vector *);
886 int ixgbe_poll(struct napi_struct *napi, int budget);
887 int ethtool_ioctl(struct ifreq *ifr);
888 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
889 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
890 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
891 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
892 union ixgbe_atr_hash_dword input,
893 union ixgbe_atr_hash_dword common,
895 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
896 union ixgbe_atr_input *input_mask);
897 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
898 union ixgbe_atr_input *input,
899 u16 soft_id, u8 queue);
900 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
901 union ixgbe_atr_input *input,
903 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
904 union ixgbe_atr_input *mask);
905 void ixgbe_set_rx_mode(struct net_device *netdev);
906 #ifdef CONFIG_IXGBE_DCB
907 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
909 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
910 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
911 void ixgbe_do_reset(struct net_device *netdev);
912 #ifdef CONFIG_IXGBE_HWMON
913 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
914 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
915 #endif /* CONFIG_IXGBE_HWMON */
917 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
918 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
920 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
921 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
922 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
923 struct scatterlist *sgl, unsigned int sgc);
924 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
925 struct scatterlist *sgl, unsigned int sgc);
926 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
927 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
928 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
929 int ixgbe_fcoe_enable(struct net_device *netdev);
930 int ixgbe_fcoe_disable(struct net_device *netdev);
931 #ifdef CONFIG_IXGBE_DCB
932 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
933 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
934 #endif /* CONFIG_IXGBE_DCB */
935 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
936 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
937 struct netdev_fcoe_hbainfo *info);
938 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
939 #endif /* IXGBE_FCOE */
940 #ifdef CONFIG_DEBUG_FS
941 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
942 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
943 void ixgbe_dbg_init(void);
944 void ixgbe_dbg_exit(void);
946 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
947 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
948 static inline void ixgbe_dbg_init(void) {}
949 static inline void ixgbe_dbg_exit(void) {}
950 #endif /* CONFIG_DEBUG_FS */
951 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
953 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
956 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
957 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
958 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
959 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
960 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
961 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb);
962 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
963 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
964 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
965 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
966 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
967 #ifdef CONFIG_PCI_IOV
968 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
971 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
972 struct ixgbe_adapter *adapter,
973 struct ixgbe_ring *tx_ring);
974 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
975 void ixgbe_store_reta(struct ixgbe_adapter *adapter);
976 #endif /* _IXGBE_H_ */