1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
34 #include "ixgbe_phy.h"
35 #include "ixgbe_mbx.h"
37 #define IXGBE_82599_MAX_TX_QUEUES 128
38 #define IXGBE_82599_MAX_RX_QUEUES 128
39 #define IXGBE_82599_RAR_ENTRIES 128
40 #define IXGBE_82599_MC_TBL_SIZE 128
41 #define IXGBE_82599_VFT_TBL_SIZE 128
42 #define IXGBE_82599_RX_PB_SIZE 512
44 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
47 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg_wait_to_complete);
53 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg_wait_to_complete);
62 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
63 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
64 u8 dev_addr, u8 *data);
65 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
66 u8 dev_addr, u8 data);
67 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
68 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
70 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
72 u32 fwsm, manc, factps;
74 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
75 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
78 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
79 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
82 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
83 if (factps & IXGBE_FACTPS_MNGCG)
89 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
91 struct ixgbe_mac_info *mac = &hw->mac;
93 /* enable the laser control functions for SFP+ fiber
96 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
97 !ixgbe_mng_enabled(hw)) {
98 mac->ops.disable_tx_laser =
99 &ixgbe_disable_tx_laser_multispeed_fiber;
100 mac->ops.enable_tx_laser =
101 &ixgbe_enable_tx_laser_multispeed_fiber;
102 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
104 mac->ops.disable_tx_laser = NULL;
105 mac->ops.enable_tx_laser = NULL;
106 mac->ops.flap_tx_laser = NULL;
109 if (hw->phy.multispeed_fiber) {
110 /* Set up dual speed SFP+ support */
111 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
113 if ((mac->ops.get_media_type(hw) ==
114 ixgbe_media_type_backplane) &&
115 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
116 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
117 !ixgbe_verify_lesm_fw_enabled_82599(hw))
118 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
120 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
124 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
127 u16 list_offset, data_offset, data_value;
129 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
130 ixgbe_init_mac_link_ops_82599(hw);
132 hw->phy.ops.reset = NULL;
134 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
139 /* PHY config will finish before releasing the semaphore */
140 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
141 IXGBE_GSSR_MAC_CSR_SM);
143 ret_val = IXGBE_ERR_SWFW_SYNC;
147 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
149 while (data_value != 0xffff) {
150 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
151 IXGBE_WRITE_FLUSH(hw);
152 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
156 /* Release the semaphore */
157 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
159 * Delay obtaining semaphore again to allow FW access,
160 * semaphore_delay is in ms usleep_range needs us.
162 usleep_range(hw->eeprom.semaphore_delay * 1000,
163 hw->eeprom.semaphore_delay * 2000);
165 /* Restart DSP and set SFI mode */
166 ret_val = hw->mac.ops.prot_autoc_write(hw,
167 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
171 hw_dbg(hw, " sfp module setup not complete\n");
172 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
181 /* Release the semaphore */
182 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
183 /* Delay obtaining semaphore again to allow FW access,
184 * semaphore_delay is in ms usleep_range needs us.
186 usleep_range(hw->eeprom.semaphore_delay * 1000,
187 hw->eeprom.semaphore_delay * 2000);
188 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
189 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
193 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
194 * @hw: pointer to hardware structure
195 * @locked: Return the if we locked for this read.
196 * @reg_val: Value we read from AUTOC
198 * For this part (82599) we need to wrap read-modify-writes with a possible
199 * FW/SW lock. It is assumed this lock will be freed with the next
200 * prot_autoc_write_82599(). Note, that locked can only be true in cases
201 * where this function doesn't return an error.
203 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,
209 /* If LESM is on then we need to hold the SW/FW semaphore. */
210 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
211 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
212 IXGBE_GSSR_MAC_CSR_SM);
214 return IXGBE_ERR_SWFW_SYNC;
219 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
224 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
225 * @hw: pointer to hardware structure
226 * @reg_val: value to write to AUTOC
227 * @locked: bool to indicate whether the SW/FW lock was already taken by
228 * previous proc_autoc_read_82599.
230 * This part (82599) may need to hold a the SW/FW lock around all writes to
231 * AUTOC. Likewise after a write we need to do a pipeline reset.
233 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
237 /* Blocked by MNG FW so bail */
238 if (ixgbe_check_reset_blocked(hw))
241 /* We only need to get the lock if:
242 * - We didn't do it already (in the read part of a read-modify-write)
245 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
246 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
247 IXGBE_GSSR_MAC_CSR_SM);
249 return IXGBE_ERR_SWFW_SYNC;
254 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
255 ret_val = ixgbe_reset_pipeline_82599(hw);
258 /* Free the SW/FW semaphore as we either grabbed it here or
259 * already had it when this function was called.
262 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
267 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
269 struct ixgbe_mac_info *mac = &hw->mac;
271 ixgbe_init_mac_link_ops_82599(hw);
273 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
274 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
275 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
276 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
277 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
278 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
279 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
285 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
286 * @hw: pointer to hardware structure
288 * Initialize any function pointers that were not able to be
289 * set during get_invariants because the PHY/SFP type was
290 * not known. Perform the SFP init if necessary.
293 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
295 struct ixgbe_mac_info *mac = &hw->mac;
296 struct ixgbe_phy_info *phy = &hw->phy;
300 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
301 /* Store flag indicating I2C bus access control unit. */
302 hw->phy.qsfp_shared_i2c_bus = true;
304 /* Initialize access to QSFP+ I2C bus */
305 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
306 esdp |= IXGBE_ESDP_SDP0_DIR;
307 esdp &= ~IXGBE_ESDP_SDP1_DIR;
308 esdp &= ~IXGBE_ESDP_SDP0;
309 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
310 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
311 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
312 IXGBE_WRITE_FLUSH(hw);
314 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
315 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
318 /* Identify the PHY or SFP module */
319 ret_val = phy->ops.identify(hw);
321 /* Setup function pointers based on detected SFP module and speeds */
322 ixgbe_init_mac_link_ops_82599(hw);
324 /* If copper media, overwrite with copper function pointers */
325 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
326 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
327 mac->ops.get_link_capabilities =
328 &ixgbe_get_copper_link_capabilities_generic;
331 /* Set necessary function pointers based on phy type */
332 switch (hw->phy.type) {
334 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
335 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
336 phy->ops.get_firmware_version =
337 &ixgbe_get_phy_firmware_version_tnx;
347 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
348 * @hw: pointer to hardware structure
349 * @speed: pointer to link speed
350 * @autoneg: true when autoneg or autotry is enabled
352 * Determines the link capabilities by reading the AUTOC register.
354 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
355 ixgbe_link_speed *speed,
361 /* Determine 1G link capabilities off of SFP+ type */
362 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
363 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
364 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
365 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
366 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
367 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
368 *speed = IXGBE_LINK_SPEED_1GB_FULL;
374 * Determine link capabilities based on the stored value of AUTOC,
375 * which represents EEPROM defaults. If AUTOC value has not been
376 * stored, use the current register value.
378 if (hw->mac.orig_link_settings_stored)
379 autoc = hw->mac.orig_autoc;
381 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
383 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
384 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
385 *speed = IXGBE_LINK_SPEED_1GB_FULL;
389 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
390 *speed = IXGBE_LINK_SPEED_10GB_FULL;
394 case IXGBE_AUTOC_LMS_1G_AN:
395 *speed = IXGBE_LINK_SPEED_1GB_FULL;
399 case IXGBE_AUTOC_LMS_10G_SERIAL:
400 *speed = IXGBE_LINK_SPEED_10GB_FULL;
404 case IXGBE_AUTOC_LMS_KX4_KX_KR:
405 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
406 *speed = IXGBE_LINK_SPEED_UNKNOWN;
407 if (autoc & IXGBE_AUTOC_KR_SUPP)
408 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
409 if (autoc & IXGBE_AUTOC_KX4_SUPP)
410 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
411 if (autoc & IXGBE_AUTOC_KX_SUPP)
412 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
416 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
417 *speed = IXGBE_LINK_SPEED_100_FULL;
418 if (autoc & IXGBE_AUTOC_KR_SUPP)
419 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
420 if (autoc & IXGBE_AUTOC_KX4_SUPP)
421 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
422 if (autoc & IXGBE_AUTOC_KX_SUPP)
423 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
427 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
428 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
433 status = IXGBE_ERR_LINK_SETUP;
437 if (hw->phy.multispeed_fiber) {
438 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
439 IXGBE_LINK_SPEED_1GB_FULL;
441 /* QSFP must not enable auto-negotiation */
442 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
453 * ixgbe_get_media_type_82599 - Get media type
454 * @hw: pointer to hardware structure
456 * Returns the media type (fiber, copper, backplane)
458 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
460 enum ixgbe_media_type media_type;
462 /* Detect if there is a copper PHY attached. */
463 switch (hw->phy.type) {
464 case ixgbe_phy_cu_unknown:
466 media_type = ixgbe_media_type_copper;
472 switch (hw->device_id) {
473 case IXGBE_DEV_ID_82599_KX4:
474 case IXGBE_DEV_ID_82599_KX4_MEZZ:
475 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
476 case IXGBE_DEV_ID_82599_KR:
477 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
478 case IXGBE_DEV_ID_82599_XAUI_LOM:
479 /* Default device ID is mezzanine card KX/KX4 */
480 media_type = ixgbe_media_type_backplane;
482 case IXGBE_DEV_ID_82599_SFP:
483 case IXGBE_DEV_ID_82599_SFP_FCOE:
484 case IXGBE_DEV_ID_82599_SFP_EM:
485 case IXGBE_DEV_ID_82599_SFP_SF2:
486 case IXGBE_DEV_ID_82599_SFP_SF_QP:
487 case IXGBE_DEV_ID_82599EN_SFP:
488 media_type = ixgbe_media_type_fiber;
490 case IXGBE_DEV_ID_82599_CX4:
491 media_type = ixgbe_media_type_cx4;
493 case IXGBE_DEV_ID_82599_T3_LOM:
494 media_type = ixgbe_media_type_copper;
496 case IXGBE_DEV_ID_82599_LS:
497 media_type = ixgbe_media_type_fiber_lco;
499 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
500 media_type = ixgbe_media_type_fiber_qsfp;
503 media_type = ixgbe_media_type_unknown;
511 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
512 * @hw: pointer to hardware structure
514 * Disables link, should be called during D3 power down sequence.
517 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
519 u32 autoc2_reg, fwsm;
522 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
524 /* Check to see if MNG FW could be enabled */
525 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
527 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
529 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
530 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
531 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
532 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
537 * ixgbe_start_mac_link_82599 - Setup MAC link settings
538 * @hw: pointer to hardware structure
539 * @autoneg_wait_to_complete: true when waiting for completion is needed
541 * Configures link settings based on values in the ixgbe_hw struct.
542 * Restarts the link. Performs autonegotiation if needed.
544 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
545 bool autoneg_wait_to_complete)
551 bool got_lock = false;
553 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
554 status = hw->mac.ops.acquire_swfw_sync(hw,
555 IXGBE_GSSR_MAC_CSR_SM);
563 ixgbe_reset_pipeline_82599(hw);
566 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
568 /* Only poll for autoneg to complete if specified to do so */
569 if (autoneg_wait_to_complete) {
570 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
571 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
572 IXGBE_AUTOC_LMS_KX4_KX_KR ||
573 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
574 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
575 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
576 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
577 links_reg = 0; /* Just in case Autoneg time = 0 */
578 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
579 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
580 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
584 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
585 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
586 hw_dbg(hw, "Autoneg did not complete.\n");
591 /* Add delay to filter out noises during initial link setup */
599 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
600 * @hw: pointer to hardware structure
602 * The base drivers may require better control over SFP+ module
603 * PHY states. This includes selectively shutting down the Tx
604 * laser on the PHY, effectively halting physical link.
606 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
608 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
610 /* Blocked by MNG FW so bail */
611 if (ixgbe_check_reset_blocked(hw))
614 /* Disable tx laser; allow 100us to go dark per spec */
615 esdp_reg |= IXGBE_ESDP_SDP3;
616 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
617 IXGBE_WRITE_FLUSH(hw);
622 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
623 * @hw: pointer to hardware structure
625 * The base drivers may require better control over SFP+ module
626 * PHY states. This includes selectively turning on the Tx
627 * laser on the PHY, effectively starting physical link.
629 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
631 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
633 /* Enable tx laser; allow 100ms to light up */
634 esdp_reg &= ~IXGBE_ESDP_SDP3;
635 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
636 IXGBE_WRITE_FLUSH(hw);
641 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
642 * @hw: pointer to hardware structure
644 * When the driver changes the link speeds that it can support,
645 * it sets autotry_restart to true to indicate that we need to
646 * initiate a new autotry session with the link partner. To do
647 * so, we set the speed then disable and re-enable the tx laser, to
648 * alert the link partner that it also needs to restart autotry on its
649 * end. This is consistent with true clause 37 autoneg, which also
650 * involves a loss of signal.
652 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
654 /* Blocked by MNG FW so bail */
655 if (ixgbe_check_reset_blocked(hw))
658 if (hw->mac.autotry_restart) {
659 ixgbe_disable_tx_laser_multispeed_fiber(hw);
660 ixgbe_enable_tx_laser_multispeed_fiber(hw);
661 hw->mac.autotry_restart = false;
666 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
667 * @hw: pointer to hardware structure
668 * @speed: new link speed
669 * @autoneg_wait_to_complete: true when waiting for completion is needed
671 * Set the link speed in the AUTOC register and restarts link.
673 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
674 ixgbe_link_speed speed,
675 bool autoneg_wait_to_complete)
678 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
679 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
681 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
683 bool link_up = false;
684 bool autoneg = false;
686 /* Mask off requested but non-supported speeds */
687 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
695 * Try each speed one by one, highest priority first. We do this in
696 * software because 10gb fiber doesn't support speed autonegotiation.
698 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
700 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
702 /* If we already have link at this speed, just jump out */
703 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
708 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
711 /* Set the module link speed */
712 switch (hw->phy.media_type) {
713 case ixgbe_media_type_fiber:
714 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
715 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
716 IXGBE_WRITE_FLUSH(hw);
718 case ixgbe_media_type_fiber_qsfp:
719 /* QSFP module automatically detects MAC link speed */
722 hw_dbg(hw, "Unexpected media type.\n");
726 /* Allow module to change analog characteristics (1G->10G) */
729 status = ixgbe_setup_mac_link_82599(hw,
730 IXGBE_LINK_SPEED_10GB_FULL,
731 autoneg_wait_to_complete);
735 /* Flap the tx laser if it has not already been done */
736 if (hw->mac.ops.flap_tx_laser)
737 hw->mac.ops.flap_tx_laser(hw);
740 * Wait for the controller to acquire link. Per IEEE 802.3ap,
741 * Section 73.10.2, we may have to wait up to 500ms if KR is
742 * attempted. 82599 uses the same timing for 10g SFI.
744 for (i = 0; i < 5; i++) {
745 /* Wait for the link partner to also set speed */
748 /* If we have link, just jump out */
749 status = hw->mac.ops.check_link(hw, &link_speed,
759 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
761 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
762 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
764 /* If we already have link at this speed, just jump out */
765 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
770 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
773 /* Set the module link speed */
774 switch (hw->phy.media_type) {
775 case ixgbe_media_type_fiber:
776 esdp_reg &= ~IXGBE_ESDP_SDP5;
777 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
778 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
779 IXGBE_WRITE_FLUSH(hw);
781 case ixgbe_media_type_fiber_qsfp:
782 /* QSFP module automatically detects MAC link speed */
785 hw_dbg(hw, "Unexpected media type.\n");
789 /* Allow module to change analog characteristics (10G->1G) */
792 status = ixgbe_setup_mac_link_82599(hw,
793 IXGBE_LINK_SPEED_1GB_FULL,
794 autoneg_wait_to_complete);
798 /* Flap the tx laser if it has not already been done */
799 if (hw->mac.ops.flap_tx_laser)
800 hw->mac.ops.flap_tx_laser(hw);
802 /* Wait for the link partner to also set speed */
805 /* If we have link, just jump out */
806 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
816 * We didn't get link. Configure back to the highest speed we tried,
817 * (if there was more than one). We call ourselves back with just the
818 * single highest speed that the user requested.
821 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
823 autoneg_wait_to_complete);
826 /* Set autoneg_advertised value based on input link speed */
827 hw->phy.autoneg_advertised = 0;
829 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
830 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
832 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
833 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
839 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
840 * @hw: pointer to hardware structure
841 * @speed: new link speed
842 * @autoneg_wait_to_complete: true when waiting for completion is needed
844 * Implements the Intel SmartSpeed algorithm.
846 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
847 ixgbe_link_speed speed,
848 bool autoneg_wait_to_complete)
851 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
853 bool link_up = false;
854 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
856 /* Set autoneg_advertised value based on input link speed */
857 hw->phy.autoneg_advertised = 0;
859 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
860 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
862 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
863 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
865 if (speed & IXGBE_LINK_SPEED_100_FULL)
866 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
869 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
870 * autoneg advertisement if link is unable to be established at the
871 * highest negotiated rate. This can sometimes happen due to integrity
872 * issues with the physical media connection.
875 /* First, try to get link with full advertisement */
876 hw->phy.smart_speed_active = false;
877 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
878 status = ixgbe_setup_mac_link_82599(hw, speed,
879 autoneg_wait_to_complete);
884 * Wait for the controller to acquire link. Per IEEE 802.3ap,
885 * Section 73.10.2, we may have to wait up to 500ms if KR is
886 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
887 * Table 9 in the AN MAS.
889 for (i = 0; i < 5; i++) {
892 /* If we have link, just jump out */
893 status = hw->mac.ops.check_link(hw, &link_speed,
904 * We didn't get link. If we advertised KR plus one of KX4/KX
905 * (or BX4/BX), then disable KR and try again.
907 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
908 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
911 /* Turn SmartSpeed on to disable KR support */
912 hw->phy.smart_speed_active = true;
913 status = ixgbe_setup_mac_link_82599(hw, speed,
914 autoneg_wait_to_complete);
919 * Wait for the controller to acquire link. 600ms will allow for
920 * the AN link_fail_inhibit_timer as well for multiple cycles of
921 * parallel detect, both 10g and 1g. This allows for the maximum
922 * connect attempts as defined in the AN MAS table 73-7.
924 for (i = 0; i < 6; i++) {
927 /* If we have link, just jump out */
928 status = hw->mac.ops.check_link(hw, &link_speed,
937 /* We didn't get link. Turn SmartSpeed back off. */
938 hw->phy.smart_speed_active = false;
939 status = ixgbe_setup_mac_link_82599(hw, speed,
940 autoneg_wait_to_complete);
943 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
944 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n");
949 * ixgbe_setup_mac_link_82599 - Set MAC link speed
950 * @hw: pointer to hardware structure
951 * @speed: new link speed
952 * @autoneg_wait_to_complete: true when waiting for completion is needed
954 * Set the link speed in the AUTOC register and restarts link.
956 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
957 ixgbe_link_speed speed,
958 bool autoneg_wait_to_complete)
960 bool autoneg = false;
962 u32 pma_pmd_1g, link_mode, links_reg, i;
963 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
964 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
965 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
967 /* holds the value of AUTOC register at this current point in time */
968 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
969 /* holds the cached value of AUTOC register */
971 /* temporary variable used for comparison purposes */
972 u32 autoc = current_autoc;
974 /* Check to see if speed passed in is supported. */
975 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
980 speed &= link_capabilities;
982 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
983 status = IXGBE_ERR_LINK_SETUP;
987 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
988 if (hw->mac.orig_link_settings_stored)
989 orig_autoc = hw->mac.orig_autoc;
993 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
994 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
996 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
997 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
998 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
999 /* Set KX4/KX/KR support according to speed requested */
1000 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
1001 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1002 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
1003 autoc |= IXGBE_AUTOC_KX4_SUPP;
1004 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1005 (hw->phy.smart_speed_active == false))
1006 autoc |= IXGBE_AUTOC_KR_SUPP;
1008 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1009 autoc |= IXGBE_AUTOC_KX_SUPP;
1010 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1011 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1012 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1013 /* Switch from 1G SFI to 10G SFI if requested */
1014 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1015 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1016 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1017 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1019 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1020 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1021 /* Switch from 10G SFI to 1G SFI if requested */
1022 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1023 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1024 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1026 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1028 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1032 if (autoc != current_autoc) {
1034 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
1038 /* Only poll for autoneg to complete if specified to do so */
1039 if (autoneg_wait_to_complete) {
1040 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1041 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1042 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1043 links_reg = 0; /*Just in case Autoneg time=0*/
1044 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1046 IXGBE_READ_REG(hw, IXGBE_LINKS);
1047 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1051 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1053 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1054 hw_dbg(hw, "Autoneg did not complete.\n");
1059 /* Add delay to filter out noises during initial link setup */
1068 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1069 * @hw: pointer to hardware structure
1070 * @speed: new link speed
1071 * @autoneg_wait_to_complete: true if waiting is needed to complete
1073 * Restarts link on PHY and MAC based on settings passed in.
1075 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1076 ixgbe_link_speed speed,
1077 bool autoneg_wait_to_complete)
1081 /* Setup the PHY according to input speed */
1082 status = hw->phy.ops.setup_link_speed(hw, speed,
1083 autoneg_wait_to_complete);
1085 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1091 * ixgbe_reset_hw_82599 - Perform hardware reset
1092 * @hw: pointer to hardware structure
1094 * Resets the hardware by resetting the transmit and receive units, masks
1095 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1098 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1100 ixgbe_link_speed link_speed;
1102 u32 ctrl, i, autoc, autoc2;
1104 bool link_up = false;
1106 /* Call adapter stop to disable tx/rx and clear interrupts */
1107 status = hw->mac.ops.stop_adapter(hw);
1111 /* flush pending Tx transactions */
1112 ixgbe_clear_tx_pending(hw);
1114 /* PHY ops must be identified and initialized prior to reset */
1116 /* Identify PHY and related function pointers */
1117 status = hw->phy.ops.init(hw);
1119 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1122 /* Setup SFP module if there is one present. */
1123 if (hw->phy.sfp_setup_needed) {
1124 status = hw->mac.ops.setup_sfp(hw);
1125 hw->phy.sfp_setup_needed = false;
1128 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1132 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1133 hw->phy.ops.reset(hw);
1135 /* remember AUTOC from before we reset */
1136 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1140 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1141 * If link reset is used when link is up, it might reset the PHY when
1142 * mng is using it. If link is down or the flag to force full link
1143 * reset is set, then perform link reset.
1145 ctrl = IXGBE_CTRL_LNK_RST;
1146 if (!hw->force_full_reset) {
1147 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1149 ctrl = IXGBE_CTRL_RST;
1152 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1153 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1154 IXGBE_WRITE_FLUSH(hw);
1156 /* Poll for reset bit to self-clear indicating reset is complete */
1157 for (i = 0; i < 10; i++) {
1159 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1160 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1164 if (ctrl & IXGBE_CTRL_RST_MASK) {
1165 status = IXGBE_ERR_RESET_FAILED;
1166 hw_dbg(hw, "Reset polling failed to complete.\n");
1172 * Double resets are required for recovery from certain error
1173 * conditions. Between resets, it is necessary to stall to allow time
1174 * for any pending HW events to complete.
1176 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1177 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1182 * Store the original AUTOC/AUTOC2 values if they have not been
1183 * stored off yet. Otherwise restore the stored original
1184 * values since the reset operation sets back to defaults.
1186 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1187 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1189 /* Enable link if disabled in NVM */
1190 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1191 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1192 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1193 IXGBE_WRITE_FLUSH(hw);
1196 if (hw->mac.orig_link_settings_stored == false) {
1197 hw->mac.orig_autoc = autoc;
1198 hw->mac.orig_autoc2 = autoc2;
1199 hw->mac.orig_link_settings_stored = true;
1202 /* If MNG FW is running on a multi-speed device that
1203 * doesn't autoneg with out driver support we need to
1204 * leave LMS in the state it was before we MAC reset.
1205 * Likewise if we support WoL we don't want change the
1208 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1210 hw->mac.orig_autoc =
1211 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1214 if (autoc != hw->mac.orig_autoc) {
1215 status = hw->mac.ops.prot_autoc_write(hw,
1222 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1223 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1224 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1225 autoc2 |= (hw->mac.orig_autoc2 &
1226 IXGBE_AUTOC2_UPPER_MASK);
1227 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1231 /* Store the permanent mac address */
1232 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1235 * Store MAC address from RAR0, clear receive address registers, and
1236 * clear the multicast table. Also reset num_rar_entries to 128,
1237 * since we modify this value when programming the SAN MAC address.
1239 hw->mac.num_rar_entries = 128;
1240 hw->mac.ops.init_rx_addrs(hw);
1242 /* Store the permanent SAN mac address */
1243 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1245 /* Add the SAN MAC address to the RAR only if it's a valid address */
1246 if (is_valid_ether_addr(hw->mac.san_addr)) {
1247 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1248 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1250 /* Save the SAN MAC RAR index */
1251 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1253 /* Reserve the last RAR for the SAN MAC address */
1254 hw->mac.num_rar_entries--;
1257 /* Store the alternative WWNN/WWPN prefix */
1258 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1259 &hw->mac.wwpn_prefix);
1266 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1267 * @hw: pointer to hardware structure
1269 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1272 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1274 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1277 * Before starting reinitialization process,
1278 * FDIRCMD.CMD must be zero.
1280 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1281 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1282 IXGBE_FDIRCMD_CMD_MASK))
1286 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1287 hw_dbg(hw, "Flow Director previous command isn't complete, aborting table re-initialization.\n");
1288 return IXGBE_ERR_FDIR_REINIT_FAILED;
1291 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1292 IXGBE_WRITE_FLUSH(hw);
1294 * 82599 adapters flow director init flow cannot be restarted,
1295 * Workaround 82599 silicon errata by performing the following steps
1296 * before re-writing the FDIRCTRL control register with the same value.
1297 * - write 1 to bit 8 of FDIRCMD register &
1298 * - write 0 to bit 8 of FDIRCMD register
1300 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1301 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1302 IXGBE_FDIRCMD_CLEARHT));
1303 IXGBE_WRITE_FLUSH(hw);
1304 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1305 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1306 ~IXGBE_FDIRCMD_CLEARHT));
1307 IXGBE_WRITE_FLUSH(hw);
1309 * Clear FDIR Hash register to clear any leftover hashes
1310 * waiting to be programmed.
1312 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1313 IXGBE_WRITE_FLUSH(hw);
1315 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1316 IXGBE_WRITE_FLUSH(hw);
1318 /* Poll init-done after we write FDIRCTRL register */
1319 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1320 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1321 IXGBE_FDIRCTRL_INIT_DONE)
1323 usleep_range(1000, 2000);
1325 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1326 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1327 return IXGBE_ERR_FDIR_REINIT_FAILED;
1330 /* Clear FDIR statistics registers (read to clear) */
1331 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1332 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1333 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1334 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1335 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1341 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1342 * @hw: pointer to hardware structure
1343 * @fdirctrl: value to write to flow director control register
1345 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1349 /* Prime the keys for hashing */
1350 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1351 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1354 * Poll init-done after we write the register. Estimated times:
1355 * 10G: PBALLOC = 11b, timing is 60us
1356 * 1G: PBALLOC = 11b, timing is 600us
1357 * 100M: PBALLOC = 11b, timing is 6ms
1359 * Multiple these timings by 4 if under full Rx load
1361 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1362 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1363 * this might not finish in our poll time, but we can live with that
1366 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1367 IXGBE_WRITE_FLUSH(hw);
1368 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1369 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1370 IXGBE_FDIRCTRL_INIT_DONE)
1372 usleep_range(1000, 2000);
1375 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1376 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1380 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1381 * @hw: pointer to hardware structure
1382 * @fdirctrl: value to write to flow director control register, initially
1383 * contains just the value of the Rx packet buffer allocation
1385 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1388 * Continue setup of fdirctrl register bits:
1389 * Move the flexible bytes to use the ethertype - shift 6 words
1390 * Set the maximum length per hash bucket to 0xA filters
1391 * Send interrupt when 64 filters are left
1393 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1394 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1395 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1397 /* write hashes and fdirctrl register, poll for completion */
1398 ixgbe_fdir_enable_82599(hw, fdirctrl);
1404 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1405 * @hw: pointer to hardware structure
1406 * @fdirctrl: value to write to flow director control register, initially
1407 * contains just the value of the Rx packet buffer allocation
1409 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1412 * Continue setup of fdirctrl register bits:
1413 * Turn perfect match filtering on
1414 * Report hash in RSS field of Rx wb descriptor
1415 * Initialize the drop queue
1416 * Move the flexible bytes to use the ethertype - shift 6 words
1417 * Set the maximum length per hash bucket to 0xA filters
1418 * Send interrupt when 64 (0x4 * 16) filters are left
1420 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1421 IXGBE_FDIRCTRL_REPORT_STATUS |
1422 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1423 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1424 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1425 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1427 /* write hashes and fdirctrl register, poll for completion */
1428 ixgbe_fdir_enable_82599(hw, fdirctrl);
1434 * These defines allow us to quickly generate all of the necessary instructions
1435 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1436 * for values 0 through 15
1438 #define IXGBE_ATR_COMMON_HASH_KEY \
1439 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1440 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1443 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1444 common_hash ^= lo_hash_dword >> n; \
1445 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1446 bucket_hash ^= lo_hash_dword >> n; \
1447 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1448 sig_hash ^= lo_hash_dword << (16 - n); \
1449 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1450 common_hash ^= hi_hash_dword >> n; \
1451 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1452 bucket_hash ^= hi_hash_dword >> n; \
1453 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1454 sig_hash ^= hi_hash_dword << (16 - n); \
1458 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1459 * @stream: input bitstream to compute the hash on
1461 * This function is almost identical to the function above but contains
1462 * several optomizations such as unwinding all of the loops, letting the
1463 * compiler work out all of the conditional ifs since the keys are static
1464 * defines, and computing two keys at once since the hashed dword stream
1465 * will be the same for both keys.
1467 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1468 union ixgbe_atr_hash_dword common)
1470 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1471 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1473 /* record the flow_vm_vlan bits as they are a key part to the hash */
1474 flow_vm_vlan = ntohl(input.dword);
1476 /* generate common hash dword */
1477 hi_hash_dword = ntohl(common.dword);
1479 /* low dword is word swapped version of common */
1480 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1482 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1483 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1485 /* Process bits 0 and 16 */
1486 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1489 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1490 * delay this because bit 0 of the stream should not be processed
1491 * so we do not add the vlan until after bit 0 was processed
1493 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1495 /* Process remaining 30 bit of the key */
1496 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1497 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1498 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1499 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1500 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1501 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1502 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1503 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1504 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1505 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1506 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1507 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1508 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1509 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1510 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1512 /* combine common_hash result with signature and bucket hashes */
1513 bucket_hash ^= common_hash;
1514 bucket_hash &= IXGBE_ATR_HASH_MASK;
1516 sig_hash ^= common_hash << 16;
1517 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1519 /* return completed signature hash */
1520 return sig_hash ^ bucket_hash;
1524 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1525 * @hw: pointer to hardware structure
1526 * @input: unique input dword
1527 * @common: compressed common input dword
1528 * @queue: queue index to direct traffic to
1530 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1531 union ixgbe_atr_hash_dword input,
1532 union ixgbe_atr_hash_dword common,
1539 * Get the flow_type in order to program FDIRCMD properly
1540 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1542 switch (input.formatted.flow_type) {
1543 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1544 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1545 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1546 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1547 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1548 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1551 hw_dbg(hw, " Error on flow type input\n");
1552 return IXGBE_ERR_CONFIG;
1555 /* configure FDIRCMD register */
1556 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1557 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1558 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1559 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1562 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1563 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1565 fdirhashcmd = (u64)fdircmd << 32;
1566 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1567 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1569 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1574 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1577 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1578 bucket_hash ^= lo_hash_dword >> n; \
1579 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1580 bucket_hash ^= hi_hash_dword >> n; \
1584 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1585 * @atr_input: input bitstream to compute the hash on
1586 * @input_mask: mask for the input bitstream
1588 * This function serves two main purposes. First it applys the input_mask
1589 * to the atr_input resulting in a cleaned up atr_input data stream.
1590 * Secondly it computes the hash and stores it in the bkt_hash field at
1591 * the end of the input byte stream. This way it will be available for
1592 * future use without needing to recompute the hash.
1594 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1595 union ixgbe_atr_input *input_mask)
1598 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1599 u32 bucket_hash = 0, hi_dword = 0;
1602 /* Apply masks to input data */
1603 for (i = 0; i <= 10; i++)
1604 input->dword_stream[i] &= input_mask->dword_stream[i];
1606 /* record the flow_vm_vlan bits as they are a key part to the hash */
1607 flow_vm_vlan = ntohl(input->dword_stream[0]);
1609 /* generate common hash dword */
1610 for (i = 1; i <= 10; i++)
1611 hi_dword ^= input->dword_stream[i];
1612 hi_hash_dword = ntohl(hi_dword);
1614 /* low dword is word swapped version of common */
1615 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1617 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1618 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1620 /* Process bits 0 and 16 */
1621 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1624 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1625 * delay this because bit 0 of the stream should not be processed
1626 * so we do not add the vlan until after bit 0 was processed
1628 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1630 /* Process remaining 30 bit of the key */
1631 for (i = 1; i <= 15; i++)
1632 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1635 * Limit hash to 13 bits since max bucket count is 8K.
1636 * Store result at the end of the input stream.
1638 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1642 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1643 * @input_mask: mask to be bit swapped
1645 * The source and destination port masks for flow director are bit swapped
1646 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1647 * generate a correctly swapped value we need to bit swap the mask and that
1648 * is what is accomplished by this function.
1650 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1652 u32 mask = ntohs(input_mask->formatted.dst_port);
1654 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1655 mask |= ntohs(input_mask->formatted.src_port);
1656 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1657 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1658 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1659 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1663 * These two macros are meant to address the fact that we have registers
1664 * that are either all or in part big-endian. As a result on big-endian
1665 * systems we will end up byte swapping the value to little-endian before
1666 * it is byte swapped again and written to the hardware in the original
1667 * big-endian format.
1669 #define IXGBE_STORE_AS_BE32(_value) \
1670 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1671 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1673 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1674 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1676 #define IXGBE_STORE_AS_BE16(_value) \
1677 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1679 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1680 union ixgbe_atr_input *input_mask)
1682 /* mask IPv6 since it is currently not supported */
1683 u32 fdirm = IXGBE_FDIRM_DIPv6;
1687 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1688 * are zero, then assume a full mask for that field. Also assume that
1689 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1690 * cannot be masked out in this implementation.
1692 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1696 /* verify bucket hash is cleared on hash generation */
1697 if (input_mask->formatted.bkt_hash)
1698 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1700 /* Program FDIRM and verify partial masks */
1701 switch (input_mask->formatted.vm_pool & 0x7F) {
1703 fdirm |= IXGBE_FDIRM_POOL;
1707 hw_dbg(hw, " Error on vm pool mask\n");
1708 return IXGBE_ERR_CONFIG;
1711 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1713 fdirm |= IXGBE_FDIRM_L4P;
1714 if (input_mask->formatted.dst_port ||
1715 input_mask->formatted.src_port) {
1716 hw_dbg(hw, " Error on src/dst port mask\n");
1717 return IXGBE_ERR_CONFIG;
1719 case IXGBE_ATR_L4TYPE_MASK:
1722 hw_dbg(hw, " Error on flow type mask\n");
1723 return IXGBE_ERR_CONFIG;
1726 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1728 /* mask VLAN ID, fall through to mask VLAN priority */
1729 fdirm |= IXGBE_FDIRM_VLANID;
1731 /* mask VLAN priority */
1732 fdirm |= IXGBE_FDIRM_VLANP;
1735 /* mask VLAN ID only, fall through */
1736 fdirm |= IXGBE_FDIRM_VLANID;
1738 /* no VLAN fields masked */
1741 hw_dbg(hw, " Error on VLAN mask\n");
1742 return IXGBE_ERR_CONFIG;
1745 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1747 /* Mask Flex Bytes, fall through */
1748 fdirm |= IXGBE_FDIRM_FLEX;
1752 hw_dbg(hw, " Error on flexible byte mask\n");
1753 return IXGBE_ERR_CONFIG;
1756 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1757 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1759 /* store the TCP/UDP port masks, bit reversed from port layout */
1760 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1762 /* write both the same so that UDP and TCP use the same mask */
1763 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1764 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1766 /* store source and destination IP masks (big-enian) */
1767 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1768 ~input_mask->formatted.src_ip[0]);
1769 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1770 ~input_mask->formatted.dst_ip[0]);
1775 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1776 union ixgbe_atr_input *input,
1777 u16 soft_id, u8 queue)
1779 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1781 /* currently IPv6 is not supported, must be programmed with 0 */
1782 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1783 input->formatted.src_ip[0]);
1784 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1785 input->formatted.src_ip[1]);
1786 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1787 input->formatted.src_ip[2]);
1789 /* record the source address (big-endian) */
1790 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1792 /* record the first 32 bits of the destination address (big-endian) */
1793 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1795 /* record source and destination port (little-endian)*/
1796 fdirport = ntohs(input->formatted.dst_port);
1797 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1798 fdirport |= ntohs(input->formatted.src_port);
1799 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1801 /* record vlan (little-endian) and flex_bytes(big-endian) */
1802 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1803 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1804 fdirvlan |= ntohs(input->formatted.vlan_id);
1805 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1807 /* configure FDIRHASH register */
1808 fdirhash = input->formatted.bkt_hash;
1809 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1810 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1813 * flush all previous writes to make certain registers are
1814 * programmed prior to issuing the command
1816 IXGBE_WRITE_FLUSH(hw);
1818 /* configure FDIRCMD register */
1819 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1820 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1821 if (queue == IXGBE_FDIR_DROP_QUEUE)
1822 fdircmd |= IXGBE_FDIRCMD_DROP;
1823 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1824 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1825 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1827 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1832 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1833 union ixgbe_atr_input *input,
1841 /* configure FDIRHASH register */
1842 fdirhash = input->formatted.bkt_hash;
1843 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1844 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1846 /* flush hash to HW */
1847 IXGBE_WRITE_FLUSH(hw);
1849 /* Query if filter is present */
1850 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1852 for (retry_count = 10; retry_count; retry_count--) {
1853 /* allow 10us for query to process */
1855 /* verify query completed successfully */
1856 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1857 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1862 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1864 /* if filter exists in hardware then remove it */
1865 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1866 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1867 IXGBE_WRITE_FLUSH(hw);
1868 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1869 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1876 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1877 * @hw: pointer to hardware structure
1878 * @reg: analog register to read
1881 * Performs read operation to Omer analog register specified.
1883 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1887 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1889 IXGBE_WRITE_FLUSH(hw);
1891 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1892 *val = (u8)core_ctl;
1898 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1899 * @hw: pointer to hardware structure
1900 * @reg: atlas register to write
1901 * @val: value to write
1903 * Performs write operation to Omer analog register specified.
1905 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1909 core_ctl = (reg << 8) | val;
1910 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1911 IXGBE_WRITE_FLUSH(hw);
1918 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1919 * @hw: pointer to hardware structure
1921 * Starts the hardware using the generic start_hw function
1922 * and the generation start_hw function.
1923 * Then performs revision-specific operations, if any.
1925 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1929 ret_val = ixgbe_start_hw_generic(hw);
1933 ret_val = ixgbe_start_hw_gen2(hw);
1937 /* We need to run link autotry after the driver loads */
1938 hw->mac.autotry_restart = true;
1941 ret_val = ixgbe_verify_fw_version_82599(hw);
1947 * ixgbe_identify_phy_82599 - Get physical layer module
1948 * @hw: pointer to hardware structure
1950 * Determines the physical layer module found on the current adapter.
1951 * If PHY already detected, maintains current PHY type in hw struct,
1952 * otherwise executes the PHY detection routine.
1954 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1956 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1958 /* Detect PHY if not unknown - returns success if already detected. */
1959 status = ixgbe_identify_phy_generic(hw);
1961 /* 82599 10GBASE-T requires an external PHY */
1962 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1965 status = ixgbe_identify_module_generic(hw);
1968 /* Set PHY type none if no PHY detected */
1969 if (hw->phy.type == ixgbe_phy_unknown) {
1970 hw->phy.type = ixgbe_phy_none;
1974 /* Return error if SFP module has been detected but is not supported */
1975 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1976 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1983 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1984 * @hw: pointer to hardware structure
1986 * Determines physical layer capabilities of the current configuration.
1988 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1990 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1991 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1992 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1993 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1994 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1995 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1996 u16 ext_ability = 0;
1997 u8 comp_codes_10g = 0;
1998 u8 comp_codes_1g = 0;
2000 hw->phy.ops.identify(hw);
2002 switch (hw->phy.type) {
2004 case ixgbe_phy_cu_unknown:
2005 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2007 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2008 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2009 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2010 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2011 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2012 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2018 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2019 case IXGBE_AUTOC_LMS_1G_AN:
2020 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2021 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2022 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2023 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2026 /* SFI mode so read SFP module */
2029 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2030 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2031 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2032 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2033 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2034 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2035 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2037 case IXGBE_AUTOC_LMS_10G_SERIAL:
2038 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2039 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2041 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2044 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2045 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2046 if (autoc & IXGBE_AUTOC_KX_SUPP)
2047 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2048 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2049 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2050 if (autoc & IXGBE_AUTOC_KR_SUPP)
2051 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2058 /* SFP check must be done last since DA modules are sometimes used to
2059 * test KR mode - we need to id KR mode correctly before SFP module.
2060 * Call identify_sfp because the pluggable module may have changed */
2061 hw->phy.ops.identify_sfp(hw);
2062 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2065 switch (hw->phy.type) {
2066 case ixgbe_phy_sfp_passive_tyco:
2067 case ixgbe_phy_sfp_passive_unknown:
2068 case ixgbe_phy_qsfp_passive_unknown:
2069 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2071 case ixgbe_phy_sfp_ftl_active:
2072 case ixgbe_phy_sfp_active_unknown:
2073 case ixgbe_phy_qsfp_active_unknown:
2074 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2076 case ixgbe_phy_sfp_avago:
2077 case ixgbe_phy_sfp_ftl:
2078 case ixgbe_phy_sfp_intel:
2079 case ixgbe_phy_sfp_unknown:
2080 hw->phy.ops.read_i2c_eeprom(hw,
2081 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2082 hw->phy.ops.read_i2c_eeprom(hw,
2083 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2084 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2085 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2086 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2087 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2088 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2089 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2091 case ixgbe_phy_qsfp_intel:
2092 case ixgbe_phy_qsfp_unknown:
2093 hw->phy.ops.read_i2c_eeprom(hw,
2094 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
2095 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2096 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2097 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2098 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2105 return physical_layer;
2109 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2110 * @hw: pointer to hardware structure
2111 * @regval: register value to write to RXCTRL
2113 * Enables the Rx DMA unit for 82599
2115 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2118 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2119 * If traffic is incoming before we enable the Rx unit, it could hang
2120 * the Rx DMA unit. Therefore, make sure the security engine is
2121 * completely disabled prior to enabling the Rx unit.
2123 hw->mac.ops.disable_rx_buff(hw);
2125 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2127 hw->mac.ops.enable_rx_buff(hw);
2133 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2134 * @hw: pointer to hardware structure
2136 * Verifies that installed the firmware version is 0.6 or higher
2137 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2139 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2140 * if the FW version is not supported.
2142 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2144 s32 status = IXGBE_ERR_EEPROM_VERSION;
2145 u16 fw_offset, fw_ptp_cfg_offset;
2149 /* firmware check is only necessary for SFI devices */
2150 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2152 goto fw_version_out;
2155 /* get the offset to the Firmware Module block */
2156 offset = IXGBE_FW_PTR;
2157 if (hw->eeprom.ops.read(hw, offset, &fw_offset))
2158 goto fw_version_err;
2160 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2161 goto fw_version_out;
2163 /* get the offset to the Pass Through Patch Configuration block */
2164 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
2165 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset))
2166 goto fw_version_err;
2168 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2169 goto fw_version_out;
2171 /* get the firmware version */
2172 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;
2173 if (hw->eeprom.ops.read(hw, offset, &fw_version))
2174 goto fw_version_err;
2176 if (fw_version > 0x5)
2183 hw_err(hw, "eeprom read at offset %d failed\n", offset);
2184 return IXGBE_ERR_EEPROM_VERSION;
2188 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2189 * @hw: pointer to hardware structure
2191 * Returns true if the LESM FW module is present and enabled. Otherwise
2192 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2194 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2196 bool lesm_enabled = false;
2197 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2200 /* get the offset to the Firmware Module block */
2201 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2203 if ((status != 0) ||
2204 (fw_offset == 0) || (fw_offset == 0xFFFF))
2207 /* get the offset to the LESM Parameters block */
2208 status = hw->eeprom.ops.read(hw, (fw_offset +
2209 IXGBE_FW_LESM_PARAMETERS_PTR),
2210 &fw_lesm_param_offset);
2212 if ((status != 0) ||
2213 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2216 /* get the lesm state word */
2217 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2218 IXGBE_FW_LESM_STATE_1),
2221 if ((status == 0) &&
2222 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2223 lesm_enabled = true;
2226 return lesm_enabled;
2230 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2231 * fastest available method
2233 * @hw: pointer to hardware structure
2234 * @offset: offset of word in EEPROM to read
2235 * @words: number of words
2236 * @data: word(s) read from the EEPROM
2238 * Retrieves 16 bit word(s) read from EEPROM
2240 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2241 u16 words, u16 *data)
2243 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2244 s32 ret_val = IXGBE_ERR_CONFIG;
2247 * If EEPROM is detected and can be addressed using 14 bits,
2248 * use EERD otherwise use bit bang
2250 if ((eeprom->type == ixgbe_eeprom_spi) &&
2251 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2252 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2255 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2263 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2264 * fastest available method
2266 * @hw: pointer to hardware structure
2267 * @offset: offset of word in the EEPROM to read
2268 * @data: word read from the EEPROM
2270 * Reads a 16 bit word from the EEPROM
2272 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2273 u16 offset, u16 *data)
2275 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2276 s32 ret_val = IXGBE_ERR_CONFIG;
2279 * If EEPROM is detected and can be addressed using 14 bits,
2280 * use EERD otherwise use bit bang
2282 if ((eeprom->type == ixgbe_eeprom_spi) &&
2283 (offset <= IXGBE_EERD_MAX_ADDR))
2284 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2286 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2292 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2294 * @hw: pointer to hardware structure
2296 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2297 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2298 * to AUTOC, so this function assumes the semaphore is held.
2300 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2304 u32 i, autoc_reg, autoc2_reg;
2306 /* Enable link if disabled in NVM */
2307 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2308 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2309 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2310 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2311 IXGBE_WRITE_FLUSH(hw);
2314 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2315 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2317 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2318 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2319 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2321 /* Wait for AN to leave state 0 */
2322 for (i = 0; i < 10; i++) {
2323 usleep_range(4000, 8000);
2324 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2325 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2329 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2330 hw_dbg(hw, "auto negotiation not completed\n");
2331 ret_val = IXGBE_ERR_RESET_FAILED;
2332 goto reset_pipeline_out;
2338 /* Write AUTOC register with original LMS field and Restart_AN */
2339 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2340 IXGBE_WRITE_FLUSH(hw);
2346 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2347 * @hw: pointer to hardware structure
2348 * @byte_offset: byte offset to read
2351 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2352 * a specified device address.
2354 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2355 u8 dev_addr, u8 *data)
2361 if (hw->phy.qsfp_shared_i2c_bus == true) {
2362 /* Acquire I2C bus ownership. */
2363 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2364 esdp |= IXGBE_ESDP_SDP0;
2365 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2366 IXGBE_WRITE_FLUSH(hw);
2369 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2370 if (esdp & IXGBE_ESDP_SDP1)
2373 usleep_range(5000, 10000);
2378 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2379 status = IXGBE_ERR_I2C;
2380 goto release_i2c_access;
2384 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2387 if (hw->phy.qsfp_shared_i2c_bus == true) {
2388 /* Release I2C bus ownership. */
2389 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2390 esdp &= ~IXGBE_ESDP_SDP0;
2391 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2392 IXGBE_WRITE_FLUSH(hw);
2399 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2400 * @hw: pointer to hardware structure
2401 * @byte_offset: byte offset to write
2402 * @data: value to write
2404 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2405 * a specified device address.
2407 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2408 u8 dev_addr, u8 data)
2414 if (hw->phy.qsfp_shared_i2c_bus == true) {
2415 /* Acquire I2C bus ownership. */
2416 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2417 esdp |= IXGBE_ESDP_SDP0;
2418 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2419 IXGBE_WRITE_FLUSH(hw);
2422 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2423 if (esdp & IXGBE_ESDP_SDP1)
2426 usleep_range(5000, 10000);
2431 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2432 status = IXGBE_ERR_I2C;
2433 goto release_i2c_access;
2437 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2440 if (hw->phy.qsfp_shared_i2c_bus == true) {
2441 /* Release I2C bus ownership. */
2442 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2443 esdp &= ~IXGBE_ESDP_SDP0;
2444 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2445 IXGBE_WRITE_FLUSH(hw);
2451 static struct ixgbe_mac_operations mac_ops_82599 = {
2452 .init_hw = &ixgbe_init_hw_generic,
2453 .reset_hw = &ixgbe_reset_hw_82599,
2454 .start_hw = &ixgbe_start_hw_82599,
2455 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2456 .get_media_type = &ixgbe_get_media_type_82599,
2457 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2458 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2459 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2460 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2461 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2462 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2463 .get_device_caps = &ixgbe_get_device_caps_generic,
2464 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2465 .stop_adapter = &ixgbe_stop_adapter_generic,
2466 .get_bus_info = &ixgbe_get_bus_info_generic,
2467 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2468 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2469 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2470 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599,
2471 .setup_link = &ixgbe_setup_mac_link_82599,
2472 .set_rxpba = &ixgbe_set_rxpba_generic,
2473 .check_link = &ixgbe_check_mac_link_generic,
2474 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2475 .led_on = &ixgbe_led_on_generic,
2476 .led_off = &ixgbe_led_off_generic,
2477 .blink_led_start = &ixgbe_blink_led_start_generic,
2478 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2479 .set_rar = &ixgbe_set_rar_generic,
2480 .clear_rar = &ixgbe_clear_rar_generic,
2481 .set_vmdq = &ixgbe_set_vmdq_generic,
2482 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2483 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2484 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2485 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2486 .enable_mc = &ixgbe_enable_mc_generic,
2487 .disable_mc = &ixgbe_disable_mc_generic,
2488 .clear_vfta = &ixgbe_clear_vfta_generic,
2489 .set_vfta = &ixgbe_set_vfta_generic,
2490 .fc_enable = &ixgbe_fc_enable_generic,
2491 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2492 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2493 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2494 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2495 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2496 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2497 .release_swfw_sync = &ixgbe_release_swfw_sync,
2498 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2499 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2500 .prot_autoc_read = &prot_autoc_read_82599,
2501 .prot_autoc_write = &prot_autoc_write_82599,
2504 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2505 .init_params = &ixgbe_init_eeprom_params_generic,
2506 .read = &ixgbe_read_eeprom_82599,
2507 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2508 .write = &ixgbe_write_eeprom_generic,
2509 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2510 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2511 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2512 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2515 static struct ixgbe_phy_operations phy_ops_82599 = {
2516 .identify = &ixgbe_identify_phy_82599,
2517 .identify_sfp = &ixgbe_identify_module_generic,
2518 .init = &ixgbe_init_phy_ops_82599,
2519 .reset = &ixgbe_reset_phy_generic,
2520 .read_reg = &ixgbe_read_phy_reg_generic,
2521 .write_reg = &ixgbe_write_phy_reg_generic,
2522 .setup_link = &ixgbe_setup_phy_link_generic,
2523 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2524 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2525 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2526 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2527 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2528 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2529 .check_overtemp = &ixgbe_tn_check_overtemp,
2532 struct ixgbe_info ixgbe_82599_info = {
2533 .mac = ixgbe_mac_82599EB,
2534 .get_invariants = &ixgbe_get_invariants_82599,
2535 .mac_ops = &mac_ops_82599,
2536 .eeprom_ops = &eeprom_ops_82599,
2537 .phy_ops = &phy_ops_82599,
2538 .mbx_ops = &mbx_ops_generic,