1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
62 static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
64 u32 fwsm, manc, factps;
66 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
67 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
70 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
71 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
74 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
75 if (factps & IXGBE_FACTPS_MNGCG)
81 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
83 struct ixgbe_mac_info *mac = &hw->mac;
85 /* enable the laser control functions for SFP+ fiber
88 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
89 !hw->mng_fw_enabled) {
90 mac->ops.disable_tx_laser =
91 &ixgbe_disable_tx_laser_multispeed_fiber;
92 mac->ops.enable_tx_laser =
93 &ixgbe_enable_tx_laser_multispeed_fiber;
94 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
96 mac->ops.disable_tx_laser = NULL;
97 mac->ops.enable_tx_laser = NULL;
98 mac->ops.flap_tx_laser = NULL;
101 if (hw->phy.multispeed_fiber) {
102 /* Set up dual speed SFP+ support */
103 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
105 if ((mac->ops.get_media_type(hw) ==
106 ixgbe_media_type_backplane) &&
107 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
108 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
109 !ixgbe_verify_lesm_fw_enabled_82599(hw))
110 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
112 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
116 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
119 u16 list_offset, data_offset, data_value;
120 bool got_lock = false;
122 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
123 ixgbe_init_mac_link_ops_82599(hw);
125 hw->phy.ops.reset = NULL;
127 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
132 /* PHY config will finish before releasing the semaphore */
133 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
134 IXGBE_GSSR_MAC_CSR_SM);
136 ret_val = IXGBE_ERR_SWFW_SYNC;
140 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
141 while (data_value != 0xffff) {
142 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
143 IXGBE_WRITE_FLUSH(hw);
144 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
147 /* Release the semaphore */
148 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
150 * Delay obtaining semaphore again to allow FW access,
151 * semaphore_delay is in ms usleep_range needs us.
153 usleep_range(hw->eeprom.semaphore_delay * 1000,
154 hw->eeprom.semaphore_delay * 2000);
156 /* Need SW/FW semaphore around AUTOC writes if LESM on,
157 * likewise reset_pipeline requires lock as it also writes
160 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
161 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
162 IXGBE_GSSR_MAC_CSR_SM);
169 /* Restart DSP and set SFI mode */
170 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
171 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
173 ret_val = ixgbe_reset_pipeline_82599(hw);
176 hw->mac.ops.release_swfw_sync(hw,
177 IXGBE_GSSR_MAC_CSR_SM);
182 hw_dbg(hw, " sfp module setup not complete\n");
183 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
192 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
194 struct ixgbe_mac_info *mac = &hw->mac;
196 ixgbe_init_mac_link_ops_82599(hw);
198 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
199 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
200 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
201 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
202 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
203 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
209 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
210 * @hw: pointer to hardware structure
212 * Initialize any function pointers that were not able to be
213 * set during get_invariants because the PHY/SFP type was
214 * not known. Perform the SFP init if necessary.
217 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
219 struct ixgbe_mac_info *mac = &hw->mac;
220 struct ixgbe_phy_info *phy = &hw->phy;
223 /* Identify the PHY or SFP module */
224 ret_val = phy->ops.identify(hw);
226 /* Setup function pointers based on detected SFP module and speeds */
227 ixgbe_init_mac_link_ops_82599(hw);
229 /* If copper media, overwrite with copper function pointers */
230 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
231 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
232 mac->ops.get_link_capabilities =
233 &ixgbe_get_copper_link_capabilities_generic;
236 /* Set necessary function pointers based on phy type */
237 switch (hw->phy.type) {
239 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
240 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
241 phy->ops.get_firmware_version =
242 &ixgbe_get_phy_firmware_version_tnx;
252 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
253 * @hw: pointer to hardware structure
254 * @speed: pointer to link speed
255 * @autoneg: true when autoneg or autotry is enabled
257 * Determines the link capabilities by reading the AUTOC register.
259 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
260 ixgbe_link_speed *speed,
266 /* Determine 1G link capabilities off of SFP+ type */
267 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
268 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
269 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
270 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
271 *speed = IXGBE_LINK_SPEED_1GB_FULL;
277 * Determine link capabilities based on the stored value of AUTOC,
278 * which represents EEPROM defaults. If AUTOC value has not been
279 * stored, use the current register value.
281 if (hw->mac.orig_link_settings_stored)
282 autoc = hw->mac.orig_autoc;
284 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
286 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
287 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
288 *speed = IXGBE_LINK_SPEED_1GB_FULL;
292 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
293 *speed = IXGBE_LINK_SPEED_10GB_FULL;
297 case IXGBE_AUTOC_LMS_1G_AN:
298 *speed = IXGBE_LINK_SPEED_1GB_FULL;
302 case IXGBE_AUTOC_LMS_10G_SERIAL:
303 *speed = IXGBE_LINK_SPEED_10GB_FULL;
307 case IXGBE_AUTOC_LMS_KX4_KX_KR:
308 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
309 *speed = IXGBE_LINK_SPEED_UNKNOWN;
310 if (autoc & IXGBE_AUTOC_KR_SUPP)
311 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
312 if (autoc & IXGBE_AUTOC_KX4_SUPP)
313 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
314 if (autoc & IXGBE_AUTOC_KX_SUPP)
315 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
319 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
320 *speed = IXGBE_LINK_SPEED_100_FULL;
321 if (autoc & IXGBE_AUTOC_KR_SUPP)
322 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
323 if (autoc & IXGBE_AUTOC_KX4_SUPP)
324 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
325 if (autoc & IXGBE_AUTOC_KX_SUPP)
326 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
330 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
331 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
336 status = IXGBE_ERR_LINK_SETUP;
341 if (hw->phy.multispeed_fiber) {
342 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
343 IXGBE_LINK_SPEED_1GB_FULL;
352 * ixgbe_get_media_type_82599 - Get media type
353 * @hw: pointer to hardware structure
355 * Returns the media type (fiber, copper, backplane)
357 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
359 enum ixgbe_media_type media_type;
361 /* Detect if there is a copper PHY attached. */
362 switch (hw->phy.type) {
363 case ixgbe_phy_cu_unknown:
365 media_type = ixgbe_media_type_copper;
371 switch (hw->device_id) {
372 case IXGBE_DEV_ID_82599_KX4:
373 case IXGBE_DEV_ID_82599_KX4_MEZZ:
374 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
375 case IXGBE_DEV_ID_82599_KR:
376 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
377 case IXGBE_DEV_ID_82599_XAUI_LOM:
378 /* Default device ID is mezzanine card KX/KX4 */
379 media_type = ixgbe_media_type_backplane;
381 case IXGBE_DEV_ID_82599_SFP:
382 case IXGBE_DEV_ID_82599_SFP_FCOE:
383 case IXGBE_DEV_ID_82599_SFP_EM:
384 case IXGBE_DEV_ID_82599_SFP_SF2:
385 case IXGBE_DEV_ID_82599_SFP_SF_QP:
386 case IXGBE_DEV_ID_82599EN_SFP:
387 media_type = ixgbe_media_type_fiber;
389 case IXGBE_DEV_ID_82599_CX4:
390 media_type = ixgbe_media_type_cx4;
392 case IXGBE_DEV_ID_82599_T3_LOM:
393 media_type = ixgbe_media_type_copper;
395 case IXGBE_DEV_ID_82599_LS:
396 media_type = ixgbe_media_type_fiber_lco;
399 media_type = ixgbe_media_type_unknown;
407 * ixgbe_start_mac_link_82599 - Setup MAC link settings
408 * @hw: pointer to hardware structure
409 * @autoneg_wait_to_complete: true when waiting for completion is needed
411 * Configures link settings based on values in the ixgbe_hw struct.
412 * Restarts the link. Performs autonegotiation if needed.
414 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
415 bool autoneg_wait_to_complete)
421 bool got_lock = false;
423 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
424 status = hw->mac.ops.acquire_swfw_sync(hw,
425 IXGBE_GSSR_MAC_CSR_SM);
433 ixgbe_reset_pipeline_82599(hw);
436 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
438 /* Only poll for autoneg to complete if specified to do so */
439 if (autoneg_wait_to_complete) {
440 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
441 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
442 IXGBE_AUTOC_LMS_KX4_KX_KR ||
443 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
444 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
445 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
446 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
447 links_reg = 0; /* Just in case Autoneg time = 0 */
448 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
449 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
450 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
454 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
455 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
456 hw_dbg(hw, "Autoneg did not complete.\n");
461 /* Add delay to filter out noises during initial link setup */
469 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
470 * @hw: pointer to hardware structure
472 * The base drivers may require better control over SFP+ module
473 * PHY states. This includes selectively shutting down the Tx
474 * laser on the PHY, effectively halting physical link.
476 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
478 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
480 /* Disable tx laser; allow 100us to go dark per spec */
481 esdp_reg |= IXGBE_ESDP_SDP3;
482 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
483 IXGBE_WRITE_FLUSH(hw);
488 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
489 * @hw: pointer to hardware structure
491 * The base drivers may require better control over SFP+ module
492 * PHY states. This includes selectively turning on the Tx
493 * laser on the PHY, effectively starting physical link.
495 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
497 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
499 /* Enable tx laser; allow 100ms to light up */
500 esdp_reg &= ~IXGBE_ESDP_SDP3;
501 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
502 IXGBE_WRITE_FLUSH(hw);
507 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
508 * @hw: pointer to hardware structure
510 * When the driver changes the link speeds that it can support,
511 * it sets autotry_restart to true to indicate that we need to
512 * initiate a new autotry session with the link partner. To do
513 * so, we set the speed then disable and re-enable the tx laser, to
514 * alert the link partner that it also needs to restart autotry on its
515 * end. This is consistent with true clause 37 autoneg, which also
516 * involves a loss of signal.
518 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
520 if (hw->mac.autotry_restart) {
521 ixgbe_disable_tx_laser_multispeed_fiber(hw);
522 ixgbe_enable_tx_laser_multispeed_fiber(hw);
523 hw->mac.autotry_restart = false;
528 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
529 * @hw: pointer to hardware structure
530 * @speed: new link speed
531 * @autoneg_wait_to_complete: true when waiting for completion is needed
533 * Set the link speed in the AUTOC register and restarts link.
535 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
536 ixgbe_link_speed speed,
537 bool autoneg_wait_to_complete)
540 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
541 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
543 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
545 bool link_up = false;
546 bool autoneg = false;
548 /* Mask off requested but non-supported speeds */
549 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
557 * Try each speed one by one, highest priority first. We do this in
558 * software because 10gb fiber doesn't support speed autonegotiation.
560 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
562 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
564 /* If we already have link at this speed, just jump out */
565 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
570 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
573 /* Set the module link speed */
574 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
575 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
576 IXGBE_WRITE_FLUSH(hw);
578 /* Allow module to change analog characteristics (1G->10G) */
581 status = ixgbe_setup_mac_link_82599(hw,
582 IXGBE_LINK_SPEED_10GB_FULL,
583 autoneg_wait_to_complete);
587 /* Flap the tx laser if it has not already been done */
588 if (hw->mac.ops.flap_tx_laser)
589 hw->mac.ops.flap_tx_laser(hw);
592 * Wait for the controller to acquire link. Per IEEE 802.3ap,
593 * Section 73.10.2, we may have to wait up to 500ms if KR is
594 * attempted. 82599 uses the same timing for 10g SFI.
596 for (i = 0; i < 5; i++) {
597 /* Wait for the link partner to also set speed */
600 /* If we have link, just jump out */
601 status = hw->mac.ops.check_link(hw, &link_speed,
611 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
613 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
614 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
616 /* If we already have link at this speed, just jump out */
617 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
622 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
625 /* Set the module link speed */
626 esdp_reg &= ~IXGBE_ESDP_SDP5;
627 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
628 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
629 IXGBE_WRITE_FLUSH(hw);
631 /* Allow module to change analog characteristics (10G->1G) */
634 status = ixgbe_setup_mac_link_82599(hw,
635 IXGBE_LINK_SPEED_1GB_FULL,
636 autoneg_wait_to_complete);
640 /* Flap the tx laser if it has not already been done */
641 if (hw->mac.ops.flap_tx_laser)
642 hw->mac.ops.flap_tx_laser(hw);
644 /* Wait for the link partner to also set speed */
647 /* If we have link, just jump out */
648 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
658 * We didn't get link. Configure back to the highest speed we tried,
659 * (if there was more than one). We call ourselves back with just the
660 * single highest speed that the user requested.
663 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
665 autoneg_wait_to_complete);
668 /* Set autoneg_advertised value based on input link speed */
669 hw->phy.autoneg_advertised = 0;
671 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
672 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
674 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
675 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
681 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
682 * @hw: pointer to hardware structure
683 * @speed: new link speed
684 * @autoneg_wait_to_complete: true when waiting for completion is needed
686 * Implements the Intel SmartSpeed algorithm.
688 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
689 ixgbe_link_speed speed,
690 bool autoneg_wait_to_complete)
693 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
695 bool link_up = false;
696 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
698 /* Set autoneg_advertised value based on input link speed */
699 hw->phy.autoneg_advertised = 0;
701 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
702 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
704 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
705 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
707 if (speed & IXGBE_LINK_SPEED_100_FULL)
708 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
711 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
712 * autoneg advertisement if link is unable to be established at the
713 * highest negotiated rate. This can sometimes happen due to integrity
714 * issues with the physical media connection.
717 /* First, try to get link with full advertisement */
718 hw->phy.smart_speed_active = false;
719 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
720 status = ixgbe_setup_mac_link_82599(hw, speed,
721 autoneg_wait_to_complete);
726 * Wait for the controller to acquire link. Per IEEE 802.3ap,
727 * Section 73.10.2, we may have to wait up to 500ms if KR is
728 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
729 * Table 9 in the AN MAS.
731 for (i = 0; i < 5; i++) {
734 /* If we have link, just jump out */
735 status = hw->mac.ops.check_link(hw, &link_speed,
746 * We didn't get link. If we advertised KR plus one of KX4/KX
747 * (or BX4/BX), then disable KR and try again.
749 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
750 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
753 /* Turn SmartSpeed on to disable KR support */
754 hw->phy.smart_speed_active = true;
755 status = ixgbe_setup_mac_link_82599(hw, speed,
756 autoneg_wait_to_complete);
761 * Wait for the controller to acquire link. 600ms will allow for
762 * the AN link_fail_inhibit_timer as well for multiple cycles of
763 * parallel detect, both 10g and 1g. This allows for the maximum
764 * connect attempts as defined in the AN MAS table 73-7.
766 for (i = 0; i < 6; i++) {
769 /* If we have link, just jump out */
770 status = hw->mac.ops.check_link(hw, &link_speed,
779 /* We didn't get link. Turn SmartSpeed back off. */
780 hw->phy.smart_speed_active = false;
781 status = ixgbe_setup_mac_link_82599(hw, speed,
782 autoneg_wait_to_complete);
785 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
786 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
787 "the maximum advertised\n");
792 * ixgbe_setup_mac_link_82599 - Set MAC link speed
793 * @hw: pointer to hardware structure
794 * @speed: new link speed
795 * @autoneg_wait_to_complete: true when waiting for completion is needed
797 * Set the link speed in the AUTOC register and restarts link.
799 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
800 ixgbe_link_speed speed,
801 bool autoneg_wait_to_complete)
804 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
805 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
806 u32 start_autoc = autoc;
808 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
809 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
810 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
813 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
814 bool got_lock = false;
815 bool autoneg = false;
817 /* Check to see if speed passed in is supported. */
818 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
823 speed &= link_capabilities;
825 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
826 status = IXGBE_ERR_LINK_SETUP;
830 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
831 if (hw->mac.orig_link_settings_stored)
832 orig_autoc = hw->mac.orig_autoc;
836 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
837 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
838 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
839 /* Set KX4/KX/KR support according to speed requested */
840 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
841 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
842 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
843 autoc |= IXGBE_AUTOC_KX4_SUPP;
844 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
845 (hw->phy.smart_speed_active == false))
846 autoc |= IXGBE_AUTOC_KR_SUPP;
848 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
849 autoc |= IXGBE_AUTOC_KX_SUPP;
850 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
851 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
852 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
853 /* Switch from 1G SFI to 10G SFI if requested */
854 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
855 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
856 autoc &= ~IXGBE_AUTOC_LMS_MASK;
857 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
859 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
860 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
861 /* Switch from 10G SFI to 1G SFI if requested */
862 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
863 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
864 autoc &= ~IXGBE_AUTOC_LMS_MASK;
866 autoc |= IXGBE_AUTOC_LMS_1G_AN;
868 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
872 if (autoc != start_autoc) {
873 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
874 * likewise reset_pipeline requires us to hold this lock as
875 * it also writes to AUTOC.
877 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
878 status = hw->mac.ops.acquire_swfw_sync(hw,
879 IXGBE_GSSR_MAC_CSR_SM);
887 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
888 ixgbe_reset_pipeline_82599(hw);
891 hw->mac.ops.release_swfw_sync(hw,
892 IXGBE_GSSR_MAC_CSR_SM);
894 /* Only poll for autoneg to complete if specified to do so */
895 if (autoneg_wait_to_complete) {
896 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
897 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
898 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
899 links_reg = 0; /*Just in case Autoneg time=0*/
900 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
902 IXGBE_READ_REG(hw, IXGBE_LINKS);
903 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
907 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
909 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
910 hw_dbg(hw, "Autoneg did not "
916 /* Add delay to filter out noises during initial link setup */
925 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
926 * @hw: pointer to hardware structure
927 * @speed: new link speed
928 * @autoneg_wait_to_complete: true if waiting is needed to complete
930 * Restarts link on PHY and MAC based on settings passed in.
932 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
933 ixgbe_link_speed speed,
934 bool autoneg_wait_to_complete)
938 /* Setup the PHY according to input speed */
939 status = hw->phy.ops.setup_link_speed(hw, speed,
940 autoneg_wait_to_complete);
942 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
948 * ixgbe_reset_hw_82599 - Perform hardware reset
949 * @hw: pointer to hardware structure
951 * Resets the hardware by resetting the transmit and receive units, masks
952 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
955 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
957 ixgbe_link_speed link_speed;
959 u32 ctrl, i, autoc, autoc2;
961 bool link_up = false;
963 /* Call adapter stop to disable tx/rx and clear interrupts */
964 status = hw->mac.ops.stop_adapter(hw);
968 /* flush pending Tx transactions */
969 ixgbe_clear_tx_pending(hw);
971 /* PHY ops must be identified and initialized prior to reset */
973 /* Identify PHY and related function pointers */
974 status = hw->phy.ops.init(hw);
976 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
979 /* Setup SFP module if there is one present. */
980 if (hw->phy.sfp_setup_needed) {
981 status = hw->mac.ops.setup_sfp(hw);
982 hw->phy.sfp_setup_needed = false;
985 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
989 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
990 hw->phy.ops.reset(hw);
992 /* remember AUTOC LMS from before we reset */
993 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
997 * Issue global reset to the MAC. Needs to be SW reset if link is up.
998 * If link reset is used when link is up, it might reset the PHY when
999 * mng is using it. If link is down or the flag to force full link
1000 * reset is set, then perform link reset.
1002 ctrl = IXGBE_CTRL_LNK_RST;
1003 if (!hw->force_full_reset) {
1004 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1006 ctrl = IXGBE_CTRL_RST;
1009 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1010 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1011 IXGBE_WRITE_FLUSH(hw);
1013 /* Poll for reset bit to self-clear indicating reset is complete */
1014 for (i = 0; i < 10; i++) {
1016 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1017 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1021 if (ctrl & IXGBE_CTRL_RST_MASK) {
1022 status = IXGBE_ERR_RESET_FAILED;
1023 hw_dbg(hw, "Reset polling failed to complete.\n");
1029 * Double resets are required for recovery from certain error
1030 * conditions. Between resets, it is necessary to stall to allow time
1031 * for any pending HW events to complete.
1033 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1034 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1039 * Store the original AUTOC/AUTOC2 values if they have not been
1040 * stored off yet. Otherwise restore the stored original
1041 * values since the reset operation sets back to defaults.
1043 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1044 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1045 if (hw->mac.orig_link_settings_stored == false) {
1046 hw->mac.orig_autoc = autoc;
1047 hw->mac.orig_autoc2 = autoc2;
1048 hw->mac.orig_link_settings_stored = true;
1051 /* If MNG FW is running on a multi-speed device that
1052 * doesn't autoneg with out driver support we need to
1053 * leave LMS in the state it was before we MAC reset.
1054 * Likewise if we support WoL we don't want change the
1057 if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
1059 hw->mac.orig_autoc =
1060 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1063 if (autoc != hw->mac.orig_autoc) {
1064 /* Need SW/FW semaphore around AUTOC writes if LESM is
1065 * on, likewise reset_pipeline requires us to hold
1066 * this lock as it also writes to AUTOC.
1068 bool got_lock = false;
1069 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1070 status = hw->mac.ops.acquire_swfw_sync(hw,
1071 IXGBE_GSSR_MAC_CSR_SM);
1078 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1079 ixgbe_reset_pipeline_82599(hw);
1082 hw->mac.ops.release_swfw_sync(hw,
1083 IXGBE_GSSR_MAC_CSR_SM);
1086 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1087 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1088 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1089 autoc2 |= (hw->mac.orig_autoc2 &
1090 IXGBE_AUTOC2_UPPER_MASK);
1091 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1095 /* Store the permanent mac address */
1096 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1099 * Store MAC address from RAR0, clear receive address registers, and
1100 * clear the multicast table. Also reset num_rar_entries to 128,
1101 * since we modify this value when programming the SAN MAC address.
1103 hw->mac.num_rar_entries = 128;
1104 hw->mac.ops.init_rx_addrs(hw);
1106 /* Store the permanent SAN mac address */
1107 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1109 /* Add the SAN MAC address to the RAR only if it's a valid address */
1110 if (is_valid_ether_addr(hw->mac.san_addr)) {
1111 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1112 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1114 /* Save the SAN MAC RAR index */
1115 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1117 /* Reserve the last RAR for the SAN MAC address */
1118 hw->mac.num_rar_entries--;
1121 /* Store the alternative WWNN/WWPN prefix */
1122 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1123 &hw->mac.wwpn_prefix);
1130 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1131 * @hw: pointer to hardware structure
1133 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1136 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1137 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1140 * Before starting reinitialization process,
1141 * FDIRCMD.CMD must be zero.
1143 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1144 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1145 IXGBE_FDIRCMD_CMD_MASK))
1149 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1150 hw_dbg(hw, "Flow Director previous command isn't complete, "
1151 "aborting table re-initialization.\n");
1152 return IXGBE_ERR_FDIR_REINIT_FAILED;
1155 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1156 IXGBE_WRITE_FLUSH(hw);
1158 * 82599 adapters flow director init flow cannot be restarted,
1159 * Workaround 82599 silicon errata by performing the following steps
1160 * before re-writing the FDIRCTRL control register with the same value.
1161 * - write 1 to bit 8 of FDIRCMD register &
1162 * - write 0 to bit 8 of FDIRCMD register
1164 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1165 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1166 IXGBE_FDIRCMD_CLEARHT));
1167 IXGBE_WRITE_FLUSH(hw);
1168 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1169 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1170 ~IXGBE_FDIRCMD_CLEARHT));
1171 IXGBE_WRITE_FLUSH(hw);
1173 * Clear FDIR Hash register to clear any leftover hashes
1174 * waiting to be programmed.
1176 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1177 IXGBE_WRITE_FLUSH(hw);
1179 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1180 IXGBE_WRITE_FLUSH(hw);
1182 /* Poll init-done after we write FDIRCTRL register */
1183 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1184 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1185 IXGBE_FDIRCTRL_INIT_DONE)
1187 usleep_range(1000, 2000);
1189 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1190 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1191 return IXGBE_ERR_FDIR_REINIT_FAILED;
1194 /* Clear FDIR statistics registers (read to clear) */
1195 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1196 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1197 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1198 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1199 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1205 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1206 * @hw: pointer to hardware structure
1207 * @fdirctrl: value to write to flow director control register
1209 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1213 /* Prime the keys for hashing */
1214 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1215 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1218 * Poll init-done after we write the register. Estimated times:
1219 * 10G: PBALLOC = 11b, timing is 60us
1220 * 1G: PBALLOC = 11b, timing is 600us
1221 * 100M: PBALLOC = 11b, timing is 6ms
1223 * Multiple these timings by 4 if under full Rx load
1225 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1226 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1227 * this might not finish in our poll time, but we can live with that
1230 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1231 IXGBE_WRITE_FLUSH(hw);
1232 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1233 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1234 IXGBE_FDIRCTRL_INIT_DONE)
1236 usleep_range(1000, 2000);
1239 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1240 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1244 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1245 * @hw: pointer to hardware structure
1246 * @fdirctrl: value to write to flow director control register, initially
1247 * contains just the value of the Rx packet buffer allocation
1249 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1252 * Continue setup of fdirctrl register bits:
1253 * Move the flexible bytes to use the ethertype - shift 6 words
1254 * Set the maximum length per hash bucket to 0xA filters
1255 * Send interrupt when 64 filters are left
1257 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1258 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1259 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1261 /* write hashes and fdirctrl register, poll for completion */
1262 ixgbe_fdir_enable_82599(hw, fdirctrl);
1268 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1269 * @hw: pointer to hardware structure
1270 * @fdirctrl: value to write to flow director control register, initially
1271 * contains just the value of the Rx packet buffer allocation
1273 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1276 * Continue setup of fdirctrl register bits:
1277 * Turn perfect match filtering on
1278 * Report hash in RSS field of Rx wb descriptor
1279 * Initialize the drop queue
1280 * Move the flexible bytes to use the ethertype - shift 6 words
1281 * Set the maximum length per hash bucket to 0xA filters
1282 * Send interrupt when 64 (0x4 * 16) filters are left
1284 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1285 IXGBE_FDIRCTRL_REPORT_STATUS |
1286 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1287 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1288 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1289 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1291 /* write hashes and fdirctrl register, poll for completion */
1292 ixgbe_fdir_enable_82599(hw, fdirctrl);
1298 * These defines allow us to quickly generate all of the necessary instructions
1299 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1300 * for values 0 through 15
1302 #define IXGBE_ATR_COMMON_HASH_KEY \
1303 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1304 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1307 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1308 common_hash ^= lo_hash_dword >> n; \
1309 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1310 bucket_hash ^= lo_hash_dword >> n; \
1311 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1312 sig_hash ^= lo_hash_dword << (16 - n); \
1313 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1314 common_hash ^= hi_hash_dword >> n; \
1315 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1316 bucket_hash ^= hi_hash_dword >> n; \
1317 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1318 sig_hash ^= hi_hash_dword << (16 - n); \
1322 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1323 * @stream: input bitstream to compute the hash on
1325 * This function is almost identical to the function above but contains
1326 * several optomizations such as unwinding all of the loops, letting the
1327 * compiler work out all of the conditional ifs since the keys are static
1328 * defines, and computing two keys at once since the hashed dword stream
1329 * will be the same for both keys.
1331 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1332 union ixgbe_atr_hash_dword common)
1334 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1335 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1337 /* record the flow_vm_vlan bits as they are a key part to the hash */
1338 flow_vm_vlan = ntohl(input.dword);
1340 /* generate common hash dword */
1341 hi_hash_dword = ntohl(common.dword);
1343 /* low dword is word swapped version of common */
1344 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1346 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1347 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1349 /* Process bits 0 and 16 */
1350 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1353 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1354 * delay this because bit 0 of the stream should not be processed
1355 * so we do not add the vlan until after bit 0 was processed
1357 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1359 /* Process remaining 30 bit of the key */
1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1365 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1366 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1367 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1368 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1369 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1370 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1371 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1372 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1373 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1374 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1376 /* combine common_hash result with signature and bucket hashes */
1377 bucket_hash ^= common_hash;
1378 bucket_hash &= IXGBE_ATR_HASH_MASK;
1380 sig_hash ^= common_hash << 16;
1381 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1383 /* return completed signature hash */
1384 return sig_hash ^ bucket_hash;
1388 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1389 * @hw: pointer to hardware structure
1390 * @input: unique input dword
1391 * @common: compressed common input dword
1392 * @queue: queue index to direct traffic to
1394 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1395 union ixgbe_atr_hash_dword input,
1396 union ixgbe_atr_hash_dword common,
1403 * Get the flow_type in order to program FDIRCMD properly
1404 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1406 switch (input.formatted.flow_type) {
1407 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1408 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1409 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1410 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1411 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1412 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1415 hw_dbg(hw, " Error on flow type input\n");
1416 return IXGBE_ERR_CONFIG;
1419 /* configure FDIRCMD register */
1420 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1421 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1422 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1423 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1426 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1427 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1429 fdirhashcmd = (u64)fdircmd << 32;
1430 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1431 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1433 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1438 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1441 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1442 bucket_hash ^= lo_hash_dword >> n; \
1443 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1444 bucket_hash ^= hi_hash_dword >> n; \
1448 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1449 * @atr_input: input bitstream to compute the hash on
1450 * @input_mask: mask for the input bitstream
1452 * This function serves two main purposes. First it applys the input_mask
1453 * to the atr_input resulting in a cleaned up atr_input data stream.
1454 * Secondly it computes the hash and stores it in the bkt_hash field at
1455 * the end of the input byte stream. This way it will be available for
1456 * future use without needing to recompute the hash.
1458 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1459 union ixgbe_atr_input *input_mask)
1462 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1463 u32 bucket_hash = 0;
1465 /* Apply masks to input data */
1466 input->dword_stream[0] &= input_mask->dword_stream[0];
1467 input->dword_stream[1] &= input_mask->dword_stream[1];
1468 input->dword_stream[2] &= input_mask->dword_stream[2];
1469 input->dword_stream[3] &= input_mask->dword_stream[3];
1470 input->dword_stream[4] &= input_mask->dword_stream[4];
1471 input->dword_stream[5] &= input_mask->dword_stream[5];
1472 input->dword_stream[6] &= input_mask->dword_stream[6];
1473 input->dword_stream[7] &= input_mask->dword_stream[7];
1474 input->dword_stream[8] &= input_mask->dword_stream[8];
1475 input->dword_stream[9] &= input_mask->dword_stream[9];
1476 input->dword_stream[10] &= input_mask->dword_stream[10];
1478 /* record the flow_vm_vlan bits as they are a key part to the hash */
1479 flow_vm_vlan = ntohl(input->dword_stream[0]);
1481 /* generate common hash dword */
1482 hi_hash_dword = ntohl(input->dword_stream[1] ^
1483 input->dword_stream[2] ^
1484 input->dword_stream[3] ^
1485 input->dword_stream[4] ^
1486 input->dword_stream[5] ^
1487 input->dword_stream[6] ^
1488 input->dword_stream[7] ^
1489 input->dword_stream[8] ^
1490 input->dword_stream[9] ^
1491 input->dword_stream[10]);
1493 /* low dword is word swapped version of common */
1494 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1496 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1497 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1499 /* Process bits 0 and 16 */
1500 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1503 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1504 * delay this because bit 0 of the stream should not be processed
1505 * so we do not add the vlan until after bit 0 was processed
1507 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1509 /* Process remaining 30 bit of the key */
1510 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1511 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1515 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1516 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1517 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1518 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1519 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1520 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1521 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1522 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1523 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1524 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1527 * Limit hash to 13 bits since max bucket count is 8K.
1528 * Store result at the end of the input stream.
1530 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1534 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1535 * @input_mask: mask to be bit swapped
1537 * The source and destination port masks for flow director are bit swapped
1538 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1539 * generate a correctly swapped value we need to bit swap the mask and that
1540 * is what is accomplished by this function.
1542 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1544 u32 mask = ntohs(input_mask->formatted.dst_port);
1545 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1546 mask |= ntohs(input_mask->formatted.src_port);
1547 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1548 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1549 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1550 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1554 * These two macros are meant to address the fact that we have registers
1555 * that are either all or in part big-endian. As a result on big-endian
1556 * systems we will end up byte swapping the value to little-endian before
1557 * it is byte swapped again and written to the hardware in the original
1558 * big-endian format.
1560 #define IXGBE_STORE_AS_BE32(_value) \
1561 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1562 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1564 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1565 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1567 #define IXGBE_STORE_AS_BE16(_value) \
1568 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1570 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1571 union ixgbe_atr_input *input_mask)
1573 /* mask IPv6 since it is currently not supported */
1574 u32 fdirm = IXGBE_FDIRM_DIPv6;
1578 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1579 * are zero, then assume a full mask for that field. Also assume that
1580 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1581 * cannot be masked out in this implementation.
1583 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1587 /* verify bucket hash is cleared on hash generation */
1588 if (input_mask->formatted.bkt_hash)
1589 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1591 /* Program FDIRM and verify partial masks */
1592 switch (input_mask->formatted.vm_pool & 0x7F) {
1594 fdirm |= IXGBE_FDIRM_POOL;
1598 hw_dbg(hw, " Error on vm pool mask\n");
1599 return IXGBE_ERR_CONFIG;
1602 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1604 fdirm |= IXGBE_FDIRM_L4P;
1605 if (input_mask->formatted.dst_port ||
1606 input_mask->formatted.src_port) {
1607 hw_dbg(hw, " Error on src/dst port mask\n");
1608 return IXGBE_ERR_CONFIG;
1610 case IXGBE_ATR_L4TYPE_MASK:
1613 hw_dbg(hw, " Error on flow type mask\n");
1614 return IXGBE_ERR_CONFIG;
1617 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1619 /* mask VLAN ID, fall through to mask VLAN priority */
1620 fdirm |= IXGBE_FDIRM_VLANID;
1622 /* mask VLAN priority */
1623 fdirm |= IXGBE_FDIRM_VLANP;
1626 /* mask VLAN ID only, fall through */
1627 fdirm |= IXGBE_FDIRM_VLANID;
1629 /* no VLAN fields masked */
1632 hw_dbg(hw, " Error on VLAN mask\n");
1633 return IXGBE_ERR_CONFIG;
1636 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1638 /* Mask Flex Bytes, fall through */
1639 fdirm |= IXGBE_FDIRM_FLEX;
1643 hw_dbg(hw, " Error on flexible byte mask\n");
1644 return IXGBE_ERR_CONFIG;
1647 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1648 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1650 /* store the TCP/UDP port masks, bit reversed from port layout */
1651 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1653 /* write both the same so that UDP and TCP use the same mask */
1654 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1655 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1657 /* store source and destination IP masks (big-enian) */
1658 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1659 ~input_mask->formatted.src_ip[0]);
1660 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1661 ~input_mask->formatted.dst_ip[0]);
1666 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1667 union ixgbe_atr_input *input,
1668 u16 soft_id, u8 queue)
1670 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1672 /* currently IPv6 is not supported, must be programmed with 0 */
1673 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1674 input->formatted.src_ip[0]);
1675 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1676 input->formatted.src_ip[1]);
1677 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1678 input->formatted.src_ip[2]);
1680 /* record the source address (big-endian) */
1681 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1683 /* record the first 32 bits of the destination address (big-endian) */
1684 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1686 /* record source and destination port (little-endian)*/
1687 fdirport = ntohs(input->formatted.dst_port);
1688 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1689 fdirport |= ntohs(input->formatted.src_port);
1690 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1692 /* record vlan (little-endian) and flex_bytes(big-endian) */
1693 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1694 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1695 fdirvlan |= ntohs(input->formatted.vlan_id);
1696 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1698 /* configure FDIRHASH register */
1699 fdirhash = input->formatted.bkt_hash;
1700 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1701 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1704 * flush all previous writes to make certain registers are
1705 * programmed prior to issuing the command
1707 IXGBE_WRITE_FLUSH(hw);
1709 /* configure FDIRCMD register */
1710 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1711 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1712 if (queue == IXGBE_FDIR_DROP_QUEUE)
1713 fdircmd |= IXGBE_FDIRCMD_DROP;
1714 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1715 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1716 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1718 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1723 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1724 union ixgbe_atr_input *input,
1732 /* configure FDIRHASH register */
1733 fdirhash = input->formatted.bkt_hash;
1734 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1735 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1737 /* flush hash to HW */
1738 IXGBE_WRITE_FLUSH(hw);
1740 /* Query if filter is present */
1741 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1743 for (retry_count = 10; retry_count; retry_count--) {
1744 /* allow 10us for query to process */
1746 /* verify query completed successfully */
1747 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1748 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1753 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1755 /* if filter exists in hardware then remove it */
1756 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1757 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1758 IXGBE_WRITE_FLUSH(hw);
1759 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1760 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1767 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1768 * @hw: pointer to hardware structure
1769 * @reg: analog register to read
1772 * Performs read operation to Omer analog register specified.
1774 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1778 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1780 IXGBE_WRITE_FLUSH(hw);
1782 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1783 *val = (u8)core_ctl;
1789 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1790 * @hw: pointer to hardware structure
1791 * @reg: atlas register to write
1792 * @val: value to write
1794 * Performs write operation to Omer analog register specified.
1796 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1800 core_ctl = (reg << 8) | val;
1801 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1802 IXGBE_WRITE_FLUSH(hw);
1809 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1810 * @hw: pointer to hardware structure
1812 * Starts the hardware using the generic start_hw function
1813 * and the generation start_hw function.
1814 * Then performs revision-specific operations, if any.
1816 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1820 ret_val = ixgbe_start_hw_generic(hw);
1824 ret_val = ixgbe_start_hw_gen2(hw);
1828 /* We need to run link autotry after the driver loads */
1829 hw->mac.autotry_restart = true;
1830 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1833 ret_val = ixgbe_verify_fw_version_82599(hw);
1839 * ixgbe_identify_phy_82599 - Get physical layer module
1840 * @hw: pointer to hardware structure
1842 * Determines the physical layer module found on the current adapter.
1843 * If PHY already detected, maintains current PHY type in hw struct,
1844 * otherwise executes the PHY detection routine.
1846 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1848 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1850 /* Detect PHY if not unknown - returns success if already detected. */
1851 status = ixgbe_identify_phy_generic(hw);
1853 /* 82599 10GBASE-T requires an external PHY */
1854 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1857 status = ixgbe_identify_sfp_module_generic(hw);
1860 /* Set PHY type none if no PHY detected */
1861 if (hw->phy.type == ixgbe_phy_unknown) {
1862 hw->phy.type = ixgbe_phy_none;
1866 /* Return error if SFP module has been detected but is not supported */
1867 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1868 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1875 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1876 * @hw: pointer to hardware structure
1878 * Determines physical layer capabilities of the current configuration.
1880 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1882 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1883 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1884 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1885 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1886 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1887 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1888 u16 ext_ability = 0;
1889 u8 comp_codes_10g = 0;
1890 u8 comp_codes_1g = 0;
1892 hw->phy.ops.identify(hw);
1894 switch (hw->phy.type) {
1896 case ixgbe_phy_cu_unknown:
1897 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1899 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1900 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1901 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1902 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1903 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1904 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1910 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1911 case IXGBE_AUTOC_LMS_1G_AN:
1912 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1913 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1914 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1915 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1918 /* SFI mode so read SFP module */
1921 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1922 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1923 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1924 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1925 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1926 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1927 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1930 case IXGBE_AUTOC_LMS_10G_SERIAL:
1931 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1932 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1934 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1937 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1938 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1939 if (autoc & IXGBE_AUTOC_KX_SUPP)
1940 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1941 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1942 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1943 if (autoc & IXGBE_AUTOC_KR_SUPP)
1944 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1953 /* SFP check must be done last since DA modules are sometimes used to
1954 * test KR mode - we need to id KR mode correctly before SFP module.
1955 * Call identify_sfp because the pluggable module may have changed */
1956 hw->phy.ops.identify_sfp(hw);
1957 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1960 switch (hw->phy.type) {
1961 case ixgbe_phy_sfp_passive_tyco:
1962 case ixgbe_phy_sfp_passive_unknown:
1963 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1965 case ixgbe_phy_sfp_ftl_active:
1966 case ixgbe_phy_sfp_active_unknown:
1967 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1969 case ixgbe_phy_sfp_avago:
1970 case ixgbe_phy_sfp_ftl:
1971 case ixgbe_phy_sfp_intel:
1972 case ixgbe_phy_sfp_unknown:
1973 hw->phy.ops.read_i2c_eeprom(hw,
1974 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1975 hw->phy.ops.read_i2c_eeprom(hw,
1976 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1977 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1978 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1979 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1980 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1981 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1982 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1989 return physical_layer;
1993 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1994 * @hw: pointer to hardware structure
1995 * @regval: register value to write to RXCTRL
1997 * Enables the Rx DMA unit for 82599
1999 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2002 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2003 * If traffic is incoming before we enable the Rx unit, it could hang
2004 * the Rx DMA unit. Therefore, make sure the security engine is
2005 * completely disabled prior to enabling the Rx unit.
2007 hw->mac.ops.disable_rx_buff(hw);
2009 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2011 hw->mac.ops.enable_rx_buff(hw);
2017 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2018 * @hw: pointer to hardware structure
2020 * Verifies that installed the firmware version is 0.6 or higher
2021 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2023 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2024 * if the FW version is not supported.
2026 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2028 s32 status = IXGBE_ERR_EEPROM_VERSION;
2029 u16 fw_offset, fw_ptp_cfg_offset;
2032 /* firmware check is only necessary for SFI devices */
2033 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2035 goto fw_version_out;
2038 /* get the offset to the Firmware Module block */
2039 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2041 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2042 goto fw_version_out;
2044 /* get the offset to the Pass Through Patch Configuration block */
2045 hw->eeprom.ops.read(hw, (fw_offset +
2046 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2047 &fw_ptp_cfg_offset);
2049 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2050 goto fw_version_out;
2052 /* get the firmware version */
2053 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2054 IXGBE_FW_PATCH_VERSION_4),
2057 if (fw_version > 0x5)
2065 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2066 * @hw: pointer to hardware structure
2068 * Returns true if the LESM FW module is present and enabled. Otherwise
2069 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2071 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2073 bool lesm_enabled = false;
2074 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2077 /* get the offset to the Firmware Module block */
2078 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2080 if ((status != 0) ||
2081 (fw_offset == 0) || (fw_offset == 0xFFFF))
2084 /* get the offset to the LESM Parameters block */
2085 status = hw->eeprom.ops.read(hw, (fw_offset +
2086 IXGBE_FW_LESM_PARAMETERS_PTR),
2087 &fw_lesm_param_offset);
2089 if ((status != 0) ||
2090 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2093 /* get the lesm state word */
2094 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2095 IXGBE_FW_LESM_STATE_1),
2098 if ((status == 0) &&
2099 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2100 lesm_enabled = true;
2103 return lesm_enabled;
2107 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2108 * fastest available method
2110 * @hw: pointer to hardware structure
2111 * @offset: offset of word in EEPROM to read
2112 * @words: number of words
2113 * @data: word(s) read from the EEPROM
2115 * Retrieves 16 bit word(s) read from EEPROM
2117 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2118 u16 words, u16 *data)
2120 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2121 s32 ret_val = IXGBE_ERR_CONFIG;
2124 * If EEPROM is detected and can be addressed using 14 bits,
2125 * use EERD otherwise use bit bang
2127 if ((eeprom->type == ixgbe_eeprom_spi) &&
2128 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2129 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2132 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2140 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2141 * fastest available method
2143 * @hw: pointer to hardware structure
2144 * @offset: offset of word in the EEPROM to read
2145 * @data: word read from the EEPROM
2147 * Reads a 16 bit word from the EEPROM
2149 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2150 u16 offset, u16 *data)
2152 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2153 s32 ret_val = IXGBE_ERR_CONFIG;
2156 * If EEPROM is detected and can be addressed using 14 bits,
2157 * use EERD otherwise use bit bang
2159 if ((eeprom->type == ixgbe_eeprom_spi) &&
2160 (offset <= IXGBE_EERD_MAX_ADDR))
2161 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2163 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2169 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2171 * @hw: pointer to hardware structure
2173 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2174 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2175 * to AUTOC, so this function assumes the semaphore is held.
2177 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2179 s32 i, autoc_reg, ret_val;
2182 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2183 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2185 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2186 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2188 /* Wait for AN to leave state 0 */
2189 for (i = 0; i < 10; i++) {
2190 usleep_range(4000, 8000);
2191 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2192 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2196 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2197 hw_dbg(hw, "auto negotiation not completed\n");
2198 ret_val = IXGBE_ERR_RESET_FAILED;
2199 goto reset_pipeline_out;
2205 /* Write AUTOC register with original LMS field and Restart_AN */
2206 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2207 IXGBE_WRITE_FLUSH(hw);
2212 static struct ixgbe_mac_operations mac_ops_82599 = {
2213 .init_hw = &ixgbe_init_hw_generic,
2214 .reset_hw = &ixgbe_reset_hw_82599,
2215 .start_hw = &ixgbe_start_hw_82599,
2216 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2217 .get_media_type = &ixgbe_get_media_type_82599,
2218 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2219 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2220 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2221 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2222 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2223 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2224 .get_device_caps = &ixgbe_get_device_caps_generic,
2225 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2226 .stop_adapter = &ixgbe_stop_adapter_generic,
2227 .get_bus_info = &ixgbe_get_bus_info_generic,
2228 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2229 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2230 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2231 .setup_link = &ixgbe_setup_mac_link_82599,
2232 .set_rxpba = &ixgbe_set_rxpba_generic,
2233 .check_link = &ixgbe_check_mac_link_generic,
2234 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2235 .led_on = &ixgbe_led_on_generic,
2236 .led_off = &ixgbe_led_off_generic,
2237 .blink_led_start = &ixgbe_blink_led_start_generic,
2238 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2239 .set_rar = &ixgbe_set_rar_generic,
2240 .clear_rar = &ixgbe_clear_rar_generic,
2241 .set_vmdq = &ixgbe_set_vmdq_generic,
2242 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2243 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2244 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2245 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2246 .enable_mc = &ixgbe_enable_mc_generic,
2247 .disable_mc = &ixgbe_disable_mc_generic,
2248 .clear_vfta = &ixgbe_clear_vfta_generic,
2249 .set_vfta = &ixgbe_set_vfta_generic,
2250 .fc_enable = &ixgbe_fc_enable_generic,
2251 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2252 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2253 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2254 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2255 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2256 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2257 .release_swfw_sync = &ixgbe_release_swfw_sync,
2258 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2259 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2260 .mng_fw_enabled = &ixgbe_mng_enabled,
2263 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2264 .init_params = &ixgbe_init_eeprom_params_generic,
2265 .read = &ixgbe_read_eeprom_82599,
2266 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2267 .write = &ixgbe_write_eeprom_generic,
2268 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2269 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2270 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2271 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2274 static struct ixgbe_phy_operations phy_ops_82599 = {
2275 .identify = &ixgbe_identify_phy_82599,
2276 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2277 .init = &ixgbe_init_phy_ops_82599,
2278 .reset = &ixgbe_reset_phy_generic,
2279 .read_reg = &ixgbe_read_phy_reg_generic,
2280 .write_reg = &ixgbe_write_phy_reg_generic,
2281 .setup_link = &ixgbe_setup_phy_link_generic,
2282 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2283 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2284 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2285 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2286 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2287 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2288 .check_overtemp = &ixgbe_tn_check_overtemp,
2291 struct ixgbe_info ixgbe_82599_info = {
2292 .mac = ixgbe_mac_82599EB,
2293 .get_invariants = &ixgbe_get_invariants_82599,
2294 .mac_ops = &mac_ops_82599,
2295 .eeprom_ops = &eeprom_ops_82599,
2296 .phy_ops = &phy_ops_82599,
2297 .mbx_ops = &mbx_ops_generic,