1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
69 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
70 __stringify(BUILD) "-k"
71 const char ixgbe_driver_version[] = DRV_VERSION;
72 static const char ixgbe_copyright[] =
73 "Copyright (c) 1999-2012 Intel Corporation.";
75 static const struct ixgbe_info *ixgbe_info_tbl[] = {
76 [board_82598] = &ixgbe_82598_info,
77 [board_82599] = &ixgbe_82599_info,
78 [board_X540] = &ixgbe_X540_info,
81 /* ixgbe_pci_tbl - PCI Device ID Table
83 * Wildcard entries (PCI_ANY_ID) should come last
84 * Last entry must be all 0s
86 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
87 * Class, Class Mask, private data (not used) }
89 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
119 /* required last entry */
122 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
124 #ifdef CONFIG_IXGBE_DCA
125 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
127 static struct notifier_block dca_notifier = {
128 .notifier_call = ixgbe_notify_dca,
134 #ifdef CONFIG_PCI_IOV
135 static unsigned int max_vfs;
136 module_param(max_vfs, uint, 0);
137 MODULE_PARM_DESC(max_vfs,
138 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
139 #endif /* CONFIG_PCI_IOV */
141 static unsigned int allow_unsupported_sfp;
142 module_param(allow_unsupported_sfp, uint, 0);
143 MODULE_PARM_DESC(allow_unsupported_sfp,
144 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
146 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
147 static int debug = -1;
148 module_param(debug, int, 0);
149 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
151 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
152 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
153 MODULE_LICENSE("GPL");
154 MODULE_VERSION(DRV_VERSION);
156 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
158 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
159 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
160 schedule_work(&adapter->service_task);
163 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
165 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
167 /* flush memory to make sure state is correct before next watchdog */
168 smp_mb__before_clear_bit();
169 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
172 struct ixgbe_reg_info {
177 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
179 /* General Registers */
180 {IXGBE_CTRL, "CTRL"},
181 {IXGBE_STATUS, "STATUS"},
182 {IXGBE_CTRL_EXT, "CTRL_EXT"},
184 /* Interrupt Registers */
185 {IXGBE_EICR, "EICR"},
188 {IXGBE_SRRCTL(0), "SRRCTL"},
189 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
190 {IXGBE_RDLEN(0), "RDLEN"},
191 {IXGBE_RDH(0), "RDH"},
192 {IXGBE_RDT(0), "RDT"},
193 {IXGBE_RXDCTL(0), "RXDCTL"},
194 {IXGBE_RDBAL(0), "RDBAL"},
195 {IXGBE_RDBAH(0), "RDBAH"},
198 {IXGBE_TDBAL(0), "TDBAL"},
199 {IXGBE_TDBAH(0), "TDBAH"},
200 {IXGBE_TDLEN(0), "TDLEN"},
201 {IXGBE_TDH(0), "TDH"},
202 {IXGBE_TDT(0), "TDT"},
203 {IXGBE_TXDCTL(0), "TXDCTL"},
205 /* List Terminator */
211 * ixgbe_regdump - register printout routine
213 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
219 switch (reginfo->ofs) {
220 case IXGBE_SRRCTL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
224 case IXGBE_DCA_RXCTRL(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
240 case IXGBE_RXDCTL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
272 case IXGBE_TXDCTL(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
277 pr_info("%-15s %08x\n", reginfo->name,
278 IXGBE_READ_REG(hw, reginfo->ofs));
282 for (i = 0; i < 8; i++) {
283 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
284 pr_err("%-15s", rname);
285 for (j = 0; j < 8; j++)
286 pr_cont(" %08x", regs[i*8+j]);
293 * ixgbe_dump - Print registers, tx-rings and rx-rings
295 static void ixgbe_dump(struct ixgbe_adapter *adapter)
297 struct net_device *netdev = adapter->netdev;
298 struct ixgbe_hw *hw = &adapter->hw;
299 struct ixgbe_reg_info *reginfo;
301 struct ixgbe_ring *tx_ring;
302 struct ixgbe_tx_buffer *tx_buffer;
303 union ixgbe_adv_tx_desc *tx_desc;
304 struct my_u0 { u64 a; u64 b; } *u0;
305 struct ixgbe_ring *rx_ring;
306 union ixgbe_adv_rx_desc *rx_desc;
307 struct ixgbe_rx_buffer *rx_buffer_info;
311 if (!netif_msg_hw(adapter))
314 /* Print netdevice Info */
316 dev_info(&adapter->pdev->dev, "Net device Info\n");
317 pr_info("Device Name state "
318 "trans_start last_rx\n");
319 pr_info("%-15s %016lX %016lX %016lX\n",
326 /* Print Registers */
327 dev_info(&adapter->pdev->dev, "Register Dump\n");
328 pr_info(" Register Name Value\n");
329 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
330 reginfo->name; reginfo++) {
331 ixgbe_regdump(hw, reginfo);
334 /* Print TX Ring Summary */
335 if (!netdev || !netif_running(netdev))
338 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
339 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
340 for (n = 0; n < adapter->num_tx_queues; n++) {
341 tx_ring = adapter->tx_ring[n];
342 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
343 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
344 n, tx_ring->next_to_use, tx_ring->next_to_clean,
345 (u64)dma_unmap_addr(tx_buffer, dma),
346 dma_unmap_len(tx_buffer, len),
347 tx_buffer->next_to_watch,
348 (u64)tx_buffer->time_stamp);
352 if (!netif_msg_tx_done(adapter))
353 goto rx_ring_summary;
355 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
357 /* Transmit Descriptor Formats
359 * 82598 Advanced Transmit Descriptor
360 * +--------------------------------------------------------------+
361 * 0 | Buffer Address [63:0] |
362 * +--------------------------------------------------------------+
363 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
364 * +--------------------------------------------------------------+
365 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
367 * 82598 Advanced Transmit Descriptor (Write-Back Format)
368 * +--------------------------------------------------------------+
370 * +--------------------------------------------------------------+
371 * 8 | RSV | STA | NXTSEQ |
372 * +--------------------------------------------------------------+
375 * 82599+ Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
383 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
384 * +--------------------------------------------------------------+
386 * +--------------------------------------------------------------+
387 * 8 | RSV | STA | RSV |
388 * +--------------------------------------------------------------+
392 for (n = 0; n < adapter->num_tx_queues; n++) {
393 tx_ring = adapter->tx_ring[n];
394 pr_info("------------------------------------\n");
395 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
396 pr_info("------------------------------------\n");
397 pr_info("T [desc] [address 63:0 ] "
398 "[PlPOIdStDDt Ln] [bi->dma ] "
399 "leng ntw timestamp bi->skb\n");
401 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
402 tx_desc = IXGBE_TX_DESC(tx_ring, i);
403 tx_buffer = &tx_ring->tx_buffer_info[i];
404 u0 = (struct my_u0 *)tx_desc;
405 pr_info("T [0x%03X] %016llX %016llX %016llX"
406 " %04X %p %016llX %p", i,
409 (u64)dma_unmap_addr(tx_buffer, dma),
410 dma_unmap_len(tx_buffer, len),
411 tx_buffer->next_to_watch,
412 (u64)tx_buffer->time_stamp,
414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
417 else if (i == tx_ring->next_to_use)
419 else if (i == tx_ring->next_to_clean)
424 if (netif_msg_pktdata(adapter) &&
426 print_hex_dump(KERN_INFO, "",
427 DUMP_PREFIX_ADDRESS, 16, 1,
428 tx_buffer->skb->data,
429 dma_unmap_len(tx_buffer, len),
434 /* Print RX Rings Summary */
436 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
437 pr_info("Queue [NTU] [NTC]\n");
438 for (n = 0; n < adapter->num_rx_queues; n++) {
439 rx_ring = adapter->rx_ring[n];
440 pr_info("%5d %5X %5X\n",
441 n, rx_ring->next_to_use, rx_ring->next_to_clean);
445 if (!netif_msg_rx_status(adapter))
448 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
450 /* Receive Descriptor Formats
452 * 82598 Advanced Receive Descriptor (Read) Format
454 * +-----------------------------------------------------+
455 * 0 | Packet Buffer Address [63:1] |A0/NSE|
456 * +----------------------------------------------+------+
457 * 8 | Header Buffer Address [63:1] | DD |
458 * +-----------------------------------------------------+
461 * 82598 Advanced Receive Descriptor (Write-Back) Format
463 * 63 48 47 32 31 30 21 20 16 15 4 3 0
464 * +------------------------------------------------------+
465 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
466 * | Packet | IP | | | | Type | Type |
467 * | Checksum | Ident | | | | | |
468 * +------------------------------------------------------+
469 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
470 * +------------------------------------------------------+
471 * 63 48 47 32 31 20 19 0
473 * 82599+ Advanced Receive Descriptor (Read) Format
475 * +-----------------------------------------------------+
476 * 0 | Packet Buffer Address [63:1] |A0/NSE|
477 * +----------------------------------------------+------+
478 * 8 | Header Buffer Address [63:1] | DD |
479 * +-----------------------------------------------------+
482 * 82599+ Advanced Receive Descriptor (Write-Back) Format
484 * 63 48 47 32 31 30 21 20 17 16 4 3 0
485 * +------------------------------------------------------+
486 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
487 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
488 * |/ Flow Dir Flt ID | | | | | |
489 * +------------------------------------------------------+
490 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
491 * +------------------------------------------------------+
492 * 63 48 47 32 31 20 19 0
495 for (n = 0; n < adapter->num_rx_queues; n++) {
496 rx_ring = adapter->rx_ring[n];
497 pr_info("------------------------------------\n");
498 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
499 pr_info("------------------------------------\n");
500 pr_info("R [desc] [ PktBuf A0] "
501 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
502 "<-- Adv Rx Read format\n");
503 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
504 "[vl er S cks ln] ---------------- [bi->skb] "
505 "<-- Adv Rx Write-Back format\n");
507 for (i = 0; i < rx_ring->count; i++) {
508 rx_buffer_info = &rx_ring->rx_buffer_info[i];
509 rx_desc = IXGBE_RX_DESC(rx_ring, i);
510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512 if (staterr & IXGBE_RXD_STAT_DD) {
513 /* Descriptor Done */
514 pr_info("RWB[0x%03X] %016llX "
515 "%016llX ---------------- %p", i,
518 rx_buffer_info->skb);
520 pr_info("R [0x%03X] %016llX "
521 "%016llX %016llX %p", i,
524 (u64)rx_buffer_info->dma,
525 rx_buffer_info->skb);
527 if (netif_msg_pktdata(adapter) &&
528 rx_buffer_info->dma) {
529 print_hex_dump(KERN_INFO, "",
530 DUMP_PREFIX_ADDRESS, 16, 1,
531 page_address(rx_buffer_info->page) +
532 rx_buffer_info->page_offset,
533 ixgbe_rx_bufsz(rx_ring), true);
537 if (i == rx_ring->next_to_use)
539 else if (i == rx_ring->next_to_clean)
551 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
555 /* Let firmware take over control of h/w */
556 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
558 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
561 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
565 /* Let firmware know the driver has taken over */
566 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
568 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
572 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
573 * @adapter: pointer to adapter struct
574 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
575 * @queue: queue to map the corresponding interrupt to
576 * @msix_vector: the vector to map to the corresponding queue
579 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
580 u8 queue, u8 msix_vector)
583 struct ixgbe_hw *hw = &adapter->hw;
584 switch (hw->mac.type) {
585 case ixgbe_mac_82598EB:
586 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
589 index = (((direction * 64) + queue) >> 2) & 0x1F;
590 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
591 ivar &= ~(0xFF << (8 * (queue & 0x3)));
592 ivar |= (msix_vector << (8 * (queue & 0x3)));
593 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
595 case ixgbe_mac_82599EB:
597 if (direction == -1) {
599 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
600 index = ((queue & 1) * 8);
601 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
602 ivar &= ~(0xFF << index);
603 ivar |= (msix_vector << index);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
607 /* tx or rx causes */
608 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
609 index = ((16 * (queue & 1)) + (8 * direction));
610 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
611 ivar &= ~(0xFF << index);
612 ivar |= (msix_vector << index);
613 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
621 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
626 switch (adapter->hw.mac.type) {
627 case ixgbe_mac_82598EB:
628 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
631 case ixgbe_mac_82599EB:
633 mask = (qmask & 0xFFFFFFFF);
634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
635 mask = (qmask >> 32);
636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
643 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
644 struct ixgbe_tx_buffer *tx_buffer)
646 if (tx_buffer->skb) {
647 dev_kfree_skb_any(tx_buffer->skb);
648 if (dma_unmap_len(tx_buffer, len))
649 dma_unmap_single(ring->dev,
650 dma_unmap_addr(tx_buffer, dma),
651 dma_unmap_len(tx_buffer, len),
653 } else if (dma_unmap_len(tx_buffer, len)) {
654 dma_unmap_page(ring->dev,
655 dma_unmap_addr(tx_buffer, dma),
656 dma_unmap_len(tx_buffer, len),
659 tx_buffer->next_to_watch = NULL;
660 tx_buffer->skb = NULL;
661 dma_unmap_len_set(tx_buffer, len, 0);
662 /* tx_buffer must be completely set up in the transmit path */
665 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
667 struct ixgbe_hw *hw = &adapter->hw;
668 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 if ((hw->fc.current_mode != ixgbe_fc_full) &&
673 (hw->fc.current_mode != ixgbe_fc_rx_pause))
676 switch (hw->mac.type) {
677 case ixgbe_mac_82598EB:
678 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
683 hwstats->lxoffrxc += data;
685 /* refill credits (no tx hang) if we received xoff */
689 for (i = 0; i < adapter->num_tx_queues; i++)
690 clear_bit(__IXGBE_HANG_CHECK_ARMED,
691 &adapter->tx_ring[i]->state);
694 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
696 struct ixgbe_hw *hw = &adapter->hw;
697 struct ixgbe_hw_stats *hwstats = &adapter->stats;
700 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
702 if (adapter->ixgbe_ieee_pfc)
703 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
705 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
706 ixgbe_update_xoff_rx_lfc(adapter);
710 /* update stats for each tc, only valid with PFC enabled */
711 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
712 switch (hw->mac.type) {
713 case ixgbe_mac_82598EB:
714 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
717 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
719 hwstats->pxoffrxc[i] += xoff[i];
722 /* disarm tx queues that have received xoff frames */
723 for (i = 0; i < adapter->num_tx_queues; i++) {
724 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
725 u8 tc = tx_ring->dcb_tc;
728 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
732 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
734 return ring->stats.packets;
737 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
739 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
740 struct ixgbe_hw *hw = &adapter->hw;
742 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
743 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
746 return (head < tail) ?
747 tail - head : (tail + ring->count - head);
752 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
754 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
755 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
756 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
759 clear_check_for_tx_hang(tx_ring);
762 * Check for a hung queue, but be thorough. This verifies
763 * that a transmit has been completed since the previous
764 * check AND there is at least one packet pending. The
765 * ARMED bit is set to indicate a potential hang. The
766 * bit is cleared if a pause frame is received to remove
767 * false hang detection due to PFC or 802.3x frames. By
768 * requiring this to fail twice we avoid races with
769 * pfc clearing the ARMED bit and conditions where we
770 * run the check_tx_hang logic with a transmit completion
771 * pending but without time to complete it yet.
773 if ((tx_done_old == tx_done) && tx_pending) {
774 /* make sure it is true for two checks in a row */
775 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
778 /* update completed stats and continue */
779 tx_ring->tx_stats.tx_done_old = tx_done;
780 /* reset the countdown */
781 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
788 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
789 * @adapter: driver private struct
791 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
794 /* Do the reset outside of interrupt context */
795 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
796 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
797 ixgbe_service_event_schedule(adapter);
802 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
803 * @q_vector: structure containing interrupt and ring information
804 * @tx_ring: tx ring to clean
806 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
807 struct ixgbe_ring *tx_ring)
809 struct ixgbe_adapter *adapter = q_vector->adapter;
810 struct ixgbe_tx_buffer *tx_buffer;
811 union ixgbe_adv_tx_desc *tx_desc;
812 unsigned int total_bytes = 0, total_packets = 0;
813 unsigned int budget = q_vector->tx.work_limit;
814 unsigned int i = tx_ring->next_to_clean;
816 if (test_bit(__IXGBE_DOWN, &adapter->state))
819 tx_buffer = &tx_ring->tx_buffer_info[i];
820 tx_desc = IXGBE_TX_DESC(tx_ring, i);
824 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
826 /* if next_to_watch is not set then there is no work pending */
830 /* prevent any other reads prior to eop_desc */
833 /* if DD is not set pending work has not been completed */
834 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
837 /* clear next_to_watch to prevent false hangs */
838 tx_buffer->next_to_watch = NULL;
840 /* update the statistics for this packet */
841 total_bytes += tx_buffer->bytecount;
842 total_packets += tx_buffer->gso_segs;
844 #ifdef CONFIG_IXGBE_PTP
845 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
846 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
850 dev_kfree_skb_any(tx_buffer->skb);
852 /* unmap skb header data */
853 dma_unmap_single(tx_ring->dev,
854 dma_unmap_addr(tx_buffer, dma),
855 dma_unmap_len(tx_buffer, len),
858 /* clear tx_buffer data */
859 tx_buffer->skb = NULL;
860 dma_unmap_len_set(tx_buffer, len, 0);
862 /* unmap remaining buffers */
863 while (tx_desc != eop_desc) {
869 tx_buffer = tx_ring->tx_buffer_info;
870 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
873 /* unmap any remaining paged data */
874 if (dma_unmap_len(tx_buffer, len)) {
875 dma_unmap_page(tx_ring->dev,
876 dma_unmap_addr(tx_buffer, dma),
877 dma_unmap_len(tx_buffer, len),
879 dma_unmap_len_set(tx_buffer, len, 0);
883 /* move us one more past the eop_desc for start of next pkt */
889 tx_buffer = tx_ring->tx_buffer_info;
890 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
893 /* issue prefetch for next Tx descriptor */
896 /* update budget accounting */
898 } while (likely(budget));
901 tx_ring->next_to_clean = i;
902 u64_stats_update_begin(&tx_ring->syncp);
903 tx_ring->stats.bytes += total_bytes;
904 tx_ring->stats.packets += total_packets;
905 u64_stats_update_end(&tx_ring->syncp);
906 q_vector->tx.total_bytes += total_bytes;
907 q_vector->tx.total_packets += total_packets;
909 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
910 /* schedule immediate reset if we believe we hung */
911 struct ixgbe_hw *hw = &adapter->hw;
912 e_err(drv, "Detected Tx Unit Hang\n"
914 " TDH, TDT <%x>, <%x>\n"
915 " next_to_use <%x>\n"
916 " next_to_clean <%x>\n"
917 "tx_buffer_info[next_to_clean]\n"
918 " time_stamp <%lx>\n"
920 tx_ring->queue_index,
921 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
922 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
923 tx_ring->next_to_use, i,
924 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
926 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
929 "tx hang %d detected on queue %d, resetting adapter\n",
930 adapter->tx_timeout_count + 1, tx_ring->queue_index);
932 /* schedule immediate reset if we believe we hung */
933 ixgbe_tx_timeout_reset(adapter);
935 /* the adapter is about to reset, no point in enabling stuff */
939 netdev_tx_completed_queue(txring_txq(tx_ring),
940 total_packets, total_bytes);
942 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
943 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
944 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
945 /* Make sure that anybody stopping the queue after this
946 * sees the new next_to_clean.
949 if (__netif_subqueue_stopped(tx_ring->netdev,
950 tx_ring->queue_index)
951 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
952 netif_wake_subqueue(tx_ring->netdev,
953 tx_ring->queue_index);
954 ++tx_ring->tx_stats.restart_queue;
961 #ifdef CONFIG_IXGBE_DCA
962 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
963 struct ixgbe_ring *tx_ring,
966 struct ixgbe_hw *hw = &adapter->hw;
967 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
970 switch (hw->mac.type) {
971 case ixgbe_mac_82598EB:
972 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
974 case ixgbe_mac_82599EB:
976 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
977 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
980 /* for unknown hardware do not write register */
985 * We can enable relaxed ordering for reads, but not writes when
986 * DCA is enabled. This is due to a known issue in some chipsets
987 * which will cause the DCA tag to be cleared.
989 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
990 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
991 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
993 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
996 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
997 struct ixgbe_ring *rx_ring,
1000 struct ixgbe_hw *hw = &adapter->hw;
1001 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1002 u8 reg_idx = rx_ring->reg_idx;
1005 switch (hw->mac.type) {
1006 case ixgbe_mac_82599EB:
1007 case ixgbe_mac_X540:
1008 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1015 * We can enable relaxed ordering for reads, but not writes when
1016 * DCA is enabled. This is due to a known issue in some chipsets
1017 * which will cause the DCA tag to be cleared.
1019 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1020 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1021 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1023 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1026 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1028 struct ixgbe_adapter *adapter = q_vector->adapter;
1029 struct ixgbe_ring *ring;
1030 int cpu = get_cpu();
1032 if (q_vector->cpu == cpu)
1035 ixgbe_for_each_ring(ring, q_vector->tx)
1036 ixgbe_update_tx_dca(adapter, ring, cpu);
1038 ixgbe_for_each_ring(ring, q_vector->rx)
1039 ixgbe_update_rx_dca(adapter, ring, cpu);
1041 q_vector->cpu = cpu;
1046 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1050 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1053 /* always use CB2 mode, difference is masked in the CB driver */
1054 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1056 for (i = 0; i < adapter->num_q_vectors; i++) {
1057 adapter->q_vector[i]->cpu = -1;
1058 ixgbe_update_dca(adapter->q_vector[i]);
1062 static int __ixgbe_notify_dca(struct device *dev, void *data)
1064 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1065 unsigned long event = *(unsigned long *)data;
1067 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1071 case DCA_PROVIDER_ADD:
1072 /* if we're already enabled, don't do it again */
1073 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1075 if (dca_add_requester(dev) == 0) {
1076 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1077 ixgbe_setup_dca(adapter);
1080 /* Fall Through since DCA is disabled. */
1081 case DCA_PROVIDER_REMOVE:
1082 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1083 dca_remove_requester(dev);
1084 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1085 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1093 #endif /* CONFIG_IXGBE_DCA */
1094 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1095 union ixgbe_adv_rx_desc *rx_desc,
1096 struct sk_buff *skb)
1098 if (ring->netdev->features & NETIF_F_RXHASH)
1099 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1104 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1105 * @ring: structure containing ring specific data
1106 * @rx_desc: advanced rx descriptor
1108 * Returns : true if it is FCoE pkt
1110 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1111 union ixgbe_adv_rx_desc *rx_desc)
1113 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1115 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1116 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1117 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1118 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1121 #endif /* IXGBE_FCOE */
1123 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1124 * @ring: structure containing ring specific data
1125 * @rx_desc: current Rx descriptor being processed
1126 * @skb: skb currently being received and modified
1128 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1129 union ixgbe_adv_rx_desc *rx_desc,
1130 struct sk_buff *skb)
1132 skb_checksum_none_assert(skb);
1134 /* Rx csum disabled */
1135 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1138 /* if IP and error */
1139 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1140 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1141 ring->rx_stats.csum_err++;
1145 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1148 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1149 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1152 * 82599 errata, UDP frames with a 0 checksum can be marked as
1155 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1156 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1159 ring->rx_stats.csum_err++;
1163 /* It must be a TCP or UDP packet with a valid checksum */
1164 skb->ip_summed = CHECKSUM_UNNECESSARY;
1167 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1169 rx_ring->next_to_use = val;
1171 /* update next to alloc since we have filled the ring */
1172 rx_ring->next_to_alloc = val;
1174 * Force memory writes to complete before letting h/w
1175 * know there are new descriptors to fetch. (Only
1176 * applicable for weak-ordered memory model archs,
1180 writel(val, rx_ring->tail);
1183 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1184 struct ixgbe_rx_buffer *bi)
1186 struct page *page = bi->page;
1187 dma_addr_t dma = bi->dma;
1189 /* since we are recycling buffers we should seldom need to alloc */
1193 /* alloc new page for storage */
1194 if (likely(!page)) {
1195 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1196 bi->skb, ixgbe_rx_pg_order(rx_ring));
1197 if (unlikely(!page)) {
1198 rx_ring->rx_stats.alloc_rx_page_failed++;
1204 /* map page for use */
1205 dma = dma_map_page(rx_ring->dev, page, 0,
1206 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1209 * if mapping failed free memory back to system since
1210 * there isn't much point in holding memory we can't use
1212 if (dma_mapping_error(rx_ring->dev, dma)) {
1213 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1216 rx_ring->rx_stats.alloc_rx_page_failed++;
1221 bi->page_offset = 0;
1227 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1228 * @rx_ring: ring to place buffers on
1229 * @cleaned_count: number of buffers to replace
1231 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1233 union ixgbe_adv_rx_desc *rx_desc;
1234 struct ixgbe_rx_buffer *bi;
1235 u16 i = rx_ring->next_to_use;
1241 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1242 bi = &rx_ring->rx_buffer_info[i];
1243 i -= rx_ring->count;
1246 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1250 * Refresh the desc even if buffer_addrs didn't change
1251 * because each write-back erases this info.
1253 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1259 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1260 bi = rx_ring->rx_buffer_info;
1261 i -= rx_ring->count;
1264 /* clear the hdr_addr for the next_to_use descriptor */
1265 rx_desc->read.hdr_addr = 0;
1268 } while (cleaned_count);
1270 i += rx_ring->count;
1272 if (rx_ring->next_to_use != i)
1273 ixgbe_release_rx_desc(rx_ring, i);
1277 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1278 * @data: pointer to the start of the headers
1279 * @max_len: total length of section to find headers in
1281 * This function is meant to determine the length of headers that will
1282 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1283 * motivation of doing this is to only perform one pull for IPv4 TCP
1284 * packets so that we can do basic things like calculating the gso_size
1285 * based on the average data per packet.
1287 static unsigned int ixgbe_get_headlen(unsigned char *data,
1288 unsigned int max_len)
1291 unsigned char *network;
1294 struct vlan_hdr *vlan;
1297 struct ipv6hdr *ipv6;
1300 u8 nexthdr = 0; /* default to not TCP */
1303 /* this should never happen, but better safe than sorry */
1304 if (max_len < ETH_HLEN)
1307 /* initialize network frame pointer */
1310 /* set first protocol and move network header forward */
1311 protocol = hdr.eth->h_proto;
1312 hdr.network += ETH_HLEN;
1314 /* handle any vlan tag if present */
1315 if (protocol == __constant_htons(ETH_P_8021Q)) {
1316 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1319 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1320 hdr.network += VLAN_HLEN;
1323 /* handle L3 protocols */
1324 if (protocol == __constant_htons(ETH_P_IP)) {
1325 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1328 /* access ihl as a u8 to avoid unaligned access on ia64 */
1329 hlen = (hdr.network[0] & 0x0F) << 2;
1331 /* verify hlen meets minimum size requirements */
1332 if (hlen < sizeof(struct iphdr))
1333 return hdr.network - data;
1335 /* record next protocol */
1336 nexthdr = hdr.ipv4->protocol;
1337 hdr.network += hlen;
1338 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1339 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1342 /* record next protocol */
1343 nexthdr = hdr.ipv6->nexthdr;
1344 hdr.network += sizeof(struct ipv6hdr);
1346 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1347 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1349 hdr.network += FCOE_HEADER_LEN;
1352 return hdr.network - data;
1355 /* finally sort out TCP/UDP */
1356 if (nexthdr == IPPROTO_TCP) {
1357 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1360 /* access doff as a u8 to avoid unaligned access on ia64 */
1361 hlen = (hdr.network[12] & 0xF0) >> 2;
1363 /* verify hlen meets minimum size requirements */
1364 if (hlen < sizeof(struct tcphdr))
1365 return hdr.network - data;
1367 hdr.network += hlen;
1368 } else if (nexthdr == IPPROTO_UDP) {
1369 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1372 hdr.network += sizeof(struct udphdr);
1376 * If everything has gone correctly hdr.network should be the
1377 * data section of the packet and will be the end of the header.
1378 * If not then it probably represents the end of the last recognized
1381 if ((hdr.network - data) < max_len)
1382 return hdr.network - data;
1387 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1388 struct sk_buff *skb)
1390 u16 hdr_len = skb_headlen(skb);
1392 /* set gso_size to avoid messing up TCP MSS */
1393 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1394 IXGBE_CB(skb)->append_cnt);
1397 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1398 struct sk_buff *skb)
1400 /* if append_cnt is 0 then frame is not RSC */
1401 if (!IXGBE_CB(skb)->append_cnt)
1404 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1405 rx_ring->rx_stats.rsc_flush++;
1407 ixgbe_set_rsc_gso_size(rx_ring, skb);
1409 /* gso_size is computed using append_cnt so always clear it last */
1410 IXGBE_CB(skb)->append_cnt = 0;
1414 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1415 * @rx_ring: rx descriptor ring packet is being transacted on
1416 * @rx_desc: pointer to the EOP Rx descriptor
1417 * @skb: pointer to current skb being populated
1419 * This function checks the ring, descriptor, and packet information in
1420 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1421 * other fields within the skb.
1423 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1424 union ixgbe_adv_rx_desc *rx_desc,
1425 struct sk_buff *skb)
1427 struct net_device *dev = rx_ring->netdev;
1429 ixgbe_update_rsc_stats(rx_ring, skb);
1431 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1433 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1435 #ifdef CONFIG_IXGBE_PTP
1436 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
1439 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1440 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1441 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1442 __vlan_hwaccel_put_tag(skb, vid);
1445 skb_record_rx_queue(skb, rx_ring->queue_index);
1447 skb->protocol = eth_type_trans(skb, dev);
1450 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1451 struct sk_buff *skb)
1453 struct ixgbe_adapter *adapter = q_vector->adapter;
1455 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1456 napi_gro_receive(&q_vector->napi, skb);
1462 * ixgbe_is_non_eop - process handling of non-EOP buffers
1463 * @rx_ring: Rx ring being processed
1464 * @rx_desc: Rx descriptor for current buffer
1465 * @skb: Current socket buffer containing buffer in progress
1467 * This function updates next to clean. If the buffer is an EOP buffer
1468 * this function exits returning false, otherwise it will place the
1469 * sk_buff in the next buffer to be chained and return true indicating
1470 * that this is in fact a non-EOP buffer.
1472 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1473 union ixgbe_adv_rx_desc *rx_desc,
1474 struct sk_buff *skb)
1476 u32 ntc = rx_ring->next_to_clean + 1;
1478 /* fetch, update, and store next to clean */
1479 ntc = (ntc < rx_ring->count) ? ntc : 0;
1480 rx_ring->next_to_clean = ntc;
1482 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1484 /* update RSC append count if present */
1485 if (ring_is_rsc_enabled(rx_ring)) {
1486 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1487 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1489 if (unlikely(rsc_enabled)) {
1490 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1492 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1493 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1495 /* update ntc based on RSC value */
1496 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1497 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1498 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1502 /* if we are the last buffer then there is nothing else to do */
1503 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1506 /* place skb in next buffer to be received */
1507 rx_ring->rx_buffer_info[ntc].skb = skb;
1508 rx_ring->rx_stats.non_eop_descs++;
1514 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1515 * @rx_ring: rx descriptor ring packet is being transacted on
1516 * @skb: pointer to current skb being adjusted
1518 * This function is an ixgbe specific version of __pskb_pull_tail. The
1519 * main difference between this version and the original function is that
1520 * this function can make several assumptions about the state of things
1521 * that allow for significant optimizations versus the standard function.
1522 * As a result we can do things like drop a frag and maintain an accurate
1523 * truesize for the skb.
1525 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1526 struct sk_buff *skb)
1528 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1530 unsigned int pull_len;
1533 * it is valid to use page_address instead of kmap since we are
1534 * working with pages allocated out of the lomem pool per
1535 * alloc_page(GFP_ATOMIC)
1537 va = skb_frag_address(frag);
1540 * we need the header to contain the greater of either ETH_HLEN or
1541 * 60 bytes if the skb->len is less than 60 for skb_pad.
1543 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1545 /* align pull length to size of long to optimize memcpy performance */
1546 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1548 /* update all of the pointers */
1549 skb_frag_size_sub(frag, pull_len);
1550 frag->page_offset += pull_len;
1551 skb->data_len -= pull_len;
1552 skb->tail += pull_len;
1556 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1557 * @rx_ring: rx descriptor ring packet is being transacted on
1558 * @skb: pointer to current skb being updated
1560 * This function provides a basic DMA sync up for the first fragment of an
1561 * skb. The reason for doing this is that the first fragment cannot be
1562 * unmapped until we have reached the end of packet descriptor for a buffer
1565 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1566 struct sk_buff *skb)
1568 /* if the page was released unmap it, else just sync our portion */
1569 if (unlikely(IXGBE_CB(skb)->page_released)) {
1570 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1571 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1572 IXGBE_CB(skb)->page_released = false;
1574 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1576 dma_sync_single_range_for_cpu(rx_ring->dev,
1579 ixgbe_rx_bufsz(rx_ring),
1582 IXGBE_CB(skb)->dma = 0;
1586 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1587 * @rx_ring: rx descriptor ring packet is being transacted on
1588 * @rx_desc: pointer to the EOP Rx descriptor
1589 * @skb: pointer to current skb being fixed
1591 * Check for corrupted packet headers caused by senders on the local L2
1592 * embedded NIC switch not setting up their Tx Descriptors right. These
1593 * should be very rare.
1595 * Also address the case where we are pulling data in on pages only
1596 * and as such no data is present in the skb header.
1598 * In addition if skb is not at least 60 bytes we need to pad it so that
1599 * it is large enough to qualify as a valid Ethernet frame.
1601 * Returns true if an error was encountered and skb was freed.
1603 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1604 union ixgbe_adv_rx_desc *rx_desc,
1605 struct sk_buff *skb)
1607 struct net_device *netdev = rx_ring->netdev;
1609 /* verify that the packet does not have any known errors */
1610 if (unlikely(ixgbe_test_staterr(rx_desc,
1611 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1612 !(netdev->features & NETIF_F_RXALL))) {
1613 dev_kfree_skb_any(skb);
1617 /* place header in linear portion of buffer */
1618 if (skb_is_nonlinear(skb))
1619 ixgbe_pull_tail(rx_ring, skb);
1622 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1623 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1627 /* if skb_pad returns an error the skb was freed */
1628 if (unlikely(skb->len < 60)) {
1629 int pad_len = 60 - skb->len;
1631 if (skb_pad(skb, pad_len))
1633 __skb_put(skb, pad_len);
1640 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1641 * @rx_ring: rx descriptor ring to store buffers on
1642 * @old_buff: donor buffer to have page reused
1644 * Synchronizes page for reuse by the adapter
1646 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1647 struct ixgbe_rx_buffer *old_buff)
1649 struct ixgbe_rx_buffer *new_buff;
1650 u16 nta = rx_ring->next_to_alloc;
1652 new_buff = &rx_ring->rx_buffer_info[nta];
1654 /* update, and store next to alloc */
1656 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1658 /* transfer page from old buffer to new buffer */
1659 new_buff->page = old_buff->page;
1660 new_buff->dma = old_buff->dma;
1661 new_buff->page_offset = old_buff->page_offset;
1663 /* sync the buffer for use by the device */
1664 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1665 new_buff->page_offset,
1666 ixgbe_rx_bufsz(rx_ring),
1671 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1672 * @rx_ring: rx descriptor ring to transact packets on
1673 * @rx_buffer: buffer containing page to add
1674 * @rx_desc: descriptor containing length of buffer written by hardware
1675 * @skb: sk_buff to place the data into
1677 * This function will add the data contained in rx_buffer->page to the skb.
1678 * This is done either through a direct copy if the data in the buffer is
1679 * less than the skb header size, otherwise it will just attach the page as
1680 * a frag to the skb.
1682 * The function will then update the page offset if necessary and return
1683 * true if the buffer can be reused by the adapter.
1685 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1686 struct ixgbe_rx_buffer *rx_buffer,
1687 union ixgbe_adv_rx_desc *rx_desc,
1688 struct sk_buff *skb)
1690 struct page *page = rx_buffer->page;
1691 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1692 #if (PAGE_SIZE < 8192)
1693 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1695 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1696 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1697 ixgbe_rx_bufsz(rx_ring);
1700 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1701 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1703 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1705 /* we can reuse buffer as-is, just make sure it is local */
1706 if (likely(page_to_nid(page) == numa_node_id()))
1709 /* this page cannot be reused so discard it */
1714 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1715 rx_buffer->page_offset, size, truesize);
1717 /* avoid re-using remote pages */
1718 if (unlikely(page_to_nid(page) != numa_node_id()))
1721 #if (PAGE_SIZE < 8192)
1722 /* if we are only owner of page we can reuse it */
1723 if (unlikely(page_count(page) != 1))
1726 /* flip page offset to other buffer */
1727 rx_buffer->page_offset ^= truesize;
1730 * since we are the only owner of the page and we need to
1731 * increment it, just set the value to 2 in order to avoid
1732 * an unecessary locked operation
1734 atomic_set(&page->_count, 2);
1736 /* move offset up to the next cache line */
1737 rx_buffer->page_offset += truesize;
1739 if (rx_buffer->page_offset > last_offset)
1742 /* bump ref count on page before it is given to the stack */
1749 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1750 union ixgbe_adv_rx_desc *rx_desc)
1752 struct ixgbe_rx_buffer *rx_buffer;
1753 struct sk_buff *skb;
1756 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1757 page = rx_buffer->page;
1760 skb = rx_buffer->skb;
1763 void *page_addr = page_address(page) +
1764 rx_buffer->page_offset;
1766 /* prefetch first cache line of first page */
1767 prefetch(page_addr);
1768 #if L1_CACHE_BYTES < 128
1769 prefetch(page_addr + L1_CACHE_BYTES);
1772 /* allocate a skb to store the frags */
1773 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1775 if (unlikely(!skb)) {
1776 rx_ring->rx_stats.alloc_rx_buff_failed++;
1781 * we will be copying header into skb->data in
1782 * pskb_may_pull so it is in our interest to prefetch
1783 * it now to avoid a possible cache miss
1785 prefetchw(skb->data);
1788 * Delay unmapping of the first packet. It carries the
1789 * header information, HW may still access the header
1790 * after the writeback. Only unmap it when EOP is
1793 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1796 IXGBE_CB(skb)->dma = rx_buffer->dma;
1798 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1799 ixgbe_dma_sync_frag(rx_ring, skb);
1802 /* we are reusing so sync this buffer for CPU use */
1803 dma_sync_single_range_for_cpu(rx_ring->dev,
1805 rx_buffer->page_offset,
1806 ixgbe_rx_bufsz(rx_ring),
1810 /* pull page into skb */
1811 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1812 /* hand second half of page back to the ring */
1813 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1814 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1815 /* the page has been released from the ring */
1816 IXGBE_CB(skb)->page_released = true;
1818 /* we are not reusing the buffer so unmap it */
1819 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1820 ixgbe_rx_pg_size(rx_ring),
1824 /* clear contents of buffer_info */
1825 rx_buffer->skb = NULL;
1827 rx_buffer->page = NULL;
1833 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1834 * @q_vector: structure containing interrupt and ring information
1835 * @rx_ring: rx descriptor ring to transact packets on
1836 * @budget: Total limit on number of packets to process
1838 * This function provides a "bounce buffer" approach to Rx interrupt
1839 * processing. The advantage to this is that on systems that have
1840 * expensive overhead for IOMMU access this provides a means of avoiding
1841 * it by maintaining the mapping of the page to the syste.
1843 * Returns true if all work is completed without reaching budget
1845 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1846 struct ixgbe_ring *rx_ring,
1849 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1851 struct ixgbe_adapter *adapter = q_vector->adapter;
1853 unsigned int mss = 0;
1854 #endif /* IXGBE_FCOE */
1855 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1858 union ixgbe_adv_rx_desc *rx_desc;
1859 struct sk_buff *skb;
1861 /* return some buffers to hardware, one at a time is too slow */
1862 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1863 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1867 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1869 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1873 * This memory barrier is needed to keep us from reading
1874 * any other fields out of the rx_desc until we know the
1875 * RXD_STAT_DD bit is set
1879 /* retrieve a buffer from the ring */
1880 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1882 /* exit if we failed to retrieve a buffer */
1888 /* place incomplete frames back on ring for completion */
1889 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1892 /* verify the packet layout is correct */
1893 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1896 /* probably a little skewed due to removing CRC */
1897 total_rx_bytes += skb->len;
1899 /* populate checksum, timestamp, VLAN, and protocol */
1900 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1903 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1904 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1905 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1906 /* include DDPed FCoE data */
1907 if (ddp_bytes > 0) {
1909 mss = rx_ring->netdev->mtu -
1910 sizeof(struct fcoe_hdr) -
1911 sizeof(struct fc_frame_header) -
1912 sizeof(struct fcoe_crc_eof);
1916 total_rx_bytes += ddp_bytes;
1917 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1921 dev_kfree_skb_any(skb);
1926 #endif /* IXGBE_FCOE */
1927 ixgbe_rx_skb(q_vector, skb);
1929 /* update budget accounting */
1931 } while (likely(total_rx_packets < budget));
1933 u64_stats_update_begin(&rx_ring->syncp);
1934 rx_ring->stats.packets += total_rx_packets;
1935 rx_ring->stats.bytes += total_rx_bytes;
1936 u64_stats_update_end(&rx_ring->syncp);
1937 q_vector->rx.total_packets += total_rx_packets;
1938 q_vector->rx.total_bytes += total_rx_bytes;
1941 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1943 return (total_rx_packets < budget);
1947 * ixgbe_configure_msix - Configure MSI-X hardware
1948 * @adapter: board private structure
1950 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1953 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1955 struct ixgbe_q_vector *q_vector;
1959 /* Populate MSIX to EITR Select */
1960 if (adapter->num_vfs > 32) {
1961 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1962 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1966 * Populate the IVAR table and set the ITR values to the
1967 * corresponding register.
1969 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1970 struct ixgbe_ring *ring;
1971 q_vector = adapter->q_vector[v_idx];
1973 ixgbe_for_each_ring(ring, q_vector->rx)
1974 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1976 ixgbe_for_each_ring(ring, q_vector->tx)
1977 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1979 ixgbe_write_eitr(q_vector);
1982 switch (adapter->hw.mac.type) {
1983 case ixgbe_mac_82598EB:
1984 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1987 case ixgbe_mac_82599EB:
1988 case ixgbe_mac_X540:
1989 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1994 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1996 /* set up to autoclear timer, and the vectors */
1997 mask = IXGBE_EIMS_ENABLE_MASK;
1998 mask &= ~(IXGBE_EIMS_OTHER |
1999 IXGBE_EIMS_MAILBOX |
2002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2005 enum latency_range {
2009 latency_invalid = 255
2013 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2014 * @q_vector: structure containing interrupt and ring information
2015 * @ring_container: structure containing ring performance data
2017 * Stores a new ITR value based on packets and byte
2018 * counts during the last interrupt. The advantage of per interrupt
2019 * computation is faster updates and more accurate ITR for the current
2020 * traffic pattern. Constants in this function were computed
2021 * based on theoretical maximum wire speed and thresholds were set based
2022 * on testing data as well as attempting to minimize response time
2023 * while increasing bulk throughput.
2024 * this functionality is controlled by the InterruptThrottleRate module
2025 * parameter (see ixgbe_param.c)
2027 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2028 struct ixgbe_ring_container *ring_container)
2030 int bytes = ring_container->total_bytes;
2031 int packets = ring_container->total_packets;
2034 u8 itr_setting = ring_container->itr;
2039 /* simple throttlerate management
2040 * 0-10MB/s lowest (100000 ints/s)
2041 * 10-20MB/s low (20000 ints/s)
2042 * 20-1249MB/s bulk (8000 ints/s)
2044 /* what was last interrupt timeslice? */
2045 timepassed_us = q_vector->itr >> 2;
2046 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2048 switch (itr_setting) {
2049 case lowest_latency:
2050 if (bytes_perint > 10)
2051 itr_setting = low_latency;
2054 if (bytes_perint > 20)
2055 itr_setting = bulk_latency;
2056 else if (bytes_perint <= 10)
2057 itr_setting = lowest_latency;
2060 if (bytes_perint <= 20)
2061 itr_setting = low_latency;
2065 /* clear work counters since we have the values we need */
2066 ring_container->total_bytes = 0;
2067 ring_container->total_packets = 0;
2069 /* write updated itr to ring container */
2070 ring_container->itr = itr_setting;
2074 * ixgbe_write_eitr - write EITR register in hardware specific way
2075 * @q_vector: structure containing interrupt and ring information
2077 * This function is made to be called by ethtool and by the driver
2078 * when it needs to update EITR registers at runtime. Hardware
2079 * specific quirks/differences are taken care of here.
2081 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2083 struct ixgbe_adapter *adapter = q_vector->adapter;
2084 struct ixgbe_hw *hw = &adapter->hw;
2085 int v_idx = q_vector->v_idx;
2086 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2088 switch (adapter->hw.mac.type) {
2089 case ixgbe_mac_82598EB:
2090 /* must write high and low 16 bits to reset counter */
2091 itr_reg |= (itr_reg << 16);
2093 case ixgbe_mac_82599EB:
2094 case ixgbe_mac_X540:
2096 * set the WDIS bit to not clear the timer bits and cause an
2097 * immediate assertion of the interrupt
2099 itr_reg |= IXGBE_EITR_CNT_WDIS;
2104 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2107 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2109 u32 new_itr = q_vector->itr;
2112 ixgbe_update_itr(q_vector, &q_vector->tx);
2113 ixgbe_update_itr(q_vector, &q_vector->rx);
2115 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2117 switch (current_itr) {
2118 /* counts and packets in update_itr are dependent on these numbers */
2119 case lowest_latency:
2120 new_itr = IXGBE_100K_ITR;
2123 new_itr = IXGBE_20K_ITR;
2126 new_itr = IXGBE_8K_ITR;
2132 if (new_itr != q_vector->itr) {
2133 /* do an exponential smoothing */
2134 new_itr = (10 * new_itr * q_vector->itr) /
2135 ((9 * new_itr) + q_vector->itr);
2137 /* save the algorithm value here */
2138 q_vector->itr = new_itr;
2140 ixgbe_write_eitr(q_vector);
2145 * ixgbe_check_overtemp_subtask - check for over temperature
2146 * @adapter: pointer to adapter
2148 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2150 struct ixgbe_hw *hw = &adapter->hw;
2151 u32 eicr = adapter->interrupt_event;
2153 if (test_bit(__IXGBE_DOWN, &adapter->state))
2156 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2157 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2160 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2162 switch (hw->device_id) {
2163 case IXGBE_DEV_ID_82599_T3_LOM:
2165 * Since the warning interrupt is for both ports
2166 * we don't have to check if:
2167 * - This interrupt wasn't for our port.
2168 * - We may have missed the interrupt so always have to
2169 * check if we got a LSC
2171 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2172 !(eicr & IXGBE_EICR_LSC))
2175 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2177 bool link_up = false;
2179 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2185 /* Check if this is not due to overtemp */
2186 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2191 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2196 "Network adapter has been stopped because it has over heated. "
2197 "Restart the computer. If the problem persists, "
2198 "power off the system and replace the adapter\n");
2200 adapter->interrupt_event = 0;
2203 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2205 struct ixgbe_hw *hw = &adapter->hw;
2207 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2208 (eicr & IXGBE_EICR_GPI_SDP1)) {
2209 e_crit(probe, "Fan has stopped, replace the adapter\n");
2210 /* write to clear the interrupt */
2211 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2215 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2217 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2220 switch (adapter->hw.mac.type) {
2221 case ixgbe_mac_82599EB:
2223 * Need to check link state so complete overtemp check
2226 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2227 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2228 adapter->interrupt_event = eicr;
2229 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2230 ixgbe_service_event_schedule(adapter);
2234 case ixgbe_mac_X540:
2235 if (!(eicr & IXGBE_EICR_TS))
2243 "Network adapter has been stopped because it has over heated. "
2244 "Restart the computer. If the problem persists, "
2245 "power off the system and replace the adapter\n");
2248 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2250 struct ixgbe_hw *hw = &adapter->hw;
2252 if (eicr & IXGBE_EICR_GPI_SDP2) {
2253 /* Clear the interrupt */
2254 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2255 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2256 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2257 ixgbe_service_event_schedule(adapter);
2261 if (eicr & IXGBE_EICR_GPI_SDP1) {
2262 /* Clear the interrupt */
2263 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2264 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2265 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2266 ixgbe_service_event_schedule(adapter);
2271 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2273 struct ixgbe_hw *hw = &adapter->hw;
2276 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2277 adapter->link_check_timeout = jiffies;
2278 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2279 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2280 IXGBE_WRITE_FLUSH(hw);
2281 ixgbe_service_event_schedule(adapter);
2285 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2289 struct ixgbe_hw *hw = &adapter->hw;
2291 switch (hw->mac.type) {
2292 case ixgbe_mac_82598EB:
2293 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2294 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2296 case ixgbe_mac_82599EB:
2297 case ixgbe_mac_X540:
2298 mask = (qmask & 0xFFFFFFFF);
2300 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2301 mask = (qmask >> 32);
2303 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2308 /* skip the flush */
2311 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2315 struct ixgbe_hw *hw = &adapter->hw;
2317 switch (hw->mac.type) {
2318 case ixgbe_mac_82598EB:
2319 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2320 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2322 case ixgbe_mac_82599EB:
2323 case ixgbe_mac_X540:
2324 mask = (qmask & 0xFFFFFFFF);
2326 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2327 mask = (qmask >> 32);
2329 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2334 /* skip the flush */
2338 * ixgbe_irq_enable - Enable default interrupt generation settings
2339 * @adapter: board private structure
2341 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2344 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2346 /* don't reenable LSC while waiting for link */
2347 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2348 mask &= ~IXGBE_EIMS_LSC;
2350 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2351 switch (adapter->hw.mac.type) {
2352 case ixgbe_mac_82599EB:
2353 mask |= IXGBE_EIMS_GPI_SDP0;
2355 case ixgbe_mac_X540:
2356 mask |= IXGBE_EIMS_TS;
2361 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2362 mask |= IXGBE_EIMS_GPI_SDP1;
2363 switch (adapter->hw.mac.type) {
2364 case ixgbe_mac_82599EB:
2365 mask |= IXGBE_EIMS_GPI_SDP1;
2366 mask |= IXGBE_EIMS_GPI_SDP2;
2367 case ixgbe_mac_X540:
2368 mask |= IXGBE_EIMS_ECC;
2369 mask |= IXGBE_EIMS_MAILBOX;
2375 #ifdef CONFIG_IXGBE_PTP
2376 if (adapter->hw.mac.type == ixgbe_mac_X540)
2377 mask |= IXGBE_EIMS_TIMESYNC;
2380 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2381 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2382 mask |= IXGBE_EIMS_FLOW_DIR;
2384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2386 ixgbe_irq_enable_queues(adapter, ~0);
2388 IXGBE_WRITE_FLUSH(&adapter->hw);
2391 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2393 struct ixgbe_adapter *adapter = data;
2394 struct ixgbe_hw *hw = &adapter->hw;
2398 * Workaround for Silicon errata. Use clear-by-write instead
2399 * of clear-by-read. Reading with EICS will return the
2400 * interrupt causes without clearing, which later be done
2401 * with the write to EICR.
2403 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2404 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2406 if (eicr & IXGBE_EICR_LSC)
2407 ixgbe_check_lsc(adapter);
2409 if (eicr & IXGBE_EICR_MAILBOX)
2410 ixgbe_msg_task(adapter);
2412 switch (hw->mac.type) {
2413 case ixgbe_mac_82599EB:
2414 case ixgbe_mac_X540:
2415 if (eicr & IXGBE_EICR_ECC)
2416 e_info(link, "Received unrecoverable ECC Err, please "
2418 /* Handle Flow Director Full threshold interrupt */
2419 if (eicr & IXGBE_EICR_FLOW_DIR) {
2420 int reinit_count = 0;
2422 for (i = 0; i < adapter->num_tx_queues; i++) {
2423 struct ixgbe_ring *ring = adapter->tx_ring[i];
2424 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2429 /* no more flow director interrupts until after init */
2430 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2431 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2432 ixgbe_service_event_schedule(adapter);
2435 ixgbe_check_sfp_event(adapter, eicr);
2436 ixgbe_check_overtemp_event(adapter, eicr);
2442 ixgbe_check_fan_failure(adapter, eicr);
2444 #ifdef CONFIG_IXGBE_PTP
2445 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2446 ixgbe_ptp_check_pps_event(adapter, eicr);
2449 /* re-enable the original interrupt state, no lsc, no queues */
2450 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2451 ixgbe_irq_enable(adapter, false, false);
2456 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2458 struct ixgbe_q_vector *q_vector = data;
2460 /* EIAM disabled interrupts (on this vector) for us */
2462 if (q_vector->rx.ring || q_vector->tx.ring)
2463 napi_schedule(&q_vector->napi);
2469 * ixgbe_poll - NAPI Rx polling callback
2470 * @napi: structure for representing this polling device
2471 * @budget: how many packets driver is allowed to clean
2473 * This function is used for legacy and MSI, NAPI mode
2475 int ixgbe_poll(struct napi_struct *napi, int budget)
2477 struct ixgbe_q_vector *q_vector =
2478 container_of(napi, struct ixgbe_q_vector, napi);
2479 struct ixgbe_adapter *adapter = q_vector->adapter;
2480 struct ixgbe_ring *ring;
2481 int per_ring_budget;
2482 bool clean_complete = true;
2484 #ifdef CONFIG_IXGBE_DCA
2485 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2486 ixgbe_update_dca(q_vector);
2489 ixgbe_for_each_ring(ring, q_vector->tx)
2490 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2492 /* attempt to distribute budget to each queue fairly, but don't allow
2493 * the budget to go below 1 because we'll exit polling */
2494 if (q_vector->rx.count > 1)
2495 per_ring_budget = max(budget/q_vector->rx.count, 1);
2497 per_ring_budget = budget;
2499 ixgbe_for_each_ring(ring, q_vector->rx)
2500 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2503 /* If all work not completed, return budget and keep polling */
2504 if (!clean_complete)
2507 /* all work done, exit the polling mode */
2508 napi_complete(napi);
2509 if (adapter->rx_itr_setting & 1)
2510 ixgbe_set_itr(q_vector);
2511 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2512 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2518 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2519 * @adapter: board private structure
2521 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2522 * interrupts from the kernel.
2524 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2526 struct net_device *netdev = adapter->netdev;
2530 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2531 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2532 struct msix_entry *entry = &adapter->msix_entries[vector];
2534 if (q_vector->tx.ring && q_vector->rx.ring) {
2535 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2536 "%s-%s-%d", netdev->name, "TxRx", ri++);
2538 } else if (q_vector->rx.ring) {
2539 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2540 "%s-%s-%d", netdev->name, "rx", ri++);
2541 } else if (q_vector->tx.ring) {
2542 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2543 "%s-%s-%d", netdev->name, "tx", ti++);
2545 /* skip this unused q_vector */
2548 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2549 q_vector->name, q_vector);
2551 e_err(probe, "request_irq failed for MSIX interrupt "
2552 "Error: %d\n", err);
2553 goto free_queue_irqs;
2555 /* If Flow Director is enabled, set interrupt affinity */
2556 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2557 /* assign the mask for this irq */
2558 irq_set_affinity_hint(entry->vector,
2559 &q_vector->affinity_mask);
2563 err = request_irq(adapter->msix_entries[vector].vector,
2564 ixgbe_msix_other, 0, netdev->name, adapter);
2566 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2567 goto free_queue_irqs;
2575 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2577 free_irq(adapter->msix_entries[vector].vector,
2578 adapter->q_vector[vector]);
2580 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2581 pci_disable_msix(adapter->pdev);
2582 kfree(adapter->msix_entries);
2583 adapter->msix_entries = NULL;
2588 * ixgbe_intr - legacy mode Interrupt Handler
2589 * @irq: interrupt number
2590 * @data: pointer to a network interface device structure
2592 static irqreturn_t ixgbe_intr(int irq, void *data)
2594 struct ixgbe_adapter *adapter = data;
2595 struct ixgbe_hw *hw = &adapter->hw;
2596 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2600 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2601 * before the read of EICR.
2603 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2605 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2606 * therefore no explicit interrupt disable is necessary */
2607 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2610 * shared interrupt alert!
2611 * make sure interrupts are enabled because the read will
2612 * have disabled interrupts due to EIAM
2613 * finish the workaround of silicon errata on 82598. Unmask
2614 * the interrupt that we masked before the EICR read.
2616 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2617 ixgbe_irq_enable(adapter, true, true);
2618 return IRQ_NONE; /* Not our interrupt */
2621 if (eicr & IXGBE_EICR_LSC)
2622 ixgbe_check_lsc(adapter);
2624 switch (hw->mac.type) {
2625 case ixgbe_mac_82599EB:
2626 ixgbe_check_sfp_event(adapter, eicr);
2628 case ixgbe_mac_X540:
2629 if (eicr & IXGBE_EICR_ECC)
2630 e_info(link, "Received unrecoverable ECC err, please "
2632 ixgbe_check_overtemp_event(adapter, eicr);
2638 ixgbe_check_fan_failure(adapter, eicr);
2639 #ifdef CONFIG_IXGBE_PTP
2640 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2641 ixgbe_ptp_check_pps_event(adapter, eicr);
2644 /* would disable interrupts here but EIAM disabled it */
2645 napi_schedule(&q_vector->napi);
2648 * re-enable link(maybe) and non-queue interrupts, no flush.
2649 * ixgbe_poll will re-enable the queue interrupts
2651 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2652 ixgbe_irq_enable(adapter, false, false);
2658 * ixgbe_request_irq - initialize interrupts
2659 * @adapter: board private structure
2661 * Attempts to configure interrupts using the best available
2662 * capabilities of the hardware and kernel.
2664 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2666 struct net_device *netdev = adapter->netdev;
2669 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2670 err = ixgbe_request_msix_irqs(adapter);
2671 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2672 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2673 netdev->name, adapter);
2675 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2676 netdev->name, adapter);
2679 e_err(probe, "request_irq failed, Error %d\n", err);
2684 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2688 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2689 free_irq(adapter->pdev->irq, adapter);
2693 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2694 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2695 struct msix_entry *entry = &adapter->msix_entries[vector];
2697 /* free only the irqs that were actually requested */
2698 if (!q_vector->rx.ring && !q_vector->tx.ring)
2701 /* clear the affinity_mask in the IRQ descriptor */
2702 irq_set_affinity_hint(entry->vector, NULL);
2704 free_irq(entry->vector, q_vector);
2707 free_irq(adapter->msix_entries[vector++].vector, adapter);
2711 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2712 * @adapter: board private structure
2714 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2716 switch (adapter->hw.mac.type) {
2717 case ixgbe_mac_82598EB:
2718 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2720 case ixgbe_mac_82599EB:
2721 case ixgbe_mac_X540:
2722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2723 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2729 IXGBE_WRITE_FLUSH(&adapter->hw);
2730 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2733 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2734 synchronize_irq(adapter->msix_entries[vector].vector);
2736 synchronize_irq(adapter->msix_entries[vector++].vector);
2738 synchronize_irq(adapter->pdev->irq);
2743 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2746 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2748 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2750 ixgbe_write_eitr(q_vector);
2752 ixgbe_set_ivar(adapter, 0, 0, 0);
2753 ixgbe_set_ivar(adapter, 1, 0, 0);
2755 e_info(hw, "Legacy interrupt IVAR setup done\n");
2759 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2760 * @adapter: board private structure
2761 * @ring: structure containing ring specific data
2763 * Configure the Tx descriptor ring after a reset.
2765 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2766 struct ixgbe_ring *ring)
2768 struct ixgbe_hw *hw = &adapter->hw;
2769 u64 tdba = ring->dma;
2771 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2772 u8 reg_idx = ring->reg_idx;
2774 /* disable queue to avoid issues while updating state */
2775 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2776 IXGBE_WRITE_FLUSH(hw);
2778 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2779 (tdba & DMA_BIT_MASK(32)));
2780 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2781 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2782 ring->count * sizeof(union ixgbe_adv_tx_desc));
2783 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2784 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2785 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2788 * set WTHRESH to encourage burst writeback, it should not be set
2789 * higher than 1 when ITR is 0 as it could cause false TX hangs
2791 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2792 * to or less than the number of on chip descriptors, which is
2795 if (!ring->q_vector || (ring->q_vector->itr < 8))
2796 txdctl |= (1 << 16); /* WTHRESH = 1 */
2798 txdctl |= (8 << 16); /* WTHRESH = 8 */
2801 * Setting PTHRESH to 32 both improves performance
2802 * and avoids a TX hang with DFP enabled
2804 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2805 32; /* PTHRESH = 32 */
2807 /* reinitialize flowdirector state */
2808 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2809 ring->atr_sample_rate = adapter->atr_sample_rate;
2810 ring->atr_count = 0;
2811 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2813 ring->atr_sample_rate = 0;
2816 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2819 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2821 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2822 if (hw->mac.type == ixgbe_mac_82598EB &&
2823 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2826 /* poll to verify queue is enabled */
2828 usleep_range(1000, 2000);
2829 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2830 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2832 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2835 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2837 struct ixgbe_hw *hw = &adapter->hw;
2839 u8 tcs = netdev_get_num_tc(adapter->netdev);
2841 if (hw->mac.type == ixgbe_mac_82598EB)
2844 /* disable the arbiter while setting MTQC */
2845 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2846 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2847 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2849 /* set transmit pool layout */
2850 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2851 mtqc = IXGBE_MTQC_VT_ENA;
2853 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2855 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2856 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2857 mtqc |= IXGBE_MTQC_32VF;
2859 mtqc |= IXGBE_MTQC_64VF;
2862 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2864 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2866 mtqc = IXGBE_MTQC_64Q_1PB;
2869 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2871 /* Enable Security TX Buffer IFG for multiple pb */
2873 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2874 sectx |= IXGBE_SECTX_DCB;
2875 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2878 /* re-enable the arbiter */
2879 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2880 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2884 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2885 * @adapter: board private structure
2887 * Configure the Tx unit of the MAC after a reset.
2889 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2891 struct ixgbe_hw *hw = &adapter->hw;
2895 ixgbe_setup_mtqc(adapter);
2897 if (hw->mac.type != ixgbe_mac_82598EB) {
2898 /* DMATXCTL.EN must be before Tx queues are enabled */
2899 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2900 dmatxctl |= IXGBE_DMATXCTL_TE;
2901 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2904 /* Setup the HW Tx Head and Tail descriptor pointers */
2905 for (i = 0; i < adapter->num_tx_queues; i++)
2906 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2909 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2910 struct ixgbe_ring *ring)
2912 struct ixgbe_hw *hw = &adapter->hw;
2913 u8 reg_idx = ring->reg_idx;
2914 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2916 srrctl |= IXGBE_SRRCTL_DROP_EN;
2918 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2921 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2922 struct ixgbe_ring *ring)
2924 struct ixgbe_hw *hw = &adapter->hw;
2925 u8 reg_idx = ring->reg_idx;
2926 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2928 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2930 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2933 #ifdef CONFIG_IXGBE_DCB
2934 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2936 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2940 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2942 if (adapter->ixgbe_ieee_pfc)
2943 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2946 * We should set the drop enable bit if:
2949 * Number of Rx queues > 1 and flow control is disabled
2951 * This allows us to avoid head of line blocking for security
2952 * and performance reasons.
2954 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2955 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2956 for (i = 0; i < adapter->num_rx_queues; i++)
2957 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2959 for (i = 0; i < adapter->num_rx_queues; i++)
2960 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2964 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2966 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2967 struct ixgbe_ring *rx_ring)
2969 struct ixgbe_hw *hw = &adapter->hw;
2971 u8 reg_idx = rx_ring->reg_idx;
2973 if (hw->mac.type == ixgbe_mac_82598EB) {
2974 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
2977 * if VMDq is not active we must program one srrctl register
2978 * per RSS queue since we have enabled RDRXCTL.MVMEN
2983 /* configure header buffer length, needed for RSC */
2984 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
2986 /* configure the packet buffer length */
2987 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2989 /* configure descriptor type */
2990 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2992 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2995 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2997 struct ixgbe_hw *hw = &adapter->hw;
2998 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2999 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3000 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3001 u32 mrqc = 0, reta = 0;
3004 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3007 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3008 * make full use of any rings they may have. We will use the
3009 * PSRTYPE register to control how many rings we use within the PF.
3011 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3014 /* Fill out hash function seeds */
3015 for (i = 0; i < 10; i++)
3016 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3018 /* Fill out redirection table */
3019 for (i = 0, j = 0; i < 128; i++, j++) {
3022 /* reta = 4-byte sliding window of
3023 * 0x00..(indices-1)(indices-1)00..etc. */
3024 reta = (reta << 8) | (j * 0x11);
3026 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3029 /* Disable indicating checksum in descriptor, enables RSS hash */
3030 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3031 rxcsum |= IXGBE_RXCSUM_PCSD;
3032 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3034 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3035 if (adapter->ring_feature[RING_F_RSS].mask)
3036 mrqc = IXGBE_MRQC_RSSEN;
3038 u8 tcs = netdev_get_num_tc(adapter->netdev);
3040 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3042 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3044 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3045 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3046 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3048 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3051 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3053 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3055 mrqc = IXGBE_MRQC_RSSEN;
3059 /* Perform hash on these packet types */
3060 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3061 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3062 IXGBE_MRQC_RSS_FIELD_IPV6 |
3063 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3065 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3066 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3067 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3068 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3070 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3074 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3075 * @adapter: address of board private structure
3076 * @index: index of ring to set
3078 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3079 struct ixgbe_ring *ring)
3081 struct ixgbe_hw *hw = &adapter->hw;
3083 u8 reg_idx = ring->reg_idx;
3085 if (!ring_is_rsc_enabled(ring))
3088 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3089 rscctrl |= IXGBE_RSCCTL_RSCEN;
3091 * we must limit the number of descriptors so that the
3092 * total size of max desc * buf_len is not greater
3095 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3096 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3099 #define IXGBE_MAX_RX_DESC_POLL 10
3100 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3101 struct ixgbe_ring *ring)
3103 struct ixgbe_hw *hw = &adapter->hw;
3104 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3106 u8 reg_idx = ring->reg_idx;
3108 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3109 if (hw->mac.type == ixgbe_mac_82598EB &&
3110 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3114 usleep_range(1000, 2000);
3115 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3116 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3119 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3120 "the polling period\n", reg_idx);
3124 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3125 struct ixgbe_ring *ring)
3127 struct ixgbe_hw *hw = &adapter->hw;
3128 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3130 u8 reg_idx = ring->reg_idx;
3132 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3133 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3135 /* write value back with RXDCTL.ENABLE bit cleared */
3136 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3138 if (hw->mac.type == ixgbe_mac_82598EB &&
3139 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3142 /* the hardware may take up to 100us to really disable the rx queue */
3145 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3146 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3149 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3150 "the polling period\n", reg_idx);
3154 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3155 struct ixgbe_ring *ring)
3157 struct ixgbe_hw *hw = &adapter->hw;
3158 u64 rdba = ring->dma;
3160 u8 reg_idx = ring->reg_idx;
3162 /* disable queue to avoid issues while updating state */
3163 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3164 ixgbe_disable_rx_queue(adapter, ring);
3166 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3167 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3168 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3169 ring->count * sizeof(union ixgbe_adv_rx_desc));
3170 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3171 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3172 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3174 ixgbe_configure_srrctl(adapter, ring);
3175 ixgbe_configure_rscctl(adapter, ring);
3177 /* If operating in IOV mode set RLPML for X540 */
3178 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3179 hw->mac.type == ixgbe_mac_X540) {
3180 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3181 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3182 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3185 if (hw->mac.type == ixgbe_mac_82598EB) {
3187 * enable cache line friendly hardware writes:
3188 * PTHRESH=32 descriptors (half the internal cache),
3189 * this also removes ugly rx_no_buffer_count increment
3190 * HTHRESH=4 descriptors (to minimize latency on fetch)
3191 * WTHRESH=8 burst writeback up to two cache lines
3193 rxdctl &= ~0x3FFFFF;
3197 /* enable receive descriptor ring */
3198 rxdctl |= IXGBE_RXDCTL_ENABLE;
3199 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3201 ixgbe_rx_desc_queue_enable(adapter, ring);
3202 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3205 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3207 struct ixgbe_hw *hw = &adapter->hw;
3208 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3211 /* PSRTYPE must be initialized in non 82598 adapters */
3212 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3213 IXGBE_PSRTYPE_UDPHDR |
3214 IXGBE_PSRTYPE_IPV4HDR |
3215 IXGBE_PSRTYPE_L2HDR |
3216 IXGBE_PSRTYPE_IPV6HDR;
3218 if (hw->mac.type == ixgbe_mac_82598EB)
3226 for (p = 0; p < adapter->num_rx_pools; p++)
3227 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3231 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3233 struct ixgbe_hw *hw = &adapter->hw;
3234 u32 reg_offset, vf_shift;
3235 u32 gcr_ext, vmdctl;
3238 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3241 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3242 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3243 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3244 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3245 vmdctl |= IXGBE_VT_CTL_REPLEN;
3246 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3248 vf_shift = VMDQ_P(0) % 32;
3249 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3251 /* Enable only the PF's pool for Tx/Rx */
3252 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3253 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3254 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3255 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3257 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3258 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3261 * Set up VF register offsets for selected VT Mode,
3262 * i.e. 32 or 64 VFs for SR-IOV
3264 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3265 case IXGBE_82599_VMDQ_8Q_MASK:
3266 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3268 case IXGBE_82599_VMDQ_4Q_MASK:
3269 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3272 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3276 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3279 /* Enable MAC Anti-Spoofing */
3280 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3282 /* For VFs that have spoof checking turned off */
3283 for (i = 0; i < adapter->num_vfs; i++) {
3284 if (!adapter->vfinfo[i].spoofchk_enabled)
3285 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3289 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3291 struct ixgbe_hw *hw = &adapter->hw;
3292 struct net_device *netdev = adapter->netdev;
3293 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3294 struct ixgbe_ring *rx_ring;
3299 /* adjust max frame to be able to do baby jumbo for FCoE */
3300 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3301 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3302 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3304 #endif /* IXGBE_FCOE */
3306 /* adjust max frame to be at least the size of a standard frame */
3307 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3308 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3310 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3311 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3312 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3313 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3315 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3318 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3319 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3320 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3321 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3324 * Setup the HW Rx Head and Tail Descriptor Pointers and
3325 * the Base and Length of the Rx Descriptor Ring
3327 for (i = 0; i < adapter->num_rx_queues; i++) {
3328 rx_ring = adapter->rx_ring[i];
3329 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3330 set_ring_rsc_enabled(rx_ring);
3332 clear_ring_rsc_enabled(rx_ring);
3336 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3338 struct ixgbe_hw *hw = &adapter->hw;
3339 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3341 switch (hw->mac.type) {
3342 case ixgbe_mac_82598EB:
3344 * For VMDq support of different descriptor types or
3345 * buffer sizes through the use of multiple SRRCTL
3346 * registers, RDRXCTL.MVMEN must be set to 1
3348 * also, the manual doesn't mention it clearly but DCA hints
3349 * will only use queue 0's tags unless this bit is set. Side
3350 * effects of setting this bit are only that SRRCTL must be
3351 * fully programmed [0..15]
3353 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3355 case ixgbe_mac_82599EB:
3356 case ixgbe_mac_X540:
3357 /* Disable RSC for ACK packets */
3358 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3359 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3360 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3361 /* hardware requires some bits to be set by default */
3362 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3363 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3366 /* We should do nothing since we don't know this hardware */
3370 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3374 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3375 * @adapter: board private structure
3377 * Configure the Rx unit of the MAC after a reset.
3379 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3381 struct ixgbe_hw *hw = &adapter->hw;
3385 /* disable receives while setting up the descriptors */
3386 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3387 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3389 ixgbe_setup_psrtype(adapter);
3390 ixgbe_setup_rdrxctl(adapter);
3392 /* Program registers for the distribution of queues */
3393 ixgbe_setup_mrqc(adapter);
3395 /* set_rx_buffer_len must be called before ring initialization */
3396 ixgbe_set_rx_buffer_len(adapter);
3399 * Setup the HW Rx Head and Tail Descriptor Pointers and
3400 * the Base and Length of the Rx Descriptor Ring
3402 for (i = 0; i < adapter->num_rx_queues; i++)
3403 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3405 /* disable drop enable for 82598 parts */
3406 if (hw->mac.type == ixgbe_mac_82598EB)
3407 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3409 /* enable all receives */
3410 rxctrl |= IXGBE_RXCTRL_RXEN;
3411 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3414 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3416 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3417 struct ixgbe_hw *hw = &adapter->hw;
3419 /* add VID to filter table */
3420 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3421 set_bit(vid, adapter->active_vlans);
3426 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3428 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3429 struct ixgbe_hw *hw = &adapter->hw;
3431 /* remove VID from filter table */
3432 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3433 clear_bit(vid, adapter->active_vlans);
3439 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3440 * @adapter: driver data
3442 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3444 struct ixgbe_hw *hw = &adapter->hw;
3447 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3448 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3449 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3453 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3454 * @adapter: driver data
3456 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3458 struct ixgbe_hw *hw = &adapter->hw;
3461 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3462 vlnctrl |= IXGBE_VLNCTRL_VFE;
3463 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3464 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3468 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3469 * @adapter: driver data
3471 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3473 struct ixgbe_hw *hw = &adapter->hw;
3477 switch (hw->mac.type) {
3478 case ixgbe_mac_82598EB:
3479 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3480 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3481 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3483 case ixgbe_mac_82599EB:
3484 case ixgbe_mac_X540:
3485 for (i = 0; i < adapter->num_rx_queues; i++) {
3486 j = adapter->rx_ring[i]->reg_idx;
3487 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3488 vlnctrl &= ~IXGBE_RXDCTL_VME;
3489 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3498 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3499 * @adapter: driver data
3501 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3503 struct ixgbe_hw *hw = &adapter->hw;
3507 switch (hw->mac.type) {
3508 case ixgbe_mac_82598EB:
3509 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3510 vlnctrl |= IXGBE_VLNCTRL_VME;
3511 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3513 case ixgbe_mac_82599EB:
3514 case ixgbe_mac_X540:
3515 for (i = 0; i < adapter->num_rx_queues; i++) {
3516 j = adapter->rx_ring[i]->reg_idx;
3517 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3518 vlnctrl |= IXGBE_RXDCTL_VME;
3519 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3527 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3531 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3533 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3534 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3538 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3539 * @netdev: network interface device structure
3541 * Writes unicast address list to the RAR table.
3542 * Returns: -ENOMEM on failure/insufficient address space
3543 * 0 on no addresses written
3544 * X on writing X addresses to the RAR table
3546 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3548 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3549 struct ixgbe_hw *hw = &adapter->hw;
3550 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3553 /* In SR-IOV mode significantly less RAR entries are available */
3554 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3555 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3557 /* return ENOMEM indicating insufficient memory for addresses */
3558 if (netdev_uc_count(netdev) > rar_entries)
3561 if (!netdev_uc_empty(netdev)) {
3562 struct netdev_hw_addr *ha;
3563 /* return error if we do not support writing to RAR table */
3564 if (!hw->mac.ops.set_rar)
3567 netdev_for_each_uc_addr(ha, netdev) {
3570 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3571 VMDQ_P(0), IXGBE_RAH_AV);
3575 /* write the addresses in reverse order to avoid write combining */
3576 for (; rar_entries > 0 ; rar_entries--)
3577 hw->mac.ops.clear_rar(hw, rar_entries);
3583 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3584 * @netdev: network interface device structure
3586 * The set_rx_method entry point is called whenever the unicast/multicast
3587 * address list or the network interface flags are updated. This routine is
3588 * responsible for configuring the hardware for proper unicast, multicast and
3591 void ixgbe_set_rx_mode(struct net_device *netdev)
3593 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3594 struct ixgbe_hw *hw = &adapter->hw;
3595 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3598 /* Check for Promiscuous and All Multicast modes */
3600 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3602 /* set all bits that we expect to always be set */
3603 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3604 fctrl |= IXGBE_FCTRL_BAM;
3605 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3606 fctrl |= IXGBE_FCTRL_PMCF;
3608 /* clear the bits we are changing the status of */
3609 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3611 if (netdev->flags & IFF_PROMISC) {
3612 hw->addr_ctrl.user_set_promisc = true;
3613 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3614 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3615 /* don't hardware filter vlans in promisc mode */
3616 ixgbe_vlan_filter_disable(adapter);
3618 if (netdev->flags & IFF_ALLMULTI) {
3619 fctrl |= IXGBE_FCTRL_MPE;
3620 vmolr |= IXGBE_VMOLR_MPE;
3623 * Write addresses to the MTA, if the attempt fails
3624 * then we should just turn on promiscuous mode so
3625 * that we can at least receive multicast traffic
3627 hw->mac.ops.update_mc_addr_list(hw, netdev);
3628 vmolr |= IXGBE_VMOLR_ROMPE;
3630 ixgbe_vlan_filter_enable(adapter);
3631 hw->addr_ctrl.user_set_promisc = false;
3635 * Write addresses to available RAR registers, if there is not
3636 * sufficient space to store all the addresses then enable
3637 * unicast promiscuous mode
3639 count = ixgbe_write_uc_addr_list(netdev);
3641 fctrl |= IXGBE_FCTRL_UPE;
3642 vmolr |= IXGBE_VMOLR_ROPE;
3645 if (adapter->num_vfs)
3646 ixgbe_restore_vf_multicasts(adapter);
3648 if (hw->mac.type != ixgbe_mac_82598EB) {
3649 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3650 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3652 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3655 /* This is useful for sniffing bad packets. */
3656 if (adapter->netdev->features & NETIF_F_RXALL) {
3657 /* UPE and MPE will be handled by normal PROMISC logic
3658 * in e1000e_set_rx_mode */
3659 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3660 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3661 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3663 fctrl &= ~(IXGBE_FCTRL_DPF);
3664 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3667 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3669 if (netdev->features & NETIF_F_HW_VLAN_RX)
3670 ixgbe_vlan_strip_enable(adapter);
3672 ixgbe_vlan_strip_disable(adapter);
3675 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3679 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3680 napi_enable(&adapter->q_vector[q_idx]->napi);
3683 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3687 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3688 napi_disable(&adapter->q_vector[q_idx]->napi);
3691 #ifdef CONFIG_IXGBE_DCB
3693 * ixgbe_configure_dcb - Configure DCB hardware
3694 * @adapter: ixgbe adapter struct
3696 * This is called by the driver on open to configure the DCB hardware.
3697 * This is also called by the gennetlink interface when reconfiguring
3700 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3702 struct ixgbe_hw *hw = &adapter->hw;
3703 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3705 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3706 if (hw->mac.type == ixgbe_mac_82598EB)
3707 netif_set_gso_max_size(adapter->netdev, 65536);
3711 if (hw->mac.type == ixgbe_mac_82598EB)
3712 netif_set_gso_max_size(adapter->netdev, 32768);
3715 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3716 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3719 /* reconfigure the hardware */
3720 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3721 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3723 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3725 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3726 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3727 ixgbe_dcb_hw_ets(&adapter->hw,
3728 adapter->ixgbe_ieee_ets,
3730 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3731 adapter->ixgbe_ieee_pfc->pfc_en,
3732 adapter->ixgbe_ieee_ets->prio_tc);
3735 /* Enable RSS Hash per TC */
3736 if (hw->mac.type != ixgbe_mac_82598EB) {
3738 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3745 /* write msb to all 8 TCs in one write */
3746 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3751 /* Additional bittime to account for IXGBE framing */
3752 #define IXGBE_ETH_FRAMING 20
3755 * ixgbe_hpbthresh - calculate high water mark for flow control
3757 * @adapter: board private structure to calculate for
3758 * @pb: packet buffer to calculate
3760 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3762 struct ixgbe_hw *hw = &adapter->hw;
3763 struct net_device *dev = adapter->netdev;
3764 int link, tc, kb, marker;
3767 /* Calculate max LAN frame size */
3768 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3771 /* FCoE traffic class uses FCOE jumbo frames */
3772 if ((dev->features & NETIF_F_FCOE_MTU) &&
3773 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3774 (pb == ixgbe_fcoe_get_tc(adapter)))
3775 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3778 /* Calculate delay value for device */
3779 switch (hw->mac.type) {
3780 case ixgbe_mac_X540:
3781 dv_id = IXGBE_DV_X540(link, tc);
3784 dv_id = IXGBE_DV(link, tc);
3788 /* Loopback switch introduces additional latency */
3789 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3790 dv_id += IXGBE_B2BT(tc);
3792 /* Delay value is calculated in bit times convert to KB */
3793 kb = IXGBE_BT2KB(dv_id);
3794 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3796 marker = rx_pba - kb;
3798 /* It is possible that the packet buffer is not large enough
3799 * to provide required headroom. In this case throw an error
3800 * to user and a do the best we can.
3803 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3804 "headroom to support flow control."
3805 "Decrease MTU or number of traffic classes\n", pb);
3813 * ixgbe_lpbthresh - calculate low water mark for for flow control
3815 * @adapter: board private structure to calculate for
3816 * @pb: packet buffer to calculate
3818 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3820 struct ixgbe_hw *hw = &adapter->hw;
3821 struct net_device *dev = adapter->netdev;
3825 /* Calculate max LAN frame size */
3826 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3828 /* Calculate delay value for device */
3829 switch (hw->mac.type) {
3830 case ixgbe_mac_X540:
3831 dv_id = IXGBE_LOW_DV_X540(tc);
3834 dv_id = IXGBE_LOW_DV(tc);
3838 /* Delay value is calculated in bit times convert to KB */
3839 return IXGBE_BT2KB(dv_id);
3843 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3845 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3847 struct ixgbe_hw *hw = &adapter->hw;
3848 int num_tc = netdev_get_num_tc(adapter->netdev);
3854 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3856 for (i = 0; i < num_tc; i++) {
3857 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3859 /* Low water marks must not be larger than high water marks */
3860 if (hw->fc.low_water > hw->fc.high_water[i])
3861 hw->fc.low_water = 0;
3865 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3867 struct ixgbe_hw *hw = &adapter->hw;
3869 u8 tc = netdev_get_num_tc(adapter->netdev);
3871 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3872 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3873 hdrm = 32 << adapter->fdir_pballoc;
3877 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3878 ixgbe_pbthresh_setup(adapter);
3881 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3883 struct ixgbe_hw *hw = &adapter->hw;
3884 struct hlist_node *node, *node2;
3885 struct ixgbe_fdir_filter *filter;
3887 spin_lock(&adapter->fdir_perfect_lock);
3889 if (!hlist_empty(&adapter->fdir_filter_list))
3890 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3892 hlist_for_each_entry_safe(filter, node, node2,
3893 &adapter->fdir_filter_list, fdir_node) {
3894 ixgbe_fdir_write_perfect_filter_82599(hw,
3897 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3898 IXGBE_FDIR_DROP_QUEUE :
3899 adapter->rx_ring[filter->action]->reg_idx);
3902 spin_unlock(&adapter->fdir_perfect_lock);
3905 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3907 struct ixgbe_hw *hw = &adapter->hw;
3909 ixgbe_configure_pb(adapter);
3910 #ifdef CONFIG_IXGBE_DCB
3911 ixgbe_configure_dcb(adapter);
3914 * We must restore virtualization before VLANs or else
3915 * the VLVF registers will not be populated
3917 ixgbe_configure_virtualization(adapter);
3919 ixgbe_set_rx_mode(adapter->netdev);
3920 ixgbe_restore_vlan(adapter);
3922 switch (hw->mac.type) {
3923 case ixgbe_mac_82599EB:
3924 case ixgbe_mac_X540:
3925 hw->mac.ops.disable_rx_buff(hw);
3931 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3932 ixgbe_init_fdir_signature_82599(&adapter->hw,
3933 adapter->fdir_pballoc);
3934 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3935 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3936 adapter->fdir_pballoc);
3937 ixgbe_fdir_filter_restore(adapter);
3940 switch (hw->mac.type) {
3941 case ixgbe_mac_82599EB:
3942 case ixgbe_mac_X540:
3943 hw->mac.ops.enable_rx_buff(hw);
3950 /* configure FCoE L2 filters, redirection table, and Rx control */
3951 ixgbe_configure_fcoe(adapter);
3953 #endif /* IXGBE_FCOE */
3954 ixgbe_configure_tx(adapter);
3955 ixgbe_configure_rx(adapter);
3958 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3960 switch (hw->phy.type) {
3961 case ixgbe_phy_sfp_avago:
3962 case ixgbe_phy_sfp_ftl:
3963 case ixgbe_phy_sfp_intel:
3964 case ixgbe_phy_sfp_unknown:
3965 case ixgbe_phy_sfp_passive_tyco:
3966 case ixgbe_phy_sfp_passive_unknown:
3967 case ixgbe_phy_sfp_active_unknown:
3968 case ixgbe_phy_sfp_ftl_active:
3971 if (hw->mac.type == ixgbe_mac_82598EB)
3979 * ixgbe_sfp_link_config - set up SFP+ link
3980 * @adapter: pointer to private adapter struct
3982 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3985 * We are assuming the worst case scenario here, and that
3986 * is that an SFP was inserted/removed after the reset
3987 * but before SFP detection was enabled. As such the best
3988 * solution is to just start searching as soon as we start
3990 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3991 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3993 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3997 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3998 * @hw: pointer to private hardware struct
4000 * Returns 0 on success, negative on failure
4002 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4005 bool negotiation, link_up = false;
4006 u32 ret = IXGBE_ERR_LINK_SETUP;
4008 if (hw->mac.ops.check_link)
4009 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
4014 autoneg = hw->phy.autoneg_advertised;
4015 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4016 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
4021 if (hw->mac.ops.setup_link)
4022 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
4027 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4029 struct ixgbe_hw *hw = &adapter->hw;
4032 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4033 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4035 gpie |= IXGBE_GPIE_EIAME;
4037 * use EIAM to auto-mask when MSI-X interrupt is asserted
4038 * this saves a register write for every interrupt
4040 switch (hw->mac.type) {
4041 case ixgbe_mac_82598EB:
4042 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4044 case ixgbe_mac_82599EB:
4045 case ixgbe_mac_X540:
4047 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4048 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4052 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4053 * specifically only auto mask tx and rx interrupts */
4054 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4057 /* XXX: to interrupt immediately for EICS writes, enable this */
4058 /* gpie |= IXGBE_GPIE_EIMEN; */
4060 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4061 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4063 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4064 case IXGBE_82599_VMDQ_8Q_MASK:
4065 gpie |= IXGBE_GPIE_VTMODE_16;
4067 case IXGBE_82599_VMDQ_4Q_MASK:
4068 gpie |= IXGBE_GPIE_VTMODE_32;
4071 gpie |= IXGBE_GPIE_VTMODE_64;
4076 /* Enable Thermal over heat sensor interrupt */
4077 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4078 switch (adapter->hw.mac.type) {
4079 case ixgbe_mac_82599EB:
4080 gpie |= IXGBE_SDP0_GPIEN;
4082 case ixgbe_mac_X540:
4083 gpie |= IXGBE_EIMS_TS;
4090 /* Enable fan failure interrupt */
4091 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4092 gpie |= IXGBE_SDP1_GPIEN;
4094 if (hw->mac.type == ixgbe_mac_82599EB) {
4095 gpie |= IXGBE_SDP1_GPIEN;
4096 gpie |= IXGBE_SDP2_GPIEN;
4099 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4102 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4104 struct ixgbe_hw *hw = &adapter->hw;
4108 ixgbe_get_hw_control(adapter);
4109 ixgbe_setup_gpie(adapter);
4111 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4112 ixgbe_configure_msix(adapter);
4114 ixgbe_configure_msi_and_legacy(adapter);
4116 /* enable the optics for 82599 SFP+ fiber */
4117 if (hw->mac.ops.enable_tx_laser)
4118 hw->mac.ops.enable_tx_laser(hw);
4120 clear_bit(__IXGBE_DOWN, &adapter->state);
4121 ixgbe_napi_enable_all(adapter);
4123 if (ixgbe_is_sfp(hw)) {
4124 ixgbe_sfp_link_config(adapter);
4126 err = ixgbe_non_sfp_link_config(hw);
4128 e_err(probe, "link_config FAILED %d\n", err);
4131 /* clear any pending interrupts, may auto mask */
4132 IXGBE_READ_REG(hw, IXGBE_EICR);
4133 ixgbe_irq_enable(adapter, true, true);
4136 * If this adapter has a fan, check to see if we had a failure
4137 * before we enabled the interrupt.
4139 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4140 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4141 if (esdp & IXGBE_ESDP_SDP1)
4142 e_crit(drv, "Fan has stopped, replace the adapter\n");
4145 /* enable transmits */
4146 netif_tx_start_all_queues(adapter->netdev);
4148 /* bring the link up in the watchdog, this could race with our first
4149 * link up interrupt but shouldn't be a problem */
4150 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4151 adapter->link_check_timeout = jiffies;
4152 mod_timer(&adapter->service_timer, jiffies);
4154 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4155 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4156 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4157 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4160 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4162 WARN_ON(in_interrupt());
4163 /* put off any impending NetWatchDogTimeout */
4164 adapter->netdev->trans_start = jiffies;
4166 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4167 usleep_range(1000, 2000);
4168 ixgbe_down(adapter);
4170 * If SR-IOV enabled then wait a bit before bringing the adapter
4171 * back up to give the VFs time to respond to the reset. The
4172 * two second wait is based upon the watchdog timer cycle in
4175 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4178 clear_bit(__IXGBE_RESETTING, &adapter->state);
4181 void ixgbe_up(struct ixgbe_adapter *adapter)
4183 /* hardware has been reset, we need to reload some things */
4184 ixgbe_configure(adapter);
4186 ixgbe_up_complete(adapter);
4189 void ixgbe_reset(struct ixgbe_adapter *adapter)
4191 struct ixgbe_hw *hw = &adapter->hw;
4194 /* lock SFP init bit to prevent race conditions with the watchdog */
4195 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4196 usleep_range(1000, 2000);
4198 /* clear all SFP and link config related flags while holding SFP_INIT */
4199 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4200 IXGBE_FLAG2_SFP_NEEDS_RESET);
4201 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4203 err = hw->mac.ops.init_hw(hw);
4206 case IXGBE_ERR_SFP_NOT_PRESENT:
4207 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4209 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4210 e_dev_err("master disable timed out\n");
4212 case IXGBE_ERR_EEPROM_VERSION:
4213 /* We are running on a pre-production device, log a warning */
4214 e_dev_warn("This device is a pre-production adapter/LOM. "
4215 "Please be aware there may be issues associated with "
4216 "your hardware. If you are experiencing problems "
4217 "please contact your Intel or hardware "
4218 "representative who provided you with this "
4222 e_dev_err("Hardware Error: %d\n", err);
4225 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4227 /* reprogram the RAR[0] in case user changed it. */
4228 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4230 /* update SAN MAC vmdq pool selection */
4231 if (hw->mac.san_mac_rar_index)
4232 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4234 #ifdef CONFIG_IXGBE_PTP
4235 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4236 ixgbe_ptp_reset(adapter);
4241 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4242 * @rx_ring: ring to free buffers from
4244 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4246 struct device *dev = rx_ring->dev;
4250 /* ring already cleared, nothing to do */
4251 if (!rx_ring->rx_buffer_info)
4254 /* Free all the Rx ring sk_buffs */
4255 for (i = 0; i < rx_ring->count; i++) {
4256 struct ixgbe_rx_buffer *rx_buffer;
4258 rx_buffer = &rx_ring->rx_buffer_info[i];
4259 if (rx_buffer->skb) {
4260 struct sk_buff *skb = rx_buffer->skb;
4261 if (IXGBE_CB(skb)->page_released) {
4264 ixgbe_rx_bufsz(rx_ring),
4266 IXGBE_CB(skb)->page_released = false;
4270 rx_buffer->skb = NULL;
4272 dma_unmap_page(dev, rx_buffer->dma,
4273 ixgbe_rx_pg_size(rx_ring),
4276 if (rx_buffer->page)
4277 __free_pages(rx_buffer->page,
4278 ixgbe_rx_pg_order(rx_ring));
4279 rx_buffer->page = NULL;
4282 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4283 memset(rx_ring->rx_buffer_info, 0, size);
4285 /* Zero out the descriptor ring */
4286 memset(rx_ring->desc, 0, rx_ring->size);
4288 rx_ring->next_to_alloc = 0;
4289 rx_ring->next_to_clean = 0;
4290 rx_ring->next_to_use = 0;
4294 * ixgbe_clean_tx_ring - Free Tx Buffers
4295 * @tx_ring: ring to be cleaned
4297 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4299 struct ixgbe_tx_buffer *tx_buffer_info;
4303 /* ring already cleared, nothing to do */
4304 if (!tx_ring->tx_buffer_info)
4307 /* Free all the Tx ring sk_buffs */
4308 for (i = 0; i < tx_ring->count; i++) {
4309 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4310 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4313 netdev_tx_reset_queue(txring_txq(tx_ring));
4315 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4316 memset(tx_ring->tx_buffer_info, 0, size);
4318 /* Zero out the descriptor ring */
4319 memset(tx_ring->desc, 0, tx_ring->size);
4321 tx_ring->next_to_use = 0;
4322 tx_ring->next_to_clean = 0;
4326 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4327 * @adapter: board private structure
4329 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4333 for (i = 0; i < adapter->num_rx_queues; i++)
4334 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4338 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4339 * @adapter: board private structure
4341 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4345 for (i = 0; i < adapter->num_tx_queues; i++)
4346 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4349 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4351 struct hlist_node *node, *node2;
4352 struct ixgbe_fdir_filter *filter;
4354 spin_lock(&adapter->fdir_perfect_lock);
4356 hlist_for_each_entry_safe(filter, node, node2,
4357 &adapter->fdir_filter_list, fdir_node) {
4358 hlist_del(&filter->fdir_node);
4361 adapter->fdir_filter_count = 0;
4363 spin_unlock(&adapter->fdir_perfect_lock);
4366 void ixgbe_down(struct ixgbe_adapter *adapter)
4368 struct net_device *netdev = adapter->netdev;
4369 struct ixgbe_hw *hw = &adapter->hw;
4373 /* signal that we are down to the interrupt handler */
4374 set_bit(__IXGBE_DOWN, &adapter->state);
4376 /* disable receives */
4377 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4378 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4380 /* disable all enabled rx queues */
4381 for (i = 0; i < adapter->num_rx_queues; i++)
4382 /* this call also flushes the previous write */
4383 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4385 usleep_range(10000, 20000);
4387 netif_tx_stop_all_queues(netdev);
4389 /* call carrier off first to avoid false dev_watchdog timeouts */
4390 netif_carrier_off(netdev);
4391 netif_tx_disable(netdev);
4393 ixgbe_irq_disable(adapter);
4395 ixgbe_napi_disable_all(adapter);
4397 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4398 IXGBE_FLAG2_RESET_REQUESTED);
4399 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4401 del_timer_sync(&adapter->service_timer);
4403 if (adapter->num_vfs) {
4404 /* Clear EITR Select mapping */
4405 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4407 /* Mark all the VFs as inactive */
4408 for (i = 0 ; i < adapter->num_vfs; i++)
4409 adapter->vfinfo[i].clear_to_send = false;
4411 /* ping all the active vfs to let them know we are going down */
4412 ixgbe_ping_all_vfs(adapter);
4414 /* Disable all VFTE/VFRE TX/RX */
4415 ixgbe_disable_tx_rx(adapter);
4418 /* disable transmits in the hardware now that interrupts are off */
4419 for (i = 0; i < adapter->num_tx_queues; i++) {
4420 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4421 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4424 /* Disable the Tx DMA engine on 82599 and X540 */
4425 switch (hw->mac.type) {
4426 case ixgbe_mac_82599EB:
4427 case ixgbe_mac_X540:
4428 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4429 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4430 ~IXGBE_DMATXCTL_TE));
4436 if (!pci_channel_offline(adapter->pdev))
4437 ixgbe_reset(adapter);
4439 /* power down the optics for 82599 SFP+ fiber */
4440 if (hw->mac.ops.disable_tx_laser)
4441 hw->mac.ops.disable_tx_laser(hw);
4443 ixgbe_clean_all_tx_rings(adapter);
4444 ixgbe_clean_all_rx_rings(adapter);
4446 #ifdef CONFIG_IXGBE_DCA
4447 /* since we reset the hardware DCA settings were cleared */
4448 ixgbe_setup_dca(adapter);
4453 * ixgbe_tx_timeout - Respond to a Tx Hang
4454 * @netdev: network interface device structure
4456 static void ixgbe_tx_timeout(struct net_device *netdev)
4458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4460 /* Do the reset outside of interrupt context */
4461 ixgbe_tx_timeout_reset(adapter);
4465 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4466 * @adapter: board private structure to initialize
4468 * ixgbe_sw_init initializes the Adapter private data structure.
4469 * Fields are initialized based on PCI device information and
4470 * OS network device settings (MTU size).
4472 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4474 struct ixgbe_hw *hw = &adapter->hw;
4475 struct pci_dev *pdev = adapter->pdev;
4477 #ifdef CONFIG_IXGBE_DCB
4479 struct tc_configuration *tc;
4482 /* PCI config space info */
4484 hw->vendor_id = pdev->vendor;
4485 hw->device_id = pdev->device;
4486 hw->revision_id = pdev->revision;
4487 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4488 hw->subsystem_device_id = pdev->subsystem_device;
4490 /* Set capability flags */
4491 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4492 adapter->ring_feature[RING_F_RSS].limit = rss;
4493 switch (hw->mac.type) {
4494 case ixgbe_mac_82598EB:
4495 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4496 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4497 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4499 case ixgbe_mac_X540:
4500 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4501 case ixgbe_mac_82599EB:
4502 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4503 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4504 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4505 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4506 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4507 /* Flow Director hash filters enabled */
4508 adapter->atr_sample_rate = 20;
4509 adapter->ring_feature[RING_F_FDIR].limit =
4510 IXGBE_MAX_FDIR_INDICES;
4511 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4513 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4514 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4515 #ifdef CONFIG_IXGBE_DCB
4516 /* Default traffic class to use for FCoE */
4517 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4519 #endif /* IXGBE_FCOE */
4526 /* FCoE support exists, always init the FCoE lock */
4527 spin_lock_init(&adapter->fcoe.lock);
4530 /* n-tuple support exists, always init our spinlock */
4531 spin_lock_init(&adapter->fdir_perfect_lock);
4533 #ifdef CONFIG_IXGBE_DCB
4534 switch (hw->mac.type) {
4535 case ixgbe_mac_X540:
4536 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4537 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4540 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4541 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4545 /* Configure DCB traffic classes */
4546 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4547 tc = &adapter->dcb_cfg.tc_config[j];
4548 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4549 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4550 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4551 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4552 tc->dcb_pfc = pfc_disabled;
4555 /* Initialize default user to priority mapping, UPx->TC0 */
4556 tc = &adapter->dcb_cfg.tc_config[0];
4557 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4558 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4560 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4561 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4562 adapter->dcb_cfg.pfc_mode_enable = false;
4563 adapter->dcb_set_bitmap = 0x00;
4564 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4565 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4566 sizeof(adapter->temp_dcb_cfg));
4570 /* default flow control settings */
4571 hw->fc.requested_mode = ixgbe_fc_full;
4572 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4573 ixgbe_pbthresh_setup(adapter);
4574 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4575 hw->fc.send_xon = true;
4576 hw->fc.disable_fc_autoneg = false;
4578 #ifdef CONFIG_PCI_IOV
4579 /* assign number of SR-IOV VFs */
4580 if (hw->mac.type != ixgbe_mac_82598EB)
4581 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4584 /* enable itr by default in dynamic mode */
4585 adapter->rx_itr_setting = 1;
4586 adapter->tx_itr_setting = 1;
4588 /* set default ring sizes */
4589 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4590 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4592 /* set default work limits */
4593 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4595 /* initialize eeprom parameters */
4596 if (ixgbe_init_eeprom_params_generic(hw)) {
4597 e_dev_err("EEPROM initialization failed\n");
4601 set_bit(__IXGBE_DOWN, &adapter->state);
4607 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4608 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4610 * Return 0 on success, negative on failure
4612 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4614 struct device *dev = tx_ring->dev;
4615 int orig_node = dev_to_node(dev);
4619 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4621 if (tx_ring->q_vector)
4622 numa_node = tx_ring->q_vector->numa_node;
4624 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4625 if (!tx_ring->tx_buffer_info)
4626 tx_ring->tx_buffer_info = vzalloc(size);
4627 if (!tx_ring->tx_buffer_info)
4630 /* round up to nearest 4K */
4631 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4632 tx_ring->size = ALIGN(tx_ring->size, 4096);
4634 set_dev_node(dev, numa_node);
4635 tx_ring->desc = dma_alloc_coherent(dev,
4639 set_dev_node(dev, orig_node);
4641 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4642 &tx_ring->dma, GFP_KERNEL);
4646 tx_ring->next_to_use = 0;
4647 tx_ring->next_to_clean = 0;
4651 vfree(tx_ring->tx_buffer_info);
4652 tx_ring->tx_buffer_info = NULL;
4653 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4658 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4659 * @adapter: board private structure
4661 * If this function returns with an error, then it's possible one or
4662 * more of the rings is populated (while the rest are not). It is the
4663 * callers duty to clean those orphaned rings.
4665 * Return 0 on success, negative on failure
4667 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4671 for (i = 0; i < adapter->num_tx_queues; i++) {
4672 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4676 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4682 /* rewind the index freeing the rings as we go */
4684 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4689 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4690 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4692 * Returns 0 on success, negative on failure
4694 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4696 struct device *dev = rx_ring->dev;
4697 int orig_node = dev_to_node(dev);
4701 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4703 if (rx_ring->q_vector)
4704 numa_node = rx_ring->q_vector->numa_node;
4706 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4707 if (!rx_ring->rx_buffer_info)
4708 rx_ring->rx_buffer_info = vzalloc(size);
4709 if (!rx_ring->rx_buffer_info)
4712 /* Round up to nearest 4K */
4713 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4714 rx_ring->size = ALIGN(rx_ring->size, 4096);
4716 set_dev_node(dev, numa_node);
4717 rx_ring->desc = dma_alloc_coherent(dev,
4721 set_dev_node(dev, orig_node);
4723 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4724 &rx_ring->dma, GFP_KERNEL);
4728 rx_ring->next_to_clean = 0;
4729 rx_ring->next_to_use = 0;
4733 vfree(rx_ring->rx_buffer_info);
4734 rx_ring->rx_buffer_info = NULL;
4735 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4740 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4741 * @adapter: board private structure
4743 * If this function returns with an error, then it's possible one or
4744 * more of the rings is populated (while the rest are not). It is the
4745 * callers duty to clean those orphaned rings.
4747 * Return 0 on success, negative on failure
4749 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4753 for (i = 0; i < adapter->num_rx_queues; i++) {
4754 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4758 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4763 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4768 /* rewind the index freeing the rings as we go */
4770 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4775 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4776 * @tx_ring: Tx descriptor ring for a specific queue
4778 * Free all transmit software resources
4780 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4782 ixgbe_clean_tx_ring(tx_ring);
4784 vfree(tx_ring->tx_buffer_info);
4785 tx_ring->tx_buffer_info = NULL;
4787 /* if not set, then don't free */
4791 dma_free_coherent(tx_ring->dev, tx_ring->size,
4792 tx_ring->desc, tx_ring->dma);
4794 tx_ring->desc = NULL;
4798 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4799 * @adapter: board private structure
4801 * Free all transmit software resources
4803 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4807 for (i = 0; i < adapter->num_tx_queues; i++)
4808 if (adapter->tx_ring[i]->desc)
4809 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4813 * ixgbe_free_rx_resources - Free Rx Resources
4814 * @rx_ring: ring to clean the resources from
4816 * Free all receive software resources
4818 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4820 ixgbe_clean_rx_ring(rx_ring);
4822 vfree(rx_ring->rx_buffer_info);
4823 rx_ring->rx_buffer_info = NULL;
4825 /* if not set, then don't free */
4829 dma_free_coherent(rx_ring->dev, rx_ring->size,
4830 rx_ring->desc, rx_ring->dma);
4832 rx_ring->desc = NULL;
4836 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4837 * @adapter: board private structure
4839 * Free all receive software resources
4841 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4846 ixgbe_free_fcoe_ddp_resources(adapter);
4849 for (i = 0; i < adapter->num_rx_queues; i++)
4850 if (adapter->rx_ring[i]->desc)
4851 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4855 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4856 * @netdev: network interface device structure
4857 * @new_mtu: new value for maximum frame size
4859 * Returns 0 on success, negative on failure
4861 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4864 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4866 /* MTU < 68 is an error and causes problems on some kernels */
4867 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4871 * For 82599EB we cannot allow legacy VFs to enable their receive
4872 * paths when MTU greater than 1500 is configured. So display a
4873 * warning that legacy VFs will be disabled.
4875 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4876 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4877 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4878 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4880 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4882 /* must set new MTU before calling down or up */
4883 netdev->mtu = new_mtu;
4885 if (netif_running(netdev))
4886 ixgbe_reinit_locked(adapter);
4892 * ixgbe_open - Called when a network interface is made active
4893 * @netdev: network interface device structure
4895 * Returns 0 on success, negative value on failure
4897 * The open entry point is called when a network interface is made
4898 * active by the system (IFF_UP). At this point all resources needed
4899 * for transmit and receive operations are allocated, the interrupt
4900 * handler is registered with the OS, the watchdog timer is started,
4901 * and the stack is notified that the interface is ready.
4903 static int ixgbe_open(struct net_device *netdev)
4905 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4908 /* disallow open during test */
4909 if (test_bit(__IXGBE_TESTING, &adapter->state))
4912 netif_carrier_off(netdev);
4914 /* allocate transmit descriptors */
4915 err = ixgbe_setup_all_tx_resources(adapter);
4919 /* allocate receive descriptors */
4920 err = ixgbe_setup_all_rx_resources(adapter);
4924 ixgbe_configure(adapter);
4926 err = ixgbe_request_irq(adapter);
4930 /* Notify the stack of the actual queue counts. */
4931 err = netif_set_real_num_tx_queues(netdev,
4932 adapter->num_rx_pools > 1 ? 1 :
4933 adapter->num_tx_queues);
4935 goto err_set_queues;
4938 err = netif_set_real_num_rx_queues(netdev,
4939 adapter->num_rx_pools > 1 ? 1 :
4940 adapter->num_rx_queues);
4942 goto err_set_queues;
4944 #ifdef CONFIG_IXGBE_PTP
4945 ixgbe_ptp_init(adapter);
4946 #endif /* CONFIG_IXGBE_PTP*/
4948 ixgbe_up_complete(adapter);
4953 ixgbe_free_irq(adapter);
4955 ixgbe_free_all_rx_resources(adapter);
4957 ixgbe_free_all_tx_resources(adapter);
4959 ixgbe_reset(adapter);
4965 * ixgbe_close - Disables a network interface
4966 * @netdev: network interface device structure
4968 * Returns 0, this is not allowed to fail
4970 * The close entry point is called when an interface is de-activated
4971 * by the OS. The hardware is still under the drivers control, but
4972 * needs to be disabled. A global MAC reset is issued to stop the
4973 * hardware, and all transmit and receive resources are freed.
4975 static int ixgbe_close(struct net_device *netdev)
4977 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4979 #ifdef CONFIG_IXGBE_PTP
4980 ixgbe_ptp_stop(adapter);
4983 ixgbe_down(adapter);
4984 ixgbe_free_irq(adapter);
4986 ixgbe_fdir_filter_exit(adapter);
4988 ixgbe_free_all_tx_resources(adapter);
4989 ixgbe_free_all_rx_resources(adapter);
4991 ixgbe_release_hw_control(adapter);
4997 static int ixgbe_resume(struct pci_dev *pdev)
4999 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5000 struct net_device *netdev = adapter->netdev;
5003 pci_set_power_state(pdev, PCI_D0);
5004 pci_restore_state(pdev);
5006 * pci_restore_state clears dev->state_saved so call
5007 * pci_save_state to restore it.
5009 pci_save_state(pdev);
5011 err = pci_enable_device_mem(pdev);
5013 e_dev_err("Cannot enable PCI device from suspend\n");
5016 pci_set_master(pdev);
5018 pci_wake_from_d3(pdev, false);
5020 ixgbe_reset(adapter);
5022 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5025 err = ixgbe_init_interrupt_scheme(adapter);
5026 if (!err && netif_running(netdev))
5027 err = ixgbe_open(netdev);
5034 netif_device_attach(netdev);
5038 #endif /* CONFIG_PM */
5040 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5042 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5043 struct net_device *netdev = adapter->netdev;
5044 struct ixgbe_hw *hw = &adapter->hw;
5046 u32 wufc = adapter->wol;
5051 netif_device_detach(netdev);
5053 if (netif_running(netdev)) {
5055 ixgbe_down(adapter);
5056 ixgbe_free_irq(adapter);
5057 ixgbe_free_all_tx_resources(adapter);
5058 ixgbe_free_all_rx_resources(adapter);
5062 ixgbe_clear_interrupt_scheme(adapter);
5065 retval = pci_save_state(pdev);
5071 ixgbe_set_rx_mode(netdev);
5073 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5074 if (hw->mac.ops.enable_tx_laser)
5075 hw->mac.ops.enable_tx_laser(hw);
5077 /* turn on all-multi mode if wake on multicast is enabled */
5078 if (wufc & IXGBE_WUFC_MC) {
5079 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5080 fctrl |= IXGBE_FCTRL_MPE;
5081 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5084 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5085 ctrl |= IXGBE_CTRL_GIO_DIS;
5086 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5088 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5090 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5091 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5094 switch (hw->mac.type) {
5095 case ixgbe_mac_82598EB:
5096 pci_wake_from_d3(pdev, false);
5098 case ixgbe_mac_82599EB:
5099 case ixgbe_mac_X540:
5100 pci_wake_from_d3(pdev, !!wufc);
5106 *enable_wake = !!wufc;
5108 ixgbe_release_hw_control(adapter);
5110 pci_disable_device(pdev);
5116 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5121 retval = __ixgbe_shutdown(pdev, &wake);
5126 pci_prepare_to_sleep(pdev);
5128 pci_wake_from_d3(pdev, false);
5129 pci_set_power_state(pdev, PCI_D3hot);
5134 #endif /* CONFIG_PM */
5136 static void ixgbe_shutdown(struct pci_dev *pdev)
5140 __ixgbe_shutdown(pdev, &wake);
5142 if (system_state == SYSTEM_POWER_OFF) {
5143 pci_wake_from_d3(pdev, wake);
5144 pci_set_power_state(pdev, PCI_D3hot);
5149 * ixgbe_update_stats - Update the board statistics counters.
5150 * @adapter: board private structure
5152 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5154 struct net_device *netdev = adapter->netdev;
5155 struct ixgbe_hw *hw = &adapter->hw;
5156 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5158 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5159 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5160 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5161 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5163 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5164 test_bit(__IXGBE_RESETTING, &adapter->state))
5167 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5170 for (i = 0; i < adapter->num_rx_queues; i++) {
5171 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5172 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5174 adapter->rsc_total_count = rsc_count;
5175 adapter->rsc_total_flush = rsc_flush;
5178 for (i = 0; i < adapter->num_rx_queues; i++) {
5179 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5180 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5181 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5182 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5183 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5184 bytes += rx_ring->stats.bytes;
5185 packets += rx_ring->stats.packets;
5187 adapter->non_eop_descs = non_eop_descs;
5188 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5189 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5190 adapter->hw_csum_rx_error = hw_csum_rx_error;
5191 netdev->stats.rx_bytes = bytes;
5192 netdev->stats.rx_packets = packets;
5196 /* gather some stats to the adapter struct that are per queue */
5197 for (i = 0; i < adapter->num_tx_queues; i++) {
5198 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5199 restart_queue += tx_ring->tx_stats.restart_queue;
5200 tx_busy += tx_ring->tx_stats.tx_busy;
5201 bytes += tx_ring->stats.bytes;
5202 packets += tx_ring->stats.packets;
5204 adapter->restart_queue = restart_queue;
5205 adapter->tx_busy = tx_busy;
5206 netdev->stats.tx_bytes = bytes;
5207 netdev->stats.tx_packets = packets;
5209 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5211 /* 8 register reads */
5212 for (i = 0; i < 8; i++) {
5213 /* for packet buffers not used, the register should read 0 */
5214 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5216 hwstats->mpc[i] += mpc;
5217 total_mpc += hwstats->mpc[i];
5218 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5219 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5220 switch (hw->mac.type) {
5221 case ixgbe_mac_82598EB:
5222 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5223 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5224 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5225 hwstats->pxonrxc[i] +=
5226 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5228 case ixgbe_mac_82599EB:
5229 case ixgbe_mac_X540:
5230 hwstats->pxonrxc[i] +=
5231 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5238 /*16 register reads */
5239 for (i = 0; i < 16; i++) {
5240 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5241 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5242 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5243 (hw->mac.type == ixgbe_mac_X540)) {
5244 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5245 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5246 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5247 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5251 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5252 /* work around hardware counting issue */
5253 hwstats->gprc -= missed_rx;
5255 ixgbe_update_xoff_received(adapter);
5257 /* 82598 hardware only has a 32 bit counter in the high register */
5258 switch (hw->mac.type) {
5259 case ixgbe_mac_82598EB:
5260 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5261 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5262 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5263 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5265 case ixgbe_mac_X540:
5266 /* OS2BMC stats are X540 only*/
5267 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5268 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5269 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5270 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5271 case ixgbe_mac_82599EB:
5272 for (i = 0; i < 16; i++)
5273 adapter->hw_rx_no_dma_resources +=
5274 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5275 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5276 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5277 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5278 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5279 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5280 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5281 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5282 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5283 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5285 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5286 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5287 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5288 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5289 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5290 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5291 /* Add up per cpu counters for total ddp aloc fail */
5292 if (adapter->fcoe.ddp_pool) {
5293 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5294 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5296 u64 noddp = 0, noddp_ext_buff = 0;
5297 for_each_possible_cpu(cpu) {
5298 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5299 noddp += ddp_pool->noddp;
5300 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5302 hwstats->fcoe_noddp = noddp;
5303 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5305 #endif /* IXGBE_FCOE */
5310 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5311 hwstats->bprc += bprc;
5312 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5313 if (hw->mac.type == ixgbe_mac_82598EB)
5314 hwstats->mprc -= bprc;
5315 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5316 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5317 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5318 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5319 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5320 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5321 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5322 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5323 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5324 hwstats->lxontxc += lxon;
5325 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5326 hwstats->lxofftxc += lxoff;
5327 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5328 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5330 * 82598 errata - tx of flow control packets is included in tx counters
5332 xon_off_tot = lxon + lxoff;
5333 hwstats->gptc -= xon_off_tot;
5334 hwstats->mptc -= xon_off_tot;
5335 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5336 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5337 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5338 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5339 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5340 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5341 hwstats->ptc64 -= xon_off_tot;
5342 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5343 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5344 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5345 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5346 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5347 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5349 /* Fill out the OS statistics structure */
5350 netdev->stats.multicast = hwstats->mprc;
5353 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5354 netdev->stats.rx_dropped = 0;
5355 netdev->stats.rx_length_errors = hwstats->rlec;
5356 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5357 netdev->stats.rx_missed_errors = total_mpc;
5361 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5362 * @adapter: pointer to the device adapter structure
5364 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5366 struct ixgbe_hw *hw = &adapter->hw;
5369 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5372 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5374 /* if interface is down do nothing */
5375 if (test_bit(__IXGBE_DOWN, &adapter->state))
5378 /* do nothing if we are not using signature filters */
5379 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5382 adapter->fdir_overflow++;
5384 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5385 for (i = 0; i < adapter->num_tx_queues; i++)
5386 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5387 &(adapter->tx_ring[i]->state));
5388 /* re-enable flow director interrupts */
5389 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5391 e_err(probe, "failed to finish FDIR re-initialization, "
5392 "ignored adding FDIR ATR filters\n");
5397 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5398 * @adapter: pointer to the device adapter structure
5400 * This function serves two purposes. First it strobes the interrupt lines
5401 * in order to make certain interrupts are occurring. Secondly it sets the
5402 * bits needed to check for TX hangs. As a result we should immediately
5403 * determine if a hang has occurred.
5405 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5407 struct ixgbe_hw *hw = &adapter->hw;
5411 /* If we're down or resetting, just bail */
5412 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5413 test_bit(__IXGBE_RESETTING, &adapter->state))
5416 /* Force detection of hung controller */
5417 if (netif_carrier_ok(adapter->netdev)) {
5418 for (i = 0; i < adapter->num_tx_queues; i++)
5419 set_check_for_tx_hang(adapter->tx_ring[i]);
5422 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5424 * for legacy and MSI interrupts don't set any bits
5425 * that are enabled for EIAM, because this operation
5426 * would set *both* EIMS and EICS for any bit in EIAM
5428 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5429 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5431 /* get one bit for every active tx/rx interrupt vector */
5432 for (i = 0; i < adapter->num_q_vectors; i++) {
5433 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5434 if (qv->rx.ring || qv->tx.ring)
5435 eics |= ((u64)1 << i);
5439 /* Cause software interrupt to ensure rings are cleaned */
5440 ixgbe_irq_rearm_queues(adapter, eics);
5445 * ixgbe_watchdog_update_link - update the link status
5446 * @adapter: pointer to the device adapter structure
5447 * @link_speed: pointer to a u32 to store the link_speed
5449 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5451 struct ixgbe_hw *hw = &adapter->hw;
5452 u32 link_speed = adapter->link_speed;
5453 bool link_up = adapter->link_up;
5454 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5456 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5459 if (hw->mac.ops.check_link) {
5460 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5462 /* always assume link is up, if no check link function */
5463 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5467 if (adapter->ixgbe_ieee_pfc)
5468 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5470 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5471 hw->mac.ops.fc_enable(hw);
5472 ixgbe_set_rx_drop_en(adapter);
5476 time_after(jiffies, (adapter->link_check_timeout +
5477 IXGBE_TRY_LINK_TIMEOUT))) {
5478 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5479 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5480 IXGBE_WRITE_FLUSH(hw);
5483 adapter->link_up = link_up;
5484 adapter->link_speed = link_speed;
5487 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5489 #ifdef CONFIG_IXGBE_DCB
5490 struct net_device *netdev = adapter->netdev;
5491 struct dcb_app app = {
5492 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5497 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5498 up = dcb_ieee_getapp_mask(netdev, &app);
5500 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5505 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5506 * print link up message
5507 * @adapter: pointer to the device adapter structure
5509 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5511 struct net_device *netdev = adapter->netdev;
5512 struct ixgbe_hw *hw = &adapter->hw;
5513 u32 link_speed = adapter->link_speed;
5514 bool flow_rx, flow_tx;
5516 /* only continue if link was previously down */
5517 if (netif_carrier_ok(netdev))
5520 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5522 switch (hw->mac.type) {
5523 case ixgbe_mac_82598EB: {
5524 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5525 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5526 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5527 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5530 case ixgbe_mac_X540:
5531 case ixgbe_mac_82599EB: {
5532 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5533 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5534 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5535 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5544 #ifdef CONFIG_IXGBE_PTP
5545 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5546 ixgbe_ptp_start_cyclecounter(adapter);
5549 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5550 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5552 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5554 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5557 ((flow_rx && flow_tx) ? "RX/TX" :
5559 (flow_tx ? "TX" : "None"))));
5561 netif_carrier_on(netdev);
5562 ixgbe_check_vf_rate_limit(adapter);
5564 /* update the default user priority for VFs */
5565 ixgbe_update_default_up(adapter);
5567 /* ping all the active vfs to let them know link has changed */
5568 ixgbe_ping_all_vfs(adapter);
5572 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5573 * print link down message
5574 * @adapter: pointer to the adapter structure
5576 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5578 struct net_device *netdev = adapter->netdev;
5579 struct ixgbe_hw *hw = &adapter->hw;
5581 adapter->link_up = false;
5582 adapter->link_speed = 0;
5584 /* only continue if link was up previously */
5585 if (!netif_carrier_ok(netdev))
5588 /* poll for SFP+ cable when link is down */
5589 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5590 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5592 #ifdef CONFIG_IXGBE_PTP
5593 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5594 ixgbe_ptp_start_cyclecounter(adapter);
5597 e_info(drv, "NIC Link is Down\n");
5598 netif_carrier_off(netdev);
5600 /* ping all the active vfs to let them know link has changed */
5601 ixgbe_ping_all_vfs(adapter);
5605 * ixgbe_watchdog_flush_tx - flush queues on link down
5606 * @adapter: pointer to the device adapter structure
5608 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5611 int some_tx_pending = 0;
5613 if (!netif_carrier_ok(adapter->netdev)) {
5614 for (i = 0; i < adapter->num_tx_queues; i++) {
5615 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5616 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5617 some_tx_pending = 1;
5622 if (some_tx_pending) {
5623 /* We've lost link, so the controller stops DMA,
5624 * but we've got queued Tx work that's never going
5625 * to get done, so reset controller to flush Tx.
5626 * (Do the reset outside of interrupt context).
5628 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5633 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5637 /* Do not perform spoof check for 82598 or if not in IOV mode */
5638 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5639 adapter->num_vfs == 0)
5642 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5645 * ssvpc register is cleared on read, if zero then no
5646 * spoofed packets in the last interval.
5651 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5655 * ixgbe_watchdog_subtask - check and bring link up
5656 * @adapter: pointer to the device adapter structure
5658 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5660 /* if interface is down do nothing */
5661 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5662 test_bit(__IXGBE_RESETTING, &adapter->state))
5665 ixgbe_watchdog_update_link(adapter);
5667 if (adapter->link_up)
5668 ixgbe_watchdog_link_is_up(adapter);
5670 ixgbe_watchdog_link_is_down(adapter);
5672 ixgbe_spoof_check(adapter);
5673 ixgbe_update_stats(adapter);
5675 ixgbe_watchdog_flush_tx(adapter);
5679 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5680 * @adapter: the ixgbe adapter structure
5682 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5684 struct ixgbe_hw *hw = &adapter->hw;
5687 /* not searching for SFP so there is nothing to do here */
5688 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5689 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5692 /* someone else is in init, wait until next service event */
5693 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5696 err = hw->phy.ops.identify_sfp(hw);
5697 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5700 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5701 /* If no cable is present, then we need to reset
5702 * the next time we find a good cable. */
5703 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5710 /* exit if reset not needed */
5711 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5714 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5717 * A module may be identified correctly, but the EEPROM may not have
5718 * support for that module. setup_sfp() will fail in that case, so
5719 * we should not allow that module to load.
5721 if (hw->mac.type == ixgbe_mac_82598EB)
5722 err = hw->phy.ops.reset(hw);
5724 err = hw->mac.ops.setup_sfp(hw);
5726 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5729 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5730 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5733 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5735 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5736 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5737 e_dev_err("failed to initialize because an unsupported "
5738 "SFP+ module type was detected.\n");
5739 e_dev_err("Reload the driver after installing a "
5740 "supported module.\n");
5741 unregister_netdev(adapter->netdev);
5746 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5747 * @adapter: the ixgbe adapter structure
5749 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5751 struct ixgbe_hw *hw = &adapter->hw;
5755 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5758 /* someone else is in init, wait until next service event */
5759 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5762 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5764 autoneg = hw->phy.autoneg_advertised;
5765 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5766 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5767 if (hw->mac.ops.setup_link)
5768 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5770 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5771 adapter->link_check_timeout = jiffies;
5772 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5775 #ifdef CONFIG_PCI_IOV
5776 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5779 struct ixgbe_hw *hw = &adapter->hw;
5780 struct net_device *netdev = adapter->netdev;
5784 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5785 if (gpc) /* If incrementing then no need for the check below */
5788 * Check to see if a bad DMA write target from an errant or
5789 * malicious VF has caused a PCIe error. If so then we can
5790 * issue a VFLR to the offending VF(s) and then resume without
5791 * requesting a full slot reset.
5794 for (vf = 0; vf < adapter->num_vfs; vf++) {
5795 ciaa = (vf << 16) | 0x80000000;
5796 /* 32 bit read so align, we really want status at offset 6 */
5797 ciaa |= PCI_COMMAND;
5798 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5799 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5801 /* disable debug mode asap after reading data */
5802 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5803 /* Get the upper 16 bits which will be the PCI status reg */
5805 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5806 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5808 ciaa = (vf << 16) | 0x80000000;
5810 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5811 ciad = 0x00008000; /* VFLR */
5812 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5814 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5821 * ixgbe_service_timer - Timer Call-back
5822 * @data: pointer to adapter cast into an unsigned long
5824 static void ixgbe_service_timer(unsigned long data)
5826 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5827 unsigned long next_event_offset;
5830 /* poll faster when waiting for link */
5831 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5832 next_event_offset = HZ / 10;
5834 next_event_offset = HZ * 2;
5836 #ifdef CONFIG_PCI_IOV
5838 * don't bother with SR-IOV VF DMA hang check if there are
5839 * no VFs or the link is down
5841 if (!adapter->num_vfs ||
5842 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5843 goto normal_timer_service;
5845 /* If we have VFs allocated then we must check for DMA hangs */
5846 ixgbe_check_for_bad_vf(adapter);
5847 next_event_offset = HZ / 50;
5848 adapter->timer_event_accumulator++;
5850 if (adapter->timer_event_accumulator >= 100)
5851 adapter->timer_event_accumulator = 0;
5855 normal_timer_service:
5857 /* Reset the timer */
5858 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5861 ixgbe_service_event_schedule(adapter);
5864 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5866 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5869 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5871 /* If we're already down or resetting, just bail */
5872 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5873 test_bit(__IXGBE_RESETTING, &adapter->state))
5876 ixgbe_dump(adapter);
5877 netdev_err(adapter->netdev, "Reset adapter\n");
5878 adapter->tx_timeout_count++;
5880 ixgbe_reinit_locked(adapter);
5884 * ixgbe_service_task - manages and runs subtasks
5885 * @work: pointer to work_struct containing our data
5887 static void ixgbe_service_task(struct work_struct *work)
5889 struct ixgbe_adapter *adapter = container_of(work,
5890 struct ixgbe_adapter,
5893 ixgbe_reset_subtask(adapter);
5894 ixgbe_sfp_detection_subtask(adapter);
5895 ixgbe_sfp_link_config_subtask(adapter);
5896 ixgbe_check_overtemp_subtask(adapter);
5897 ixgbe_watchdog_subtask(adapter);
5898 ixgbe_fdir_reinit_subtask(adapter);
5899 ixgbe_check_hang_subtask(adapter);
5900 #ifdef CONFIG_IXGBE_PTP
5901 ixgbe_ptp_overflow_check(adapter);
5904 ixgbe_service_event_complete(adapter);
5907 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5908 struct ixgbe_tx_buffer *first,
5911 struct sk_buff *skb = first->skb;
5912 u32 vlan_macip_lens, type_tucmd;
5913 u32 mss_l4len_idx, l4len;
5915 if (!skb_is_gso(skb))
5918 if (skb_header_cloned(skb)) {
5919 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5924 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5925 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5927 if (first->protocol == __constant_htons(ETH_P_IP)) {
5928 struct iphdr *iph = ip_hdr(skb);
5931 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5935 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5936 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5937 IXGBE_TX_FLAGS_CSUM |
5938 IXGBE_TX_FLAGS_IPV4;
5939 } else if (skb_is_gso_v6(skb)) {
5940 ipv6_hdr(skb)->payload_len = 0;
5941 tcp_hdr(skb)->check =
5942 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5943 &ipv6_hdr(skb)->daddr,
5945 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5946 IXGBE_TX_FLAGS_CSUM;
5949 /* compute header lengths */
5950 l4len = tcp_hdrlen(skb);
5951 *hdr_len = skb_transport_offset(skb) + l4len;
5953 /* update gso size and bytecount with header size */
5954 first->gso_segs = skb_shinfo(skb)->gso_segs;
5955 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5957 /* mss_l4len_id: use 1 as index for TSO */
5958 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5959 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5960 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5962 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5963 vlan_macip_lens = skb_network_header_len(skb);
5964 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5965 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5967 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5973 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5974 struct ixgbe_tx_buffer *first)
5976 struct sk_buff *skb = first->skb;
5977 u32 vlan_macip_lens = 0;
5978 u32 mss_l4len_idx = 0;
5981 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5982 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5983 if (unlikely(skb->no_fcs))
5984 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5985 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5990 switch (first->protocol) {
5991 case __constant_htons(ETH_P_IP):
5992 vlan_macip_lens |= skb_network_header_len(skb);
5993 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5994 l4_hdr = ip_hdr(skb)->protocol;
5996 case __constant_htons(ETH_P_IPV6):
5997 vlan_macip_lens |= skb_network_header_len(skb);
5998 l4_hdr = ipv6_hdr(skb)->nexthdr;
6001 if (unlikely(net_ratelimit())) {
6002 dev_warn(tx_ring->dev,
6003 "partial checksum but proto=%x!\n",
6011 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6012 mss_l4len_idx = tcp_hdrlen(skb) <<
6013 IXGBE_ADVTXD_L4LEN_SHIFT;
6016 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6017 mss_l4len_idx = sizeof(struct sctphdr) <<
6018 IXGBE_ADVTXD_L4LEN_SHIFT;
6021 mss_l4len_idx = sizeof(struct udphdr) <<
6022 IXGBE_ADVTXD_L4LEN_SHIFT;
6025 if (unlikely(net_ratelimit())) {
6026 dev_warn(tx_ring->dev,
6027 "partial checksum but l4 proto=%x!\n",
6033 /* update TX checksum flag */
6034 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6037 /* vlan_macip_lens: MACLEN, VLAN tag */
6038 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6039 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6041 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6042 type_tucmd, mss_l4len_idx);
6045 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6047 /* set type for advanced descriptor with frame checksum insertion */
6048 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6049 IXGBE_ADVTXD_DCMD_DEXT);
6051 /* set HW vlan bit if vlan is present */
6052 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6053 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6055 #ifdef CONFIG_IXGBE_PTP
6056 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6057 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
6060 /* set segmentation enable bits for TSO/FSO */
6062 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
6064 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6066 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6068 /* insert frame checksum */
6069 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6070 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6075 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6076 u32 tx_flags, unsigned int paylen)
6078 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6080 /* enable L4 checksum for TSO and TX checksum offload */
6081 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6082 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6084 /* enble IPv4 checksum for TSO */
6085 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6086 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6088 /* use index 1 context for TSO/FSO/FCOE */
6090 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6092 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6094 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6097 * Check Context must be set if Tx switch is enabled, which it
6098 * always is for case where virtual functions are running
6101 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6103 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6105 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6107 tx_desc->read.olinfo_status = olinfo_status;
6110 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6113 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6114 struct ixgbe_tx_buffer *first,
6118 struct sk_buff *skb = first->skb;
6119 struct ixgbe_tx_buffer *tx_buffer;
6120 union ixgbe_adv_tx_desc *tx_desc;
6121 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6122 unsigned int data_len = skb->data_len;
6123 unsigned int size = skb_headlen(skb);
6124 unsigned int paylen = skb->len - hdr_len;
6125 u32 tx_flags = first->tx_flags;
6127 u16 i = tx_ring->next_to_use;
6129 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6131 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6132 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6135 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6136 if (data_len < sizeof(struct fcoe_crc_eof)) {
6137 size -= sizeof(struct fcoe_crc_eof) - data_len;
6140 data_len -= sizeof(struct fcoe_crc_eof);
6145 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6146 if (dma_mapping_error(tx_ring->dev, dma))
6149 /* record length, and DMA address */
6150 dma_unmap_len_set(first, len, size);
6151 dma_unmap_addr_set(first, dma, dma);
6153 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6156 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6157 tx_desc->read.cmd_type_len =
6158 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6162 if (i == tx_ring->count) {
6163 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6167 dma += IXGBE_MAX_DATA_PER_TXD;
6168 size -= IXGBE_MAX_DATA_PER_TXD;
6170 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6171 tx_desc->read.olinfo_status = 0;
6174 if (likely(!data_len))
6177 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6181 if (i == tx_ring->count) {
6182 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6187 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6189 size = skb_frag_size(frag);
6193 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6195 if (dma_mapping_error(tx_ring->dev, dma))
6198 tx_buffer = &tx_ring->tx_buffer_info[i];
6199 dma_unmap_len_set(tx_buffer, len, size);
6200 dma_unmap_addr_set(tx_buffer, dma, dma);
6202 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6203 tx_desc->read.olinfo_status = 0;
6208 /* write last descriptor with RS and EOP bits */
6209 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6210 tx_desc->read.cmd_type_len = cmd_type;
6212 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6214 /* set the timestamp */
6215 first->time_stamp = jiffies;
6218 * Force memory writes to complete before letting h/w know there
6219 * are new descriptors to fetch. (Only applicable for weak-ordered
6220 * memory model archs, such as IA-64).
6222 * We also need this memory barrier to make certain all of the
6223 * status bits have been updated before next_to_watch is written.
6227 /* set next_to_watch value indicating a packet is present */
6228 first->next_to_watch = tx_desc;
6231 if (i == tx_ring->count)
6234 tx_ring->next_to_use = i;
6236 /* notify HW of packet */
6237 writel(i, tx_ring->tail);
6241 dev_err(tx_ring->dev, "TX DMA map failed\n");
6243 /* clear dma mappings for failed tx_buffer_info map */
6245 tx_buffer = &tx_ring->tx_buffer_info[i];
6246 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6247 if (tx_buffer == first)
6254 tx_ring->next_to_use = i;
6257 static void ixgbe_atr(struct ixgbe_ring *ring,
6258 struct ixgbe_tx_buffer *first)
6260 struct ixgbe_q_vector *q_vector = ring->q_vector;
6261 union ixgbe_atr_hash_dword input = { .dword = 0 };
6262 union ixgbe_atr_hash_dword common = { .dword = 0 };
6264 unsigned char *network;
6266 struct ipv6hdr *ipv6;
6271 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6275 /* do nothing if sampling is disabled */
6276 if (!ring->atr_sample_rate)
6281 /* snag network header to get L4 type and address */
6282 hdr.network = skb_network_header(first->skb);
6284 /* Currently only IPv4/IPv6 with TCP is supported */
6285 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6286 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6287 (first->protocol != __constant_htons(ETH_P_IP) ||
6288 hdr.ipv4->protocol != IPPROTO_TCP))
6291 th = tcp_hdr(first->skb);
6293 /* skip this packet since it is invalid or the socket is closing */
6297 /* sample on all syn packets or once every atr sample count */
6298 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6301 /* reset sample count */
6302 ring->atr_count = 0;
6304 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6307 * src and dst are inverted, think how the receiver sees them
6309 * The input is broken into two sections, a non-compressed section
6310 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6311 * is XORed together and stored in the compressed dword.
6313 input.formatted.vlan_id = vlan_id;
6316 * since src port and flex bytes occupy the same word XOR them together
6317 * and write the value to source port portion of compressed dword
6319 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6320 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6322 common.port.src ^= th->dest ^ first->protocol;
6323 common.port.dst ^= th->source;
6325 if (first->protocol == __constant_htons(ETH_P_IP)) {
6326 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6327 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6329 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6330 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6331 hdr.ipv6->saddr.s6_addr32[1] ^
6332 hdr.ipv6->saddr.s6_addr32[2] ^
6333 hdr.ipv6->saddr.s6_addr32[3] ^
6334 hdr.ipv6->daddr.s6_addr32[0] ^
6335 hdr.ipv6->daddr.s6_addr32[1] ^
6336 hdr.ipv6->daddr.s6_addr32[2] ^
6337 hdr.ipv6->daddr.s6_addr32[3];
6340 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6341 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6342 input, common, ring->queue_index);
6345 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6347 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6348 /* Herbert's original patch had:
6349 * smp_mb__after_netif_stop_queue();
6350 * but since that doesn't exist yet, just open code it. */
6353 /* We need to check again in a case another CPU has just
6354 * made room available. */
6355 if (likely(ixgbe_desc_unused(tx_ring) < size))
6358 /* A reprieve! - use start_queue because it doesn't call schedule */
6359 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6360 ++tx_ring->tx_stats.restart_queue;
6364 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6366 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6368 return __ixgbe_maybe_stop_tx(tx_ring, size);
6371 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6373 struct ixgbe_adapter *adapter = netdev_priv(dev);
6374 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6377 __be16 protocol = vlan_get_protocol(skb);
6379 if (((protocol == htons(ETH_P_FCOE)) ||
6380 (protocol == htons(ETH_P_FIP))) &&
6381 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6382 struct ixgbe_ring_feature *f;
6384 f = &adapter->ring_feature[RING_F_FCOE];
6386 while (txq >= f->indices)
6388 txq += adapter->ring_feature[RING_F_FCOE].offset;
6394 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6395 while (unlikely(txq >= dev->real_num_tx_queues))
6396 txq -= dev->real_num_tx_queues;
6400 return skb_tx_hash(dev, skb);
6403 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6404 struct ixgbe_adapter *adapter,
6405 struct ixgbe_ring *tx_ring)
6407 struct ixgbe_tx_buffer *first;
6410 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6413 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6414 __be16 protocol = skb->protocol;
6418 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6419 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6420 * + 2 desc gap to keep tail from touching head,
6421 * + 1 desc for context descriptor,
6422 * otherwise try next time
6424 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6425 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6426 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6428 count += skb_shinfo(skb)->nr_frags;
6430 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6431 tx_ring->tx_stats.tx_busy++;
6432 return NETDEV_TX_BUSY;
6435 /* record the location of the first descriptor for this packet */
6436 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6438 first->bytecount = skb->len;
6439 first->gso_segs = 1;
6441 /* if we have a HW VLAN tag being added default to the HW one */
6442 if (vlan_tx_tag_present(skb)) {
6443 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6444 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6445 /* else if it is a SW VLAN check the next protocol and store the tag */
6446 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6447 struct vlan_hdr *vhdr, _vhdr;
6448 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6452 protocol = vhdr->h_vlan_encapsulated_proto;
6453 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6454 IXGBE_TX_FLAGS_VLAN_SHIFT;
6455 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6458 skb_tx_timestamp(skb);
6460 #ifdef CONFIG_IXGBE_PTP
6461 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6462 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6463 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6467 #ifdef CONFIG_PCI_IOV
6469 * Use the l2switch_enable flag - would be false if the DMA
6470 * Tx switch had been disabled.
6472 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6473 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6476 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6477 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6478 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6479 (skb->priority != TC_PRIO_CONTROL))) {
6480 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6481 tx_flags |= (skb->priority & 0x7) <<
6482 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6483 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6484 struct vlan_ethhdr *vhdr;
6485 if (skb_header_cloned(skb) &&
6486 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6488 vhdr = (struct vlan_ethhdr *)skb->data;
6489 vhdr->h_vlan_TCI = htons(tx_flags >>
6490 IXGBE_TX_FLAGS_VLAN_SHIFT);
6492 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6496 /* record initial flags and protocol */
6497 first->tx_flags = tx_flags;
6498 first->protocol = protocol;
6501 /* setup tx offload for FCoE */
6502 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6503 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6504 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6511 #endif /* IXGBE_FCOE */
6512 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6516 ixgbe_tx_csum(tx_ring, first);
6518 /* add the ATR filter if ATR is on */
6519 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6520 ixgbe_atr(tx_ring, first);
6524 #endif /* IXGBE_FCOE */
6525 ixgbe_tx_map(tx_ring, first, hdr_len);
6527 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6529 return NETDEV_TX_OK;
6532 dev_kfree_skb_any(first->skb);
6535 return NETDEV_TX_OK;
6538 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6539 struct net_device *netdev)
6541 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6542 struct ixgbe_ring *tx_ring;
6545 * The minimum packet size for olinfo paylen is 17 so pad the skb
6546 * in order to meet this minimum size requirement.
6548 if (unlikely(skb->len < 17)) {
6549 if (skb_pad(skb, 17 - skb->len))
6550 return NETDEV_TX_OK;
6552 skb_set_tail_pointer(skb, 17);
6555 tx_ring = adapter->tx_ring[skb->queue_mapping];
6556 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6560 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6561 * @netdev: network interface device structure
6562 * @p: pointer to an address structure
6564 * Returns 0 on success, negative on failure
6566 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6569 struct ixgbe_hw *hw = &adapter->hw;
6570 struct sockaddr *addr = p;
6572 if (!is_valid_ether_addr(addr->sa_data))
6573 return -EADDRNOTAVAIL;
6575 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6576 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6578 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6584 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6586 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6587 struct ixgbe_hw *hw = &adapter->hw;
6591 if (prtad != hw->phy.mdio.prtad)
6593 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6599 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6600 u16 addr, u16 value)
6602 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6603 struct ixgbe_hw *hw = &adapter->hw;
6605 if (prtad != hw->phy.mdio.prtad)
6607 return hw->phy.ops.write_reg(hw, addr, devad, value);
6610 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6612 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6615 #ifdef CONFIG_IXGBE_PTP
6617 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6620 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6625 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6627 * @netdev: network interface device structure
6629 * Returns non-zero on failure
6631 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6634 struct ixgbe_adapter *adapter = netdev_priv(dev);
6635 struct ixgbe_hw *hw = &adapter->hw;
6637 if (is_valid_ether_addr(hw->mac.san_addr)) {
6639 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6642 /* update SAN MAC vmdq pool selection */
6643 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6649 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6651 * @netdev: network interface device structure
6653 * Returns non-zero on failure
6655 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6658 struct ixgbe_adapter *adapter = netdev_priv(dev);
6659 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6661 if (is_valid_ether_addr(mac->san_addr)) {
6663 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6669 #ifdef CONFIG_NET_POLL_CONTROLLER
6671 * Polling 'interrupt' - used by things like netconsole to send skbs
6672 * without having to re-enable interrupts. It's not called while
6673 * the interrupt routine is executing.
6675 static void ixgbe_netpoll(struct net_device *netdev)
6677 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6680 /* if interface is down do nothing */
6681 if (test_bit(__IXGBE_DOWN, &adapter->state))
6684 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6685 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6686 for (i = 0; i < adapter->num_q_vectors; i++)
6687 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6689 ixgbe_intr(adapter->pdev->irq, netdev);
6691 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6695 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6696 struct rtnl_link_stats64 *stats)
6698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6702 for (i = 0; i < adapter->num_rx_queues; i++) {
6703 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6709 start = u64_stats_fetch_begin_bh(&ring->syncp);
6710 packets = ring->stats.packets;
6711 bytes = ring->stats.bytes;
6712 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6713 stats->rx_packets += packets;
6714 stats->rx_bytes += bytes;
6718 for (i = 0; i < adapter->num_tx_queues; i++) {
6719 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6725 start = u64_stats_fetch_begin_bh(&ring->syncp);
6726 packets = ring->stats.packets;
6727 bytes = ring->stats.bytes;
6728 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6729 stats->tx_packets += packets;
6730 stats->tx_bytes += bytes;
6734 /* following stats updated by ixgbe_watchdog_task() */
6735 stats->multicast = netdev->stats.multicast;
6736 stats->rx_errors = netdev->stats.rx_errors;
6737 stats->rx_length_errors = netdev->stats.rx_length_errors;
6738 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6739 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6743 #ifdef CONFIG_IXGBE_DCB
6745 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6746 * @adapter: pointer to ixgbe_adapter
6747 * @tc: number of traffic classes currently enabled
6749 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6750 * 802.1Q priority maps to a packet buffer that exists.
6752 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6754 struct ixgbe_hw *hw = &adapter->hw;
6758 /* 82598 have a static priority to TC mapping that can not
6759 * be changed so no validation is needed.
6761 if (hw->mac.type == ixgbe_mac_82598EB)
6764 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6767 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6768 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6770 /* If up2tc is out of bounds default to zero */
6772 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6776 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6782 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6783 * @adapter: Pointer to adapter struct
6785 * Populate the netdev user priority to tc map
6787 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6789 struct net_device *dev = adapter->netdev;
6790 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6791 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6794 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6797 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6798 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6800 tc = ets->prio_tc[prio];
6802 netdev_set_prio_tc_map(dev, prio, tc);
6807 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6809 * @netdev: net device to configure
6810 * @tc: number of traffic classes to enable
6812 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6814 struct ixgbe_adapter *adapter = netdev_priv(dev);
6815 struct ixgbe_hw *hw = &adapter->hw;
6817 /* Hardware supports up to 8 traffic classes */
6818 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6819 (hw->mac.type == ixgbe_mac_82598EB &&
6820 tc < MAX_TRAFFIC_CLASS))
6823 /* Hardware has to reinitialize queues and interrupts to
6824 * match packet buffer alignment. Unfortunately, the
6825 * hardware is not flexible enough to do this dynamically.
6827 if (netif_running(dev))
6829 ixgbe_clear_interrupt_scheme(adapter);
6832 netdev_set_num_tc(dev, tc);
6833 ixgbe_set_prio_tc_map(adapter);
6835 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6837 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6838 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6839 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6842 netdev_reset_tc(dev);
6844 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6845 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6847 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6849 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6850 adapter->dcb_cfg.pfc_mode_enable = false;
6853 ixgbe_init_interrupt_scheme(adapter);
6854 ixgbe_validate_rtr(adapter, tc);
6855 if (netif_running(dev))
6861 #endif /* CONFIG_IXGBE_DCB */
6862 void ixgbe_do_reset(struct net_device *netdev)
6864 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6866 if (netif_running(netdev))
6867 ixgbe_reinit_locked(adapter);
6869 ixgbe_reset(adapter);
6872 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6873 netdev_features_t features)
6875 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6877 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6878 if (!(features & NETIF_F_RXCSUM))
6879 features &= ~NETIF_F_LRO;
6881 /* Turn off LRO if not RSC capable */
6882 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6883 features &= ~NETIF_F_LRO;
6888 static int ixgbe_set_features(struct net_device *netdev,
6889 netdev_features_t features)
6891 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6892 netdev_features_t changed = netdev->features ^ features;
6893 bool need_reset = false;
6895 /* Make sure RSC matches LRO, reset if change */
6896 if (!(features & NETIF_F_LRO)) {
6897 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6899 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6900 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6901 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6902 if (adapter->rx_itr_setting == 1 ||
6903 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6904 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6906 } else if ((changed ^ features) & NETIF_F_LRO) {
6907 e_info(probe, "rx-usecs set too low, "
6913 * Check if Flow Director n-tuple support was enabled or disabled. If
6914 * the state changed, we need to reset.
6916 switch (features & NETIF_F_NTUPLE) {
6917 case NETIF_F_NTUPLE:
6918 /* turn off ATR, enable perfect filters and reset */
6919 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6922 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6923 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6926 /* turn off perfect filters, enable ATR and reset */
6927 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6930 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6932 /* We cannot enable ATR if SR-IOV is enabled */
6933 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6936 /* We cannot enable ATR if we have 2 or more traffic classes */
6937 if (netdev_get_num_tc(netdev) > 1)
6940 /* We cannot enable ATR if RSS is disabled */
6941 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6944 /* A sample rate of 0 indicates ATR disabled */
6945 if (!adapter->atr_sample_rate)
6948 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6952 if (features & NETIF_F_HW_VLAN_RX)
6953 ixgbe_vlan_strip_enable(adapter);
6955 ixgbe_vlan_strip_disable(adapter);
6957 if (changed & NETIF_F_RXALL)
6960 netdev->features = features;
6962 ixgbe_do_reset(netdev);
6967 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6968 struct net_device *dev,
6969 const unsigned char *addr,
6972 struct ixgbe_adapter *adapter = netdev_priv(dev);
6975 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6978 if (ndm->ndm_state & NUD_PERMANENT) {
6979 pr_info("%s: FDB only supports static addresses\n",
6984 if (is_unicast_ether_addr(addr) || is_link_local(addr)) {
6985 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6987 if (netdev_uc_count(dev) < rar_uc_entries)
6988 err = dev_uc_add_excl(dev, addr);
6991 } else if (is_multicast_ether_addr(addr)) {
6992 err = dev_mc_add_excl(dev, addr);
6997 /* Only return duplicate errors if NLM_F_EXCL is set */
6998 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7004 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
7005 struct net_device *dev,
7006 const unsigned char *addr)
7008 struct ixgbe_adapter *adapter = netdev_priv(dev);
7009 int err = -EOPNOTSUPP;
7011 if (ndm->ndm_state & NUD_PERMANENT) {
7012 pr_info("%s: FDB only supports static addresses\n",
7017 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7018 if (is_unicast_ether_addr(addr))
7019 err = dev_uc_del(dev, addr);
7020 else if (is_multicast_ether_addr(addr))
7021 err = dev_mc_del(dev, addr);
7029 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7030 struct netlink_callback *cb,
7031 struct net_device *dev,
7034 struct ixgbe_adapter *adapter = netdev_priv(dev);
7036 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7037 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7042 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7043 struct nlmsghdr *nlh)
7045 struct ixgbe_adapter *adapter = netdev_priv(dev);
7046 struct nlattr *attr, *br_spec;
7049 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7052 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7054 nla_for_each_nested(attr, br_spec, rem) {
7058 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7061 mode = nla_get_u16(attr);
7062 if (mode == BRIDGE_MODE_VEPA)
7064 else if (mode == BRIDGE_MODE_VEB)
7065 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7069 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7071 e_info(drv, "enabling bridge mode: %s\n",
7072 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7078 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7079 struct net_device *dev)
7081 struct ixgbe_adapter *adapter = netdev_priv(dev);
7084 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7087 if (IXGBE_READ_REG(&adapter->hw, IXGBE_PFDTXGSWC) & 1)
7088 mode = BRIDGE_MODE_VEB;
7090 mode = BRIDGE_MODE_VEPA;
7092 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7095 static const struct net_device_ops ixgbe_netdev_ops = {
7096 .ndo_open = ixgbe_open,
7097 .ndo_stop = ixgbe_close,
7098 .ndo_start_xmit = ixgbe_xmit_frame,
7099 .ndo_select_queue = ixgbe_select_queue,
7100 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7101 .ndo_validate_addr = eth_validate_addr,
7102 .ndo_set_mac_address = ixgbe_set_mac,
7103 .ndo_change_mtu = ixgbe_change_mtu,
7104 .ndo_tx_timeout = ixgbe_tx_timeout,
7105 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7106 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7107 .ndo_do_ioctl = ixgbe_ioctl,
7108 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7109 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7110 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7111 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7112 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7113 .ndo_get_stats64 = ixgbe_get_stats64,
7114 #ifdef CONFIG_IXGBE_DCB
7115 .ndo_setup_tc = ixgbe_setup_tc,
7117 #ifdef CONFIG_NET_POLL_CONTROLLER
7118 .ndo_poll_controller = ixgbe_netpoll,
7121 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7122 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7123 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7124 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7125 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7126 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7127 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7128 #endif /* IXGBE_FCOE */
7129 .ndo_set_features = ixgbe_set_features,
7130 .ndo_fix_features = ixgbe_fix_features,
7131 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7132 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7133 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
7134 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7135 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7139 * ixgbe_wol_supported - Check whether device supports WoL
7140 * @hw: hw specific details
7141 * @device_id: the device ID
7142 * @subdev_id: the subsystem device ID
7144 * This function is used by probe and ethtool to determine
7145 * which devices have WoL support
7148 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7151 struct ixgbe_hw *hw = &adapter->hw;
7152 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7153 int is_wol_supported = 0;
7155 switch (device_id) {
7156 case IXGBE_DEV_ID_82599_SFP:
7157 /* Only these subdevices could supports WOL */
7158 switch (subdevice_id) {
7159 case IXGBE_SUBDEV_ID_82599_560FLR:
7160 /* only support first port */
7161 if (hw->bus.func != 0)
7163 case IXGBE_SUBDEV_ID_82599_SFP:
7164 case IXGBE_SUBDEV_ID_82599_RNDC:
7165 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7166 is_wol_supported = 1;
7170 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7171 /* All except this subdevice support WOL */
7172 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7173 is_wol_supported = 1;
7175 case IXGBE_DEV_ID_82599_KX4:
7176 is_wol_supported = 1;
7178 case IXGBE_DEV_ID_X540T:
7179 case IXGBE_DEV_ID_X540T1:
7180 /* check eeprom to see if enabled wol */
7181 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7182 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7183 (hw->bus.func == 0))) {
7184 is_wol_supported = 1;
7189 return is_wol_supported;
7193 * ixgbe_probe - Device Initialization Routine
7194 * @pdev: PCI device information struct
7195 * @ent: entry in ixgbe_pci_tbl
7197 * Returns 0 on success, negative on failure
7199 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7200 * The OS initialization, configuring of the adapter private structure,
7201 * and a hardware reset occur.
7203 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7204 const struct pci_device_id *ent)
7206 struct net_device *netdev;
7207 struct ixgbe_adapter *adapter = NULL;
7208 struct ixgbe_hw *hw;
7209 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7210 static int cards_found;
7211 int i, err, pci_using_dac;
7212 u8 part_str[IXGBE_PBANUM_LENGTH];
7213 unsigned int indices = num_possible_cpus();
7214 unsigned int dcb_max = 0;
7220 /* Catch broken hardware that put the wrong VF device ID in
7221 * the PCIe SR-IOV capability.
7223 if (pdev->is_virtfn) {
7224 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7225 pci_name(pdev), pdev->vendor, pdev->device);
7229 err = pci_enable_device_mem(pdev);
7233 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7234 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7237 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7239 err = dma_set_coherent_mask(&pdev->dev,
7243 "No usable DMA configuration, aborting\n");
7250 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7251 IORESOURCE_MEM), ixgbe_driver_name);
7254 "pci_request_selected_regions failed 0x%x\n", err);
7258 pci_enable_pcie_error_reporting(pdev);
7260 pci_set_master(pdev);
7261 pci_save_state(pdev);
7263 #ifdef CONFIG_IXGBE_DCB
7264 if (ii->mac == ixgbe_mac_82598EB)
7265 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7266 IXGBE_MAX_RSS_INDICES);
7268 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7269 IXGBE_MAX_FDIR_INDICES);
7272 if (ii->mac == ixgbe_mac_82598EB)
7273 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7275 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7278 indices += min_t(unsigned int, num_possible_cpus(),
7279 IXGBE_MAX_FCOE_INDICES);
7281 indices = max_t(unsigned int, dcb_max, indices);
7282 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7285 goto err_alloc_etherdev;
7288 SET_NETDEV_DEV(netdev, &pdev->dev);
7290 adapter = netdev_priv(netdev);
7291 pci_set_drvdata(pdev, adapter);
7293 adapter->netdev = netdev;
7294 adapter->pdev = pdev;
7297 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7299 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7300 pci_resource_len(pdev, 0));
7306 netdev->netdev_ops = &ixgbe_netdev_ops;
7307 ixgbe_set_ethtool_ops(netdev);
7308 netdev->watchdog_timeo = 5 * HZ;
7309 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7311 adapter->bd_number = cards_found;
7314 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7315 hw->mac.type = ii->mac;
7318 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7319 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7320 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7321 if (!(eec & (1 << 8)))
7322 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7325 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7326 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7327 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7328 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7329 hw->phy.mdio.mmds = 0;
7330 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7331 hw->phy.mdio.dev = netdev;
7332 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7333 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7335 ii->get_invariants(hw);
7337 /* setup the private structure */
7338 err = ixgbe_sw_init(adapter);
7342 /* Make it possible the adapter to be woken up via WOL */
7343 switch (adapter->hw.mac.type) {
7344 case ixgbe_mac_82599EB:
7345 case ixgbe_mac_X540:
7346 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7353 * If there is a fan on this device and it has failed log the
7356 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7357 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7358 if (esdp & IXGBE_ESDP_SDP1)
7359 e_crit(probe, "Fan has stopped, replace the adapter\n");
7362 if (allow_unsupported_sfp)
7363 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7365 /* reset_hw fills in the perm_addr as well */
7366 hw->phy.reset_if_overtemp = true;
7367 err = hw->mac.ops.reset_hw(hw);
7368 hw->phy.reset_if_overtemp = false;
7369 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7370 hw->mac.type == ixgbe_mac_82598EB) {
7372 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7373 e_dev_err("failed to load because an unsupported SFP+ "
7374 "module type was detected.\n");
7375 e_dev_err("Reload the driver after installing a supported "
7379 e_dev_err("HW Init failed: %d\n", err);
7383 #ifdef CONFIG_PCI_IOV
7384 ixgbe_enable_sriov(adapter, ii);
7387 netdev->features = NETIF_F_SG |
7390 NETIF_F_HW_VLAN_TX |
7391 NETIF_F_HW_VLAN_RX |
7392 NETIF_F_HW_VLAN_FILTER |
7398 netdev->hw_features = netdev->features;
7400 switch (adapter->hw.mac.type) {
7401 case ixgbe_mac_82599EB:
7402 case ixgbe_mac_X540:
7403 netdev->features |= NETIF_F_SCTP_CSUM;
7404 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7411 netdev->hw_features |= NETIF_F_RXALL;
7413 netdev->vlan_features |= NETIF_F_TSO;
7414 netdev->vlan_features |= NETIF_F_TSO6;
7415 netdev->vlan_features |= NETIF_F_IP_CSUM;
7416 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7417 netdev->vlan_features |= NETIF_F_SG;
7419 netdev->priv_flags |= IFF_UNICAST_FLT;
7420 netdev->priv_flags |= IFF_SUPP_NOFCS;
7422 #ifdef CONFIG_IXGBE_DCB
7423 netdev->dcbnl_ops = &dcbnl_ops;
7427 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7428 if (hw->mac.ops.get_device_caps) {
7429 hw->mac.ops.get_device_caps(hw, &device_caps);
7430 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7431 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7434 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7436 netdev->features |= NETIF_F_FSO |
7439 netdev->vlan_features |= NETIF_F_FSO |
7443 #endif /* IXGBE_FCOE */
7444 if (pci_using_dac) {
7445 netdev->features |= NETIF_F_HIGHDMA;
7446 netdev->vlan_features |= NETIF_F_HIGHDMA;
7449 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7450 netdev->hw_features |= NETIF_F_LRO;
7451 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7452 netdev->features |= NETIF_F_LRO;
7454 /* make sure the EEPROM is good */
7455 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7456 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7461 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7462 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7464 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7465 e_dev_err("invalid MAC address\n");
7470 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7471 (unsigned long) adapter);
7473 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7474 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7476 err = ixgbe_init_interrupt_scheme(adapter);
7480 /* WOL not supported for all devices */
7482 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7483 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7484 adapter->wol = IXGBE_WUFC_MAG;
7486 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7488 /* save off EEPROM version number */
7489 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7490 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7492 /* pick up the PCI bus settings for reporting later */
7493 hw->mac.ops.get_bus_info(hw);
7495 /* print bus type/speed/width info */
7496 e_dev_info("(PCI Express:%s:%s) %pM\n",
7497 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7498 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7500 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7501 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7502 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7506 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7508 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7509 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7510 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7511 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7514 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7515 hw->mac.type, hw->phy.type, part_str);
7517 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7518 e_dev_warn("PCI-Express bandwidth available for this card is "
7519 "not sufficient for optimal performance.\n");
7520 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7524 /* reset the hardware with the new settings */
7525 err = hw->mac.ops.start_hw(hw);
7526 if (err == IXGBE_ERR_EEPROM_VERSION) {
7527 /* We are running on a pre-production device, log a warning */
7528 e_dev_warn("This device is a pre-production adapter/LOM. "
7529 "Please be aware there may be issues associated "
7530 "with your hardware. If you are experiencing "
7531 "problems please contact your Intel or hardware "
7532 "representative who provided you with this "
7535 strcpy(netdev->name, "eth%d");
7536 err = register_netdev(netdev);
7540 /* power down the optics for 82599 SFP+ fiber */
7541 if (hw->mac.ops.disable_tx_laser)
7542 hw->mac.ops.disable_tx_laser(hw);
7544 /* carrier off reporting is important to ethtool even BEFORE open */
7545 netif_carrier_off(netdev);
7547 #ifdef CONFIG_IXGBE_DCA
7548 if (dca_add_requester(&pdev->dev) == 0) {
7549 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7550 ixgbe_setup_dca(adapter);
7553 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7554 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7555 for (i = 0; i < adapter->num_vfs; i++)
7556 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7559 /* firmware requires driver version to be 0xFFFFFFFF
7560 * since os does not support feature
7562 if (hw->mac.ops.set_fw_drv_ver)
7563 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7566 /* add san mac addr to netdev */
7567 ixgbe_add_sanmac_netdev(netdev);
7569 e_dev_info("%s\n", ixgbe_default_device_descr);
7572 #ifdef CONFIG_IXGBE_HWMON
7573 if (ixgbe_sysfs_init(adapter))
7574 e_err(probe, "failed to allocate sysfs resources\n");
7575 #endif /* CONFIG_IXGBE_HWMON */
7577 #ifdef CONFIG_DEBUG_FS
7578 ixgbe_dbg_adapter_init(adapter);
7579 #endif /* CONFIG_DEBUG_FS */
7584 ixgbe_release_hw_control(adapter);
7585 ixgbe_clear_interrupt_scheme(adapter);
7587 ixgbe_disable_sriov(adapter);
7588 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7589 iounmap(hw->hw_addr);
7591 free_netdev(netdev);
7593 pci_release_selected_regions(pdev,
7594 pci_select_bars(pdev, IORESOURCE_MEM));
7597 pci_disable_device(pdev);
7602 * ixgbe_remove - Device Removal Routine
7603 * @pdev: PCI device information struct
7605 * ixgbe_remove is called by the PCI subsystem to alert the driver
7606 * that it should release a PCI device. The could be caused by a
7607 * Hot-Plug event, or because the driver is going to be removed from
7610 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7612 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7613 struct net_device *netdev = adapter->netdev;
7615 #ifdef CONFIG_DEBUG_FS
7616 ixgbe_dbg_adapter_exit(adapter);
7617 #endif /*CONFIG_DEBUG_FS */
7619 set_bit(__IXGBE_DOWN, &adapter->state);
7620 cancel_work_sync(&adapter->service_task);
7623 #ifdef CONFIG_IXGBE_DCA
7624 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7625 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7626 dca_remove_requester(&pdev->dev);
7627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7631 #ifdef CONFIG_IXGBE_HWMON
7632 ixgbe_sysfs_exit(adapter);
7633 #endif /* CONFIG_IXGBE_HWMON */
7635 /* remove the added san mac */
7636 ixgbe_del_sanmac_netdev(netdev);
7638 if (netdev->reg_state == NETREG_REGISTERED)
7639 unregister_netdev(netdev);
7641 ixgbe_disable_sriov(adapter);
7643 ixgbe_clear_interrupt_scheme(adapter);
7645 ixgbe_release_hw_control(adapter);
7648 kfree(adapter->ixgbe_ieee_pfc);
7649 kfree(adapter->ixgbe_ieee_ets);
7652 iounmap(adapter->hw.hw_addr);
7653 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7656 e_dev_info("complete\n");
7658 free_netdev(netdev);
7660 pci_disable_pcie_error_reporting(pdev);
7662 pci_disable_device(pdev);
7666 * ixgbe_io_error_detected - called when PCI error is detected
7667 * @pdev: Pointer to PCI device
7668 * @state: The current pci connection state
7670 * This function is called after a PCI bus error affecting
7671 * this device has been detected.
7673 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7674 pci_channel_state_t state)
7676 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7677 struct net_device *netdev = adapter->netdev;
7679 #ifdef CONFIG_PCI_IOV
7680 struct pci_dev *bdev, *vfdev;
7681 u32 dw0, dw1, dw2, dw3;
7683 u16 req_id, pf_func;
7685 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7686 adapter->num_vfs == 0)
7687 goto skip_bad_vf_detection;
7689 bdev = pdev->bus->self;
7690 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7691 bdev = bdev->bus->self;
7694 goto skip_bad_vf_detection;
7696 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7698 goto skip_bad_vf_detection;
7700 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7701 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7702 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7703 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7706 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7707 if (!(req_id & 0x0080))
7708 goto skip_bad_vf_detection;
7710 pf_func = req_id & 0x01;
7711 if ((pf_func & 1) == (pdev->devfn & 1)) {
7712 unsigned int device_id;
7714 vf = (req_id & 0x7F) >> 1;
7715 e_dev_err("VF %d has caused a PCIe error\n", vf);
7716 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7717 "%8.8x\tdw3: %8.8x\n",
7718 dw0, dw1, dw2, dw3);
7719 switch (adapter->hw.mac.type) {
7720 case ixgbe_mac_82599EB:
7721 device_id = IXGBE_82599_VF_DEVICE_ID;
7723 case ixgbe_mac_X540:
7724 device_id = IXGBE_X540_VF_DEVICE_ID;
7731 /* Find the pci device of the offending VF */
7732 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7734 if (vfdev->devfn == (req_id & 0xFF))
7736 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7740 * There's a slim chance the VF could have been hot plugged,
7741 * so if it is no longer present we don't need to issue the
7742 * VFLR. Just clean up the AER in that case.
7745 e_dev_err("Issuing VFLR to VF %d\n", vf);
7746 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7749 pci_cleanup_aer_uncorrect_error_status(pdev);
7753 * Even though the error may have occurred on the other port
7754 * we still need to increment the vf error reference count for
7755 * both ports because the I/O resume function will be called
7758 adapter->vferr_refcount++;
7760 return PCI_ERS_RESULT_RECOVERED;
7762 skip_bad_vf_detection:
7763 #endif /* CONFIG_PCI_IOV */
7764 netif_device_detach(netdev);
7766 if (state == pci_channel_io_perm_failure)
7767 return PCI_ERS_RESULT_DISCONNECT;
7769 if (netif_running(netdev))
7770 ixgbe_down(adapter);
7771 pci_disable_device(pdev);
7773 /* Request a slot reset. */
7774 return PCI_ERS_RESULT_NEED_RESET;
7778 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7779 * @pdev: Pointer to PCI device
7781 * Restart the card from scratch, as if from a cold-boot.
7783 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7785 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7786 pci_ers_result_t result;
7789 if (pci_enable_device_mem(pdev)) {
7790 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7791 result = PCI_ERS_RESULT_DISCONNECT;
7793 pci_set_master(pdev);
7794 pci_restore_state(pdev);
7795 pci_save_state(pdev);
7797 pci_wake_from_d3(pdev, false);
7799 ixgbe_reset(adapter);
7800 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7801 result = PCI_ERS_RESULT_RECOVERED;
7804 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7806 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7807 "failed 0x%0x\n", err);
7808 /* non-fatal, continue */
7815 * ixgbe_io_resume - called when traffic can start flowing again.
7816 * @pdev: Pointer to PCI device
7818 * This callback is called when the error recovery driver tells us that
7819 * its OK to resume normal operation.
7821 static void ixgbe_io_resume(struct pci_dev *pdev)
7823 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7824 struct net_device *netdev = adapter->netdev;
7826 #ifdef CONFIG_PCI_IOV
7827 if (adapter->vferr_refcount) {
7828 e_info(drv, "Resuming after VF err\n");
7829 adapter->vferr_refcount--;
7834 if (netif_running(netdev))
7837 netif_device_attach(netdev);
7840 static const struct pci_error_handlers ixgbe_err_handler = {
7841 .error_detected = ixgbe_io_error_detected,
7842 .slot_reset = ixgbe_io_slot_reset,
7843 .resume = ixgbe_io_resume,
7846 static struct pci_driver ixgbe_driver = {
7847 .name = ixgbe_driver_name,
7848 .id_table = ixgbe_pci_tbl,
7849 .probe = ixgbe_probe,
7850 .remove = __devexit_p(ixgbe_remove),
7852 .suspend = ixgbe_suspend,
7853 .resume = ixgbe_resume,
7855 .shutdown = ixgbe_shutdown,
7856 .err_handler = &ixgbe_err_handler
7860 * ixgbe_init_module - Driver Registration Routine
7862 * ixgbe_init_module is the first routine called when the driver is
7863 * loaded. All it does is register with the PCI subsystem.
7865 static int __init ixgbe_init_module(void)
7868 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7869 pr_info("%s\n", ixgbe_copyright);
7871 #ifdef CONFIG_DEBUG_FS
7873 #endif /* CONFIG_DEBUG_FS */
7875 #ifdef CONFIG_IXGBE_DCA
7876 dca_register_notify(&dca_notifier);
7879 ret = pci_register_driver(&ixgbe_driver);
7883 module_init(ixgbe_init_module);
7886 * ixgbe_exit_module - Driver Exit Cleanup Routine
7888 * ixgbe_exit_module is called just before the driver is removed
7891 static void __exit ixgbe_exit_module(void)
7893 #ifdef CONFIG_IXGBE_DCA
7894 dca_unregister_notify(&dca_notifier);
7896 pci_unregister_driver(&ixgbe_driver);
7898 #ifdef CONFIG_DEBUG_FS
7900 #endif /* CONFIG_DEBUG_FS */
7902 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7905 #ifdef CONFIG_IXGBE_DCA
7906 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7911 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7912 __ixgbe_notify_dca);
7914 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7917 #endif /* CONFIG_IXGBE_DCA */
7919 module_exit(ixgbe_exit_module);