1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
62 static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
68 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
69 __stringify(BUILD) "-k"
70 const char ixgbe_driver_version[] = DRV_VERSION;
71 static const char ixgbe_copyright[] =
72 "Copyright (c) 1999-2012 Intel Corporation.";
74 static const struct ixgbe_info *ixgbe_info_tbl[] = {
75 [board_82598] = &ixgbe_82598_info,
76 [board_82599] = &ixgbe_82599_info,
77 [board_X540] = &ixgbe_X540_info,
80 /* ixgbe_pci_tbl - PCI Device ID Table
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
88 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 /* required last entry */
120 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122 #ifdef CONFIG_IXGBE_DCA
123 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
125 static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
132 #ifdef CONFIG_PCI_IOV
133 static unsigned int max_vfs;
134 module_param(max_vfs, uint, 0);
135 MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function");
137 #endif /* CONFIG_PCI_IOV */
139 static unsigned int allow_unsupported_sfp;
140 module_param(allow_unsupported_sfp, uint, 0);
141 MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
145 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
146 MODULE_LICENSE("GPL");
147 MODULE_VERSION(DRV_VERSION);
149 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
151 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
153 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
154 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
155 schedule_work(&adapter->service_task);
158 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
160 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
162 /* flush memory to make sure state is correct before next watchdog */
163 smp_mb__before_clear_bit();
164 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
167 struct ixgbe_reg_info {
172 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
174 /* General Registers */
175 {IXGBE_CTRL, "CTRL"},
176 {IXGBE_STATUS, "STATUS"},
177 {IXGBE_CTRL_EXT, "CTRL_EXT"},
179 /* Interrupt Registers */
180 {IXGBE_EICR, "EICR"},
183 {IXGBE_SRRCTL(0), "SRRCTL"},
184 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
185 {IXGBE_RDLEN(0), "RDLEN"},
186 {IXGBE_RDH(0), "RDH"},
187 {IXGBE_RDT(0), "RDT"},
188 {IXGBE_RXDCTL(0), "RXDCTL"},
189 {IXGBE_RDBAL(0), "RDBAL"},
190 {IXGBE_RDBAH(0), "RDBAH"},
193 {IXGBE_TDBAL(0), "TDBAL"},
194 {IXGBE_TDBAH(0), "TDBAH"},
195 {IXGBE_TDLEN(0), "TDLEN"},
196 {IXGBE_TDH(0), "TDH"},
197 {IXGBE_TDT(0), "TDT"},
198 {IXGBE_TXDCTL(0), "TXDCTL"},
200 /* List Terminator */
206 * ixgbe_regdump - register printout routine
208 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
214 switch (reginfo->ofs) {
215 case IXGBE_SRRCTL(0):
216 for (i = 0; i < 64; i++)
217 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
219 case IXGBE_DCA_RXCTRL(0):
220 for (i = 0; i < 64; i++)
221 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
224 for (i = 0; i < 64; i++)
225 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
228 for (i = 0; i < 64; i++)
229 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
232 for (i = 0; i < 64; i++)
233 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
235 case IXGBE_RXDCTL(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
260 for (i = 0; i < 64; i++)
261 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
264 for (i = 0; i < 64; i++)
265 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
267 case IXGBE_TXDCTL(0):
268 for (i = 0; i < 64; i++)
269 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
272 pr_info("%-15s %08x\n", reginfo->name,
273 IXGBE_READ_REG(hw, reginfo->ofs));
277 for (i = 0; i < 8; i++) {
278 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
279 pr_err("%-15s", rname);
280 for (j = 0; j < 8; j++)
281 pr_cont(" %08x", regs[i*8+j]);
288 * ixgbe_dump - Print registers, tx-rings and rx-rings
290 static void ixgbe_dump(struct ixgbe_adapter *adapter)
292 struct net_device *netdev = adapter->netdev;
293 struct ixgbe_hw *hw = &adapter->hw;
294 struct ixgbe_reg_info *reginfo;
296 struct ixgbe_ring *tx_ring;
297 struct ixgbe_tx_buffer *tx_buffer;
298 union ixgbe_adv_tx_desc *tx_desc;
299 struct my_u0 { u64 a; u64 b; } *u0;
300 struct ixgbe_ring *rx_ring;
301 union ixgbe_adv_rx_desc *rx_desc;
302 struct ixgbe_rx_buffer *rx_buffer_info;
306 if (!netif_msg_hw(adapter))
309 /* Print netdevice Info */
311 dev_info(&adapter->pdev->dev, "Net device Info\n");
312 pr_info("Device Name state "
313 "trans_start last_rx\n");
314 pr_info("%-15s %016lX %016lX %016lX\n",
321 /* Print Registers */
322 dev_info(&adapter->pdev->dev, "Register Dump\n");
323 pr_info(" Register Name Value\n");
324 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
325 reginfo->name; reginfo++) {
326 ixgbe_regdump(hw, reginfo);
329 /* Print TX Ring Summary */
330 if (!netdev || !netif_running(netdev))
333 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
334 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
335 for (n = 0; n < adapter->num_tx_queues; n++) {
336 tx_ring = adapter->tx_ring[n];
337 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
338 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
339 n, tx_ring->next_to_use, tx_ring->next_to_clean,
340 (u64)dma_unmap_addr(tx_buffer, dma),
341 dma_unmap_len(tx_buffer, len),
342 tx_buffer->next_to_watch,
343 (u64)tx_buffer->time_stamp);
347 if (!netif_msg_tx_done(adapter))
348 goto rx_ring_summary;
350 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
352 /* Transmit Descriptor Formats
354 * Advanced Transmit Descriptor
355 * +--------------------------------------------------------------+
356 * 0 | Buffer Address [63:0] |
357 * +--------------------------------------------------------------+
358 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
359 * +--------------------------------------------------------------+
360 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
363 for (n = 0; n < adapter->num_tx_queues; n++) {
364 tx_ring = adapter->tx_ring[n];
365 pr_info("------------------------------------\n");
366 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
367 pr_info("------------------------------------\n");
368 pr_info("T [desc] [address 63:0 ] "
369 "[PlPOIdStDDt Ln] [bi->dma ] "
370 "leng ntw timestamp bi->skb\n");
372 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
373 tx_desc = IXGBE_TX_DESC(tx_ring, i);
374 tx_buffer = &tx_ring->tx_buffer_info[i];
375 u0 = (struct my_u0 *)tx_desc;
376 pr_info("T [0x%03X] %016llX %016llX %016llX"
377 " %04X %p %016llX %p", i,
380 (u64)dma_unmap_addr(tx_buffer, dma),
381 dma_unmap_len(tx_buffer, len),
382 tx_buffer->next_to_watch,
383 (u64)tx_buffer->time_stamp,
385 if (i == tx_ring->next_to_use &&
386 i == tx_ring->next_to_clean)
388 else if (i == tx_ring->next_to_use)
390 else if (i == tx_ring->next_to_clean)
395 if (netif_msg_pktdata(adapter) &&
396 dma_unmap_len(tx_buffer, len) != 0)
397 print_hex_dump(KERN_INFO, "",
398 DUMP_PREFIX_ADDRESS, 16, 1,
399 phys_to_virt(dma_unmap_addr(tx_buffer,
401 dma_unmap_len(tx_buffer, len),
406 /* Print RX Rings Summary */
408 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
409 pr_info("Queue [NTU] [NTC]\n");
410 for (n = 0; n < adapter->num_rx_queues; n++) {
411 rx_ring = adapter->rx_ring[n];
412 pr_info("%5d %5X %5X\n",
413 n, rx_ring->next_to_use, rx_ring->next_to_clean);
417 if (!netif_msg_rx_status(adapter))
420 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
422 /* Advanced Receive Descriptor (Read) Format
424 * +-----------------------------------------------------+
425 * 0 | Packet Buffer Address [63:1] |A0/NSE|
426 * +----------------------------------------------+------+
427 * 8 | Header Buffer Address [63:1] | DD |
428 * +-----------------------------------------------------+
431 * Advanced Receive Descriptor (Write-Back) Format
433 * 63 48 47 32 31 30 21 20 16 15 4 3 0
434 * +------------------------------------------------------+
435 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
436 * | Checksum Ident | | | | Type | Type |
437 * +------------------------------------------------------+
438 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
439 * +------------------------------------------------------+
440 * 63 48 47 32 31 20 19 0
442 for (n = 0; n < adapter->num_rx_queues; n++) {
443 rx_ring = adapter->rx_ring[n];
444 pr_info("------------------------------------\n");
445 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
446 pr_info("------------------------------------\n");
447 pr_info("R [desc] [ PktBuf A0] "
448 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
449 "<-- Adv Rx Read format\n");
450 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
451 "[vl er S cks ln] ---------------- [bi->skb] "
452 "<-- Adv Rx Write-Back format\n");
454 for (i = 0; i < rx_ring->count; i++) {
455 rx_buffer_info = &rx_ring->rx_buffer_info[i];
456 rx_desc = IXGBE_RX_DESC(rx_ring, i);
457 u0 = (struct my_u0 *)rx_desc;
458 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
459 if (staterr & IXGBE_RXD_STAT_DD) {
460 /* Descriptor Done */
461 pr_info("RWB[0x%03X] %016llX "
462 "%016llX ---------------- %p", i,
465 rx_buffer_info->skb);
467 pr_info("R [0x%03X] %016llX "
468 "%016llX %016llX %p", i,
471 (u64)rx_buffer_info->dma,
472 rx_buffer_info->skb);
474 if (netif_msg_pktdata(adapter)) {
475 print_hex_dump(KERN_INFO, "",
476 DUMP_PREFIX_ADDRESS, 16, 1,
477 phys_to_virt(rx_buffer_info->dma),
478 ixgbe_rx_bufsz(rx_ring), true);
482 if (i == rx_ring->next_to_use)
484 else if (i == rx_ring->next_to_clean)
496 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500 /* Let firmware take over control of h/w */
501 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
502 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
503 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
506 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510 /* Let firmware know the driver has taken over */
511 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
512 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
513 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
517 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
518 * @adapter: pointer to adapter struct
519 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
520 * @queue: queue to map the corresponding interrupt to
521 * @msix_vector: the vector to map to the corresponding queue
524 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
525 u8 queue, u8 msix_vector)
528 struct ixgbe_hw *hw = &adapter->hw;
529 switch (hw->mac.type) {
530 case ixgbe_mac_82598EB:
531 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
534 index = (((direction * 64) + queue) >> 2) & 0x1F;
535 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
536 ivar &= ~(0xFF << (8 * (queue & 0x3)));
537 ivar |= (msix_vector << (8 * (queue & 0x3)));
538 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
540 case ixgbe_mac_82599EB:
542 if (direction == -1) {
544 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
545 index = ((queue & 1) * 8);
546 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
547 ivar &= ~(0xFF << index);
548 ivar |= (msix_vector << index);
549 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
552 /* tx or rx causes */
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 index = ((16 * (queue & 1)) + (8 * direction));
555 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
556 ivar &= ~(0xFF << index);
557 ivar |= (msix_vector << index);
558 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
566 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
571 switch (adapter->hw.mac.type) {
572 case ixgbe_mac_82598EB:
573 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
576 case ixgbe_mac_82599EB:
578 mask = (qmask & 0xFFFFFFFF);
579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
580 mask = (qmask >> 32);
581 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
588 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
589 struct ixgbe_tx_buffer *tx_buffer)
591 if (tx_buffer->skb) {
592 dev_kfree_skb_any(tx_buffer->skb);
593 if (dma_unmap_len(tx_buffer, len))
594 dma_unmap_single(ring->dev,
595 dma_unmap_addr(tx_buffer, dma),
596 dma_unmap_len(tx_buffer, len),
598 } else if (dma_unmap_len(tx_buffer, len)) {
599 dma_unmap_page(ring->dev,
600 dma_unmap_addr(tx_buffer, dma),
601 dma_unmap_len(tx_buffer, len),
604 tx_buffer->next_to_watch = NULL;
605 tx_buffer->skb = NULL;
606 dma_unmap_len_set(tx_buffer, len, 0);
607 /* tx_buffer must be completely set up in the transmit path */
610 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
612 struct ixgbe_hw *hw = &adapter->hw;
613 struct ixgbe_hw_stats *hwstats = &adapter->stats;
618 if ((hw->fc.current_mode == ixgbe_fc_full) ||
619 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
620 switch (hw->mac.type) {
621 case ixgbe_mac_82598EB:
622 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
625 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
627 hwstats->lxoffrxc += data;
629 /* refill credits (no tx hang) if we received xoff */
633 for (i = 0; i < adapter->num_tx_queues; i++)
634 clear_bit(__IXGBE_HANG_CHECK_ARMED,
635 &adapter->tx_ring[i]->state);
637 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
640 /* update stats for each tc, only valid with PFC enabled */
641 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
642 switch (hw->mac.type) {
643 case ixgbe_mac_82598EB:
644 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
647 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
649 hwstats->pxoffrxc[i] += xoff[i];
652 /* disarm tx queues that have received xoff frames */
653 for (i = 0; i < adapter->num_tx_queues; i++) {
654 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
655 u8 tc = tx_ring->dcb_tc;
658 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
662 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
664 return ring->stats.packets;
667 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
669 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
670 struct ixgbe_hw *hw = &adapter->hw;
672 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
673 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
676 return (head < tail) ?
677 tail - head : (tail + ring->count - head);
682 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
684 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
685 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
686 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
689 clear_check_for_tx_hang(tx_ring);
692 * Check for a hung queue, but be thorough. This verifies
693 * that a transmit has been completed since the previous
694 * check AND there is at least one packet pending. The
695 * ARMED bit is set to indicate a potential hang. The
696 * bit is cleared if a pause frame is received to remove
697 * false hang detection due to PFC or 802.3x frames. By
698 * requiring this to fail twice we avoid races with
699 * pfc clearing the ARMED bit and conditions where we
700 * run the check_tx_hang logic with a transmit completion
701 * pending but without time to complete it yet.
703 if ((tx_done_old == tx_done) && tx_pending) {
704 /* make sure it is true for two checks in a row */
705 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
708 /* update completed stats and continue */
709 tx_ring->tx_stats.tx_done_old = tx_done;
710 /* reset the countdown */
711 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
718 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
719 * @adapter: driver private struct
721 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
724 /* Do the reset outside of interrupt context */
725 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
726 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
727 ixgbe_service_event_schedule(adapter);
732 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
733 * @q_vector: structure containing interrupt and ring information
734 * @tx_ring: tx ring to clean
736 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
737 struct ixgbe_ring *tx_ring)
739 struct ixgbe_adapter *adapter = q_vector->adapter;
740 struct ixgbe_tx_buffer *tx_buffer;
741 union ixgbe_adv_tx_desc *tx_desc;
742 unsigned int total_bytes = 0, total_packets = 0;
743 unsigned int budget = q_vector->tx.work_limit;
744 unsigned int i = tx_ring->next_to_clean;
746 if (test_bit(__IXGBE_DOWN, &adapter->state))
749 tx_buffer = &tx_ring->tx_buffer_info[i];
750 tx_desc = IXGBE_TX_DESC(tx_ring, i);
754 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
756 /* if next_to_watch is not set then there is no work pending */
760 /* prevent any other reads prior to eop_desc */
763 /* if DD is not set pending work has not been completed */
764 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
767 /* clear next_to_watch to prevent false hangs */
768 tx_buffer->next_to_watch = NULL;
770 /* update the statistics for this packet */
771 total_bytes += tx_buffer->bytecount;
772 total_packets += tx_buffer->gso_segs;
775 dev_kfree_skb_any(tx_buffer->skb);
777 /* unmap skb header data */
778 dma_unmap_single(tx_ring->dev,
779 dma_unmap_addr(tx_buffer, dma),
780 dma_unmap_len(tx_buffer, len),
783 /* clear tx_buffer data */
784 tx_buffer->skb = NULL;
785 dma_unmap_len_set(tx_buffer, len, 0);
787 /* unmap remaining buffers */
788 while (tx_desc != eop_desc) {
794 tx_buffer = tx_ring->tx_buffer_info;
795 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
798 /* unmap any remaining paged data */
799 if (dma_unmap_len(tx_buffer, len)) {
800 dma_unmap_page(tx_ring->dev,
801 dma_unmap_addr(tx_buffer, dma),
802 dma_unmap_len(tx_buffer, len),
804 dma_unmap_len_set(tx_buffer, len, 0);
808 /* move us one more past the eop_desc for start of next pkt */
814 tx_buffer = tx_ring->tx_buffer_info;
815 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
818 /* issue prefetch for next Tx descriptor */
821 /* update budget accounting */
823 } while (likely(budget));
826 tx_ring->next_to_clean = i;
827 u64_stats_update_begin(&tx_ring->syncp);
828 tx_ring->stats.bytes += total_bytes;
829 tx_ring->stats.packets += total_packets;
830 u64_stats_update_end(&tx_ring->syncp);
831 q_vector->tx.total_bytes += total_bytes;
832 q_vector->tx.total_packets += total_packets;
834 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
835 /* schedule immediate reset if we believe we hung */
836 struct ixgbe_hw *hw = &adapter->hw;
837 e_err(drv, "Detected Tx Unit Hang\n"
839 " TDH, TDT <%x>, <%x>\n"
840 " next_to_use <%x>\n"
841 " next_to_clean <%x>\n"
842 "tx_buffer_info[next_to_clean]\n"
843 " time_stamp <%lx>\n"
845 tx_ring->queue_index,
846 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
847 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
848 tx_ring->next_to_use, i,
849 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
851 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
854 "tx hang %d detected on queue %d, resetting adapter\n",
855 adapter->tx_timeout_count + 1, tx_ring->queue_index);
857 /* schedule immediate reset if we believe we hung */
858 ixgbe_tx_timeout_reset(adapter);
860 /* the adapter is about to reset, no point in enabling stuff */
864 netdev_tx_completed_queue(txring_txq(tx_ring),
865 total_packets, total_bytes);
867 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
868 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
869 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
870 /* Make sure that anybody stopping the queue after this
871 * sees the new next_to_clean.
874 if (__netif_subqueue_stopped(tx_ring->netdev,
875 tx_ring->queue_index)
876 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
877 netif_wake_subqueue(tx_ring->netdev,
878 tx_ring->queue_index);
879 ++tx_ring->tx_stats.restart_queue;
886 #ifdef CONFIG_IXGBE_DCA
887 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
888 struct ixgbe_ring *tx_ring,
891 struct ixgbe_hw *hw = &adapter->hw;
892 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
895 switch (hw->mac.type) {
896 case ixgbe_mac_82598EB:
897 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
899 case ixgbe_mac_82599EB:
901 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
902 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
905 /* for unknown hardware do not write register */
910 * We can enable relaxed ordering for reads, but not writes when
911 * DCA is enabled. This is due to a known issue in some chipsets
912 * which will cause the DCA tag to be cleared.
914 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
915 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
916 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
918 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
921 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
922 struct ixgbe_ring *rx_ring,
925 struct ixgbe_hw *hw = &adapter->hw;
926 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
927 u8 reg_idx = rx_ring->reg_idx;
930 switch (hw->mac.type) {
931 case ixgbe_mac_82599EB:
933 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
940 * We can enable relaxed ordering for reads, but not writes when
941 * DCA is enabled. This is due to a known issue in some chipsets
942 * which will cause the DCA tag to be cleared.
944 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
945 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
946 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
948 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
951 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct ixgbe_ring *ring;
957 if (q_vector->cpu == cpu)
960 ixgbe_for_each_ring(ring, q_vector->tx)
961 ixgbe_update_tx_dca(adapter, ring, cpu);
963 ixgbe_for_each_ring(ring, q_vector->rx)
964 ixgbe_update_rx_dca(adapter, ring, cpu);
971 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
976 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
979 /* always use CB2 mode, difference is masked in the CB driver */
980 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
982 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
983 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
987 for (i = 0; i < num_q_vectors; i++) {
988 adapter->q_vector[i]->cpu = -1;
989 ixgbe_update_dca(adapter->q_vector[i]);
993 static int __ixgbe_notify_dca(struct device *dev, void *data)
995 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
996 unsigned long event = *(unsigned long *)data;
998 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1002 case DCA_PROVIDER_ADD:
1003 /* if we're already enabled, don't do it again */
1004 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1006 if (dca_add_requester(dev) == 0) {
1007 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1008 ixgbe_setup_dca(adapter);
1011 /* Fall Through since DCA is disabled. */
1012 case DCA_PROVIDER_REMOVE:
1013 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1014 dca_remove_requester(dev);
1015 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1016 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1024 #endif /* CONFIG_IXGBE_DCA */
1025 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1026 union ixgbe_adv_rx_desc *rx_desc,
1027 struct sk_buff *skb)
1029 if (ring->netdev->features & NETIF_F_RXHASH)
1030 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1035 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1036 * @adapter: address of board private structure
1037 * @rx_desc: advanced rx descriptor
1039 * Returns : true if it is FCoE pkt
1041 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1042 union ixgbe_adv_rx_desc *rx_desc)
1044 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1046 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1047 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1048 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1049 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1052 #endif /* IXGBE_FCOE */
1054 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1055 * @ring: structure containing ring specific data
1056 * @rx_desc: current Rx descriptor being processed
1057 * @skb: skb currently being received and modified
1059 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1060 union ixgbe_adv_rx_desc *rx_desc,
1061 struct sk_buff *skb)
1063 skb_checksum_none_assert(skb);
1065 /* Rx csum disabled */
1066 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1069 /* if IP and error */
1070 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1071 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1072 ring->rx_stats.csum_err++;
1076 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1079 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1080 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1083 * 82599 errata, UDP frames with a 0 checksum can be marked as
1086 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1087 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1090 ring->rx_stats.csum_err++;
1094 /* It must be a TCP or UDP packet with a valid checksum */
1095 skb->ip_summed = CHECKSUM_UNNECESSARY;
1098 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1100 rx_ring->next_to_use = val;
1102 /* update next to alloc since we have filled the ring */
1103 rx_ring->next_to_alloc = val;
1105 * Force memory writes to complete before letting h/w
1106 * know there are new descriptors to fetch. (Only
1107 * applicable for weak-ordered memory model archs,
1111 writel(val, rx_ring->tail);
1114 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1115 struct ixgbe_rx_buffer *bi)
1117 struct page *page = bi->page;
1118 dma_addr_t dma = bi->dma;
1120 /* since we are recycling buffers we should seldom need to alloc */
1124 /* alloc new page for storage */
1125 if (likely(!page)) {
1126 page = alloc_pages(GFP_ATOMIC | __GFP_COLD,
1127 ixgbe_rx_pg_order(rx_ring));
1128 if (unlikely(!page)) {
1129 rx_ring->rx_stats.alloc_rx_page_failed++;
1135 /* map page for use */
1136 dma = dma_map_page(rx_ring->dev, page, 0,
1137 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1140 * if mapping failed free memory back to system since
1141 * there isn't much point in holding memory we can't use
1143 if (dma_mapping_error(rx_ring->dev, dma)) {
1147 rx_ring->rx_stats.alloc_rx_page_failed++;
1152 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1158 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1159 * @rx_ring: ring to place buffers on
1160 * @cleaned_count: number of buffers to replace
1162 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1164 union ixgbe_adv_rx_desc *rx_desc;
1165 struct ixgbe_rx_buffer *bi;
1166 u16 i = rx_ring->next_to_use;
1172 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1173 bi = &rx_ring->rx_buffer_info[i];
1174 i -= rx_ring->count;
1177 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1181 * Refresh the desc even if buffer_addrs didn't change
1182 * because each write-back erases this info.
1184 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1190 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1191 bi = rx_ring->rx_buffer_info;
1192 i -= rx_ring->count;
1195 /* clear the hdr_addr for the next_to_use descriptor */
1196 rx_desc->read.hdr_addr = 0;
1199 } while (cleaned_count);
1201 i += rx_ring->count;
1203 if (rx_ring->next_to_use != i)
1204 ixgbe_release_rx_desc(rx_ring, i);
1208 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1209 * @data: pointer to the start of the headers
1210 * @max_len: total length of section to find headers in
1212 * This function is meant to determine the length of headers that will
1213 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1214 * motivation of doing this is to only perform one pull for IPv4 TCP
1215 * packets so that we can do basic things like calculating the gso_size
1216 * based on the average data per packet.
1218 static unsigned int ixgbe_get_headlen(unsigned char *data,
1219 unsigned int max_len)
1222 unsigned char *network;
1225 struct vlan_hdr *vlan;
1230 u8 nexthdr = 0; /* default to not TCP */
1233 /* this should never happen, but better safe than sorry */
1234 if (max_len < ETH_HLEN)
1237 /* initialize network frame pointer */
1240 /* set first protocol and move network header forward */
1241 protocol = hdr.eth->h_proto;
1242 hdr.network += ETH_HLEN;
1244 /* handle any vlan tag if present */
1245 if (protocol == __constant_htons(ETH_P_8021Q)) {
1246 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1249 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1250 hdr.network += VLAN_HLEN;
1253 /* handle L3 protocols */
1254 if (protocol == __constant_htons(ETH_P_IP)) {
1255 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1258 /* access ihl as a u8 to avoid unaligned access on ia64 */
1259 hlen = (hdr.network[0] & 0x0F) << 2;
1261 /* verify hlen meets minimum size requirements */
1262 if (hlen < sizeof(struct iphdr))
1263 return hdr.network - data;
1265 /* record next protocol */
1266 nexthdr = hdr.ipv4->protocol;
1267 hdr.network += hlen;
1269 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1270 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1272 hdr.network += FCOE_HEADER_LEN;
1275 return hdr.network - data;
1278 /* finally sort out TCP */
1279 if (nexthdr == IPPROTO_TCP) {
1280 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1283 /* access doff as a u8 to avoid unaligned access on ia64 */
1284 hlen = (hdr.network[12] & 0xF0) >> 2;
1286 /* verify hlen meets minimum size requirements */
1287 if (hlen < sizeof(struct tcphdr))
1288 return hdr.network - data;
1290 hdr.network += hlen;
1294 * If everything has gone correctly hdr.network should be the
1295 * data section of the packet and will be the end of the header.
1296 * If not then it probably represents the end of the last recognized
1299 if ((hdr.network - data) < max_len)
1300 return hdr.network - data;
1305 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1306 union ixgbe_adv_rx_desc *rx_desc,
1307 struct sk_buff *skb)
1312 if (!ring_is_rsc_enabled(rx_ring))
1315 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1316 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1318 /* If this is an RSC frame rsc_cnt should be non-zero */
1322 rsc_cnt = le32_to_cpu(rsc_enabled);
1323 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1325 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1328 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1329 struct sk_buff *skb)
1331 u16 hdr_len = skb_headlen(skb);
1333 /* set gso_size to avoid messing up TCP MSS */
1334 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1335 IXGBE_CB(skb)->append_cnt);
1338 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1339 struct sk_buff *skb)
1341 /* if append_cnt is 0 then frame is not RSC */
1342 if (!IXGBE_CB(skb)->append_cnt)
1345 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1346 rx_ring->rx_stats.rsc_flush++;
1348 ixgbe_set_rsc_gso_size(rx_ring, skb);
1350 /* gso_size is computed using append_cnt so always clear it last */
1351 IXGBE_CB(skb)->append_cnt = 0;
1355 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1356 * @rx_ring: rx descriptor ring packet is being transacted on
1357 * @rx_desc: pointer to the EOP Rx descriptor
1358 * @skb: pointer to current skb being populated
1360 * This function checks the ring, descriptor, and packet information in
1361 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1362 * other fields within the skb.
1364 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1365 union ixgbe_adv_rx_desc *rx_desc,
1366 struct sk_buff *skb)
1368 ixgbe_update_rsc_stats(rx_ring, skb);
1370 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1372 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1374 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1375 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1376 __vlan_hwaccel_put_tag(skb, vid);
1379 skb_record_rx_queue(skb, rx_ring->queue_index);
1381 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1384 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1385 struct sk_buff *skb)
1387 struct ixgbe_adapter *adapter = q_vector->adapter;
1389 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1390 napi_gro_receive(&q_vector->napi, skb);
1396 * ixgbe_is_non_eop - process handling of non-EOP buffers
1397 * @rx_ring: Rx ring being processed
1398 * @rx_desc: Rx descriptor for current buffer
1399 * @skb: Current socket buffer containing buffer in progress
1401 * This function updates next to clean. If the buffer is an EOP buffer
1402 * this function exits returning false, otherwise it will place the
1403 * sk_buff in the next buffer to be chained and return true indicating
1404 * that this is in fact a non-EOP buffer.
1406 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1407 union ixgbe_adv_rx_desc *rx_desc,
1408 struct sk_buff *skb)
1410 u32 ntc = rx_ring->next_to_clean + 1;
1412 /* fetch, update, and store next to clean */
1413 ntc = (ntc < rx_ring->count) ? ntc : 0;
1414 rx_ring->next_to_clean = ntc;
1416 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1418 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1421 /* append_cnt indicates packet is RSC, if so fetch nextp */
1422 if (IXGBE_CB(skb)->append_cnt) {
1423 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1424 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1425 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1428 /* place skb in next buffer to be received */
1429 rx_ring->rx_buffer_info[ntc].skb = skb;
1430 rx_ring->rx_stats.non_eop_descs++;
1436 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1437 * @rx_ring: rx descriptor ring packet is being transacted on
1438 * @rx_desc: pointer to the EOP Rx descriptor
1439 * @skb: pointer to current skb being fixed
1441 * Check for corrupted packet headers caused by senders on the local L2
1442 * embedded NIC switch not setting up their Tx Descriptors right. These
1443 * should be very rare.
1445 * Also address the case where we are pulling data in on pages only
1446 * and as such no data is present in the skb header.
1448 * In addition if skb is not at least 60 bytes we need to pad it so that
1449 * it is large enough to qualify as a valid Ethernet frame.
1451 * Returns true if an error was encountered and skb was freed.
1453 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1454 union ixgbe_adv_rx_desc *rx_desc,
1455 struct sk_buff *skb)
1457 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1458 struct net_device *netdev = rx_ring->netdev;
1460 unsigned int pull_len;
1462 /* if the page was released unmap it, else just sync our portion */
1463 if (unlikely(IXGBE_CB(skb)->page_released)) {
1464 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1465 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1466 IXGBE_CB(skb)->page_released = false;
1468 dma_sync_single_range_for_cpu(rx_ring->dev,
1471 ixgbe_rx_bufsz(rx_ring),
1474 IXGBE_CB(skb)->dma = 0;
1476 /* verify that the packet does not have any known errors */
1477 if (unlikely(ixgbe_test_staterr(rx_desc,
1478 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1479 !(netdev->features & NETIF_F_RXALL))) {
1480 dev_kfree_skb_any(skb);
1485 * it is valid to use page_address instead of kmap since we are
1486 * working with pages allocated out of the lomem pool per
1487 * alloc_page(GFP_ATOMIC)
1489 va = skb_frag_address(frag);
1492 * we need the header to contain the greater of either ETH_HLEN or
1493 * 60 bytes if the skb->len is less than 60 for skb_pad.
1495 pull_len = skb_frag_size(frag);
1497 pull_len = ixgbe_get_headlen(va, pull_len);
1499 /* align pull length to size of long to optimize memcpy performance */
1500 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1502 /* update all of the pointers */
1503 skb_frag_size_sub(frag, pull_len);
1504 frag->page_offset += pull_len;
1505 skb->data_len -= pull_len;
1506 skb->tail += pull_len;
1509 * if we sucked the frag empty then we should free it,
1510 * if there are other frags here something is screwed up in hardware
1512 if (skb_frag_size(frag) == 0) {
1513 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1514 skb_shinfo(skb)->nr_frags = 0;
1515 __skb_frag_unref(frag);
1516 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1519 /* if skb_pad returns an error the skb was freed */
1520 if (unlikely(skb->len < 60)) {
1521 int pad_len = 60 - skb->len;
1523 if (skb_pad(skb, pad_len))
1525 __skb_put(skb, pad_len);
1532 * ixgbe_can_reuse_page - determine if we can reuse a page
1533 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1535 * Returns true if page can be reused in another Rx buffer
1537 static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1539 struct page *page = rx_buffer->page;
1541 /* if we are only owner of page and it is local we can reuse it */
1542 return likely(page_count(page) == 1) &&
1543 likely(page_to_nid(page) == numa_node_id());
1547 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1548 * @rx_ring: rx descriptor ring to store buffers on
1549 * @old_buff: donor buffer to have page reused
1551 * Syncronizes page for reuse by the adapter
1553 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1554 struct ixgbe_rx_buffer *old_buff)
1556 struct ixgbe_rx_buffer *new_buff;
1557 u16 nta = rx_ring->next_to_alloc;
1558 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1560 new_buff = &rx_ring->rx_buffer_info[nta];
1562 /* update, and store next to alloc */
1564 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1566 /* transfer page from old buffer to new buffer */
1567 new_buff->page = old_buff->page;
1568 new_buff->dma = old_buff->dma;
1570 /* flip page offset to other buffer and store to new_buff */
1571 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1573 /* sync the buffer for use by the device */
1574 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1575 new_buff->page_offset, bufsz,
1578 /* bump ref count on page before it is given to the stack */
1579 get_page(new_buff->page);
1583 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1584 * @rx_ring: rx descriptor ring to transact packets on
1585 * @rx_buffer: buffer containing page to add
1586 * @rx_desc: descriptor containing length of buffer written by hardware
1587 * @skb: sk_buff to place the data into
1589 * This function is based on skb_add_rx_frag. I would have used that
1590 * function however it doesn't handle the truesize case correctly since we
1591 * are allocating more memory than might be used for a single receive.
1593 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1594 struct ixgbe_rx_buffer *rx_buffer,
1595 struct sk_buff *skb, int size)
1597 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1598 rx_buffer->page, rx_buffer->page_offset,
1601 skb->data_len += size;
1602 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1606 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1607 * @q_vector: structure containing interrupt and ring information
1608 * @rx_ring: rx descriptor ring to transact packets on
1609 * @budget: Total limit on number of packets to process
1611 * This function provides a "bounce buffer" approach to Rx interrupt
1612 * processing. The advantage to this is that on systems that have
1613 * expensive overhead for IOMMU access this provides a means of avoiding
1614 * it by maintaining the mapping of the page to the syste.
1616 * Returns true if all work is completed without reaching budget
1618 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1619 struct ixgbe_ring *rx_ring,
1622 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1624 struct ixgbe_adapter *adapter = q_vector->adapter;
1626 #endif /* IXGBE_FCOE */
1627 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1630 struct ixgbe_rx_buffer *rx_buffer;
1631 union ixgbe_adv_rx_desc *rx_desc;
1632 struct sk_buff *skb;
1636 /* return some buffers to hardware, one at a time is too slow */
1637 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1638 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1642 ntc = rx_ring->next_to_clean;
1643 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1644 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1646 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1650 * This memory barrier is needed to keep us from reading
1651 * any other fields out of the rx_desc until we know the
1652 * RXD_STAT_DD bit is set
1656 page = rx_buffer->page;
1659 skb = rx_buffer->skb;
1662 void *page_addr = page_address(page) +
1663 rx_buffer->page_offset;
1665 /* prefetch first cache line of first page */
1666 prefetch(page_addr);
1667 #if L1_CACHE_BYTES < 128
1668 prefetch(page_addr + L1_CACHE_BYTES);
1671 /* allocate a skb to store the frags */
1672 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1674 if (unlikely(!skb)) {
1675 rx_ring->rx_stats.alloc_rx_buff_failed++;
1680 * we will be copying header into skb->data in
1681 * pskb_may_pull so it is in our interest to prefetch
1682 * it now to avoid a possible cache miss
1684 prefetchw(skb->data);
1687 * Delay unmapping of the first packet. It carries the
1688 * header information, HW may still access the header
1689 * after the writeback. Only unmap it when EOP is
1692 IXGBE_CB(skb)->dma = rx_buffer->dma;
1694 /* we are reusing so sync this buffer for CPU use */
1695 dma_sync_single_range_for_cpu(rx_ring->dev,
1697 rx_buffer->page_offset,
1698 ixgbe_rx_bufsz(rx_ring),
1702 /* pull page into skb */
1703 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1704 le16_to_cpu(rx_desc->wb.upper.length));
1706 if (ixgbe_can_reuse_page(rx_buffer)) {
1707 /* hand second half of page back to the ring */
1708 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1709 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1710 /* the page has been released from the ring */
1711 IXGBE_CB(skb)->page_released = true;
1713 /* we are not reusing the buffer so unmap it */
1714 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1715 ixgbe_rx_pg_size(rx_ring),
1719 /* clear contents of buffer_info */
1720 rx_buffer->skb = NULL;
1722 rx_buffer->page = NULL;
1724 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1728 /* place incomplete frames back on ring for completion */
1729 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1732 /* verify the packet layout is correct */
1733 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1736 /* probably a little skewed due to removing CRC */
1737 total_rx_bytes += skb->len;
1740 /* populate checksum, timestamp, VLAN, and protocol */
1741 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1744 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1745 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1746 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1748 dev_kfree_skb_any(skb);
1753 #endif /* IXGBE_FCOE */
1754 ixgbe_rx_skb(q_vector, skb);
1756 /* update budget accounting */
1758 } while (likely(budget));
1761 /* include DDPed FCoE data */
1762 if (ddp_bytes > 0) {
1765 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1766 sizeof(struct fc_frame_header) -
1767 sizeof(struct fcoe_crc_eof);
1770 total_rx_bytes += ddp_bytes;
1771 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1774 #endif /* IXGBE_FCOE */
1775 u64_stats_update_begin(&rx_ring->syncp);
1776 rx_ring->stats.packets += total_rx_packets;
1777 rx_ring->stats.bytes += total_rx_bytes;
1778 u64_stats_update_end(&rx_ring->syncp);
1779 q_vector->rx.total_packets += total_rx_packets;
1780 q_vector->rx.total_bytes += total_rx_bytes;
1783 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1789 * ixgbe_configure_msix - Configure MSI-X hardware
1790 * @adapter: board private structure
1792 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1795 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1797 struct ixgbe_q_vector *q_vector;
1798 int q_vectors, v_idx;
1801 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1803 /* Populate MSIX to EITR Select */
1804 if (adapter->num_vfs > 32) {
1805 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1806 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1810 * Populate the IVAR table and set the ITR values to the
1811 * corresponding register.
1813 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1814 struct ixgbe_ring *ring;
1815 q_vector = adapter->q_vector[v_idx];
1817 ixgbe_for_each_ring(ring, q_vector->rx)
1818 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1820 ixgbe_for_each_ring(ring, q_vector->tx)
1821 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1823 if (q_vector->tx.ring && !q_vector->rx.ring) {
1824 /* tx only vector */
1825 if (adapter->tx_itr_setting == 1)
1826 q_vector->itr = IXGBE_10K_ITR;
1828 q_vector->itr = adapter->tx_itr_setting;
1830 /* rx or rx/tx vector */
1831 if (adapter->rx_itr_setting == 1)
1832 q_vector->itr = IXGBE_20K_ITR;
1834 q_vector->itr = adapter->rx_itr_setting;
1837 ixgbe_write_eitr(q_vector);
1840 switch (adapter->hw.mac.type) {
1841 case ixgbe_mac_82598EB:
1842 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1845 case ixgbe_mac_82599EB:
1846 case ixgbe_mac_X540:
1847 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1852 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1854 /* set up to autoclear timer, and the vectors */
1855 mask = IXGBE_EIMS_ENABLE_MASK;
1856 mask &= ~(IXGBE_EIMS_OTHER |
1857 IXGBE_EIMS_MAILBOX |
1860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1863 enum latency_range {
1867 latency_invalid = 255
1871 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1872 * @q_vector: structure containing interrupt and ring information
1873 * @ring_container: structure containing ring performance data
1875 * Stores a new ITR value based on packets and byte
1876 * counts during the last interrupt. The advantage of per interrupt
1877 * computation is faster updates and more accurate ITR for the current
1878 * traffic pattern. Constants in this function were computed
1879 * based on theoretical maximum wire speed and thresholds were set based
1880 * on testing data as well as attempting to minimize response time
1881 * while increasing bulk throughput.
1882 * this functionality is controlled by the InterruptThrottleRate module
1883 * parameter (see ixgbe_param.c)
1885 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1886 struct ixgbe_ring_container *ring_container)
1888 int bytes = ring_container->total_bytes;
1889 int packets = ring_container->total_packets;
1892 u8 itr_setting = ring_container->itr;
1897 /* simple throttlerate management
1898 * 0-10MB/s lowest (100000 ints/s)
1899 * 10-20MB/s low (20000 ints/s)
1900 * 20-1249MB/s bulk (8000 ints/s)
1902 /* what was last interrupt timeslice? */
1903 timepassed_us = q_vector->itr >> 2;
1904 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1906 switch (itr_setting) {
1907 case lowest_latency:
1908 if (bytes_perint > 10)
1909 itr_setting = low_latency;
1912 if (bytes_perint > 20)
1913 itr_setting = bulk_latency;
1914 else if (bytes_perint <= 10)
1915 itr_setting = lowest_latency;
1918 if (bytes_perint <= 20)
1919 itr_setting = low_latency;
1923 /* clear work counters since we have the values we need */
1924 ring_container->total_bytes = 0;
1925 ring_container->total_packets = 0;
1927 /* write updated itr to ring container */
1928 ring_container->itr = itr_setting;
1932 * ixgbe_write_eitr - write EITR register in hardware specific way
1933 * @q_vector: structure containing interrupt and ring information
1935 * This function is made to be called by ethtool and by the driver
1936 * when it needs to update EITR registers at runtime. Hardware
1937 * specific quirks/differences are taken care of here.
1939 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1941 struct ixgbe_adapter *adapter = q_vector->adapter;
1942 struct ixgbe_hw *hw = &adapter->hw;
1943 int v_idx = q_vector->v_idx;
1944 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
1946 switch (adapter->hw.mac.type) {
1947 case ixgbe_mac_82598EB:
1948 /* must write high and low 16 bits to reset counter */
1949 itr_reg |= (itr_reg << 16);
1951 case ixgbe_mac_82599EB:
1952 case ixgbe_mac_X540:
1954 * set the WDIS bit to not clear the timer bits and cause an
1955 * immediate assertion of the interrupt
1957 itr_reg |= IXGBE_EITR_CNT_WDIS;
1962 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1965 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1967 u32 new_itr = q_vector->itr;
1970 ixgbe_update_itr(q_vector, &q_vector->tx);
1971 ixgbe_update_itr(q_vector, &q_vector->rx);
1973 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1975 switch (current_itr) {
1976 /* counts and packets in update_itr are dependent on these numbers */
1977 case lowest_latency:
1978 new_itr = IXGBE_100K_ITR;
1981 new_itr = IXGBE_20K_ITR;
1984 new_itr = IXGBE_8K_ITR;
1990 if (new_itr != q_vector->itr) {
1991 /* do an exponential smoothing */
1992 new_itr = (10 * new_itr * q_vector->itr) /
1993 ((9 * new_itr) + q_vector->itr);
1995 /* save the algorithm value here */
1996 q_vector->itr = new_itr;
1998 ixgbe_write_eitr(q_vector);
2003 * ixgbe_check_overtemp_subtask - check for over temperature
2004 * @adapter: pointer to adapter
2006 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2008 struct ixgbe_hw *hw = &adapter->hw;
2009 u32 eicr = adapter->interrupt_event;
2011 if (test_bit(__IXGBE_DOWN, &adapter->state))
2014 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2015 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2018 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2020 switch (hw->device_id) {
2021 case IXGBE_DEV_ID_82599_T3_LOM:
2023 * Since the warning interrupt is for both ports
2024 * we don't have to check if:
2025 * - This interrupt wasn't for our port.
2026 * - We may have missed the interrupt so always have to
2027 * check if we got a LSC
2029 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2030 !(eicr & IXGBE_EICR_LSC))
2033 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2035 bool link_up = false;
2037 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2043 /* Check if this is not due to overtemp */
2044 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2049 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2054 "Network adapter has been stopped because it has over heated. "
2055 "Restart the computer. If the problem persists, "
2056 "power off the system and replace the adapter\n");
2058 adapter->interrupt_event = 0;
2061 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2063 struct ixgbe_hw *hw = &adapter->hw;
2065 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2066 (eicr & IXGBE_EICR_GPI_SDP1)) {
2067 e_crit(probe, "Fan has stopped, replace the adapter\n");
2068 /* write to clear the interrupt */
2069 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2073 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2075 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2078 switch (adapter->hw.mac.type) {
2079 case ixgbe_mac_82599EB:
2081 * Need to check link state so complete overtemp check
2084 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2085 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2086 adapter->interrupt_event = eicr;
2087 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2088 ixgbe_service_event_schedule(adapter);
2092 case ixgbe_mac_X540:
2093 if (!(eicr & IXGBE_EICR_TS))
2101 "Network adapter has been stopped because it has over heated. "
2102 "Restart the computer. If the problem persists, "
2103 "power off the system and replace the adapter\n");
2106 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2108 struct ixgbe_hw *hw = &adapter->hw;
2110 if (eicr & IXGBE_EICR_GPI_SDP2) {
2111 /* Clear the interrupt */
2112 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2113 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2114 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2115 ixgbe_service_event_schedule(adapter);
2119 if (eicr & IXGBE_EICR_GPI_SDP1) {
2120 /* Clear the interrupt */
2121 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2122 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2123 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2124 ixgbe_service_event_schedule(adapter);
2129 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2131 struct ixgbe_hw *hw = &adapter->hw;
2134 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2135 adapter->link_check_timeout = jiffies;
2136 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2137 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2138 IXGBE_WRITE_FLUSH(hw);
2139 ixgbe_service_event_schedule(adapter);
2143 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2147 struct ixgbe_hw *hw = &adapter->hw;
2149 switch (hw->mac.type) {
2150 case ixgbe_mac_82598EB:
2151 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2152 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2154 case ixgbe_mac_82599EB:
2155 case ixgbe_mac_X540:
2156 mask = (qmask & 0xFFFFFFFF);
2158 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2159 mask = (qmask >> 32);
2161 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2166 /* skip the flush */
2169 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2173 struct ixgbe_hw *hw = &adapter->hw;
2175 switch (hw->mac.type) {
2176 case ixgbe_mac_82598EB:
2177 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2178 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2180 case ixgbe_mac_82599EB:
2181 case ixgbe_mac_X540:
2182 mask = (qmask & 0xFFFFFFFF);
2184 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2185 mask = (qmask >> 32);
2187 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2192 /* skip the flush */
2196 * ixgbe_irq_enable - Enable default interrupt generation settings
2197 * @adapter: board private structure
2199 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2202 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2204 /* don't reenable LSC while waiting for link */
2205 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2206 mask &= ~IXGBE_EIMS_LSC;
2208 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2209 switch (adapter->hw.mac.type) {
2210 case ixgbe_mac_82599EB:
2211 mask |= IXGBE_EIMS_GPI_SDP0;
2213 case ixgbe_mac_X540:
2214 mask |= IXGBE_EIMS_TS;
2219 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2220 mask |= IXGBE_EIMS_GPI_SDP1;
2221 switch (adapter->hw.mac.type) {
2222 case ixgbe_mac_82599EB:
2223 mask |= IXGBE_EIMS_GPI_SDP1;
2224 mask |= IXGBE_EIMS_GPI_SDP2;
2225 case ixgbe_mac_X540:
2226 mask |= IXGBE_EIMS_ECC;
2227 mask |= IXGBE_EIMS_MAILBOX;
2232 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2233 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2234 mask |= IXGBE_EIMS_FLOW_DIR;
2236 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2238 ixgbe_irq_enable_queues(adapter, ~0);
2240 IXGBE_WRITE_FLUSH(&adapter->hw);
2243 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2245 struct ixgbe_adapter *adapter = data;
2246 struct ixgbe_hw *hw = &adapter->hw;
2250 * Workaround for Silicon errata. Use clear-by-write instead
2251 * of clear-by-read. Reading with EICS will return the
2252 * interrupt causes without clearing, which later be done
2253 * with the write to EICR.
2255 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2256 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2258 if (eicr & IXGBE_EICR_LSC)
2259 ixgbe_check_lsc(adapter);
2261 if (eicr & IXGBE_EICR_MAILBOX)
2262 ixgbe_msg_task(adapter);
2264 switch (hw->mac.type) {
2265 case ixgbe_mac_82599EB:
2266 case ixgbe_mac_X540:
2267 if (eicr & IXGBE_EICR_ECC)
2268 e_info(link, "Received unrecoverable ECC Err, please "
2270 /* Handle Flow Director Full threshold interrupt */
2271 if (eicr & IXGBE_EICR_FLOW_DIR) {
2272 int reinit_count = 0;
2274 for (i = 0; i < adapter->num_tx_queues; i++) {
2275 struct ixgbe_ring *ring = adapter->tx_ring[i];
2276 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2281 /* no more flow director interrupts until after init */
2282 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2283 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2284 ixgbe_service_event_schedule(adapter);
2287 ixgbe_check_sfp_event(adapter, eicr);
2288 ixgbe_check_overtemp_event(adapter, eicr);
2294 ixgbe_check_fan_failure(adapter, eicr);
2296 /* re-enable the original interrupt state, no lsc, no queues */
2297 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2298 ixgbe_irq_enable(adapter, false, false);
2303 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2305 struct ixgbe_q_vector *q_vector = data;
2307 /* EIAM disabled interrupts (on this vector) for us */
2309 if (q_vector->rx.ring || q_vector->tx.ring)
2310 napi_schedule(&q_vector->napi);
2316 * ixgbe_poll - NAPI Rx polling callback
2317 * @napi: structure for representing this polling device
2318 * @budget: how many packets driver is allowed to clean
2320 * This function is used for legacy and MSI, NAPI mode
2322 int ixgbe_poll(struct napi_struct *napi, int budget)
2324 struct ixgbe_q_vector *q_vector =
2325 container_of(napi, struct ixgbe_q_vector, napi);
2326 struct ixgbe_adapter *adapter = q_vector->adapter;
2327 struct ixgbe_ring *ring;
2328 int per_ring_budget;
2329 bool clean_complete = true;
2331 #ifdef CONFIG_IXGBE_DCA
2332 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2333 ixgbe_update_dca(q_vector);
2336 ixgbe_for_each_ring(ring, q_vector->tx)
2337 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2339 /* attempt to distribute budget to each queue fairly, but don't allow
2340 * the budget to go below 1 because we'll exit polling */
2341 if (q_vector->rx.count > 1)
2342 per_ring_budget = max(budget/q_vector->rx.count, 1);
2344 per_ring_budget = budget;
2346 ixgbe_for_each_ring(ring, q_vector->rx)
2347 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2350 /* If all work not completed, return budget and keep polling */
2351 if (!clean_complete)
2354 /* all work done, exit the polling mode */
2355 napi_complete(napi);
2356 if (adapter->rx_itr_setting & 1)
2357 ixgbe_set_itr(q_vector);
2358 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2359 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2365 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2366 * @adapter: board private structure
2368 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2369 * interrupts from the kernel.
2371 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2373 struct net_device *netdev = adapter->netdev;
2374 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2378 for (vector = 0; vector < q_vectors; vector++) {
2379 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2380 struct msix_entry *entry = &adapter->msix_entries[vector];
2382 if (q_vector->tx.ring && q_vector->rx.ring) {
2383 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2384 "%s-%s-%d", netdev->name, "TxRx", ri++);
2386 } else if (q_vector->rx.ring) {
2387 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2388 "%s-%s-%d", netdev->name, "rx", ri++);
2389 } else if (q_vector->tx.ring) {
2390 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2391 "%s-%s-%d", netdev->name, "tx", ti++);
2393 /* skip this unused q_vector */
2396 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2397 q_vector->name, q_vector);
2399 e_err(probe, "request_irq failed for MSIX interrupt "
2400 "Error: %d\n", err);
2401 goto free_queue_irqs;
2403 /* If Flow Director is enabled, set interrupt affinity */
2404 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2405 /* assign the mask for this irq */
2406 irq_set_affinity_hint(entry->vector,
2407 &q_vector->affinity_mask);
2411 err = request_irq(adapter->msix_entries[vector].vector,
2412 ixgbe_msix_other, 0, netdev->name, adapter);
2414 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2415 goto free_queue_irqs;
2423 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2425 free_irq(adapter->msix_entries[vector].vector,
2426 adapter->q_vector[vector]);
2428 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2429 pci_disable_msix(adapter->pdev);
2430 kfree(adapter->msix_entries);
2431 adapter->msix_entries = NULL;
2436 * ixgbe_intr - legacy mode Interrupt Handler
2437 * @irq: interrupt number
2438 * @data: pointer to a network interface device structure
2440 static irqreturn_t ixgbe_intr(int irq, void *data)
2442 struct ixgbe_adapter *adapter = data;
2443 struct ixgbe_hw *hw = &adapter->hw;
2444 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2448 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2449 * before the read of EICR.
2451 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2453 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2454 * therefore no explicit interrupt disable is necessary */
2455 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2458 * shared interrupt alert!
2459 * make sure interrupts are enabled because the read will
2460 * have disabled interrupts due to EIAM
2461 * finish the workaround of silicon errata on 82598. Unmask
2462 * the interrupt that we masked before the EICR read.
2464 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2465 ixgbe_irq_enable(adapter, true, true);
2466 return IRQ_NONE; /* Not our interrupt */
2469 if (eicr & IXGBE_EICR_LSC)
2470 ixgbe_check_lsc(adapter);
2472 switch (hw->mac.type) {
2473 case ixgbe_mac_82599EB:
2474 ixgbe_check_sfp_event(adapter, eicr);
2476 case ixgbe_mac_X540:
2477 if (eicr & IXGBE_EICR_ECC)
2478 e_info(link, "Received unrecoverable ECC err, please "
2480 ixgbe_check_overtemp_event(adapter, eicr);
2486 ixgbe_check_fan_failure(adapter, eicr);
2488 /* would disable interrupts here but EIAM disabled it */
2489 napi_schedule(&q_vector->napi);
2492 * re-enable link(maybe) and non-queue interrupts, no flush.
2493 * ixgbe_poll will re-enable the queue interrupts
2495 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2496 ixgbe_irq_enable(adapter, false, false);
2502 * ixgbe_request_irq - initialize interrupts
2503 * @adapter: board private structure
2505 * Attempts to configure interrupts using the best available
2506 * capabilities of the hardware and kernel.
2508 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2510 struct net_device *netdev = adapter->netdev;
2513 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2514 err = ixgbe_request_msix_irqs(adapter);
2515 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2516 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2517 netdev->name, adapter);
2519 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2520 netdev->name, adapter);
2523 e_err(probe, "request_irq failed, Error %d\n", err);
2528 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2530 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2533 q_vectors = adapter->num_msix_vectors;
2535 free_irq(adapter->msix_entries[i].vector, adapter);
2538 for (; i >= 0; i--) {
2539 /* free only the irqs that were actually requested */
2540 if (!adapter->q_vector[i]->rx.ring &&
2541 !adapter->q_vector[i]->tx.ring)
2544 /* clear the affinity_mask in the IRQ descriptor */
2545 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2548 free_irq(adapter->msix_entries[i].vector,
2549 adapter->q_vector[i]);
2552 free_irq(adapter->pdev->irq, adapter);
2557 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2558 * @adapter: board private structure
2560 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2562 switch (adapter->hw.mac.type) {
2563 case ixgbe_mac_82598EB:
2564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2566 case ixgbe_mac_82599EB:
2567 case ixgbe_mac_X540:
2568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2575 IXGBE_WRITE_FLUSH(&adapter->hw);
2576 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2578 for (i = 0; i < adapter->num_msix_vectors; i++)
2579 synchronize_irq(adapter->msix_entries[i].vector);
2581 synchronize_irq(adapter->pdev->irq);
2586 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2589 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2591 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2594 if (adapter->rx_itr_setting == 1)
2595 q_vector->itr = IXGBE_20K_ITR;
2597 q_vector->itr = adapter->rx_itr_setting;
2599 ixgbe_write_eitr(q_vector);
2601 ixgbe_set_ivar(adapter, 0, 0, 0);
2602 ixgbe_set_ivar(adapter, 1, 0, 0);
2604 e_info(hw, "Legacy interrupt IVAR setup done\n");
2608 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2609 * @adapter: board private structure
2610 * @ring: structure containing ring specific data
2612 * Configure the Tx descriptor ring after a reset.
2614 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2615 struct ixgbe_ring *ring)
2617 struct ixgbe_hw *hw = &adapter->hw;
2618 u64 tdba = ring->dma;
2620 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2621 u8 reg_idx = ring->reg_idx;
2623 /* disable queue to avoid issues while updating state */
2624 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2625 IXGBE_WRITE_FLUSH(hw);
2627 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2628 (tdba & DMA_BIT_MASK(32)));
2629 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2630 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2631 ring->count * sizeof(union ixgbe_adv_tx_desc));
2632 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2633 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2634 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2637 * set WTHRESH to encourage burst writeback, it should not be set
2638 * higher than 1 when ITR is 0 as it could cause false TX hangs
2640 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2641 * to or less than the number of on chip descriptors, which is
2644 if (!ring->q_vector || (ring->q_vector->itr < 8))
2645 txdctl |= (1 << 16); /* WTHRESH = 1 */
2647 txdctl |= (8 << 16); /* WTHRESH = 8 */
2650 * Setting PTHRESH to 32 both improves performance
2651 * and avoids a TX hang with DFP enabled
2653 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2654 32; /* PTHRESH = 32 */
2656 /* reinitialize flowdirector state */
2657 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2658 adapter->atr_sample_rate) {
2659 ring->atr_sample_rate = adapter->atr_sample_rate;
2660 ring->atr_count = 0;
2661 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2663 ring->atr_sample_rate = 0;
2666 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2669 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2671 netdev_tx_reset_queue(txring_txq(ring));
2673 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2674 if (hw->mac.type == ixgbe_mac_82598EB &&
2675 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2678 /* poll to verify queue is enabled */
2680 usleep_range(1000, 2000);
2681 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2682 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2684 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2687 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2689 struct ixgbe_hw *hw = &adapter->hw;
2692 u8 tcs = netdev_get_num_tc(adapter->netdev);
2694 if (hw->mac.type == ixgbe_mac_82598EB)
2697 /* disable the arbiter while setting MTQC */
2698 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2699 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2700 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2702 /* set transmit pool layout */
2703 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2704 case (IXGBE_FLAG_SRIOV_ENABLED):
2705 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2706 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2710 reg = IXGBE_MTQC_64Q_1PB;
2712 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2714 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2716 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2718 /* Enable Security TX Buffer IFG for multiple pb */
2720 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2721 reg |= IXGBE_SECTX_DCB;
2722 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2727 /* re-enable the arbiter */
2728 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2729 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2733 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2734 * @adapter: board private structure
2736 * Configure the Tx unit of the MAC after a reset.
2738 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2740 struct ixgbe_hw *hw = &adapter->hw;
2744 ixgbe_setup_mtqc(adapter);
2746 if (hw->mac.type != ixgbe_mac_82598EB) {
2747 /* DMATXCTL.EN must be before Tx queues are enabled */
2748 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2749 dmatxctl |= IXGBE_DMATXCTL_TE;
2750 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2753 /* Setup the HW Tx Head and Tail descriptor pointers */
2754 for (i = 0; i < adapter->num_tx_queues; i++)
2755 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2758 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2760 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2761 struct ixgbe_ring *rx_ring)
2764 u8 reg_idx = rx_ring->reg_idx;
2766 switch (adapter->hw.mac.type) {
2767 case ixgbe_mac_82598EB: {
2768 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2769 const int mask = feature[RING_F_RSS].mask;
2770 reg_idx = reg_idx & mask;
2773 case ixgbe_mac_82599EB:
2774 case ixgbe_mac_X540:
2779 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2781 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2782 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2783 if (adapter->num_vfs)
2784 srrctl |= IXGBE_SRRCTL_DROP_EN;
2786 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2787 IXGBE_SRRCTL_BSIZEHDR_MASK;
2789 #if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2790 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2792 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2794 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2796 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2799 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2801 struct ixgbe_hw *hw = &adapter->hw;
2802 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2803 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2804 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2805 u32 mrqc = 0, reta = 0;
2808 u8 tcs = netdev_get_num_tc(adapter->netdev);
2809 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2812 maxq = min(maxq, adapter->num_tx_queues / tcs);
2814 /* Fill out hash function seeds */
2815 for (i = 0; i < 10; i++)
2816 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2818 /* Fill out redirection table */
2819 for (i = 0, j = 0; i < 128; i++, j++) {
2822 /* reta = 4-byte sliding window of
2823 * 0x00..(indices-1)(indices-1)00..etc. */
2824 reta = (reta << 8) | (j * 0x11);
2826 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2829 /* Disable indicating checksum in descriptor, enables RSS hash */
2830 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2831 rxcsum |= IXGBE_RXCSUM_PCSD;
2832 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2834 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2835 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2836 mrqc = IXGBE_MRQC_RSSEN;
2838 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2839 | IXGBE_FLAG_SRIOV_ENABLED);
2842 case (IXGBE_FLAG_RSS_ENABLED):
2844 mrqc = IXGBE_MRQC_RSSEN;
2846 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2848 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2850 case (IXGBE_FLAG_SRIOV_ENABLED):
2851 mrqc = IXGBE_MRQC_VMDQEN;
2858 /* Perform hash on these packet types */
2859 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2860 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2861 | IXGBE_MRQC_RSS_FIELD_IPV6
2862 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2864 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2865 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2866 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2867 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2869 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2873 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2874 * @adapter: address of board private structure
2875 * @index: index of ring to set
2877 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2878 struct ixgbe_ring *ring)
2880 struct ixgbe_hw *hw = &adapter->hw;
2882 u8 reg_idx = ring->reg_idx;
2884 if (!ring_is_rsc_enabled(ring))
2887 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2888 rscctrl |= IXGBE_RSCCTL_RSCEN;
2890 * we must limit the number of descriptors so that the
2891 * total size of max desc * buf_len is not greater
2894 #if (PAGE_SIZE <= 8192)
2895 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2896 #elif (PAGE_SIZE <= 16384)
2897 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2899 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2901 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2905 * ixgbe_set_uta - Set unicast filter table address
2906 * @adapter: board private structure
2908 * The unicast table address is a register array of 32-bit registers.
2909 * The table is meant to be used in a way similar to how the MTA is used
2910 * however due to certain limitations in the hardware it is necessary to
2911 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2912 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2914 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2916 struct ixgbe_hw *hw = &adapter->hw;
2919 /* The UTA table only exists on 82599 hardware and newer */
2920 if (hw->mac.type < ixgbe_mac_82599EB)
2923 /* we only need to do this if VMDq is enabled */
2924 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2927 for (i = 0; i < 128; i++)
2928 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2931 #define IXGBE_MAX_RX_DESC_POLL 10
2932 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2933 struct ixgbe_ring *ring)
2935 struct ixgbe_hw *hw = &adapter->hw;
2936 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2938 u8 reg_idx = ring->reg_idx;
2940 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2941 if (hw->mac.type == ixgbe_mac_82598EB &&
2942 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2946 usleep_range(1000, 2000);
2947 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2948 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2951 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2952 "the polling period\n", reg_idx);
2956 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2957 struct ixgbe_ring *ring)
2959 struct ixgbe_hw *hw = &adapter->hw;
2960 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2962 u8 reg_idx = ring->reg_idx;
2964 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2965 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2967 /* write value back with RXDCTL.ENABLE bit cleared */
2968 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2970 if (hw->mac.type == ixgbe_mac_82598EB &&
2971 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2974 /* the hardware may take up to 100us to really disable the rx queue */
2977 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2978 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2981 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2982 "the polling period\n", reg_idx);
2986 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2987 struct ixgbe_ring *ring)
2989 struct ixgbe_hw *hw = &adapter->hw;
2990 u64 rdba = ring->dma;
2992 u8 reg_idx = ring->reg_idx;
2994 /* disable queue to avoid issues while updating state */
2995 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2996 ixgbe_disable_rx_queue(adapter, ring);
2998 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2999 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3000 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3001 ring->count * sizeof(union ixgbe_adv_rx_desc));
3002 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3003 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3004 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3006 ixgbe_configure_srrctl(adapter, ring);
3007 ixgbe_configure_rscctl(adapter, ring);
3009 /* If operating in IOV mode set RLPML for X540 */
3010 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3011 hw->mac.type == ixgbe_mac_X540) {
3012 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3013 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3014 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3017 if (hw->mac.type == ixgbe_mac_82598EB) {
3019 * enable cache line friendly hardware writes:
3020 * PTHRESH=32 descriptors (half the internal cache),
3021 * this also removes ugly rx_no_buffer_count increment
3022 * HTHRESH=4 descriptors (to minimize latency on fetch)
3023 * WTHRESH=8 burst writeback up to two cache lines
3025 rxdctl &= ~0x3FFFFF;
3029 /* enable receive descriptor ring */
3030 rxdctl |= IXGBE_RXDCTL_ENABLE;
3031 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3033 ixgbe_rx_desc_queue_enable(adapter, ring);
3034 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3037 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3039 struct ixgbe_hw *hw = &adapter->hw;
3042 /* PSRTYPE must be initialized in non 82598 adapters */
3043 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3044 IXGBE_PSRTYPE_UDPHDR |
3045 IXGBE_PSRTYPE_IPV4HDR |
3046 IXGBE_PSRTYPE_L2HDR |
3047 IXGBE_PSRTYPE_IPV6HDR;
3049 if (hw->mac.type == ixgbe_mac_82598EB)
3052 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3053 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3055 for (p = 0; p < adapter->num_rx_pools; p++)
3056 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3060 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3062 struct ixgbe_hw *hw = &adapter->hw;
3065 u32 reg_offset, vf_shift;
3069 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3072 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3073 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3074 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3075 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3077 vf_shift = adapter->num_vfs % 32;
3078 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3080 /* Enable only the PF's pool for Tx/Rx */
3081 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3082 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3083 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3084 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3085 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3087 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3088 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3091 * Set up VF register offsets for selected VT Mode,
3092 * i.e. 32 or 64 VFs for SR-IOV
3094 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3095 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3096 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3097 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3099 /* enable Tx loopback for VF/PF communication */
3100 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3101 /* Enable MAC Anti-Spoofing */
3102 hw->mac.ops.set_mac_anti_spoofing(hw,
3103 (adapter->num_vfs != 0),
3105 /* For VFs that have spoof checking turned off */
3106 for (i = 0; i < adapter->num_vfs; i++) {
3107 if (!adapter->vfinfo[i].spoofchk_enabled)
3108 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3112 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3114 struct ixgbe_hw *hw = &adapter->hw;
3115 struct net_device *netdev = adapter->netdev;
3116 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3117 struct ixgbe_ring *rx_ring;
3122 /* adjust max frame to be able to do baby jumbo for FCoE */
3123 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3124 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3125 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3127 #endif /* IXGBE_FCOE */
3128 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3129 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3130 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3131 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3133 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3136 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3137 max_frame += VLAN_HLEN;
3139 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3140 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3141 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3142 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3145 * Setup the HW Rx Head and Tail Descriptor Pointers and
3146 * the Base and Length of the Rx Descriptor Ring
3148 for (i = 0; i < adapter->num_rx_queues; i++) {
3149 rx_ring = adapter->rx_ring[i];
3150 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3151 set_ring_rsc_enabled(rx_ring);
3153 clear_ring_rsc_enabled(rx_ring);
3155 if (netdev->features & NETIF_F_FCOE_MTU) {
3156 struct ixgbe_ring_feature *f;
3157 f = &adapter->ring_feature[RING_F_FCOE];
3158 if ((i >= f->mask) && (i < f->mask + f->indices))
3159 set_bit(__IXGBE_RX_FCOE_BUFSZ, &rx_ring->state);
3161 #endif /* IXGBE_FCOE */
3165 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3167 struct ixgbe_hw *hw = &adapter->hw;
3168 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3170 switch (hw->mac.type) {
3171 case ixgbe_mac_82598EB:
3173 * For VMDq support of different descriptor types or
3174 * buffer sizes through the use of multiple SRRCTL
3175 * registers, RDRXCTL.MVMEN must be set to 1
3177 * also, the manual doesn't mention it clearly but DCA hints
3178 * will only use queue 0's tags unless this bit is set. Side
3179 * effects of setting this bit are only that SRRCTL must be
3180 * fully programmed [0..15]
3182 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3184 case ixgbe_mac_82599EB:
3185 case ixgbe_mac_X540:
3186 /* Disable RSC for ACK packets */
3187 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3188 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3189 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3190 /* hardware requires some bits to be set by default */
3191 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3192 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3195 /* We should do nothing since we don't know this hardware */
3199 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3203 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3204 * @adapter: board private structure
3206 * Configure the Rx unit of the MAC after a reset.
3208 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3210 struct ixgbe_hw *hw = &adapter->hw;
3214 /* disable receives while setting up the descriptors */
3215 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3216 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3218 ixgbe_setup_psrtype(adapter);
3219 ixgbe_setup_rdrxctl(adapter);
3221 /* Program registers for the distribution of queues */
3222 ixgbe_setup_mrqc(adapter);
3224 ixgbe_set_uta(adapter);
3226 /* set_rx_buffer_len must be called before ring initialization */
3227 ixgbe_set_rx_buffer_len(adapter);
3230 * Setup the HW Rx Head and Tail Descriptor Pointers and
3231 * the Base and Length of the Rx Descriptor Ring
3233 for (i = 0; i < adapter->num_rx_queues; i++)
3234 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3236 /* disable drop enable for 82598 parts */
3237 if (hw->mac.type == ixgbe_mac_82598EB)
3238 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3240 /* enable all receives */
3241 rxctrl |= IXGBE_RXCTRL_RXEN;
3242 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3245 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3247 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3248 struct ixgbe_hw *hw = &adapter->hw;
3249 int pool_ndx = adapter->num_vfs;
3251 /* add VID to filter table */
3252 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3253 set_bit(vid, adapter->active_vlans);
3258 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3260 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3261 struct ixgbe_hw *hw = &adapter->hw;
3262 int pool_ndx = adapter->num_vfs;
3264 /* remove VID from filter table */
3265 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3266 clear_bit(vid, adapter->active_vlans);
3272 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3273 * @adapter: driver data
3275 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3277 struct ixgbe_hw *hw = &adapter->hw;
3280 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3281 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3282 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3286 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3287 * @adapter: driver data
3289 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3291 struct ixgbe_hw *hw = &adapter->hw;
3294 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3295 vlnctrl |= IXGBE_VLNCTRL_VFE;
3296 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3297 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3301 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3302 * @adapter: driver data
3304 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3306 struct ixgbe_hw *hw = &adapter->hw;
3310 switch (hw->mac.type) {
3311 case ixgbe_mac_82598EB:
3312 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3313 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3314 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3316 case ixgbe_mac_82599EB:
3317 case ixgbe_mac_X540:
3318 for (i = 0; i < adapter->num_rx_queues; i++) {
3319 j = adapter->rx_ring[i]->reg_idx;
3320 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3321 vlnctrl &= ~IXGBE_RXDCTL_VME;
3322 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3331 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3332 * @adapter: driver data
3334 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3336 struct ixgbe_hw *hw = &adapter->hw;
3340 switch (hw->mac.type) {
3341 case ixgbe_mac_82598EB:
3342 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3343 vlnctrl |= IXGBE_VLNCTRL_VME;
3344 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3346 case ixgbe_mac_82599EB:
3347 case ixgbe_mac_X540:
3348 for (i = 0; i < adapter->num_rx_queues; i++) {
3349 j = adapter->rx_ring[i]->reg_idx;
3350 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3351 vlnctrl |= IXGBE_RXDCTL_VME;
3352 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3360 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3364 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3366 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3367 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3371 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3372 * @netdev: network interface device structure
3374 * Writes unicast address list to the RAR table.
3375 * Returns: -ENOMEM on failure/insufficient address space
3376 * 0 on no addresses written
3377 * X on writing X addresses to the RAR table
3379 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3381 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3382 struct ixgbe_hw *hw = &adapter->hw;
3383 unsigned int vfn = adapter->num_vfs;
3384 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3387 /* return ENOMEM indicating insufficient memory for addresses */
3388 if (netdev_uc_count(netdev) > rar_entries)
3391 if (!netdev_uc_empty(netdev) && rar_entries) {
3392 struct netdev_hw_addr *ha;
3393 /* return error if we do not support writing to RAR table */
3394 if (!hw->mac.ops.set_rar)
3397 netdev_for_each_uc_addr(ha, netdev) {
3400 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3405 /* write the addresses in reverse order to avoid write combining */
3406 for (; rar_entries > 0 ; rar_entries--)
3407 hw->mac.ops.clear_rar(hw, rar_entries);
3413 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3414 * @netdev: network interface device structure
3416 * The set_rx_method entry point is called whenever the unicast/multicast
3417 * address list or the network interface flags are updated. This routine is
3418 * responsible for configuring the hardware for proper unicast, multicast and
3421 void ixgbe_set_rx_mode(struct net_device *netdev)
3423 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3424 struct ixgbe_hw *hw = &adapter->hw;
3425 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3428 /* Check for Promiscuous and All Multicast modes */
3430 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3432 /* set all bits that we expect to always be set */
3433 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3434 fctrl |= IXGBE_FCTRL_BAM;
3435 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3436 fctrl |= IXGBE_FCTRL_PMCF;
3438 /* clear the bits we are changing the status of */
3439 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3441 if (netdev->flags & IFF_PROMISC) {
3442 hw->addr_ctrl.user_set_promisc = true;
3443 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3444 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3445 /* don't hardware filter vlans in promisc mode */
3446 ixgbe_vlan_filter_disable(adapter);
3448 if (netdev->flags & IFF_ALLMULTI) {
3449 fctrl |= IXGBE_FCTRL_MPE;
3450 vmolr |= IXGBE_VMOLR_MPE;
3453 * Write addresses to the MTA, if the attempt fails
3454 * then we should just turn on promiscuous mode so
3455 * that we can at least receive multicast traffic
3457 hw->mac.ops.update_mc_addr_list(hw, netdev);
3458 vmolr |= IXGBE_VMOLR_ROMPE;
3460 ixgbe_vlan_filter_enable(adapter);
3461 hw->addr_ctrl.user_set_promisc = false;
3463 * Write addresses to available RAR registers, if there is not
3464 * sufficient space to store all the addresses then enable
3465 * unicast promiscuous mode
3467 count = ixgbe_write_uc_addr_list(netdev);
3469 fctrl |= IXGBE_FCTRL_UPE;
3470 vmolr |= IXGBE_VMOLR_ROPE;
3474 if (adapter->num_vfs) {
3475 ixgbe_restore_vf_multicasts(adapter);
3476 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3477 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3479 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3482 /* This is useful for sniffing bad packets. */
3483 if (adapter->netdev->features & NETIF_F_RXALL) {
3484 /* UPE and MPE will be handled by normal PROMISC logic
3485 * in e1000e_set_rx_mode */
3486 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3487 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3488 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3490 fctrl &= ~(IXGBE_FCTRL_DPF);
3491 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3494 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3496 if (netdev->features & NETIF_F_HW_VLAN_RX)
3497 ixgbe_vlan_strip_enable(adapter);
3499 ixgbe_vlan_strip_disable(adapter);
3502 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3505 struct ixgbe_q_vector *q_vector;
3506 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3508 /* legacy and MSI only use one vector */
3509 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3512 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3513 q_vector = adapter->q_vector[q_idx];
3514 napi_enable(&q_vector->napi);
3518 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3521 struct ixgbe_q_vector *q_vector;
3522 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3524 /* legacy and MSI only use one vector */
3525 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3528 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3529 q_vector = adapter->q_vector[q_idx];
3530 napi_disable(&q_vector->napi);
3534 #ifdef CONFIG_IXGBE_DCB
3536 * ixgbe_configure_dcb - Configure DCB hardware
3537 * @adapter: ixgbe adapter struct
3539 * This is called by the driver on open to configure the DCB hardware.
3540 * This is also called by the gennetlink interface when reconfiguring
3543 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3545 struct ixgbe_hw *hw = &adapter->hw;
3546 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3548 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3549 if (hw->mac.type == ixgbe_mac_82598EB)
3550 netif_set_gso_max_size(adapter->netdev, 65536);
3554 if (hw->mac.type == ixgbe_mac_82598EB)
3555 netif_set_gso_max_size(adapter->netdev, 32768);
3558 /* Enable VLAN tag insert/strip */
3559 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3561 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3564 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3565 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3568 /* reconfigure the hardware */
3569 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3570 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3572 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3574 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3575 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3576 ixgbe_dcb_hw_ets(&adapter->hw,
3577 adapter->ixgbe_ieee_ets,
3579 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3580 adapter->ixgbe_ieee_pfc->pfc_en,
3581 adapter->ixgbe_ieee_ets->prio_tc);
3584 /* Enable RSS Hash per TC */
3585 if (hw->mac.type != ixgbe_mac_82598EB) {
3589 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3591 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3596 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3598 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3603 /* Additional bittime to account for IXGBE framing */
3604 #define IXGBE_ETH_FRAMING 20
3607 * ixgbe_hpbthresh - calculate high water mark for flow control
3609 * @adapter: board private structure to calculate for
3610 * @pb - packet buffer to calculate
3612 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3614 struct ixgbe_hw *hw = &adapter->hw;
3615 struct net_device *dev = adapter->netdev;
3616 int link, tc, kb, marker;
3619 /* Calculate max LAN frame size */
3620 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3623 /* FCoE traffic class uses FCOE jumbo frames */
3624 if (dev->features & NETIF_F_FCOE_MTU) {
3627 #ifdef CONFIG_IXGBE_DCB
3628 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3631 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3632 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3636 /* Calculate delay value for device */
3637 switch (hw->mac.type) {
3638 case ixgbe_mac_X540:
3639 dv_id = IXGBE_DV_X540(link, tc);
3642 dv_id = IXGBE_DV(link, tc);
3646 /* Loopback switch introduces additional latency */
3647 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3648 dv_id += IXGBE_B2BT(tc);
3650 /* Delay value is calculated in bit times convert to KB */
3651 kb = IXGBE_BT2KB(dv_id);
3652 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3654 marker = rx_pba - kb;
3656 /* It is possible that the packet buffer is not large enough
3657 * to provide required headroom. In this case throw an error
3658 * to user and a do the best we can.
3661 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3662 "headroom to support flow control."
3663 "Decrease MTU or number of traffic classes\n", pb);
3671 * ixgbe_lpbthresh - calculate low water mark for for flow control
3673 * @adapter: board private structure to calculate for
3674 * @pb - packet buffer to calculate
3676 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3678 struct ixgbe_hw *hw = &adapter->hw;
3679 struct net_device *dev = adapter->netdev;
3683 /* Calculate max LAN frame size */
3684 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3686 /* Calculate delay value for device */
3687 switch (hw->mac.type) {
3688 case ixgbe_mac_X540:
3689 dv_id = IXGBE_LOW_DV_X540(tc);
3692 dv_id = IXGBE_LOW_DV(tc);
3696 /* Delay value is calculated in bit times convert to KB */
3697 return IXGBE_BT2KB(dv_id);
3701 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3703 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3705 struct ixgbe_hw *hw = &adapter->hw;
3706 int num_tc = netdev_get_num_tc(adapter->netdev);
3712 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3714 for (i = 0; i < num_tc; i++) {
3715 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3717 /* Low water marks must not be larger than high water marks */
3718 if (hw->fc.low_water > hw->fc.high_water[i])
3719 hw->fc.low_water = 0;
3723 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3725 struct ixgbe_hw *hw = &adapter->hw;
3727 u8 tc = netdev_get_num_tc(adapter->netdev);
3729 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3730 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3731 hdrm = 32 << adapter->fdir_pballoc;
3735 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3736 ixgbe_pbthresh_setup(adapter);
3739 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3741 struct ixgbe_hw *hw = &adapter->hw;
3742 struct hlist_node *node, *node2;
3743 struct ixgbe_fdir_filter *filter;
3745 spin_lock(&adapter->fdir_perfect_lock);
3747 if (!hlist_empty(&adapter->fdir_filter_list))
3748 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3750 hlist_for_each_entry_safe(filter, node, node2,
3751 &adapter->fdir_filter_list, fdir_node) {
3752 ixgbe_fdir_write_perfect_filter_82599(hw,
3755 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3756 IXGBE_FDIR_DROP_QUEUE :
3757 adapter->rx_ring[filter->action]->reg_idx);
3760 spin_unlock(&adapter->fdir_perfect_lock);
3763 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3765 struct ixgbe_hw *hw = &adapter->hw;
3767 ixgbe_configure_pb(adapter);
3768 #ifdef CONFIG_IXGBE_DCB
3769 ixgbe_configure_dcb(adapter);
3772 ixgbe_set_rx_mode(adapter->netdev);
3773 ixgbe_restore_vlan(adapter);
3776 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3777 ixgbe_configure_fcoe(adapter);
3779 #endif /* IXGBE_FCOE */
3781 switch (hw->mac.type) {
3782 case ixgbe_mac_82599EB:
3783 case ixgbe_mac_X540:
3784 hw->mac.ops.disable_rx_buff(hw);
3790 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3791 ixgbe_init_fdir_signature_82599(&adapter->hw,
3792 adapter->fdir_pballoc);
3793 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3794 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3795 adapter->fdir_pballoc);
3796 ixgbe_fdir_filter_restore(adapter);
3799 switch (hw->mac.type) {
3800 case ixgbe_mac_82599EB:
3801 case ixgbe_mac_X540:
3802 hw->mac.ops.enable_rx_buff(hw);
3808 ixgbe_configure_virtualization(adapter);
3810 ixgbe_configure_tx(adapter);
3811 ixgbe_configure_rx(adapter);
3814 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3816 switch (hw->phy.type) {
3817 case ixgbe_phy_sfp_avago:
3818 case ixgbe_phy_sfp_ftl:
3819 case ixgbe_phy_sfp_intel:
3820 case ixgbe_phy_sfp_unknown:
3821 case ixgbe_phy_sfp_passive_tyco:
3822 case ixgbe_phy_sfp_passive_unknown:
3823 case ixgbe_phy_sfp_active_unknown:
3824 case ixgbe_phy_sfp_ftl_active:
3827 if (hw->mac.type == ixgbe_mac_82598EB)
3835 * ixgbe_sfp_link_config - set up SFP+ link
3836 * @adapter: pointer to private adapter struct
3838 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3841 * We are assuming the worst case scenario here, and that
3842 * is that an SFP was inserted/removed after the reset
3843 * but before SFP detection was enabled. As such the best
3844 * solution is to just start searching as soon as we start
3846 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3847 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3849 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3853 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3854 * @hw: pointer to private hardware struct
3856 * Returns 0 on success, negative on failure
3858 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3861 bool negotiation, link_up = false;
3862 u32 ret = IXGBE_ERR_LINK_SETUP;
3864 if (hw->mac.ops.check_link)
3865 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3870 autoneg = hw->phy.autoneg_advertised;
3871 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3872 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3877 if (hw->mac.ops.setup_link)
3878 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3883 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3885 struct ixgbe_hw *hw = &adapter->hw;
3888 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3889 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3891 gpie |= IXGBE_GPIE_EIAME;
3893 * use EIAM to auto-mask when MSI-X interrupt is asserted
3894 * this saves a register write for every interrupt
3896 switch (hw->mac.type) {
3897 case ixgbe_mac_82598EB:
3898 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3900 case ixgbe_mac_82599EB:
3901 case ixgbe_mac_X540:
3903 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3904 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3908 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3909 * specifically only auto mask tx and rx interrupts */
3910 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3913 /* XXX: to interrupt immediately for EICS writes, enable this */
3914 /* gpie |= IXGBE_GPIE_EIMEN; */
3916 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3917 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3918 gpie |= IXGBE_GPIE_VTMODE_64;
3921 /* Enable Thermal over heat sensor interrupt */
3922 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3923 switch (adapter->hw.mac.type) {
3924 case ixgbe_mac_82599EB:
3925 gpie |= IXGBE_SDP0_GPIEN;
3927 case ixgbe_mac_X540:
3928 gpie |= IXGBE_EIMS_TS;
3935 /* Enable fan failure interrupt */
3936 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3937 gpie |= IXGBE_SDP1_GPIEN;
3939 if (hw->mac.type == ixgbe_mac_82599EB) {
3940 gpie |= IXGBE_SDP1_GPIEN;
3941 gpie |= IXGBE_SDP2_GPIEN;
3944 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3947 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3949 struct ixgbe_hw *hw = &adapter->hw;
3953 ixgbe_get_hw_control(adapter);
3954 ixgbe_setup_gpie(adapter);
3956 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3957 ixgbe_configure_msix(adapter);
3959 ixgbe_configure_msi_and_legacy(adapter);
3961 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3962 if (hw->mac.ops.enable_tx_laser &&
3963 ((hw->phy.multispeed_fiber) ||
3964 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3965 (hw->mac.type == ixgbe_mac_82599EB))))
3966 hw->mac.ops.enable_tx_laser(hw);
3968 clear_bit(__IXGBE_DOWN, &adapter->state);
3969 ixgbe_napi_enable_all(adapter);
3971 if (ixgbe_is_sfp(hw)) {
3972 ixgbe_sfp_link_config(adapter);
3974 err = ixgbe_non_sfp_link_config(hw);
3976 e_err(probe, "link_config FAILED %d\n", err);
3979 /* clear any pending interrupts, may auto mask */
3980 IXGBE_READ_REG(hw, IXGBE_EICR);
3981 ixgbe_irq_enable(adapter, true, true);
3984 * If this adapter has a fan, check to see if we had a failure
3985 * before we enabled the interrupt.
3987 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3988 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3989 if (esdp & IXGBE_ESDP_SDP1)
3990 e_crit(drv, "Fan has stopped, replace the adapter\n");
3993 /* enable transmits */
3994 netif_tx_start_all_queues(adapter->netdev);
3996 /* bring the link up in the watchdog, this could race with our first
3997 * link up interrupt but shouldn't be a problem */
3998 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3999 adapter->link_check_timeout = jiffies;
4000 mod_timer(&adapter->service_timer, jiffies);
4002 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4003 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4004 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4005 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4008 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4010 WARN_ON(in_interrupt());
4011 /* put off any impending NetWatchDogTimeout */
4012 adapter->netdev->trans_start = jiffies;
4014 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4015 usleep_range(1000, 2000);
4016 ixgbe_down(adapter);
4018 * If SR-IOV enabled then wait a bit before bringing the adapter
4019 * back up to give the VFs time to respond to the reset. The
4020 * two second wait is based upon the watchdog timer cycle in
4023 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4026 clear_bit(__IXGBE_RESETTING, &adapter->state);
4029 void ixgbe_up(struct ixgbe_adapter *adapter)
4031 /* hardware has been reset, we need to reload some things */
4032 ixgbe_configure(adapter);
4034 ixgbe_up_complete(adapter);
4037 void ixgbe_reset(struct ixgbe_adapter *adapter)
4039 struct ixgbe_hw *hw = &adapter->hw;
4042 /* lock SFP init bit to prevent race conditions with the watchdog */
4043 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4044 usleep_range(1000, 2000);
4046 /* clear all SFP and link config related flags while holding SFP_INIT */
4047 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4048 IXGBE_FLAG2_SFP_NEEDS_RESET);
4049 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4051 err = hw->mac.ops.init_hw(hw);
4054 case IXGBE_ERR_SFP_NOT_PRESENT:
4055 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4057 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4058 e_dev_err("master disable timed out\n");
4060 case IXGBE_ERR_EEPROM_VERSION:
4061 /* We are running on a pre-production device, log a warning */
4062 e_dev_warn("This device is a pre-production adapter/LOM. "
4063 "Please be aware there may be issues associated with "
4064 "your hardware. If you are experiencing problems "
4065 "please contact your Intel or hardware "
4066 "representative who provided you with this "
4070 e_dev_err("Hardware Error: %d\n", err);
4073 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4075 /* reprogram the RAR[0] in case user changed it. */
4076 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4081 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4082 * @rx_ring: ring to setup
4084 * On many IA platforms the L1 cache has a critical stride of 4K, this
4085 * results in each receive buffer starting in the same cache set. To help
4086 * reduce the pressure on this cache set we can interleave the offsets so
4087 * that only every other buffer will be in the same cache set.
4089 static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4091 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4094 for (i = 0; i < rx_ring->count; i += 2) {
4095 rx_buffer[0].page_offset = 0;
4096 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4097 rx_buffer = &rx_buffer[2];
4102 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4103 * @rx_ring: ring to free buffers from
4105 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4107 struct device *dev = rx_ring->dev;
4111 /* ring already cleared, nothing to do */
4112 if (!rx_ring->rx_buffer_info)
4115 /* Free all the Rx ring sk_buffs */
4116 for (i = 0; i < rx_ring->count; i++) {
4117 struct ixgbe_rx_buffer *rx_buffer;
4119 rx_buffer = &rx_ring->rx_buffer_info[i];
4120 if (rx_buffer->skb) {
4121 struct sk_buff *skb = rx_buffer->skb;
4122 if (IXGBE_CB(skb)->page_released) {
4125 ixgbe_rx_bufsz(rx_ring),
4127 IXGBE_CB(skb)->page_released = false;
4131 rx_buffer->skb = NULL;
4133 dma_unmap_page(dev, rx_buffer->dma,
4134 ixgbe_rx_pg_size(rx_ring),
4137 if (rx_buffer->page)
4138 put_page(rx_buffer->page);
4139 rx_buffer->page = NULL;
4142 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4143 memset(rx_ring->rx_buffer_info, 0, size);
4145 ixgbe_init_rx_page_offset(rx_ring);
4147 /* Zero out the descriptor ring */
4148 memset(rx_ring->desc, 0, rx_ring->size);
4150 rx_ring->next_to_alloc = 0;
4151 rx_ring->next_to_clean = 0;
4152 rx_ring->next_to_use = 0;
4156 * ixgbe_clean_tx_ring - Free Tx Buffers
4157 * @tx_ring: ring to be cleaned
4159 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4161 struct ixgbe_tx_buffer *tx_buffer_info;
4165 /* ring already cleared, nothing to do */
4166 if (!tx_ring->tx_buffer_info)
4169 /* Free all the Tx ring sk_buffs */
4170 for (i = 0; i < tx_ring->count; i++) {
4171 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4172 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4175 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4176 memset(tx_ring->tx_buffer_info, 0, size);
4178 /* Zero out the descriptor ring */
4179 memset(tx_ring->desc, 0, tx_ring->size);
4181 tx_ring->next_to_use = 0;
4182 tx_ring->next_to_clean = 0;
4186 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4187 * @adapter: board private structure
4189 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4193 for (i = 0; i < adapter->num_rx_queues; i++)
4194 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4198 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4199 * @adapter: board private structure
4201 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4205 for (i = 0; i < adapter->num_tx_queues; i++)
4206 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4209 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4211 struct hlist_node *node, *node2;
4212 struct ixgbe_fdir_filter *filter;
4214 spin_lock(&adapter->fdir_perfect_lock);
4216 hlist_for_each_entry_safe(filter, node, node2,
4217 &adapter->fdir_filter_list, fdir_node) {
4218 hlist_del(&filter->fdir_node);
4221 adapter->fdir_filter_count = 0;
4223 spin_unlock(&adapter->fdir_perfect_lock);
4226 void ixgbe_down(struct ixgbe_adapter *adapter)
4228 struct net_device *netdev = adapter->netdev;
4229 struct ixgbe_hw *hw = &adapter->hw;
4233 /* signal that we are down to the interrupt handler */
4234 set_bit(__IXGBE_DOWN, &adapter->state);
4236 /* disable receives */
4237 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4238 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4240 /* disable all enabled rx queues */
4241 for (i = 0; i < adapter->num_rx_queues; i++)
4242 /* this call also flushes the previous write */
4243 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4245 usleep_range(10000, 20000);
4247 netif_tx_stop_all_queues(netdev);
4249 /* call carrier off first to avoid false dev_watchdog timeouts */
4250 netif_carrier_off(netdev);
4251 netif_tx_disable(netdev);
4253 ixgbe_irq_disable(adapter);
4255 ixgbe_napi_disable_all(adapter);
4257 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4258 IXGBE_FLAG2_RESET_REQUESTED);
4259 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4261 del_timer_sync(&adapter->service_timer);
4263 if (adapter->num_vfs) {
4264 /* Clear EITR Select mapping */
4265 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4267 /* Mark all the VFs as inactive */
4268 for (i = 0 ; i < adapter->num_vfs; i++)
4269 adapter->vfinfo[i].clear_to_send = false;
4271 /* ping all the active vfs to let them know we are going down */
4272 ixgbe_ping_all_vfs(adapter);
4274 /* Disable all VFTE/VFRE TX/RX */
4275 ixgbe_disable_tx_rx(adapter);
4278 /* disable transmits in the hardware now that interrupts are off */
4279 for (i = 0; i < adapter->num_tx_queues; i++) {
4280 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4281 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4284 /* Disable the Tx DMA engine on 82599 and X540 */
4285 switch (hw->mac.type) {
4286 case ixgbe_mac_82599EB:
4287 case ixgbe_mac_X540:
4288 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4289 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4290 ~IXGBE_DMATXCTL_TE));
4296 if (!pci_channel_offline(adapter->pdev))
4297 ixgbe_reset(adapter);
4299 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4300 if (hw->mac.ops.disable_tx_laser &&
4301 ((hw->phy.multispeed_fiber) ||
4302 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4303 (hw->mac.type == ixgbe_mac_82599EB))))
4304 hw->mac.ops.disable_tx_laser(hw);
4306 ixgbe_clean_all_tx_rings(adapter);
4307 ixgbe_clean_all_rx_rings(adapter);
4309 #ifdef CONFIG_IXGBE_DCA
4310 /* since we reset the hardware DCA settings were cleared */
4311 ixgbe_setup_dca(adapter);
4316 * ixgbe_tx_timeout - Respond to a Tx Hang
4317 * @netdev: network interface device structure
4319 static void ixgbe_tx_timeout(struct net_device *netdev)
4321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4323 /* Do the reset outside of interrupt context */
4324 ixgbe_tx_timeout_reset(adapter);
4328 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4329 * @adapter: board private structure to initialize
4331 * ixgbe_sw_init initializes the Adapter private data structure.
4332 * Fields are initialized based on PCI device information and
4333 * OS network device settings (MTU size).
4335 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4337 struct ixgbe_hw *hw = &adapter->hw;
4338 struct pci_dev *pdev = adapter->pdev;
4340 #ifdef CONFIG_IXGBE_DCB
4342 struct tc_configuration *tc;
4345 /* PCI config space info */
4347 hw->vendor_id = pdev->vendor;
4348 hw->device_id = pdev->device;
4349 hw->revision_id = pdev->revision;
4350 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4351 hw->subsystem_device_id = pdev->subsystem_device;
4353 /* Set capability flags */
4354 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4355 adapter->ring_feature[RING_F_RSS].indices = rss;
4356 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4357 switch (hw->mac.type) {
4358 case ixgbe_mac_82598EB:
4359 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4360 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4361 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4363 case ixgbe_mac_X540:
4364 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4365 case ixgbe_mac_82599EB:
4366 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4367 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4368 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4369 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4370 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4371 /* Flow Director hash filters enabled */
4372 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4373 adapter->atr_sample_rate = 20;
4374 adapter->ring_feature[RING_F_FDIR].indices =
4375 IXGBE_MAX_FDIR_INDICES;
4376 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4378 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4379 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4380 adapter->ring_feature[RING_F_FCOE].indices = 0;
4381 #ifdef CONFIG_IXGBE_DCB
4382 /* Default traffic class to use for FCoE */
4383 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4385 #endif /* IXGBE_FCOE */
4391 /* n-tuple support exists, always init our spinlock */
4392 spin_lock_init(&adapter->fdir_perfect_lock);
4394 #ifdef CONFIG_IXGBE_DCB
4395 switch (hw->mac.type) {
4396 case ixgbe_mac_X540:
4397 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4398 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4401 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4402 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4406 /* Configure DCB traffic classes */
4407 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4408 tc = &adapter->dcb_cfg.tc_config[j];
4409 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4410 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4411 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4412 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4413 tc->dcb_pfc = pfc_disabled;
4416 /* Initialize default user to priority mapping, UPx->TC0 */
4417 tc = &adapter->dcb_cfg.tc_config[0];
4418 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4419 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4421 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4422 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4423 adapter->dcb_cfg.pfc_mode_enable = false;
4424 adapter->dcb_set_bitmap = 0x00;
4425 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4426 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4431 /* default flow control settings */
4432 hw->fc.requested_mode = ixgbe_fc_full;
4433 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4435 adapter->last_lfc_mode = hw->fc.current_mode;
4437 ixgbe_pbthresh_setup(adapter);
4438 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4439 hw->fc.send_xon = true;
4440 hw->fc.disable_fc_autoneg = false;
4442 /* enable itr by default in dynamic mode */
4443 adapter->rx_itr_setting = 1;
4444 adapter->tx_itr_setting = 1;
4446 /* set default ring sizes */
4447 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4448 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4450 /* set default work limits */
4451 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4453 /* initialize eeprom parameters */
4454 if (ixgbe_init_eeprom_params_generic(hw)) {
4455 e_dev_err("EEPROM initialization failed\n");
4459 set_bit(__IXGBE_DOWN, &adapter->state);
4465 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4466 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4468 * Return 0 on success, negative on failure
4470 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4472 struct device *dev = tx_ring->dev;
4473 int orig_node = dev_to_node(dev);
4477 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4479 if (tx_ring->q_vector)
4480 numa_node = tx_ring->q_vector->numa_node;
4482 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4483 if (!tx_ring->tx_buffer_info)
4484 tx_ring->tx_buffer_info = vzalloc(size);
4485 if (!tx_ring->tx_buffer_info)
4488 /* round up to nearest 4K */
4489 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4490 tx_ring->size = ALIGN(tx_ring->size, 4096);
4492 set_dev_node(dev, numa_node);
4493 tx_ring->desc = dma_alloc_coherent(dev,
4497 set_dev_node(dev, orig_node);
4499 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4500 &tx_ring->dma, GFP_KERNEL);
4504 tx_ring->next_to_use = 0;
4505 tx_ring->next_to_clean = 0;
4509 vfree(tx_ring->tx_buffer_info);
4510 tx_ring->tx_buffer_info = NULL;
4511 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4516 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4517 * @adapter: board private structure
4519 * If this function returns with an error, then it's possible one or
4520 * more of the rings is populated (while the rest are not). It is the
4521 * callers duty to clean those orphaned rings.
4523 * Return 0 on success, negative on failure
4525 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4529 for (i = 0; i < adapter->num_tx_queues; i++) {
4530 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4533 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4541 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4542 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4544 * Returns 0 on success, negative on failure
4546 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4548 struct device *dev = rx_ring->dev;
4549 int orig_node = dev_to_node(dev);
4553 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4555 if (rx_ring->q_vector)
4556 numa_node = rx_ring->q_vector->numa_node;
4558 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4559 if (!rx_ring->rx_buffer_info)
4560 rx_ring->rx_buffer_info = vzalloc(size);
4561 if (!rx_ring->rx_buffer_info)
4564 /* Round up to nearest 4K */
4565 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4566 rx_ring->size = ALIGN(rx_ring->size, 4096);
4568 set_dev_node(dev, numa_node);
4569 rx_ring->desc = dma_alloc_coherent(dev,
4573 set_dev_node(dev, orig_node);
4575 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4576 &rx_ring->dma, GFP_KERNEL);
4580 rx_ring->next_to_clean = 0;
4581 rx_ring->next_to_use = 0;
4583 ixgbe_init_rx_page_offset(rx_ring);
4587 vfree(rx_ring->rx_buffer_info);
4588 rx_ring->rx_buffer_info = NULL;
4589 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4594 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4595 * @adapter: board private structure
4597 * If this function returns with an error, then it's possible one or
4598 * more of the rings is populated (while the rest are not). It is the
4599 * callers duty to clean those orphaned rings.
4601 * Return 0 on success, negative on failure
4603 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4607 for (i = 0; i < adapter->num_rx_queues; i++) {
4608 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4611 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4619 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4620 * @tx_ring: Tx descriptor ring for a specific queue
4622 * Free all transmit software resources
4624 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4626 ixgbe_clean_tx_ring(tx_ring);
4628 vfree(tx_ring->tx_buffer_info);
4629 tx_ring->tx_buffer_info = NULL;
4631 /* if not set, then don't free */
4635 dma_free_coherent(tx_ring->dev, tx_ring->size,
4636 tx_ring->desc, tx_ring->dma);
4638 tx_ring->desc = NULL;
4642 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4643 * @adapter: board private structure
4645 * Free all transmit software resources
4647 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4651 for (i = 0; i < adapter->num_tx_queues; i++)
4652 if (adapter->tx_ring[i]->desc)
4653 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4657 * ixgbe_free_rx_resources - Free Rx Resources
4658 * @rx_ring: ring to clean the resources from
4660 * Free all receive software resources
4662 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4664 ixgbe_clean_rx_ring(rx_ring);
4666 vfree(rx_ring->rx_buffer_info);
4667 rx_ring->rx_buffer_info = NULL;
4669 /* if not set, then don't free */
4673 dma_free_coherent(rx_ring->dev, rx_ring->size,
4674 rx_ring->desc, rx_ring->dma);
4676 rx_ring->desc = NULL;
4680 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4681 * @adapter: board private structure
4683 * Free all receive software resources
4685 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4689 for (i = 0; i < adapter->num_rx_queues; i++)
4690 if (adapter->rx_ring[i]->desc)
4691 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4695 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4696 * @netdev: network interface device structure
4697 * @new_mtu: new value for maximum frame size
4699 * Returns 0 on success, negative on failure
4701 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4703 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4704 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4706 /* MTU < 68 is an error and causes problems on some kernels */
4707 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4711 * For 82599EB we cannot allow PF to change MTU greater than 1500
4712 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4713 * don't allocate and chain buffers correctly.
4715 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4716 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4717 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4720 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4722 /* must set new MTU before calling down or up */
4723 netdev->mtu = new_mtu;
4725 if (netif_running(netdev))
4726 ixgbe_reinit_locked(adapter);
4732 * ixgbe_open - Called when a network interface is made active
4733 * @netdev: network interface device structure
4735 * Returns 0 on success, negative value on failure
4737 * The open entry point is called when a network interface is made
4738 * active by the system (IFF_UP). At this point all resources needed
4739 * for transmit and receive operations are allocated, the interrupt
4740 * handler is registered with the OS, the watchdog timer is started,
4741 * and the stack is notified that the interface is ready.
4743 static int ixgbe_open(struct net_device *netdev)
4745 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4748 /* disallow open during test */
4749 if (test_bit(__IXGBE_TESTING, &adapter->state))
4752 netif_carrier_off(netdev);
4754 /* allocate transmit descriptors */
4755 err = ixgbe_setup_all_tx_resources(adapter);
4759 /* allocate receive descriptors */
4760 err = ixgbe_setup_all_rx_resources(adapter);
4764 ixgbe_configure(adapter);
4766 err = ixgbe_request_irq(adapter);
4770 ixgbe_up_complete(adapter);
4776 ixgbe_free_all_rx_resources(adapter);
4778 ixgbe_free_all_tx_resources(adapter);
4779 ixgbe_reset(adapter);
4785 * ixgbe_close - Disables a network interface
4786 * @netdev: network interface device structure
4788 * Returns 0, this is not allowed to fail
4790 * The close entry point is called when an interface is de-activated
4791 * by the OS. The hardware is still under the drivers control, but
4792 * needs to be disabled. A global MAC reset is issued to stop the
4793 * hardware, and all transmit and receive resources are freed.
4795 static int ixgbe_close(struct net_device *netdev)
4797 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4799 ixgbe_down(adapter);
4800 ixgbe_free_irq(adapter);
4802 ixgbe_fdir_filter_exit(adapter);
4804 ixgbe_free_all_tx_resources(adapter);
4805 ixgbe_free_all_rx_resources(adapter);
4807 ixgbe_release_hw_control(adapter);
4813 static int ixgbe_resume(struct pci_dev *pdev)
4815 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4816 struct net_device *netdev = adapter->netdev;
4819 pci_set_power_state(pdev, PCI_D0);
4820 pci_restore_state(pdev);
4822 * pci_restore_state clears dev->state_saved so call
4823 * pci_save_state to restore it.
4825 pci_save_state(pdev);
4827 err = pci_enable_device_mem(pdev);
4829 e_dev_err("Cannot enable PCI device from suspend\n");
4832 pci_set_master(pdev);
4834 pci_wake_from_d3(pdev, false);
4836 err = ixgbe_init_interrupt_scheme(adapter);
4838 e_dev_err("Cannot initialize interrupts for device\n");
4842 ixgbe_reset(adapter);
4844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4846 if (netif_running(netdev)) {
4847 err = ixgbe_open(netdev);
4852 netif_device_attach(netdev);
4856 #endif /* CONFIG_PM */
4858 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4860 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4861 struct net_device *netdev = adapter->netdev;
4862 struct ixgbe_hw *hw = &adapter->hw;
4864 u32 wufc = adapter->wol;
4869 netif_device_detach(netdev);
4871 if (netif_running(netdev)) {
4872 ixgbe_down(adapter);
4873 ixgbe_free_irq(adapter);
4874 ixgbe_free_all_tx_resources(adapter);
4875 ixgbe_free_all_rx_resources(adapter);
4878 ixgbe_clear_interrupt_scheme(adapter);
4880 kfree(adapter->ixgbe_ieee_pfc);
4881 kfree(adapter->ixgbe_ieee_ets);
4885 retval = pci_save_state(pdev);
4891 ixgbe_set_rx_mode(netdev);
4893 /* turn on all-multi mode if wake on multicast is enabled */
4894 if (wufc & IXGBE_WUFC_MC) {
4895 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4896 fctrl |= IXGBE_FCTRL_MPE;
4897 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4900 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4901 ctrl |= IXGBE_CTRL_GIO_DIS;
4902 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4904 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4906 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4907 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4910 switch (hw->mac.type) {
4911 case ixgbe_mac_82598EB:
4912 pci_wake_from_d3(pdev, false);
4914 case ixgbe_mac_82599EB:
4915 case ixgbe_mac_X540:
4916 pci_wake_from_d3(pdev, !!wufc);
4922 *enable_wake = !!wufc;
4924 ixgbe_release_hw_control(adapter);
4926 pci_disable_device(pdev);
4932 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4937 retval = __ixgbe_shutdown(pdev, &wake);
4942 pci_prepare_to_sleep(pdev);
4944 pci_wake_from_d3(pdev, false);
4945 pci_set_power_state(pdev, PCI_D3hot);
4950 #endif /* CONFIG_PM */
4952 static void ixgbe_shutdown(struct pci_dev *pdev)
4956 __ixgbe_shutdown(pdev, &wake);
4958 if (system_state == SYSTEM_POWER_OFF) {
4959 pci_wake_from_d3(pdev, wake);
4960 pci_set_power_state(pdev, PCI_D3hot);
4965 * ixgbe_update_stats - Update the board statistics counters.
4966 * @adapter: board private structure
4968 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4970 struct net_device *netdev = adapter->netdev;
4971 struct ixgbe_hw *hw = &adapter->hw;
4972 struct ixgbe_hw_stats *hwstats = &adapter->stats;
4974 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4975 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
4976 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
4977 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
4979 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4981 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
4982 #endif /* IXGBE_FCOE */
4984 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4985 test_bit(__IXGBE_RESETTING, &adapter->state))
4988 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4991 for (i = 0; i < 16; i++)
4992 adapter->hw_rx_no_dma_resources +=
4993 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4994 for (i = 0; i < adapter->num_rx_queues; i++) {
4995 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
4996 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
4998 adapter->rsc_total_count = rsc_count;
4999 adapter->rsc_total_flush = rsc_flush;
5002 for (i = 0; i < adapter->num_rx_queues; i++) {
5003 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5004 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5005 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5006 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5007 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5008 bytes += rx_ring->stats.bytes;
5009 packets += rx_ring->stats.packets;
5011 adapter->non_eop_descs = non_eop_descs;
5012 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5013 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5014 adapter->hw_csum_rx_error = hw_csum_rx_error;
5015 netdev->stats.rx_bytes = bytes;
5016 netdev->stats.rx_packets = packets;
5020 /* gather some stats to the adapter struct that are per queue */
5021 for (i = 0; i < adapter->num_tx_queues; i++) {
5022 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5023 restart_queue += tx_ring->tx_stats.restart_queue;
5024 tx_busy += tx_ring->tx_stats.tx_busy;
5025 bytes += tx_ring->stats.bytes;
5026 packets += tx_ring->stats.packets;
5028 adapter->restart_queue = restart_queue;
5029 adapter->tx_busy = tx_busy;
5030 netdev->stats.tx_bytes = bytes;
5031 netdev->stats.tx_packets = packets;
5033 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5035 /* 8 register reads */
5036 for (i = 0; i < 8; i++) {
5037 /* for packet buffers not used, the register should read 0 */
5038 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5040 hwstats->mpc[i] += mpc;
5041 total_mpc += hwstats->mpc[i];
5042 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5043 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5044 switch (hw->mac.type) {
5045 case ixgbe_mac_82598EB:
5046 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5047 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5048 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5049 hwstats->pxonrxc[i] +=
5050 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5052 case ixgbe_mac_82599EB:
5053 case ixgbe_mac_X540:
5054 hwstats->pxonrxc[i] +=
5055 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5062 /*16 register reads */
5063 for (i = 0; i < 16; i++) {
5064 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5065 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5066 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5067 (hw->mac.type == ixgbe_mac_X540)) {
5068 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5069 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5070 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5071 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5075 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5076 /* work around hardware counting issue */
5077 hwstats->gprc -= missed_rx;
5079 ixgbe_update_xoff_received(adapter);
5081 /* 82598 hardware only has a 32 bit counter in the high register */
5082 switch (hw->mac.type) {
5083 case ixgbe_mac_82598EB:
5084 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5085 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5086 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5087 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5089 case ixgbe_mac_X540:
5090 /* OS2BMC stats are X540 only*/
5091 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5092 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5093 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5094 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5095 case ixgbe_mac_82599EB:
5096 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5097 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5098 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5099 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5100 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5101 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5102 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5103 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5104 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5106 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5107 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5108 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5109 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5110 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5111 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5112 /* Add up per cpu counters for total ddp aloc fail */
5113 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5114 for_each_possible_cpu(cpu) {
5115 fcoe_noddp_counts_sum +=
5116 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5117 fcoe_noddp_ext_buff_counts_sum +=
5119 pcpu_noddp_ext_buff, cpu);
5122 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5123 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5124 #endif /* IXGBE_FCOE */
5129 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5130 hwstats->bprc += bprc;
5131 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5132 if (hw->mac.type == ixgbe_mac_82598EB)
5133 hwstats->mprc -= bprc;
5134 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5135 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5136 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5137 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5138 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5139 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5140 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5141 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5142 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5143 hwstats->lxontxc += lxon;
5144 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5145 hwstats->lxofftxc += lxoff;
5146 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5147 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5149 * 82598 errata - tx of flow control packets is included in tx counters
5151 xon_off_tot = lxon + lxoff;
5152 hwstats->gptc -= xon_off_tot;
5153 hwstats->mptc -= xon_off_tot;
5154 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5155 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5156 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5157 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5158 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5159 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5160 hwstats->ptc64 -= xon_off_tot;
5161 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5162 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5163 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5164 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5165 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5166 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5168 /* Fill out the OS statistics structure */
5169 netdev->stats.multicast = hwstats->mprc;
5172 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5173 netdev->stats.rx_dropped = 0;
5174 netdev->stats.rx_length_errors = hwstats->rlec;
5175 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5176 netdev->stats.rx_missed_errors = total_mpc;
5180 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5181 * @adapter - pointer to the device adapter structure
5183 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5185 struct ixgbe_hw *hw = &adapter->hw;
5188 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5191 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5193 /* if interface is down do nothing */
5194 if (test_bit(__IXGBE_DOWN, &adapter->state))
5197 /* do nothing if we are not using signature filters */
5198 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5201 adapter->fdir_overflow++;
5203 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5204 for (i = 0; i < adapter->num_tx_queues; i++)
5205 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5206 &(adapter->tx_ring[i]->state));
5207 /* re-enable flow director interrupts */
5208 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5210 e_err(probe, "failed to finish FDIR re-initialization, "
5211 "ignored adding FDIR ATR filters\n");
5216 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5217 * @adapter - pointer to the device adapter structure
5219 * This function serves two purposes. First it strobes the interrupt lines
5220 * in order to make certain interrupts are occurring. Secondly it sets the
5221 * bits needed to check for TX hangs. As a result we should immediately
5222 * determine if a hang has occurred.
5224 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5226 struct ixgbe_hw *hw = &adapter->hw;
5230 /* If we're down or resetting, just bail */
5231 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5232 test_bit(__IXGBE_RESETTING, &adapter->state))
5235 /* Force detection of hung controller */
5236 if (netif_carrier_ok(adapter->netdev)) {
5237 for (i = 0; i < adapter->num_tx_queues; i++)
5238 set_check_for_tx_hang(adapter->tx_ring[i]);
5241 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5243 * for legacy and MSI interrupts don't set any bits
5244 * that are enabled for EIAM, because this operation
5245 * would set *both* EIMS and EICS for any bit in EIAM
5247 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5248 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5250 /* get one bit for every active tx/rx interrupt vector */
5251 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5252 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5253 if (qv->rx.ring || qv->tx.ring)
5254 eics |= ((u64)1 << i);
5258 /* Cause software interrupt to ensure rings are cleaned */
5259 ixgbe_irq_rearm_queues(adapter, eics);
5264 * ixgbe_watchdog_update_link - update the link status
5265 * @adapter - pointer to the device adapter structure
5266 * @link_speed - pointer to a u32 to store the link_speed
5268 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5270 struct ixgbe_hw *hw = &adapter->hw;
5271 u32 link_speed = adapter->link_speed;
5272 bool link_up = adapter->link_up;
5275 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5278 if (hw->mac.ops.check_link) {
5279 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5281 /* always assume link is up, if no check link function */
5282 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5286 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5287 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5288 hw->mac.ops.fc_enable(hw, i);
5290 hw->mac.ops.fc_enable(hw, 0);
5295 time_after(jiffies, (adapter->link_check_timeout +
5296 IXGBE_TRY_LINK_TIMEOUT))) {
5297 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5298 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5299 IXGBE_WRITE_FLUSH(hw);
5302 adapter->link_up = link_up;
5303 adapter->link_speed = link_speed;
5307 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5308 * print link up message
5309 * @adapter - pointer to the device adapter structure
5311 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5313 struct net_device *netdev = adapter->netdev;
5314 struct ixgbe_hw *hw = &adapter->hw;
5315 u32 link_speed = adapter->link_speed;
5316 bool flow_rx, flow_tx;
5318 /* only continue if link was previously down */
5319 if (netif_carrier_ok(netdev))
5322 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5324 switch (hw->mac.type) {
5325 case ixgbe_mac_82598EB: {
5326 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5327 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5328 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5329 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5332 case ixgbe_mac_X540:
5333 case ixgbe_mac_82599EB: {
5334 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5335 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5336 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5337 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5345 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5346 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5348 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5350 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5353 ((flow_rx && flow_tx) ? "RX/TX" :
5355 (flow_tx ? "TX" : "None"))));
5357 netif_carrier_on(netdev);
5358 ixgbe_check_vf_rate_limit(adapter);
5362 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5363 * print link down message
5364 * @adapter - pointer to the adapter structure
5366 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5368 struct net_device *netdev = adapter->netdev;
5369 struct ixgbe_hw *hw = &adapter->hw;
5371 adapter->link_up = false;
5372 adapter->link_speed = 0;
5374 /* only continue if link was up previously */
5375 if (!netif_carrier_ok(netdev))
5378 /* poll for SFP+ cable when link is down */
5379 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5380 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5382 e_info(drv, "NIC Link is Down\n");
5383 netif_carrier_off(netdev);
5387 * ixgbe_watchdog_flush_tx - flush queues on link down
5388 * @adapter - pointer to the device adapter structure
5390 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5393 int some_tx_pending = 0;
5395 if (!netif_carrier_ok(adapter->netdev)) {
5396 for (i = 0; i < adapter->num_tx_queues; i++) {
5397 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5398 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5399 some_tx_pending = 1;
5404 if (some_tx_pending) {
5405 /* We've lost link, so the controller stops DMA,
5406 * but we've got queued Tx work that's never going
5407 * to get done, so reset controller to flush Tx.
5408 * (Do the reset outside of interrupt context).
5410 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5415 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5419 /* Do not perform spoof check for 82598 */
5420 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5423 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5426 * ssvpc register is cleared on read, if zero then no
5427 * spoofed packets in the last interval.
5432 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5436 * ixgbe_watchdog_subtask - check and bring link up
5437 * @adapter - pointer to the device adapter structure
5439 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5441 /* if interface is down do nothing */
5442 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5443 test_bit(__IXGBE_RESETTING, &adapter->state))
5446 ixgbe_watchdog_update_link(adapter);
5448 if (adapter->link_up)
5449 ixgbe_watchdog_link_is_up(adapter);
5451 ixgbe_watchdog_link_is_down(adapter);
5453 ixgbe_spoof_check(adapter);
5454 ixgbe_update_stats(adapter);
5456 ixgbe_watchdog_flush_tx(adapter);
5460 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5461 * @adapter - the ixgbe adapter structure
5463 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5465 struct ixgbe_hw *hw = &adapter->hw;
5468 /* not searching for SFP so there is nothing to do here */
5469 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5470 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5473 /* someone else is in init, wait until next service event */
5474 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5477 err = hw->phy.ops.identify_sfp(hw);
5478 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5481 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5482 /* If no cable is present, then we need to reset
5483 * the next time we find a good cable. */
5484 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5491 /* exit if reset not needed */
5492 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5495 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5498 * A module may be identified correctly, but the EEPROM may not have
5499 * support for that module. setup_sfp() will fail in that case, so
5500 * we should not allow that module to load.
5502 if (hw->mac.type == ixgbe_mac_82598EB)
5503 err = hw->phy.ops.reset(hw);
5505 err = hw->mac.ops.setup_sfp(hw);
5507 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5510 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5511 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5514 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5516 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5517 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5518 e_dev_err("failed to initialize because an unsupported "
5519 "SFP+ module type was detected.\n");
5520 e_dev_err("Reload the driver after installing a "
5521 "supported module.\n");
5522 unregister_netdev(adapter->netdev);
5527 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5528 * @adapter - the ixgbe adapter structure
5530 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5532 struct ixgbe_hw *hw = &adapter->hw;
5536 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5539 /* someone else is in init, wait until next service event */
5540 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5543 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5545 autoneg = hw->phy.autoneg_advertised;
5546 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5547 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5548 if (hw->mac.ops.setup_link)
5549 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5551 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5552 adapter->link_check_timeout = jiffies;
5553 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5556 #ifdef CONFIG_PCI_IOV
5557 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5560 struct ixgbe_hw *hw = &adapter->hw;
5561 struct net_device *netdev = adapter->netdev;
5565 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5566 if (gpc) /* If incrementing then no need for the check below */
5569 * Check to see if a bad DMA write target from an errant or
5570 * malicious VF has caused a PCIe error. If so then we can
5571 * issue a VFLR to the offending VF(s) and then resume without
5572 * requesting a full slot reset.
5575 for (vf = 0; vf < adapter->num_vfs; vf++) {
5576 ciaa = (vf << 16) | 0x80000000;
5577 /* 32 bit read so align, we really want status at offset 6 */
5578 ciaa |= PCI_COMMAND;
5579 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5580 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5582 /* disable debug mode asap after reading data */
5583 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5584 /* Get the upper 16 bits which will be the PCI status reg */
5586 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5587 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5589 ciaa = (vf << 16) | 0x80000000;
5591 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5592 ciad = 0x00008000; /* VFLR */
5593 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5595 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5602 * ixgbe_service_timer - Timer Call-back
5603 * @data: pointer to adapter cast into an unsigned long
5605 static void ixgbe_service_timer(unsigned long data)
5607 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5608 unsigned long next_event_offset;
5611 /* poll faster when waiting for link */
5612 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5613 next_event_offset = HZ / 10;
5615 next_event_offset = HZ * 2;
5617 #ifdef CONFIG_PCI_IOV
5619 * don't bother with SR-IOV VF DMA hang check if there are
5620 * no VFs or the link is down
5622 if (!adapter->num_vfs ||
5623 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5624 goto normal_timer_service;
5626 /* If we have VFs allocated then we must check for DMA hangs */
5627 ixgbe_check_for_bad_vf(adapter);
5628 next_event_offset = HZ / 50;
5629 adapter->timer_event_accumulator++;
5631 if (adapter->timer_event_accumulator >= 100)
5632 adapter->timer_event_accumulator = 0;
5636 normal_timer_service:
5638 /* Reset the timer */
5639 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5642 ixgbe_service_event_schedule(adapter);
5645 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5647 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5650 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5652 /* If we're already down or resetting, just bail */
5653 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5654 test_bit(__IXGBE_RESETTING, &adapter->state))
5657 ixgbe_dump(adapter);
5658 netdev_err(adapter->netdev, "Reset adapter\n");
5659 adapter->tx_timeout_count++;
5661 ixgbe_reinit_locked(adapter);
5665 * ixgbe_service_task - manages and runs subtasks
5666 * @work: pointer to work_struct containing our data
5668 static void ixgbe_service_task(struct work_struct *work)
5670 struct ixgbe_adapter *adapter = container_of(work,
5671 struct ixgbe_adapter,
5674 ixgbe_reset_subtask(adapter);
5675 ixgbe_sfp_detection_subtask(adapter);
5676 ixgbe_sfp_link_config_subtask(adapter);
5677 ixgbe_check_overtemp_subtask(adapter);
5678 ixgbe_watchdog_subtask(adapter);
5679 ixgbe_fdir_reinit_subtask(adapter);
5680 ixgbe_check_hang_subtask(adapter);
5682 ixgbe_service_event_complete(adapter);
5685 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5686 struct ixgbe_tx_buffer *first,
5689 struct sk_buff *skb = first->skb;
5690 u32 vlan_macip_lens, type_tucmd;
5691 u32 mss_l4len_idx, l4len;
5693 if (!skb_is_gso(skb))
5696 if (skb_header_cloned(skb)) {
5697 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5702 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5703 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5705 if (first->protocol == __constant_htons(ETH_P_IP)) {
5706 struct iphdr *iph = ip_hdr(skb);
5709 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5713 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5714 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5715 IXGBE_TX_FLAGS_CSUM |
5716 IXGBE_TX_FLAGS_IPV4;
5717 } else if (skb_is_gso_v6(skb)) {
5718 ipv6_hdr(skb)->payload_len = 0;
5719 tcp_hdr(skb)->check =
5720 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5721 &ipv6_hdr(skb)->daddr,
5723 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5724 IXGBE_TX_FLAGS_CSUM;
5727 /* compute header lengths */
5728 l4len = tcp_hdrlen(skb);
5729 *hdr_len = skb_transport_offset(skb) + l4len;
5731 /* update gso size and bytecount with header size */
5732 first->gso_segs = skb_shinfo(skb)->gso_segs;
5733 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5735 /* mss_l4len_id: use 1 as index for TSO */
5736 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5737 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5738 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5740 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5741 vlan_macip_lens = skb_network_header_len(skb);
5742 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5743 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5745 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5751 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5752 struct ixgbe_tx_buffer *first)
5754 struct sk_buff *skb = first->skb;
5755 u32 vlan_macip_lens = 0;
5756 u32 mss_l4len_idx = 0;
5759 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5760 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5761 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5765 switch (first->protocol) {
5766 case __constant_htons(ETH_P_IP):
5767 vlan_macip_lens |= skb_network_header_len(skb);
5768 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5769 l4_hdr = ip_hdr(skb)->protocol;
5771 case __constant_htons(ETH_P_IPV6):
5772 vlan_macip_lens |= skb_network_header_len(skb);
5773 l4_hdr = ipv6_hdr(skb)->nexthdr;
5776 if (unlikely(net_ratelimit())) {
5777 dev_warn(tx_ring->dev,
5778 "partial checksum but proto=%x!\n",
5786 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5787 mss_l4len_idx = tcp_hdrlen(skb) <<
5788 IXGBE_ADVTXD_L4LEN_SHIFT;
5791 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5792 mss_l4len_idx = sizeof(struct sctphdr) <<
5793 IXGBE_ADVTXD_L4LEN_SHIFT;
5796 mss_l4len_idx = sizeof(struct udphdr) <<
5797 IXGBE_ADVTXD_L4LEN_SHIFT;
5800 if (unlikely(net_ratelimit())) {
5801 dev_warn(tx_ring->dev,
5802 "partial checksum but l4 proto=%x!\n",
5808 /* update TX checksum flag */
5809 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
5812 /* vlan_macip_lens: MACLEN, VLAN tag */
5813 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5814 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5816 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5817 type_tucmd, mss_l4len_idx);
5820 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
5822 /* set type for advanced descriptor with frame checksum insertion */
5823 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5824 IXGBE_ADVTXD_DCMD_IFCS |
5825 IXGBE_ADVTXD_DCMD_DEXT);
5827 /* set HW vlan bit if vlan is present */
5828 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
5829 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
5831 /* set segmentation enable bits for TSO/FSO */
5833 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
5835 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5837 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
5842 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5843 u32 tx_flags, unsigned int paylen)
5845 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
5847 /* enable L4 checksum for TSO and TX checksum offload */
5848 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5849 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
5851 /* enble IPv4 checksum for TSO */
5852 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5853 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
5855 /* use index 1 context for TSO/FSO/FCOE */
5857 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5859 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5861 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5864 * Check Context must be set if Tx switch is enabled, which it
5865 * always is for case where virtual functions are running
5868 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5870 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
5872 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5874 tx_desc->read.olinfo_status = olinfo_status;
5877 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5880 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
5881 struct ixgbe_tx_buffer *first,
5885 struct sk_buff *skb = first->skb;
5886 struct ixgbe_tx_buffer *tx_buffer;
5887 union ixgbe_adv_tx_desc *tx_desc;
5888 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
5889 unsigned int data_len = skb->data_len;
5890 unsigned int size = skb_headlen(skb);
5891 unsigned int paylen = skb->len - hdr_len;
5892 u32 tx_flags = first->tx_flags;
5894 u16 i = tx_ring->next_to_use;
5896 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5898 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5899 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5902 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5903 if (data_len < sizeof(struct fcoe_crc_eof)) {
5904 size -= sizeof(struct fcoe_crc_eof) - data_len;
5907 data_len -= sizeof(struct fcoe_crc_eof);
5912 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5913 if (dma_mapping_error(tx_ring->dev, dma))
5916 /* record length, and DMA address */
5917 dma_unmap_len_set(first, len, size);
5918 dma_unmap_addr_set(first, dma, dma);
5920 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5923 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
5924 tx_desc->read.cmd_type_len =
5925 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
5929 if (i == tx_ring->count) {
5930 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5934 dma += IXGBE_MAX_DATA_PER_TXD;
5935 size -= IXGBE_MAX_DATA_PER_TXD;
5937 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5938 tx_desc->read.olinfo_status = 0;
5941 if (likely(!data_len))
5944 if (unlikely(skb->no_fcs))
5945 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
5946 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
5950 if (i == tx_ring->count) {
5951 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5956 size = min_t(unsigned int, data_len, skb_frag_size(frag));
5958 size = skb_frag_size(frag);
5962 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
5964 if (dma_mapping_error(tx_ring->dev, dma))
5967 tx_buffer = &tx_ring->tx_buffer_info[i];
5968 dma_unmap_len_set(tx_buffer, len, size);
5969 dma_unmap_addr_set(tx_buffer, dma, dma);
5971 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5972 tx_desc->read.olinfo_status = 0;
5977 /* write last descriptor with RS and EOP bits */
5978 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
5979 tx_desc->read.cmd_type_len = cmd_type;
5981 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5983 /* set the timestamp */
5984 first->time_stamp = jiffies;
5987 * Force memory writes to complete before letting h/w know there
5988 * are new descriptors to fetch. (Only applicable for weak-ordered
5989 * memory model archs, such as IA-64).
5991 * We also need this memory barrier to make certain all of the
5992 * status bits have been updated before next_to_watch is written.
5996 /* set next_to_watch value indicating a packet is present */
5997 first->next_to_watch = tx_desc;
6000 if (i == tx_ring->count)
6003 tx_ring->next_to_use = i;
6005 /* notify HW of packet */
6006 writel(i, tx_ring->tail);
6010 dev_err(tx_ring->dev, "TX DMA map failed\n");
6012 /* clear dma mappings for failed tx_buffer_info map */
6014 tx_buffer = &tx_ring->tx_buffer_info[i];
6015 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6016 if (tx_buffer == first)
6023 tx_ring->next_to_use = i;
6026 static void ixgbe_atr(struct ixgbe_ring *ring,
6027 struct ixgbe_tx_buffer *first)
6029 struct ixgbe_q_vector *q_vector = ring->q_vector;
6030 union ixgbe_atr_hash_dword input = { .dword = 0 };
6031 union ixgbe_atr_hash_dword common = { .dword = 0 };
6033 unsigned char *network;
6035 struct ipv6hdr *ipv6;
6040 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6044 /* do nothing if sampling is disabled */
6045 if (!ring->atr_sample_rate)
6050 /* snag network header to get L4 type and address */
6051 hdr.network = skb_network_header(first->skb);
6053 /* Currently only IPv4/IPv6 with TCP is supported */
6054 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6055 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6056 (first->protocol != __constant_htons(ETH_P_IP) ||
6057 hdr.ipv4->protocol != IPPROTO_TCP))
6060 th = tcp_hdr(first->skb);
6062 /* skip this packet since it is invalid or the socket is closing */
6066 /* sample on all syn packets or once every atr sample count */
6067 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6070 /* reset sample count */
6071 ring->atr_count = 0;
6073 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6076 * src and dst are inverted, think how the receiver sees them
6078 * The input is broken into two sections, a non-compressed section
6079 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6080 * is XORed together and stored in the compressed dword.
6082 input.formatted.vlan_id = vlan_id;
6085 * since src port and flex bytes occupy the same word XOR them together
6086 * and write the value to source port portion of compressed dword
6088 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6089 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6091 common.port.src ^= th->dest ^ first->protocol;
6092 common.port.dst ^= th->source;
6094 if (first->protocol == __constant_htons(ETH_P_IP)) {
6095 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6096 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6098 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6099 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6100 hdr.ipv6->saddr.s6_addr32[1] ^
6101 hdr.ipv6->saddr.s6_addr32[2] ^
6102 hdr.ipv6->saddr.s6_addr32[3] ^
6103 hdr.ipv6->daddr.s6_addr32[0] ^
6104 hdr.ipv6->daddr.s6_addr32[1] ^
6105 hdr.ipv6->daddr.s6_addr32[2] ^
6106 hdr.ipv6->daddr.s6_addr32[3];
6109 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6110 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6111 input, common, ring->queue_index);
6114 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6116 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6117 /* Herbert's original patch had:
6118 * smp_mb__after_netif_stop_queue();
6119 * but since that doesn't exist yet, just open code it. */
6122 /* We need to check again in a case another CPU has just
6123 * made room available. */
6124 if (likely(ixgbe_desc_unused(tx_ring) < size))
6127 /* A reprieve! - use start_queue because it doesn't call schedule */
6128 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6129 ++tx_ring->tx_stats.restart_queue;
6133 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6135 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6137 return __ixgbe_maybe_stop_tx(tx_ring, size);
6140 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6142 struct ixgbe_adapter *adapter = netdev_priv(dev);
6143 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6146 __be16 protocol = vlan_get_protocol(skb);
6148 if (((protocol == htons(ETH_P_FCOE)) ||
6149 (protocol == htons(ETH_P_FIP))) &&
6150 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6151 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6152 txq += adapter->ring_feature[RING_F_FCOE].mask;
6157 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6158 while (unlikely(txq >= dev->real_num_tx_queues))
6159 txq -= dev->real_num_tx_queues;
6163 return skb_tx_hash(dev, skb);
6166 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6167 struct ixgbe_adapter *adapter,
6168 struct ixgbe_ring *tx_ring)
6170 struct ixgbe_tx_buffer *first;
6173 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6176 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6177 __be16 protocol = skb->protocol;
6181 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6182 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6183 * + 2 desc gap to keep tail from touching head,
6184 * + 1 desc for context descriptor,
6185 * otherwise try next time
6187 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6188 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6189 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6191 count += skb_shinfo(skb)->nr_frags;
6193 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6194 tx_ring->tx_stats.tx_busy++;
6195 return NETDEV_TX_BUSY;
6198 /* record the location of the first descriptor for this packet */
6199 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6201 first->bytecount = skb->len;
6202 first->gso_segs = 1;
6204 /* if we have a HW VLAN tag being added default to the HW one */
6205 if (vlan_tx_tag_present(skb)) {
6206 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6207 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6208 /* else if it is a SW VLAN check the next protocol and store the tag */
6209 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6210 struct vlan_hdr *vhdr, _vhdr;
6211 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6215 protocol = vhdr->h_vlan_encapsulated_proto;
6216 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6217 IXGBE_TX_FLAGS_VLAN_SHIFT;
6218 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6221 #ifdef CONFIG_PCI_IOV
6223 * Use the l2switch_enable flag - would be false if the DMA
6224 * Tx switch had been disabled.
6226 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6227 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6230 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6231 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6232 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6233 (skb->priority != TC_PRIO_CONTROL))) {
6234 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6235 tx_flags |= (skb->priority & 0x7) <<
6236 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6237 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6238 struct vlan_ethhdr *vhdr;
6239 if (skb_header_cloned(skb) &&
6240 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6242 vhdr = (struct vlan_ethhdr *)skb->data;
6243 vhdr->h_vlan_TCI = htons(tx_flags >>
6244 IXGBE_TX_FLAGS_VLAN_SHIFT);
6246 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6250 /* record initial flags and protocol */
6251 first->tx_flags = tx_flags;
6252 first->protocol = protocol;
6255 /* setup tx offload for FCoE */
6256 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6257 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6258 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6265 #endif /* IXGBE_FCOE */
6266 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6270 ixgbe_tx_csum(tx_ring, first);
6272 /* add the ATR filter if ATR is on */
6273 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6274 ixgbe_atr(tx_ring, first);
6278 #endif /* IXGBE_FCOE */
6279 ixgbe_tx_map(tx_ring, first, hdr_len);
6281 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6283 return NETDEV_TX_OK;
6286 dev_kfree_skb_any(first->skb);
6289 return NETDEV_TX_OK;
6292 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6293 struct net_device *netdev)
6295 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6296 struct ixgbe_ring *tx_ring;
6298 if (skb->len <= 0) {
6299 dev_kfree_skb_any(skb);
6300 return NETDEV_TX_OK;
6304 * The minimum packet size for olinfo paylen is 17 so pad the skb
6305 * in order to meet this minimum size requirement.
6307 if (skb->len < 17) {
6308 if (skb_padto(skb, 17))
6309 return NETDEV_TX_OK;
6313 tx_ring = adapter->tx_ring[skb->queue_mapping];
6314 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6318 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6319 * @netdev: network interface device structure
6320 * @p: pointer to an address structure
6322 * Returns 0 on success, negative on failure
6324 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6326 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6327 struct ixgbe_hw *hw = &adapter->hw;
6328 struct sockaddr *addr = p;
6330 if (!is_valid_ether_addr(addr->sa_data))
6331 return -EADDRNOTAVAIL;
6333 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6334 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6336 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6343 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6345 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6346 struct ixgbe_hw *hw = &adapter->hw;
6350 if (prtad != hw->phy.mdio.prtad)
6352 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6358 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6359 u16 addr, u16 value)
6361 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6362 struct ixgbe_hw *hw = &adapter->hw;
6364 if (prtad != hw->phy.mdio.prtad)
6366 return hw->phy.ops.write_reg(hw, addr, devad, value);
6369 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6371 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6373 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6377 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6379 * @netdev: network interface device structure
6381 * Returns non-zero on failure
6383 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6386 struct ixgbe_adapter *adapter = netdev_priv(dev);
6387 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6389 if (is_valid_ether_addr(mac->san_addr)) {
6391 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6398 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6400 * @netdev: network interface device structure
6402 * Returns non-zero on failure
6404 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6407 struct ixgbe_adapter *adapter = netdev_priv(dev);
6408 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6410 if (is_valid_ether_addr(mac->san_addr)) {
6412 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6418 #ifdef CONFIG_NET_POLL_CONTROLLER
6420 * Polling 'interrupt' - used by things like netconsole to send skbs
6421 * without having to re-enable interrupts. It's not called while
6422 * the interrupt routine is executing.
6424 static void ixgbe_netpoll(struct net_device *netdev)
6426 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6429 /* if interface is down do nothing */
6430 if (test_bit(__IXGBE_DOWN, &adapter->state))
6433 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6434 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6435 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6436 for (i = 0; i < num_q_vectors; i++) {
6437 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6438 ixgbe_msix_clean_rings(0, q_vector);
6441 ixgbe_intr(adapter->pdev->irq, netdev);
6443 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6447 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6448 struct rtnl_link_stats64 *stats)
6450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6454 for (i = 0; i < adapter->num_rx_queues; i++) {
6455 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6461 start = u64_stats_fetch_begin_bh(&ring->syncp);
6462 packets = ring->stats.packets;
6463 bytes = ring->stats.bytes;
6464 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6465 stats->rx_packets += packets;
6466 stats->rx_bytes += bytes;
6470 for (i = 0; i < adapter->num_tx_queues; i++) {
6471 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6477 start = u64_stats_fetch_begin_bh(&ring->syncp);
6478 packets = ring->stats.packets;
6479 bytes = ring->stats.bytes;
6480 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6481 stats->tx_packets += packets;
6482 stats->tx_bytes += bytes;
6486 /* following stats updated by ixgbe_watchdog_task() */
6487 stats->multicast = netdev->stats.multicast;
6488 stats->rx_errors = netdev->stats.rx_errors;
6489 stats->rx_length_errors = netdev->stats.rx_length_errors;
6490 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6491 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6495 #ifdef CONFIG_IXGBE_DCB
6496 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6497 * #adapter: pointer to ixgbe_adapter
6498 * @tc: number of traffic classes currently enabled
6500 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6501 * 802.1Q priority maps to a packet buffer that exists.
6503 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6505 struct ixgbe_hw *hw = &adapter->hw;
6509 /* 82598 have a static priority to TC mapping that can not
6510 * be changed so no validation is needed.
6512 if (hw->mac.type == ixgbe_mac_82598EB)
6515 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6518 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6519 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6521 /* If up2tc is out of bounds default to zero */
6523 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6527 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6532 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6535 * @netdev: net device to configure
6536 * @tc: number of traffic classes to enable
6538 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6540 struct ixgbe_adapter *adapter = netdev_priv(dev);
6541 struct ixgbe_hw *hw = &adapter->hw;
6543 /* Multiple traffic classes requires multiple queues */
6544 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6545 e_err(drv, "Enable failed, needs MSI-X\n");
6549 /* Hardware supports up to 8 traffic classes */
6550 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6551 (hw->mac.type == ixgbe_mac_82598EB &&
6552 tc < MAX_TRAFFIC_CLASS))
6555 /* Hardware has to reinitialize queues and interrupts to
6556 * match packet buffer alignment. Unfortunately, the
6557 * hardware is not flexible enough to do this dynamically.
6559 if (netif_running(dev))
6561 ixgbe_clear_interrupt_scheme(adapter);
6564 netdev_set_num_tc(dev, tc);
6565 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6566 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6567 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6569 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6570 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6572 netdev_reset_tc(dev);
6573 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6575 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6576 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6578 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6579 adapter->dcb_cfg.pfc_mode_enable = false;
6582 ixgbe_init_interrupt_scheme(adapter);
6583 ixgbe_validate_rtr(adapter, tc);
6584 if (netif_running(dev))
6590 #endif /* CONFIG_IXGBE_DCB */
6591 void ixgbe_do_reset(struct net_device *netdev)
6593 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6595 if (netif_running(netdev))
6596 ixgbe_reinit_locked(adapter);
6598 ixgbe_reset(adapter);
6601 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6602 netdev_features_t features)
6604 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6607 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6608 features &= ~NETIF_F_HW_VLAN_RX;
6611 /* return error if RXHASH is being enabled when RSS is not supported */
6612 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6613 features &= ~NETIF_F_RXHASH;
6615 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6616 if (!(features & NETIF_F_RXCSUM))
6617 features &= ~NETIF_F_LRO;
6619 /* Turn off LRO if not RSC capable */
6620 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6621 features &= ~NETIF_F_LRO;
6627 static int ixgbe_set_features(struct net_device *netdev,
6628 netdev_features_t features)
6630 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6631 netdev_features_t changed = netdev->features ^ features;
6632 bool need_reset = false;
6634 /* Make sure RSC matches LRO, reset if change */
6635 if (!(features & NETIF_F_LRO)) {
6636 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6638 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6639 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6640 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6641 if (adapter->rx_itr_setting == 1 ||
6642 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6643 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6645 } else if ((changed ^ features) & NETIF_F_LRO) {
6646 e_info(probe, "rx-usecs set too low, "
6652 * Check if Flow Director n-tuple support was enabled or disabled. If
6653 * the state changed, we need to reset.
6655 if (!(features & NETIF_F_NTUPLE)) {
6656 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6657 /* turn off Flow Director, set ATR and reset */
6658 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6659 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6660 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6663 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6664 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6665 /* turn off ATR, enable perfect filters and reset */
6666 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6667 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6671 if (changed & NETIF_F_RXALL)
6674 netdev->features = features;
6676 ixgbe_do_reset(netdev);
6681 static const struct net_device_ops ixgbe_netdev_ops = {
6682 .ndo_open = ixgbe_open,
6683 .ndo_stop = ixgbe_close,
6684 .ndo_start_xmit = ixgbe_xmit_frame,
6685 .ndo_select_queue = ixgbe_select_queue,
6686 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6687 .ndo_validate_addr = eth_validate_addr,
6688 .ndo_set_mac_address = ixgbe_set_mac,
6689 .ndo_change_mtu = ixgbe_change_mtu,
6690 .ndo_tx_timeout = ixgbe_tx_timeout,
6691 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6692 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6693 .ndo_do_ioctl = ixgbe_ioctl,
6694 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6695 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6696 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6697 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
6698 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6699 .ndo_get_stats64 = ixgbe_get_stats64,
6700 #ifdef CONFIG_IXGBE_DCB
6701 .ndo_setup_tc = ixgbe_setup_tc,
6703 #ifdef CONFIG_NET_POLL_CONTROLLER
6704 .ndo_poll_controller = ixgbe_netpoll,
6707 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6708 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6709 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6710 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6711 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6712 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6713 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
6714 #endif /* IXGBE_FCOE */
6715 .ndo_set_features = ixgbe_set_features,
6716 .ndo_fix_features = ixgbe_fix_features,
6719 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6720 const struct ixgbe_info *ii)
6722 #ifdef CONFIG_PCI_IOV
6723 struct ixgbe_hw *hw = &adapter->hw;
6725 if (hw->mac.type == ixgbe_mac_82598EB)
6728 /* The 82599 supports up to 64 VFs per physical function
6729 * but this implementation limits allocation to 63 so that
6730 * basic networking resources are still available to the
6733 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6734 ixgbe_enable_sriov(adapter, ii);
6735 #endif /* CONFIG_PCI_IOV */
6739 * ixgbe_probe - Device Initialization Routine
6740 * @pdev: PCI device information struct
6741 * @ent: entry in ixgbe_pci_tbl
6743 * Returns 0 on success, negative on failure
6745 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6746 * The OS initialization, configuring of the adapter private structure,
6747 * and a hardware reset occur.
6749 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6750 const struct pci_device_id *ent)
6752 struct net_device *netdev;
6753 struct ixgbe_adapter *adapter = NULL;
6754 struct ixgbe_hw *hw;
6755 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6756 static int cards_found;
6757 int i, err, pci_using_dac;
6758 u8 part_str[IXGBE_PBANUM_LENGTH];
6759 unsigned int indices = num_possible_cpus();
6766 /* Catch broken hardware that put the wrong VF device ID in
6767 * the PCIe SR-IOV capability.
6769 if (pdev->is_virtfn) {
6770 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6771 pci_name(pdev), pdev->vendor, pdev->device);
6775 err = pci_enable_device_mem(pdev);
6779 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6780 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6783 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6785 err = dma_set_coherent_mask(&pdev->dev,
6789 "No usable DMA configuration, aborting\n");
6796 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6797 IORESOURCE_MEM), ixgbe_driver_name);
6800 "pci_request_selected_regions failed 0x%x\n", err);
6804 pci_enable_pcie_error_reporting(pdev);
6806 pci_set_master(pdev);
6807 pci_save_state(pdev);
6809 #ifdef CONFIG_IXGBE_DCB
6810 indices *= MAX_TRAFFIC_CLASS;
6813 if (ii->mac == ixgbe_mac_82598EB)
6814 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6816 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6819 indices += min_t(unsigned int, num_possible_cpus(),
6820 IXGBE_MAX_FCOE_INDICES);
6822 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6825 goto err_alloc_etherdev;
6828 SET_NETDEV_DEV(netdev, &pdev->dev);
6830 adapter = netdev_priv(netdev);
6831 pci_set_drvdata(pdev, adapter);
6833 adapter->netdev = netdev;
6834 adapter->pdev = pdev;
6837 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6839 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6840 pci_resource_len(pdev, 0));
6846 for (i = 1; i <= 5; i++) {
6847 if (pci_resource_len(pdev, i) == 0)
6851 netdev->netdev_ops = &ixgbe_netdev_ops;
6852 ixgbe_set_ethtool_ops(netdev);
6853 netdev->watchdog_timeo = 5 * HZ;
6854 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6856 adapter->bd_number = cards_found;
6859 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6860 hw->mac.type = ii->mac;
6863 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6864 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6865 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6866 if (!(eec & (1 << 8)))
6867 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6870 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6871 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6872 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6873 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6874 hw->phy.mdio.mmds = 0;
6875 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6876 hw->phy.mdio.dev = netdev;
6877 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6878 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6880 ii->get_invariants(hw);
6882 /* setup the private structure */
6883 err = ixgbe_sw_init(adapter);
6887 /* Make it possible the adapter to be woken up via WOL */
6888 switch (adapter->hw.mac.type) {
6889 case ixgbe_mac_82599EB:
6890 case ixgbe_mac_X540:
6891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6898 * If there is a fan on this device and it has failed log the
6901 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6902 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6903 if (esdp & IXGBE_ESDP_SDP1)
6904 e_crit(probe, "Fan has stopped, replace the adapter\n");
6907 if (allow_unsupported_sfp)
6908 hw->allow_unsupported_sfp = allow_unsupported_sfp;
6910 /* reset_hw fills in the perm_addr as well */
6911 hw->phy.reset_if_overtemp = true;
6912 err = hw->mac.ops.reset_hw(hw);
6913 hw->phy.reset_if_overtemp = false;
6914 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6915 hw->mac.type == ixgbe_mac_82598EB) {
6917 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6918 e_dev_err("failed to load because an unsupported SFP+ "
6919 "module type was detected.\n");
6920 e_dev_err("Reload the driver after installing a supported "
6924 e_dev_err("HW Init failed: %d\n", err);
6928 ixgbe_probe_vf(adapter, ii);
6930 netdev->features = NETIF_F_SG |
6933 NETIF_F_HW_VLAN_TX |
6934 NETIF_F_HW_VLAN_RX |
6935 NETIF_F_HW_VLAN_FILTER |
6941 netdev->hw_features = netdev->features;
6943 switch (adapter->hw.mac.type) {
6944 case ixgbe_mac_82599EB:
6945 case ixgbe_mac_X540:
6946 netdev->features |= NETIF_F_SCTP_CSUM;
6947 netdev->hw_features |= NETIF_F_SCTP_CSUM |
6954 netdev->hw_features |= NETIF_F_RXALL;
6956 netdev->vlan_features |= NETIF_F_TSO;
6957 netdev->vlan_features |= NETIF_F_TSO6;
6958 netdev->vlan_features |= NETIF_F_IP_CSUM;
6959 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6960 netdev->vlan_features |= NETIF_F_SG;
6962 netdev->priv_flags |= IFF_UNICAST_FLT;
6963 netdev->priv_flags |= IFF_SUPP_NOFCS;
6965 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6966 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6967 IXGBE_FLAG_DCB_ENABLED);
6969 #ifdef CONFIG_IXGBE_DCB
6970 netdev->dcbnl_ops = &dcbnl_ops;
6974 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6975 if (hw->mac.ops.get_device_caps) {
6976 hw->mac.ops.get_device_caps(hw, &device_caps);
6977 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6978 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6981 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6982 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6983 netdev->vlan_features |= NETIF_F_FSO;
6984 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6986 #endif /* IXGBE_FCOE */
6987 if (pci_using_dac) {
6988 netdev->features |= NETIF_F_HIGHDMA;
6989 netdev->vlan_features |= NETIF_F_HIGHDMA;
6992 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
6993 netdev->hw_features |= NETIF_F_LRO;
6994 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6995 netdev->features |= NETIF_F_LRO;
6997 /* make sure the EEPROM is good */
6998 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6999 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7004 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7005 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7007 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7008 e_dev_err("invalid MAC address\n");
7013 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7014 (unsigned long) adapter);
7016 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7017 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7019 err = ixgbe_init_interrupt_scheme(adapter);
7023 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7024 netdev->hw_features &= ~NETIF_F_RXHASH;
7025 netdev->features &= ~NETIF_F_RXHASH;
7028 /* WOL not supported for all but the following */
7030 switch (pdev->device) {
7031 case IXGBE_DEV_ID_82599_SFP:
7032 /* Only these subdevice supports WOL */
7033 switch (pdev->subsystem_device) {
7034 case IXGBE_SUBDEV_ID_82599_560FLR:
7035 /* only support first port */
7036 if (hw->bus.func != 0)
7038 case IXGBE_SUBDEV_ID_82599_SFP:
7039 adapter->wol = IXGBE_WUFC_MAG;
7043 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7044 /* All except this subdevice support WOL */
7045 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7046 adapter->wol = IXGBE_WUFC_MAG;
7048 case IXGBE_DEV_ID_82599_KX4:
7049 adapter->wol = IXGBE_WUFC_MAG;
7051 case IXGBE_DEV_ID_X540T:
7052 /* Check eeprom to see if it is enabled */
7053 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7054 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7056 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7057 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7058 (hw->bus.func == 0)))
7059 adapter->wol = IXGBE_WUFC_MAG;
7062 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7064 /* save off EEPROM version number */
7065 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7066 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7068 /* pick up the PCI bus settings for reporting later */
7069 hw->mac.ops.get_bus_info(hw);
7071 /* print bus type/speed/width info */
7072 e_dev_info("(PCI Express:%s:%s) %pM\n",
7073 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7074 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7076 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7077 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7078 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7082 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7084 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7085 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7086 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7087 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7090 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7091 hw->mac.type, hw->phy.type, part_str);
7093 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7094 e_dev_warn("PCI-Express bandwidth available for this card is "
7095 "not sufficient for optimal performance.\n");
7096 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7100 /* reset the hardware with the new settings */
7101 err = hw->mac.ops.start_hw(hw);
7102 if (err == IXGBE_ERR_EEPROM_VERSION) {
7103 /* We are running on a pre-production device, log a warning */
7104 e_dev_warn("This device is a pre-production adapter/LOM. "
7105 "Please be aware there may be issues associated "
7106 "with your hardware. If you are experiencing "
7107 "problems please contact your Intel or hardware "
7108 "representative who provided you with this "
7111 strcpy(netdev->name, "eth%d");
7112 err = register_netdev(netdev);
7116 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7117 if (hw->mac.ops.disable_tx_laser &&
7118 ((hw->phy.multispeed_fiber) ||
7119 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7120 (hw->mac.type == ixgbe_mac_82599EB))))
7121 hw->mac.ops.disable_tx_laser(hw);
7123 /* carrier off reporting is important to ethtool even BEFORE open */
7124 netif_carrier_off(netdev);
7126 #ifdef CONFIG_IXGBE_DCA
7127 if (dca_add_requester(&pdev->dev) == 0) {
7128 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7129 ixgbe_setup_dca(adapter);
7132 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7133 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7134 for (i = 0; i < adapter->num_vfs; i++)
7135 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7138 /* firmware requires driver version to be 0xFFFFFFFF
7139 * since os does not support feature
7141 if (hw->mac.ops.set_fw_drv_ver)
7142 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7145 /* add san mac addr to netdev */
7146 ixgbe_add_sanmac_netdev(netdev);
7148 e_dev_info("%s\n", ixgbe_default_device_descr);
7153 ixgbe_release_hw_control(adapter);
7154 ixgbe_clear_interrupt_scheme(adapter);
7156 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7157 ixgbe_disable_sriov(adapter);
7158 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7159 iounmap(hw->hw_addr);
7161 free_netdev(netdev);
7163 pci_release_selected_regions(pdev,
7164 pci_select_bars(pdev, IORESOURCE_MEM));
7167 pci_disable_device(pdev);
7172 * ixgbe_remove - Device Removal Routine
7173 * @pdev: PCI device information struct
7175 * ixgbe_remove is called by the PCI subsystem to alert the driver
7176 * that it should release a PCI device. The could be caused by a
7177 * Hot-Plug event, or because the driver is going to be removed from
7180 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7182 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7183 struct net_device *netdev = adapter->netdev;
7185 set_bit(__IXGBE_DOWN, &adapter->state);
7186 cancel_work_sync(&adapter->service_task);
7188 #ifdef CONFIG_IXGBE_DCA
7189 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7190 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7191 dca_remove_requester(&pdev->dev);
7192 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7197 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7198 ixgbe_cleanup_fcoe(adapter);
7200 #endif /* IXGBE_FCOE */
7202 /* remove the added san mac */
7203 ixgbe_del_sanmac_netdev(netdev);
7205 if (netdev->reg_state == NETREG_REGISTERED)
7206 unregister_netdev(netdev);
7208 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7209 if (!(ixgbe_check_vf_assignment(adapter)))
7210 ixgbe_disable_sriov(adapter);
7212 e_dev_warn("Unloading driver while VFs are assigned "
7213 "- VFs will not be deallocated\n");
7216 ixgbe_clear_interrupt_scheme(adapter);
7218 ixgbe_release_hw_control(adapter);
7220 iounmap(adapter->hw.hw_addr);
7221 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7224 e_dev_info("complete\n");
7226 free_netdev(netdev);
7228 pci_disable_pcie_error_reporting(pdev);
7230 pci_disable_device(pdev);
7234 * ixgbe_io_error_detected - called when PCI error is detected
7235 * @pdev: Pointer to PCI device
7236 * @state: The current pci connection state
7238 * This function is called after a PCI bus error affecting
7239 * this device has been detected.
7241 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7242 pci_channel_state_t state)
7244 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7245 struct net_device *netdev = adapter->netdev;
7247 #ifdef CONFIG_PCI_IOV
7248 struct pci_dev *bdev, *vfdev;
7249 u32 dw0, dw1, dw2, dw3;
7251 u16 req_id, pf_func;
7253 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7254 adapter->num_vfs == 0)
7255 goto skip_bad_vf_detection;
7257 bdev = pdev->bus->self;
7258 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7259 bdev = bdev->bus->self;
7262 goto skip_bad_vf_detection;
7264 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7266 goto skip_bad_vf_detection;
7268 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7269 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7270 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7271 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7274 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7275 if (!(req_id & 0x0080))
7276 goto skip_bad_vf_detection;
7278 pf_func = req_id & 0x01;
7279 if ((pf_func & 1) == (pdev->devfn & 1)) {
7280 unsigned int device_id;
7282 vf = (req_id & 0x7F) >> 1;
7283 e_dev_err("VF %d has caused a PCIe error\n", vf);
7284 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7285 "%8.8x\tdw3: %8.8x\n",
7286 dw0, dw1, dw2, dw3);
7287 switch (adapter->hw.mac.type) {
7288 case ixgbe_mac_82599EB:
7289 device_id = IXGBE_82599_VF_DEVICE_ID;
7291 case ixgbe_mac_X540:
7292 device_id = IXGBE_X540_VF_DEVICE_ID;
7299 /* Find the pci device of the offending VF */
7300 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7302 if (vfdev->devfn == (req_id & 0xFF))
7304 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7308 * There's a slim chance the VF could have been hot plugged,
7309 * so if it is no longer present we don't need to issue the
7310 * VFLR. Just clean up the AER in that case.
7313 e_dev_err("Issuing VFLR to VF %d\n", vf);
7314 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7317 pci_cleanup_aer_uncorrect_error_status(pdev);
7321 * Even though the error may have occurred on the other port
7322 * we still need to increment the vf error reference count for
7323 * both ports because the I/O resume function will be called
7326 adapter->vferr_refcount++;
7328 return PCI_ERS_RESULT_RECOVERED;
7330 skip_bad_vf_detection:
7331 #endif /* CONFIG_PCI_IOV */
7332 netif_device_detach(netdev);
7334 if (state == pci_channel_io_perm_failure)
7335 return PCI_ERS_RESULT_DISCONNECT;
7337 if (netif_running(netdev))
7338 ixgbe_down(adapter);
7339 pci_disable_device(pdev);
7341 /* Request a slot reset. */
7342 return PCI_ERS_RESULT_NEED_RESET;
7346 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7347 * @pdev: Pointer to PCI device
7349 * Restart the card from scratch, as if from a cold-boot.
7351 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7353 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7354 pci_ers_result_t result;
7357 if (pci_enable_device_mem(pdev)) {
7358 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7359 result = PCI_ERS_RESULT_DISCONNECT;
7361 pci_set_master(pdev);
7362 pci_restore_state(pdev);
7363 pci_save_state(pdev);
7365 pci_wake_from_d3(pdev, false);
7367 ixgbe_reset(adapter);
7368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7369 result = PCI_ERS_RESULT_RECOVERED;
7372 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7374 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7375 "failed 0x%0x\n", err);
7376 /* non-fatal, continue */
7383 * ixgbe_io_resume - called when traffic can start flowing again.
7384 * @pdev: Pointer to PCI device
7386 * This callback is called when the error recovery driver tells us that
7387 * its OK to resume normal operation.
7389 static void ixgbe_io_resume(struct pci_dev *pdev)
7391 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7392 struct net_device *netdev = adapter->netdev;
7394 #ifdef CONFIG_PCI_IOV
7395 if (adapter->vferr_refcount) {
7396 e_info(drv, "Resuming after VF err\n");
7397 adapter->vferr_refcount--;
7402 if (netif_running(netdev))
7405 netif_device_attach(netdev);
7408 static struct pci_error_handlers ixgbe_err_handler = {
7409 .error_detected = ixgbe_io_error_detected,
7410 .slot_reset = ixgbe_io_slot_reset,
7411 .resume = ixgbe_io_resume,
7414 static struct pci_driver ixgbe_driver = {
7415 .name = ixgbe_driver_name,
7416 .id_table = ixgbe_pci_tbl,
7417 .probe = ixgbe_probe,
7418 .remove = __devexit_p(ixgbe_remove),
7420 .suspend = ixgbe_suspend,
7421 .resume = ixgbe_resume,
7423 .shutdown = ixgbe_shutdown,
7424 .err_handler = &ixgbe_err_handler
7428 * ixgbe_init_module - Driver Registration Routine
7430 * ixgbe_init_module is the first routine called when the driver is
7431 * loaded. All it does is register with the PCI subsystem.
7433 static int __init ixgbe_init_module(void)
7436 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7437 pr_info("%s\n", ixgbe_copyright);
7439 #ifdef CONFIG_IXGBE_DCA
7440 dca_register_notify(&dca_notifier);
7443 ret = pci_register_driver(&ixgbe_driver);
7447 module_init(ixgbe_init_module);
7450 * ixgbe_exit_module - Driver Exit Cleanup Routine
7452 * ixgbe_exit_module is called just before the driver is removed
7455 static void __exit ixgbe_exit_module(void)
7457 #ifdef CONFIG_IXGBE_DCA
7458 dca_unregister_notify(&dca_notifier);
7460 pci_unregister_driver(&ixgbe_driver);
7461 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7464 #ifdef CONFIG_IXGBE_DCA
7465 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7470 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7471 __ixgbe_notify_dca);
7473 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7476 #endif /* CONFIG_IXGBE_DCA */
7478 module_exit(ixgbe_exit_module);