drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_PHY_H_
  29 #define _IXGBE_PHY_H_
  30
  31 #include "ixgbe_type.h"
  32 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
  33 #define IXGBE_I2C_EEPROM_DEV_ADDR2   0xA2
  34
  35 /* EEPROM byte offsets */
  36 #define IXGBE_SFF_IDENTIFIER            0x0
  37 #define IXGBE_SFF_IDENTIFIER_SFP        0x3
  38 #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
  39 #define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
  40 #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
  41 #define IXGBE_SFF_1GBE_COMP_CODES       0x6
  42 #define IXGBE_SFF_10GBE_COMP_CODES      0x3
  43 #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
  44 #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
  45 #define IXGBE_SFF_SFF_8472_SWAP         0x5C
  46 #define IXGBE_SFF_SFF_8472_COMP         0x5E
  47 #define IXGBE_SFF_SFF_8472_OSCB         0x6E
  48 #define IXGBE_SFF_SFF_8472_ESCB         0x76
  49 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS  0xD
  50 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
  51 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
  52 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
  53 #define IXGBE_SFF_QSFP_10GBE_COMP       0x83
  54 #define IXGBE_SFF_QSFP_1GBE_COMP        0x86
  55
  56 /* Bitmasks */
  57 #define IXGBE_SFF_DA_PASSIVE_CABLE           0x4
  58 #define IXGBE_SFF_DA_ACTIVE_CABLE            0x8
  59 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING    0x4
  60 #define IXGBE_SFF_1GBASESX_CAPABLE           0x1
  61 #define IXGBE_SFF_1GBASELX_CAPABLE           0x2
  62 #define IXGBE_SFF_1GBASET_CAPABLE            0x8
  63 #define IXGBE_SFF_10GBASESR_CAPABLE          0x10
  64 #define IXGBE_SFF_10GBASELR_CAPABLE          0x20
  65 #define IXGBE_SFF_SOFT_RS_SELECT_MASK   0x8
  66 #define IXGBE_SFF_SOFT_RS_SELECT_10G    0x8
  67 #define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
  68 #define IXGBE_SFF_ADDRESSING_MODE            0x4
  69 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE       0x1
  70 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE      0x8
  71 #define IXGBE_I2C_EEPROM_READ_MASK           0x100
  72 #define IXGBE_I2C_EEPROM_STATUS_MASK         0x3
  73 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
  74 #define IXGBE_I2C_EEPROM_STATUS_PASS         0x1
  75 #define IXGBE_I2C_EEPROM_STATUS_FAIL         0x2
  76 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS  0x3
  77
  78 /* Flow control defines */
  79 #define IXGBE_TAF_SYM_PAUSE                  0x400
  80 #define IXGBE_TAF_ASM_PAUSE                  0x800
  81
  82 /* Bit-shift macros */
  83 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
  84 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
  85 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
  86
  87 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
  88 #define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
  89 #define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
  90 #define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
  91 #define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
  92
  93 /* I2C SDA and SCL timing parameters for standard mode */
  94 #define IXGBE_I2C_T_HD_STA  4
  95 #define IXGBE_I2C_T_LOW     5
  96 #define IXGBE_I2C_T_HIGH    4
  97 #define IXGBE_I2C_T_SU_STA  5
  98 #define IXGBE_I2C_T_HD_DATA 5
  99 #define IXGBE_I2C_T_SU_DATA 1
 100 #define IXGBE_I2C_T_RISE    1
 101 #define IXGBE_I2C_T_FALL    1
 102 #define IXGBE_I2C_T_SU_STO  4
 103 #define IXGBE_I2C_T_BUF     5
 104
 105 #define IXGBE_TN_LASI_STATUS_REG        0x9005
 106 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
 107
 108 /* SFP+ SFF-8472 Compliance code */
 109 #define IXGBE_SFF_SFF_8472_UNSUP      0x00
 110
 111 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
 112 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 113 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
 114 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 115                                u32 device_type, u16 *phy_data);
 116 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 117                                 u32 device_type, u16 phy_data);
 118 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 119                            u32 device_type, u16 *phy_data);
 120 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 121                             u32 device_type, u16 phy_data);
 122 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 123 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 124                                        ixgbe_link_speed speed,
 125                                        bool autoneg_wait_to_complete);
 126 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 127                                                ixgbe_link_speed *speed,
 128                                                bool *autoneg);
 129
 130 /* PHY specific */
 131 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
 132                              ixgbe_link_speed *speed,
 133                              bool *link_up);
 134 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 135 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 136                                        u16 *firmware_version);
 137 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 138                                            u16 *firmware_version);
 139
 140 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 141 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
 142 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
 143 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
 144 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 145                                         u16 *list_offset,
 146                                         u16 *data_offset);
 147 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 148 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 149                                 u8 dev_addr, u8 *data);
 150 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 151                                  u8 dev_addr, u8 data);
 152 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 153                                   u8 *eeprom_data);
 154 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
 155                                    u8 *sff8472_data);
 156 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 157                                    u8 eeprom_data);
 158 #endif /* _IXGBE_PHY_H_ */