1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/export.h>
30 #include <linux/ptp_classify.h>
33 * The 82599 and the X540 do not have true 64bit nanosecond scale
34 * counter registers. Instead, SYSTIME is defined by a fixed point
35 * system which allows the user to define the scale counter increment
36 * value at every level change of the oscillator driving the SYSTIME
37 * value. For both devices the TIMINCA:IV field defines this
38 * increment. On the X540 device, 31 bits are provided. However on the
39 * 82599 only provides 24 bits. The time unit is determined by the
40 * clock frequency of the oscillator in combination with the TIMINCA
41 * register. When these devices link at 10Gb the oscillator has a
42 * period of 6.4ns. In order to convert the scale counter into
43 * nanoseconds the cyclecounter and timecounter structures are
44 * used. The SYSTIME registers need to be converted to ns values by use
45 * of only a right shift (division by power of 2). The following math
46 * determines the largest incvalue that will fit into the available
47 * bits in the TIMINCA register.
49 * PeriodWidth: Number of bits to store the clock period
50 * MaxWidth: The maximum width value of the TIMINCA register
51 * Period: The clock period for the oscillator
52 * round(): discard the fractional portion of the calculation
54 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
56 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
57 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
59 * The period also changes based on the link speed:
60 * At 10Gb link or no link, the period remains the same.
61 * At 1Gb link, the period is multiplied by 10. (64ns)
62 * At 100Mb link, the period is multiplied by 100. (640ns)
64 * The calculated value allows us to right shift the SYSTIME register
65 * value in order to quickly convert it into a nanosecond clock,
66 * while allowing for the maximum possible adjustment value.
68 * These diagrams are only for the 10Gb link period
71 * +--------------+ +--------------+
72 * X540 | 32 | | 1 | 3 | 28 |
73 * *--------------+ +--------------+
74 * \________ 36 bits ______/ fract
76 * +--------------+ +--------------+
77 * 82599 | 32 | | 8 | 3 | 21 |
78 * *--------------+ +--------------+
79 * \________ 43 bits ______/ fract
81 * The 36 bit X540 SYSTIME overflows every
82 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
84 * The 43 bit 82599 SYSTIME overflows every
85 * 2^43 * 10^-9 / 3600 = 2.4 hours
87 #define IXGBE_INCVAL_10GB 0x66666666
88 #define IXGBE_INCVAL_1GB 0x40000000
89 #define IXGBE_INCVAL_100 0x50000000
91 #define IXGBE_INCVAL_SHIFT_10GB 28
92 #define IXGBE_INCVAL_SHIFT_1GB 24
93 #define IXGBE_INCVAL_SHIFT_100 21
95 #define IXGBE_INCVAL_SHIFT_82599 7
96 #define IXGBE_INCPER_SHIFT_82599 24
97 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
99 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
100 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
102 #ifndef NSECS_PER_SEC
103 #define NSECS_PER_SEC 1000000000ULL
107 * ixgbe_ptp_setup_sdp
108 * @hw: the hardware private structure
110 * this function enables or disables the clock out feature on SDP0 for
111 * the X540 device. It will create a 1second periodic output that can
112 * be used as the PPS (via an interrupt).
114 * It calculates when the systime will be on an exact second, and then
115 * aligns the start of the PPS signal to that value. The shift is
116 * necessary because it can change based on the link speed.
118 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
120 struct ixgbe_hw *hw = &adapter->hw;
121 int shift = adapter->cc.shift;
122 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
123 u64 ns = 0, clock_edge = 0;
125 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
126 (hw->mac.type == ixgbe_mac_X540)) {
128 /* disable the pin first */
129 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
130 IXGBE_WRITE_FLUSH(hw);
132 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
135 * enable the SDP0 pin as output, and connected to the
136 * native function for Timesync (ClockOut)
138 esdp |= (IXGBE_ESDP_SDP0_DIR |
139 IXGBE_ESDP_SDP0_NATIVE);
142 * enable the Clock Out feature on SDP0, and allow
143 * interrupts to occur when the pin changes
145 tsauxc = (IXGBE_TSAUXC_EN_CLK |
146 IXGBE_TSAUXC_SYNCLK |
147 IXGBE_TSAUXC_SDP0_INT);
149 /* clock period (or pulse length) */
150 clktiml = (u32)(NSECS_PER_SEC << shift);
151 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
154 * Account for the cyclecounter wrap-around value by
155 * using the converted ns value of the current time to
156 * check for when the next aligned second would occur.
158 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
159 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
160 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
162 div_u64_rem(ns, NSECS_PER_SEC, &rem);
163 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
165 /* specify the initial clock start time */
166 trgttiml = (u32)clock_edge;
167 trgttimh = (u32)(clock_edge >> 32);
169 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
170 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
171 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
172 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
174 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
175 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
177 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
180 IXGBE_WRITE_FLUSH(hw);
184 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
185 * @cc: the cyclecounter structure
187 * this function reads the cyclecounter registers and is called by the
188 * cyclecounter structure used to construct a ns counter from the
189 * arbitrary fixed point registers
191 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
193 struct ixgbe_adapter *adapter =
194 container_of(cc, struct ixgbe_adapter, cc);
195 struct ixgbe_hw *hw = &adapter->hw;
198 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
199 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
206 * @ptp: the ptp clock structure
207 * @ppb: parts per billion adjustment from base
209 * adjust the frequency of the ptp cycle counter by the
210 * indicated ppb from the base frequency.
212 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
214 struct ixgbe_adapter *adapter =
215 container_of(ptp, struct ixgbe_adapter, ptp_caps);
216 struct ixgbe_hw *hw = &adapter->hw;
227 incval = ACCESS_ONCE(adapter->base_incval);
231 diff = div_u64(freq, 1000000000ULL);
233 incval = neg_adj ? (incval - diff) : (incval + diff);
235 switch (hw->mac.type) {
237 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
239 case ixgbe_mac_82599EB:
240 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
241 (1 << IXGBE_INCPER_SHIFT_82599) |
253 * @ptp: the ptp clock structure
254 * @delta: offset to adjust the cycle counter by
256 * adjust the timer by resetting the timecounter structure.
258 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
260 struct ixgbe_adapter *adapter =
261 container_of(ptp, struct ixgbe_adapter, ptp_caps);
265 spin_lock_irqsave(&adapter->tmreg_lock, flags);
267 now = timecounter_read(&adapter->tc);
270 /* reset the timecounter */
271 timecounter_init(&adapter->tc,
275 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
277 ixgbe_ptp_setup_sdp(adapter);
284 * @ptp: the ptp clock structure
285 * @ts: timespec structure to hold the current time value
287 * read the timecounter and return the correct value on ns,
288 * after converting it into a struct timespec.
290 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
292 struct ixgbe_adapter *adapter =
293 container_of(ptp, struct ixgbe_adapter, ptp_caps);
298 spin_lock_irqsave(&adapter->tmreg_lock, flags);
299 ns = timecounter_read(&adapter->tc);
300 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
302 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
303 ts->tv_nsec = remainder;
310 * @ptp: the ptp clock structure
311 * @ts: the timespec containing the new time for the cycle counter
313 * reset the timecounter to use a new base value instead of the kernel
316 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
317 const struct timespec *ts)
319 struct ixgbe_adapter *adapter =
320 container_of(ptp, struct ixgbe_adapter, ptp_caps);
324 ns = ts->tv_sec * 1000000000ULL;
327 /* reset the timecounter */
328 spin_lock_irqsave(&adapter->tmreg_lock, flags);
329 timecounter_init(&adapter->tc, &adapter->cc, ns);
330 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
332 ixgbe_ptp_setup_sdp(adapter);
337 * ixgbe_ptp_feature_enable
338 * @ptp: the ptp clock structure
339 * @rq: the requested feature to change
340 * @on: whether to enable or disable the feature
342 * enable (or disable) ancillary features of the phc subsystem.
343 * our driver only supports the PPS feature on the X540
345 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
346 struct ptp_clock_request *rq, int on)
348 struct ixgbe_adapter *adapter =
349 container_of(ptp, struct ixgbe_adapter, ptp_caps);
352 * When PPS is enabled, unmask the interrupt for the ClockOut
353 * feature, so that the interrupt handler can send the PPS
354 * event when the clock SDP triggers. Clear mask when PPS is
357 if (rq->type == PTP_CLK_REQ_PPS) {
358 switch (adapter->hw.mac.type) {
361 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
363 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
365 ixgbe_ptp_setup_sdp(adapter);
376 * ixgbe_ptp_check_pps_event
377 * @adapter: the private adapter structure
378 * @eicr: the interrupt cause register value
380 * This function is called by the interrupt routine when checking for
381 * interrupts. It will check and handle a pps event.
383 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
385 struct ixgbe_hw *hw = &adapter->hw;
386 struct ptp_clock_event event;
388 event.type = PTP_CLOCK_PPS;
390 /* this check is necessary in case the interrupt was enabled via some
391 * alternative means (ex. debug_fs). Better to check here than
392 * everywhere that calls this function.
394 if (!adapter->ptp_clock)
397 switch (hw->mac.type) {
399 ptp_clock_event(adapter->ptp_clock, &event);
407 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
408 * @adapter: private adapter struct
410 * this watchdog task periodically reads the timecounter
411 * in order to prevent missing when the system time registers wrap
412 * around. This needs to be run approximately twice a minute.
414 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
416 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
417 IXGBE_OVERFLOW_PERIOD);
421 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
422 adapter->last_overflow_check = jiffies;
427 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
428 * @adapter: private network adapter structure
430 * this watchdog task is scheduled to detect error case where hardware has
431 * dropped an Rx packet that was timestamped when the ring is full. The
432 * particular error is rare but leaves the device in a state unable to timestamp
433 * any future packets.
435 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
437 struct ixgbe_hw *hw = &adapter->hw;
438 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
439 unsigned long rx_event;
441 /* if we don't have a valid timestamp in the registers, just update the
442 * timeout counter and exit
444 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
445 adapter->last_rx_ptp_check = jiffies;
449 /* determine the most recent watchdog or rx_timestamp event */
450 rx_event = adapter->last_rx_ptp_check;
451 if (time_after(adapter->last_rx_timestamp, rx_event))
452 rx_event = adapter->last_rx_timestamp;
454 /* only need to read the high RXSTMP register to clear the lock */
455 if (time_is_before_jiffies(rx_event + 5*HZ)) {
456 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
457 adapter->last_rx_ptp_check = jiffies;
459 e_warn(drv, "clearing RX Timestamp hang\n");
464 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
465 * @adapter: the private adapter struct
467 * if the timestamp is valid, we convert it into the timecounter ns
468 * value, then store that result into the shhwtstamps structure which
469 * is passed up the network stack
471 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
473 struct ixgbe_hw *hw = &adapter->hw;
474 struct skb_shared_hwtstamps shhwtstamps;
478 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
479 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
481 spin_lock_irqsave(&adapter->tmreg_lock, flags);
482 ns = timecounter_cyc2time(&adapter->tc, regval);
483 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
485 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
486 shhwtstamps.hwtstamp = ns_to_ktime(ns);
487 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
489 dev_kfree_skb_any(adapter->ptp_tx_skb);
490 adapter->ptp_tx_skb = NULL;
491 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
495 * ixgbe_ptp_tx_hwtstamp_work
496 * @work: pointer to the work struct
498 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
499 * timestamp has been taken for the current skb. It is necesary, because the
500 * descriptor's "done" bit does not correlate with the timestamp event.
502 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
504 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
506 struct ixgbe_hw *hw = &adapter->hw;
507 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
508 IXGBE_PTP_TX_TIMEOUT);
512 dev_kfree_skb_any(adapter->ptp_tx_skb);
513 adapter->ptp_tx_skb = NULL;
514 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
515 e_warn(drv, "clearing Tx Timestamp hang\n");
519 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
520 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID)
521 ixgbe_ptp_tx_hwtstamp(adapter);
523 /* reschedule to keep checking if it's not available yet */
524 schedule_work(&adapter->ptp_tx_work);
528 * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
529 * @adapter: pointer to adapter struct
530 * @skb: particular skb to send timestamp with
532 * if the timestamp is valid, we convert it into the timecounter ns
533 * value, then store that result into the shhwtstamps structure which
534 * is passed up the network stack
536 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb)
538 struct ixgbe_hw *hw = &adapter->hw;
539 struct skb_shared_hwtstamps *shhwtstamps;
544 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
545 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
548 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
549 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
551 spin_lock_irqsave(&adapter->tmreg_lock, flags);
552 ns = timecounter_cyc2time(&adapter->tc, regval);
553 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
555 shhwtstamps = skb_hwtstamps(skb);
556 shhwtstamps->hwtstamp = ns_to_ktime(ns);
558 /* Update the last_rx_timestamp timer in order to enable watchdog check
559 * for error case of latched timestamp on a dropped packet.
561 adapter->last_rx_timestamp = jiffies;
564 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
566 struct hwtstamp_config *config = &adapter->tstamp_config;
568 return copy_to_user(ifr->ifr_data, config,
569 sizeof(*config)) ? -EFAULT : 0;
573 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
574 * @adapter: the private ixgbe adapter structure
575 * @config: the hwtstamp configuration requested
577 * Outgoing time stamping can be enabled and disabled. Play nice and
578 * disable it when requested, although it shouldn't cause any overhead
579 * when no packet needs it. At most one packet in the queue may be
580 * marked for time stamping, otherwise it would be impossible to tell
581 * for sure to which packet the hardware time stamp belongs.
583 * Incoming time stamping has to be configured via the hardware
584 * filters. Not all combinations are supported, in particular event
585 * type has to be specified. Matching the kind of event packet is
586 * not supported, with the exception of "all V2 events regardless of
589 * Since hardware always timestamps Path delay packets when timestamping V2
590 * packets, regardless of the type specified in the register, only use V2
591 * Event mode. This more accurately tells the user what the hardware is going
594 * Note: this may modify the hwtstamp configuration towards a more general
595 * mode, if required to support the specifically requested mode.
597 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
598 struct hwtstamp_config *config)
600 struct ixgbe_hw *hw = &adapter->hw;
601 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
602 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
603 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
607 /* reserved for future extensions */
611 switch (config->tx_type) {
612 case HWTSTAMP_TX_OFF:
620 switch (config->rx_filter) {
621 case HWTSTAMP_FILTER_NONE:
625 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
626 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
627 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
629 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
630 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
631 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
633 case HWTSTAMP_FILTER_PTP_V2_EVENT:
634 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
635 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
636 case HWTSTAMP_FILTER_PTP_V2_SYNC:
637 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
638 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
639 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
640 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
641 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
642 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
644 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
646 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
647 case HWTSTAMP_FILTER_ALL:
650 * register RXMTRL must be set in order to do V1 packets,
651 * therefore it is not possible to time stamp both V1 Sync and
652 * Delay_Req messages and hardware does not support
653 * timestamping all packets => return error
655 config->rx_filter = HWTSTAMP_FILTER_NONE;
659 if (hw->mac.type == ixgbe_mac_82598EB) {
660 if (tsync_rx_ctl | tsync_tx_ctl)
665 /* define ethertype filter for timestamping L2 packets */
667 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
668 (IXGBE_ETQF_FILTER_EN | /* enable filter */
669 IXGBE_ETQF_1588 | /* enable timestamping */
670 ETH_P_1588)); /* 1588 eth protocol type */
672 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
674 /* enable/disable TX */
675 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
676 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
677 regval |= tsync_tx_ctl;
678 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
680 /* enable/disable RX */
681 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
682 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
683 regval |= tsync_rx_ctl;
684 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
686 /* define which PTP packets are time stamped */
687 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
689 IXGBE_WRITE_FLUSH(hw);
691 /* clear TX/RX time stamp registers, just to be sure */
692 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
693 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
699 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
700 * @adapter: pointer to adapter struct
703 * Set hardware to requested mode. If unsupported, return an error with no
704 * changes. Otherwise, store the mode for future reference.
706 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
708 struct hwtstamp_config config;
711 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
714 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
718 /* save these settings for future reference */
719 memcpy(&adapter->tstamp_config, &config,
720 sizeof(adapter->tstamp_config));
722 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
727 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
728 * @adapter: pointer to the adapter structure
730 * This function should be called to set the proper values for the TIMINCA
731 * register and tell the cyclecounter structure what the tick rate of SYSTIME
732 * is. It does not directly modify SYSTIME registers or the timecounter
733 * structure. It should be called whenever a new TIMINCA value is necessary,
734 * such as during initialization or when the link speed changes.
736 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
738 struct ixgbe_hw *hw = &adapter->hw;
744 * Scale the NIC cycle counter by a large factor so that
745 * relatively small corrections to the frequency can be added
746 * or subtracted. The drawbacks of a large factor include
747 * (a) the clock register overflows more quickly, (b) the cycle
748 * counter structure must be able to convert the systime value
749 * to nanoseconds using only a multiplier and a right-shift,
750 * and (c) the value must fit within the timinca register space
751 * => math based on internal DMA clock rate and available bits
753 * Note that when there is no link, internal DMA clock is same as when
754 * link speed is 10Gb. Set the registers correctly even when link is
755 * down to preserve the clock setting
757 switch (adapter->link_speed) {
758 case IXGBE_LINK_SPEED_100_FULL:
759 incval = IXGBE_INCVAL_100;
760 shift = IXGBE_INCVAL_SHIFT_100;
762 case IXGBE_LINK_SPEED_1GB_FULL:
763 incval = IXGBE_INCVAL_1GB;
764 shift = IXGBE_INCVAL_SHIFT_1GB;
766 case IXGBE_LINK_SPEED_10GB_FULL:
768 incval = IXGBE_INCVAL_10GB;
769 shift = IXGBE_INCVAL_SHIFT_10GB;
774 * Modify the calculated values to fit within the correct
775 * number of bits specified by the hardware. The 82599 doesn't
776 * have the same space as the X540, so bitshift the calculated
779 switch (hw->mac.type) {
781 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
783 case ixgbe_mac_82599EB:
784 incval >>= IXGBE_INCVAL_SHIFT_82599;
785 shift -= IXGBE_INCVAL_SHIFT_82599;
786 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
787 (1 << IXGBE_INCPER_SHIFT_82599) |
791 /* other devices aren't supported */
795 /* update the base incval used to calculate frequency adjustment */
796 ACCESS_ONCE(adapter->base_incval) = incval;
799 /* need lock to prevent incorrect read while modifying cyclecounter */
800 spin_lock_irqsave(&adapter->tmreg_lock, flags);
802 memset(&adapter->cc, 0, sizeof(adapter->cc));
803 adapter->cc.read = ixgbe_ptp_read;
804 adapter->cc.mask = CLOCKSOURCE_MASK(64);
805 adapter->cc.shift = shift;
806 adapter->cc.mult = 1;
808 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
813 * @adapter: the ixgbe private board structure
815 * When the MAC resets, all the hardware bits for timesync are reset. This
816 * function is used to re-enable the device for PTP based on current settings.
817 * We do lose the current clock time, so just reset the cyclecounter to the
818 * system real clock time.
820 * This function will maintain hwtstamp_config settings, and resets the SDP
821 * output if it was enabled.
823 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
825 struct ixgbe_hw *hw = &adapter->hw;
828 /* set SYSTIME registers to 0 just in case */
829 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
830 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
831 IXGBE_WRITE_FLUSH(hw);
833 /* reset the hardware timestamping mode */
834 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
836 ixgbe_ptp_start_cyclecounter(adapter);
838 spin_lock_irqsave(&adapter->tmreg_lock, flags);
840 /* reset the ns time counter */
841 timecounter_init(&adapter->tc, &adapter->cc,
842 ktime_to_ns(ktime_get_real()));
844 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
847 * Now that the shift has been calculated and the systime
848 * registers reset, (re-)enable the Clock out feature
850 ixgbe_ptp_setup_sdp(adapter);
854 * ixgbe_ptp_create_clock
855 * @adapter: the ixgbe private adapter structure
857 * This function performs setup of the user entry point function table and
858 * initializes the PTP clock device, which is used to access the clock-like
859 * features of the PTP core. It will be called by ixgbe_ptp_init, only if
860 * there isn't already a clock device (such as after a suspend/resume cycle,
861 * where the clock device wasn't destroyed).
863 static int ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
865 struct net_device *netdev = adapter->netdev;
868 /* do nothing if we already have a clock device */
869 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
872 switch (adapter->hw.mac.type) {
874 snprintf(adapter->ptp_caps.name,
875 sizeof(adapter->ptp_caps.name),
877 adapter->ptp_caps.owner = THIS_MODULE;
878 adapter->ptp_caps.max_adj = 250000000;
879 adapter->ptp_caps.n_alarm = 0;
880 adapter->ptp_caps.n_ext_ts = 0;
881 adapter->ptp_caps.n_per_out = 0;
882 adapter->ptp_caps.pps = 1;
883 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
884 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
885 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
886 adapter->ptp_caps.settime = ixgbe_ptp_settime;
887 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
889 case ixgbe_mac_82599EB:
890 snprintf(adapter->ptp_caps.name,
891 sizeof(adapter->ptp_caps.name),
893 adapter->ptp_caps.owner = THIS_MODULE;
894 adapter->ptp_caps.max_adj = 250000000;
895 adapter->ptp_caps.n_alarm = 0;
896 adapter->ptp_caps.n_ext_ts = 0;
897 adapter->ptp_caps.n_per_out = 0;
898 adapter->ptp_caps.pps = 0;
899 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
900 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
901 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
902 adapter->ptp_caps.settime = ixgbe_ptp_settime;
903 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
906 adapter->ptp_clock = NULL;
910 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
911 &adapter->pdev->dev);
912 if (IS_ERR(adapter->ptp_clock)) {
913 err = PTR_ERR(adapter->ptp_clock);
914 adapter->ptp_clock = NULL;
915 e_dev_err("ptp_clock_register failed\n");
918 e_dev_info("registered PHC device on %s\n", netdev->name);
920 /* set default timestamp mode to disabled here. We do this in
921 * create_clock instead of init, because we don't want to override the
922 * previous settings during a resume cycle.
924 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
925 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
932 * @adapter: the ixgbe private adapter structure
934 * This function performs the required steps for enabling PTP
935 * support. If PTP support has already been loaded it simply calls the
936 * cyclecounter init routine and exits.
938 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
940 /* initialize the spin lock first since we can't control when a user
941 * will call the entry functions once we have initialized the clock
944 spin_lock_init(&adapter->tmreg_lock);
946 /* obtain a PTP device, or re-use an existing device */
947 if (ixgbe_ptp_create_clock(adapter))
950 /* we have a clock so we can initialize work now */
951 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
953 /* reset the PTP related hardware bits */
954 ixgbe_ptp_reset(adapter);
956 /* enter the IXGBE_PTP_RUNNING state */
957 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
963 * ixgbe_ptp_stop - disable ptp device and stop the overflow check
964 * @adapter: pointer to adapter struct
966 * this function stops the ptp support, and cancels the delayed work.
968 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
970 /* Leave the IXGBE_PTP_RUNNING state. */
971 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
974 /* stop the PPS signal */
975 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
976 ixgbe_ptp_setup_sdp(adapter);
978 cancel_work_sync(&adapter->ptp_tx_work);
979 if (adapter->ptp_tx_skb) {
980 dev_kfree_skb_any(adapter->ptp_tx_skb);
981 adapter->ptp_tx_skb = NULL;
982 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
985 if (adapter->ptp_clock) {
986 ptp_clock_unregister(adapter->ptp_clock);
987 adapter->ptp_clock = NULL;
988 e_dev_info("removed PHC on %s\n",
989 adapter->netdev->name);