2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/pci-aspm.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/crc32.h>
36 #include <linux/delay.h>
37 #include <linux/spinlock.h>
40 #include <linux/ipv6.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/if_vlan.h>
44 #include <linux/slab.h>
45 #include <net/ip6_checksum.h>
48 static int force_pseudohp = -1;
49 static int no_pseudohp = -1;
50 static int no_extplug = -1;
51 module_param(force_pseudohp, int, 0);
52 MODULE_PARM_DESC(force_pseudohp,
53 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
54 module_param(no_pseudohp, int, 0);
55 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
56 module_param(no_extplug, int, 0);
57 MODULE_PARM_DESC(no_extplug,
58 "Do not use external plug signal for pseudo hot-plug.");
61 jme_mdio_read(struct net_device *netdev, int phy, int reg)
63 struct jme_adapter *jme = netdev_priv(netdev);
64 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
67 jwrite32(jme, JME_SMI, SMI_OP_REQ |
72 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
74 val = jread32(jme, JME_SMI);
75 if ((val & SMI_OP_REQ) == 0)
80 pr_err("phy(%d) read timeout : %d\n", phy, reg);
87 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
91 jme_mdio_write(struct net_device *netdev,
92 int phy, int reg, int val)
94 struct jme_adapter *jme = netdev_priv(netdev);
97 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
98 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
99 smi_phy_addr(phy) | smi_reg_addr(reg));
102 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
104 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
109 pr_err("phy(%d) write timeout : %d\n", phy, reg);
113 jme_reset_phy_processor(struct jme_adapter *jme)
117 jme_mdio_write(jme->dev,
119 MII_ADVERTISE, ADVERTISE_ALL |
120 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
122 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
123 jme_mdio_write(jme->dev,
126 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
128 val = jme_mdio_read(jme->dev,
132 jme_mdio_write(jme->dev,
134 MII_BMCR, val | BMCR_RESET);
138 jme_setup_wakeup_frame(struct jme_adapter *jme,
139 const u32 *mask, u32 crc, int fnr)
146 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
148 jwrite32(jme, JME_WFODP, crc);
154 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
155 jwrite32(jme, JME_WFOI,
156 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
157 (fnr & WFOI_FRAME_SEL));
159 jwrite32(jme, JME_WFODP, mask[i]);
165 jme_mac_rxclk_off(struct jme_adapter *jme)
167 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
168 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
172 jme_mac_rxclk_on(struct jme_adapter *jme)
174 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
175 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
179 jme_mac_txclk_off(struct jme_adapter *jme)
181 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
182 jwrite32f(jme, JME_GHC, jme->reg_ghc);
186 jme_mac_txclk_on(struct jme_adapter *jme)
188 u32 speed = jme->reg_ghc & GHC_SPEED;
189 if (speed == GHC_SPEED_1000M)
190 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
192 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
193 jwrite32f(jme, JME_GHC, jme->reg_ghc);
197 jme_reset_ghc_speed(struct jme_adapter *jme)
199 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
200 jwrite32f(jme, JME_GHC, jme->reg_ghc);
204 jme_reset_250A2_workaround(struct jme_adapter *jme)
206 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
208 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
212 jme_assert_ghc_reset(struct jme_adapter *jme)
214 jme->reg_ghc |= GHC_SWRST;
215 jwrite32f(jme, JME_GHC, jme->reg_ghc);
219 jme_clear_ghc_reset(struct jme_adapter *jme)
221 jme->reg_ghc &= ~GHC_SWRST;
222 jwrite32f(jme, JME_GHC, jme->reg_ghc);
226 jme_reset_mac_processor(struct jme_adapter *jme)
228 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
229 u32 crc = 0xCDCDCDCD;
233 jme_reset_ghc_speed(jme);
234 jme_reset_250A2_workaround(jme);
236 jme_mac_rxclk_on(jme);
237 jme_mac_txclk_on(jme);
239 jme_assert_ghc_reset(jme);
241 jme_mac_rxclk_off(jme);
242 jme_mac_txclk_off(jme);
244 jme_clear_ghc_reset(jme);
246 jme_mac_rxclk_on(jme);
247 jme_mac_txclk_on(jme);
249 jme_mac_rxclk_off(jme);
250 jme_mac_txclk_off(jme);
252 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
253 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
254 jwrite32(jme, JME_RXQDC, 0x00000000);
255 jwrite32(jme, JME_RXNDA, 0x00000000);
256 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
257 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
258 jwrite32(jme, JME_TXQDC, 0x00000000);
259 jwrite32(jme, JME_TXNDA, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
262 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
263 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
264 jme_setup_wakeup_frame(jme, mask, crc, i);
266 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
268 gpreg0 = GPREG0_DEFAULT;
269 jwrite32(jme, JME_GPREG0, gpreg0);
273 jme_clear_pm(struct jme_adapter *jme)
275 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
279 jme_reload_eeprom(struct jme_adapter *jme)
284 val = jread32(jme, JME_SMBCSR);
286 if (val & SMBCSR_EEPROMD) {
288 jwrite32(jme, JME_SMBCSR, val);
289 val |= SMBCSR_RELOAD;
290 jwrite32(jme, JME_SMBCSR, val);
293 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
295 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
300 pr_err("eeprom reload timeout\n");
309 jme_load_macaddr(struct net_device *netdev)
311 struct jme_adapter *jme = netdev_priv(netdev);
312 unsigned char macaddr[ETH_ALEN];
315 spin_lock_bh(&jme->macaddr_lock);
316 val = jread32(jme, JME_RXUMA_LO);
317 macaddr[0] = (val >> 0) & 0xFF;
318 macaddr[1] = (val >> 8) & 0xFF;
319 macaddr[2] = (val >> 16) & 0xFF;
320 macaddr[3] = (val >> 24) & 0xFF;
321 val = jread32(jme, JME_RXUMA_HI);
322 macaddr[4] = (val >> 0) & 0xFF;
323 macaddr[5] = (val >> 8) & 0xFF;
324 memcpy(netdev->dev_addr, macaddr, ETH_ALEN);
325 spin_unlock_bh(&jme->macaddr_lock);
329 jme_set_rx_pcc(struct jme_adapter *jme, int p)
333 jwrite32(jme, JME_PCCRX0,
334 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
335 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
338 jwrite32(jme, JME_PCCRX0,
339 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
340 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
343 jwrite32(jme, JME_PCCRX0,
344 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
345 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
348 jwrite32(jme, JME_PCCRX0,
349 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
350 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
357 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
358 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
362 jme_start_irq(struct jme_adapter *jme)
364 register struct dynpcc_info *dpi = &(jme->dpi);
366 jme_set_rx_pcc(jme, PCC_P1);
368 dpi->attempt = PCC_P1;
371 jwrite32(jme, JME_PCCTX,
372 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
373 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
380 jwrite32(jme, JME_IENS, INTR_ENABLE);
384 jme_stop_irq(struct jme_adapter *jme)
389 jwrite32f(jme, JME_IENC, INTR_ENABLE);
393 jme_linkstat_from_phy(struct jme_adapter *jme)
397 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
398 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
399 if (bmsr & BMSR_ANCOMP)
400 phylink |= PHY_LINK_AUTONEG_COMPLETE;
406 jme_set_phyfifo_5level(struct jme_adapter *jme)
408 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
412 jme_set_phyfifo_8level(struct jme_adapter *jme)
414 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
418 jme_check_link(struct net_device *netdev, int testonly)
420 struct jme_adapter *jme = netdev_priv(netdev);
421 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
428 phylink = jme_linkstat_from_phy(jme);
430 phylink = jread32(jme, JME_PHY_LINK);
432 if (phylink & PHY_LINK_UP) {
433 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
435 * If we did not enable AN
436 * Speed/Duplex Info should be obtained from SMI
438 phylink = PHY_LINK_UP;
440 bmcr = jme_mdio_read(jme->dev,
444 phylink |= ((bmcr & BMCR_SPEED1000) &&
445 (bmcr & BMCR_SPEED100) == 0) ?
446 PHY_LINK_SPEED_1000M :
447 (bmcr & BMCR_SPEED100) ?
448 PHY_LINK_SPEED_100M :
451 phylink |= (bmcr & BMCR_FULLDPLX) ?
454 strcat(linkmsg, "Forced: ");
457 * Keep polling for speed/duplex resolve complete
459 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
465 phylink = jme_linkstat_from_phy(jme);
467 phylink = jread32(jme, JME_PHY_LINK);
470 pr_err("Waiting speed resolve timeout\n");
472 strcat(linkmsg, "ANed: ");
475 if (jme->phylink == phylink) {
482 jme->phylink = phylink;
485 * The speed/duplex setting of jme->reg_ghc already cleared
486 * by jme_reset_mac_processor()
488 switch (phylink & PHY_LINK_SPEED_MASK) {
489 case PHY_LINK_SPEED_10M:
490 jme->reg_ghc |= GHC_SPEED_10M;
491 strcat(linkmsg, "10 Mbps, ");
493 case PHY_LINK_SPEED_100M:
494 jme->reg_ghc |= GHC_SPEED_100M;
495 strcat(linkmsg, "100 Mbps, ");
497 case PHY_LINK_SPEED_1000M:
498 jme->reg_ghc |= GHC_SPEED_1000M;
499 strcat(linkmsg, "1000 Mbps, ");
505 if (phylink & PHY_LINK_DUPLEX) {
506 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
507 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
508 jme->reg_ghc |= GHC_DPX;
510 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
514 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
517 jwrite32(jme, JME_GHC, jme->reg_ghc);
519 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
520 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
522 if (!(phylink & PHY_LINK_DUPLEX))
523 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
524 switch (phylink & PHY_LINK_SPEED_MASK) {
525 case PHY_LINK_SPEED_10M:
526 jme_set_phyfifo_8level(jme);
527 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
529 case PHY_LINK_SPEED_100M:
530 jme_set_phyfifo_5level(jme);
531 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
533 case PHY_LINK_SPEED_1000M:
534 jme_set_phyfifo_8level(jme);
540 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
542 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
545 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
548 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
549 netif_carrier_on(netdev);
554 netif_info(jme, link, jme->dev, "Link is down\n");
556 netif_carrier_off(netdev);
564 jme_setup_tx_resources(struct jme_adapter *jme)
566 struct jme_ring *txring = &(jme->txring[0]);
568 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
569 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
579 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
581 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
582 txring->next_to_use = 0;
583 atomic_set(&txring->next_to_clean, 0);
584 atomic_set(&txring->nr_free, jme->tx_ring_size);
586 txring->bufinf = kzalloc(sizeof(struct jme_buffer_info) *
587 jme->tx_ring_size, GFP_ATOMIC);
588 if (unlikely(!(txring->bufinf)))
589 goto err_free_txring;
592 * Initialize Transmit Descriptors
594 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
599 dma_free_coherent(&(jme->pdev->dev),
600 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
606 txring->dmaalloc = 0;
608 txring->bufinf = NULL;
614 jme_free_tx_resources(struct jme_adapter *jme)
617 struct jme_ring *txring = &(jme->txring[0]);
618 struct jme_buffer_info *txbi;
621 if (txring->bufinf) {
622 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
623 txbi = txring->bufinf + i;
625 dev_kfree_skb(txbi->skb);
631 txbi->start_xmit = 0;
633 kfree(txring->bufinf);
636 dma_free_coherent(&(jme->pdev->dev),
637 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
641 txring->alloc = NULL;
643 txring->dmaalloc = 0;
645 txring->bufinf = NULL;
647 txring->next_to_use = 0;
648 atomic_set(&txring->next_to_clean, 0);
649 atomic_set(&txring->nr_free, 0);
653 jme_enable_tx_engine(struct jme_adapter *jme)
658 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
662 * Setup TX Queue 0 DMA Bass Address
664 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
665 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
666 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
669 * Setup TX Descptor Count
671 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
677 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
682 * Start clock for TX MAC Processor
684 jme_mac_txclk_on(jme);
688 jme_restart_tx_engine(struct jme_adapter *jme)
693 jwrite32(jme, JME_TXCS, jme->reg_txcs |
699 jme_disable_tx_engine(struct jme_adapter *jme)
707 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
710 val = jread32(jme, JME_TXCS);
711 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
713 val = jread32(jme, JME_TXCS);
718 pr_err("Disable TX engine timeout\n");
721 * Stop clock for TX MAC Processor
723 jme_mac_txclk_off(jme);
727 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
729 struct jme_ring *rxring = &(jme->rxring[0]);
730 register struct rxdesc *rxdesc = rxring->desc;
731 struct jme_buffer_info *rxbi = rxring->bufinf;
737 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
738 rxdesc->desc1.bufaddrl = cpu_to_le32(
739 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
740 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
741 if (jme->dev->features & NETIF_F_HIGHDMA)
742 rxdesc->desc1.flags = RXFLAG_64BIT;
744 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
748 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
750 struct jme_ring *rxring = &(jme->rxring[0]);
751 struct jme_buffer_info *rxbi = rxring->bufinf + i;
755 skb = netdev_alloc_skb(jme->dev,
756 jme->dev->mtu + RX_EXTRA_LEN);
760 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
761 offset_in_page(skb->data), skb_tailroom(skb),
763 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
768 if (likely(rxbi->mapping))
769 pci_unmap_page(jme->pdev, rxbi->mapping,
770 rxbi->len, PCI_DMA_FROMDEVICE);
773 rxbi->len = skb_tailroom(skb);
774 rxbi->mapping = mapping;
779 jme_free_rx_buf(struct jme_adapter *jme, int i)
781 struct jme_ring *rxring = &(jme->rxring[0]);
782 struct jme_buffer_info *rxbi = rxring->bufinf;
786 pci_unmap_page(jme->pdev,
790 dev_kfree_skb(rxbi->skb);
798 jme_free_rx_resources(struct jme_adapter *jme)
801 struct jme_ring *rxring = &(jme->rxring[0]);
804 if (rxring->bufinf) {
805 for (i = 0 ; i < jme->rx_ring_size ; ++i)
806 jme_free_rx_buf(jme, i);
807 kfree(rxring->bufinf);
810 dma_free_coherent(&(jme->pdev->dev),
811 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
814 rxring->alloc = NULL;
816 rxring->dmaalloc = 0;
818 rxring->bufinf = NULL;
820 rxring->next_to_use = 0;
821 atomic_set(&rxring->next_to_clean, 0);
825 jme_setup_rx_resources(struct jme_adapter *jme)
828 struct jme_ring *rxring = &(jme->rxring[0]);
830 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
831 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
840 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
842 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
843 rxring->next_to_use = 0;
844 atomic_set(&rxring->next_to_clean, 0);
846 rxring->bufinf = kzalloc(sizeof(struct jme_buffer_info) *
847 jme->rx_ring_size, GFP_ATOMIC);
848 if (unlikely(!(rxring->bufinf)))
849 goto err_free_rxring;
852 * Initiallize Receive Descriptors
854 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
855 if (unlikely(jme_make_new_rx_buf(jme, i))) {
856 jme_free_rx_resources(jme);
860 jme_set_clean_rxdesc(jme, i);
866 dma_free_coherent(&(jme->pdev->dev),
867 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
872 rxring->dmaalloc = 0;
874 rxring->bufinf = NULL;
880 jme_enable_rx_engine(struct jme_adapter *jme)
885 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
890 * Setup RX DMA Bass Address
892 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
893 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
894 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
897 * Setup RX Descriptor Count
899 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
902 * Setup Unicast Filter
904 jme_set_unicastaddr(jme->dev);
905 jme_set_multi(jme->dev);
911 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
917 * Start clock for RX MAC Processor
919 jme_mac_rxclk_on(jme);
923 jme_restart_rx_engine(struct jme_adapter *jme)
928 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
935 jme_disable_rx_engine(struct jme_adapter *jme)
943 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
946 val = jread32(jme, JME_RXCS);
947 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
949 val = jread32(jme, JME_RXCS);
954 pr_err("Disable RX engine timeout\n");
957 * Stop clock for RX MAC Processor
959 jme_mac_rxclk_off(jme);
963 jme_udpsum(struct sk_buff *skb)
967 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
969 if (skb->protocol != htons(ETH_P_IP))
971 skb_set_network_header(skb, ETH_HLEN);
972 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
973 (skb->len < (ETH_HLEN +
974 (ip_hdr(skb)->ihl << 2) +
975 sizeof(struct udphdr)))) {
976 skb_reset_network_header(skb);
979 skb_set_transport_header(skb,
980 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
981 csum = udp_hdr(skb)->check;
982 skb_reset_transport_header(skb);
983 skb_reset_network_header(skb);
989 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
991 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
994 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
995 == RXWBFLAG_TCPON)) {
996 if (flags & RXWBFLAG_IPV4)
997 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1001 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1002 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1003 if (flags & RXWBFLAG_IPV4)
1004 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1008 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1009 == RXWBFLAG_IPV4)) {
1010 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1018 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1020 struct jme_ring *rxring = &(jme->rxring[0]);
1021 struct rxdesc *rxdesc = rxring->desc;
1022 struct jme_buffer_info *rxbi = rxring->bufinf;
1023 struct sk_buff *skb;
1030 pci_dma_sync_single_for_cpu(jme->pdev,
1033 PCI_DMA_FROMDEVICE);
1035 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1036 pci_dma_sync_single_for_device(jme->pdev,
1039 PCI_DMA_FROMDEVICE);
1041 ++(NET_STAT(jme).rx_dropped);
1043 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1046 skb_reserve(skb, RX_PREPAD_SIZE);
1047 skb_put(skb, framesize);
1048 skb->protocol = eth_type_trans(skb, jme->dev);
1050 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1051 skb->ip_summed = CHECKSUM_UNNECESSARY;
1053 skb_checksum_none_assert(skb);
1055 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1056 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1058 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1059 NET_STAT(jme).rx_bytes += 4;
1063 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1064 cpu_to_le16(RXWBFLAG_DEST_MUL))
1065 ++(NET_STAT(jme).multicast);
1067 NET_STAT(jme).rx_bytes += framesize;
1068 ++(NET_STAT(jme).rx_packets);
1071 jme_set_clean_rxdesc(jme, idx);
1076 jme_process_receive(struct jme_adapter *jme, int limit)
1078 struct jme_ring *rxring = &(jme->rxring[0]);
1079 struct rxdesc *rxdesc = rxring->desc;
1080 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1082 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1085 if (unlikely(atomic_read(&jme->link_changing) != 1))
1088 if (unlikely(!netif_carrier_ok(jme->dev)))
1091 i = atomic_read(&rxring->next_to_clean);
1093 rxdesc = rxring->desc;
1096 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1097 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1102 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1104 if (unlikely(desccnt > 1 ||
1105 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1107 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1108 ++(NET_STAT(jme).rx_crc_errors);
1109 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1110 ++(NET_STAT(jme).rx_fifo_errors);
1112 ++(NET_STAT(jme).rx_errors);
1115 limit -= desccnt - 1;
1117 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1118 jme_set_clean_rxdesc(jme, j);
1119 j = (j + 1) & (mask);
1123 jme_alloc_and_feed_skb(jme, i);
1126 i = (i + desccnt) & (mask);
1130 atomic_set(&rxring->next_to_clean, i);
1133 atomic_inc(&jme->rx_cleaning);
1135 return limit > 0 ? limit : 0;
1140 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1142 if (likely(atmp == dpi->cur)) {
1147 if (dpi->attempt == atmp) {
1150 dpi->attempt = atmp;
1157 jme_dynamic_pcc(struct jme_adapter *jme)
1159 register struct dynpcc_info *dpi = &(jme->dpi);
1161 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1162 jme_attempt_pcc(dpi, PCC_P3);
1163 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1164 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1165 jme_attempt_pcc(dpi, PCC_P2);
1167 jme_attempt_pcc(dpi, PCC_P1);
1169 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1170 if (dpi->attempt < dpi->cur)
1171 tasklet_schedule(&jme->rxclean_task);
1172 jme_set_rx_pcc(jme, dpi->attempt);
1173 dpi->cur = dpi->attempt;
1179 jme_start_pcc_timer(struct jme_adapter *jme)
1181 struct dynpcc_info *dpi = &(jme->dpi);
1182 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1183 dpi->last_pkts = NET_STAT(jme).rx_packets;
1185 jwrite32(jme, JME_TMCSR,
1186 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1190 jme_stop_pcc_timer(struct jme_adapter *jme)
1192 jwrite32(jme, JME_TMCSR, 0);
1196 jme_shutdown_nic(struct jme_adapter *jme)
1200 phylink = jme_linkstat_from_phy(jme);
1202 if (!(phylink & PHY_LINK_UP)) {
1204 * Disable all interrupt before issue timer
1207 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1212 jme_pcc_tasklet(unsigned long arg)
1214 struct jme_adapter *jme = (struct jme_adapter *)arg;
1215 struct net_device *netdev = jme->dev;
1217 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1218 jme_shutdown_nic(jme);
1222 if (unlikely(!netif_carrier_ok(netdev) ||
1223 (atomic_read(&jme->link_changing) != 1)
1225 jme_stop_pcc_timer(jme);
1229 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1230 jme_dynamic_pcc(jme);
1232 jme_start_pcc_timer(jme);
1236 jme_polling_mode(struct jme_adapter *jme)
1238 jme_set_rx_pcc(jme, PCC_OFF);
1242 jme_interrupt_mode(struct jme_adapter *jme)
1244 jme_set_rx_pcc(jme, PCC_P1);
1248 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1251 apmc = jread32(jme, JME_APMC);
1252 return apmc & JME_APMC_PSEUDO_HP_EN;
1256 jme_start_shutdown_timer(struct jme_adapter *jme)
1260 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1261 apmc &= ~JME_APMC_EPIEN_CTRL;
1263 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1266 jwrite32f(jme, JME_APMC, apmc);
1268 jwrite32f(jme, JME_TIMER2, 0);
1269 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1270 jwrite32(jme, JME_TMCSR,
1271 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1275 jme_stop_shutdown_timer(struct jme_adapter *jme)
1279 jwrite32f(jme, JME_TMCSR, 0);
1280 jwrite32f(jme, JME_TIMER2, 0);
1281 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1283 apmc = jread32(jme, JME_APMC);
1284 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1285 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1287 jwrite32f(jme, JME_APMC, apmc);
1291 jme_link_change_tasklet(unsigned long arg)
1293 struct jme_adapter *jme = (struct jme_adapter *)arg;
1294 struct net_device *netdev = jme->dev;
1297 while (!atomic_dec_and_test(&jme->link_changing)) {
1298 atomic_inc(&jme->link_changing);
1299 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1300 while (atomic_read(&jme->link_changing) != 1)
1301 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1304 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1307 jme->old_mtu = netdev->mtu;
1308 netif_stop_queue(netdev);
1309 if (jme_pseudo_hotplug_enabled(jme))
1310 jme_stop_shutdown_timer(jme);
1312 jme_stop_pcc_timer(jme);
1313 tasklet_disable(&jme->txclean_task);
1314 tasklet_disable(&jme->rxclean_task);
1315 tasklet_disable(&jme->rxempty_task);
1317 if (netif_carrier_ok(netdev)) {
1318 jme_disable_rx_engine(jme);
1319 jme_disable_tx_engine(jme);
1320 jme_reset_mac_processor(jme);
1321 jme_free_rx_resources(jme);
1322 jme_free_tx_resources(jme);
1324 if (test_bit(JME_FLAG_POLL, &jme->flags))
1325 jme_polling_mode(jme);
1327 netif_carrier_off(netdev);
1330 jme_check_link(netdev, 0);
1331 if (netif_carrier_ok(netdev)) {
1332 rc = jme_setup_rx_resources(jme);
1334 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1335 goto out_enable_tasklet;
1338 rc = jme_setup_tx_resources(jme);
1340 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1341 goto err_out_free_rx_resources;
1344 jme_enable_rx_engine(jme);
1345 jme_enable_tx_engine(jme);
1347 netif_start_queue(netdev);
1349 if (test_bit(JME_FLAG_POLL, &jme->flags))
1350 jme_interrupt_mode(jme);
1352 jme_start_pcc_timer(jme);
1353 } else if (jme_pseudo_hotplug_enabled(jme)) {
1354 jme_start_shutdown_timer(jme);
1357 goto out_enable_tasklet;
1359 err_out_free_rx_resources:
1360 jme_free_rx_resources(jme);
1362 tasklet_enable(&jme->txclean_task);
1363 tasklet_enable(&jme->rxclean_task);
1364 tasklet_enable(&jme->rxempty_task);
1366 atomic_inc(&jme->link_changing);
1370 jme_rx_clean_tasklet(unsigned long arg)
1372 struct jme_adapter *jme = (struct jme_adapter *)arg;
1373 struct dynpcc_info *dpi = &(jme->dpi);
1375 jme_process_receive(jme, jme->rx_ring_size);
1381 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1383 struct jme_adapter *jme = jme_napi_priv(holder);
1386 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1388 while (atomic_read(&jme->rx_empty) > 0) {
1389 atomic_dec(&jme->rx_empty);
1390 ++(NET_STAT(jme).rx_dropped);
1391 jme_restart_rx_engine(jme);
1393 atomic_inc(&jme->rx_empty);
1396 JME_RX_COMPLETE(netdev, holder);
1397 jme_interrupt_mode(jme);
1400 JME_NAPI_WEIGHT_SET(budget, rest);
1401 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1405 jme_rx_empty_tasklet(unsigned long arg)
1407 struct jme_adapter *jme = (struct jme_adapter *)arg;
1409 if (unlikely(atomic_read(&jme->link_changing) != 1))
1412 if (unlikely(!netif_carrier_ok(jme->dev)))
1415 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1417 jme_rx_clean_tasklet(arg);
1419 while (atomic_read(&jme->rx_empty) > 0) {
1420 atomic_dec(&jme->rx_empty);
1421 ++(NET_STAT(jme).rx_dropped);
1422 jme_restart_rx_engine(jme);
1424 atomic_inc(&jme->rx_empty);
1428 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1430 struct jme_ring *txring = &(jme->txring[0]);
1433 if (unlikely(netif_queue_stopped(jme->dev) &&
1434 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1435 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1436 netif_wake_queue(jme->dev);
1442 jme_tx_clean_tasklet(unsigned long arg)
1444 struct jme_adapter *jme = (struct jme_adapter *)arg;
1445 struct jme_ring *txring = &(jme->txring[0]);
1446 struct txdesc *txdesc = txring->desc;
1447 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1448 int i, j, cnt = 0, max, err, mask;
1450 tx_dbg(jme, "Into txclean\n");
1452 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1455 if (unlikely(atomic_read(&jme->link_changing) != 1))
1458 if (unlikely(!netif_carrier_ok(jme->dev)))
1461 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1462 mask = jme->tx_ring_mask;
1464 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1468 if (likely(ctxbi->skb &&
1469 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1471 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1472 i, ctxbi->nr_desc, jiffies);
1474 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1476 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1477 ttxbi = txbi + ((i + j) & (mask));
1478 txdesc[(i + j) & (mask)].dw[0] = 0;
1480 pci_unmap_page(jme->pdev,
1489 dev_kfree_skb(ctxbi->skb);
1491 cnt += ctxbi->nr_desc;
1493 if (unlikely(err)) {
1494 ++(NET_STAT(jme).tx_carrier_errors);
1496 ++(NET_STAT(jme).tx_packets);
1497 NET_STAT(jme).tx_bytes += ctxbi->len;
1502 ctxbi->start_xmit = 0;
1508 i = (i + ctxbi->nr_desc) & mask;
1513 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1514 atomic_set(&txring->next_to_clean, i);
1515 atomic_add(cnt, &txring->nr_free);
1517 jme_wake_queue_if_stopped(jme);
1520 atomic_inc(&jme->tx_cleaning);
1524 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1529 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1531 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1533 * Link change event is critical
1534 * all other events are ignored
1536 jwrite32(jme, JME_IEVE, intrstat);
1537 tasklet_schedule(&jme->linkch_task);
1541 if (intrstat & INTR_TMINTR) {
1542 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1543 tasklet_schedule(&jme->pcc_task);
1546 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1547 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1548 tasklet_schedule(&jme->txclean_task);
1551 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1552 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1558 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1559 if (intrstat & INTR_RX0EMP)
1560 atomic_inc(&jme->rx_empty);
1562 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1563 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1564 jme_polling_mode(jme);
1565 JME_RX_SCHEDULE(jme);
1569 if (intrstat & INTR_RX0EMP) {
1570 atomic_inc(&jme->rx_empty);
1571 tasklet_hi_schedule(&jme->rxempty_task);
1572 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1573 tasklet_hi_schedule(&jme->rxclean_task);
1579 * Re-enable interrupt
1581 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1585 jme_intr(int irq, void *dev_id)
1587 struct net_device *netdev = dev_id;
1588 struct jme_adapter *jme = netdev_priv(netdev);
1591 intrstat = jread32(jme, JME_IEVE);
1594 * Check if it's really an interrupt for us
1596 if (unlikely((intrstat & INTR_ENABLE) == 0))
1600 * Check if the device still exist
1602 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1605 jme_intr_msi(jme, intrstat);
1611 jme_msi(int irq, void *dev_id)
1613 struct net_device *netdev = dev_id;
1614 struct jme_adapter *jme = netdev_priv(netdev);
1617 intrstat = jread32(jme, JME_IEVE);
1619 jme_intr_msi(jme, intrstat);
1625 jme_reset_link(struct jme_adapter *jme)
1627 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1631 jme_restart_an(struct jme_adapter *jme)
1635 spin_lock_bh(&jme->phy_lock);
1636 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1637 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1638 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1639 spin_unlock_bh(&jme->phy_lock);
1643 jme_request_irq(struct jme_adapter *jme)
1646 struct net_device *netdev = jme->dev;
1647 irq_handler_t handler = jme_intr;
1648 int irq_flags = IRQF_SHARED;
1650 if (!pci_enable_msi(jme->pdev)) {
1651 set_bit(JME_FLAG_MSI, &jme->flags);
1656 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1660 "Unable to request %s interrupt (return: %d)\n",
1661 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1664 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1665 pci_disable_msi(jme->pdev);
1666 clear_bit(JME_FLAG_MSI, &jme->flags);
1669 netdev->irq = jme->pdev->irq;
1676 jme_free_irq(struct jme_adapter *jme)
1678 free_irq(jme->pdev->irq, jme->dev);
1679 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1680 pci_disable_msi(jme->pdev);
1681 clear_bit(JME_FLAG_MSI, &jme->flags);
1682 jme->dev->irq = jme->pdev->irq;
1687 jme_new_phy_on(struct jme_adapter *jme)
1691 reg = jread32(jme, JME_PHY_PWR);
1692 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1693 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1694 jwrite32(jme, JME_PHY_PWR, reg);
1696 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1697 reg &= ~PE1_GPREG0_PBG;
1698 reg |= PE1_GPREG0_ENBG;
1699 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1703 jme_new_phy_off(struct jme_adapter *jme)
1707 reg = jread32(jme, JME_PHY_PWR);
1708 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1709 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1710 jwrite32(jme, JME_PHY_PWR, reg);
1712 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1713 reg &= ~PE1_GPREG0_PBG;
1714 reg |= PE1_GPREG0_PDD3COLD;
1715 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1719 jme_phy_on(struct jme_adapter *jme)
1723 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1724 bmcr &= ~BMCR_PDOWN;
1725 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1727 if (new_phy_power_ctrl(jme->chip_main_rev))
1728 jme_new_phy_on(jme);
1732 jme_phy_off(struct jme_adapter *jme)
1736 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1738 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1740 if (new_phy_power_ctrl(jme->chip_main_rev))
1741 jme_new_phy_off(jme);
1745 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1749 phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1750 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1752 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1753 JM_PHY_SPEC_DATA_REG);
1757 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1761 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1762 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1764 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1769 jme_phy_calibration(struct jme_adapter *jme)
1771 u32 ctrl1000, phy_data;
1775 /* Enabel PHY test mode 1 */
1776 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1777 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1778 ctrl1000 |= PHY_GAD_TEST_MODE_1;
1779 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1781 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1782 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1783 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1784 JM_PHY_EXT_COMM_2_CALI_ENABLE;
1785 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1787 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1788 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1789 JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1790 JM_PHY_EXT_COMM_2_CALI_LATCH);
1791 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1793 /* Disable PHY test mode */
1794 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1795 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1796 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1801 jme_phy_setEA(struct jme_adapter *jme)
1803 u32 phy_comm0 = 0, phy_comm1 = 0;
1806 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1807 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1810 switch (jme->pdev->device) {
1811 case PCI_DEVICE_ID_JMICRON_JMC250:
1812 if (((jme->chip_main_rev == 5) &&
1813 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1814 (jme->chip_sub_rev == 3))) ||
1815 (jme->chip_main_rev >= 6)) {
1819 if ((jme->chip_main_rev == 3) &&
1820 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1823 case PCI_DEVICE_ID_JMICRON_JMC260:
1824 if (((jme->chip_main_rev == 5) &&
1825 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1826 (jme->chip_sub_rev == 3))) ||
1827 (jme->chip_main_rev >= 6)) {
1831 if ((jme->chip_main_rev == 3) &&
1832 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1834 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1836 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1843 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1845 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1851 jme_open(struct net_device *netdev)
1853 struct jme_adapter *jme = netdev_priv(netdev);
1857 JME_NAPI_ENABLE(jme);
1859 tasklet_init(&jme->linkch_task, jme_link_change_tasklet,
1860 (unsigned long) jme);
1861 tasklet_init(&jme->txclean_task, jme_tx_clean_tasklet,
1862 (unsigned long) jme);
1863 tasklet_init(&jme->rxclean_task, jme_rx_clean_tasklet,
1864 (unsigned long) jme);
1865 tasklet_init(&jme->rxempty_task, jme_rx_empty_tasklet,
1866 (unsigned long) jme);
1868 rc = jme_request_irq(jme);
1875 if (test_bit(JME_FLAG_SSET, &jme->flags))
1876 jme_set_settings(netdev, &jme->old_ecmd);
1878 jme_reset_phy_processor(jme);
1879 jme_phy_calibration(jme);
1881 jme_reset_link(jme);
1886 netif_stop_queue(netdev);
1887 netif_carrier_off(netdev);
1892 jme_set_100m_half(struct jme_adapter *jme)
1897 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1898 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1899 BMCR_SPEED1000 | BMCR_FULLDPLX);
1900 tmp |= BMCR_SPEED100;
1903 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1906 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1908 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1911 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1913 jme_wait_link(struct jme_adapter *jme)
1915 u32 phylink, to = JME_WAIT_LINK_TIME;
1918 phylink = jme_linkstat_from_phy(jme);
1919 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1921 phylink = jme_linkstat_from_phy(jme);
1926 jme_powersave_phy(struct jme_adapter *jme)
1928 if (jme->reg_pmcs) {
1929 jme_set_100m_half(jme);
1930 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1939 jme_close(struct net_device *netdev)
1941 struct jme_adapter *jme = netdev_priv(netdev);
1943 netif_stop_queue(netdev);
1944 netif_carrier_off(netdev);
1949 JME_NAPI_DISABLE(jme);
1951 tasklet_kill(&jme->linkch_task);
1952 tasklet_kill(&jme->txclean_task);
1953 tasklet_kill(&jme->rxclean_task);
1954 tasklet_kill(&jme->rxempty_task);
1956 jme_disable_rx_engine(jme);
1957 jme_disable_tx_engine(jme);
1958 jme_reset_mac_processor(jme);
1959 jme_free_rx_resources(jme);
1960 jme_free_tx_resources(jme);
1968 jme_alloc_txdesc(struct jme_adapter *jme,
1969 struct sk_buff *skb)
1971 struct jme_ring *txring = &(jme->txring[0]);
1972 int idx, nr_alloc, mask = jme->tx_ring_mask;
1974 idx = txring->next_to_use;
1975 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1977 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1980 atomic_sub(nr_alloc, &txring->nr_free);
1982 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1988 jme_fill_tx_map(struct pci_dev *pdev,
1989 struct txdesc *txdesc,
1990 struct jme_buffer_info *txbi,
1998 dmaaddr = pci_map_page(pdev,
2004 if (unlikely(pci_dma_mapping_error(pdev, dmaaddr)))
2007 pci_dma_sync_single_for_device(pdev,
2014 txdesc->desc2.flags = TXFLAG_OWN;
2015 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
2016 txdesc->desc2.datalen = cpu_to_le16(len);
2017 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
2018 txdesc->desc2.bufaddrl = cpu_to_le32(
2019 (__u64)dmaaddr & 0xFFFFFFFFUL);
2021 txbi->mapping = dmaaddr;
2026 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
2028 struct jme_ring *txring = &(jme->txring[0]);
2029 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2030 int mask = jme->tx_ring_mask;
2033 for (j = 0 ; j < count ; j++) {
2034 ctxbi = txbi + ((startidx + j + 2) & (mask));
2035 pci_unmap_page(jme->pdev,
2047 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2049 struct jme_ring *txring = &(jme->txring[0]);
2050 struct txdesc *txdesc = txring->desc, *ctxdesc;
2051 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2052 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2053 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2054 int mask = jme->tx_ring_mask;
2055 const struct skb_frag_struct *frag;
2059 for (i = 0 ; i < nr_frags ; ++i) {
2060 frag = &skb_shinfo(skb)->frags[i];
2061 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2062 ctxbi = txbi + ((idx + i + 2) & (mask));
2064 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2065 skb_frag_page(frag),
2066 frag->page_offset, skb_frag_size(frag), hidma);
2068 jme_drop_tx_map(jme, idx, i);
2074 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2075 ctxdesc = txdesc + ((idx + 1) & (mask));
2076 ctxbi = txbi + ((idx + 1) & (mask));
2077 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2078 offset_in_page(skb->data), len, hidma);
2080 jme_drop_tx_map(jme, idx, i);
2089 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2091 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2093 *flags |= TXFLAG_LSEN;
2095 if (skb->protocol == htons(ETH_P_IP)) {
2096 struct iphdr *iph = ip_hdr(skb);
2099 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2104 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2106 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2119 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2121 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2124 switch (skb->protocol) {
2125 case htons(ETH_P_IP):
2126 ip_proto = ip_hdr(skb)->protocol;
2128 case htons(ETH_P_IPV6):
2129 ip_proto = ipv6_hdr(skb)->nexthdr;
2138 *flags |= TXFLAG_TCPCS;
2141 *flags |= TXFLAG_UDPCS;
2144 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2151 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2153 if (skb_vlan_tag_present(skb)) {
2154 *flags |= TXFLAG_TAGON;
2155 *vlan = cpu_to_le16(skb_vlan_tag_get(skb));
2160 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2162 struct jme_ring *txring = &(jme->txring[0]);
2163 struct txdesc *txdesc;
2164 struct jme_buffer_info *txbi;
2168 txdesc = (struct txdesc *)txring->desc + idx;
2169 txbi = txring->bufinf + idx;
2175 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2177 * Set OWN bit at final.
2178 * When kernel transmit faster than NIC.
2179 * And NIC trying to send this descriptor before we tell
2180 * it to start sending this TX queue.
2181 * Other fields are already filled correctly.
2184 flags = TXFLAG_OWN | TXFLAG_INT;
2186 * Set checksum flags while not tso
2188 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2189 jme_tx_csum(jme, skb, &flags);
2190 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2191 ret = jme_map_tx_skb(jme, skb, idx);
2195 txdesc->desc1.flags = flags;
2197 * Set tx buffer info after telling NIC to send
2198 * For better tx_clean timing
2201 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2203 txbi->len = skb->len;
2204 txbi->start_xmit = jiffies;
2205 if (!txbi->start_xmit)
2206 txbi->start_xmit = (0UL-1);
2212 jme_stop_queue_if_full(struct jme_adapter *jme)
2214 struct jme_ring *txring = &(jme->txring[0]);
2215 struct jme_buffer_info *txbi = txring->bufinf;
2216 int idx = atomic_read(&txring->next_to_clean);
2221 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2222 netif_stop_queue(jme->dev);
2223 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2225 if (atomic_read(&txring->nr_free)
2226 >= (jme->tx_wake_threshold)) {
2227 netif_wake_queue(jme->dev);
2228 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2232 if (unlikely(txbi->start_xmit &&
2233 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2235 netif_stop_queue(jme->dev);
2236 netif_info(jme, tx_queued, jme->dev,
2237 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2242 * This function is already protected by netif_tx_lock()
2246 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2248 struct jme_adapter *jme = netdev_priv(netdev);
2251 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
2252 dev_kfree_skb_any(skb);
2253 ++(NET_STAT(jme).tx_dropped);
2254 return NETDEV_TX_OK;
2257 idx = jme_alloc_txdesc(jme, skb);
2259 if (unlikely(idx < 0)) {
2260 netif_stop_queue(netdev);
2261 netif_err(jme, tx_err, jme->dev,
2262 "BUG! Tx ring full when queue awake!\n");
2264 return NETDEV_TX_BUSY;
2267 if (jme_fill_tx_desc(jme, skb, idx))
2268 return NETDEV_TX_OK;
2270 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2271 TXCS_SELECT_QUEUE0 |
2275 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2276 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2277 jme_stop_queue_if_full(jme);
2279 return NETDEV_TX_OK;
2283 jme_set_unicastaddr(struct net_device *netdev)
2285 struct jme_adapter *jme = netdev_priv(netdev);
2288 val = (netdev->dev_addr[3] & 0xff) << 24 |
2289 (netdev->dev_addr[2] & 0xff) << 16 |
2290 (netdev->dev_addr[1] & 0xff) << 8 |
2291 (netdev->dev_addr[0] & 0xff);
2292 jwrite32(jme, JME_RXUMA_LO, val);
2293 val = (netdev->dev_addr[5] & 0xff) << 8 |
2294 (netdev->dev_addr[4] & 0xff);
2295 jwrite32(jme, JME_RXUMA_HI, val);
2299 jme_set_macaddr(struct net_device *netdev, void *p)
2301 struct jme_adapter *jme = netdev_priv(netdev);
2302 struct sockaddr *addr = p;
2304 if (netif_running(netdev))
2307 spin_lock_bh(&jme->macaddr_lock);
2308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2309 jme_set_unicastaddr(netdev);
2310 spin_unlock_bh(&jme->macaddr_lock);
2316 jme_set_multi(struct net_device *netdev)
2318 struct jme_adapter *jme = netdev_priv(netdev);
2319 u32 mc_hash[2] = {};
2321 spin_lock_bh(&jme->rxmcs_lock);
2323 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2325 if (netdev->flags & IFF_PROMISC) {
2326 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2327 } else if (netdev->flags & IFF_ALLMULTI) {
2328 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2329 } else if (netdev->flags & IFF_MULTICAST) {
2330 struct netdev_hw_addr *ha;
2333 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2334 netdev_for_each_mc_addr(ha, netdev) {
2335 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2336 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2339 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2340 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2344 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2346 spin_unlock_bh(&jme->rxmcs_lock);
2350 jme_change_mtu(struct net_device *netdev, int new_mtu)
2352 struct jme_adapter *jme = netdev_priv(netdev);
2354 if (new_mtu == jme->old_mtu)
2357 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2358 ((new_mtu) < IPV6_MIN_MTU))
2362 netdev->mtu = new_mtu;
2363 netdev_update_features(netdev);
2365 jme_restart_rx_engine(jme);
2366 jme_reset_link(jme);
2372 jme_tx_timeout(struct net_device *netdev)
2374 struct jme_adapter *jme = netdev_priv(netdev);
2377 jme_reset_phy_processor(jme);
2378 if (test_bit(JME_FLAG_SSET, &jme->flags))
2379 jme_set_settings(netdev, &jme->old_ecmd);
2382 * Force to Reset the link again
2384 jme_reset_link(jme);
2387 static inline void jme_pause_rx(struct jme_adapter *jme)
2389 atomic_dec(&jme->link_changing);
2391 jme_set_rx_pcc(jme, PCC_OFF);
2392 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2393 JME_NAPI_DISABLE(jme);
2395 tasklet_disable(&jme->rxclean_task);
2396 tasklet_disable(&jme->rxempty_task);
2400 static inline void jme_resume_rx(struct jme_adapter *jme)
2402 struct dynpcc_info *dpi = &(jme->dpi);
2404 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2405 JME_NAPI_ENABLE(jme);
2407 tasklet_enable(&jme->rxclean_task);
2408 tasklet_enable(&jme->rxempty_task);
2411 dpi->attempt = PCC_P1;
2413 jme_set_rx_pcc(jme, PCC_P1);
2415 atomic_inc(&jme->link_changing);
2419 jme_get_drvinfo(struct net_device *netdev,
2420 struct ethtool_drvinfo *info)
2422 struct jme_adapter *jme = netdev_priv(netdev);
2424 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2425 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2426 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2430 jme_get_regs_len(struct net_device *netdev)
2436 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2440 for (i = 0 ; i < len ; i += 4)
2441 p[i >> 2] = jread32(jme, reg + i);
2445 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2448 u16 *p16 = (u16 *)p;
2450 for (i = 0 ; i < reg_nr ; ++i)
2451 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2455 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2457 struct jme_adapter *jme = netdev_priv(netdev);
2458 u32 *p32 = (u32 *)p;
2460 memset(p, 0xFF, JME_REG_LEN);
2463 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2466 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2469 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2472 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2475 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2479 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2481 struct jme_adapter *jme = netdev_priv(netdev);
2483 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2484 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2486 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2487 ecmd->use_adaptive_rx_coalesce = false;
2488 ecmd->rx_coalesce_usecs = 0;
2489 ecmd->rx_max_coalesced_frames = 0;
2493 ecmd->use_adaptive_rx_coalesce = true;
2495 switch (jme->dpi.cur) {
2497 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2498 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2501 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2502 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2505 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2506 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2516 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2518 struct jme_adapter *jme = netdev_priv(netdev);
2519 struct dynpcc_info *dpi = &(jme->dpi);
2521 if (netif_running(netdev))
2524 if (ecmd->use_adaptive_rx_coalesce &&
2525 test_bit(JME_FLAG_POLL, &jme->flags)) {
2526 clear_bit(JME_FLAG_POLL, &jme->flags);
2527 jme->jme_rx = netif_rx;
2529 dpi->attempt = PCC_P1;
2531 jme_set_rx_pcc(jme, PCC_P1);
2532 jme_interrupt_mode(jme);
2533 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2534 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2535 set_bit(JME_FLAG_POLL, &jme->flags);
2536 jme->jme_rx = netif_receive_skb;
2537 jme_interrupt_mode(jme);
2544 jme_get_pauseparam(struct net_device *netdev,
2545 struct ethtool_pauseparam *ecmd)
2547 struct jme_adapter *jme = netdev_priv(netdev);
2550 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2551 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2553 spin_lock_bh(&jme->phy_lock);
2554 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2555 spin_unlock_bh(&jme->phy_lock);
2558 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2562 jme_set_pauseparam(struct net_device *netdev,
2563 struct ethtool_pauseparam *ecmd)
2565 struct jme_adapter *jme = netdev_priv(netdev);
2568 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2569 (ecmd->tx_pause != 0)) {
2572 jme->reg_txpfc |= TXPFC_PF_EN;
2574 jme->reg_txpfc &= ~TXPFC_PF_EN;
2576 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2579 spin_lock_bh(&jme->rxmcs_lock);
2580 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2581 (ecmd->rx_pause != 0)) {
2584 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2586 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2588 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2590 spin_unlock_bh(&jme->rxmcs_lock);
2592 spin_lock_bh(&jme->phy_lock);
2593 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2594 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2595 (ecmd->autoneg != 0)) {
2598 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2600 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2602 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2603 MII_ADVERTISE, val);
2605 spin_unlock_bh(&jme->phy_lock);
2611 jme_get_wol(struct net_device *netdev,
2612 struct ethtool_wolinfo *wol)
2614 struct jme_adapter *jme = netdev_priv(netdev);
2616 wol->supported = WAKE_MAGIC | WAKE_PHY;
2620 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2621 wol->wolopts |= WAKE_PHY;
2623 if (jme->reg_pmcs & PMCS_MFEN)
2624 wol->wolopts |= WAKE_MAGIC;
2629 jme_set_wol(struct net_device *netdev,
2630 struct ethtool_wolinfo *wol)
2632 struct jme_adapter *jme = netdev_priv(netdev);
2634 if (wol->wolopts & (WAKE_MAGICSECURE |
2643 if (wol->wolopts & WAKE_PHY)
2644 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2646 if (wol->wolopts & WAKE_MAGIC)
2647 jme->reg_pmcs |= PMCS_MFEN;
2649 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2650 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2656 jme_get_settings(struct net_device *netdev,
2657 struct ethtool_cmd *ecmd)
2659 struct jme_adapter *jme = netdev_priv(netdev);
2662 spin_lock_bh(&jme->phy_lock);
2663 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2664 spin_unlock_bh(&jme->phy_lock);
2669 jme_set_settings(struct net_device *netdev,
2670 struct ethtool_cmd *ecmd)
2672 struct jme_adapter *jme = netdev_priv(netdev);
2675 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2676 && ecmd->autoneg != AUTONEG_ENABLE)
2680 * Check If user changed duplex only while force_media.
2681 * Hardware would not generate link change interrupt.
2683 if (jme->mii_if.force_media &&
2684 ecmd->autoneg != AUTONEG_ENABLE &&
2685 (jme->mii_if.full_duplex != ecmd->duplex))
2688 spin_lock_bh(&jme->phy_lock);
2689 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2690 spin_unlock_bh(&jme->phy_lock);
2694 jme_reset_link(jme);
2695 jme->old_ecmd = *ecmd;
2696 set_bit(JME_FLAG_SSET, &jme->flags);
2703 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2706 struct jme_adapter *jme = netdev_priv(netdev);
2707 struct mii_ioctl_data *mii_data = if_mii(rq);
2708 unsigned int duplex_chg;
2710 if (cmd == SIOCSMIIREG) {
2711 u16 val = mii_data->val_in;
2712 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2713 (val & BMCR_SPEED1000))
2717 spin_lock_bh(&jme->phy_lock);
2718 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2719 spin_unlock_bh(&jme->phy_lock);
2721 if (!rc && (cmd == SIOCSMIIREG)) {
2723 jme_reset_link(jme);
2724 jme_get_settings(netdev, &jme->old_ecmd);
2725 set_bit(JME_FLAG_SSET, &jme->flags);
2732 jme_get_link(struct net_device *netdev)
2734 struct jme_adapter *jme = netdev_priv(netdev);
2735 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2739 jme_get_msglevel(struct net_device *netdev)
2741 struct jme_adapter *jme = netdev_priv(netdev);
2742 return jme->msg_enable;
2746 jme_set_msglevel(struct net_device *netdev, u32 value)
2748 struct jme_adapter *jme = netdev_priv(netdev);
2749 jme->msg_enable = value;
2752 static netdev_features_t
2753 jme_fix_features(struct net_device *netdev, netdev_features_t features)
2755 if (netdev->mtu > 1900)
2756 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2761 jme_set_features(struct net_device *netdev, netdev_features_t features)
2763 struct jme_adapter *jme = netdev_priv(netdev);
2765 spin_lock_bh(&jme->rxmcs_lock);
2766 if (features & NETIF_F_RXCSUM)
2767 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2769 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2770 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2771 spin_unlock_bh(&jme->rxmcs_lock);
2776 #ifdef CONFIG_NET_POLL_CONTROLLER
2777 static void jme_netpoll(struct net_device *dev)
2779 unsigned long flags;
2781 local_irq_save(flags);
2782 jme_intr(dev->irq, dev);
2783 local_irq_restore(flags);
2788 jme_nway_reset(struct net_device *netdev)
2790 struct jme_adapter *jme = netdev_priv(netdev);
2791 jme_restart_an(jme);
2796 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2801 val = jread32(jme, JME_SMBCSR);
2802 to = JME_SMB_BUSY_TIMEOUT;
2803 while ((val & SMBCSR_BUSY) && --to) {
2805 val = jread32(jme, JME_SMBCSR);
2808 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2812 jwrite32(jme, JME_SMBINTF,
2813 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2814 SMBINTF_HWRWN_READ |
2817 val = jread32(jme, JME_SMBINTF);
2818 to = JME_SMB_BUSY_TIMEOUT;
2819 while ((val & SMBINTF_HWCMD) && --to) {
2821 val = jread32(jme, JME_SMBINTF);
2824 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2828 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2832 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2837 val = jread32(jme, JME_SMBCSR);
2838 to = JME_SMB_BUSY_TIMEOUT;
2839 while ((val & SMBCSR_BUSY) && --to) {
2841 val = jread32(jme, JME_SMBCSR);
2844 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2848 jwrite32(jme, JME_SMBINTF,
2849 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2850 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2851 SMBINTF_HWRWN_WRITE |
2854 val = jread32(jme, JME_SMBINTF);
2855 to = JME_SMB_BUSY_TIMEOUT;
2856 while ((val & SMBINTF_HWCMD) && --to) {
2858 val = jread32(jme, JME_SMBINTF);
2861 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2869 jme_get_eeprom_len(struct net_device *netdev)
2871 struct jme_adapter *jme = netdev_priv(netdev);
2873 val = jread32(jme, JME_SMBCSR);
2874 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2878 jme_get_eeprom(struct net_device *netdev,
2879 struct ethtool_eeprom *eeprom, u8 *data)
2881 struct jme_adapter *jme = netdev_priv(netdev);
2882 int i, offset = eeprom->offset, len = eeprom->len;
2885 * ethtool will check the boundary for us
2887 eeprom->magic = JME_EEPROM_MAGIC;
2888 for (i = 0 ; i < len ; ++i)
2889 data[i] = jme_smb_read(jme, i + offset);
2895 jme_set_eeprom(struct net_device *netdev,
2896 struct ethtool_eeprom *eeprom, u8 *data)
2898 struct jme_adapter *jme = netdev_priv(netdev);
2899 int i, offset = eeprom->offset, len = eeprom->len;
2901 if (eeprom->magic != JME_EEPROM_MAGIC)
2905 * ethtool will check the boundary for us
2907 for (i = 0 ; i < len ; ++i)
2908 jme_smb_write(jme, i + offset, data[i]);
2913 static const struct ethtool_ops jme_ethtool_ops = {
2914 .get_drvinfo = jme_get_drvinfo,
2915 .get_regs_len = jme_get_regs_len,
2916 .get_regs = jme_get_regs,
2917 .get_coalesce = jme_get_coalesce,
2918 .set_coalesce = jme_set_coalesce,
2919 .get_pauseparam = jme_get_pauseparam,
2920 .set_pauseparam = jme_set_pauseparam,
2921 .get_wol = jme_get_wol,
2922 .set_wol = jme_set_wol,
2923 .get_settings = jme_get_settings,
2924 .set_settings = jme_set_settings,
2925 .get_link = jme_get_link,
2926 .get_msglevel = jme_get_msglevel,
2927 .set_msglevel = jme_set_msglevel,
2928 .nway_reset = jme_nway_reset,
2929 .get_eeprom_len = jme_get_eeprom_len,
2930 .get_eeprom = jme_get_eeprom,
2931 .set_eeprom = jme_set_eeprom,
2935 jme_pci_dma64(struct pci_dev *pdev)
2937 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2938 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2939 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2942 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2943 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2944 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2947 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2948 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2955 jme_phy_init(struct jme_adapter *jme)
2959 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2960 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2964 jme_check_hw_ver(struct jme_adapter *jme)
2968 chipmode = jread32(jme, JME_CHIPMODE);
2970 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2971 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2972 jme->chip_main_rev = jme->chiprev & 0xF;
2973 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2976 static const struct net_device_ops jme_netdev_ops = {
2977 .ndo_open = jme_open,
2978 .ndo_stop = jme_close,
2979 .ndo_validate_addr = eth_validate_addr,
2980 .ndo_do_ioctl = jme_ioctl,
2981 .ndo_start_xmit = jme_start_xmit,
2982 .ndo_set_mac_address = jme_set_macaddr,
2983 .ndo_set_rx_mode = jme_set_multi,
2984 .ndo_change_mtu = jme_change_mtu,
2985 .ndo_tx_timeout = jme_tx_timeout,
2986 .ndo_fix_features = jme_fix_features,
2987 .ndo_set_features = jme_set_features,
2988 #ifdef CONFIG_NET_POLL_CONTROLLER
2989 .ndo_poll_controller = jme_netpoll,
2994 jme_init_one(struct pci_dev *pdev,
2995 const struct pci_device_id *ent)
2997 int rc = 0, using_dac, i;
2998 struct net_device *netdev;
2999 struct jme_adapter *jme;
3004 * set up PCI device basics
3006 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3007 PCIE_LINK_STATE_CLKPM);
3009 rc = pci_enable_device(pdev);
3011 pr_err("Cannot enable PCI device\n");
3015 using_dac = jme_pci_dma64(pdev);
3016 if (using_dac < 0) {
3017 pr_err("Cannot set PCI DMA Mask\n");
3019 goto err_out_disable_pdev;
3022 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3023 pr_err("No PCI resource region found\n");
3025 goto err_out_disable_pdev;
3028 rc = pci_request_regions(pdev, DRV_NAME);
3030 pr_err("Cannot obtain PCI resource region\n");
3031 goto err_out_disable_pdev;
3034 pci_set_master(pdev);
3037 * alloc and init net device
3039 netdev = alloc_etherdev(sizeof(*jme));
3042 goto err_out_release_regions;
3044 netdev->netdev_ops = &jme_netdev_ops;
3045 netdev->ethtool_ops = &jme_ethtool_ops;
3046 netdev->watchdog_timeo = TX_TIMEOUT;
3047 netdev->hw_features = NETIF_F_IP_CSUM |
3053 netdev->features = NETIF_F_IP_CSUM |
3058 NETIF_F_HW_VLAN_CTAG_TX |
3059 NETIF_F_HW_VLAN_CTAG_RX;
3061 netdev->features |= NETIF_F_HIGHDMA;
3063 SET_NETDEV_DEV(netdev, &pdev->dev);
3064 pci_set_drvdata(pdev, netdev);
3069 jme = netdev_priv(netdev);
3072 jme->jme_rx = netif_rx;
3073 jme->old_mtu = netdev->mtu = 1500;
3075 jme->tx_ring_size = 1 << 10;
3076 jme->tx_ring_mask = jme->tx_ring_size - 1;
3077 jme->tx_wake_threshold = 1 << 9;
3078 jme->rx_ring_size = 1 << 9;
3079 jme->rx_ring_mask = jme->rx_ring_size - 1;
3080 jme->msg_enable = JME_DEF_MSG_ENABLE;
3081 jme->regs = ioremap(pci_resource_start(pdev, 0),
3082 pci_resource_len(pdev, 0));
3084 pr_err("Mapping PCI resource region error\n");
3086 goto err_out_free_netdev;
3090 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3091 jwrite32(jme, JME_APMC, apmc);
3092 } else if (force_pseudohp) {
3093 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3094 jwrite32(jme, JME_APMC, apmc);
3097 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT)
3099 spin_lock_init(&jme->phy_lock);
3100 spin_lock_init(&jme->macaddr_lock);
3101 spin_lock_init(&jme->rxmcs_lock);
3103 atomic_set(&jme->link_changing, 1);
3104 atomic_set(&jme->rx_cleaning, 1);
3105 atomic_set(&jme->tx_cleaning, 1);
3106 atomic_set(&jme->rx_empty, 1);
3108 tasklet_init(&jme->pcc_task,
3110 (unsigned long) jme);
3111 jme->dpi.cur = PCC_P1;
3114 jme->reg_rxcs = RXCS_DEFAULT;
3115 jme->reg_rxmcs = RXMCS_DEFAULT;
3117 jme->reg_pmcs = PMCS_MFEN;
3118 jme->reg_gpreg1 = GPREG1_DEFAULT;
3120 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3121 netdev->features |= NETIF_F_RXCSUM;
3124 * Get Max Read Req Size from PCI Config Space
3126 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3127 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3128 switch (jme->mrrs) {
3130 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3133 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3136 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3141 * Must check before reset_mac_processor
3143 jme_check_hw_ver(jme);
3144 jme->mii_if.dev = netdev;
3146 jme->mii_if.phy_id = 0;
3147 for (i = 1 ; i < 32 ; ++i) {
3148 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3149 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3150 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3151 jme->mii_if.phy_id = i;
3156 if (!jme->mii_if.phy_id) {
3158 pr_err("Can not find phy_id\n");
3162 jme->reg_ghc |= GHC_LINK_POLL;
3164 jme->mii_if.phy_id = 1;
3166 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3167 jme->mii_if.supports_gmii = true;
3169 jme->mii_if.supports_gmii = false;
3170 jme->mii_if.phy_id_mask = 0x1F;
3171 jme->mii_if.reg_num_mask = 0x1F;
3172 jme->mii_if.mdio_read = jme_mdio_read;
3173 jme->mii_if.mdio_write = jme_mdio_write;
3176 device_set_wakeup_enable(&pdev->dev, true);
3178 jme_set_phyfifo_5level(jme);
3179 jme->pcirev = pdev->revision;
3185 * Reset MAC processor and reload EEPROM for MAC Address
3187 jme_reset_mac_processor(jme);
3188 rc = jme_reload_eeprom(jme);
3190 pr_err("Reload eeprom for reading MAC Address error\n");
3193 jme_load_macaddr(netdev);
3196 * Tell stack that we are not ready to work until open()
3198 netif_carrier_off(netdev);
3200 rc = register_netdev(netdev);
3202 pr_err("Cannot register net device\n");
3206 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3207 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3208 "JMC250 Gigabit Ethernet" :
3209 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3210 "JMC260 Fast Ethernet" : "Unknown",
3211 (jme->fpgaver != 0) ? " (FPGA)" : "",
3212 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3213 jme->pcirev, netdev->dev_addr);
3219 err_out_free_netdev:
3220 free_netdev(netdev);
3221 err_out_release_regions:
3222 pci_release_regions(pdev);
3223 err_out_disable_pdev:
3224 pci_disable_device(pdev);
3230 jme_remove_one(struct pci_dev *pdev)
3232 struct net_device *netdev = pci_get_drvdata(pdev);
3233 struct jme_adapter *jme = netdev_priv(netdev);
3235 unregister_netdev(netdev);
3237 free_netdev(netdev);
3238 pci_release_regions(pdev);
3239 pci_disable_device(pdev);
3244 jme_shutdown(struct pci_dev *pdev)
3246 struct net_device *netdev = pci_get_drvdata(pdev);
3247 struct jme_adapter *jme = netdev_priv(netdev);
3249 jme_powersave_phy(jme);
3250 pci_pme_active(pdev, true);
3253 #ifdef CONFIG_PM_SLEEP
3255 jme_suspend(struct device *dev)
3257 struct pci_dev *pdev = to_pci_dev(dev);
3258 struct net_device *netdev = pci_get_drvdata(pdev);
3259 struct jme_adapter *jme = netdev_priv(netdev);
3261 if (!netif_running(netdev))
3264 atomic_dec(&jme->link_changing);
3266 netif_device_detach(netdev);
3267 netif_stop_queue(netdev);
3270 tasklet_disable(&jme->txclean_task);
3271 tasklet_disable(&jme->rxclean_task);
3272 tasklet_disable(&jme->rxempty_task);
3274 if (netif_carrier_ok(netdev)) {
3275 if (test_bit(JME_FLAG_POLL, &jme->flags))
3276 jme_polling_mode(jme);
3278 jme_stop_pcc_timer(jme);
3279 jme_disable_rx_engine(jme);
3280 jme_disable_tx_engine(jme);
3281 jme_reset_mac_processor(jme);
3282 jme_free_rx_resources(jme);
3283 jme_free_tx_resources(jme);
3284 netif_carrier_off(netdev);
3288 tasklet_enable(&jme->txclean_task);
3289 tasklet_enable(&jme->rxclean_task);
3290 tasklet_enable(&jme->rxempty_task);
3292 jme_powersave_phy(jme);
3298 jme_resume(struct device *dev)
3300 struct pci_dev *pdev = to_pci_dev(dev);
3301 struct net_device *netdev = pci_get_drvdata(pdev);
3302 struct jme_adapter *jme = netdev_priv(netdev);
3304 if (!netif_running(netdev))
3309 if (test_bit(JME_FLAG_SSET, &jme->flags))
3310 jme_set_settings(netdev, &jme->old_ecmd);
3312 jme_reset_phy_processor(jme);
3313 jme_phy_calibration(jme);
3316 netif_device_attach(netdev);
3318 atomic_inc(&jme->link_changing);
3320 jme_reset_link(jme);
3325 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3326 #define JME_PM_OPS (&jme_pm_ops)
3330 #define JME_PM_OPS NULL
3333 static const struct pci_device_id jme_pci_tbl[] = {
3334 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3335 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3339 static struct pci_driver jme_driver = {
3341 .id_table = jme_pci_tbl,
3342 .probe = jme_init_one,
3343 .remove = jme_remove_one,
3344 .shutdown = jme_shutdown,
3345 .driver.pm = JME_PM_OPS,
3349 jme_init_module(void)
3351 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3352 return pci_register_driver(&jme_driver);
3356 jme_cleanup_module(void)
3358 pci_unregister_driver(&jme_driver);
3361 module_init(jme_init_module);
3362 module_exit(jme_cleanup_module);
3364 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3365 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3366 MODULE_LICENSE("GPL");
3367 MODULE_VERSION(DRV_VERSION);
3368 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);