2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41 #include <linux/init.h>
42 #include <linux/dma-mapping.h>
45 #include <linux/tcp.h>
46 #include <linux/udp.h>
47 #include <linux/etherdevice.h>
48 #include <linux/delay.h>
49 #include <linux/ethtool.h>
50 #include <linux/platform_device.h>
51 #include <linux/module.h>
52 #include <linux/kernel.h>
53 #include <linux/spinlock.h>
54 #include <linux/workqueue.h>
55 #include <linux/phy.h>
56 #include <linux/mv643xx_eth.h>
58 #include <linux/interrupt.h>
59 #include <linux/types.h>
60 #include <linux/slab.h>
61 #include <linux/clk.h>
63 #include <linux/of_irq.h>
64 #include <linux/of_net.h>
65 #include <linux/of_mdio.h>
67 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
68 static char mv643xx_eth_driver_version[] = "1.4";
72 * Registers shared between all ports.
74 #define PHY_ADDR 0x0000
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
85 #define PORT_CONFIG 0x0000
86 #define UNICAST_PROMISCUOUS_MODE 0x00000001
87 #define PORT_CONFIG_EXT 0x0004
88 #define MAC_ADDR_LOW 0x0014
89 #define MAC_ADDR_HIGH 0x0018
90 #define SDMA_CONFIG 0x001c
91 #define TX_BURST_SIZE_16_64BIT 0x01000000
92 #define TX_BURST_SIZE_4_64BIT 0x00800000
93 #define BLM_TX_NO_SWAP 0x00000020
94 #define BLM_RX_NO_SWAP 0x00000010
95 #define RX_BURST_SIZE_16_64BIT 0x00000008
96 #define RX_BURST_SIZE_4_64BIT 0x00000004
97 #define PORT_SERIAL_CONTROL 0x003c
98 #define SET_MII_SPEED_TO_100 0x01000000
99 #define SET_GMII_SPEED_TO_1000 0x00800000
100 #define SET_FULL_DUPLEX_MODE 0x00200000
101 #define MAX_RX_PACKET_9700BYTE 0x000a0000
102 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
103 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
104 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
105 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
106 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
107 #define FORCE_LINK_PASS 0x00000002
108 #define SERIAL_PORT_ENABLE 0x00000001
109 #define PORT_STATUS 0x0044
110 #define TX_FIFO_EMPTY 0x00000400
111 #define TX_IN_PROGRESS 0x00000080
112 #define PORT_SPEED_MASK 0x00000030
113 #define PORT_SPEED_1000 0x00000010
114 #define PORT_SPEED_100 0x00000020
115 #define PORT_SPEED_10 0x00000000
116 #define FLOW_CONTROL_ENABLED 0x00000008
117 #define FULL_DUPLEX 0x00000004
118 #define LINK_UP 0x00000002
119 #define TXQ_COMMAND 0x0048
120 #define TXQ_FIX_PRIO_CONF 0x004c
121 #define PORT_SERIAL_CONTROL1 0x004c
122 #define CLK125_BYPASS_EN 0x00000010
123 #define TX_BW_RATE 0x0050
124 #define TX_BW_MTU 0x0058
125 #define TX_BW_BURST 0x005c
126 #define INT_CAUSE 0x0060
127 #define INT_TX_END 0x07f80000
128 #define INT_TX_END_0 0x00080000
129 #define INT_RX 0x000003fc
130 #define INT_RX_0 0x00000004
131 #define INT_EXT 0x00000002
132 #define INT_CAUSE_EXT 0x0064
133 #define INT_EXT_LINK_PHY 0x00110000
134 #define INT_EXT_TX 0x000000ff
135 #define INT_MASK 0x0068
136 #define INT_MASK_EXT 0x006c
137 #define TX_FIFO_URGENT_THRESHOLD 0x0074
138 #define RX_DISCARD_FRAME_CNT 0x0084
139 #define RX_OVERRUN_FRAME_CNT 0x0088
140 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
141 #define TX_BW_RATE_MOVED 0x00e0
142 #define TX_BW_MTU_MOVED 0x00e8
143 #define TX_BW_BURST_MOVED 0x00ec
144 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
145 #define RXQ_COMMAND 0x0280
146 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
147 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
148 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
149 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
152 * Misc per-port registers.
154 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
155 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
156 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
157 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
161 * SDMA configuration register default value.
163 #if defined(__BIG_ENDIAN)
164 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
165 (RX_BURST_SIZE_4_64BIT | \
166 TX_BURST_SIZE_4_64BIT)
167 #elif defined(__LITTLE_ENDIAN)
168 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
169 (RX_BURST_SIZE_4_64BIT | \
172 TX_BURST_SIZE_4_64BIT)
174 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
181 #define DEFAULT_RX_QUEUE_SIZE 128
182 #define DEFAULT_TX_QUEUE_SIZE 256
183 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
189 #if defined(__BIG_ENDIAN)
191 u16 byte_cnt; /* Descriptor buffer byte count */
192 u16 buf_size; /* Buffer size */
193 u32 cmd_sts; /* Descriptor command status */
194 u32 next_desc_ptr; /* Next descriptor pointer */
195 u32 buf_ptr; /* Descriptor buffer pointer */
199 u16 byte_cnt; /* buffer byte count */
200 u16 l4i_chk; /* CPU provided TCP checksum */
201 u32 cmd_sts; /* Command/status field */
202 u32 next_desc_ptr; /* Pointer to next descriptor */
203 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 #elif defined(__LITTLE_ENDIAN)
207 u32 cmd_sts; /* Descriptor command status */
208 u16 buf_size; /* Buffer size */
209 u16 byte_cnt; /* Descriptor buffer byte count */
210 u32 buf_ptr; /* Descriptor buffer pointer */
211 u32 next_desc_ptr; /* Next descriptor pointer */
215 u32 cmd_sts; /* Command/status field */
216 u16 l4i_chk; /* CPU provided TCP checksum */
217 u16 byte_cnt; /* buffer byte count */
218 u32 buf_ptr; /* pointer to buffer for this descriptor*/
219 u32 next_desc_ptr; /* Pointer to next descriptor */
222 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
225 /* RX & TX descriptor command */
226 #define BUFFER_OWNED_BY_DMA 0x80000000
228 /* RX & TX descriptor status */
229 #define ERROR_SUMMARY 0x00000001
231 /* RX descriptor status */
232 #define LAYER_4_CHECKSUM_OK 0x40000000
233 #define RX_ENABLE_INTERRUPT 0x20000000
234 #define RX_FIRST_DESC 0x08000000
235 #define RX_LAST_DESC 0x04000000
236 #define RX_IP_HDR_OK 0x02000000
237 #define RX_PKT_IS_IPV4 0x01000000
238 #define RX_PKT_IS_ETHERNETV2 0x00800000
239 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
240 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
241 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
243 /* TX descriptor command */
244 #define TX_ENABLE_INTERRUPT 0x00800000
245 #define GEN_CRC 0x00400000
246 #define TX_FIRST_DESC 0x00200000
247 #define TX_LAST_DESC 0x00100000
248 #define ZERO_PADDING 0x00080000
249 #define GEN_IP_V4_CHECKSUM 0x00040000
250 #define GEN_TCP_UDP_CHECKSUM 0x00020000
251 #define UDP_FRAME 0x00010000
252 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
253 #define GEN_TCP_UDP_CHK_FULL 0x00000400
254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
256 #define TX_IHL_SHIFT 11
259 /* global *******************************************************************/
260 struct mv643xx_eth_shared_private {
262 * Ethernet controller base address.
267 * Per-port MBUS window access register value.
272 * Hardware-specific parameters.
274 int extended_rx_coal_limit;
280 #define TX_BW_CONTROL_ABSENT 0
281 #define TX_BW_CONTROL_OLD_LAYOUT 1
282 #define TX_BW_CONTROL_NEW_LAYOUT 2
284 static int mv643xx_eth_open(struct net_device *dev);
285 static int mv643xx_eth_stop(struct net_device *dev);
288 /* per-port *****************************************************************/
289 struct mib_counters {
290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
310 u32 good_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
316 u32 mac_receive_error;
320 /* Non MIB hardware counters */
334 struct rx_desc *rx_desc_area;
335 dma_addr_t rx_desc_dma;
336 int rx_desc_area_size;
337 struct sk_buff **rx_skb;
349 struct tx_desc *tx_desc_area;
350 dma_addr_t tx_desc_dma;
351 int tx_desc_area_size;
353 struct sk_buff_head tx_skb;
355 unsigned long tx_packets;
356 unsigned long tx_bytes;
357 unsigned long tx_dropped;
360 struct mv643xx_eth_private {
361 struct mv643xx_eth_shared_private *shared;
365 struct net_device *dev;
367 struct phy_device *phy;
369 struct timer_list mib_counters_timer;
370 spinlock_t mib_counters_lock;
371 struct mib_counters mib_counters;
373 struct work_struct tx_timeout_task;
375 struct napi_struct napi;
390 unsigned long rx_desc_sram_addr;
391 int rx_desc_sram_size;
393 struct timer_list rx_oom;
394 struct rx_queue rxq[8];
400 unsigned long tx_desc_sram_addr;
401 int tx_desc_sram_size;
403 struct tx_queue txq[8];
406 * Hardware-specific parameters.
413 /* port register accessors **************************************************/
414 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
416 return readl(mp->shared->base + offset);
419 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
421 return readl(mp->base + offset);
424 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
426 writel(data, mp->shared->base + offset);
429 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
431 writel(data, mp->base + offset);
435 /* rxq/txq helper functions *************************************************/
436 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
438 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
441 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
443 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
446 static void rxq_enable(struct rx_queue *rxq)
448 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
449 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
452 static void rxq_disable(struct rx_queue *rxq)
454 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
455 u8 mask = 1 << rxq->index;
457 wrlp(mp, RXQ_COMMAND, mask << 8);
458 while (rdlp(mp, RXQ_COMMAND) & mask)
462 static void txq_reset_hw_ptr(struct tx_queue *txq)
464 struct mv643xx_eth_private *mp = txq_to_mp(txq);
467 addr = (u32)txq->tx_desc_dma;
468 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
469 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
472 static void txq_enable(struct tx_queue *txq)
474 struct mv643xx_eth_private *mp = txq_to_mp(txq);
475 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
478 static void txq_disable(struct tx_queue *txq)
480 struct mv643xx_eth_private *mp = txq_to_mp(txq);
481 u8 mask = 1 << txq->index;
483 wrlp(mp, TXQ_COMMAND, mask << 8);
484 while (rdlp(mp, TXQ_COMMAND) & mask)
488 static void txq_maybe_wake(struct tx_queue *txq)
490 struct mv643xx_eth_private *mp = txq_to_mp(txq);
491 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
493 if (netif_tx_queue_stopped(nq)) {
494 __netif_tx_lock(nq, smp_processor_id());
495 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
496 netif_tx_wake_queue(nq);
497 __netif_tx_unlock(nq);
501 static int rxq_process(struct rx_queue *rxq, int budget)
503 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
504 struct net_device_stats *stats = &mp->dev->stats;
508 while (rx < budget && rxq->rx_desc_count) {
509 struct rx_desc *rx_desc;
510 unsigned int cmd_sts;
514 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
516 cmd_sts = rx_desc->cmd_sts;
517 if (cmd_sts & BUFFER_OWNED_BY_DMA)
521 skb = rxq->rx_skb[rxq->rx_curr_desc];
522 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
525 if (rxq->rx_curr_desc == rxq->rx_ring_size)
526 rxq->rx_curr_desc = 0;
528 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
529 rx_desc->buf_size, DMA_FROM_DEVICE);
530 rxq->rx_desc_count--;
533 mp->work_rx_refill |= 1 << rxq->index;
535 byte_cnt = rx_desc->byte_cnt;
540 * Note that the descriptor byte count includes 2 dummy
541 * bytes automatically inserted by the hardware at the
542 * start of the packet (which we don't count), and a 4
543 * byte CRC at the end of the packet (which we do count).
546 stats->rx_bytes += byte_cnt - 2;
549 * In case we received a packet without first / last bits
550 * on, or the error summary bit is set, the packet needs
553 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
554 != (RX_FIRST_DESC | RX_LAST_DESC))
558 * The -4 is for the CRC in the trailer of the
561 skb_put(skb, byte_cnt - 2 - 4);
563 if (cmd_sts & LAYER_4_CHECKSUM_OK)
564 skb->ip_summed = CHECKSUM_UNNECESSARY;
565 skb->protocol = eth_type_trans(skb, mp->dev);
567 napi_gro_receive(&mp->napi, skb);
574 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
575 (RX_FIRST_DESC | RX_LAST_DESC)) {
578 "received packet spanning multiple descriptors\n");
581 if (cmd_sts & ERROR_SUMMARY)
588 mp->work_rx &= ~(1 << rxq->index);
593 static int rxq_refill(struct rx_queue *rxq, int budget)
595 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
599 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
602 struct rx_desc *rx_desc;
605 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
613 skb_reserve(skb, SKB_DMA_REALIGN);
616 rxq->rx_desc_count++;
618 rx = rxq->rx_used_desc++;
619 if (rxq->rx_used_desc == rxq->rx_ring_size)
620 rxq->rx_used_desc = 0;
622 rx_desc = rxq->rx_desc_area + rx;
624 size = skb_end_pointer(skb) - skb->data;
625 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
628 rx_desc->buf_size = size;
629 rxq->rx_skb[rx] = skb;
631 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
635 * The hardware automatically prepends 2 bytes of
636 * dummy data to each received packet, so that the
637 * IP header ends up 16-byte aligned.
642 if (refilled < budget)
643 mp->work_rx_refill &= ~(1 << rxq->index);
650 /* tx ***********************************************************************/
651 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
655 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
656 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
658 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
665 static inline __be16 sum16_as_be(__sum16 sum)
667 return (__force __be16)sum;
670 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
671 u16 *l4i_chk, u32 *command, int length)
676 if (skb->ip_summed == CHECKSUM_PARTIAL) {
680 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
681 skb->protocol != htons(ETH_P_8021Q));
683 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
684 tag_bytes = hdr_len - ETH_HLEN;
686 if (length - hdr_len > mp->shared->tx_csum_limit ||
687 unlikely(tag_bytes & ~12)) {
688 ret = skb_checksum_help(skb);
695 cmd |= MAC_HDR_EXTRA_4_BYTES;
697 cmd |= MAC_HDR_EXTRA_8_BYTES;
699 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
701 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
703 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
704 * it seems we don't need to pass the initial checksum. */
705 switch (ip_hdr(skb)->protocol) {
714 WARN(1, "protocol not supported");
718 /* Errata BTS #50, IHL must be 5 if no HW checksum */
719 cmd |= 5 << TX_IHL_SHIFT;
725 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
727 struct mv643xx_eth_private *mp = txq_to_mp(txq);
728 int nr_frags = skb_shinfo(skb)->nr_frags;
731 for (frag = 0; frag < nr_frags; frag++) {
732 skb_frag_t *this_frag;
734 struct tx_desc *desc;
736 this_frag = &skb_shinfo(skb)->frags[frag];
737 tx_index = txq->tx_curr_desc++;
738 if (txq->tx_curr_desc == txq->tx_ring_size)
739 txq->tx_curr_desc = 0;
740 desc = &txq->tx_desc_area[tx_index];
743 * The last fragment will generate an interrupt
744 * which will free the skb on TX completion.
746 if (frag == nr_frags - 1) {
747 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
748 ZERO_PADDING | TX_LAST_DESC |
751 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
755 desc->byte_cnt = skb_frag_size(this_frag);
756 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
758 skb_frag_size(this_frag),
763 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
765 struct mv643xx_eth_private *mp = txq_to_mp(txq);
766 int nr_frags = skb_shinfo(skb)->nr_frags;
768 struct tx_desc *desc;
776 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
778 dev_kfree_skb_any(skb);
781 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
783 tx_index = txq->tx_curr_desc++;
784 if (txq->tx_curr_desc == txq->tx_ring_size)
785 txq->tx_curr_desc = 0;
786 desc = &txq->tx_desc_area[tx_index];
789 txq_submit_frag_skb(txq, skb);
790 length = skb_headlen(skb);
792 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
796 desc->l4i_chk = l4i_chk;
797 desc->byte_cnt = length;
798 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
799 length, DMA_TO_DEVICE);
801 __skb_queue_tail(&txq->tx_skb, skb);
803 skb_tx_timestamp(skb);
805 /* ensure all other descriptors are written before first cmd_sts */
807 desc->cmd_sts = cmd_sts;
809 /* clear TX_END status */
810 mp->work_tx_end &= ~(1 << txq->index);
812 /* ensure all descriptors are written before poking hardware */
816 txq->tx_desc_count += nr_frags + 1;
821 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
823 struct mv643xx_eth_private *mp = netdev_priv(dev);
825 struct tx_queue *txq;
826 struct netdev_queue *nq;
828 queue = skb_get_queue_mapping(skb);
829 txq = mp->txq + queue;
830 nq = netdev_get_tx_queue(dev, queue);
832 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
834 netdev_printk(KERN_DEBUG, dev,
835 "failed to linearize skb with tiny unaligned fragment\n");
836 return NETDEV_TX_BUSY;
839 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
841 netdev_err(dev, "tx queue full?!\n");
842 dev_kfree_skb_any(skb);
848 if (!txq_submit_skb(txq, skb)) {
851 txq->tx_bytes += length;
854 entries_left = txq->tx_ring_size - txq->tx_desc_count;
855 if (entries_left < MAX_SKB_FRAGS + 1)
856 netif_tx_stop_queue(nq);
863 /* tx napi ******************************************************************/
864 static void txq_kick(struct tx_queue *txq)
866 struct mv643xx_eth_private *mp = txq_to_mp(txq);
867 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
871 __netif_tx_lock(nq, smp_processor_id());
873 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
876 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
877 expected_ptr = (u32)txq->tx_desc_dma +
878 txq->tx_curr_desc * sizeof(struct tx_desc);
880 if (hw_desc_ptr != expected_ptr)
884 __netif_tx_unlock(nq);
886 mp->work_tx_end &= ~(1 << txq->index);
889 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
891 struct mv643xx_eth_private *mp = txq_to_mp(txq);
892 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
895 __netif_tx_lock_bh(nq);
898 while (reclaimed < budget && txq->tx_desc_count > 0) {
900 struct tx_desc *desc;
904 tx_index = txq->tx_used_desc;
905 desc = &txq->tx_desc_area[tx_index];
906 cmd_sts = desc->cmd_sts;
908 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
911 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
914 txq->tx_used_desc = tx_index + 1;
915 if (txq->tx_used_desc == txq->tx_ring_size)
916 txq->tx_used_desc = 0;
919 txq->tx_desc_count--;
922 if (cmd_sts & TX_LAST_DESC)
923 skb = __skb_dequeue(&txq->tx_skb);
925 if (cmd_sts & ERROR_SUMMARY) {
926 netdev_info(mp->dev, "tx error\n");
927 mp->dev->stats.tx_errors++;
930 if (cmd_sts & TX_FIRST_DESC) {
931 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
932 desc->byte_cnt, DMA_TO_DEVICE);
934 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
935 desc->byte_cnt, DMA_TO_DEVICE);
941 __netif_tx_unlock_bh(nq);
943 if (reclaimed < budget)
944 mp->work_tx &= ~(1 << txq->index);
950 /* tx rate control **********************************************************/
952 * Set total maximum TX rate (shared by all TX queues for this port)
953 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
955 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
961 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
962 if (token_rate > 1023)
965 mtu = (mp->dev->mtu + 255) >> 8;
969 bucket_size = (burst + 255) >> 8;
970 if (bucket_size > 65535)
973 switch (mp->shared->tx_bw_control) {
974 case TX_BW_CONTROL_OLD_LAYOUT:
975 wrlp(mp, TX_BW_RATE, token_rate);
976 wrlp(mp, TX_BW_MTU, mtu);
977 wrlp(mp, TX_BW_BURST, bucket_size);
979 case TX_BW_CONTROL_NEW_LAYOUT:
980 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
981 wrlp(mp, TX_BW_MTU_MOVED, mtu);
982 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
987 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
989 struct mv643xx_eth_private *mp = txq_to_mp(txq);
993 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
994 if (token_rate > 1023)
997 bucket_size = (burst + 255) >> 8;
998 if (bucket_size > 65535)
1001 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1002 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1005 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1007 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1012 * Turn on fixed priority mode.
1015 switch (mp->shared->tx_bw_control) {
1016 case TX_BW_CONTROL_OLD_LAYOUT:
1017 off = TXQ_FIX_PRIO_CONF;
1019 case TX_BW_CONTROL_NEW_LAYOUT:
1020 off = TXQ_FIX_PRIO_CONF_MOVED;
1025 val = rdlp(mp, off);
1026 val |= 1 << txq->index;
1032 /* mii management interface *************************************************/
1033 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1035 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1036 u32 autoneg_disable = FORCE_LINK_PASS |
1037 DISABLE_AUTO_NEG_SPEED_GMII |
1038 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1039 DISABLE_AUTO_NEG_FOR_DUPLEX;
1041 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1042 /* enable auto negotiation */
1043 pscr &= ~autoneg_disable;
1047 pscr |= autoneg_disable;
1049 if (mp->phy->speed == SPEED_1000) {
1050 /* force gigabit, half duplex not supported */
1051 pscr |= SET_GMII_SPEED_TO_1000;
1052 pscr |= SET_FULL_DUPLEX_MODE;
1056 pscr &= ~SET_GMII_SPEED_TO_1000;
1058 if (mp->phy->speed == SPEED_100)
1059 pscr |= SET_MII_SPEED_TO_100;
1061 pscr &= ~SET_MII_SPEED_TO_100;
1063 if (mp->phy->duplex == DUPLEX_FULL)
1064 pscr |= SET_FULL_DUPLEX_MODE;
1066 pscr &= ~SET_FULL_DUPLEX_MODE;
1069 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1072 /* statistics ***************************************************************/
1073 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1075 struct mv643xx_eth_private *mp = netdev_priv(dev);
1076 struct net_device_stats *stats = &dev->stats;
1077 unsigned long tx_packets = 0;
1078 unsigned long tx_bytes = 0;
1079 unsigned long tx_dropped = 0;
1082 for (i = 0; i < mp->txq_count; i++) {
1083 struct tx_queue *txq = mp->txq + i;
1085 tx_packets += txq->tx_packets;
1086 tx_bytes += txq->tx_bytes;
1087 tx_dropped += txq->tx_dropped;
1090 stats->tx_packets = tx_packets;
1091 stats->tx_bytes = tx_bytes;
1092 stats->tx_dropped = tx_dropped;
1097 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1099 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1102 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1106 for (i = 0; i < 0x80; i += 4)
1109 /* Clear non MIB hw counters also */
1110 rdlp(mp, RX_DISCARD_FRAME_CNT);
1111 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1114 static void mib_counters_update(struct mv643xx_eth_private *mp)
1116 struct mib_counters *p = &mp->mib_counters;
1118 spin_lock_bh(&mp->mib_counters_lock);
1119 p->good_octets_received += mib_read(mp, 0x00);
1120 p->bad_octets_received += mib_read(mp, 0x08);
1121 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1122 p->good_frames_received += mib_read(mp, 0x10);
1123 p->bad_frames_received += mib_read(mp, 0x14);
1124 p->broadcast_frames_received += mib_read(mp, 0x18);
1125 p->multicast_frames_received += mib_read(mp, 0x1c);
1126 p->frames_64_octets += mib_read(mp, 0x20);
1127 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1128 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1129 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1130 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1131 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1132 p->good_octets_sent += mib_read(mp, 0x38);
1133 p->good_frames_sent += mib_read(mp, 0x40);
1134 p->excessive_collision += mib_read(mp, 0x44);
1135 p->multicast_frames_sent += mib_read(mp, 0x48);
1136 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1137 p->unrec_mac_control_received += mib_read(mp, 0x50);
1138 p->fc_sent += mib_read(mp, 0x54);
1139 p->good_fc_received += mib_read(mp, 0x58);
1140 p->bad_fc_received += mib_read(mp, 0x5c);
1141 p->undersize_received += mib_read(mp, 0x60);
1142 p->fragments_received += mib_read(mp, 0x64);
1143 p->oversize_received += mib_read(mp, 0x68);
1144 p->jabber_received += mib_read(mp, 0x6c);
1145 p->mac_receive_error += mib_read(mp, 0x70);
1146 p->bad_crc_event += mib_read(mp, 0x74);
1147 p->collision += mib_read(mp, 0x78);
1148 p->late_collision += mib_read(mp, 0x7c);
1149 /* Non MIB hardware counters */
1150 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1151 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1152 spin_unlock_bh(&mp->mib_counters_lock);
1155 static void mib_counters_timer_wrapper(unsigned long _mp)
1157 struct mv643xx_eth_private *mp = (void *)_mp;
1158 mib_counters_update(mp);
1159 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1163 /* interrupt coalescing *****************************************************/
1165 * Hardware coalescing parameters are set in units of 64 t_clk
1168 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1170 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1172 * In the ->set*() methods, we round the computed register value
1173 * to the nearest integer.
1175 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1177 u32 val = rdlp(mp, SDMA_CONFIG);
1180 if (mp->shared->extended_rx_coal_limit)
1181 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1183 temp = (val & 0x003fff00) >> 8;
1186 do_div(temp, mp->t_clk);
1188 return (unsigned int)temp;
1191 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1196 temp = (u64)usec * mp->t_clk;
1198 do_div(temp, 64000000);
1200 val = rdlp(mp, SDMA_CONFIG);
1201 if (mp->shared->extended_rx_coal_limit) {
1205 val |= (temp & 0x8000) << 10;
1206 val |= (temp & 0x7fff) << 7;
1211 val |= (temp & 0x3fff) << 8;
1213 wrlp(mp, SDMA_CONFIG, val);
1216 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1220 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1222 do_div(temp, mp->t_clk);
1224 return (unsigned int)temp;
1227 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1231 temp = (u64)usec * mp->t_clk;
1233 do_div(temp, 64000000);
1238 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1242 /* ethtool ******************************************************************/
1243 struct mv643xx_eth_stats {
1244 char stat_string[ETH_GSTRING_LEN];
1251 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1252 offsetof(struct net_device, stats.m), -1 }
1254 #define MIBSTAT(m) \
1255 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1256 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1258 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1267 MIBSTAT(good_octets_received),
1268 MIBSTAT(bad_octets_received),
1269 MIBSTAT(internal_mac_transmit_err),
1270 MIBSTAT(good_frames_received),
1271 MIBSTAT(bad_frames_received),
1272 MIBSTAT(broadcast_frames_received),
1273 MIBSTAT(multicast_frames_received),
1274 MIBSTAT(frames_64_octets),
1275 MIBSTAT(frames_65_to_127_octets),
1276 MIBSTAT(frames_128_to_255_octets),
1277 MIBSTAT(frames_256_to_511_octets),
1278 MIBSTAT(frames_512_to_1023_octets),
1279 MIBSTAT(frames_1024_to_max_octets),
1280 MIBSTAT(good_octets_sent),
1281 MIBSTAT(good_frames_sent),
1282 MIBSTAT(excessive_collision),
1283 MIBSTAT(multicast_frames_sent),
1284 MIBSTAT(broadcast_frames_sent),
1285 MIBSTAT(unrec_mac_control_received),
1287 MIBSTAT(good_fc_received),
1288 MIBSTAT(bad_fc_received),
1289 MIBSTAT(undersize_received),
1290 MIBSTAT(fragments_received),
1291 MIBSTAT(oversize_received),
1292 MIBSTAT(jabber_received),
1293 MIBSTAT(mac_receive_error),
1294 MIBSTAT(bad_crc_event),
1296 MIBSTAT(late_collision),
1297 MIBSTAT(rx_discard),
1298 MIBSTAT(rx_overrun),
1302 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1303 struct ethtool_cmd *cmd)
1307 err = phy_read_status(mp->phy);
1309 err = phy_ethtool_gset(mp->phy, cmd);
1312 * The MAC does not support 1000baseT_Half.
1314 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1315 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1321 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1322 struct ethtool_cmd *cmd)
1326 port_status = rdlp(mp, PORT_STATUS);
1328 cmd->supported = SUPPORTED_MII;
1329 cmd->advertising = ADVERTISED_MII;
1330 switch (port_status & PORT_SPEED_MASK) {
1332 ethtool_cmd_speed_set(cmd, SPEED_10);
1334 case PORT_SPEED_100:
1335 ethtool_cmd_speed_set(cmd, SPEED_100);
1337 case PORT_SPEED_1000:
1338 ethtool_cmd_speed_set(cmd, SPEED_1000);
1344 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1345 cmd->port = PORT_MII;
1346 cmd->phy_address = 0;
1347 cmd->transceiver = XCVR_INTERNAL;
1348 cmd->autoneg = AUTONEG_DISABLE;
1356 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1358 struct mv643xx_eth_private *mp = netdev_priv(dev);
1362 phy_ethtool_get_wol(mp->phy, wol);
1366 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1368 struct mv643xx_eth_private *mp = netdev_priv(dev);
1371 if (mp->phy == NULL)
1374 err = phy_ethtool_set_wol(mp->phy, wol);
1375 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1376 * this debugging hint is useful to have.
1378 if (err == -EOPNOTSUPP)
1379 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1384 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1386 struct mv643xx_eth_private *mp = netdev_priv(dev);
1388 if (mp->phy != NULL)
1389 return mv643xx_eth_get_settings_phy(mp, cmd);
1391 return mv643xx_eth_get_settings_phyless(mp, cmd);
1395 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1397 struct mv643xx_eth_private *mp = netdev_priv(dev);
1400 if (mp->phy == NULL)
1404 * The MAC does not support 1000baseT_Half.
1406 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1408 ret = phy_ethtool_sset(mp->phy, cmd);
1410 mv643xx_adjust_pscr(mp);
1414 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1415 struct ethtool_drvinfo *drvinfo)
1417 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1418 sizeof(drvinfo->driver));
1419 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1420 sizeof(drvinfo->version));
1421 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1422 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1423 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1426 static int mv643xx_eth_nway_reset(struct net_device *dev)
1428 struct mv643xx_eth_private *mp = netdev_priv(dev);
1430 if (mp->phy == NULL)
1433 return genphy_restart_aneg(mp->phy);
1437 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1439 struct mv643xx_eth_private *mp = netdev_priv(dev);
1441 ec->rx_coalesce_usecs = get_rx_coal(mp);
1442 ec->tx_coalesce_usecs = get_tx_coal(mp);
1448 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1450 struct mv643xx_eth_private *mp = netdev_priv(dev);
1452 set_rx_coal(mp, ec->rx_coalesce_usecs);
1453 set_tx_coal(mp, ec->tx_coalesce_usecs);
1459 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1461 struct mv643xx_eth_private *mp = netdev_priv(dev);
1463 er->rx_max_pending = 4096;
1464 er->tx_max_pending = 4096;
1466 er->rx_pending = mp->rx_ring_size;
1467 er->tx_pending = mp->tx_ring_size;
1471 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1473 struct mv643xx_eth_private *mp = netdev_priv(dev);
1475 if (er->rx_mini_pending || er->rx_jumbo_pending)
1478 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1479 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1481 if (netif_running(dev)) {
1482 mv643xx_eth_stop(dev);
1483 if (mv643xx_eth_open(dev)) {
1485 "fatal error on re-opening device after ring param change\n");
1495 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1497 struct mv643xx_eth_private *mp = netdev_priv(dev);
1498 bool rx_csum = features & NETIF_F_RXCSUM;
1500 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1505 static void mv643xx_eth_get_strings(struct net_device *dev,
1506 uint32_t stringset, uint8_t *data)
1510 if (stringset == ETH_SS_STATS) {
1511 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1512 memcpy(data + i * ETH_GSTRING_LEN,
1513 mv643xx_eth_stats[i].stat_string,
1519 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1520 struct ethtool_stats *stats,
1523 struct mv643xx_eth_private *mp = netdev_priv(dev);
1526 mv643xx_eth_get_stats(dev);
1527 mib_counters_update(mp);
1529 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1530 const struct mv643xx_eth_stats *stat;
1533 stat = mv643xx_eth_stats + i;
1535 if (stat->netdev_off >= 0)
1536 p = ((void *)mp->dev) + stat->netdev_off;
1538 p = ((void *)mp) + stat->mp_off;
1540 data[i] = (stat->sizeof_stat == 8) ?
1541 *(uint64_t *)p : *(uint32_t *)p;
1545 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1547 if (sset == ETH_SS_STATS)
1548 return ARRAY_SIZE(mv643xx_eth_stats);
1553 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1554 .get_settings = mv643xx_eth_get_settings,
1555 .set_settings = mv643xx_eth_set_settings,
1556 .get_drvinfo = mv643xx_eth_get_drvinfo,
1557 .nway_reset = mv643xx_eth_nway_reset,
1558 .get_link = ethtool_op_get_link,
1559 .get_coalesce = mv643xx_eth_get_coalesce,
1560 .set_coalesce = mv643xx_eth_set_coalesce,
1561 .get_ringparam = mv643xx_eth_get_ringparam,
1562 .set_ringparam = mv643xx_eth_set_ringparam,
1563 .get_strings = mv643xx_eth_get_strings,
1564 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1565 .get_sset_count = mv643xx_eth_get_sset_count,
1566 .get_ts_info = ethtool_op_get_ts_info,
1567 .get_wol = mv643xx_eth_get_wol,
1568 .set_wol = mv643xx_eth_set_wol,
1572 /* address handling *********************************************************/
1573 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1575 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1576 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1578 addr[0] = (mac_h >> 24) & 0xff;
1579 addr[1] = (mac_h >> 16) & 0xff;
1580 addr[2] = (mac_h >> 8) & 0xff;
1581 addr[3] = mac_h & 0xff;
1582 addr[4] = (mac_l >> 8) & 0xff;
1583 addr[5] = mac_l & 0xff;
1586 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1588 wrlp(mp, MAC_ADDR_HIGH,
1589 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1590 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1593 static u32 uc_addr_filter_mask(struct net_device *dev)
1595 struct netdev_hw_addr *ha;
1598 if (dev->flags & IFF_PROMISC)
1601 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1602 netdev_for_each_uc_addr(ha, dev) {
1603 if (memcmp(dev->dev_addr, ha->addr, 5))
1605 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1608 nibbles |= 1 << (ha->addr[5] & 0x0f);
1614 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1616 struct mv643xx_eth_private *mp = netdev_priv(dev);
1621 uc_addr_set(mp, dev->dev_addr);
1623 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1625 nibbles = uc_addr_filter_mask(dev);
1627 port_config |= UNICAST_PROMISCUOUS_MODE;
1631 for (i = 0; i < 16; i += 4) {
1632 int off = UNICAST_TABLE(mp->port_num) + i;
1649 wrlp(mp, PORT_CONFIG, port_config);
1652 static int addr_crc(unsigned char *addr)
1657 for (i = 0; i < 6; i++) {
1660 crc = (crc ^ addr[i]) << 8;
1661 for (j = 7; j >= 0; j--) {
1662 if (crc & (0x100 << j))
1670 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1672 struct mv643xx_eth_private *mp = netdev_priv(dev);
1675 struct netdev_hw_addr *ha;
1678 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1683 port_num = mp->port_num;
1684 accept = 0x01010101;
1685 for (i = 0; i < 0x100; i += 4) {
1686 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1687 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1692 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1693 if (mc_spec == NULL)
1695 mc_other = mc_spec + (0x100 >> 2);
1697 memset(mc_spec, 0, 0x100);
1698 memset(mc_other, 0, 0x100);
1700 netdev_for_each_mc_addr(ha, dev) {
1705 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1710 entry = addr_crc(a);
1713 table[entry >> 2] |= 1 << (8 * (entry & 3));
1716 for (i = 0; i < 0x100; i += 4) {
1717 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1718 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1724 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1726 mv643xx_eth_program_unicast_filter(dev);
1727 mv643xx_eth_program_multicast_filter(dev);
1730 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1732 struct sockaddr *sa = addr;
1734 if (!is_valid_ether_addr(sa->sa_data))
1735 return -EADDRNOTAVAIL;
1737 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1739 netif_addr_lock_bh(dev);
1740 mv643xx_eth_program_unicast_filter(dev);
1741 netif_addr_unlock_bh(dev);
1747 /* rx/tx queue initialisation ***********************************************/
1748 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1750 struct rx_queue *rxq = mp->rxq + index;
1751 struct rx_desc *rx_desc;
1757 rxq->rx_ring_size = mp->rx_ring_size;
1759 rxq->rx_desc_count = 0;
1760 rxq->rx_curr_desc = 0;
1761 rxq->rx_used_desc = 0;
1763 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1765 if (index == 0 && size <= mp->rx_desc_sram_size) {
1766 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1767 mp->rx_desc_sram_size);
1768 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1770 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1771 size, &rxq->rx_desc_dma,
1775 if (rxq->rx_desc_area == NULL) {
1777 "can't allocate rx ring (%d bytes)\n", size);
1780 memset(rxq->rx_desc_area, 0, size);
1782 rxq->rx_desc_area_size = size;
1783 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1785 if (rxq->rx_skb == NULL)
1788 rx_desc = rxq->rx_desc_area;
1789 for (i = 0; i < rxq->rx_ring_size; i++) {
1793 if (nexti == rxq->rx_ring_size)
1796 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1797 nexti * sizeof(struct rx_desc);
1804 if (index == 0 && size <= mp->rx_desc_sram_size)
1805 iounmap(rxq->rx_desc_area);
1807 dma_free_coherent(mp->dev->dev.parent, size,
1815 static void rxq_deinit(struct rx_queue *rxq)
1817 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1822 for (i = 0; i < rxq->rx_ring_size; i++) {
1823 if (rxq->rx_skb[i]) {
1824 dev_kfree_skb(rxq->rx_skb[i]);
1825 rxq->rx_desc_count--;
1829 if (rxq->rx_desc_count) {
1830 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1831 rxq->rx_desc_count);
1834 if (rxq->index == 0 &&
1835 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1836 iounmap(rxq->rx_desc_area);
1838 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1839 rxq->rx_desc_area, rxq->rx_desc_dma);
1844 static int txq_init(struct mv643xx_eth_private *mp, int index)
1846 struct tx_queue *txq = mp->txq + index;
1847 struct tx_desc *tx_desc;
1853 txq->tx_ring_size = mp->tx_ring_size;
1855 txq->tx_desc_count = 0;
1856 txq->tx_curr_desc = 0;
1857 txq->tx_used_desc = 0;
1859 size = txq->tx_ring_size * sizeof(struct tx_desc);
1861 if (index == 0 && size <= mp->tx_desc_sram_size) {
1862 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1863 mp->tx_desc_sram_size);
1864 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1866 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1867 size, &txq->tx_desc_dma,
1871 if (txq->tx_desc_area == NULL) {
1873 "can't allocate tx ring (%d bytes)\n", size);
1876 memset(txq->tx_desc_area, 0, size);
1878 txq->tx_desc_area_size = size;
1880 tx_desc = txq->tx_desc_area;
1881 for (i = 0; i < txq->tx_ring_size; i++) {
1882 struct tx_desc *txd = tx_desc + i;
1886 if (nexti == txq->tx_ring_size)
1890 txd->next_desc_ptr = txq->tx_desc_dma +
1891 nexti * sizeof(struct tx_desc);
1894 skb_queue_head_init(&txq->tx_skb);
1899 static void txq_deinit(struct tx_queue *txq)
1901 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1904 txq_reclaim(txq, txq->tx_ring_size, 1);
1906 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1908 if (txq->index == 0 &&
1909 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1910 iounmap(txq->tx_desc_area);
1912 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
1913 txq->tx_desc_area, txq->tx_desc_dma);
1917 /* netdev ops and related ***************************************************/
1918 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1923 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1928 if (int_cause & INT_EXT) {
1929 int_cause &= ~INT_EXT;
1930 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1934 wrlp(mp, INT_CAUSE, ~int_cause);
1935 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1936 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1937 mp->work_rx |= (int_cause & INT_RX) >> 2;
1940 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1941 if (int_cause_ext) {
1942 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1943 if (int_cause_ext & INT_EXT_LINK_PHY)
1945 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1951 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1953 struct net_device *dev = (struct net_device *)dev_id;
1954 struct mv643xx_eth_private *mp = netdev_priv(dev);
1956 if (unlikely(!mv643xx_eth_collect_events(mp)))
1959 wrlp(mp, INT_MASK, 0);
1960 napi_schedule(&mp->napi);
1965 static void handle_link_event(struct mv643xx_eth_private *mp)
1967 struct net_device *dev = mp->dev;
1973 port_status = rdlp(mp, PORT_STATUS);
1974 if (!(port_status & LINK_UP)) {
1975 if (netif_carrier_ok(dev)) {
1978 netdev_info(dev, "link down\n");
1980 netif_carrier_off(dev);
1982 for (i = 0; i < mp->txq_count; i++) {
1983 struct tx_queue *txq = mp->txq + i;
1985 txq_reclaim(txq, txq->tx_ring_size, 1);
1986 txq_reset_hw_ptr(txq);
1992 switch (port_status & PORT_SPEED_MASK) {
1996 case PORT_SPEED_100:
1999 case PORT_SPEED_1000:
2006 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2007 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2009 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2010 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2012 if (!netif_carrier_ok(dev))
2013 netif_carrier_on(dev);
2016 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2018 struct mv643xx_eth_private *mp;
2021 mp = container_of(napi, struct mv643xx_eth_private, napi);
2023 if (unlikely(mp->oom)) {
2025 del_timer(&mp->rx_oom);
2029 while (work_done < budget) {
2034 if (mp->work_link) {
2036 handle_link_event(mp);
2041 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2042 if (likely(!mp->oom))
2043 queue_mask |= mp->work_rx_refill;
2046 if (mv643xx_eth_collect_events(mp))
2051 queue = fls(queue_mask) - 1;
2052 queue_mask = 1 << queue;
2054 work_tbd = budget - work_done;
2058 if (mp->work_tx_end & queue_mask) {
2059 txq_kick(mp->txq + queue);
2060 } else if (mp->work_tx & queue_mask) {
2061 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2062 txq_maybe_wake(mp->txq + queue);
2063 } else if (mp->work_rx & queue_mask) {
2064 work_done += rxq_process(mp->rxq + queue, work_tbd);
2065 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2066 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2072 if (work_done < budget) {
2074 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2075 napi_complete(napi);
2076 wrlp(mp, INT_MASK, mp->int_mask);
2082 static inline void oom_timer_wrapper(unsigned long data)
2084 struct mv643xx_eth_private *mp = (void *)data;
2086 napi_schedule(&mp->napi);
2089 static void port_start(struct mv643xx_eth_private *mp)
2095 * Perform PHY reset, if there is a PHY.
2097 if (mp->phy != NULL) {
2098 struct ethtool_cmd cmd;
2100 mv643xx_eth_get_settings(mp->dev, &cmd);
2101 phy_init_hw(mp->phy);
2102 mv643xx_eth_set_settings(mp->dev, &cmd);
2107 * Configure basic link parameters.
2109 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2111 pscr |= SERIAL_PORT_ENABLE;
2112 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2114 pscr |= DO_NOT_FORCE_LINK_FAIL;
2115 if (mp->phy == NULL)
2116 pscr |= FORCE_LINK_PASS;
2117 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2120 * Configure TX path and queues.
2122 tx_set_rate(mp, 1000000000, 16777216);
2123 for (i = 0; i < mp->txq_count; i++) {
2124 struct tx_queue *txq = mp->txq + i;
2126 txq_reset_hw_ptr(txq);
2127 txq_set_rate(txq, 1000000000, 16777216);
2128 txq_set_fixed_prio_mode(txq);
2132 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2133 * frames to RX queue #0, and include the pseudo-header when
2134 * calculating receive checksums.
2136 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2139 * Treat BPDUs as normal multicasts, and disable partition mode.
2141 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2144 * Add configured unicast addresses to address filter table.
2146 mv643xx_eth_program_unicast_filter(mp->dev);
2149 * Enable the receive queues.
2151 for (i = 0; i < mp->rxq_count; i++) {
2152 struct rx_queue *rxq = mp->rxq + i;
2155 addr = (u32)rxq->rx_desc_dma;
2156 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2157 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2163 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2168 * Reserve 2+14 bytes for an ethernet header (the hardware
2169 * automatically prepends 2 bytes of dummy data to each
2170 * received packet), 16 bytes for up to four VLAN tags, and
2171 * 4 bytes for the trailing FCS -- 36 bytes total.
2173 skb_size = mp->dev->mtu + 36;
2176 * Make sure that the skb size is a multiple of 8 bytes, as
2177 * the lower three bits of the receive descriptor's buffer
2178 * size field are ignored by the hardware.
2180 mp->skb_size = (skb_size + 7) & ~7;
2183 * If NET_SKB_PAD is smaller than a cache line,
2184 * netdev_alloc_skb() will cause skb->data to be misaligned
2185 * to a cache line boundary. If this is the case, include
2186 * some extra space to allow re-aligning the data area.
2188 mp->skb_size += SKB_DMA_REALIGN;
2191 static int mv643xx_eth_open(struct net_device *dev)
2193 struct mv643xx_eth_private *mp = netdev_priv(dev);
2197 wrlp(mp, INT_CAUSE, 0);
2198 wrlp(mp, INT_CAUSE_EXT, 0);
2199 rdlp(mp, INT_CAUSE_EXT);
2201 err = request_irq(dev->irq, mv643xx_eth_irq,
2202 IRQF_SHARED, dev->name, dev);
2204 netdev_err(dev, "can't assign irq\n");
2208 mv643xx_eth_recalc_skb_size(mp);
2210 napi_enable(&mp->napi);
2212 mp->int_mask = INT_EXT;
2214 for (i = 0; i < mp->rxq_count; i++) {
2215 err = rxq_init(mp, i);
2218 rxq_deinit(mp->rxq + i);
2222 rxq_refill(mp->rxq + i, INT_MAX);
2223 mp->int_mask |= INT_RX_0 << i;
2227 mp->rx_oom.expires = jiffies + (HZ / 10);
2228 add_timer(&mp->rx_oom);
2231 for (i = 0; i < mp->txq_count; i++) {
2232 err = txq_init(mp, i);
2235 txq_deinit(mp->txq + i);
2238 mp->int_mask |= INT_TX_END_0 << i;
2241 add_timer(&mp->mib_counters_timer);
2244 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2245 wrlp(mp, INT_MASK, mp->int_mask);
2251 for (i = 0; i < mp->rxq_count; i++)
2252 rxq_deinit(mp->rxq + i);
2254 free_irq(dev->irq, dev);
2259 static void port_reset(struct mv643xx_eth_private *mp)
2264 for (i = 0; i < mp->rxq_count; i++)
2265 rxq_disable(mp->rxq + i);
2266 for (i = 0; i < mp->txq_count; i++)
2267 txq_disable(mp->txq + i);
2270 u32 ps = rdlp(mp, PORT_STATUS);
2272 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2277 /* Reset the Enable bit in the Configuration Register */
2278 data = rdlp(mp, PORT_SERIAL_CONTROL);
2279 data &= ~(SERIAL_PORT_ENABLE |
2280 DO_NOT_FORCE_LINK_FAIL |
2282 wrlp(mp, PORT_SERIAL_CONTROL, data);
2285 static int mv643xx_eth_stop(struct net_device *dev)
2287 struct mv643xx_eth_private *mp = netdev_priv(dev);
2290 wrlp(mp, INT_MASK_EXT, 0x00000000);
2291 wrlp(mp, INT_MASK, 0x00000000);
2294 napi_disable(&mp->napi);
2296 del_timer_sync(&mp->rx_oom);
2298 netif_carrier_off(dev);
2301 free_irq(dev->irq, dev);
2304 mv643xx_eth_get_stats(dev);
2305 mib_counters_update(mp);
2306 del_timer_sync(&mp->mib_counters_timer);
2308 for (i = 0; i < mp->rxq_count; i++)
2309 rxq_deinit(mp->rxq + i);
2310 for (i = 0; i < mp->txq_count; i++)
2311 txq_deinit(mp->txq + i);
2316 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2318 struct mv643xx_eth_private *mp = netdev_priv(dev);
2321 if (mp->phy == NULL)
2324 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2326 mv643xx_adjust_pscr(mp);
2330 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2332 struct mv643xx_eth_private *mp = netdev_priv(dev);
2334 if (new_mtu < 64 || new_mtu > 9500)
2338 mv643xx_eth_recalc_skb_size(mp);
2339 tx_set_rate(mp, 1000000000, 16777216);
2341 if (!netif_running(dev))
2345 * Stop and then re-open the interface. This will allocate RX
2346 * skbs of the new MTU.
2347 * There is a possible danger that the open will not succeed,
2348 * due to memory being full.
2350 mv643xx_eth_stop(dev);
2351 if (mv643xx_eth_open(dev)) {
2353 "fatal error on re-opening device after MTU change\n");
2359 static void tx_timeout_task(struct work_struct *ugly)
2361 struct mv643xx_eth_private *mp;
2363 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2364 if (netif_running(mp->dev)) {
2365 netif_tx_stop_all_queues(mp->dev);
2368 netif_tx_wake_all_queues(mp->dev);
2372 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2374 struct mv643xx_eth_private *mp = netdev_priv(dev);
2376 netdev_info(dev, "tx timeout\n");
2378 schedule_work(&mp->tx_timeout_task);
2381 #ifdef CONFIG_NET_POLL_CONTROLLER
2382 static void mv643xx_eth_netpoll(struct net_device *dev)
2384 struct mv643xx_eth_private *mp = netdev_priv(dev);
2386 wrlp(mp, INT_MASK, 0x00000000);
2389 mv643xx_eth_irq(dev->irq, dev);
2391 wrlp(mp, INT_MASK, mp->int_mask);
2396 /* platform glue ************************************************************/
2398 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2399 const struct mbus_dram_target_info *dram)
2401 void __iomem *base = msp->base;
2406 for (i = 0; i < 6; i++) {
2407 writel(0, base + WINDOW_BASE(i));
2408 writel(0, base + WINDOW_SIZE(i));
2410 writel(0, base + WINDOW_REMAP_HIGH(i));
2416 for (i = 0; i < dram->num_cs; i++) {
2417 const struct mbus_dram_window *cs = dram->cs + i;
2419 writel((cs->base & 0xffff0000) |
2420 (cs->mbus_attr << 8) |
2421 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2422 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2424 win_enable &= ~(1 << i);
2425 win_protect |= 3 << (2 * i);
2428 writel(win_enable, base + WINDOW_BAR_ENABLE);
2429 msp->win_protect = win_protect;
2432 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2435 * Check whether we have a 14-bit coal limit field in bits
2436 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2437 * SDMA config register.
2439 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2440 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2441 msp->extended_rx_coal_limit = 1;
2443 msp->extended_rx_coal_limit = 0;
2446 * Check whether the MAC supports TX rate control, and if
2447 * yes, whether its associated registers are in the old or
2450 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2451 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2452 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2454 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2455 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2456 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2458 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2462 #if defined(CONFIG_OF)
2463 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2464 { .compatible = "marvell,orion-eth", },
2465 { .compatible = "marvell,kirkwood-eth", },
2468 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2471 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2472 #define mv643xx_eth_property(_np, _name, _v) \
2475 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2479 static struct platform_device *port_platdev[3];
2481 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2482 struct device_node *pnp)
2484 struct platform_device *ppdev;
2485 struct mv643xx_eth_platform_data ppd;
2486 struct resource res;
2487 const char *mac_addr;
2491 memset(&ppd, 0, sizeof(ppd));
2494 memset(&res, 0, sizeof(res));
2495 if (!of_irq_to_resource(pnp, 0, &res)) {
2496 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2500 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2501 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2505 if (ppd.port_number >= 3) {
2506 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2510 while (dev_num < 3 && port_platdev[dev_num])
2514 dev_err(&pdev->dev, "too many ports registered\n");
2518 mac_addr = of_get_mac_address(pnp);
2520 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2522 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2523 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2524 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2525 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2526 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2527 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2529 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2530 if (!ppd.phy_node) {
2531 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2532 of_property_read_u32(pnp, "speed", &ppd.speed);
2533 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2536 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2539 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2540 ppdev->dev.of_node = pnp;
2542 ret = platform_device_add_resources(ppdev, &res, 1);
2546 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2550 ret = platform_device_add(ppdev);
2554 port_platdev[dev_num] = ppdev;
2559 platform_device_put(ppdev);
2563 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2565 struct mv643xx_eth_shared_platform_data *pd;
2566 struct device_node *pnp, *np = pdev->dev.of_node;
2569 /* bail out if not registered from DT */
2573 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2576 pdev->dev.platform_data = pd;
2578 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2580 for_each_available_child_of_node(np, pnp) {
2581 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2588 static void mv643xx_eth_shared_of_remove(void)
2592 for (n = 0; n < 3; n++) {
2593 platform_device_del(port_platdev[n]);
2594 port_platdev[n] = NULL;
2598 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2603 static inline void mv643xx_eth_shared_of_remove(void)
2608 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2610 static int mv643xx_eth_version_printed;
2611 struct mv643xx_eth_shared_platform_data *pd;
2612 struct mv643xx_eth_shared_private *msp;
2613 const struct mbus_dram_target_info *dram;
2614 struct resource *res;
2617 if (!mv643xx_eth_version_printed++)
2618 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2619 mv643xx_eth_driver_version);
2621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2625 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2628 platform_set_drvdata(pdev, msp);
2630 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2631 if (msp->base == NULL)
2634 msp->clk = devm_clk_get(&pdev->dev, NULL);
2635 if (!IS_ERR(msp->clk))
2636 clk_prepare_enable(msp->clk);
2639 * (Re-)program MBUS remapping windows if we are asked to.
2641 dram = mv_mbus_dram_info();
2643 mv643xx_eth_conf_mbus_windows(msp, dram);
2645 ret = mv643xx_eth_shared_of_probe(pdev);
2648 pd = dev_get_platdata(&pdev->dev);
2650 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2651 pd->tx_csum_limit : 9 * 1024;
2652 infer_hw_params(msp);
2657 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2659 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2661 mv643xx_eth_shared_of_remove();
2662 if (!IS_ERR(msp->clk))
2663 clk_disable_unprepare(msp->clk);
2667 static struct platform_driver mv643xx_eth_shared_driver = {
2668 .probe = mv643xx_eth_shared_probe,
2669 .remove = mv643xx_eth_shared_remove,
2671 .name = MV643XX_ETH_SHARED_NAME,
2672 .owner = THIS_MODULE,
2673 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2677 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2679 int addr_shift = 5 * mp->port_num;
2682 data = rdl(mp, PHY_ADDR);
2683 data &= ~(0x1f << addr_shift);
2684 data |= (phy_addr & 0x1f) << addr_shift;
2685 wrl(mp, PHY_ADDR, data);
2688 static int phy_addr_get(struct mv643xx_eth_private *mp)
2692 data = rdl(mp, PHY_ADDR);
2694 return (data >> (5 * mp->port_num)) & 0x1f;
2697 static void set_params(struct mv643xx_eth_private *mp,
2698 struct mv643xx_eth_platform_data *pd)
2700 struct net_device *dev = mp->dev;
2702 if (is_valid_ether_addr(pd->mac_addr))
2703 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2705 uc_addr_get(mp, dev->dev_addr);
2707 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2708 if (pd->rx_queue_size)
2709 mp->rx_ring_size = pd->rx_queue_size;
2710 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2711 mp->rx_desc_sram_size = pd->rx_sram_size;
2713 mp->rxq_count = pd->rx_queue_count ? : 1;
2715 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2716 if (pd->tx_queue_size)
2717 mp->tx_ring_size = pd->tx_queue_size;
2718 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2719 mp->tx_desc_sram_size = pd->tx_sram_size;
2721 mp->txq_count = pd->tx_queue_count ? : 1;
2724 static void mv643xx_eth_adjust_link(struct net_device *dev)
2726 struct mv643xx_eth_private *mp = netdev_priv(dev);
2728 mv643xx_adjust_pscr(mp);
2731 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2734 struct phy_device *phydev;
2738 char phy_id[MII_BUS_ID_SIZE + 3];
2740 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2741 start = phy_addr_get(mp) & 0x1f;
2744 start = phy_addr & 0x1f;
2748 /* Attempt to connect to the PHY using orion-mdio */
2749 phydev = ERR_PTR(-ENODEV);
2750 for (i = 0; i < num; i++) {
2751 int addr = (start + i) & 0x1f;
2753 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2754 "orion-mdio-mii", addr);
2756 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2757 PHY_INTERFACE_MODE_GMII);
2758 if (!IS_ERR(phydev)) {
2759 phy_addr_set(mp, addr);
2767 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2769 struct phy_device *phy = mp->phy;
2772 phy->autoneg = AUTONEG_ENABLE;
2775 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2777 phy->autoneg = AUTONEG_DISABLE;
2778 phy->advertising = 0;
2780 phy->duplex = duplex;
2782 phy_start_aneg(phy);
2785 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2789 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2790 if (pscr & SERIAL_PORT_ENABLE) {
2791 pscr &= ~SERIAL_PORT_ENABLE;
2792 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2795 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2796 if (mp->phy == NULL) {
2797 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2798 if (speed == SPEED_1000)
2799 pscr |= SET_GMII_SPEED_TO_1000;
2800 else if (speed == SPEED_100)
2801 pscr |= SET_MII_SPEED_TO_100;
2803 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2805 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2806 if (duplex == DUPLEX_FULL)
2807 pscr |= SET_FULL_DUPLEX_MODE;
2810 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2813 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2814 .ndo_open = mv643xx_eth_open,
2815 .ndo_stop = mv643xx_eth_stop,
2816 .ndo_start_xmit = mv643xx_eth_xmit,
2817 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2818 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2819 .ndo_validate_addr = eth_validate_addr,
2820 .ndo_do_ioctl = mv643xx_eth_ioctl,
2821 .ndo_change_mtu = mv643xx_eth_change_mtu,
2822 .ndo_set_features = mv643xx_eth_set_features,
2823 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2824 .ndo_get_stats = mv643xx_eth_get_stats,
2825 #ifdef CONFIG_NET_POLL_CONTROLLER
2826 .ndo_poll_controller = mv643xx_eth_netpoll,
2830 static int mv643xx_eth_probe(struct platform_device *pdev)
2832 struct mv643xx_eth_platform_data *pd;
2833 struct mv643xx_eth_private *mp;
2834 struct net_device *dev;
2835 struct resource *res;
2838 pd = dev_get_platdata(&pdev->dev);
2840 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2844 if (pd->shared == NULL) {
2845 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2849 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2853 mp = netdev_priv(dev);
2854 platform_set_drvdata(pdev, mp);
2856 mp->shared = platform_get_drvdata(pd->shared);
2857 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2858 mp->port_num = pd->port_number;
2862 /* Kirkwood resets some registers on gated clocks. Especially
2863 * CLK125_BYPASS_EN must be cleared but is not available on
2864 * all other SoCs/System Controllers using this driver.
2866 if (of_device_is_compatible(pdev->dev.of_node,
2867 "marvell,kirkwood-eth-port"))
2868 wrlp(mp, PORT_SERIAL_CONTROL1,
2869 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
2872 * Start with a default rate, and if there is a clock, allow
2873 * it to override the default.
2875 mp->t_clk = 133000000;
2876 mp->clk = devm_clk_get(&pdev->dev, NULL);
2877 if (!IS_ERR(mp->clk)) {
2878 clk_prepare_enable(mp->clk);
2879 mp->t_clk = clk_get_rate(mp->clk);
2880 } else if (!IS_ERR(mp->shared->clk)) {
2881 mp->t_clk = clk_get_rate(mp->shared->clk);
2885 netif_set_real_num_tx_queues(dev, mp->txq_count);
2886 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2890 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
2891 mv643xx_eth_adjust_link, 0,
2892 PHY_INTERFACE_MODE_GMII);
2896 phy_addr_set(mp, mp->phy->addr);
2897 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
2898 mp->phy = phy_scan(mp, pd->phy_addr);
2900 if (IS_ERR(mp->phy))
2901 err = PTR_ERR(mp->phy);
2903 phy_init(mp, pd->speed, pd->duplex);
2905 if (err == -ENODEV) {
2906 err = -EPROBE_DEFER;
2912 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
2914 init_pscr(mp, pd->speed, pd->duplex);
2917 mib_counters_clear(mp);
2919 init_timer(&mp->mib_counters_timer);
2920 mp->mib_counters_timer.data = (unsigned long)mp;
2921 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2922 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2924 spin_lock_init(&mp->mib_counters_lock);
2926 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2928 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
2930 init_timer(&mp->rx_oom);
2931 mp->rx_oom.data = (unsigned long)mp;
2932 mp->rx_oom.function = oom_timer_wrapper;
2935 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2937 dev->irq = res->start;
2939 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2941 dev->watchdog_timeo = 2 * HZ;
2944 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2945 dev->vlan_features = dev->features;
2947 dev->features |= NETIF_F_RXCSUM;
2948 dev->hw_features = dev->features;
2950 dev->priv_flags |= IFF_UNICAST_FLT;
2952 SET_NETDEV_DEV(dev, &pdev->dev);
2954 if (mp->shared->win_protect)
2955 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2957 netif_carrier_off(dev);
2959 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2961 set_rx_coal(mp, 250);
2964 err = register_netdev(dev);
2968 netdev_notice(dev, "port %d with MAC address %pM\n",
2969 mp->port_num, dev->dev_addr);
2971 if (mp->tx_desc_sram_size > 0)
2972 netdev_notice(dev, "configured with sram\n");
2977 if (!IS_ERR(mp->clk))
2978 clk_disable_unprepare(mp->clk);
2984 static int mv643xx_eth_remove(struct platform_device *pdev)
2986 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2988 unregister_netdev(mp->dev);
2989 if (mp->phy != NULL)
2990 phy_disconnect(mp->phy);
2991 cancel_work_sync(&mp->tx_timeout_task);
2993 if (!IS_ERR(mp->clk))
2994 clk_disable_unprepare(mp->clk);
2996 free_netdev(mp->dev);
3001 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3003 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3005 /* Mask all interrupts on ethernet port */
3006 wrlp(mp, INT_MASK, 0);
3009 if (netif_running(mp->dev))
3013 static struct platform_driver mv643xx_eth_driver = {
3014 .probe = mv643xx_eth_probe,
3015 .remove = mv643xx_eth_remove,
3016 .shutdown = mv643xx_eth_shutdown,
3018 .name = MV643XX_ETH_NAME,
3019 .owner = THIS_MODULE,
3023 static int __init mv643xx_eth_init_module(void)
3027 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3029 rc = platform_driver_register(&mv643xx_eth_driver);
3031 platform_driver_unregister(&mv643xx_eth_shared_driver);
3036 module_init(mv643xx_eth_init_module);
3038 static void __exit mv643xx_eth_cleanup_module(void)
3040 platform_driver_unregister(&mv643xx_eth_driver);
3041 platform_driver_unregister(&mv643xx_eth_shared_driver);
3043 module_exit(mv643xx_eth_cleanup_module);
3045 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3046 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3047 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3048 MODULE_LICENSE("GPL");
3049 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3050 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);