2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/types.h>
60 #include <linux/inet_lro.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
65 static char mv643xx_eth_driver_version[] = "1.4";
69 * Registers shared between all ports.
71 #define PHY_ADDR 0x0000
72 #define SMI_REG 0x0004
73 #define SMI_BUSY 0x10000000
74 #define SMI_READ_VALID 0x08000000
75 #define SMI_OPCODE_READ 0x04000000
76 #define SMI_OPCODE_WRITE 0x00000000
77 #define ERR_INT_CAUSE 0x0080
78 #define ERR_INT_SMI_DONE 0x00000010
79 #define ERR_INT_MASK 0x0084
80 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
81 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
82 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
83 #define WINDOW_BAR_ENABLE 0x0290
84 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
87 * Main per-port registers. These live at offset 0x0400 for
88 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
90 #define PORT_CONFIG 0x0000
91 #define UNICAST_PROMISCUOUS_MODE 0x00000001
92 #define PORT_CONFIG_EXT 0x0004
93 #define MAC_ADDR_LOW 0x0014
94 #define MAC_ADDR_HIGH 0x0018
95 #define SDMA_CONFIG 0x001c
96 #define TX_BURST_SIZE_16_64BIT 0x01000000
97 #define TX_BURST_SIZE_4_64BIT 0x00800000
98 #define BLM_TX_NO_SWAP 0x00000020
99 #define BLM_RX_NO_SWAP 0x00000010
100 #define RX_BURST_SIZE_16_64BIT 0x00000008
101 #define RX_BURST_SIZE_4_64BIT 0x00000004
102 #define PORT_SERIAL_CONTROL 0x003c
103 #define SET_MII_SPEED_TO_100 0x01000000
104 #define SET_GMII_SPEED_TO_1000 0x00800000
105 #define SET_FULL_DUPLEX_MODE 0x00200000
106 #define MAX_RX_PACKET_9700BYTE 0x000a0000
107 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
108 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
109 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
110 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
111 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
112 #define FORCE_LINK_PASS 0x00000002
113 #define SERIAL_PORT_ENABLE 0x00000001
114 #define PORT_STATUS 0x0044
115 #define TX_FIFO_EMPTY 0x00000400
116 #define TX_IN_PROGRESS 0x00000080
117 #define PORT_SPEED_MASK 0x00000030
118 #define PORT_SPEED_1000 0x00000010
119 #define PORT_SPEED_100 0x00000020
120 #define PORT_SPEED_10 0x00000000
121 #define FLOW_CONTROL_ENABLED 0x00000008
122 #define FULL_DUPLEX 0x00000004
123 #define LINK_UP 0x00000002
124 #define TXQ_COMMAND 0x0048
125 #define TXQ_FIX_PRIO_CONF 0x004c
126 #define TX_BW_RATE 0x0050
127 #define TX_BW_MTU 0x0058
128 #define TX_BW_BURST 0x005c
129 #define INT_CAUSE 0x0060
130 #define INT_TX_END 0x07f80000
131 #define INT_TX_END_0 0x00080000
132 #define INT_RX 0x000003fc
133 #define INT_RX_0 0x00000004
134 #define INT_EXT 0x00000002
135 #define INT_CAUSE_EXT 0x0064
136 #define INT_EXT_LINK_PHY 0x00110000
137 #define INT_EXT_TX 0x000000ff
138 #define INT_MASK 0x0068
139 #define INT_MASK_EXT 0x006c
140 #define TX_FIFO_URGENT_THRESHOLD 0x0074
141 #define RX_DISCARD_FRAME_CNT 0x0084
142 #define RX_OVERRUN_FRAME_CNT 0x0088
143 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
144 #define TX_BW_RATE_MOVED 0x00e0
145 #define TX_BW_MTU_MOVED 0x00e8
146 #define TX_BW_BURST_MOVED 0x00ec
147 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
148 #define RXQ_COMMAND 0x0280
149 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
150 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
151 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
152 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
155 * Misc per-port registers.
157 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
158 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
159 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
160 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
164 * SDMA configuration register default value.
166 #if defined(__BIG_ENDIAN)
167 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
168 (RX_BURST_SIZE_4_64BIT | \
169 TX_BURST_SIZE_4_64BIT)
170 #elif defined(__LITTLE_ENDIAN)
171 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
172 (RX_BURST_SIZE_4_64BIT | \
175 TX_BURST_SIZE_4_64BIT)
177 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
184 #define DEFAULT_RX_QUEUE_SIZE 128
185 #define DEFAULT_TX_QUEUE_SIZE 256
186 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
192 #if defined(__BIG_ENDIAN)
194 u16 byte_cnt; /* Descriptor buffer byte count */
195 u16 buf_size; /* Buffer size */
196 u32 cmd_sts; /* Descriptor command status */
197 u32 next_desc_ptr; /* Next descriptor pointer */
198 u32 buf_ptr; /* Descriptor buffer pointer */
202 u16 byte_cnt; /* buffer byte count */
203 u16 l4i_chk; /* CPU provided TCP checksum */
204 u32 cmd_sts; /* Command/status field */
205 u32 next_desc_ptr; /* Pointer to next descriptor */
206 u32 buf_ptr; /* pointer to buffer for this descriptor*/
208 #elif defined(__LITTLE_ENDIAN)
210 u32 cmd_sts; /* Descriptor command status */
211 u16 buf_size; /* Buffer size */
212 u16 byte_cnt; /* Descriptor buffer byte count */
213 u32 buf_ptr; /* Descriptor buffer pointer */
214 u32 next_desc_ptr; /* Next descriptor pointer */
218 u32 cmd_sts; /* Command/status field */
219 u16 l4i_chk; /* CPU provided TCP checksum */
220 u16 byte_cnt; /* buffer byte count */
221 u32 buf_ptr; /* pointer to buffer for this descriptor*/
222 u32 next_desc_ptr; /* Pointer to next descriptor */
225 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
228 /* RX & TX descriptor command */
229 #define BUFFER_OWNED_BY_DMA 0x80000000
231 /* RX & TX descriptor status */
232 #define ERROR_SUMMARY 0x00000001
234 /* RX descriptor status */
235 #define LAYER_4_CHECKSUM_OK 0x40000000
236 #define RX_ENABLE_INTERRUPT 0x20000000
237 #define RX_FIRST_DESC 0x08000000
238 #define RX_LAST_DESC 0x04000000
239 #define RX_IP_HDR_OK 0x02000000
240 #define RX_PKT_IS_IPV4 0x01000000
241 #define RX_PKT_IS_ETHERNETV2 0x00800000
242 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
243 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
244 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
246 /* TX descriptor command */
247 #define TX_ENABLE_INTERRUPT 0x00800000
248 #define GEN_CRC 0x00400000
249 #define TX_FIRST_DESC 0x00200000
250 #define TX_LAST_DESC 0x00100000
251 #define ZERO_PADDING 0x00080000
252 #define GEN_IP_V4_CHECKSUM 0x00040000
253 #define GEN_TCP_UDP_CHECKSUM 0x00020000
254 #define UDP_FRAME 0x00010000
255 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
256 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
258 #define TX_IHL_SHIFT 11
261 /* global *******************************************************************/
262 struct mv643xx_eth_shared_private {
264 * Ethernet controller base address.
269 * Points at the right SMI instance to use.
271 struct mv643xx_eth_shared_private *smi;
274 * Provides access to local SMI interface.
276 struct mii_bus *smi_bus;
279 * If we have access to the error interrupt pin (which is
280 * somewhat misnamed as it not only reflects internal errors
281 * but also reflects SMI completion), use that to wait for
282 * SMI access completion instead of polling the SMI busy bit.
285 wait_queue_head_t smi_busy_wait;
288 * Per-port MBUS window access register value.
293 * Hardware-specific parameters.
295 int extended_rx_coal_limit;
301 #define TX_BW_CONTROL_ABSENT 0
302 #define TX_BW_CONTROL_OLD_LAYOUT 1
303 #define TX_BW_CONTROL_NEW_LAYOUT 2
305 static int mv643xx_eth_open(struct net_device *dev);
306 static int mv643xx_eth_stop(struct net_device *dev);
309 /* per-port *****************************************************************/
310 struct mib_counters {
311 u64 good_octets_received;
312 u32 bad_octets_received;
313 u32 internal_mac_transmit_err;
314 u32 good_frames_received;
315 u32 bad_frames_received;
316 u32 broadcast_frames_received;
317 u32 multicast_frames_received;
318 u32 frames_64_octets;
319 u32 frames_65_to_127_octets;
320 u32 frames_128_to_255_octets;
321 u32 frames_256_to_511_octets;
322 u32 frames_512_to_1023_octets;
323 u32 frames_1024_to_max_octets;
324 u64 good_octets_sent;
325 u32 good_frames_sent;
326 u32 excessive_collision;
327 u32 multicast_frames_sent;
328 u32 broadcast_frames_sent;
329 u32 unrec_mac_control_received;
331 u32 good_fc_received;
333 u32 undersize_received;
334 u32 fragments_received;
335 u32 oversize_received;
337 u32 mac_receive_error;
341 /* Non MIB hardware counters */
346 struct lro_counters {
361 struct rx_desc *rx_desc_area;
362 dma_addr_t rx_desc_dma;
363 int rx_desc_area_size;
364 struct sk_buff **rx_skb;
366 struct net_lro_mgr lro_mgr;
367 struct net_lro_desc lro_arr[8];
379 struct tx_desc *tx_desc_area;
380 dma_addr_t tx_desc_dma;
381 int tx_desc_area_size;
383 struct sk_buff_head tx_skb;
385 unsigned long tx_packets;
386 unsigned long tx_bytes;
387 unsigned long tx_dropped;
390 struct mv643xx_eth_private {
391 struct mv643xx_eth_shared_private *shared;
395 struct net_device *dev;
397 struct phy_device *phy;
399 struct timer_list mib_counters_timer;
400 spinlock_t mib_counters_lock;
401 struct mib_counters mib_counters;
403 struct lro_counters lro_counters;
405 struct work_struct tx_timeout_task;
407 struct napi_struct napi;
422 unsigned long rx_desc_sram_addr;
423 int rx_desc_sram_size;
425 struct timer_list rx_oom;
426 struct rx_queue rxq[8];
432 unsigned long tx_desc_sram_addr;
433 int tx_desc_sram_size;
435 struct tx_queue txq[8];
438 * Hardware-specific parameters.
440 #if defined(CONFIG_HAVE_CLK)
447 /* port register accessors **************************************************/
448 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
450 return readl(mp->shared->base + offset);
453 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
455 return readl(mp->base + offset);
458 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
460 writel(data, mp->shared->base + offset);
463 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
465 writel(data, mp->base + offset);
469 /* rxq/txq helper functions *************************************************/
470 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
472 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
475 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
477 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
480 static void rxq_enable(struct rx_queue *rxq)
482 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
483 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
486 static void rxq_disable(struct rx_queue *rxq)
488 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
489 u8 mask = 1 << rxq->index;
491 wrlp(mp, RXQ_COMMAND, mask << 8);
492 while (rdlp(mp, RXQ_COMMAND) & mask)
496 static void txq_reset_hw_ptr(struct tx_queue *txq)
498 struct mv643xx_eth_private *mp = txq_to_mp(txq);
501 addr = (u32)txq->tx_desc_dma;
502 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
503 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
506 static void txq_enable(struct tx_queue *txq)
508 struct mv643xx_eth_private *mp = txq_to_mp(txq);
509 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
512 static void txq_disable(struct tx_queue *txq)
514 struct mv643xx_eth_private *mp = txq_to_mp(txq);
515 u8 mask = 1 << txq->index;
517 wrlp(mp, TXQ_COMMAND, mask << 8);
518 while (rdlp(mp, TXQ_COMMAND) & mask)
522 static void txq_maybe_wake(struct tx_queue *txq)
524 struct mv643xx_eth_private *mp = txq_to_mp(txq);
525 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
527 if (netif_tx_queue_stopped(nq)) {
528 __netif_tx_lock(nq, smp_processor_id());
529 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
530 netif_tx_wake_queue(nq);
531 __netif_tx_unlock(nq);
536 /* rx napi ******************************************************************/
538 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
539 u64 *hdr_flags, void *priv)
541 unsigned long cmd_sts = (unsigned long)priv;
544 * Make sure that this packet is Ethernet II, is not VLAN
545 * tagged, is IPv4, has a valid IP header, and is TCP.
547 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
548 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
549 RX_PKT_IS_VLAN_TAGGED)) !=
550 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
551 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
554 skb_reset_network_header(skb);
555 skb_set_transport_header(skb, ip_hdrlen(skb));
556 *iphdr = ip_hdr(skb);
557 *tcph = tcp_hdr(skb);
558 *hdr_flags = LRO_IPV4 | LRO_TCP;
563 static int rxq_process(struct rx_queue *rxq, int budget)
565 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
566 struct net_device_stats *stats = &mp->dev->stats;
567 int lro_flush_needed;
570 lro_flush_needed = 0;
572 while (rx < budget && rxq->rx_desc_count) {
573 struct rx_desc *rx_desc;
574 unsigned int cmd_sts;
578 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
580 cmd_sts = rx_desc->cmd_sts;
581 if (cmd_sts & BUFFER_OWNED_BY_DMA)
585 skb = rxq->rx_skb[rxq->rx_curr_desc];
586 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
589 if (rxq->rx_curr_desc == rxq->rx_ring_size)
590 rxq->rx_curr_desc = 0;
592 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
593 rx_desc->buf_size, DMA_FROM_DEVICE);
594 rxq->rx_desc_count--;
597 mp->work_rx_refill |= 1 << rxq->index;
599 byte_cnt = rx_desc->byte_cnt;
604 * Note that the descriptor byte count includes 2 dummy
605 * bytes automatically inserted by the hardware at the
606 * start of the packet (which we don't count), and a 4
607 * byte CRC at the end of the packet (which we do count).
610 stats->rx_bytes += byte_cnt - 2;
613 * In case we received a packet without first / last bits
614 * on, or the error summary bit is set, the packet needs
617 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
618 != (RX_FIRST_DESC | RX_LAST_DESC))
622 * The -4 is for the CRC in the trailer of the
625 skb_put(skb, byte_cnt - 2 - 4);
627 if (cmd_sts & LAYER_4_CHECKSUM_OK)
628 skb->ip_summed = CHECKSUM_UNNECESSARY;
629 skb->protocol = eth_type_trans(skb, mp->dev);
631 if (skb->dev->features & NETIF_F_LRO &&
632 skb->ip_summed == CHECKSUM_UNNECESSARY) {
633 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
634 lro_flush_needed = 1;
636 netif_receive_skb(skb);
643 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
644 (RX_FIRST_DESC | RX_LAST_DESC)) {
647 "received packet spanning multiple descriptors\n");
650 if (cmd_sts & ERROR_SUMMARY)
656 if (lro_flush_needed)
657 lro_flush_all(&rxq->lro_mgr);
660 mp->work_rx &= ~(1 << rxq->index);
665 static int rxq_refill(struct rx_queue *rxq, int budget)
667 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
671 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
674 struct rx_desc *rx_desc;
677 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
685 skb_reserve(skb, SKB_DMA_REALIGN);
688 rxq->rx_desc_count++;
690 rx = rxq->rx_used_desc++;
691 if (rxq->rx_used_desc == rxq->rx_ring_size)
692 rxq->rx_used_desc = 0;
694 rx_desc = rxq->rx_desc_area + rx;
696 size = skb->end - skb->data;
697 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
700 rx_desc->buf_size = size;
701 rxq->rx_skb[rx] = skb;
703 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
707 * The hardware automatically prepends 2 bytes of
708 * dummy data to each received packet, so that the
709 * IP header ends up 16-byte aligned.
714 if (refilled < budget)
715 mp->work_rx_refill &= ~(1 << rxq->index);
722 /* tx ***********************************************************************/
723 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
727 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
728 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
730 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
737 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
739 struct mv643xx_eth_private *mp = txq_to_mp(txq);
740 int nr_frags = skb_shinfo(skb)->nr_frags;
743 for (frag = 0; frag < nr_frags; frag++) {
744 skb_frag_t *this_frag;
746 struct tx_desc *desc;
748 this_frag = &skb_shinfo(skb)->frags[frag];
749 tx_index = txq->tx_curr_desc++;
750 if (txq->tx_curr_desc == txq->tx_ring_size)
751 txq->tx_curr_desc = 0;
752 desc = &txq->tx_desc_area[tx_index];
755 * The last fragment will generate an interrupt
756 * which will free the skb on TX completion.
758 if (frag == nr_frags - 1) {
759 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
760 ZERO_PADDING | TX_LAST_DESC |
763 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
767 desc->byte_cnt = skb_frag_size(this_frag);
768 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
770 skb_frag_size(this_frag),
775 static inline __be16 sum16_as_be(__sum16 sum)
777 return (__force __be16)sum;
780 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
782 struct mv643xx_eth_private *mp = txq_to_mp(txq);
783 int nr_frags = skb_shinfo(skb)->nr_frags;
785 struct tx_desc *desc;
790 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
793 if (skb->ip_summed == CHECKSUM_PARTIAL) {
797 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
798 skb->protocol != htons(ETH_P_8021Q));
800 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
801 tag_bytes = hdr_len - ETH_HLEN;
802 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
803 unlikely(tag_bytes & ~12)) {
804 if (skb_checksum_help(skb) == 0)
811 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
813 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
815 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
817 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
819 switch (ip_hdr(skb)->protocol) {
821 cmd_sts |= UDP_FRAME;
822 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
825 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
832 /* Errata BTS #50, IHL must be 5 if no HW checksum */
833 cmd_sts |= 5 << TX_IHL_SHIFT;
836 tx_index = txq->tx_curr_desc++;
837 if (txq->tx_curr_desc == txq->tx_ring_size)
838 txq->tx_curr_desc = 0;
839 desc = &txq->tx_desc_area[tx_index];
842 txq_submit_frag_skb(txq, skb);
843 length = skb_headlen(skb);
845 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
849 desc->l4i_chk = l4i_chk;
850 desc->byte_cnt = length;
851 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
852 length, DMA_TO_DEVICE);
854 __skb_queue_tail(&txq->tx_skb, skb);
856 skb_tx_timestamp(skb);
858 /* ensure all other descriptors are written before first cmd_sts */
860 desc->cmd_sts = cmd_sts;
862 /* clear TX_END status */
863 mp->work_tx_end &= ~(1 << txq->index);
865 /* ensure all descriptors are written before poking hardware */
869 txq->tx_desc_count += nr_frags + 1;
874 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
876 struct mv643xx_eth_private *mp = netdev_priv(dev);
878 struct tx_queue *txq;
879 struct netdev_queue *nq;
881 queue = skb_get_queue_mapping(skb);
882 txq = mp->txq + queue;
883 nq = netdev_get_tx_queue(dev, queue);
885 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
887 netdev_printk(KERN_DEBUG, dev,
888 "failed to linearize skb with tiny unaligned fragment\n");
889 return NETDEV_TX_BUSY;
892 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
894 netdev_err(dev, "tx queue full?!\n");
901 if (!txq_submit_skb(txq, skb)) {
904 txq->tx_bytes += length;
907 entries_left = txq->tx_ring_size - txq->tx_desc_count;
908 if (entries_left < MAX_SKB_FRAGS + 1)
909 netif_tx_stop_queue(nq);
916 /* tx napi ******************************************************************/
917 static void txq_kick(struct tx_queue *txq)
919 struct mv643xx_eth_private *mp = txq_to_mp(txq);
920 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
924 __netif_tx_lock(nq, smp_processor_id());
926 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
929 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
930 expected_ptr = (u32)txq->tx_desc_dma +
931 txq->tx_curr_desc * sizeof(struct tx_desc);
933 if (hw_desc_ptr != expected_ptr)
937 __netif_tx_unlock(nq);
939 mp->work_tx_end &= ~(1 << txq->index);
942 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
944 struct mv643xx_eth_private *mp = txq_to_mp(txq);
945 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
948 __netif_tx_lock(nq, smp_processor_id());
951 while (reclaimed < budget && txq->tx_desc_count > 0) {
953 struct tx_desc *desc;
957 tx_index = txq->tx_used_desc;
958 desc = &txq->tx_desc_area[tx_index];
959 cmd_sts = desc->cmd_sts;
961 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
964 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
967 txq->tx_used_desc = tx_index + 1;
968 if (txq->tx_used_desc == txq->tx_ring_size)
969 txq->tx_used_desc = 0;
972 txq->tx_desc_count--;
975 if (cmd_sts & TX_LAST_DESC)
976 skb = __skb_dequeue(&txq->tx_skb);
978 if (cmd_sts & ERROR_SUMMARY) {
979 netdev_info(mp->dev, "tx error\n");
980 mp->dev->stats.tx_errors++;
983 if (cmd_sts & TX_FIRST_DESC) {
984 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
985 desc->byte_cnt, DMA_TO_DEVICE);
987 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
988 desc->byte_cnt, DMA_TO_DEVICE);
994 __netif_tx_unlock(nq);
996 if (reclaimed < budget)
997 mp->work_tx &= ~(1 << txq->index);
1003 /* tx rate control **********************************************************/
1005 * Set total maximum TX rate (shared by all TX queues for this port)
1006 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1008 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1014 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1015 if (token_rate > 1023)
1018 mtu = (mp->dev->mtu + 255) >> 8;
1022 bucket_size = (burst + 255) >> 8;
1023 if (bucket_size > 65535)
1024 bucket_size = 65535;
1026 switch (mp->shared->tx_bw_control) {
1027 case TX_BW_CONTROL_OLD_LAYOUT:
1028 wrlp(mp, TX_BW_RATE, token_rate);
1029 wrlp(mp, TX_BW_MTU, mtu);
1030 wrlp(mp, TX_BW_BURST, bucket_size);
1032 case TX_BW_CONTROL_NEW_LAYOUT:
1033 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1034 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1035 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1040 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1042 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1046 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1047 if (token_rate > 1023)
1050 bucket_size = (burst + 255) >> 8;
1051 if (bucket_size > 65535)
1052 bucket_size = 65535;
1054 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1055 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1058 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1060 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1065 * Turn on fixed priority mode.
1068 switch (mp->shared->tx_bw_control) {
1069 case TX_BW_CONTROL_OLD_LAYOUT:
1070 off = TXQ_FIX_PRIO_CONF;
1072 case TX_BW_CONTROL_NEW_LAYOUT:
1073 off = TXQ_FIX_PRIO_CONF_MOVED;
1078 val = rdlp(mp, off);
1079 val |= 1 << txq->index;
1085 /* mii management interface *************************************************/
1086 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1088 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1089 u32 autoneg_disable = FORCE_LINK_PASS |
1090 DISABLE_AUTO_NEG_SPEED_GMII |
1091 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1092 DISABLE_AUTO_NEG_FOR_DUPLEX;
1094 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1095 /* enable auto negotiation */
1096 pscr &= ~autoneg_disable;
1100 pscr |= autoneg_disable;
1102 if (mp->phy->speed == SPEED_1000) {
1103 /* force gigabit, half duplex not supported */
1104 pscr |= SET_GMII_SPEED_TO_1000;
1105 pscr |= SET_FULL_DUPLEX_MODE;
1109 pscr &= ~SET_GMII_SPEED_TO_1000;
1111 if (mp->phy->speed == SPEED_100)
1112 pscr |= SET_MII_SPEED_TO_100;
1114 pscr &= ~SET_MII_SPEED_TO_100;
1116 if (mp->phy->duplex == DUPLEX_FULL)
1117 pscr |= SET_FULL_DUPLEX_MODE;
1119 pscr &= ~SET_FULL_DUPLEX_MODE;
1122 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1125 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1127 struct mv643xx_eth_shared_private *msp = dev_id;
1129 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1130 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1131 wake_up(&msp->smi_busy_wait);
1138 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1140 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1143 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1145 if (msp->err_interrupt == NO_IRQ) {
1148 for (i = 0; !smi_is_done(msp); i++) {
1157 if (!smi_is_done(msp)) {
1158 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1159 msecs_to_jiffies(100));
1160 if (!smi_is_done(msp))
1167 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1169 struct mv643xx_eth_shared_private *msp = bus->priv;
1170 void __iomem *smi_reg = msp->base + SMI_REG;
1173 if (smi_wait_ready(msp)) {
1174 pr_warn("SMI bus busy timeout\n");
1178 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1180 if (smi_wait_ready(msp)) {
1181 pr_warn("SMI bus busy timeout\n");
1185 ret = readl(smi_reg);
1186 if (!(ret & SMI_READ_VALID)) {
1187 pr_warn("SMI bus read not valid\n");
1191 return ret & 0xffff;
1194 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1196 struct mv643xx_eth_shared_private *msp = bus->priv;
1197 void __iomem *smi_reg = msp->base + SMI_REG;
1199 if (smi_wait_ready(msp)) {
1200 pr_warn("SMI bus busy timeout\n");
1204 writel(SMI_OPCODE_WRITE | (reg << 21) |
1205 (addr << 16) | (val & 0xffff), smi_reg);
1207 if (smi_wait_ready(msp)) {
1208 pr_warn("SMI bus busy timeout\n");
1216 /* statistics ***************************************************************/
1217 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1219 struct mv643xx_eth_private *mp = netdev_priv(dev);
1220 struct net_device_stats *stats = &dev->stats;
1221 unsigned long tx_packets = 0;
1222 unsigned long tx_bytes = 0;
1223 unsigned long tx_dropped = 0;
1226 for (i = 0; i < mp->txq_count; i++) {
1227 struct tx_queue *txq = mp->txq + i;
1229 tx_packets += txq->tx_packets;
1230 tx_bytes += txq->tx_bytes;
1231 tx_dropped += txq->tx_dropped;
1234 stats->tx_packets = tx_packets;
1235 stats->tx_bytes = tx_bytes;
1236 stats->tx_dropped = tx_dropped;
1241 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1243 u32 lro_aggregated = 0;
1244 u32 lro_flushed = 0;
1245 u32 lro_no_desc = 0;
1248 for (i = 0; i < mp->rxq_count; i++) {
1249 struct rx_queue *rxq = mp->rxq + i;
1251 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1252 lro_flushed += rxq->lro_mgr.stats.flushed;
1253 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1256 mp->lro_counters.lro_aggregated = lro_aggregated;
1257 mp->lro_counters.lro_flushed = lro_flushed;
1258 mp->lro_counters.lro_no_desc = lro_no_desc;
1261 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1263 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1266 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1270 for (i = 0; i < 0x80; i += 4)
1273 /* Clear non MIB hw counters also */
1274 rdlp(mp, RX_DISCARD_FRAME_CNT);
1275 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1278 static void mib_counters_update(struct mv643xx_eth_private *mp)
1280 struct mib_counters *p = &mp->mib_counters;
1282 spin_lock_bh(&mp->mib_counters_lock);
1283 p->good_octets_received += mib_read(mp, 0x00);
1284 p->bad_octets_received += mib_read(mp, 0x08);
1285 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1286 p->good_frames_received += mib_read(mp, 0x10);
1287 p->bad_frames_received += mib_read(mp, 0x14);
1288 p->broadcast_frames_received += mib_read(mp, 0x18);
1289 p->multicast_frames_received += mib_read(mp, 0x1c);
1290 p->frames_64_octets += mib_read(mp, 0x20);
1291 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1292 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1293 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1294 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1295 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1296 p->good_octets_sent += mib_read(mp, 0x38);
1297 p->good_frames_sent += mib_read(mp, 0x40);
1298 p->excessive_collision += mib_read(mp, 0x44);
1299 p->multicast_frames_sent += mib_read(mp, 0x48);
1300 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1301 p->unrec_mac_control_received += mib_read(mp, 0x50);
1302 p->fc_sent += mib_read(mp, 0x54);
1303 p->good_fc_received += mib_read(mp, 0x58);
1304 p->bad_fc_received += mib_read(mp, 0x5c);
1305 p->undersize_received += mib_read(mp, 0x60);
1306 p->fragments_received += mib_read(mp, 0x64);
1307 p->oversize_received += mib_read(mp, 0x68);
1308 p->jabber_received += mib_read(mp, 0x6c);
1309 p->mac_receive_error += mib_read(mp, 0x70);
1310 p->bad_crc_event += mib_read(mp, 0x74);
1311 p->collision += mib_read(mp, 0x78);
1312 p->late_collision += mib_read(mp, 0x7c);
1313 /* Non MIB hardware counters */
1314 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1315 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1316 spin_unlock_bh(&mp->mib_counters_lock);
1318 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1321 static void mib_counters_timer_wrapper(unsigned long _mp)
1323 struct mv643xx_eth_private *mp = (void *)_mp;
1325 mib_counters_update(mp);
1329 /* interrupt coalescing *****************************************************/
1331 * Hardware coalescing parameters are set in units of 64 t_clk
1334 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1336 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1338 * In the ->set*() methods, we round the computed register value
1339 * to the nearest integer.
1341 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1343 u32 val = rdlp(mp, SDMA_CONFIG);
1346 if (mp->shared->extended_rx_coal_limit)
1347 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1349 temp = (val & 0x003fff00) >> 8;
1352 do_div(temp, mp->t_clk);
1354 return (unsigned int)temp;
1357 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1362 temp = (u64)usec * mp->t_clk;
1364 do_div(temp, 64000000);
1366 val = rdlp(mp, SDMA_CONFIG);
1367 if (mp->shared->extended_rx_coal_limit) {
1371 val |= (temp & 0x8000) << 10;
1372 val |= (temp & 0x7fff) << 7;
1377 val |= (temp & 0x3fff) << 8;
1379 wrlp(mp, SDMA_CONFIG, val);
1382 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1386 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1388 do_div(temp, mp->t_clk);
1390 return (unsigned int)temp;
1393 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1397 temp = (u64)usec * mp->t_clk;
1399 do_div(temp, 64000000);
1404 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1408 /* ethtool ******************************************************************/
1409 struct mv643xx_eth_stats {
1410 char stat_string[ETH_GSTRING_LEN];
1417 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1418 offsetof(struct net_device, stats.m), -1 }
1420 #define MIBSTAT(m) \
1421 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1422 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1424 #define LROSTAT(m) \
1425 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1426 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1428 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1437 MIBSTAT(good_octets_received),
1438 MIBSTAT(bad_octets_received),
1439 MIBSTAT(internal_mac_transmit_err),
1440 MIBSTAT(good_frames_received),
1441 MIBSTAT(bad_frames_received),
1442 MIBSTAT(broadcast_frames_received),
1443 MIBSTAT(multicast_frames_received),
1444 MIBSTAT(frames_64_octets),
1445 MIBSTAT(frames_65_to_127_octets),
1446 MIBSTAT(frames_128_to_255_octets),
1447 MIBSTAT(frames_256_to_511_octets),
1448 MIBSTAT(frames_512_to_1023_octets),
1449 MIBSTAT(frames_1024_to_max_octets),
1450 MIBSTAT(good_octets_sent),
1451 MIBSTAT(good_frames_sent),
1452 MIBSTAT(excessive_collision),
1453 MIBSTAT(multicast_frames_sent),
1454 MIBSTAT(broadcast_frames_sent),
1455 MIBSTAT(unrec_mac_control_received),
1457 MIBSTAT(good_fc_received),
1458 MIBSTAT(bad_fc_received),
1459 MIBSTAT(undersize_received),
1460 MIBSTAT(fragments_received),
1461 MIBSTAT(oversize_received),
1462 MIBSTAT(jabber_received),
1463 MIBSTAT(mac_receive_error),
1464 MIBSTAT(bad_crc_event),
1466 MIBSTAT(late_collision),
1467 MIBSTAT(rx_discard),
1468 MIBSTAT(rx_overrun),
1469 LROSTAT(lro_aggregated),
1470 LROSTAT(lro_flushed),
1471 LROSTAT(lro_no_desc),
1475 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1476 struct ethtool_cmd *cmd)
1480 err = phy_read_status(mp->phy);
1482 err = phy_ethtool_gset(mp->phy, cmd);
1485 * The MAC does not support 1000baseT_Half.
1487 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1488 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1494 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1495 struct ethtool_cmd *cmd)
1499 port_status = rdlp(mp, PORT_STATUS);
1501 cmd->supported = SUPPORTED_MII;
1502 cmd->advertising = ADVERTISED_MII;
1503 switch (port_status & PORT_SPEED_MASK) {
1505 ethtool_cmd_speed_set(cmd, SPEED_10);
1507 case PORT_SPEED_100:
1508 ethtool_cmd_speed_set(cmd, SPEED_100);
1510 case PORT_SPEED_1000:
1511 ethtool_cmd_speed_set(cmd, SPEED_1000);
1517 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1518 cmd->port = PORT_MII;
1519 cmd->phy_address = 0;
1520 cmd->transceiver = XCVR_INTERNAL;
1521 cmd->autoneg = AUTONEG_DISABLE;
1529 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1531 struct mv643xx_eth_private *mp = netdev_priv(dev);
1535 phy_ethtool_get_wol(mp->phy, wol);
1539 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1541 struct mv643xx_eth_private *mp = netdev_priv(dev);
1544 if (mp->phy == NULL)
1547 err = phy_ethtool_set_wol(mp->phy, wol);
1548 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1549 * this debugging hint is useful to have.
1551 if (err == -EOPNOTSUPP)
1552 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1557 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1559 struct mv643xx_eth_private *mp = netdev_priv(dev);
1561 if (mp->phy != NULL)
1562 return mv643xx_eth_get_settings_phy(mp, cmd);
1564 return mv643xx_eth_get_settings_phyless(mp, cmd);
1568 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1570 struct mv643xx_eth_private *mp = netdev_priv(dev);
1573 if (mp->phy == NULL)
1577 * The MAC does not support 1000baseT_Half.
1579 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1581 ret = phy_ethtool_sset(mp->phy, cmd);
1583 mv643xx_adjust_pscr(mp);
1587 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1588 struct ethtool_drvinfo *drvinfo)
1590 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1591 sizeof(drvinfo->driver));
1592 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1593 sizeof(drvinfo->version));
1594 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1595 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1596 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1599 static int mv643xx_eth_nway_reset(struct net_device *dev)
1601 struct mv643xx_eth_private *mp = netdev_priv(dev);
1603 if (mp->phy == NULL)
1606 return genphy_restart_aneg(mp->phy);
1610 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1612 struct mv643xx_eth_private *mp = netdev_priv(dev);
1614 ec->rx_coalesce_usecs = get_rx_coal(mp);
1615 ec->tx_coalesce_usecs = get_tx_coal(mp);
1621 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1623 struct mv643xx_eth_private *mp = netdev_priv(dev);
1625 set_rx_coal(mp, ec->rx_coalesce_usecs);
1626 set_tx_coal(mp, ec->tx_coalesce_usecs);
1632 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1634 struct mv643xx_eth_private *mp = netdev_priv(dev);
1636 er->rx_max_pending = 4096;
1637 er->tx_max_pending = 4096;
1639 er->rx_pending = mp->rx_ring_size;
1640 er->tx_pending = mp->tx_ring_size;
1644 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1646 struct mv643xx_eth_private *mp = netdev_priv(dev);
1648 if (er->rx_mini_pending || er->rx_jumbo_pending)
1651 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1652 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1654 if (netif_running(dev)) {
1655 mv643xx_eth_stop(dev);
1656 if (mv643xx_eth_open(dev)) {
1658 "fatal error on re-opening device after ring param change\n");
1668 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1670 struct mv643xx_eth_private *mp = netdev_priv(dev);
1671 bool rx_csum = features & NETIF_F_RXCSUM;
1673 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1678 static void mv643xx_eth_get_strings(struct net_device *dev,
1679 uint32_t stringset, uint8_t *data)
1683 if (stringset == ETH_SS_STATS) {
1684 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1685 memcpy(data + i * ETH_GSTRING_LEN,
1686 mv643xx_eth_stats[i].stat_string,
1692 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1693 struct ethtool_stats *stats,
1696 struct mv643xx_eth_private *mp = netdev_priv(dev);
1699 mv643xx_eth_get_stats(dev);
1700 mib_counters_update(mp);
1701 mv643xx_eth_grab_lro_stats(mp);
1703 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1704 const struct mv643xx_eth_stats *stat;
1707 stat = mv643xx_eth_stats + i;
1709 if (stat->netdev_off >= 0)
1710 p = ((void *)mp->dev) + stat->netdev_off;
1712 p = ((void *)mp) + stat->mp_off;
1714 data[i] = (stat->sizeof_stat == 8) ?
1715 *(uint64_t *)p : *(uint32_t *)p;
1719 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1721 if (sset == ETH_SS_STATS)
1722 return ARRAY_SIZE(mv643xx_eth_stats);
1727 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1728 .get_settings = mv643xx_eth_get_settings,
1729 .set_settings = mv643xx_eth_set_settings,
1730 .get_drvinfo = mv643xx_eth_get_drvinfo,
1731 .nway_reset = mv643xx_eth_nway_reset,
1732 .get_link = ethtool_op_get_link,
1733 .get_coalesce = mv643xx_eth_get_coalesce,
1734 .set_coalesce = mv643xx_eth_set_coalesce,
1735 .get_ringparam = mv643xx_eth_get_ringparam,
1736 .set_ringparam = mv643xx_eth_set_ringparam,
1737 .get_strings = mv643xx_eth_get_strings,
1738 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1739 .get_sset_count = mv643xx_eth_get_sset_count,
1740 .get_ts_info = ethtool_op_get_ts_info,
1741 .get_wol = mv643xx_eth_get_wol,
1742 .set_wol = mv643xx_eth_set_wol,
1746 /* address handling *********************************************************/
1747 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1749 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1750 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1752 addr[0] = (mac_h >> 24) & 0xff;
1753 addr[1] = (mac_h >> 16) & 0xff;
1754 addr[2] = (mac_h >> 8) & 0xff;
1755 addr[3] = mac_h & 0xff;
1756 addr[4] = (mac_l >> 8) & 0xff;
1757 addr[5] = mac_l & 0xff;
1760 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1762 wrlp(mp, MAC_ADDR_HIGH,
1763 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1764 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1767 static u32 uc_addr_filter_mask(struct net_device *dev)
1769 struct netdev_hw_addr *ha;
1772 if (dev->flags & IFF_PROMISC)
1775 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1776 netdev_for_each_uc_addr(ha, dev) {
1777 if (memcmp(dev->dev_addr, ha->addr, 5))
1779 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1782 nibbles |= 1 << (ha->addr[5] & 0x0f);
1788 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1790 struct mv643xx_eth_private *mp = netdev_priv(dev);
1795 uc_addr_set(mp, dev->dev_addr);
1797 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1799 nibbles = uc_addr_filter_mask(dev);
1801 port_config |= UNICAST_PROMISCUOUS_MODE;
1805 for (i = 0; i < 16; i += 4) {
1806 int off = UNICAST_TABLE(mp->port_num) + i;
1823 wrlp(mp, PORT_CONFIG, port_config);
1826 static int addr_crc(unsigned char *addr)
1831 for (i = 0; i < 6; i++) {
1834 crc = (crc ^ addr[i]) << 8;
1835 for (j = 7; j >= 0; j--) {
1836 if (crc & (0x100 << j))
1844 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1846 struct mv643xx_eth_private *mp = netdev_priv(dev);
1849 struct netdev_hw_addr *ha;
1852 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1857 port_num = mp->port_num;
1858 accept = 0x01010101;
1859 for (i = 0; i < 0x100; i += 4) {
1860 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1861 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1866 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1867 if (mc_spec == NULL)
1869 mc_other = mc_spec + (0x100 >> 2);
1871 memset(mc_spec, 0, 0x100);
1872 memset(mc_other, 0, 0x100);
1874 netdev_for_each_mc_addr(ha, dev) {
1879 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1884 entry = addr_crc(a);
1887 table[entry >> 2] |= 1 << (8 * (entry & 3));
1890 for (i = 0; i < 0x100; i += 4) {
1891 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1892 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1898 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1900 mv643xx_eth_program_unicast_filter(dev);
1901 mv643xx_eth_program_multicast_filter(dev);
1904 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1906 struct sockaddr *sa = addr;
1908 if (!is_valid_ether_addr(sa->sa_data))
1909 return -EADDRNOTAVAIL;
1911 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1913 netif_addr_lock_bh(dev);
1914 mv643xx_eth_program_unicast_filter(dev);
1915 netif_addr_unlock_bh(dev);
1921 /* rx/tx queue initialisation ***********************************************/
1922 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1924 struct rx_queue *rxq = mp->rxq + index;
1925 struct rx_desc *rx_desc;
1931 rxq->rx_ring_size = mp->rx_ring_size;
1933 rxq->rx_desc_count = 0;
1934 rxq->rx_curr_desc = 0;
1935 rxq->rx_used_desc = 0;
1937 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1939 if (index == 0 && size <= mp->rx_desc_sram_size) {
1940 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1941 mp->rx_desc_sram_size);
1942 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1944 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1945 size, &rxq->rx_desc_dma,
1949 if (rxq->rx_desc_area == NULL) {
1951 "can't allocate rx ring (%d bytes)\n", size);
1954 memset(rxq->rx_desc_area, 0, size);
1956 rxq->rx_desc_area_size = size;
1957 rxq->rx_skb = kmalloc_array(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1959 if (rxq->rx_skb == NULL)
1962 rx_desc = rxq->rx_desc_area;
1963 for (i = 0; i < rxq->rx_ring_size; i++) {
1967 if (nexti == rxq->rx_ring_size)
1970 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1971 nexti * sizeof(struct rx_desc);
1974 rxq->lro_mgr.dev = mp->dev;
1975 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1976 rxq->lro_mgr.features = LRO_F_NAPI;
1977 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1978 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1979 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1980 rxq->lro_mgr.max_aggr = 32;
1981 rxq->lro_mgr.frag_align_pad = 0;
1982 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1983 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1985 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1991 if (index == 0 && size <= mp->rx_desc_sram_size)
1992 iounmap(rxq->rx_desc_area);
1994 dma_free_coherent(mp->dev->dev.parent, size,
2002 static void rxq_deinit(struct rx_queue *rxq)
2004 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2009 for (i = 0; i < rxq->rx_ring_size; i++) {
2010 if (rxq->rx_skb[i]) {
2011 dev_kfree_skb(rxq->rx_skb[i]);
2012 rxq->rx_desc_count--;
2016 if (rxq->rx_desc_count) {
2017 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2018 rxq->rx_desc_count);
2021 if (rxq->index == 0 &&
2022 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2023 iounmap(rxq->rx_desc_area);
2025 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2026 rxq->rx_desc_area, rxq->rx_desc_dma);
2031 static int txq_init(struct mv643xx_eth_private *mp, int index)
2033 struct tx_queue *txq = mp->txq + index;
2034 struct tx_desc *tx_desc;
2040 txq->tx_ring_size = mp->tx_ring_size;
2042 txq->tx_desc_count = 0;
2043 txq->tx_curr_desc = 0;
2044 txq->tx_used_desc = 0;
2046 size = txq->tx_ring_size * sizeof(struct tx_desc);
2048 if (index == 0 && size <= mp->tx_desc_sram_size) {
2049 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2050 mp->tx_desc_sram_size);
2051 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2053 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2054 size, &txq->tx_desc_dma,
2058 if (txq->tx_desc_area == NULL) {
2060 "can't allocate tx ring (%d bytes)\n", size);
2063 memset(txq->tx_desc_area, 0, size);
2065 txq->tx_desc_area_size = size;
2067 tx_desc = txq->tx_desc_area;
2068 for (i = 0; i < txq->tx_ring_size; i++) {
2069 struct tx_desc *txd = tx_desc + i;
2073 if (nexti == txq->tx_ring_size)
2077 txd->next_desc_ptr = txq->tx_desc_dma +
2078 nexti * sizeof(struct tx_desc);
2081 skb_queue_head_init(&txq->tx_skb);
2086 static void txq_deinit(struct tx_queue *txq)
2088 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2091 txq_reclaim(txq, txq->tx_ring_size, 1);
2093 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2095 if (txq->index == 0 &&
2096 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2097 iounmap(txq->tx_desc_area);
2099 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2100 txq->tx_desc_area, txq->tx_desc_dma);
2104 /* netdev ops and related ***************************************************/
2105 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2110 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2115 if (int_cause & INT_EXT) {
2116 int_cause &= ~INT_EXT;
2117 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2121 wrlp(mp, INT_CAUSE, ~int_cause);
2122 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2123 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2124 mp->work_rx |= (int_cause & INT_RX) >> 2;
2127 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2128 if (int_cause_ext) {
2129 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2130 if (int_cause_ext & INT_EXT_LINK_PHY)
2132 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2138 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2140 struct net_device *dev = (struct net_device *)dev_id;
2141 struct mv643xx_eth_private *mp = netdev_priv(dev);
2143 if (unlikely(!mv643xx_eth_collect_events(mp)))
2146 wrlp(mp, INT_MASK, 0);
2147 napi_schedule(&mp->napi);
2152 static void handle_link_event(struct mv643xx_eth_private *mp)
2154 struct net_device *dev = mp->dev;
2160 port_status = rdlp(mp, PORT_STATUS);
2161 if (!(port_status & LINK_UP)) {
2162 if (netif_carrier_ok(dev)) {
2165 netdev_info(dev, "link down\n");
2167 netif_carrier_off(dev);
2169 for (i = 0; i < mp->txq_count; i++) {
2170 struct tx_queue *txq = mp->txq + i;
2172 txq_reclaim(txq, txq->tx_ring_size, 1);
2173 txq_reset_hw_ptr(txq);
2179 switch (port_status & PORT_SPEED_MASK) {
2183 case PORT_SPEED_100:
2186 case PORT_SPEED_1000:
2193 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2194 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2196 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2197 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2199 if (!netif_carrier_ok(dev))
2200 netif_carrier_on(dev);
2203 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2205 struct mv643xx_eth_private *mp;
2208 mp = container_of(napi, struct mv643xx_eth_private, napi);
2210 if (unlikely(mp->oom)) {
2212 del_timer(&mp->rx_oom);
2216 while (work_done < budget) {
2221 if (mp->work_link) {
2223 handle_link_event(mp);
2228 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2229 if (likely(!mp->oom))
2230 queue_mask |= mp->work_rx_refill;
2233 if (mv643xx_eth_collect_events(mp))
2238 queue = fls(queue_mask) - 1;
2239 queue_mask = 1 << queue;
2241 work_tbd = budget - work_done;
2245 if (mp->work_tx_end & queue_mask) {
2246 txq_kick(mp->txq + queue);
2247 } else if (mp->work_tx & queue_mask) {
2248 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2249 txq_maybe_wake(mp->txq + queue);
2250 } else if (mp->work_rx & queue_mask) {
2251 work_done += rxq_process(mp->rxq + queue, work_tbd);
2252 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2253 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2259 if (work_done < budget) {
2261 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2262 napi_complete(napi);
2263 wrlp(mp, INT_MASK, mp->int_mask);
2269 static inline void oom_timer_wrapper(unsigned long data)
2271 struct mv643xx_eth_private *mp = (void *)data;
2273 napi_schedule(&mp->napi);
2276 static void phy_reset(struct mv643xx_eth_private *mp)
2280 data = phy_read(mp->phy, MII_BMCR);
2285 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2289 data = phy_read(mp->phy, MII_BMCR);
2290 } while (data >= 0 && data & BMCR_RESET);
2293 static void port_start(struct mv643xx_eth_private *mp)
2299 * Perform PHY reset, if there is a PHY.
2301 if (mp->phy != NULL) {
2302 struct ethtool_cmd cmd;
2304 mv643xx_eth_get_settings(mp->dev, &cmd);
2306 mv643xx_eth_set_settings(mp->dev, &cmd);
2310 * Configure basic link parameters.
2312 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2314 pscr |= SERIAL_PORT_ENABLE;
2315 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2317 pscr |= DO_NOT_FORCE_LINK_FAIL;
2318 if (mp->phy == NULL)
2319 pscr |= FORCE_LINK_PASS;
2320 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2323 * Configure TX path and queues.
2325 tx_set_rate(mp, 1000000000, 16777216);
2326 for (i = 0; i < mp->txq_count; i++) {
2327 struct tx_queue *txq = mp->txq + i;
2329 txq_reset_hw_ptr(txq);
2330 txq_set_rate(txq, 1000000000, 16777216);
2331 txq_set_fixed_prio_mode(txq);
2335 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2336 * frames to RX queue #0, and include the pseudo-header when
2337 * calculating receive checksums.
2339 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2342 * Treat BPDUs as normal multicasts, and disable partition mode.
2344 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2347 * Add configured unicast addresses to address filter table.
2349 mv643xx_eth_program_unicast_filter(mp->dev);
2352 * Enable the receive queues.
2354 for (i = 0; i < mp->rxq_count; i++) {
2355 struct rx_queue *rxq = mp->rxq + i;
2358 addr = (u32)rxq->rx_desc_dma;
2359 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2360 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2366 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2371 * Reserve 2+14 bytes for an ethernet header (the hardware
2372 * automatically prepends 2 bytes of dummy data to each
2373 * received packet), 16 bytes for up to four VLAN tags, and
2374 * 4 bytes for the trailing FCS -- 36 bytes total.
2376 skb_size = mp->dev->mtu + 36;
2379 * Make sure that the skb size is a multiple of 8 bytes, as
2380 * the lower three bits of the receive descriptor's buffer
2381 * size field are ignored by the hardware.
2383 mp->skb_size = (skb_size + 7) & ~7;
2386 * If NET_SKB_PAD is smaller than a cache line,
2387 * netdev_alloc_skb() will cause skb->data to be misaligned
2388 * to a cache line boundary. If this is the case, include
2389 * some extra space to allow re-aligning the data area.
2391 mp->skb_size += SKB_DMA_REALIGN;
2394 static int mv643xx_eth_open(struct net_device *dev)
2396 struct mv643xx_eth_private *mp = netdev_priv(dev);
2400 wrlp(mp, INT_CAUSE, 0);
2401 wrlp(mp, INT_CAUSE_EXT, 0);
2402 rdlp(mp, INT_CAUSE_EXT);
2404 err = request_irq(dev->irq, mv643xx_eth_irq,
2405 IRQF_SHARED, dev->name, dev);
2407 netdev_err(dev, "can't assign irq\n");
2411 mv643xx_eth_recalc_skb_size(mp);
2413 napi_enable(&mp->napi);
2415 mp->int_mask = INT_EXT;
2417 for (i = 0; i < mp->rxq_count; i++) {
2418 err = rxq_init(mp, i);
2421 rxq_deinit(mp->rxq + i);
2425 rxq_refill(mp->rxq + i, INT_MAX);
2426 mp->int_mask |= INT_RX_0 << i;
2430 mp->rx_oom.expires = jiffies + (HZ / 10);
2431 add_timer(&mp->rx_oom);
2434 for (i = 0; i < mp->txq_count; i++) {
2435 err = txq_init(mp, i);
2438 txq_deinit(mp->txq + i);
2441 mp->int_mask |= INT_TX_END_0 << i;
2446 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2447 wrlp(mp, INT_MASK, mp->int_mask);
2453 for (i = 0; i < mp->rxq_count; i++)
2454 rxq_deinit(mp->rxq + i);
2456 free_irq(dev->irq, dev);
2461 static void port_reset(struct mv643xx_eth_private *mp)
2466 for (i = 0; i < mp->rxq_count; i++)
2467 rxq_disable(mp->rxq + i);
2468 for (i = 0; i < mp->txq_count; i++)
2469 txq_disable(mp->txq + i);
2472 u32 ps = rdlp(mp, PORT_STATUS);
2474 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2479 /* Reset the Enable bit in the Configuration Register */
2480 data = rdlp(mp, PORT_SERIAL_CONTROL);
2481 data &= ~(SERIAL_PORT_ENABLE |
2482 DO_NOT_FORCE_LINK_FAIL |
2484 wrlp(mp, PORT_SERIAL_CONTROL, data);
2487 static int mv643xx_eth_stop(struct net_device *dev)
2489 struct mv643xx_eth_private *mp = netdev_priv(dev);
2492 wrlp(mp, INT_MASK_EXT, 0x00000000);
2493 wrlp(mp, INT_MASK, 0x00000000);
2496 napi_disable(&mp->napi);
2498 del_timer_sync(&mp->rx_oom);
2500 netif_carrier_off(dev);
2502 free_irq(dev->irq, dev);
2505 mv643xx_eth_get_stats(dev);
2506 mib_counters_update(mp);
2507 del_timer_sync(&mp->mib_counters_timer);
2509 for (i = 0; i < mp->rxq_count; i++)
2510 rxq_deinit(mp->rxq + i);
2511 for (i = 0; i < mp->txq_count; i++)
2512 txq_deinit(mp->txq + i);
2517 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2519 struct mv643xx_eth_private *mp = netdev_priv(dev);
2522 if (mp->phy == NULL)
2525 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2527 mv643xx_adjust_pscr(mp);
2531 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2533 struct mv643xx_eth_private *mp = netdev_priv(dev);
2535 if (new_mtu < 64 || new_mtu > 9500)
2539 mv643xx_eth_recalc_skb_size(mp);
2540 tx_set_rate(mp, 1000000000, 16777216);
2542 if (!netif_running(dev))
2546 * Stop and then re-open the interface. This will allocate RX
2547 * skbs of the new MTU.
2548 * There is a possible danger that the open will not succeed,
2549 * due to memory being full.
2551 mv643xx_eth_stop(dev);
2552 if (mv643xx_eth_open(dev)) {
2554 "fatal error on re-opening device after MTU change\n");
2560 static void tx_timeout_task(struct work_struct *ugly)
2562 struct mv643xx_eth_private *mp;
2564 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2565 if (netif_running(mp->dev)) {
2566 netif_tx_stop_all_queues(mp->dev);
2569 netif_tx_wake_all_queues(mp->dev);
2573 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2575 struct mv643xx_eth_private *mp = netdev_priv(dev);
2577 netdev_info(dev, "tx timeout\n");
2579 schedule_work(&mp->tx_timeout_task);
2582 #ifdef CONFIG_NET_POLL_CONTROLLER
2583 static void mv643xx_eth_netpoll(struct net_device *dev)
2585 struct mv643xx_eth_private *mp = netdev_priv(dev);
2587 wrlp(mp, INT_MASK, 0x00000000);
2590 mv643xx_eth_irq(dev->irq, dev);
2592 wrlp(mp, INT_MASK, mp->int_mask);
2597 /* platform glue ************************************************************/
2599 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2600 const struct mbus_dram_target_info *dram)
2602 void __iomem *base = msp->base;
2607 for (i = 0; i < 6; i++) {
2608 writel(0, base + WINDOW_BASE(i));
2609 writel(0, base + WINDOW_SIZE(i));
2611 writel(0, base + WINDOW_REMAP_HIGH(i));
2617 for (i = 0; i < dram->num_cs; i++) {
2618 const struct mbus_dram_window *cs = dram->cs + i;
2620 writel((cs->base & 0xffff0000) |
2621 (cs->mbus_attr << 8) |
2622 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2623 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2625 win_enable &= ~(1 << i);
2626 win_protect |= 3 << (2 * i);
2629 writel(win_enable, base + WINDOW_BAR_ENABLE);
2630 msp->win_protect = win_protect;
2633 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2636 * Check whether we have a 14-bit coal limit field in bits
2637 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2638 * SDMA config register.
2640 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2641 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2642 msp->extended_rx_coal_limit = 1;
2644 msp->extended_rx_coal_limit = 0;
2647 * Check whether the MAC supports TX rate control, and if
2648 * yes, whether its associated registers are in the old or
2651 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2652 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2653 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2655 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2656 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2657 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2659 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2663 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2665 static int mv643xx_eth_version_printed;
2666 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2667 struct mv643xx_eth_shared_private *msp;
2668 const struct mbus_dram_target_info *dram;
2669 struct resource *res;
2672 if (!mv643xx_eth_version_printed++)
2673 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2674 mv643xx_eth_driver_version);
2677 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2682 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
2686 msp->base = ioremap(res->start, resource_size(res));
2687 if (msp->base == NULL)
2691 * Set up and register SMI bus.
2693 if (pd == NULL || pd->shared_smi == NULL) {
2694 msp->smi_bus = mdiobus_alloc();
2695 if (msp->smi_bus == NULL)
2698 msp->smi_bus->priv = msp;
2699 msp->smi_bus->name = "mv643xx_eth smi";
2700 msp->smi_bus->read = smi_bus_read;
2701 msp->smi_bus->write = smi_bus_write,
2702 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
2703 pdev->name, pdev->id);
2704 msp->smi_bus->parent = &pdev->dev;
2705 msp->smi_bus->phy_mask = 0xffffffff;
2706 if (mdiobus_register(msp->smi_bus) < 0)
2707 goto out_free_mii_bus;
2710 msp->smi = platform_get_drvdata(pd->shared_smi);
2713 msp->err_interrupt = NO_IRQ;
2714 init_waitqueue_head(&msp->smi_busy_wait);
2717 * Check whether the error interrupt is hooked up.
2719 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2723 err = request_irq(res->start, mv643xx_eth_err_irq,
2724 IRQF_SHARED, "mv643xx_eth", msp);
2726 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2727 msp->err_interrupt = res->start;
2732 * (Re-)program MBUS remapping windows if we are asked to.
2734 dram = mv_mbus_dram_info();
2736 mv643xx_eth_conf_mbus_windows(msp, dram);
2738 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2739 pd->tx_csum_limit : 9 * 1024;
2740 infer_hw_params(msp);
2742 platform_set_drvdata(pdev, msp);
2747 mdiobus_free(msp->smi_bus);
2756 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2758 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2759 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2761 if (pd == NULL || pd->shared_smi == NULL) {
2762 mdiobus_unregister(msp->smi_bus);
2763 mdiobus_free(msp->smi_bus);
2765 if (msp->err_interrupt != NO_IRQ)
2766 free_irq(msp->err_interrupt, msp);
2773 static struct platform_driver mv643xx_eth_shared_driver = {
2774 .probe = mv643xx_eth_shared_probe,
2775 .remove = mv643xx_eth_shared_remove,
2777 .name = MV643XX_ETH_SHARED_NAME,
2778 .owner = THIS_MODULE,
2782 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2784 int addr_shift = 5 * mp->port_num;
2787 data = rdl(mp, PHY_ADDR);
2788 data &= ~(0x1f << addr_shift);
2789 data |= (phy_addr & 0x1f) << addr_shift;
2790 wrl(mp, PHY_ADDR, data);
2793 static int phy_addr_get(struct mv643xx_eth_private *mp)
2797 data = rdl(mp, PHY_ADDR);
2799 return (data >> (5 * mp->port_num)) & 0x1f;
2802 static void set_params(struct mv643xx_eth_private *mp,
2803 struct mv643xx_eth_platform_data *pd)
2805 struct net_device *dev = mp->dev;
2807 if (is_valid_ether_addr(pd->mac_addr))
2808 memcpy(dev->dev_addr, pd->mac_addr, 6);
2810 uc_addr_get(mp, dev->dev_addr);
2812 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2813 if (pd->rx_queue_size)
2814 mp->rx_ring_size = pd->rx_queue_size;
2815 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2816 mp->rx_desc_sram_size = pd->rx_sram_size;
2818 mp->rxq_count = pd->rx_queue_count ? : 1;
2820 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2821 if (pd->tx_queue_size)
2822 mp->tx_ring_size = pd->tx_queue_size;
2823 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2824 mp->tx_desc_sram_size = pd->tx_sram_size;
2826 mp->txq_count = pd->tx_queue_count ? : 1;
2829 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2832 struct mii_bus *bus = mp->shared->smi->smi_bus;
2833 struct phy_device *phydev;
2838 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2839 start = phy_addr_get(mp) & 0x1f;
2842 start = phy_addr & 0x1f;
2847 for (i = 0; i < num; i++) {
2848 int addr = (start + i) & 0x1f;
2850 if (bus->phy_map[addr] == NULL)
2851 mdiobus_scan(bus, addr);
2853 if (phydev == NULL) {
2854 phydev = bus->phy_map[addr];
2856 phy_addr_set(mp, addr);
2863 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2865 struct phy_device *phy = mp->phy;
2869 phy_attach(mp->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_GMII);
2872 phy->autoneg = AUTONEG_ENABLE;
2875 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2877 phy->autoneg = AUTONEG_DISABLE;
2878 phy->advertising = 0;
2880 phy->duplex = duplex;
2882 phy_start_aneg(phy);
2885 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2889 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2890 if (pscr & SERIAL_PORT_ENABLE) {
2891 pscr &= ~SERIAL_PORT_ENABLE;
2892 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2895 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2896 if (mp->phy == NULL) {
2897 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2898 if (speed == SPEED_1000)
2899 pscr |= SET_GMII_SPEED_TO_1000;
2900 else if (speed == SPEED_100)
2901 pscr |= SET_MII_SPEED_TO_100;
2903 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2905 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2906 if (duplex == DUPLEX_FULL)
2907 pscr |= SET_FULL_DUPLEX_MODE;
2910 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2913 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2914 .ndo_open = mv643xx_eth_open,
2915 .ndo_stop = mv643xx_eth_stop,
2916 .ndo_start_xmit = mv643xx_eth_xmit,
2917 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2918 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2919 .ndo_validate_addr = eth_validate_addr,
2920 .ndo_do_ioctl = mv643xx_eth_ioctl,
2921 .ndo_change_mtu = mv643xx_eth_change_mtu,
2922 .ndo_set_features = mv643xx_eth_set_features,
2923 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2924 .ndo_get_stats = mv643xx_eth_get_stats,
2925 #ifdef CONFIG_NET_POLL_CONTROLLER
2926 .ndo_poll_controller = mv643xx_eth_netpoll,
2930 static int mv643xx_eth_probe(struct platform_device *pdev)
2932 struct mv643xx_eth_platform_data *pd;
2933 struct mv643xx_eth_private *mp;
2934 struct net_device *dev;
2935 struct resource *res;
2938 pd = pdev->dev.platform_data;
2940 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2944 if (pd->shared == NULL) {
2945 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2949 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2953 mp = netdev_priv(dev);
2954 platform_set_drvdata(pdev, mp);
2956 mp->shared = platform_get_drvdata(pd->shared);
2957 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2958 mp->port_num = pd->port_number;
2963 * Start with a default rate, and if there is a clock, allow
2964 * it to override the default.
2966 mp->t_clk = 133000000;
2967 #if defined(CONFIG_HAVE_CLK)
2968 mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
2969 if (!IS_ERR(mp->clk)) {
2970 clk_prepare_enable(mp->clk);
2971 mp->t_clk = clk_get_rate(mp->clk);
2975 netif_set_real_num_tx_queues(dev, mp->txq_count);
2976 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2978 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2979 mp->phy = phy_scan(mp, pd->phy_addr);
2981 if (mp->phy != NULL)
2982 phy_init(mp, pd->speed, pd->duplex);
2984 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2986 init_pscr(mp, pd->speed, pd->duplex);
2989 mib_counters_clear(mp);
2991 init_timer(&mp->mib_counters_timer);
2992 mp->mib_counters_timer.data = (unsigned long)mp;
2993 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2994 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2995 add_timer(&mp->mib_counters_timer);
2997 spin_lock_init(&mp->mib_counters_lock);
2999 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3001 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
3003 init_timer(&mp->rx_oom);
3004 mp->rx_oom.data = (unsigned long)mp;
3005 mp->rx_oom.function = oom_timer_wrapper;
3008 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3010 dev->irq = res->start;
3012 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3014 dev->watchdog_timeo = 2 * HZ;
3017 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
3018 NETIF_F_RXCSUM | NETIF_F_LRO;
3019 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3020 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
3022 dev->priv_flags |= IFF_UNICAST_FLT;
3024 SET_NETDEV_DEV(dev, &pdev->dev);
3026 if (mp->shared->win_protect)
3027 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3029 netif_carrier_off(dev);
3031 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3033 set_rx_coal(mp, 250);
3036 err = register_netdev(dev);
3040 netdev_notice(dev, "port %d with MAC address %pM\n",
3041 mp->port_num, dev->dev_addr);
3043 if (mp->tx_desc_sram_size > 0)
3044 netdev_notice(dev, "configured with sram\n");
3049 #if defined(CONFIG_HAVE_CLK)
3050 if (!IS_ERR(mp->clk)) {
3051 clk_disable_unprepare(mp->clk);
3060 static int mv643xx_eth_remove(struct platform_device *pdev)
3062 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3064 unregister_netdev(mp->dev);
3065 if (mp->phy != NULL)
3066 phy_detach(mp->phy);
3067 cancel_work_sync(&mp->tx_timeout_task);
3069 #if defined(CONFIG_HAVE_CLK)
3070 if (!IS_ERR(mp->clk)) {
3071 clk_disable_unprepare(mp->clk);
3076 free_netdev(mp->dev);
3078 platform_set_drvdata(pdev, NULL);
3083 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3085 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3087 /* Mask all interrupts on ethernet port */
3088 wrlp(mp, INT_MASK, 0);
3091 if (netif_running(mp->dev))
3095 static struct platform_driver mv643xx_eth_driver = {
3096 .probe = mv643xx_eth_probe,
3097 .remove = mv643xx_eth_remove,
3098 .shutdown = mv643xx_eth_shutdown,
3100 .name = MV643XX_ETH_NAME,
3101 .owner = THIS_MODULE,
3105 static int __init mv643xx_eth_init_module(void)
3109 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3111 rc = platform_driver_register(&mv643xx_eth_driver);
3113 platform_driver_unregister(&mv643xx_eth_shared_driver);
3118 module_init(mv643xx_eth_init_module);
3120 static void __exit mv643xx_eth_cleanup_module(void)
3122 platform_driver_unregister(&mv643xx_eth_driver);
3123 platform_driver_unregister(&mv643xx_eth_shared_driver);
3125 module_exit(mv643xx_eth_cleanup_module);
3127 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3128 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3129 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3130 MODULE_LICENSE("GPL");
3131 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3132 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);