2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41 #include <linux/init.h>
42 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
66 #include <linux/of_mdio.h>
68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
69 static char mv643xx_eth_driver_version[] = "1.4";
73 * Registers shared between all ports.
75 #define PHY_ADDR 0x0000
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define PORT_SERIAL_CONTROL1 0x004c
123 #define CLK125_BYPASS_EN 0x00000010
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
153 * Misc per-port registers.
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
162 * SDMA configuration register default value.
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
173 TX_BURST_SIZE_4_64BIT)
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 512
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
186 #define TSO_HEADER_SIZE 128
188 /* Max number of allowed TCP segments for software TSO */
189 #define MV643XX_MAX_TSO_SEGS 100
190 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
192 #define IS_TSO_HEADER(txq, addr) \
193 ((addr >= txq->tso_hdrs_dma) && \
194 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
196 #define DESC_DMA_MAP_SINGLE 0
197 #define DESC_DMA_MAP_PAGE 1
202 #if defined(__BIG_ENDIAN)
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u16 buf_size; /* Buffer size */
206 u32 cmd_sts; /* Descriptor command status */
207 u32 next_desc_ptr; /* Next descriptor pointer */
208 u32 buf_ptr; /* Descriptor buffer pointer */
212 u16 byte_cnt; /* buffer byte count */
213 u16 l4i_chk; /* CPU provided TCP checksum */
214 u32 cmd_sts; /* Command/status field */
215 u32 next_desc_ptr; /* Pointer to next descriptor */
216 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 #elif defined(__LITTLE_ENDIAN)
220 u32 cmd_sts; /* Descriptor command status */
221 u16 buf_size; /* Buffer size */
222 u16 byte_cnt; /* Descriptor buffer byte count */
223 u32 buf_ptr; /* Descriptor buffer pointer */
224 u32 next_desc_ptr; /* Next descriptor pointer */
228 u32 cmd_sts; /* Command/status field */
229 u16 l4i_chk; /* CPU provided TCP checksum */
230 u16 byte_cnt; /* buffer byte count */
231 u32 buf_ptr; /* pointer to buffer for this descriptor*/
232 u32 next_desc_ptr; /* Pointer to next descriptor */
235 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
238 /* RX & TX descriptor command */
239 #define BUFFER_OWNED_BY_DMA 0x80000000
241 /* RX & TX descriptor status */
242 #define ERROR_SUMMARY 0x00000001
244 /* RX descriptor status */
245 #define LAYER_4_CHECKSUM_OK 0x40000000
246 #define RX_ENABLE_INTERRUPT 0x20000000
247 #define RX_FIRST_DESC 0x08000000
248 #define RX_LAST_DESC 0x04000000
249 #define RX_IP_HDR_OK 0x02000000
250 #define RX_PKT_IS_IPV4 0x01000000
251 #define RX_PKT_IS_ETHERNETV2 0x00800000
252 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
253 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
254 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
256 /* TX descriptor command */
257 #define TX_ENABLE_INTERRUPT 0x00800000
258 #define GEN_CRC 0x00400000
259 #define TX_FIRST_DESC 0x00200000
260 #define TX_LAST_DESC 0x00100000
261 #define ZERO_PADDING 0x00080000
262 #define GEN_IP_V4_CHECKSUM 0x00040000
263 #define GEN_TCP_UDP_CHECKSUM 0x00020000
264 #define UDP_FRAME 0x00010000
265 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
266 #define GEN_TCP_UDP_CHK_FULL 0x00000400
267 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
269 #define TX_IHL_SHIFT 11
272 /* global *******************************************************************/
273 struct mv643xx_eth_shared_private {
275 * Ethernet controller base address.
280 * Per-port MBUS window access register value.
285 * Hardware-specific parameters.
287 int extended_rx_coal_limit;
293 #define TX_BW_CONTROL_ABSENT 0
294 #define TX_BW_CONTROL_OLD_LAYOUT 1
295 #define TX_BW_CONTROL_NEW_LAYOUT 2
297 static int mv643xx_eth_open(struct net_device *dev);
298 static int mv643xx_eth_stop(struct net_device *dev);
301 /* per-port *****************************************************************/
302 struct mib_counters {
303 u64 good_octets_received;
304 u32 bad_octets_received;
305 u32 internal_mac_transmit_err;
306 u32 good_frames_received;
307 u32 bad_frames_received;
308 u32 broadcast_frames_received;
309 u32 multicast_frames_received;
310 u32 frames_64_octets;
311 u32 frames_65_to_127_octets;
312 u32 frames_128_to_255_octets;
313 u32 frames_256_to_511_octets;
314 u32 frames_512_to_1023_octets;
315 u32 frames_1024_to_max_octets;
316 u64 good_octets_sent;
317 u32 good_frames_sent;
318 u32 excessive_collision;
319 u32 multicast_frames_sent;
320 u32 broadcast_frames_sent;
321 u32 unrec_mac_control_received;
323 u32 good_fc_received;
325 u32 undersize_received;
326 u32 fragments_received;
327 u32 oversize_received;
329 u32 mac_receive_error;
333 /* Non MIB hardware counters */
347 struct rx_desc *rx_desc_area;
348 dma_addr_t rx_desc_dma;
349 int rx_desc_area_size;
350 struct sk_buff **rx_skb;
362 int tx_stop_threshold;
363 int tx_wake_threshold;
366 dma_addr_t tso_hdrs_dma;
368 struct tx_desc *tx_desc_area;
369 char *tx_desc_mapping; /* array to track the type of the dma mapping */
370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
373 struct sk_buff_head tx_skb;
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
380 struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
385 struct net_device *dev;
387 struct phy_device *phy;
389 struct timer_list mib_counters_timer;
390 spinlock_t mib_counters_lock;
391 struct mib_counters mib_counters;
393 struct work_struct tx_timeout_task;
395 struct napi_struct napi;
410 unsigned long rx_desc_sram_addr;
411 int rx_desc_sram_size;
413 struct timer_list rx_oom;
414 struct rx_queue rxq[8];
420 unsigned long tx_desc_sram_addr;
421 int tx_desc_sram_size;
423 struct tx_queue txq[8];
426 * Hardware-specific parameters.
433 /* port register accessors **************************************************/
434 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
436 return readl(mp->shared->base + offset);
439 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
441 return readl(mp->base + offset);
444 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
446 writel(data, mp->shared->base + offset);
449 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
451 writel(data, mp->base + offset);
455 /* rxq/txq helper functions *************************************************/
456 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
458 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
461 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
463 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
466 static void rxq_enable(struct rx_queue *rxq)
468 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
469 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
472 static void rxq_disable(struct rx_queue *rxq)
474 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
475 u8 mask = 1 << rxq->index;
477 wrlp(mp, RXQ_COMMAND, mask << 8);
478 while (rdlp(mp, RXQ_COMMAND) & mask)
482 static void txq_reset_hw_ptr(struct tx_queue *txq)
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
487 addr = (u32)txq->tx_desc_dma;
488 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
489 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
492 static void txq_enable(struct tx_queue *txq)
494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
495 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
498 static void txq_disable(struct tx_queue *txq)
500 struct mv643xx_eth_private *mp = txq_to_mp(txq);
501 u8 mask = 1 << txq->index;
503 wrlp(mp, TXQ_COMMAND, mask << 8);
504 while (rdlp(mp, TXQ_COMMAND) & mask)
508 static void txq_maybe_wake(struct tx_queue *txq)
510 struct mv643xx_eth_private *mp = txq_to_mp(txq);
511 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
513 if (netif_tx_queue_stopped(nq)) {
514 __netif_tx_lock(nq, smp_processor_id());
515 if (txq->tx_desc_count <= txq->tx_wake_threshold)
516 netif_tx_wake_queue(nq);
517 __netif_tx_unlock(nq);
521 static int rxq_process(struct rx_queue *rxq, int budget)
523 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
524 struct net_device_stats *stats = &mp->dev->stats;
528 while (rx < budget && rxq->rx_desc_count) {
529 struct rx_desc *rx_desc;
530 unsigned int cmd_sts;
534 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
536 cmd_sts = rx_desc->cmd_sts;
537 if (cmd_sts & BUFFER_OWNED_BY_DMA)
541 skb = rxq->rx_skb[rxq->rx_curr_desc];
542 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
545 if (rxq->rx_curr_desc == rxq->rx_ring_size)
546 rxq->rx_curr_desc = 0;
548 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
549 rx_desc->buf_size, DMA_FROM_DEVICE);
550 rxq->rx_desc_count--;
553 mp->work_rx_refill |= 1 << rxq->index;
555 byte_cnt = rx_desc->byte_cnt;
560 * Note that the descriptor byte count includes 2 dummy
561 * bytes automatically inserted by the hardware at the
562 * start of the packet (which we don't count), and a 4
563 * byte CRC at the end of the packet (which we do count).
566 stats->rx_bytes += byte_cnt - 2;
569 * In case we received a packet without first / last bits
570 * on, or the error summary bit is set, the packet needs
573 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
574 != (RX_FIRST_DESC | RX_LAST_DESC))
578 * The -4 is for the CRC in the trailer of the
581 skb_put(skb, byte_cnt - 2 - 4);
583 if (cmd_sts & LAYER_4_CHECKSUM_OK)
584 skb->ip_summed = CHECKSUM_UNNECESSARY;
585 skb->protocol = eth_type_trans(skb, mp->dev);
587 napi_gro_receive(&mp->napi, skb);
594 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
595 (RX_FIRST_DESC | RX_LAST_DESC)) {
598 "received packet spanning multiple descriptors\n");
601 if (cmd_sts & ERROR_SUMMARY)
608 mp->work_rx &= ~(1 << rxq->index);
613 static int rxq_refill(struct rx_queue *rxq, int budget)
615 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
619 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
622 struct rx_desc *rx_desc;
625 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
633 skb_reserve(skb, SKB_DMA_REALIGN);
636 rxq->rx_desc_count++;
638 rx = rxq->rx_used_desc++;
639 if (rxq->rx_used_desc == rxq->rx_ring_size)
640 rxq->rx_used_desc = 0;
642 rx_desc = rxq->rx_desc_area + rx;
644 size = skb_end_pointer(skb) - skb->data;
645 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
648 rx_desc->buf_size = size;
649 rxq->rx_skb[rx] = skb;
651 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
655 * The hardware automatically prepends 2 bytes of
656 * dummy data to each received packet, so that the
657 * IP header ends up 16-byte aligned.
662 if (refilled < budget)
663 mp->work_rx_refill &= ~(1 << rxq->index);
670 /* tx ***********************************************************************/
671 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
675 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
676 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
678 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
685 static inline __be16 sum16_as_be(__sum16 sum)
687 return (__force __be16)sum;
690 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
691 u16 *l4i_chk, u32 *command, int length)
696 if (skb->ip_summed == CHECKSUM_PARTIAL) {
700 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
701 skb->protocol != htons(ETH_P_8021Q));
703 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
704 tag_bytes = hdr_len - ETH_HLEN;
706 if (length - hdr_len > mp->shared->tx_csum_limit ||
707 unlikely(tag_bytes & ~12)) {
708 ret = skb_checksum_help(skb);
715 cmd |= MAC_HDR_EXTRA_4_BYTES;
717 cmd |= MAC_HDR_EXTRA_8_BYTES;
719 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
721 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
723 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
724 * it seems we don't need to pass the initial checksum. */
725 switch (ip_hdr(skb)->protocol) {
734 WARN(1, "protocol not supported");
738 /* Errata BTS #50, IHL must be 5 if no HW checksum */
739 cmd |= 5 << TX_IHL_SHIFT;
746 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
747 struct sk_buff *skb, char *data, int length,
748 bool last_tcp, bool is_last)
752 struct tx_desc *desc;
754 tx_index = txq->tx_curr_desc++;
755 if (txq->tx_curr_desc == txq->tx_ring_size)
756 txq->tx_curr_desc = 0;
757 desc = &txq->tx_desc_area[tx_index];
758 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
761 desc->byte_cnt = length;
763 if (length <= 8 && (uintptr_t)data & 0x7) {
764 /* Copy unaligned small data fragment to TSO header data area */
765 memcpy(txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE,
767 desc->buf_ptr = txq->tso_hdrs_dma
768 + txq->tx_curr_desc * TSO_HEADER_SIZE;
770 /* Alignment is okay, map buffer and hand off to hardware */
771 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
772 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
773 length, DMA_TO_DEVICE);
774 if (unlikely(dma_mapping_error(dev->dev.parent,
776 WARN(1, "dma_map_single failed!\n");
781 cmd_sts = BUFFER_OWNED_BY_DMA;
783 /* last descriptor in the TCP packet */
784 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
785 /* last descriptor in SKB */
787 cmd_sts |= TX_ENABLE_INTERRUPT;
789 desc->cmd_sts = cmd_sts;
794 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length)
796 struct mv643xx_eth_private *mp = txq_to_mp(txq);
797 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
799 struct tx_desc *desc;
804 tx_index = txq->tx_curr_desc;
805 desc = &txq->tx_desc_area[tx_index];
807 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
809 WARN(1, "failed to prepare checksum!");
811 /* Should we set this? Can't use the value from skb_tx_csum()
812 * as it's not the correct initial L4 checksum to use. */
815 desc->byte_cnt = hdr_len;
816 desc->buf_ptr = txq->tso_hdrs_dma +
817 txq->tx_curr_desc * TSO_HEADER_SIZE;
818 desc->cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
822 if (txq->tx_curr_desc == txq->tx_ring_size)
823 txq->tx_curr_desc = 0;
826 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
827 struct net_device *dev)
829 struct mv643xx_eth_private *mp = txq_to_mp(txq);
830 int total_len, data_left, ret;
833 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
835 /* Count needed descriptors */
836 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
837 netdev_dbg(dev, "not enough descriptors for TSO!\n");
841 /* Initialize the TSO handler, and prepare the first payload */
842 tso_start(skb, &tso);
844 total_len = skb->len - hdr_len;
845 while (total_len > 0) {
848 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
849 total_len -= data_left;
852 /* prepare packet headers: MAC + IP + TCP */
853 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
854 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
855 txq_put_hdr_tso(skb, txq, data_left);
857 while (data_left > 0) {
861 size = min_t(int, tso.size, data_left);
862 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
868 tso_build_data(skb, &tso, size);
872 __skb_queue_tail(&txq->tx_skb, skb);
873 skb_tx_timestamp(skb);
875 /* clear TX_END status */
876 mp->work_tx_end &= ~(1 << txq->index);
878 /* ensure all descriptors are written before poking hardware */
881 txq->tx_desc_count += desc_count;
884 /* TODO: Release all used data descriptors; header descriptors must not
890 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
892 struct mv643xx_eth_private *mp = txq_to_mp(txq);
893 int nr_frags = skb_shinfo(skb)->nr_frags;
896 for (frag = 0; frag < nr_frags; frag++) {
897 skb_frag_t *this_frag;
899 struct tx_desc *desc;
901 this_frag = &skb_shinfo(skb)->frags[frag];
902 tx_index = txq->tx_curr_desc++;
903 if (txq->tx_curr_desc == txq->tx_ring_size)
904 txq->tx_curr_desc = 0;
905 desc = &txq->tx_desc_area[tx_index];
906 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
909 * The last fragment will generate an interrupt
910 * which will free the skb on TX completion.
912 if (frag == nr_frags - 1) {
913 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
914 ZERO_PADDING | TX_LAST_DESC |
917 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
921 desc->byte_cnt = skb_frag_size(this_frag);
922 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
923 this_frag, 0, desc->byte_cnt,
928 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
929 struct net_device *dev)
931 struct mv643xx_eth_private *mp = txq_to_mp(txq);
932 int nr_frags = skb_shinfo(skb)->nr_frags;
934 struct tx_desc *desc;
942 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
944 netdev_err(dev, "tx queue full?!\n");
948 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
951 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
953 tx_index = txq->tx_curr_desc++;
954 if (txq->tx_curr_desc == txq->tx_ring_size)
955 txq->tx_curr_desc = 0;
956 desc = &txq->tx_desc_area[tx_index];
957 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
960 txq_submit_frag_skb(txq, skb);
961 length = skb_headlen(skb);
963 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
967 desc->l4i_chk = l4i_chk;
968 desc->byte_cnt = length;
969 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
970 length, DMA_TO_DEVICE);
972 __skb_queue_tail(&txq->tx_skb, skb);
974 skb_tx_timestamp(skb);
976 /* ensure all other descriptors are written before first cmd_sts */
978 desc->cmd_sts = cmd_sts;
980 /* clear TX_END status */
981 mp->work_tx_end &= ~(1 << txq->index);
983 /* ensure all descriptors are written before poking hardware */
987 txq->tx_desc_count += nr_frags + 1;
992 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
994 struct mv643xx_eth_private *mp = netdev_priv(dev);
995 int length, queue, ret;
996 struct tx_queue *txq;
997 struct netdev_queue *nq;
999 queue = skb_get_queue_mapping(skb);
1000 txq = mp->txq + queue;
1001 nq = netdev_get_tx_queue(dev, queue);
1003 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1004 netdev_printk(KERN_DEBUG, dev,
1005 "failed to linearize skb with tiny unaligned fragment\n");
1006 return NETDEV_TX_BUSY;
1011 if (skb_is_gso(skb))
1012 ret = txq_submit_tso(txq, skb, dev);
1014 ret = txq_submit_skb(txq, skb, dev);
1016 txq->tx_bytes += length;
1019 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1020 netif_tx_stop_queue(nq);
1023 dev_kfree_skb_any(skb);
1026 return NETDEV_TX_OK;
1030 /* tx napi ******************************************************************/
1031 static void txq_kick(struct tx_queue *txq)
1033 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1034 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1038 __netif_tx_lock(nq, smp_processor_id());
1040 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1043 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1044 expected_ptr = (u32)txq->tx_desc_dma +
1045 txq->tx_curr_desc * sizeof(struct tx_desc);
1047 if (hw_desc_ptr != expected_ptr)
1051 __netif_tx_unlock(nq);
1053 mp->work_tx_end &= ~(1 << txq->index);
1056 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1058 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1059 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1062 __netif_tx_lock_bh(nq);
1065 while (reclaimed < budget && txq->tx_desc_count > 0) {
1067 struct tx_desc *desc;
1071 tx_index = txq->tx_used_desc;
1072 desc = &txq->tx_desc_area[tx_index];
1073 desc_dma_map = txq->tx_desc_mapping[tx_index];
1075 cmd_sts = desc->cmd_sts;
1077 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1080 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1083 txq->tx_used_desc = tx_index + 1;
1084 if (txq->tx_used_desc == txq->tx_ring_size)
1085 txq->tx_used_desc = 0;
1088 txq->tx_desc_count--;
1090 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1092 if (desc_dma_map == DESC_DMA_MAP_PAGE)
1093 dma_unmap_page(mp->dev->dev.parent,
1098 dma_unmap_single(mp->dev->dev.parent,
1104 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1105 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1111 if (cmd_sts & ERROR_SUMMARY) {
1112 netdev_info(mp->dev, "tx error\n");
1113 mp->dev->stats.tx_errors++;
1118 __netif_tx_unlock_bh(nq);
1120 if (reclaimed < budget)
1121 mp->work_tx &= ~(1 << txq->index);
1127 /* tx rate control **********************************************************/
1129 * Set total maximum TX rate (shared by all TX queues for this port)
1130 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1132 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1138 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1139 if (token_rate > 1023)
1142 mtu = (mp->dev->mtu + 255) >> 8;
1146 bucket_size = (burst + 255) >> 8;
1147 if (bucket_size > 65535)
1148 bucket_size = 65535;
1150 switch (mp->shared->tx_bw_control) {
1151 case TX_BW_CONTROL_OLD_LAYOUT:
1152 wrlp(mp, TX_BW_RATE, token_rate);
1153 wrlp(mp, TX_BW_MTU, mtu);
1154 wrlp(mp, TX_BW_BURST, bucket_size);
1156 case TX_BW_CONTROL_NEW_LAYOUT:
1157 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1158 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1159 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1164 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1166 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1170 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1171 if (token_rate > 1023)
1174 bucket_size = (burst + 255) >> 8;
1175 if (bucket_size > 65535)
1176 bucket_size = 65535;
1178 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1179 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1182 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1184 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1189 * Turn on fixed priority mode.
1192 switch (mp->shared->tx_bw_control) {
1193 case TX_BW_CONTROL_OLD_LAYOUT:
1194 off = TXQ_FIX_PRIO_CONF;
1196 case TX_BW_CONTROL_NEW_LAYOUT:
1197 off = TXQ_FIX_PRIO_CONF_MOVED;
1202 val = rdlp(mp, off);
1203 val |= 1 << txq->index;
1209 /* mii management interface *************************************************/
1210 static void mv643xx_eth_adjust_link(struct net_device *dev)
1212 struct mv643xx_eth_private *mp = netdev_priv(dev);
1213 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1214 u32 autoneg_disable = FORCE_LINK_PASS |
1215 DISABLE_AUTO_NEG_SPEED_GMII |
1216 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1217 DISABLE_AUTO_NEG_FOR_DUPLEX;
1219 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1220 /* enable auto negotiation */
1221 pscr &= ~autoneg_disable;
1225 pscr |= autoneg_disable;
1227 if (mp->phy->speed == SPEED_1000) {
1228 /* force gigabit, half duplex not supported */
1229 pscr |= SET_GMII_SPEED_TO_1000;
1230 pscr |= SET_FULL_DUPLEX_MODE;
1234 pscr &= ~SET_GMII_SPEED_TO_1000;
1236 if (mp->phy->speed == SPEED_100)
1237 pscr |= SET_MII_SPEED_TO_100;
1239 pscr &= ~SET_MII_SPEED_TO_100;
1241 if (mp->phy->duplex == DUPLEX_FULL)
1242 pscr |= SET_FULL_DUPLEX_MODE;
1244 pscr &= ~SET_FULL_DUPLEX_MODE;
1247 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1250 /* statistics ***************************************************************/
1251 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1253 struct mv643xx_eth_private *mp = netdev_priv(dev);
1254 struct net_device_stats *stats = &dev->stats;
1255 unsigned long tx_packets = 0;
1256 unsigned long tx_bytes = 0;
1257 unsigned long tx_dropped = 0;
1260 for (i = 0; i < mp->txq_count; i++) {
1261 struct tx_queue *txq = mp->txq + i;
1263 tx_packets += txq->tx_packets;
1264 tx_bytes += txq->tx_bytes;
1265 tx_dropped += txq->tx_dropped;
1268 stats->tx_packets = tx_packets;
1269 stats->tx_bytes = tx_bytes;
1270 stats->tx_dropped = tx_dropped;
1275 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1277 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1280 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1284 for (i = 0; i < 0x80; i += 4)
1287 /* Clear non MIB hw counters also */
1288 rdlp(mp, RX_DISCARD_FRAME_CNT);
1289 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1292 static void mib_counters_update(struct mv643xx_eth_private *mp)
1294 struct mib_counters *p = &mp->mib_counters;
1296 spin_lock_bh(&mp->mib_counters_lock);
1297 p->good_octets_received += mib_read(mp, 0x00);
1298 p->bad_octets_received += mib_read(mp, 0x08);
1299 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1300 p->good_frames_received += mib_read(mp, 0x10);
1301 p->bad_frames_received += mib_read(mp, 0x14);
1302 p->broadcast_frames_received += mib_read(mp, 0x18);
1303 p->multicast_frames_received += mib_read(mp, 0x1c);
1304 p->frames_64_octets += mib_read(mp, 0x20);
1305 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1306 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1307 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1308 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1309 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1310 p->good_octets_sent += mib_read(mp, 0x38);
1311 p->good_frames_sent += mib_read(mp, 0x40);
1312 p->excessive_collision += mib_read(mp, 0x44);
1313 p->multicast_frames_sent += mib_read(mp, 0x48);
1314 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1315 p->unrec_mac_control_received += mib_read(mp, 0x50);
1316 p->fc_sent += mib_read(mp, 0x54);
1317 p->good_fc_received += mib_read(mp, 0x58);
1318 p->bad_fc_received += mib_read(mp, 0x5c);
1319 p->undersize_received += mib_read(mp, 0x60);
1320 p->fragments_received += mib_read(mp, 0x64);
1321 p->oversize_received += mib_read(mp, 0x68);
1322 p->jabber_received += mib_read(mp, 0x6c);
1323 p->mac_receive_error += mib_read(mp, 0x70);
1324 p->bad_crc_event += mib_read(mp, 0x74);
1325 p->collision += mib_read(mp, 0x78);
1326 p->late_collision += mib_read(mp, 0x7c);
1327 /* Non MIB hardware counters */
1328 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1329 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1330 spin_unlock_bh(&mp->mib_counters_lock);
1333 static void mib_counters_timer_wrapper(unsigned long _mp)
1335 struct mv643xx_eth_private *mp = (void *)_mp;
1336 mib_counters_update(mp);
1337 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1341 /* interrupt coalescing *****************************************************/
1343 * Hardware coalescing parameters are set in units of 64 t_clk
1346 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1348 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1350 * In the ->set*() methods, we round the computed register value
1351 * to the nearest integer.
1353 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1355 u32 val = rdlp(mp, SDMA_CONFIG);
1358 if (mp->shared->extended_rx_coal_limit)
1359 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1361 temp = (val & 0x003fff00) >> 8;
1364 do_div(temp, mp->t_clk);
1366 return (unsigned int)temp;
1369 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1374 temp = (u64)usec * mp->t_clk;
1376 do_div(temp, 64000000);
1378 val = rdlp(mp, SDMA_CONFIG);
1379 if (mp->shared->extended_rx_coal_limit) {
1383 val |= (temp & 0x8000) << 10;
1384 val |= (temp & 0x7fff) << 7;
1389 val |= (temp & 0x3fff) << 8;
1391 wrlp(mp, SDMA_CONFIG, val);
1394 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1398 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1400 do_div(temp, mp->t_clk);
1402 return (unsigned int)temp;
1405 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1409 temp = (u64)usec * mp->t_clk;
1411 do_div(temp, 64000000);
1416 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1420 /* ethtool ******************************************************************/
1421 struct mv643xx_eth_stats {
1422 char stat_string[ETH_GSTRING_LEN];
1429 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1430 offsetof(struct net_device, stats.m), -1 }
1432 #define MIBSTAT(m) \
1433 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1434 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1436 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1445 MIBSTAT(good_octets_received),
1446 MIBSTAT(bad_octets_received),
1447 MIBSTAT(internal_mac_transmit_err),
1448 MIBSTAT(good_frames_received),
1449 MIBSTAT(bad_frames_received),
1450 MIBSTAT(broadcast_frames_received),
1451 MIBSTAT(multicast_frames_received),
1452 MIBSTAT(frames_64_octets),
1453 MIBSTAT(frames_65_to_127_octets),
1454 MIBSTAT(frames_128_to_255_octets),
1455 MIBSTAT(frames_256_to_511_octets),
1456 MIBSTAT(frames_512_to_1023_octets),
1457 MIBSTAT(frames_1024_to_max_octets),
1458 MIBSTAT(good_octets_sent),
1459 MIBSTAT(good_frames_sent),
1460 MIBSTAT(excessive_collision),
1461 MIBSTAT(multicast_frames_sent),
1462 MIBSTAT(broadcast_frames_sent),
1463 MIBSTAT(unrec_mac_control_received),
1465 MIBSTAT(good_fc_received),
1466 MIBSTAT(bad_fc_received),
1467 MIBSTAT(undersize_received),
1468 MIBSTAT(fragments_received),
1469 MIBSTAT(oversize_received),
1470 MIBSTAT(jabber_received),
1471 MIBSTAT(mac_receive_error),
1472 MIBSTAT(bad_crc_event),
1474 MIBSTAT(late_collision),
1475 MIBSTAT(rx_discard),
1476 MIBSTAT(rx_overrun),
1480 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1481 struct ethtool_cmd *cmd)
1485 err = phy_read_status(mp->phy);
1487 err = phy_ethtool_gset(mp->phy, cmd);
1490 * The MAC does not support 1000baseT_Half.
1492 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1493 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1499 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1500 struct ethtool_cmd *cmd)
1504 port_status = rdlp(mp, PORT_STATUS);
1506 cmd->supported = SUPPORTED_MII;
1507 cmd->advertising = ADVERTISED_MII;
1508 switch (port_status & PORT_SPEED_MASK) {
1510 ethtool_cmd_speed_set(cmd, SPEED_10);
1512 case PORT_SPEED_100:
1513 ethtool_cmd_speed_set(cmd, SPEED_100);
1515 case PORT_SPEED_1000:
1516 ethtool_cmd_speed_set(cmd, SPEED_1000);
1522 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1523 cmd->port = PORT_MII;
1524 cmd->phy_address = 0;
1525 cmd->transceiver = XCVR_INTERNAL;
1526 cmd->autoneg = AUTONEG_DISABLE;
1534 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1536 struct mv643xx_eth_private *mp = netdev_priv(dev);
1540 phy_ethtool_get_wol(mp->phy, wol);
1544 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1546 struct mv643xx_eth_private *mp = netdev_priv(dev);
1549 if (mp->phy == NULL)
1552 err = phy_ethtool_set_wol(mp->phy, wol);
1553 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1554 * this debugging hint is useful to have.
1556 if (err == -EOPNOTSUPP)
1557 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1562 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1564 struct mv643xx_eth_private *mp = netdev_priv(dev);
1566 if (mp->phy != NULL)
1567 return mv643xx_eth_get_settings_phy(mp, cmd);
1569 return mv643xx_eth_get_settings_phyless(mp, cmd);
1573 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1575 struct mv643xx_eth_private *mp = netdev_priv(dev);
1578 if (mp->phy == NULL)
1582 * The MAC does not support 1000baseT_Half.
1584 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1586 ret = phy_ethtool_sset(mp->phy, cmd);
1588 mv643xx_eth_adjust_link(dev);
1592 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1593 struct ethtool_drvinfo *drvinfo)
1595 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1596 sizeof(drvinfo->driver));
1597 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1598 sizeof(drvinfo->version));
1599 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1600 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1601 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1604 static int mv643xx_eth_nway_reset(struct net_device *dev)
1606 struct mv643xx_eth_private *mp = netdev_priv(dev);
1608 if (mp->phy == NULL)
1611 return genphy_restart_aneg(mp->phy);
1615 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1617 struct mv643xx_eth_private *mp = netdev_priv(dev);
1619 ec->rx_coalesce_usecs = get_rx_coal(mp);
1620 ec->tx_coalesce_usecs = get_tx_coal(mp);
1626 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1628 struct mv643xx_eth_private *mp = netdev_priv(dev);
1630 set_rx_coal(mp, ec->rx_coalesce_usecs);
1631 set_tx_coal(mp, ec->tx_coalesce_usecs);
1637 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1639 struct mv643xx_eth_private *mp = netdev_priv(dev);
1641 er->rx_max_pending = 4096;
1642 er->tx_max_pending = 4096;
1644 er->rx_pending = mp->rx_ring_size;
1645 er->tx_pending = mp->tx_ring_size;
1649 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1651 struct mv643xx_eth_private *mp = netdev_priv(dev);
1653 if (er->rx_mini_pending || er->rx_jumbo_pending)
1656 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1657 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1658 MV643XX_MAX_SKB_DESCS * 2, 4096);
1659 if (mp->tx_ring_size != er->tx_pending)
1660 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1661 mp->tx_ring_size, er->tx_pending);
1663 if (netif_running(dev)) {
1664 mv643xx_eth_stop(dev);
1665 if (mv643xx_eth_open(dev)) {
1667 "fatal error on re-opening device after ring param change\n");
1677 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1679 struct mv643xx_eth_private *mp = netdev_priv(dev);
1680 bool rx_csum = features & NETIF_F_RXCSUM;
1682 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1687 static void mv643xx_eth_get_strings(struct net_device *dev,
1688 uint32_t stringset, uint8_t *data)
1692 if (stringset == ETH_SS_STATS) {
1693 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1694 memcpy(data + i * ETH_GSTRING_LEN,
1695 mv643xx_eth_stats[i].stat_string,
1701 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1702 struct ethtool_stats *stats,
1705 struct mv643xx_eth_private *mp = netdev_priv(dev);
1708 mv643xx_eth_get_stats(dev);
1709 mib_counters_update(mp);
1711 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1712 const struct mv643xx_eth_stats *stat;
1715 stat = mv643xx_eth_stats + i;
1717 if (stat->netdev_off >= 0)
1718 p = ((void *)mp->dev) + stat->netdev_off;
1720 p = ((void *)mp) + stat->mp_off;
1722 data[i] = (stat->sizeof_stat == 8) ?
1723 *(uint64_t *)p : *(uint32_t *)p;
1727 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1729 if (sset == ETH_SS_STATS)
1730 return ARRAY_SIZE(mv643xx_eth_stats);
1735 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1736 .get_settings = mv643xx_eth_get_settings,
1737 .set_settings = mv643xx_eth_set_settings,
1738 .get_drvinfo = mv643xx_eth_get_drvinfo,
1739 .nway_reset = mv643xx_eth_nway_reset,
1740 .get_link = ethtool_op_get_link,
1741 .get_coalesce = mv643xx_eth_get_coalesce,
1742 .set_coalesce = mv643xx_eth_set_coalesce,
1743 .get_ringparam = mv643xx_eth_get_ringparam,
1744 .set_ringparam = mv643xx_eth_set_ringparam,
1745 .get_strings = mv643xx_eth_get_strings,
1746 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1747 .get_sset_count = mv643xx_eth_get_sset_count,
1748 .get_ts_info = ethtool_op_get_ts_info,
1749 .get_wol = mv643xx_eth_get_wol,
1750 .set_wol = mv643xx_eth_set_wol,
1754 /* address handling *********************************************************/
1755 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1757 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1758 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1760 addr[0] = (mac_h >> 24) & 0xff;
1761 addr[1] = (mac_h >> 16) & 0xff;
1762 addr[2] = (mac_h >> 8) & 0xff;
1763 addr[3] = mac_h & 0xff;
1764 addr[4] = (mac_l >> 8) & 0xff;
1765 addr[5] = mac_l & 0xff;
1768 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1770 wrlp(mp, MAC_ADDR_HIGH,
1771 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1772 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1775 static u32 uc_addr_filter_mask(struct net_device *dev)
1777 struct netdev_hw_addr *ha;
1780 if (dev->flags & IFF_PROMISC)
1783 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1784 netdev_for_each_uc_addr(ha, dev) {
1785 if (memcmp(dev->dev_addr, ha->addr, 5))
1787 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1790 nibbles |= 1 << (ha->addr[5] & 0x0f);
1796 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1798 struct mv643xx_eth_private *mp = netdev_priv(dev);
1803 uc_addr_set(mp, dev->dev_addr);
1805 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1807 nibbles = uc_addr_filter_mask(dev);
1809 port_config |= UNICAST_PROMISCUOUS_MODE;
1813 for (i = 0; i < 16; i += 4) {
1814 int off = UNICAST_TABLE(mp->port_num) + i;
1831 wrlp(mp, PORT_CONFIG, port_config);
1834 static int addr_crc(unsigned char *addr)
1839 for (i = 0; i < 6; i++) {
1842 crc = (crc ^ addr[i]) << 8;
1843 for (j = 7; j >= 0; j--) {
1844 if (crc & (0x100 << j))
1852 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1854 struct mv643xx_eth_private *mp = netdev_priv(dev);
1857 struct netdev_hw_addr *ha;
1860 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1865 port_num = mp->port_num;
1866 accept = 0x01010101;
1867 for (i = 0; i < 0x100; i += 4) {
1868 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1869 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1874 mc_spec = kzalloc(0x200, GFP_ATOMIC);
1875 if (mc_spec == NULL)
1877 mc_other = mc_spec + (0x100 >> 2);
1879 netdev_for_each_mc_addr(ha, dev) {
1884 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1889 entry = addr_crc(a);
1892 table[entry >> 2] |= 1 << (8 * (entry & 3));
1895 for (i = 0; i < 0x100; i += 4) {
1896 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1897 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1903 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1905 mv643xx_eth_program_unicast_filter(dev);
1906 mv643xx_eth_program_multicast_filter(dev);
1909 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1911 struct sockaddr *sa = addr;
1913 if (!is_valid_ether_addr(sa->sa_data))
1914 return -EADDRNOTAVAIL;
1916 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1918 netif_addr_lock_bh(dev);
1919 mv643xx_eth_program_unicast_filter(dev);
1920 netif_addr_unlock_bh(dev);
1926 /* rx/tx queue initialisation ***********************************************/
1927 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1929 struct rx_queue *rxq = mp->rxq + index;
1930 struct rx_desc *rx_desc;
1936 rxq->rx_ring_size = mp->rx_ring_size;
1938 rxq->rx_desc_count = 0;
1939 rxq->rx_curr_desc = 0;
1940 rxq->rx_used_desc = 0;
1942 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1944 if (index == 0 && size <= mp->rx_desc_sram_size) {
1945 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1946 mp->rx_desc_sram_size);
1947 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1949 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1950 size, &rxq->rx_desc_dma,
1954 if (rxq->rx_desc_area == NULL) {
1956 "can't allocate rx ring (%d bytes)\n", size);
1959 memset(rxq->rx_desc_area, 0, size);
1961 rxq->rx_desc_area_size = size;
1962 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1964 if (rxq->rx_skb == NULL)
1967 rx_desc = rxq->rx_desc_area;
1968 for (i = 0; i < rxq->rx_ring_size; i++) {
1972 if (nexti == rxq->rx_ring_size)
1975 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1976 nexti * sizeof(struct rx_desc);
1983 if (index == 0 && size <= mp->rx_desc_sram_size)
1984 iounmap(rxq->rx_desc_area);
1986 dma_free_coherent(mp->dev->dev.parent, size,
1994 static void rxq_deinit(struct rx_queue *rxq)
1996 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2001 for (i = 0; i < rxq->rx_ring_size; i++) {
2002 if (rxq->rx_skb[i]) {
2003 dev_kfree_skb(rxq->rx_skb[i]);
2004 rxq->rx_desc_count--;
2008 if (rxq->rx_desc_count) {
2009 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2010 rxq->rx_desc_count);
2013 if (rxq->index == 0 &&
2014 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2015 iounmap(rxq->rx_desc_area);
2017 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2018 rxq->rx_desc_area, rxq->rx_desc_dma);
2023 static int txq_init(struct mv643xx_eth_private *mp, int index)
2025 struct tx_queue *txq = mp->txq + index;
2026 struct tx_desc *tx_desc;
2033 txq->tx_ring_size = mp->tx_ring_size;
2035 /* A queue must always have room for at least one skb.
2036 * Therefore, stop the queue when the free entries reaches
2037 * the maximum number of descriptors per skb.
2039 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2040 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2042 txq->tx_desc_count = 0;
2043 txq->tx_curr_desc = 0;
2044 txq->tx_used_desc = 0;
2046 size = txq->tx_ring_size * sizeof(struct tx_desc);
2048 if (index == 0 && size <= mp->tx_desc_sram_size) {
2049 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2050 mp->tx_desc_sram_size);
2051 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2053 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2054 size, &txq->tx_desc_dma,
2058 if (txq->tx_desc_area == NULL) {
2060 "can't allocate tx ring (%d bytes)\n", size);
2063 memset(txq->tx_desc_area, 0, size);
2065 txq->tx_desc_area_size = size;
2067 tx_desc = txq->tx_desc_area;
2068 for (i = 0; i < txq->tx_ring_size; i++) {
2069 struct tx_desc *txd = tx_desc + i;
2073 if (nexti == txq->tx_ring_size)
2077 txd->next_desc_ptr = txq->tx_desc_dma +
2078 nexti * sizeof(struct tx_desc);
2081 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2083 if (!txq->tx_desc_mapping) {
2085 goto err_free_desc_area;
2088 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2089 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2090 txq->tx_ring_size * TSO_HEADER_SIZE,
2091 &txq->tso_hdrs_dma, GFP_KERNEL);
2092 if (txq->tso_hdrs == NULL) {
2094 goto err_free_desc_mapping;
2096 skb_queue_head_init(&txq->tx_skb);
2100 err_free_desc_mapping:
2101 kfree(txq->tx_desc_mapping);
2103 if (index == 0 && size <= mp->tx_desc_sram_size)
2104 iounmap(txq->tx_desc_area);
2106 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2107 txq->tx_desc_area, txq->tx_desc_dma);
2111 static void txq_deinit(struct tx_queue *txq)
2113 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2116 txq_reclaim(txq, txq->tx_ring_size, 1);
2118 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2120 if (txq->index == 0 &&
2121 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2122 iounmap(txq->tx_desc_area);
2124 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2125 txq->tx_desc_area, txq->tx_desc_dma);
2126 kfree(txq->tx_desc_mapping);
2129 dma_free_coherent(mp->dev->dev.parent,
2130 txq->tx_ring_size * TSO_HEADER_SIZE,
2131 txq->tso_hdrs, txq->tso_hdrs_dma);
2135 /* netdev ops and related ***************************************************/
2136 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2141 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2146 if (int_cause & INT_EXT) {
2147 int_cause &= ~INT_EXT;
2148 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2152 wrlp(mp, INT_CAUSE, ~int_cause);
2153 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2154 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2155 mp->work_rx |= (int_cause & INT_RX) >> 2;
2158 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2159 if (int_cause_ext) {
2160 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2161 if (int_cause_ext & INT_EXT_LINK_PHY)
2163 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2169 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2171 struct net_device *dev = (struct net_device *)dev_id;
2172 struct mv643xx_eth_private *mp = netdev_priv(dev);
2174 if (unlikely(!mv643xx_eth_collect_events(mp)))
2177 wrlp(mp, INT_MASK, 0);
2178 napi_schedule(&mp->napi);
2183 static void handle_link_event(struct mv643xx_eth_private *mp)
2185 struct net_device *dev = mp->dev;
2191 port_status = rdlp(mp, PORT_STATUS);
2192 if (!(port_status & LINK_UP)) {
2193 if (netif_carrier_ok(dev)) {
2196 netdev_info(dev, "link down\n");
2198 netif_carrier_off(dev);
2200 for (i = 0; i < mp->txq_count; i++) {
2201 struct tx_queue *txq = mp->txq + i;
2203 txq_reclaim(txq, txq->tx_ring_size, 1);
2204 txq_reset_hw_ptr(txq);
2210 switch (port_status & PORT_SPEED_MASK) {
2214 case PORT_SPEED_100:
2217 case PORT_SPEED_1000:
2224 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2225 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2227 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2228 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2230 if (!netif_carrier_ok(dev))
2231 netif_carrier_on(dev);
2234 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2236 struct mv643xx_eth_private *mp;
2239 mp = container_of(napi, struct mv643xx_eth_private, napi);
2241 if (unlikely(mp->oom)) {
2243 del_timer(&mp->rx_oom);
2247 while (work_done < budget) {
2252 if (mp->work_link) {
2254 handle_link_event(mp);
2259 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2260 if (likely(!mp->oom))
2261 queue_mask |= mp->work_rx_refill;
2264 if (mv643xx_eth_collect_events(mp))
2269 queue = fls(queue_mask) - 1;
2270 queue_mask = 1 << queue;
2272 work_tbd = budget - work_done;
2276 if (mp->work_tx_end & queue_mask) {
2277 txq_kick(mp->txq + queue);
2278 } else if (mp->work_tx & queue_mask) {
2279 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2280 txq_maybe_wake(mp->txq + queue);
2281 } else if (mp->work_rx & queue_mask) {
2282 work_done += rxq_process(mp->rxq + queue, work_tbd);
2283 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2284 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2290 if (work_done < budget) {
2292 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2293 napi_complete(napi);
2294 wrlp(mp, INT_MASK, mp->int_mask);
2300 static inline void oom_timer_wrapper(unsigned long data)
2302 struct mv643xx_eth_private *mp = (void *)data;
2304 napi_schedule(&mp->napi);
2307 static void port_start(struct mv643xx_eth_private *mp)
2313 * Perform PHY reset, if there is a PHY.
2315 if (mp->phy != NULL) {
2316 struct ethtool_cmd cmd;
2318 mv643xx_eth_get_settings(mp->dev, &cmd);
2319 phy_init_hw(mp->phy);
2320 mv643xx_eth_set_settings(mp->dev, &cmd);
2325 * Configure basic link parameters.
2327 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2329 pscr |= SERIAL_PORT_ENABLE;
2330 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2332 pscr |= DO_NOT_FORCE_LINK_FAIL;
2333 if (mp->phy == NULL)
2334 pscr |= FORCE_LINK_PASS;
2335 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2338 * Configure TX path and queues.
2340 tx_set_rate(mp, 1000000000, 16777216);
2341 for (i = 0; i < mp->txq_count; i++) {
2342 struct tx_queue *txq = mp->txq + i;
2344 txq_reset_hw_ptr(txq);
2345 txq_set_rate(txq, 1000000000, 16777216);
2346 txq_set_fixed_prio_mode(txq);
2350 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2351 * frames to RX queue #0, and include the pseudo-header when
2352 * calculating receive checksums.
2354 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2357 * Treat BPDUs as normal multicasts, and disable partition mode.
2359 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2362 * Add configured unicast addresses to address filter table.
2364 mv643xx_eth_program_unicast_filter(mp->dev);
2367 * Enable the receive queues.
2369 for (i = 0; i < mp->rxq_count; i++) {
2370 struct rx_queue *rxq = mp->rxq + i;
2373 addr = (u32)rxq->rx_desc_dma;
2374 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2375 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2381 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2386 * Reserve 2+14 bytes for an ethernet header (the hardware
2387 * automatically prepends 2 bytes of dummy data to each
2388 * received packet), 16 bytes for up to four VLAN tags, and
2389 * 4 bytes for the trailing FCS -- 36 bytes total.
2391 skb_size = mp->dev->mtu + 36;
2394 * Make sure that the skb size is a multiple of 8 bytes, as
2395 * the lower three bits of the receive descriptor's buffer
2396 * size field are ignored by the hardware.
2398 mp->skb_size = (skb_size + 7) & ~7;
2401 * If NET_SKB_PAD is smaller than a cache line,
2402 * netdev_alloc_skb() will cause skb->data to be misaligned
2403 * to a cache line boundary. If this is the case, include
2404 * some extra space to allow re-aligning the data area.
2406 mp->skb_size += SKB_DMA_REALIGN;
2409 static int mv643xx_eth_open(struct net_device *dev)
2411 struct mv643xx_eth_private *mp = netdev_priv(dev);
2415 wrlp(mp, INT_CAUSE, 0);
2416 wrlp(mp, INT_CAUSE_EXT, 0);
2417 rdlp(mp, INT_CAUSE_EXT);
2419 err = request_irq(dev->irq, mv643xx_eth_irq,
2420 IRQF_SHARED, dev->name, dev);
2422 netdev_err(dev, "can't assign irq\n");
2426 mv643xx_eth_recalc_skb_size(mp);
2428 napi_enable(&mp->napi);
2430 mp->int_mask = INT_EXT;
2432 for (i = 0; i < mp->rxq_count; i++) {
2433 err = rxq_init(mp, i);
2436 rxq_deinit(mp->rxq + i);
2440 rxq_refill(mp->rxq + i, INT_MAX);
2441 mp->int_mask |= INT_RX_0 << i;
2445 mp->rx_oom.expires = jiffies + (HZ / 10);
2446 add_timer(&mp->rx_oom);
2449 for (i = 0; i < mp->txq_count; i++) {
2450 err = txq_init(mp, i);
2453 txq_deinit(mp->txq + i);
2456 mp->int_mask |= INT_TX_END_0 << i;
2459 add_timer(&mp->mib_counters_timer);
2462 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2463 wrlp(mp, INT_MASK, mp->int_mask);
2469 for (i = 0; i < mp->rxq_count; i++)
2470 rxq_deinit(mp->rxq + i);
2472 free_irq(dev->irq, dev);
2477 static void port_reset(struct mv643xx_eth_private *mp)
2482 for (i = 0; i < mp->rxq_count; i++)
2483 rxq_disable(mp->rxq + i);
2484 for (i = 0; i < mp->txq_count; i++)
2485 txq_disable(mp->txq + i);
2488 u32 ps = rdlp(mp, PORT_STATUS);
2490 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2495 /* Reset the Enable bit in the Configuration Register */
2496 data = rdlp(mp, PORT_SERIAL_CONTROL);
2497 data &= ~(SERIAL_PORT_ENABLE |
2498 DO_NOT_FORCE_LINK_FAIL |
2500 wrlp(mp, PORT_SERIAL_CONTROL, data);
2503 static int mv643xx_eth_stop(struct net_device *dev)
2505 struct mv643xx_eth_private *mp = netdev_priv(dev);
2508 wrlp(mp, INT_MASK_EXT, 0x00000000);
2509 wrlp(mp, INT_MASK, 0x00000000);
2512 napi_disable(&mp->napi);
2514 del_timer_sync(&mp->rx_oom);
2516 netif_carrier_off(dev);
2519 free_irq(dev->irq, dev);
2522 mv643xx_eth_get_stats(dev);
2523 mib_counters_update(mp);
2524 del_timer_sync(&mp->mib_counters_timer);
2526 for (i = 0; i < mp->rxq_count; i++)
2527 rxq_deinit(mp->rxq + i);
2528 for (i = 0; i < mp->txq_count; i++)
2529 txq_deinit(mp->txq + i);
2534 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2536 struct mv643xx_eth_private *mp = netdev_priv(dev);
2539 if (mp->phy == NULL)
2542 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2544 mv643xx_eth_adjust_link(dev);
2548 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2550 struct mv643xx_eth_private *mp = netdev_priv(dev);
2552 if (new_mtu < 64 || new_mtu > 9500)
2556 mv643xx_eth_recalc_skb_size(mp);
2557 tx_set_rate(mp, 1000000000, 16777216);
2559 if (!netif_running(dev))
2563 * Stop and then re-open the interface. This will allocate RX
2564 * skbs of the new MTU.
2565 * There is a possible danger that the open will not succeed,
2566 * due to memory being full.
2568 mv643xx_eth_stop(dev);
2569 if (mv643xx_eth_open(dev)) {
2571 "fatal error on re-opening device after MTU change\n");
2577 static void tx_timeout_task(struct work_struct *ugly)
2579 struct mv643xx_eth_private *mp;
2581 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2582 if (netif_running(mp->dev)) {
2583 netif_tx_stop_all_queues(mp->dev);
2586 netif_tx_wake_all_queues(mp->dev);
2590 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2592 struct mv643xx_eth_private *mp = netdev_priv(dev);
2594 netdev_info(dev, "tx timeout\n");
2596 schedule_work(&mp->tx_timeout_task);
2599 #ifdef CONFIG_NET_POLL_CONTROLLER
2600 static void mv643xx_eth_netpoll(struct net_device *dev)
2602 struct mv643xx_eth_private *mp = netdev_priv(dev);
2604 wrlp(mp, INT_MASK, 0x00000000);
2607 mv643xx_eth_irq(dev->irq, dev);
2609 wrlp(mp, INT_MASK, mp->int_mask);
2614 /* platform glue ************************************************************/
2616 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2617 const struct mbus_dram_target_info *dram)
2619 void __iomem *base = msp->base;
2624 for (i = 0; i < 6; i++) {
2625 writel(0, base + WINDOW_BASE(i));
2626 writel(0, base + WINDOW_SIZE(i));
2628 writel(0, base + WINDOW_REMAP_HIGH(i));
2634 for (i = 0; i < dram->num_cs; i++) {
2635 const struct mbus_dram_window *cs = dram->cs + i;
2637 writel((cs->base & 0xffff0000) |
2638 (cs->mbus_attr << 8) |
2639 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2640 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2642 win_enable &= ~(1 << i);
2643 win_protect |= 3 << (2 * i);
2646 writel(win_enable, base + WINDOW_BAR_ENABLE);
2647 msp->win_protect = win_protect;
2650 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2653 * Check whether we have a 14-bit coal limit field in bits
2654 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2655 * SDMA config register.
2657 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2658 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2659 msp->extended_rx_coal_limit = 1;
2661 msp->extended_rx_coal_limit = 0;
2664 * Check whether the MAC supports TX rate control, and if
2665 * yes, whether its associated registers are in the old or
2668 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2669 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2670 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2672 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2673 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2674 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2676 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2680 #if defined(CONFIG_OF)
2681 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2682 { .compatible = "marvell,orion-eth", },
2683 { .compatible = "marvell,kirkwood-eth", },
2686 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2689 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2690 #define mv643xx_eth_property(_np, _name, _v) \
2693 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2697 static struct platform_device *port_platdev[3];
2699 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2700 struct device_node *pnp)
2702 struct platform_device *ppdev;
2703 struct mv643xx_eth_platform_data ppd;
2704 struct resource res;
2705 const char *mac_addr;
2709 memset(&ppd, 0, sizeof(ppd));
2712 memset(&res, 0, sizeof(res));
2713 if (!of_irq_to_resource(pnp, 0, &res)) {
2714 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2718 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2719 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2723 if (ppd.port_number >= 3) {
2724 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2728 while (dev_num < 3 && port_platdev[dev_num])
2732 dev_err(&pdev->dev, "too many ports registered\n");
2736 mac_addr = of_get_mac_address(pnp);
2738 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2740 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2741 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2742 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2743 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2744 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2745 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2747 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2748 if (!ppd.phy_node) {
2749 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2750 of_property_read_u32(pnp, "speed", &ppd.speed);
2751 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2754 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2757 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2758 ppdev->dev.of_node = pnp;
2760 ret = platform_device_add_resources(ppdev, &res, 1);
2764 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2768 ret = platform_device_add(ppdev);
2772 port_platdev[dev_num] = ppdev;
2777 platform_device_put(ppdev);
2781 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2783 struct mv643xx_eth_shared_platform_data *pd;
2784 struct device_node *pnp, *np = pdev->dev.of_node;
2787 /* bail out if not registered from DT */
2791 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2794 pdev->dev.platform_data = pd;
2796 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2798 for_each_available_child_of_node(np, pnp) {
2799 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2806 static void mv643xx_eth_shared_of_remove(void)
2810 for (n = 0; n < 3; n++) {
2811 platform_device_del(port_platdev[n]);
2812 port_platdev[n] = NULL;
2816 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2821 static inline void mv643xx_eth_shared_of_remove(void)
2826 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2828 static int mv643xx_eth_version_printed;
2829 struct mv643xx_eth_shared_platform_data *pd;
2830 struct mv643xx_eth_shared_private *msp;
2831 const struct mbus_dram_target_info *dram;
2832 struct resource *res;
2835 if (!mv643xx_eth_version_printed++)
2836 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2837 mv643xx_eth_driver_version);
2839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2843 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2846 platform_set_drvdata(pdev, msp);
2848 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2849 if (msp->base == NULL)
2852 msp->clk = devm_clk_get(&pdev->dev, NULL);
2853 if (!IS_ERR(msp->clk))
2854 clk_prepare_enable(msp->clk);
2857 * (Re-)program MBUS remapping windows if we are asked to.
2859 dram = mv_mbus_dram_info();
2861 mv643xx_eth_conf_mbus_windows(msp, dram);
2863 ret = mv643xx_eth_shared_of_probe(pdev);
2866 pd = dev_get_platdata(&pdev->dev);
2868 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2869 pd->tx_csum_limit : 9 * 1024;
2870 infer_hw_params(msp);
2875 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2877 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2879 mv643xx_eth_shared_of_remove();
2880 if (!IS_ERR(msp->clk))
2881 clk_disable_unprepare(msp->clk);
2885 static struct platform_driver mv643xx_eth_shared_driver = {
2886 .probe = mv643xx_eth_shared_probe,
2887 .remove = mv643xx_eth_shared_remove,
2889 .name = MV643XX_ETH_SHARED_NAME,
2890 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2894 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2896 int addr_shift = 5 * mp->port_num;
2899 data = rdl(mp, PHY_ADDR);
2900 data &= ~(0x1f << addr_shift);
2901 data |= (phy_addr & 0x1f) << addr_shift;
2902 wrl(mp, PHY_ADDR, data);
2905 static int phy_addr_get(struct mv643xx_eth_private *mp)
2909 data = rdl(mp, PHY_ADDR);
2911 return (data >> (5 * mp->port_num)) & 0x1f;
2914 static void set_params(struct mv643xx_eth_private *mp,
2915 struct mv643xx_eth_platform_data *pd)
2917 struct net_device *dev = mp->dev;
2918 unsigned int tx_ring_size;
2920 if (is_valid_ether_addr(pd->mac_addr))
2921 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2923 uc_addr_get(mp, dev->dev_addr);
2925 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2926 if (pd->rx_queue_size)
2927 mp->rx_ring_size = pd->rx_queue_size;
2928 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2929 mp->rx_desc_sram_size = pd->rx_sram_size;
2931 mp->rxq_count = pd->rx_queue_count ? : 1;
2933 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2934 if (pd->tx_queue_size)
2935 tx_ring_size = pd->tx_queue_size;
2937 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2938 MV643XX_MAX_SKB_DESCS * 2, 4096);
2939 if (mp->tx_ring_size != tx_ring_size)
2940 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2941 mp->tx_ring_size, tx_ring_size);
2943 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2944 mp->tx_desc_sram_size = pd->tx_sram_size;
2946 mp->txq_count = pd->tx_queue_count ? : 1;
2949 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2952 struct phy_device *phydev;
2956 char phy_id[MII_BUS_ID_SIZE + 3];
2958 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2959 start = phy_addr_get(mp) & 0x1f;
2962 start = phy_addr & 0x1f;
2966 /* Attempt to connect to the PHY using orion-mdio */
2967 phydev = ERR_PTR(-ENODEV);
2968 for (i = 0; i < num; i++) {
2969 int addr = (start + i) & 0x1f;
2971 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2972 "orion-mdio-mii", addr);
2974 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2975 PHY_INTERFACE_MODE_GMII);
2976 if (!IS_ERR(phydev)) {
2977 phy_addr_set(mp, addr);
2985 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2987 struct phy_device *phy = mp->phy;
2990 phy->autoneg = AUTONEG_ENABLE;
2993 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2995 phy->autoneg = AUTONEG_DISABLE;
2996 phy->advertising = 0;
2998 phy->duplex = duplex;
3000 phy_start_aneg(phy);
3003 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3007 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3008 if (pscr & SERIAL_PORT_ENABLE) {
3009 pscr &= ~SERIAL_PORT_ENABLE;
3010 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3013 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3014 if (mp->phy == NULL) {
3015 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3016 if (speed == SPEED_1000)
3017 pscr |= SET_GMII_SPEED_TO_1000;
3018 else if (speed == SPEED_100)
3019 pscr |= SET_MII_SPEED_TO_100;
3021 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3023 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3024 if (duplex == DUPLEX_FULL)
3025 pscr |= SET_FULL_DUPLEX_MODE;
3028 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3031 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3032 .ndo_open = mv643xx_eth_open,
3033 .ndo_stop = mv643xx_eth_stop,
3034 .ndo_start_xmit = mv643xx_eth_xmit,
3035 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
3036 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
3037 .ndo_validate_addr = eth_validate_addr,
3038 .ndo_do_ioctl = mv643xx_eth_ioctl,
3039 .ndo_change_mtu = mv643xx_eth_change_mtu,
3040 .ndo_set_features = mv643xx_eth_set_features,
3041 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
3042 .ndo_get_stats = mv643xx_eth_get_stats,
3043 #ifdef CONFIG_NET_POLL_CONTROLLER
3044 .ndo_poll_controller = mv643xx_eth_netpoll,
3048 static int mv643xx_eth_probe(struct platform_device *pdev)
3050 struct mv643xx_eth_platform_data *pd;
3051 struct mv643xx_eth_private *mp;
3052 struct net_device *dev;
3053 struct resource *res;
3056 pd = dev_get_platdata(&pdev->dev);
3058 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3062 if (pd->shared == NULL) {
3063 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3067 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3071 mp = netdev_priv(dev);
3072 platform_set_drvdata(pdev, mp);
3074 mp->shared = platform_get_drvdata(pd->shared);
3075 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3076 mp->port_num = pd->port_number;
3080 /* Kirkwood resets some registers on gated clocks. Especially
3081 * CLK125_BYPASS_EN must be cleared but is not available on
3082 * all other SoCs/System Controllers using this driver.
3084 if (of_device_is_compatible(pdev->dev.of_node,
3085 "marvell,kirkwood-eth-port"))
3086 wrlp(mp, PORT_SERIAL_CONTROL1,
3087 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3090 * Start with a default rate, and if there is a clock, allow
3091 * it to override the default.
3093 mp->t_clk = 133000000;
3094 mp->clk = devm_clk_get(&pdev->dev, NULL);
3095 if (!IS_ERR(mp->clk)) {
3096 clk_prepare_enable(mp->clk);
3097 mp->t_clk = clk_get_rate(mp->clk);
3098 } else if (!IS_ERR(mp->shared->clk)) {
3099 mp->t_clk = clk_get_rate(mp->shared->clk);
3103 netif_set_real_num_tx_queues(dev, mp->txq_count);
3104 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3108 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
3109 mv643xx_eth_adjust_link, 0,
3110 PHY_INTERFACE_MODE_GMII);
3114 phy_addr_set(mp, mp->phy->addr);
3115 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3116 mp->phy = phy_scan(mp, pd->phy_addr);
3118 if (IS_ERR(mp->phy))
3119 err = PTR_ERR(mp->phy);
3121 phy_init(mp, pd->speed, pd->duplex);
3123 if (err == -ENODEV) {
3124 err = -EPROBE_DEFER;
3130 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3132 init_pscr(mp, pd->speed, pd->duplex);
3135 mib_counters_clear(mp);
3137 setup_timer(&mp->mib_counters_timer, mib_counters_timer_wrapper,
3139 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3141 spin_lock_init(&mp->mib_counters_lock);
3143 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3145 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3147 setup_timer(&mp->rx_oom, oom_timer_wrapper, (unsigned long)mp);
3150 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3152 dev->irq = res->start;
3154 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3156 dev->watchdog_timeo = 2 * HZ;
3159 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3160 dev->vlan_features = dev->features;
3162 dev->features |= NETIF_F_RXCSUM;
3163 dev->hw_features = dev->features;
3165 dev->priv_flags |= IFF_UNICAST_FLT;
3166 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3168 SET_NETDEV_DEV(dev, &pdev->dev);
3170 if (mp->shared->win_protect)
3171 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3173 netif_carrier_off(dev);
3175 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3177 set_rx_coal(mp, 250);
3180 err = register_netdev(dev);
3184 netdev_notice(dev, "port %d with MAC address %pM\n",
3185 mp->port_num, dev->dev_addr);
3187 if (mp->tx_desc_sram_size > 0)
3188 netdev_notice(dev, "configured with sram\n");
3193 if (!IS_ERR(mp->clk))
3194 clk_disable_unprepare(mp->clk);
3200 static int mv643xx_eth_remove(struct platform_device *pdev)
3202 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3204 unregister_netdev(mp->dev);
3205 if (mp->phy != NULL)
3206 phy_disconnect(mp->phy);
3207 cancel_work_sync(&mp->tx_timeout_task);
3209 if (!IS_ERR(mp->clk))
3210 clk_disable_unprepare(mp->clk);
3212 free_netdev(mp->dev);
3217 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3219 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3221 /* Mask all interrupts on ethernet port */
3222 wrlp(mp, INT_MASK, 0);
3225 if (netif_running(mp->dev))
3229 static struct platform_driver mv643xx_eth_driver = {
3230 .probe = mv643xx_eth_probe,
3231 .remove = mv643xx_eth_remove,
3232 .shutdown = mv643xx_eth_shutdown,
3234 .name = MV643XX_ETH_NAME,
3238 static int __init mv643xx_eth_init_module(void)
3242 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3244 rc = platform_driver_register(&mv643xx_eth_driver);
3246 platform_driver_unregister(&mv643xx_eth_shared_driver);
3251 module_init(mv643xx_eth_init_module);
3253 static void __exit mv643xx_eth_cleanup_module(void)
3255 platform_driver_unregister(&mv643xx_eth_driver);
3256 platform_driver_unregister(&mv643xx_eth_shared_driver);
3258 module_exit(mv643xx_eth_cleanup_module);
3260 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3261 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3262 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3263 MODULE_LICENSE("GPL");
3264 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3265 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);