2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/types.h>
60 #include <linux/inet_lro.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
65 static char mv643xx_eth_driver_version[] = "1.4";
69 * Registers shared between all ports.
71 #define PHY_ADDR 0x0000
72 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
73 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
74 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
75 #define WINDOW_BAR_ENABLE 0x0290
76 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
79 * Main per-port registers. These live at offset 0x0400 for
80 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
82 #define PORT_CONFIG 0x0000
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT 0x0004
85 #define MAC_ADDR_LOW 0x0014
86 #define MAC_ADDR_HIGH 0x0018
87 #define SDMA_CONFIG 0x001c
88 #define TX_BURST_SIZE_16_64BIT 0x01000000
89 #define TX_BURST_SIZE_4_64BIT 0x00800000
90 #define BLM_TX_NO_SWAP 0x00000020
91 #define BLM_RX_NO_SWAP 0x00000010
92 #define RX_BURST_SIZE_16_64BIT 0x00000008
93 #define RX_BURST_SIZE_4_64BIT 0x00000004
94 #define PORT_SERIAL_CONTROL 0x003c
95 #define SET_MII_SPEED_TO_100 0x01000000
96 #define SET_GMII_SPEED_TO_1000 0x00800000
97 #define SET_FULL_DUPLEX_MODE 0x00200000
98 #define MAX_RX_PACKET_9700BYTE 0x000a0000
99 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
100 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
101 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
102 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
103 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
104 #define FORCE_LINK_PASS 0x00000002
105 #define SERIAL_PORT_ENABLE 0x00000001
106 #define PORT_STATUS 0x0044
107 #define TX_FIFO_EMPTY 0x00000400
108 #define TX_IN_PROGRESS 0x00000080
109 #define PORT_SPEED_MASK 0x00000030
110 #define PORT_SPEED_1000 0x00000010
111 #define PORT_SPEED_100 0x00000020
112 #define PORT_SPEED_10 0x00000000
113 #define FLOW_CONTROL_ENABLED 0x00000008
114 #define FULL_DUPLEX 0x00000004
115 #define LINK_UP 0x00000002
116 #define TXQ_COMMAND 0x0048
117 #define TXQ_FIX_PRIO_CONF 0x004c
118 #define TX_BW_RATE 0x0050
119 #define TX_BW_MTU 0x0058
120 #define TX_BW_BURST 0x005c
121 #define INT_CAUSE 0x0060
122 #define INT_TX_END 0x07f80000
123 #define INT_TX_END_0 0x00080000
124 #define INT_RX 0x000003fc
125 #define INT_RX_0 0x00000004
126 #define INT_EXT 0x00000002
127 #define INT_CAUSE_EXT 0x0064
128 #define INT_EXT_LINK_PHY 0x00110000
129 #define INT_EXT_TX 0x000000ff
130 #define INT_MASK 0x0068
131 #define INT_MASK_EXT 0x006c
132 #define TX_FIFO_URGENT_THRESHOLD 0x0074
133 #define RX_DISCARD_FRAME_CNT 0x0084
134 #define RX_OVERRUN_FRAME_CNT 0x0088
135 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
136 #define TX_BW_RATE_MOVED 0x00e0
137 #define TX_BW_MTU_MOVED 0x00e8
138 #define TX_BW_BURST_MOVED 0x00ec
139 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
140 #define RXQ_COMMAND 0x0280
141 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
142 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
143 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
144 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
147 * Misc per-port registers.
149 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
150 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
151 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
152 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
156 * SDMA configuration register default value.
158 #if defined(__BIG_ENDIAN)
159 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
160 (RX_BURST_SIZE_4_64BIT | \
161 TX_BURST_SIZE_4_64BIT)
162 #elif defined(__LITTLE_ENDIAN)
163 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
164 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
169 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176 #define DEFAULT_RX_QUEUE_SIZE 128
177 #define DEFAULT_TX_QUEUE_SIZE 256
178 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
184 #if defined(__BIG_ENDIAN)
186 u16 byte_cnt; /* Descriptor buffer byte count */
187 u16 buf_size; /* Buffer size */
188 u32 cmd_sts; /* Descriptor command status */
189 u32 next_desc_ptr; /* Next descriptor pointer */
190 u32 buf_ptr; /* Descriptor buffer pointer */
194 u16 byte_cnt; /* buffer byte count */
195 u16 l4i_chk; /* CPU provided TCP checksum */
196 u32 cmd_sts; /* Command/status field */
197 u32 next_desc_ptr; /* Pointer to next descriptor */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
200 #elif defined(__LITTLE_ENDIAN)
202 u32 cmd_sts; /* Descriptor command status */
203 u16 buf_size; /* Buffer size */
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u32 buf_ptr; /* Descriptor buffer pointer */
206 u32 next_desc_ptr; /* Next descriptor pointer */
210 u32 cmd_sts; /* Command/status field */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u16 byte_cnt; /* buffer byte count */
213 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr; /* Pointer to next descriptor */
217 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
220 /* RX & TX descriptor command */
221 #define BUFFER_OWNED_BY_DMA 0x80000000
223 /* RX & TX descriptor status */
224 #define ERROR_SUMMARY 0x00000001
226 /* RX descriptor status */
227 #define LAYER_4_CHECKSUM_OK 0x40000000
228 #define RX_ENABLE_INTERRUPT 0x20000000
229 #define RX_FIRST_DESC 0x08000000
230 #define RX_LAST_DESC 0x04000000
231 #define RX_IP_HDR_OK 0x02000000
232 #define RX_PKT_IS_IPV4 0x01000000
233 #define RX_PKT_IS_ETHERNETV2 0x00800000
234 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
238 /* TX descriptor command */
239 #define TX_ENABLE_INTERRUPT 0x00800000
240 #define GEN_CRC 0x00400000
241 #define TX_FIRST_DESC 0x00200000
242 #define TX_LAST_DESC 0x00100000
243 #define ZERO_PADDING 0x00080000
244 #define GEN_IP_V4_CHECKSUM 0x00040000
245 #define GEN_TCP_UDP_CHECKSUM 0x00020000
246 #define UDP_FRAME 0x00010000
247 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
248 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
250 #define TX_IHL_SHIFT 11
253 /* global *******************************************************************/
254 struct mv643xx_eth_shared_private {
256 * Ethernet controller base address.
261 * Per-port MBUS window access register value.
266 * Hardware-specific parameters.
268 int extended_rx_coal_limit;
274 #define TX_BW_CONTROL_ABSENT 0
275 #define TX_BW_CONTROL_OLD_LAYOUT 1
276 #define TX_BW_CONTROL_NEW_LAYOUT 2
278 static int mv643xx_eth_open(struct net_device *dev);
279 static int mv643xx_eth_stop(struct net_device *dev);
282 /* per-port *****************************************************************/
283 struct mib_counters {
284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
304 u32 good_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
310 u32 mac_receive_error;
314 /* Non MIB hardware counters */
319 struct lro_counters {
334 struct rx_desc *rx_desc_area;
335 dma_addr_t rx_desc_dma;
336 int rx_desc_area_size;
337 struct sk_buff **rx_skb;
339 struct net_lro_mgr lro_mgr;
340 struct net_lro_desc lro_arr[8];
352 struct tx_desc *tx_desc_area;
353 dma_addr_t tx_desc_dma;
354 int tx_desc_area_size;
356 struct sk_buff_head tx_skb;
358 unsigned long tx_packets;
359 unsigned long tx_bytes;
360 unsigned long tx_dropped;
363 struct mv643xx_eth_private {
364 struct mv643xx_eth_shared_private *shared;
368 struct net_device *dev;
370 struct phy_device *phy;
372 struct timer_list mib_counters_timer;
373 spinlock_t mib_counters_lock;
374 struct mib_counters mib_counters;
376 struct lro_counters lro_counters;
378 struct work_struct tx_timeout_task;
380 struct napi_struct napi;
395 unsigned long rx_desc_sram_addr;
396 int rx_desc_sram_size;
398 struct timer_list rx_oom;
399 struct rx_queue rxq[8];
405 unsigned long tx_desc_sram_addr;
406 int tx_desc_sram_size;
408 struct tx_queue txq[8];
411 * Hardware-specific parameters.
413 #if defined(CONFIG_HAVE_CLK)
420 /* port register accessors **************************************************/
421 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
423 return readl(mp->shared->base + offset);
426 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
428 return readl(mp->base + offset);
431 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
433 writel(data, mp->shared->base + offset);
436 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
438 writel(data, mp->base + offset);
442 /* rxq/txq helper functions *************************************************/
443 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
445 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
448 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
450 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
453 static void rxq_enable(struct rx_queue *rxq)
455 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
456 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
459 static void rxq_disable(struct rx_queue *rxq)
461 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
462 u8 mask = 1 << rxq->index;
464 wrlp(mp, RXQ_COMMAND, mask << 8);
465 while (rdlp(mp, RXQ_COMMAND) & mask)
469 static void txq_reset_hw_ptr(struct tx_queue *txq)
471 struct mv643xx_eth_private *mp = txq_to_mp(txq);
474 addr = (u32)txq->tx_desc_dma;
475 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
476 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
479 static void txq_enable(struct tx_queue *txq)
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
482 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
485 static void txq_disable(struct tx_queue *txq)
487 struct mv643xx_eth_private *mp = txq_to_mp(txq);
488 u8 mask = 1 << txq->index;
490 wrlp(mp, TXQ_COMMAND, mask << 8);
491 while (rdlp(mp, TXQ_COMMAND) & mask)
495 static void txq_maybe_wake(struct tx_queue *txq)
497 struct mv643xx_eth_private *mp = txq_to_mp(txq);
498 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
500 if (netif_tx_queue_stopped(nq)) {
501 __netif_tx_lock(nq, smp_processor_id());
502 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
503 netif_tx_wake_queue(nq);
504 __netif_tx_unlock(nq);
509 /* rx napi ******************************************************************/
511 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
512 u64 *hdr_flags, void *priv)
514 unsigned long cmd_sts = (unsigned long)priv;
517 * Make sure that this packet is Ethernet II, is not VLAN
518 * tagged, is IPv4, has a valid IP header, and is TCP.
520 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
521 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
522 RX_PKT_IS_VLAN_TAGGED)) !=
523 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
524 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
527 skb_reset_network_header(skb);
528 skb_set_transport_header(skb, ip_hdrlen(skb));
529 *iphdr = ip_hdr(skb);
530 *tcph = tcp_hdr(skb);
531 *hdr_flags = LRO_IPV4 | LRO_TCP;
536 static int rxq_process(struct rx_queue *rxq, int budget)
538 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
539 struct net_device_stats *stats = &mp->dev->stats;
540 int lro_flush_needed;
543 lro_flush_needed = 0;
545 while (rx < budget && rxq->rx_desc_count) {
546 struct rx_desc *rx_desc;
547 unsigned int cmd_sts;
551 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
553 cmd_sts = rx_desc->cmd_sts;
554 if (cmd_sts & BUFFER_OWNED_BY_DMA)
558 skb = rxq->rx_skb[rxq->rx_curr_desc];
559 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
562 if (rxq->rx_curr_desc == rxq->rx_ring_size)
563 rxq->rx_curr_desc = 0;
565 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
566 rx_desc->buf_size, DMA_FROM_DEVICE);
567 rxq->rx_desc_count--;
570 mp->work_rx_refill |= 1 << rxq->index;
572 byte_cnt = rx_desc->byte_cnt;
577 * Note that the descriptor byte count includes 2 dummy
578 * bytes automatically inserted by the hardware at the
579 * start of the packet (which we don't count), and a 4
580 * byte CRC at the end of the packet (which we do count).
583 stats->rx_bytes += byte_cnt - 2;
586 * In case we received a packet without first / last bits
587 * on, or the error summary bit is set, the packet needs
590 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
591 != (RX_FIRST_DESC | RX_LAST_DESC))
595 * The -4 is for the CRC in the trailer of the
598 skb_put(skb, byte_cnt - 2 - 4);
600 if (cmd_sts & LAYER_4_CHECKSUM_OK)
601 skb->ip_summed = CHECKSUM_UNNECESSARY;
602 skb->protocol = eth_type_trans(skb, mp->dev);
604 if (skb->dev->features & NETIF_F_LRO &&
605 skb->ip_summed == CHECKSUM_UNNECESSARY) {
606 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
607 lro_flush_needed = 1;
609 netif_receive_skb(skb);
616 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
617 (RX_FIRST_DESC | RX_LAST_DESC)) {
620 "received packet spanning multiple descriptors\n");
623 if (cmd_sts & ERROR_SUMMARY)
629 if (lro_flush_needed)
630 lro_flush_all(&rxq->lro_mgr);
633 mp->work_rx &= ~(1 << rxq->index);
638 static int rxq_refill(struct rx_queue *rxq, int budget)
640 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
644 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
647 struct rx_desc *rx_desc;
650 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
658 skb_reserve(skb, SKB_DMA_REALIGN);
661 rxq->rx_desc_count++;
663 rx = rxq->rx_used_desc++;
664 if (rxq->rx_used_desc == rxq->rx_ring_size)
665 rxq->rx_used_desc = 0;
667 rx_desc = rxq->rx_desc_area + rx;
669 size = skb->end - skb->data;
670 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
673 rx_desc->buf_size = size;
674 rxq->rx_skb[rx] = skb;
676 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
680 * The hardware automatically prepends 2 bytes of
681 * dummy data to each received packet, so that the
682 * IP header ends up 16-byte aligned.
687 if (refilled < budget)
688 mp->work_rx_refill &= ~(1 << rxq->index);
695 /* tx ***********************************************************************/
696 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
700 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
701 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
703 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
710 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
712 struct mv643xx_eth_private *mp = txq_to_mp(txq);
713 int nr_frags = skb_shinfo(skb)->nr_frags;
716 for (frag = 0; frag < nr_frags; frag++) {
717 skb_frag_t *this_frag;
719 struct tx_desc *desc;
721 this_frag = &skb_shinfo(skb)->frags[frag];
722 tx_index = txq->tx_curr_desc++;
723 if (txq->tx_curr_desc == txq->tx_ring_size)
724 txq->tx_curr_desc = 0;
725 desc = &txq->tx_desc_area[tx_index];
728 * The last fragment will generate an interrupt
729 * which will free the skb on TX completion.
731 if (frag == nr_frags - 1) {
732 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
733 ZERO_PADDING | TX_LAST_DESC |
736 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
740 desc->byte_cnt = skb_frag_size(this_frag);
741 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
743 skb_frag_size(this_frag),
748 static inline __be16 sum16_as_be(__sum16 sum)
750 return (__force __be16)sum;
753 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
755 struct mv643xx_eth_private *mp = txq_to_mp(txq);
756 int nr_frags = skb_shinfo(skb)->nr_frags;
758 struct tx_desc *desc;
763 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
766 if (skb->ip_summed == CHECKSUM_PARTIAL) {
770 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
771 skb->protocol != htons(ETH_P_8021Q));
773 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
774 tag_bytes = hdr_len - ETH_HLEN;
775 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
776 unlikely(tag_bytes & ~12)) {
777 if (skb_checksum_help(skb) == 0)
784 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
786 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
788 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
790 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
792 switch (ip_hdr(skb)->protocol) {
794 cmd_sts |= UDP_FRAME;
795 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
798 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
805 /* Errata BTS #50, IHL must be 5 if no HW checksum */
806 cmd_sts |= 5 << TX_IHL_SHIFT;
809 tx_index = txq->tx_curr_desc++;
810 if (txq->tx_curr_desc == txq->tx_ring_size)
811 txq->tx_curr_desc = 0;
812 desc = &txq->tx_desc_area[tx_index];
815 txq_submit_frag_skb(txq, skb);
816 length = skb_headlen(skb);
818 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
822 desc->l4i_chk = l4i_chk;
823 desc->byte_cnt = length;
824 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
825 length, DMA_TO_DEVICE);
827 __skb_queue_tail(&txq->tx_skb, skb);
829 skb_tx_timestamp(skb);
831 /* ensure all other descriptors are written before first cmd_sts */
833 desc->cmd_sts = cmd_sts;
835 /* clear TX_END status */
836 mp->work_tx_end &= ~(1 << txq->index);
838 /* ensure all descriptors are written before poking hardware */
842 txq->tx_desc_count += nr_frags + 1;
847 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
849 struct mv643xx_eth_private *mp = netdev_priv(dev);
851 struct tx_queue *txq;
852 struct netdev_queue *nq;
854 queue = skb_get_queue_mapping(skb);
855 txq = mp->txq + queue;
856 nq = netdev_get_tx_queue(dev, queue);
858 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
860 netdev_printk(KERN_DEBUG, dev,
861 "failed to linearize skb with tiny unaligned fragment\n");
862 return NETDEV_TX_BUSY;
865 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
867 netdev_err(dev, "tx queue full?!\n");
874 if (!txq_submit_skb(txq, skb)) {
877 txq->tx_bytes += length;
880 entries_left = txq->tx_ring_size - txq->tx_desc_count;
881 if (entries_left < MAX_SKB_FRAGS + 1)
882 netif_tx_stop_queue(nq);
889 /* tx napi ******************************************************************/
890 static void txq_kick(struct tx_queue *txq)
892 struct mv643xx_eth_private *mp = txq_to_mp(txq);
893 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
897 __netif_tx_lock(nq, smp_processor_id());
899 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
902 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
903 expected_ptr = (u32)txq->tx_desc_dma +
904 txq->tx_curr_desc * sizeof(struct tx_desc);
906 if (hw_desc_ptr != expected_ptr)
910 __netif_tx_unlock(nq);
912 mp->work_tx_end &= ~(1 << txq->index);
915 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
917 struct mv643xx_eth_private *mp = txq_to_mp(txq);
918 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
921 __netif_tx_lock(nq, smp_processor_id());
924 while (reclaimed < budget && txq->tx_desc_count > 0) {
926 struct tx_desc *desc;
930 tx_index = txq->tx_used_desc;
931 desc = &txq->tx_desc_area[tx_index];
932 cmd_sts = desc->cmd_sts;
934 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
937 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
940 txq->tx_used_desc = tx_index + 1;
941 if (txq->tx_used_desc == txq->tx_ring_size)
942 txq->tx_used_desc = 0;
945 txq->tx_desc_count--;
948 if (cmd_sts & TX_LAST_DESC)
949 skb = __skb_dequeue(&txq->tx_skb);
951 if (cmd_sts & ERROR_SUMMARY) {
952 netdev_info(mp->dev, "tx error\n");
953 mp->dev->stats.tx_errors++;
956 if (cmd_sts & TX_FIRST_DESC) {
957 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
958 desc->byte_cnt, DMA_TO_DEVICE);
960 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
961 desc->byte_cnt, DMA_TO_DEVICE);
967 __netif_tx_unlock(nq);
969 if (reclaimed < budget)
970 mp->work_tx &= ~(1 << txq->index);
976 /* tx rate control **********************************************************/
978 * Set total maximum TX rate (shared by all TX queues for this port)
979 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
981 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
987 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
988 if (token_rate > 1023)
991 mtu = (mp->dev->mtu + 255) >> 8;
995 bucket_size = (burst + 255) >> 8;
996 if (bucket_size > 65535)
999 switch (mp->shared->tx_bw_control) {
1000 case TX_BW_CONTROL_OLD_LAYOUT:
1001 wrlp(mp, TX_BW_RATE, token_rate);
1002 wrlp(mp, TX_BW_MTU, mtu);
1003 wrlp(mp, TX_BW_BURST, bucket_size);
1005 case TX_BW_CONTROL_NEW_LAYOUT:
1006 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1007 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1008 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1013 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1015 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1019 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1020 if (token_rate > 1023)
1023 bucket_size = (burst + 255) >> 8;
1024 if (bucket_size > 65535)
1025 bucket_size = 65535;
1027 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1028 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1031 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1033 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1038 * Turn on fixed priority mode.
1041 switch (mp->shared->tx_bw_control) {
1042 case TX_BW_CONTROL_OLD_LAYOUT:
1043 off = TXQ_FIX_PRIO_CONF;
1045 case TX_BW_CONTROL_NEW_LAYOUT:
1046 off = TXQ_FIX_PRIO_CONF_MOVED;
1051 val = rdlp(mp, off);
1052 val |= 1 << txq->index;
1058 /* mii management interface *************************************************/
1059 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1061 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1062 u32 autoneg_disable = FORCE_LINK_PASS |
1063 DISABLE_AUTO_NEG_SPEED_GMII |
1064 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1065 DISABLE_AUTO_NEG_FOR_DUPLEX;
1067 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1068 /* enable auto negotiation */
1069 pscr &= ~autoneg_disable;
1073 pscr |= autoneg_disable;
1075 if (mp->phy->speed == SPEED_1000) {
1076 /* force gigabit, half duplex not supported */
1077 pscr |= SET_GMII_SPEED_TO_1000;
1078 pscr |= SET_FULL_DUPLEX_MODE;
1082 pscr &= ~SET_GMII_SPEED_TO_1000;
1084 if (mp->phy->speed == SPEED_100)
1085 pscr |= SET_MII_SPEED_TO_100;
1087 pscr &= ~SET_MII_SPEED_TO_100;
1089 if (mp->phy->duplex == DUPLEX_FULL)
1090 pscr |= SET_FULL_DUPLEX_MODE;
1092 pscr &= ~SET_FULL_DUPLEX_MODE;
1095 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1098 /* statistics ***************************************************************/
1099 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1101 struct mv643xx_eth_private *mp = netdev_priv(dev);
1102 struct net_device_stats *stats = &dev->stats;
1103 unsigned long tx_packets = 0;
1104 unsigned long tx_bytes = 0;
1105 unsigned long tx_dropped = 0;
1108 for (i = 0; i < mp->txq_count; i++) {
1109 struct tx_queue *txq = mp->txq + i;
1111 tx_packets += txq->tx_packets;
1112 tx_bytes += txq->tx_bytes;
1113 tx_dropped += txq->tx_dropped;
1116 stats->tx_packets = tx_packets;
1117 stats->tx_bytes = tx_bytes;
1118 stats->tx_dropped = tx_dropped;
1123 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1125 u32 lro_aggregated = 0;
1126 u32 lro_flushed = 0;
1127 u32 lro_no_desc = 0;
1130 for (i = 0; i < mp->rxq_count; i++) {
1131 struct rx_queue *rxq = mp->rxq + i;
1133 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1134 lro_flushed += rxq->lro_mgr.stats.flushed;
1135 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1138 mp->lro_counters.lro_aggregated = lro_aggregated;
1139 mp->lro_counters.lro_flushed = lro_flushed;
1140 mp->lro_counters.lro_no_desc = lro_no_desc;
1143 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1145 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1148 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1152 for (i = 0; i < 0x80; i += 4)
1155 /* Clear non MIB hw counters also */
1156 rdlp(mp, RX_DISCARD_FRAME_CNT);
1157 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1160 static void mib_counters_update(struct mv643xx_eth_private *mp)
1162 struct mib_counters *p = &mp->mib_counters;
1164 spin_lock_bh(&mp->mib_counters_lock);
1165 p->good_octets_received += mib_read(mp, 0x00);
1166 p->bad_octets_received += mib_read(mp, 0x08);
1167 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1168 p->good_frames_received += mib_read(mp, 0x10);
1169 p->bad_frames_received += mib_read(mp, 0x14);
1170 p->broadcast_frames_received += mib_read(mp, 0x18);
1171 p->multicast_frames_received += mib_read(mp, 0x1c);
1172 p->frames_64_octets += mib_read(mp, 0x20);
1173 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1174 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1175 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1176 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1177 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1178 p->good_octets_sent += mib_read(mp, 0x38);
1179 p->good_frames_sent += mib_read(mp, 0x40);
1180 p->excessive_collision += mib_read(mp, 0x44);
1181 p->multicast_frames_sent += mib_read(mp, 0x48);
1182 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1183 p->unrec_mac_control_received += mib_read(mp, 0x50);
1184 p->fc_sent += mib_read(mp, 0x54);
1185 p->good_fc_received += mib_read(mp, 0x58);
1186 p->bad_fc_received += mib_read(mp, 0x5c);
1187 p->undersize_received += mib_read(mp, 0x60);
1188 p->fragments_received += mib_read(mp, 0x64);
1189 p->oversize_received += mib_read(mp, 0x68);
1190 p->jabber_received += mib_read(mp, 0x6c);
1191 p->mac_receive_error += mib_read(mp, 0x70);
1192 p->bad_crc_event += mib_read(mp, 0x74);
1193 p->collision += mib_read(mp, 0x78);
1194 p->late_collision += mib_read(mp, 0x7c);
1195 /* Non MIB hardware counters */
1196 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1197 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1198 spin_unlock_bh(&mp->mib_counters_lock);
1200 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1203 static void mib_counters_timer_wrapper(unsigned long _mp)
1205 struct mv643xx_eth_private *mp = (void *)_mp;
1207 mib_counters_update(mp);
1211 /* interrupt coalescing *****************************************************/
1213 * Hardware coalescing parameters are set in units of 64 t_clk
1216 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1218 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1220 * In the ->set*() methods, we round the computed register value
1221 * to the nearest integer.
1223 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1225 u32 val = rdlp(mp, SDMA_CONFIG);
1228 if (mp->shared->extended_rx_coal_limit)
1229 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1231 temp = (val & 0x003fff00) >> 8;
1234 do_div(temp, mp->t_clk);
1236 return (unsigned int)temp;
1239 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1244 temp = (u64)usec * mp->t_clk;
1246 do_div(temp, 64000000);
1248 val = rdlp(mp, SDMA_CONFIG);
1249 if (mp->shared->extended_rx_coal_limit) {
1253 val |= (temp & 0x8000) << 10;
1254 val |= (temp & 0x7fff) << 7;
1259 val |= (temp & 0x3fff) << 8;
1261 wrlp(mp, SDMA_CONFIG, val);
1264 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1268 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1270 do_div(temp, mp->t_clk);
1272 return (unsigned int)temp;
1275 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1279 temp = (u64)usec * mp->t_clk;
1281 do_div(temp, 64000000);
1286 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1290 /* ethtool ******************************************************************/
1291 struct mv643xx_eth_stats {
1292 char stat_string[ETH_GSTRING_LEN];
1299 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1300 offsetof(struct net_device, stats.m), -1 }
1302 #define MIBSTAT(m) \
1303 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1304 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1306 #define LROSTAT(m) \
1307 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1308 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1310 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1319 MIBSTAT(good_octets_received),
1320 MIBSTAT(bad_octets_received),
1321 MIBSTAT(internal_mac_transmit_err),
1322 MIBSTAT(good_frames_received),
1323 MIBSTAT(bad_frames_received),
1324 MIBSTAT(broadcast_frames_received),
1325 MIBSTAT(multicast_frames_received),
1326 MIBSTAT(frames_64_octets),
1327 MIBSTAT(frames_65_to_127_octets),
1328 MIBSTAT(frames_128_to_255_octets),
1329 MIBSTAT(frames_256_to_511_octets),
1330 MIBSTAT(frames_512_to_1023_octets),
1331 MIBSTAT(frames_1024_to_max_octets),
1332 MIBSTAT(good_octets_sent),
1333 MIBSTAT(good_frames_sent),
1334 MIBSTAT(excessive_collision),
1335 MIBSTAT(multicast_frames_sent),
1336 MIBSTAT(broadcast_frames_sent),
1337 MIBSTAT(unrec_mac_control_received),
1339 MIBSTAT(good_fc_received),
1340 MIBSTAT(bad_fc_received),
1341 MIBSTAT(undersize_received),
1342 MIBSTAT(fragments_received),
1343 MIBSTAT(oversize_received),
1344 MIBSTAT(jabber_received),
1345 MIBSTAT(mac_receive_error),
1346 MIBSTAT(bad_crc_event),
1348 MIBSTAT(late_collision),
1349 MIBSTAT(rx_discard),
1350 MIBSTAT(rx_overrun),
1351 LROSTAT(lro_aggregated),
1352 LROSTAT(lro_flushed),
1353 LROSTAT(lro_no_desc),
1357 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1358 struct ethtool_cmd *cmd)
1362 err = phy_read_status(mp->phy);
1364 err = phy_ethtool_gset(mp->phy, cmd);
1367 * The MAC does not support 1000baseT_Half.
1369 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1370 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1376 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1377 struct ethtool_cmd *cmd)
1381 port_status = rdlp(mp, PORT_STATUS);
1383 cmd->supported = SUPPORTED_MII;
1384 cmd->advertising = ADVERTISED_MII;
1385 switch (port_status & PORT_SPEED_MASK) {
1387 ethtool_cmd_speed_set(cmd, SPEED_10);
1389 case PORT_SPEED_100:
1390 ethtool_cmd_speed_set(cmd, SPEED_100);
1392 case PORT_SPEED_1000:
1393 ethtool_cmd_speed_set(cmd, SPEED_1000);
1399 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1400 cmd->port = PORT_MII;
1401 cmd->phy_address = 0;
1402 cmd->transceiver = XCVR_INTERNAL;
1403 cmd->autoneg = AUTONEG_DISABLE;
1411 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1413 struct mv643xx_eth_private *mp = netdev_priv(dev);
1417 phy_ethtool_get_wol(mp->phy, wol);
1421 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1423 struct mv643xx_eth_private *mp = netdev_priv(dev);
1426 if (mp->phy == NULL)
1429 err = phy_ethtool_set_wol(mp->phy, wol);
1430 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1431 * this debugging hint is useful to have.
1433 if (err == -EOPNOTSUPP)
1434 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1439 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1441 struct mv643xx_eth_private *mp = netdev_priv(dev);
1443 if (mp->phy != NULL)
1444 return mv643xx_eth_get_settings_phy(mp, cmd);
1446 return mv643xx_eth_get_settings_phyless(mp, cmd);
1450 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1452 struct mv643xx_eth_private *mp = netdev_priv(dev);
1455 if (mp->phy == NULL)
1459 * The MAC does not support 1000baseT_Half.
1461 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1463 ret = phy_ethtool_sset(mp->phy, cmd);
1465 mv643xx_adjust_pscr(mp);
1469 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1470 struct ethtool_drvinfo *drvinfo)
1472 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1473 sizeof(drvinfo->driver));
1474 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1475 sizeof(drvinfo->version));
1476 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1477 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1478 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1481 static int mv643xx_eth_nway_reset(struct net_device *dev)
1483 struct mv643xx_eth_private *mp = netdev_priv(dev);
1485 if (mp->phy == NULL)
1488 return genphy_restart_aneg(mp->phy);
1492 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1494 struct mv643xx_eth_private *mp = netdev_priv(dev);
1496 ec->rx_coalesce_usecs = get_rx_coal(mp);
1497 ec->tx_coalesce_usecs = get_tx_coal(mp);
1503 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1505 struct mv643xx_eth_private *mp = netdev_priv(dev);
1507 set_rx_coal(mp, ec->rx_coalesce_usecs);
1508 set_tx_coal(mp, ec->tx_coalesce_usecs);
1514 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1516 struct mv643xx_eth_private *mp = netdev_priv(dev);
1518 er->rx_max_pending = 4096;
1519 er->tx_max_pending = 4096;
1521 er->rx_pending = mp->rx_ring_size;
1522 er->tx_pending = mp->tx_ring_size;
1526 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1528 struct mv643xx_eth_private *mp = netdev_priv(dev);
1530 if (er->rx_mini_pending || er->rx_jumbo_pending)
1533 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1534 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1536 if (netif_running(dev)) {
1537 mv643xx_eth_stop(dev);
1538 if (mv643xx_eth_open(dev)) {
1540 "fatal error on re-opening device after ring param change\n");
1550 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1552 struct mv643xx_eth_private *mp = netdev_priv(dev);
1553 bool rx_csum = features & NETIF_F_RXCSUM;
1555 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1560 static void mv643xx_eth_get_strings(struct net_device *dev,
1561 uint32_t stringset, uint8_t *data)
1565 if (stringset == ETH_SS_STATS) {
1566 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1567 memcpy(data + i * ETH_GSTRING_LEN,
1568 mv643xx_eth_stats[i].stat_string,
1574 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1575 struct ethtool_stats *stats,
1578 struct mv643xx_eth_private *mp = netdev_priv(dev);
1581 mv643xx_eth_get_stats(dev);
1582 mib_counters_update(mp);
1583 mv643xx_eth_grab_lro_stats(mp);
1585 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1586 const struct mv643xx_eth_stats *stat;
1589 stat = mv643xx_eth_stats + i;
1591 if (stat->netdev_off >= 0)
1592 p = ((void *)mp->dev) + stat->netdev_off;
1594 p = ((void *)mp) + stat->mp_off;
1596 data[i] = (stat->sizeof_stat == 8) ?
1597 *(uint64_t *)p : *(uint32_t *)p;
1601 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1603 if (sset == ETH_SS_STATS)
1604 return ARRAY_SIZE(mv643xx_eth_stats);
1609 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1610 .get_settings = mv643xx_eth_get_settings,
1611 .set_settings = mv643xx_eth_set_settings,
1612 .get_drvinfo = mv643xx_eth_get_drvinfo,
1613 .nway_reset = mv643xx_eth_nway_reset,
1614 .get_link = ethtool_op_get_link,
1615 .get_coalesce = mv643xx_eth_get_coalesce,
1616 .set_coalesce = mv643xx_eth_set_coalesce,
1617 .get_ringparam = mv643xx_eth_get_ringparam,
1618 .set_ringparam = mv643xx_eth_set_ringparam,
1619 .get_strings = mv643xx_eth_get_strings,
1620 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1621 .get_sset_count = mv643xx_eth_get_sset_count,
1622 .get_ts_info = ethtool_op_get_ts_info,
1623 .get_wol = mv643xx_eth_get_wol,
1624 .set_wol = mv643xx_eth_set_wol,
1628 /* address handling *********************************************************/
1629 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1631 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1632 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1634 addr[0] = (mac_h >> 24) & 0xff;
1635 addr[1] = (mac_h >> 16) & 0xff;
1636 addr[2] = (mac_h >> 8) & 0xff;
1637 addr[3] = mac_h & 0xff;
1638 addr[4] = (mac_l >> 8) & 0xff;
1639 addr[5] = mac_l & 0xff;
1642 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1644 wrlp(mp, MAC_ADDR_HIGH,
1645 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1646 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1649 static u32 uc_addr_filter_mask(struct net_device *dev)
1651 struct netdev_hw_addr *ha;
1654 if (dev->flags & IFF_PROMISC)
1657 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1658 netdev_for_each_uc_addr(ha, dev) {
1659 if (memcmp(dev->dev_addr, ha->addr, 5))
1661 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1664 nibbles |= 1 << (ha->addr[5] & 0x0f);
1670 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1672 struct mv643xx_eth_private *mp = netdev_priv(dev);
1677 uc_addr_set(mp, dev->dev_addr);
1679 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1681 nibbles = uc_addr_filter_mask(dev);
1683 port_config |= UNICAST_PROMISCUOUS_MODE;
1687 for (i = 0; i < 16; i += 4) {
1688 int off = UNICAST_TABLE(mp->port_num) + i;
1705 wrlp(mp, PORT_CONFIG, port_config);
1708 static int addr_crc(unsigned char *addr)
1713 for (i = 0; i < 6; i++) {
1716 crc = (crc ^ addr[i]) << 8;
1717 for (j = 7; j >= 0; j--) {
1718 if (crc & (0x100 << j))
1726 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1728 struct mv643xx_eth_private *mp = netdev_priv(dev);
1731 struct netdev_hw_addr *ha;
1734 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1739 port_num = mp->port_num;
1740 accept = 0x01010101;
1741 for (i = 0; i < 0x100; i += 4) {
1742 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1743 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1748 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1749 if (mc_spec == NULL)
1751 mc_other = mc_spec + (0x100 >> 2);
1753 memset(mc_spec, 0, 0x100);
1754 memset(mc_other, 0, 0x100);
1756 netdev_for_each_mc_addr(ha, dev) {
1761 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1766 entry = addr_crc(a);
1769 table[entry >> 2] |= 1 << (8 * (entry & 3));
1772 for (i = 0; i < 0x100; i += 4) {
1773 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1774 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1780 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1782 mv643xx_eth_program_unicast_filter(dev);
1783 mv643xx_eth_program_multicast_filter(dev);
1786 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1788 struct sockaddr *sa = addr;
1790 if (!is_valid_ether_addr(sa->sa_data))
1791 return -EADDRNOTAVAIL;
1793 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1795 netif_addr_lock_bh(dev);
1796 mv643xx_eth_program_unicast_filter(dev);
1797 netif_addr_unlock_bh(dev);
1803 /* rx/tx queue initialisation ***********************************************/
1804 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1806 struct rx_queue *rxq = mp->rxq + index;
1807 struct rx_desc *rx_desc;
1813 rxq->rx_ring_size = mp->rx_ring_size;
1815 rxq->rx_desc_count = 0;
1816 rxq->rx_curr_desc = 0;
1817 rxq->rx_used_desc = 0;
1819 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1821 if (index == 0 && size <= mp->rx_desc_sram_size) {
1822 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1823 mp->rx_desc_sram_size);
1824 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1826 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1827 size, &rxq->rx_desc_dma,
1831 if (rxq->rx_desc_area == NULL) {
1833 "can't allocate rx ring (%d bytes)\n", size);
1836 memset(rxq->rx_desc_area, 0, size);
1838 rxq->rx_desc_area_size = size;
1839 rxq->rx_skb = kmalloc_array(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1841 if (rxq->rx_skb == NULL)
1844 rx_desc = rxq->rx_desc_area;
1845 for (i = 0; i < rxq->rx_ring_size; i++) {
1849 if (nexti == rxq->rx_ring_size)
1852 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1853 nexti * sizeof(struct rx_desc);
1856 rxq->lro_mgr.dev = mp->dev;
1857 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1858 rxq->lro_mgr.features = LRO_F_NAPI;
1859 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1860 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1861 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1862 rxq->lro_mgr.max_aggr = 32;
1863 rxq->lro_mgr.frag_align_pad = 0;
1864 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1865 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1867 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1873 if (index == 0 && size <= mp->rx_desc_sram_size)
1874 iounmap(rxq->rx_desc_area);
1876 dma_free_coherent(mp->dev->dev.parent, size,
1884 static void rxq_deinit(struct rx_queue *rxq)
1886 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1891 for (i = 0; i < rxq->rx_ring_size; i++) {
1892 if (rxq->rx_skb[i]) {
1893 dev_kfree_skb(rxq->rx_skb[i]);
1894 rxq->rx_desc_count--;
1898 if (rxq->rx_desc_count) {
1899 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1900 rxq->rx_desc_count);
1903 if (rxq->index == 0 &&
1904 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1905 iounmap(rxq->rx_desc_area);
1907 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1908 rxq->rx_desc_area, rxq->rx_desc_dma);
1913 static int txq_init(struct mv643xx_eth_private *mp, int index)
1915 struct tx_queue *txq = mp->txq + index;
1916 struct tx_desc *tx_desc;
1922 txq->tx_ring_size = mp->tx_ring_size;
1924 txq->tx_desc_count = 0;
1925 txq->tx_curr_desc = 0;
1926 txq->tx_used_desc = 0;
1928 size = txq->tx_ring_size * sizeof(struct tx_desc);
1930 if (index == 0 && size <= mp->tx_desc_sram_size) {
1931 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1932 mp->tx_desc_sram_size);
1933 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1935 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1936 size, &txq->tx_desc_dma,
1940 if (txq->tx_desc_area == NULL) {
1942 "can't allocate tx ring (%d bytes)\n", size);
1945 memset(txq->tx_desc_area, 0, size);
1947 txq->tx_desc_area_size = size;
1949 tx_desc = txq->tx_desc_area;
1950 for (i = 0; i < txq->tx_ring_size; i++) {
1951 struct tx_desc *txd = tx_desc + i;
1955 if (nexti == txq->tx_ring_size)
1959 txd->next_desc_ptr = txq->tx_desc_dma +
1960 nexti * sizeof(struct tx_desc);
1963 skb_queue_head_init(&txq->tx_skb);
1968 static void txq_deinit(struct tx_queue *txq)
1970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1973 txq_reclaim(txq, txq->tx_ring_size, 1);
1975 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1977 if (txq->index == 0 &&
1978 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1979 iounmap(txq->tx_desc_area);
1981 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
1982 txq->tx_desc_area, txq->tx_desc_dma);
1986 /* netdev ops and related ***************************************************/
1987 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1992 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1997 if (int_cause & INT_EXT) {
1998 int_cause &= ~INT_EXT;
1999 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2003 wrlp(mp, INT_CAUSE, ~int_cause);
2004 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2005 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2006 mp->work_rx |= (int_cause & INT_RX) >> 2;
2009 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2010 if (int_cause_ext) {
2011 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2012 if (int_cause_ext & INT_EXT_LINK_PHY)
2014 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2020 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2022 struct net_device *dev = (struct net_device *)dev_id;
2023 struct mv643xx_eth_private *mp = netdev_priv(dev);
2025 if (unlikely(!mv643xx_eth_collect_events(mp)))
2028 wrlp(mp, INT_MASK, 0);
2029 napi_schedule(&mp->napi);
2034 static void handle_link_event(struct mv643xx_eth_private *mp)
2036 struct net_device *dev = mp->dev;
2042 port_status = rdlp(mp, PORT_STATUS);
2043 if (!(port_status & LINK_UP)) {
2044 if (netif_carrier_ok(dev)) {
2047 netdev_info(dev, "link down\n");
2049 netif_carrier_off(dev);
2051 for (i = 0; i < mp->txq_count; i++) {
2052 struct tx_queue *txq = mp->txq + i;
2054 txq_reclaim(txq, txq->tx_ring_size, 1);
2055 txq_reset_hw_ptr(txq);
2061 switch (port_status & PORT_SPEED_MASK) {
2065 case PORT_SPEED_100:
2068 case PORT_SPEED_1000:
2075 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2076 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2078 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2079 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2081 if (!netif_carrier_ok(dev))
2082 netif_carrier_on(dev);
2085 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2087 struct mv643xx_eth_private *mp;
2090 mp = container_of(napi, struct mv643xx_eth_private, napi);
2092 if (unlikely(mp->oom)) {
2094 del_timer(&mp->rx_oom);
2098 while (work_done < budget) {
2103 if (mp->work_link) {
2105 handle_link_event(mp);
2110 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2111 if (likely(!mp->oom))
2112 queue_mask |= mp->work_rx_refill;
2115 if (mv643xx_eth_collect_events(mp))
2120 queue = fls(queue_mask) - 1;
2121 queue_mask = 1 << queue;
2123 work_tbd = budget - work_done;
2127 if (mp->work_tx_end & queue_mask) {
2128 txq_kick(mp->txq + queue);
2129 } else if (mp->work_tx & queue_mask) {
2130 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2131 txq_maybe_wake(mp->txq + queue);
2132 } else if (mp->work_rx & queue_mask) {
2133 work_done += rxq_process(mp->rxq + queue, work_tbd);
2134 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2135 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2141 if (work_done < budget) {
2143 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2144 napi_complete(napi);
2145 wrlp(mp, INT_MASK, mp->int_mask);
2151 static inline void oom_timer_wrapper(unsigned long data)
2153 struct mv643xx_eth_private *mp = (void *)data;
2155 napi_schedule(&mp->napi);
2158 static void phy_reset(struct mv643xx_eth_private *mp)
2162 data = phy_read(mp->phy, MII_BMCR);
2167 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2171 data = phy_read(mp->phy, MII_BMCR);
2172 } while (data >= 0 && data & BMCR_RESET);
2175 static void port_start(struct mv643xx_eth_private *mp)
2181 * Perform PHY reset, if there is a PHY.
2183 if (mp->phy != NULL) {
2184 struct ethtool_cmd cmd;
2186 mv643xx_eth_get_settings(mp->dev, &cmd);
2188 mv643xx_eth_set_settings(mp->dev, &cmd);
2192 * Configure basic link parameters.
2194 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2196 pscr |= SERIAL_PORT_ENABLE;
2197 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2199 pscr |= DO_NOT_FORCE_LINK_FAIL;
2200 if (mp->phy == NULL)
2201 pscr |= FORCE_LINK_PASS;
2202 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2205 * Configure TX path and queues.
2207 tx_set_rate(mp, 1000000000, 16777216);
2208 for (i = 0; i < mp->txq_count; i++) {
2209 struct tx_queue *txq = mp->txq + i;
2211 txq_reset_hw_ptr(txq);
2212 txq_set_rate(txq, 1000000000, 16777216);
2213 txq_set_fixed_prio_mode(txq);
2217 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2218 * frames to RX queue #0, and include the pseudo-header when
2219 * calculating receive checksums.
2221 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2224 * Treat BPDUs as normal multicasts, and disable partition mode.
2226 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2229 * Add configured unicast addresses to address filter table.
2231 mv643xx_eth_program_unicast_filter(mp->dev);
2234 * Enable the receive queues.
2236 for (i = 0; i < mp->rxq_count; i++) {
2237 struct rx_queue *rxq = mp->rxq + i;
2240 addr = (u32)rxq->rx_desc_dma;
2241 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2242 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2248 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2253 * Reserve 2+14 bytes for an ethernet header (the hardware
2254 * automatically prepends 2 bytes of dummy data to each
2255 * received packet), 16 bytes for up to four VLAN tags, and
2256 * 4 bytes for the trailing FCS -- 36 bytes total.
2258 skb_size = mp->dev->mtu + 36;
2261 * Make sure that the skb size is a multiple of 8 bytes, as
2262 * the lower three bits of the receive descriptor's buffer
2263 * size field are ignored by the hardware.
2265 mp->skb_size = (skb_size + 7) & ~7;
2268 * If NET_SKB_PAD is smaller than a cache line,
2269 * netdev_alloc_skb() will cause skb->data to be misaligned
2270 * to a cache line boundary. If this is the case, include
2271 * some extra space to allow re-aligning the data area.
2273 mp->skb_size += SKB_DMA_REALIGN;
2276 static int mv643xx_eth_open(struct net_device *dev)
2278 struct mv643xx_eth_private *mp = netdev_priv(dev);
2282 wrlp(mp, INT_CAUSE, 0);
2283 wrlp(mp, INT_CAUSE_EXT, 0);
2284 rdlp(mp, INT_CAUSE_EXT);
2286 err = request_irq(dev->irq, mv643xx_eth_irq,
2287 IRQF_SHARED, dev->name, dev);
2289 netdev_err(dev, "can't assign irq\n");
2293 mv643xx_eth_recalc_skb_size(mp);
2295 napi_enable(&mp->napi);
2297 mp->int_mask = INT_EXT;
2299 for (i = 0; i < mp->rxq_count; i++) {
2300 err = rxq_init(mp, i);
2303 rxq_deinit(mp->rxq + i);
2307 rxq_refill(mp->rxq + i, INT_MAX);
2308 mp->int_mask |= INT_RX_0 << i;
2312 mp->rx_oom.expires = jiffies + (HZ / 10);
2313 add_timer(&mp->rx_oom);
2316 for (i = 0; i < mp->txq_count; i++) {
2317 err = txq_init(mp, i);
2320 txq_deinit(mp->txq + i);
2323 mp->int_mask |= INT_TX_END_0 << i;
2328 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2329 wrlp(mp, INT_MASK, mp->int_mask);
2335 for (i = 0; i < mp->rxq_count; i++)
2336 rxq_deinit(mp->rxq + i);
2338 free_irq(dev->irq, dev);
2343 static void port_reset(struct mv643xx_eth_private *mp)
2348 for (i = 0; i < mp->rxq_count; i++)
2349 rxq_disable(mp->rxq + i);
2350 for (i = 0; i < mp->txq_count; i++)
2351 txq_disable(mp->txq + i);
2354 u32 ps = rdlp(mp, PORT_STATUS);
2356 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2361 /* Reset the Enable bit in the Configuration Register */
2362 data = rdlp(mp, PORT_SERIAL_CONTROL);
2363 data &= ~(SERIAL_PORT_ENABLE |
2364 DO_NOT_FORCE_LINK_FAIL |
2366 wrlp(mp, PORT_SERIAL_CONTROL, data);
2369 static int mv643xx_eth_stop(struct net_device *dev)
2371 struct mv643xx_eth_private *mp = netdev_priv(dev);
2374 wrlp(mp, INT_MASK_EXT, 0x00000000);
2375 wrlp(mp, INT_MASK, 0x00000000);
2378 napi_disable(&mp->napi);
2380 del_timer_sync(&mp->rx_oom);
2382 netif_carrier_off(dev);
2384 free_irq(dev->irq, dev);
2387 mv643xx_eth_get_stats(dev);
2388 mib_counters_update(mp);
2389 del_timer_sync(&mp->mib_counters_timer);
2391 for (i = 0; i < mp->rxq_count; i++)
2392 rxq_deinit(mp->rxq + i);
2393 for (i = 0; i < mp->txq_count; i++)
2394 txq_deinit(mp->txq + i);
2399 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2401 struct mv643xx_eth_private *mp = netdev_priv(dev);
2404 if (mp->phy == NULL)
2407 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2409 mv643xx_adjust_pscr(mp);
2413 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2415 struct mv643xx_eth_private *mp = netdev_priv(dev);
2417 if (new_mtu < 64 || new_mtu > 9500)
2421 mv643xx_eth_recalc_skb_size(mp);
2422 tx_set_rate(mp, 1000000000, 16777216);
2424 if (!netif_running(dev))
2428 * Stop and then re-open the interface. This will allocate RX
2429 * skbs of the new MTU.
2430 * There is a possible danger that the open will not succeed,
2431 * due to memory being full.
2433 mv643xx_eth_stop(dev);
2434 if (mv643xx_eth_open(dev)) {
2436 "fatal error on re-opening device after MTU change\n");
2442 static void tx_timeout_task(struct work_struct *ugly)
2444 struct mv643xx_eth_private *mp;
2446 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2447 if (netif_running(mp->dev)) {
2448 netif_tx_stop_all_queues(mp->dev);
2451 netif_tx_wake_all_queues(mp->dev);
2455 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2457 struct mv643xx_eth_private *mp = netdev_priv(dev);
2459 netdev_info(dev, "tx timeout\n");
2461 schedule_work(&mp->tx_timeout_task);
2464 #ifdef CONFIG_NET_POLL_CONTROLLER
2465 static void mv643xx_eth_netpoll(struct net_device *dev)
2467 struct mv643xx_eth_private *mp = netdev_priv(dev);
2469 wrlp(mp, INT_MASK, 0x00000000);
2472 mv643xx_eth_irq(dev->irq, dev);
2474 wrlp(mp, INT_MASK, mp->int_mask);
2479 /* platform glue ************************************************************/
2481 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2482 const struct mbus_dram_target_info *dram)
2484 void __iomem *base = msp->base;
2489 for (i = 0; i < 6; i++) {
2490 writel(0, base + WINDOW_BASE(i));
2491 writel(0, base + WINDOW_SIZE(i));
2493 writel(0, base + WINDOW_REMAP_HIGH(i));
2499 for (i = 0; i < dram->num_cs; i++) {
2500 const struct mbus_dram_window *cs = dram->cs + i;
2502 writel((cs->base & 0xffff0000) |
2503 (cs->mbus_attr << 8) |
2504 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2505 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2507 win_enable &= ~(1 << i);
2508 win_protect |= 3 << (2 * i);
2511 writel(win_enable, base + WINDOW_BAR_ENABLE);
2512 msp->win_protect = win_protect;
2515 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2518 * Check whether we have a 14-bit coal limit field in bits
2519 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2520 * SDMA config register.
2522 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2523 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2524 msp->extended_rx_coal_limit = 1;
2526 msp->extended_rx_coal_limit = 0;
2529 * Check whether the MAC supports TX rate control, and if
2530 * yes, whether its associated registers are in the old or
2533 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2534 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2535 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2537 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2538 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2539 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2541 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2545 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2547 static int mv643xx_eth_version_printed;
2548 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2549 struct mv643xx_eth_shared_private *msp;
2550 const struct mbus_dram_target_info *dram;
2551 struct resource *res;
2554 if (!mv643xx_eth_version_printed++)
2555 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2556 mv643xx_eth_driver_version);
2559 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2564 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
2568 msp->base = ioremap(res->start, resource_size(res));
2569 if (msp->base == NULL)
2573 * (Re-)program MBUS remapping windows if we are asked to.
2575 dram = mv_mbus_dram_info();
2577 mv643xx_eth_conf_mbus_windows(msp, dram);
2579 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2580 pd->tx_csum_limit : 9 * 1024;
2581 infer_hw_params(msp);
2583 platform_set_drvdata(pdev, msp);
2593 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2595 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2603 static struct platform_driver mv643xx_eth_shared_driver = {
2604 .probe = mv643xx_eth_shared_probe,
2605 .remove = mv643xx_eth_shared_remove,
2607 .name = MV643XX_ETH_SHARED_NAME,
2608 .owner = THIS_MODULE,
2612 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2614 int addr_shift = 5 * mp->port_num;
2617 data = rdl(mp, PHY_ADDR);
2618 data &= ~(0x1f << addr_shift);
2619 data |= (phy_addr & 0x1f) << addr_shift;
2620 wrl(mp, PHY_ADDR, data);
2623 static int phy_addr_get(struct mv643xx_eth_private *mp)
2627 data = rdl(mp, PHY_ADDR);
2629 return (data >> (5 * mp->port_num)) & 0x1f;
2632 static void set_params(struct mv643xx_eth_private *mp,
2633 struct mv643xx_eth_platform_data *pd)
2635 struct net_device *dev = mp->dev;
2637 if (is_valid_ether_addr(pd->mac_addr))
2638 memcpy(dev->dev_addr, pd->mac_addr, 6);
2640 uc_addr_get(mp, dev->dev_addr);
2642 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2643 if (pd->rx_queue_size)
2644 mp->rx_ring_size = pd->rx_queue_size;
2645 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2646 mp->rx_desc_sram_size = pd->rx_sram_size;
2648 mp->rxq_count = pd->rx_queue_count ? : 1;
2650 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2651 if (pd->tx_queue_size)
2652 mp->tx_ring_size = pd->tx_queue_size;
2653 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2654 mp->tx_desc_sram_size = pd->tx_sram_size;
2656 mp->txq_count = pd->tx_queue_count ? : 1;
2659 static void mv643xx_eth_adjust_link(struct net_device *dev)
2661 struct mv643xx_eth_private *mp = netdev_priv(dev);
2663 mv643xx_adjust_pscr(mp);
2666 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2669 struct phy_device *phydev;
2673 char phy_id[MII_BUS_ID_SIZE + 3];
2675 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2676 start = phy_addr_get(mp) & 0x1f;
2679 start = phy_addr & 0x1f;
2683 /* Attempt to connect to the PHY using orion-mdio */
2685 for (i = 0; i < num; i++) {
2686 int addr = (start + i) & 0x1f;
2688 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2689 "orion-mdio-mii", addr);
2691 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2692 PHY_INTERFACE_MODE_GMII);
2693 if (!IS_ERR(phydev)) {
2694 phy_addr_set(mp, addr);
2702 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2704 struct phy_device *phy = mp->phy;
2709 phy->autoneg = AUTONEG_ENABLE;
2712 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2714 phy->autoneg = AUTONEG_DISABLE;
2715 phy->advertising = 0;
2717 phy->duplex = duplex;
2719 phy_start_aneg(phy);
2722 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2726 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2727 if (pscr & SERIAL_PORT_ENABLE) {
2728 pscr &= ~SERIAL_PORT_ENABLE;
2729 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2732 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2733 if (mp->phy == NULL) {
2734 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2735 if (speed == SPEED_1000)
2736 pscr |= SET_GMII_SPEED_TO_1000;
2737 else if (speed == SPEED_100)
2738 pscr |= SET_MII_SPEED_TO_100;
2740 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2742 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2743 if (duplex == DUPLEX_FULL)
2744 pscr |= SET_FULL_DUPLEX_MODE;
2747 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2750 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2751 .ndo_open = mv643xx_eth_open,
2752 .ndo_stop = mv643xx_eth_stop,
2753 .ndo_start_xmit = mv643xx_eth_xmit,
2754 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2755 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2756 .ndo_validate_addr = eth_validate_addr,
2757 .ndo_do_ioctl = mv643xx_eth_ioctl,
2758 .ndo_change_mtu = mv643xx_eth_change_mtu,
2759 .ndo_set_features = mv643xx_eth_set_features,
2760 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2761 .ndo_get_stats = mv643xx_eth_get_stats,
2762 #ifdef CONFIG_NET_POLL_CONTROLLER
2763 .ndo_poll_controller = mv643xx_eth_netpoll,
2767 static int mv643xx_eth_probe(struct platform_device *pdev)
2769 struct mv643xx_eth_platform_data *pd;
2770 struct mv643xx_eth_private *mp;
2771 struct net_device *dev;
2772 struct resource *res;
2775 pd = pdev->dev.platform_data;
2777 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2781 if (pd->shared == NULL) {
2782 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2786 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2790 mp = netdev_priv(dev);
2791 platform_set_drvdata(pdev, mp);
2793 mp->shared = platform_get_drvdata(pd->shared);
2794 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2795 mp->port_num = pd->port_number;
2800 * Start with a default rate, and if there is a clock, allow
2801 * it to override the default.
2803 mp->t_clk = 133000000;
2804 #if defined(CONFIG_HAVE_CLK)
2805 mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
2806 if (!IS_ERR(mp->clk)) {
2807 clk_prepare_enable(mp->clk);
2808 mp->t_clk = clk_get_rate(mp->clk);
2812 netif_set_real_num_tx_queues(dev, mp->txq_count);
2813 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2815 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2816 mp->phy = phy_scan(mp, pd->phy_addr);
2818 if (mp->phy != NULL)
2819 phy_init(mp, pd->speed, pd->duplex);
2821 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2823 init_pscr(mp, pd->speed, pd->duplex);
2826 mib_counters_clear(mp);
2828 init_timer(&mp->mib_counters_timer);
2829 mp->mib_counters_timer.data = (unsigned long)mp;
2830 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2831 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2832 add_timer(&mp->mib_counters_timer);
2834 spin_lock_init(&mp->mib_counters_lock);
2836 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2838 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2840 init_timer(&mp->rx_oom);
2841 mp->rx_oom.data = (unsigned long)mp;
2842 mp->rx_oom.function = oom_timer_wrapper;
2845 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2847 dev->irq = res->start;
2849 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2851 dev->watchdog_timeo = 2 * HZ;
2854 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2855 NETIF_F_RXCSUM | NETIF_F_LRO;
2856 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2857 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2859 dev->priv_flags |= IFF_UNICAST_FLT;
2861 SET_NETDEV_DEV(dev, &pdev->dev);
2863 if (mp->shared->win_protect)
2864 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2866 netif_carrier_off(dev);
2868 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2870 set_rx_coal(mp, 250);
2873 err = register_netdev(dev);
2877 netdev_notice(dev, "port %d with MAC address %pM\n",
2878 mp->port_num, dev->dev_addr);
2880 if (mp->tx_desc_sram_size > 0)
2881 netdev_notice(dev, "configured with sram\n");
2886 #if defined(CONFIG_HAVE_CLK)
2887 if (!IS_ERR(mp->clk)) {
2888 clk_disable_unprepare(mp->clk);
2897 static int mv643xx_eth_remove(struct platform_device *pdev)
2899 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2901 unregister_netdev(mp->dev);
2902 if (mp->phy != NULL)
2903 phy_detach(mp->phy);
2904 cancel_work_sync(&mp->tx_timeout_task);
2906 #if defined(CONFIG_HAVE_CLK)
2907 if (!IS_ERR(mp->clk)) {
2908 clk_disable_unprepare(mp->clk);
2913 free_netdev(mp->dev);
2915 platform_set_drvdata(pdev, NULL);
2920 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2922 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2924 /* Mask all interrupts on ethernet port */
2925 wrlp(mp, INT_MASK, 0);
2928 if (netif_running(mp->dev))
2932 static struct platform_driver mv643xx_eth_driver = {
2933 .probe = mv643xx_eth_probe,
2934 .remove = mv643xx_eth_remove,
2935 .shutdown = mv643xx_eth_shutdown,
2937 .name = MV643XX_ETH_NAME,
2938 .owner = THIS_MODULE,
2942 static int __init mv643xx_eth_init_module(void)
2946 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2948 rc = platform_driver_register(&mv643xx_eth_driver);
2950 platform_driver_unregister(&mv643xx_eth_shared_driver);
2955 module_init(mv643xx_eth_init_module);
2957 static void __exit mv643xx_eth_cleanup_module(void)
2959 platform_driver_unregister(&mv643xx_eth_driver);
2960 platform_driver_unregister(&mv643xx_eth_shared_driver);
2962 module_exit(mv643xx_eth_cleanup_module);
2964 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2965 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2966 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2967 MODULE_LICENSE("GPL");
2968 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2969 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);