2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41 #include <linux/init.h>
42 #include <linux/dma-mapping.h>
45 #include <linux/tcp.h>
46 #include <linux/udp.h>
47 #include <linux/etherdevice.h>
48 #include <linux/delay.h>
49 #include <linux/ethtool.h>
50 #include <linux/platform_device.h>
51 #include <linux/module.h>
52 #include <linux/kernel.h>
53 #include <linux/spinlock.h>
54 #include <linux/workqueue.h>
55 #include <linux/phy.h>
56 #include <linux/mv643xx_eth.h>
58 #include <linux/interrupt.h>
59 #include <linux/types.h>
60 #include <linux/slab.h>
61 #include <linux/clk.h>
63 #include <linux/of_irq.h>
64 #include <linux/of_net.h>
65 #include <linux/of_mdio.h>
67 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
68 static char mv643xx_eth_driver_version[] = "1.4";
72 * Registers shared between all ports.
74 #define PHY_ADDR 0x0000
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
85 #define PORT_CONFIG 0x0000
86 #define UNICAST_PROMISCUOUS_MODE 0x00000001
87 #define PORT_CONFIG_EXT 0x0004
88 #define MAC_ADDR_LOW 0x0014
89 #define MAC_ADDR_HIGH 0x0018
90 #define SDMA_CONFIG 0x001c
91 #define TX_BURST_SIZE_16_64BIT 0x01000000
92 #define TX_BURST_SIZE_4_64BIT 0x00800000
93 #define BLM_TX_NO_SWAP 0x00000020
94 #define BLM_RX_NO_SWAP 0x00000010
95 #define RX_BURST_SIZE_16_64BIT 0x00000008
96 #define RX_BURST_SIZE_4_64BIT 0x00000004
97 #define PORT_SERIAL_CONTROL 0x003c
98 #define SET_MII_SPEED_TO_100 0x01000000
99 #define SET_GMII_SPEED_TO_1000 0x00800000
100 #define SET_FULL_DUPLEX_MODE 0x00200000
101 #define MAX_RX_PACKET_9700BYTE 0x000a0000
102 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
103 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
104 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
105 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
106 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
107 #define FORCE_LINK_PASS 0x00000002
108 #define SERIAL_PORT_ENABLE 0x00000001
109 #define PORT_STATUS 0x0044
110 #define TX_FIFO_EMPTY 0x00000400
111 #define TX_IN_PROGRESS 0x00000080
112 #define PORT_SPEED_MASK 0x00000030
113 #define PORT_SPEED_1000 0x00000010
114 #define PORT_SPEED_100 0x00000020
115 #define PORT_SPEED_10 0x00000000
116 #define FLOW_CONTROL_ENABLED 0x00000008
117 #define FULL_DUPLEX 0x00000004
118 #define LINK_UP 0x00000002
119 #define TXQ_COMMAND 0x0048
120 #define TXQ_FIX_PRIO_CONF 0x004c
121 #define PORT_SERIAL_CONTROL1 0x004c
122 #define CLK125_BYPASS_EN 0x00000010
123 #define TX_BW_RATE 0x0050
124 #define TX_BW_MTU 0x0058
125 #define TX_BW_BURST 0x005c
126 #define INT_CAUSE 0x0060
127 #define INT_TX_END 0x07f80000
128 #define INT_TX_END_0 0x00080000
129 #define INT_RX 0x000003fc
130 #define INT_RX_0 0x00000004
131 #define INT_EXT 0x00000002
132 #define INT_CAUSE_EXT 0x0064
133 #define INT_EXT_LINK_PHY 0x00110000
134 #define INT_EXT_TX 0x000000ff
135 #define INT_MASK 0x0068
136 #define INT_MASK_EXT 0x006c
137 #define TX_FIFO_URGENT_THRESHOLD 0x0074
138 #define RX_DISCARD_FRAME_CNT 0x0084
139 #define RX_OVERRUN_FRAME_CNT 0x0088
140 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
141 #define TX_BW_RATE_MOVED 0x00e0
142 #define TX_BW_MTU_MOVED 0x00e8
143 #define TX_BW_BURST_MOVED 0x00ec
144 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
145 #define RXQ_COMMAND 0x0280
146 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
147 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
148 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
149 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
152 * Misc per-port registers.
154 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
155 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
156 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
157 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
161 * SDMA configuration register default value.
163 #if defined(__BIG_ENDIAN)
164 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
165 (RX_BURST_SIZE_4_64BIT | \
166 TX_BURST_SIZE_4_64BIT)
167 #elif defined(__LITTLE_ENDIAN)
168 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
169 (RX_BURST_SIZE_4_64BIT | \
172 TX_BURST_SIZE_4_64BIT)
174 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
181 #define DEFAULT_RX_QUEUE_SIZE 128
182 #define DEFAULT_TX_QUEUE_SIZE 256
183 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
189 #if defined(__BIG_ENDIAN)
191 u16 byte_cnt; /* Descriptor buffer byte count */
192 u16 buf_size; /* Buffer size */
193 u32 cmd_sts; /* Descriptor command status */
194 u32 next_desc_ptr; /* Next descriptor pointer */
195 u32 buf_ptr; /* Descriptor buffer pointer */
199 u16 byte_cnt; /* buffer byte count */
200 u16 l4i_chk; /* CPU provided TCP checksum */
201 u32 cmd_sts; /* Command/status field */
202 u32 next_desc_ptr; /* Pointer to next descriptor */
203 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 #elif defined(__LITTLE_ENDIAN)
207 u32 cmd_sts; /* Descriptor command status */
208 u16 buf_size; /* Buffer size */
209 u16 byte_cnt; /* Descriptor buffer byte count */
210 u32 buf_ptr; /* Descriptor buffer pointer */
211 u32 next_desc_ptr; /* Next descriptor pointer */
215 u32 cmd_sts; /* Command/status field */
216 u16 l4i_chk; /* CPU provided TCP checksum */
217 u16 byte_cnt; /* buffer byte count */
218 u32 buf_ptr; /* pointer to buffer for this descriptor*/
219 u32 next_desc_ptr; /* Pointer to next descriptor */
222 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
225 /* RX & TX descriptor command */
226 #define BUFFER_OWNED_BY_DMA 0x80000000
228 /* RX & TX descriptor status */
229 #define ERROR_SUMMARY 0x00000001
231 /* RX descriptor status */
232 #define LAYER_4_CHECKSUM_OK 0x40000000
233 #define RX_ENABLE_INTERRUPT 0x20000000
234 #define RX_FIRST_DESC 0x08000000
235 #define RX_LAST_DESC 0x04000000
236 #define RX_IP_HDR_OK 0x02000000
237 #define RX_PKT_IS_IPV4 0x01000000
238 #define RX_PKT_IS_ETHERNETV2 0x00800000
239 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
240 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
241 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
243 /* TX descriptor command */
244 #define TX_ENABLE_INTERRUPT 0x00800000
245 #define GEN_CRC 0x00400000
246 #define TX_FIRST_DESC 0x00200000
247 #define TX_LAST_DESC 0x00100000
248 #define ZERO_PADDING 0x00080000
249 #define GEN_IP_V4_CHECKSUM 0x00040000
250 #define GEN_TCP_UDP_CHECKSUM 0x00020000
251 #define UDP_FRAME 0x00010000
252 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
253 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
255 #define TX_IHL_SHIFT 11
258 /* global *******************************************************************/
259 struct mv643xx_eth_shared_private {
261 * Ethernet controller base address.
266 * Per-port MBUS window access register value.
271 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
279 #define TX_BW_CONTROL_ABSENT 0
280 #define TX_BW_CONTROL_OLD_LAYOUT 1
281 #define TX_BW_CONTROL_NEW_LAYOUT 2
283 static int mv643xx_eth_open(struct net_device *dev);
284 static int mv643xx_eth_stop(struct net_device *dev);
287 /* per-port *****************************************************************/
288 struct mib_counters {
289 u64 good_octets_received;
290 u32 bad_octets_received;
291 u32 internal_mac_transmit_err;
292 u32 good_frames_received;
293 u32 bad_frames_received;
294 u32 broadcast_frames_received;
295 u32 multicast_frames_received;
296 u32 frames_64_octets;
297 u32 frames_65_to_127_octets;
298 u32 frames_128_to_255_octets;
299 u32 frames_256_to_511_octets;
300 u32 frames_512_to_1023_octets;
301 u32 frames_1024_to_max_octets;
302 u64 good_octets_sent;
303 u32 good_frames_sent;
304 u32 excessive_collision;
305 u32 multicast_frames_sent;
306 u32 broadcast_frames_sent;
307 u32 unrec_mac_control_received;
309 u32 good_fc_received;
311 u32 undersize_received;
312 u32 fragments_received;
313 u32 oversize_received;
315 u32 mac_receive_error;
319 /* Non MIB hardware counters */
333 struct rx_desc *rx_desc_area;
334 dma_addr_t rx_desc_dma;
335 int rx_desc_area_size;
336 struct sk_buff **rx_skb;
348 struct tx_desc *tx_desc_area;
349 dma_addr_t tx_desc_dma;
350 int tx_desc_area_size;
352 struct sk_buff_head tx_skb;
354 unsigned long tx_packets;
355 unsigned long tx_bytes;
356 unsigned long tx_dropped;
359 struct mv643xx_eth_private {
360 struct mv643xx_eth_shared_private *shared;
364 struct net_device *dev;
366 struct phy_device *phy;
368 struct timer_list mib_counters_timer;
369 spinlock_t mib_counters_lock;
370 struct mib_counters mib_counters;
372 struct work_struct tx_timeout_task;
374 struct napi_struct napi;
389 unsigned long rx_desc_sram_addr;
390 int rx_desc_sram_size;
392 struct timer_list rx_oom;
393 struct rx_queue rxq[8];
399 unsigned long tx_desc_sram_addr;
400 int tx_desc_sram_size;
402 struct tx_queue txq[8];
405 * Hardware-specific parameters.
412 /* port register accessors **************************************************/
413 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
415 return readl(mp->shared->base + offset);
418 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
420 return readl(mp->base + offset);
423 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
425 writel(data, mp->shared->base + offset);
428 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
430 writel(data, mp->base + offset);
434 /* rxq/txq helper functions *************************************************/
435 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
437 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
440 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
442 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
445 static void rxq_enable(struct rx_queue *rxq)
447 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
448 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
451 static void rxq_disable(struct rx_queue *rxq)
453 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
454 u8 mask = 1 << rxq->index;
456 wrlp(mp, RXQ_COMMAND, mask << 8);
457 while (rdlp(mp, RXQ_COMMAND) & mask)
461 static void txq_reset_hw_ptr(struct tx_queue *txq)
463 struct mv643xx_eth_private *mp = txq_to_mp(txq);
466 addr = (u32)txq->tx_desc_dma;
467 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
468 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
471 static void txq_enable(struct tx_queue *txq)
473 struct mv643xx_eth_private *mp = txq_to_mp(txq);
474 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
477 static void txq_disable(struct tx_queue *txq)
479 struct mv643xx_eth_private *mp = txq_to_mp(txq);
480 u8 mask = 1 << txq->index;
482 wrlp(mp, TXQ_COMMAND, mask << 8);
483 while (rdlp(mp, TXQ_COMMAND) & mask)
487 static void txq_maybe_wake(struct tx_queue *txq)
489 struct mv643xx_eth_private *mp = txq_to_mp(txq);
490 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
492 if (netif_tx_queue_stopped(nq)) {
493 __netif_tx_lock(nq, smp_processor_id());
494 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
495 netif_tx_wake_queue(nq);
496 __netif_tx_unlock(nq);
500 static int rxq_process(struct rx_queue *rxq, int budget)
502 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
503 struct net_device_stats *stats = &mp->dev->stats;
507 while (rx < budget && rxq->rx_desc_count) {
508 struct rx_desc *rx_desc;
509 unsigned int cmd_sts;
513 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
515 cmd_sts = rx_desc->cmd_sts;
516 if (cmd_sts & BUFFER_OWNED_BY_DMA)
520 skb = rxq->rx_skb[rxq->rx_curr_desc];
521 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
524 if (rxq->rx_curr_desc == rxq->rx_ring_size)
525 rxq->rx_curr_desc = 0;
527 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
528 rx_desc->buf_size, DMA_FROM_DEVICE);
529 rxq->rx_desc_count--;
532 mp->work_rx_refill |= 1 << rxq->index;
534 byte_cnt = rx_desc->byte_cnt;
539 * Note that the descriptor byte count includes 2 dummy
540 * bytes automatically inserted by the hardware at the
541 * start of the packet (which we don't count), and a 4
542 * byte CRC at the end of the packet (which we do count).
545 stats->rx_bytes += byte_cnt - 2;
548 * In case we received a packet without first / last bits
549 * on, or the error summary bit is set, the packet needs
552 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
553 != (RX_FIRST_DESC | RX_LAST_DESC))
557 * The -4 is for the CRC in the trailer of the
560 skb_put(skb, byte_cnt - 2 - 4);
562 if (cmd_sts & LAYER_4_CHECKSUM_OK)
563 skb->ip_summed = CHECKSUM_UNNECESSARY;
564 skb->protocol = eth_type_trans(skb, mp->dev);
566 napi_gro_receive(&mp->napi, skb);
573 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
574 (RX_FIRST_DESC | RX_LAST_DESC)) {
577 "received packet spanning multiple descriptors\n");
580 if (cmd_sts & ERROR_SUMMARY)
587 mp->work_rx &= ~(1 << rxq->index);
592 static int rxq_refill(struct rx_queue *rxq, int budget)
594 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
598 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
601 struct rx_desc *rx_desc;
604 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
612 skb_reserve(skb, SKB_DMA_REALIGN);
615 rxq->rx_desc_count++;
617 rx = rxq->rx_used_desc++;
618 if (rxq->rx_used_desc == rxq->rx_ring_size)
619 rxq->rx_used_desc = 0;
621 rx_desc = rxq->rx_desc_area + rx;
623 size = skb_end_pointer(skb) - skb->data;
624 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
627 rx_desc->buf_size = size;
628 rxq->rx_skb[rx] = skb;
630 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
634 * The hardware automatically prepends 2 bytes of
635 * dummy data to each received packet, so that the
636 * IP header ends up 16-byte aligned.
641 if (refilled < budget)
642 mp->work_rx_refill &= ~(1 << rxq->index);
649 /* tx ***********************************************************************/
650 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
654 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
655 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
657 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
664 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
666 struct mv643xx_eth_private *mp = txq_to_mp(txq);
667 int nr_frags = skb_shinfo(skb)->nr_frags;
670 for (frag = 0; frag < nr_frags; frag++) {
671 skb_frag_t *this_frag;
673 struct tx_desc *desc;
675 this_frag = &skb_shinfo(skb)->frags[frag];
676 tx_index = txq->tx_curr_desc++;
677 if (txq->tx_curr_desc == txq->tx_ring_size)
678 txq->tx_curr_desc = 0;
679 desc = &txq->tx_desc_area[tx_index];
682 * The last fragment will generate an interrupt
683 * which will free the skb on TX completion.
685 if (frag == nr_frags - 1) {
686 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
687 ZERO_PADDING | TX_LAST_DESC |
690 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
694 desc->byte_cnt = skb_frag_size(this_frag);
695 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
697 skb_frag_size(this_frag),
702 static inline __be16 sum16_as_be(__sum16 sum)
704 return (__force __be16)sum;
707 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
709 struct mv643xx_eth_private *mp = txq_to_mp(txq);
710 int nr_frags = skb_shinfo(skb)->nr_frags;
712 struct tx_desc *desc;
717 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
720 if (skb->ip_summed == CHECKSUM_PARTIAL) {
724 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
725 skb->protocol != htons(ETH_P_8021Q));
727 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
728 tag_bytes = hdr_len - ETH_HLEN;
729 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
730 unlikely(tag_bytes & ~12)) {
731 if (skb_checksum_help(skb) == 0)
733 dev_kfree_skb_any(skb);
738 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
740 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
742 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
744 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
746 switch (ip_hdr(skb)->protocol) {
748 cmd_sts |= UDP_FRAME;
749 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
752 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
759 /* Errata BTS #50, IHL must be 5 if no HW checksum */
760 cmd_sts |= 5 << TX_IHL_SHIFT;
763 tx_index = txq->tx_curr_desc++;
764 if (txq->tx_curr_desc == txq->tx_ring_size)
765 txq->tx_curr_desc = 0;
766 desc = &txq->tx_desc_area[tx_index];
769 txq_submit_frag_skb(txq, skb);
770 length = skb_headlen(skb);
772 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
776 desc->l4i_chk = l4i_chk;
777 desc->byte_cnt = length;
778 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
779 length, DMA_TO_DEVICE);
781 __skb_queue_tail(&txq->tx_skb, skb);
783 skb_tx_timestamp(skb);
785 /* ensure all other descriptors are written before first cmd_sts */
787 desc->cmd_sts = cmd_sts;
789 /* clear TX_END status */
790 mp->work_tx_end &= ~(1 << txq->index);
792 /* ensure all descriptors are written before poking hardware */
796 txq->tx_desc_count += nr_frags + 1;
801 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
803 struct mv643xx_eth_private *mp = netdev_priv(dev);
805 struct tx_queue *txq;
806 struct netdev_queue *nq;
808 queue = skb_get_queue_mapping(skb);
809 txq = mp->txq + queue;
810 nq = netdev_get_tx_queue(dev, queue);
812 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
814 netdev_printk(KERN_DEBUG, dev,
815 "failed to linearize skb with tiny unaligned fragment\n");
816 return NETDEV_TX_BUSY;
819 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
821 netdev_err(dev, "tx queue full?!\n");
822 dev_kfree_skb_any(skb);
828 if (!txq_submit_skb(txq, skb)) {
831 txq->tx_bytes += length;
834 entries_left = txq->tx_ring_size - txq->tx_desc_count;
835 if (entries_left < MAX_SKB_FRAGS + 1)
836 netif_tx_stop_queue(nq);
843 /* tx napi ******************************************************************/
844 static void txq_kick(struct tx_queue *txq)
846 struct mv643xx_eth_private *mp = txq_to_mp(txq);
847 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
851 __netif_tx_lock(nq, smp_processor_id());
853 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
856 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
857 expected_ptr = (u32)txq->tx_desc_dma +
858 txq->tx_curr_desc * sizeof(struct tx_desc);
860 if (hw_desc_ptr != expected_ptr)
864 __netif_tx_unlock(nq);
866 mp->work_tx_end &= ~(1 << txq->index);
869 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
871 struct mv643xx_eth_private *mp = txq_to_mp(txq);
872 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
875 __netif_tx_lock_bh(nq);
878 while (reclaimed < budget && txq->tx_desc_count > 0) {
880 struct tx_desc *desc;
884 tx_index = txq->tx_used_desc;
885 desc = &txq->tx_desc_area[tx_index];
886 cmd_sts = desc->cmd_sts;
888 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
891 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
894 txq->tx_used_desc = tx_index + 1;
895 if (txq->tx_used_desc == txq->tx_ring_size)
896 txq->tx_used_desc = 0;
899 txq->tx_desc_count--;
902 if (cmd_sts & TX_LAST_DESC)
903 skb = __skb_dequeue(&txq->tx_skb);
905 if (cmd_sts & ERROR_SUMMARY) {
906 netdev_info(mp->dev, "tx error\n");
907 mp->dev->stats.tx_errors++;
910 if (cmd_sts & TX_FIRST_DESC) {
911 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
912 desc->byte_cnt, DMA_TO_DEVICE);
914 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
915 desc->byte_cnt, DMA_TO_DEVICE);
921 __netif_tx_unlock_bh(nq);
923 if (reclaimed < budget)
924 mp->work_tx &= ~(1 << txq->index);
930 /* tx rate control **********************************************************/
932 * Set total maximum TX rate (shared by all TX queues for this port)
933 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
935 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
941 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
942 if (token_rate > 1023)
945 mtu = (mp->dev->mtu + 255) >> 8;
949 bucket_size = (burst + 255) >> 8;
950 if (bucket_size > 65535)
953 switch (mp->shared->tx_bw_control) {
954 case TX_BW_CONTROL_OLD_LAYOUT:
955 wrlp(mp, TX_BW_RATE, token_rate);
956 wrlp(mp, TX_BW_MTU, mtu);
957 wrlp(mp, TX_BW_BURST, bucket_size);
959 case TX_BW_CONTROL_NEW_LAYOUT:
960 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
961 wrlp(mp, TX_BW_MTU_MOVED, mtu);
962 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
967 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
969 struct mv643xx_eth_private *mp = txq_to_mp(txq);
973 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
974 if (token_rate > 1023)
977 bucket_size = (burst + 255) >> 8;
978 if (bucket_size > 65535)
981 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
982 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
985 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
987 struct mv643xx_eth_private *mp = txq_to_mp(txq);
992 * Turn on fixed priority mode.
995 switch (mp->shared->tx_bw_control) {
996 case TX_BW_CONTROL_OLD_LAYOUT:
997 off = TXQ_FIX_PRIO_CONF;
999 case TX_BW_CONTROL_NEW_LAYOUT:
1000 off = TXQ_FIX_PRIO_CONF_MOVED;
1005 val = rdlp(mp, off);
1006 val |= 1 << txq->index;
1012 /* mii management interface *************************************************/
1013 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1015 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1016 u32 autoneg_disable = FORCE_LINK_PASS |
1017 DISABLE_AUTO_NEG_SPEED_GMII |
1018 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1019 DISABLE_AUTO_NEG_FOR_DUPLEX;
1021 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1022 /* enable auto negotiation */
1023 pscr &= ~autoneg_disable;
1027 pscr |= autoneg_disable;
1029 if (mp->phy->speed == SPEED_1000) {
1030 /* force gigabit, half duplex not supported */
1031 pscr |= SET_GMII_SPEED_TO_1000;
1032 pscr |= SET_FULL_DUPLEX_MODE;
1036 pscr &= ~SET_GMII_SPEED_TO_1000;
1038 if (mp->phy->speed == SPEED_100)
1039 pscr |= SET_MII_SPEED_TO_100;
1041 pscr &= ~SET_MII_SPEED_TO_100;
1043 if (mp->phy->duplex == DUPLEX_FULL)
1044 pscr |= SET_FULL_DUPLEX_MODE;
1046 pscr &= ~SET_FULL_DUPLEX_MODE;
1049 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1052 /* statistics ***************************************************************/
1053 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1055 struct mv643xx_eth_private *mp = netdev_priv(dev);
1056 struct net_device_stats *stats = &dev->stats;
1057 unsigned long tx_packets = 0;
1058 unsigned long tx_bytes = 0;
1059 unsigned long tx_dropped = 0;
1062 for (i = 0; i < mp->txq_count; i++) {
1063 struct tx_queue *txq = mp->txq + i;
1065 tx_packets += txq->tx_packets;
1066 tx_bytes += txq->tx_bytes;
1067 tx_dropped += txq->tx_dropped;
1070 stats->tx_packets = tx_packets;
1071 stats->tx_bytes = tx_bytes;
1072 stats->tx_dropped = tx_dropped;
1077 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1079 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1082 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1086 for (i = 0; i < 0x80; i += 4)
1089 /* Clear non MIB hw counters also */
1090 rdlp(mp, RX_DISCARD_FRAME_CNT);
1091 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1094 static void mib_counters_update(struct mv643xx_eth_private *mp)
1096 struct mib_counters *p = &mp->mib_counters;
1098 spin_lock_bh(&mp->mib_counters_lock);
1099 p->good_octets_received += mib_read(mp, 0x00);
1100 p->bad_octets_received += mib_read(mp, 0x08);
1101 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1102 p->good_frames_received += mib_read(mp, 0x10);
1103 p->bad_frames_received += mib_read(mp, 0x14);
1104 p->broadcast_frames_received += mib_read(mp, 0x18);
1105 p->multicast_frames_received += mib_read(mp, 0x1c);
1106 p->frames_64_octets += mib_read(mp, 0x20);
1107 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1108 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1109 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1110 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1111 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1112 p->good_octets_sent += mib_read(mp, 0x38);
1113 p->good_frames_sent += mib_read(mp, 0x40);
1114 p->excessive_collision += mib_read(mp, 0x44);
1115 p->multicast_frames_sent += mib_read(mp, 0x48);
1116 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1117 p->unrec_mac_control_received += mib_read(mp, 0x50);
1118 p->fc_sent += mib_read(mp, 0x54);
1119 p->good_fc_received += mib_read(mp, 0x58);
1120 p->bad_fc_received += mib_read(mp, 0x5c);
1121 p->undersize_received += mib_read(mp, 0x60);
1122 p->fragments_received += mib_read(mp, 0x64);
1123 p->oversize_received += mib_read(mp, 0x68);
1124 p->jabber_received += mib_read(mp, 0x6c);
1125 p->mac_receive_error += mib_read(mp, 0x70);
1126 p->bad_crc_event += mib_read(mp, 0x74);
1127 p->collision += mib_read(mp, 0x78);
1128 p->late_collision += mib_read(mp, 0x7c);
1129 /* Non MIB hardware counters */
1130 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1131 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1132 spin_unlock_bh(&mp->mib_counters_lock);
1135 static void mib_counters_timer_wrapper(unsigned long _mp)
1137 struct mv643xx_eth_private *mp = (void *)_mp;
1138 mib_counters_update(mp);
1139 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1143 /* interrupt coalescing *****************************************************/
1145 * Hardware coalescing parameters are set in units of 64 t_clk
1148 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1150 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1152 * In the ->set*() methods, we round the computed register value
1153 * to the nearest integer.
1155 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1157 u32 val = rdlp(mp, SDMA_CONFIG);
1160 if (mp->shared->extended_rx_coal_limit)
1161 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1163 temp = (val & 0x003fff00) >> 8;
1166 do_div(temp, mp->t_clk);
1168 return (unsigned int)temp;
1171 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1176 temp = (u64)usec * mp->t_clk;
1178 do_div(temp, 64000000);
1180 val = rdlp(mp, SDMA_CONFIG);
1181 if (mp->shared->extended_rx_coal_limit) {
1185 val |= (temp & 0x8000) << 10;
1186 val |= (temp & 0x7fff) << 7;
1191 val |= (temp & 0x3fff) << 8;
1193 wrlp(mp, SDMA_CONFIG, val);
1196 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1200 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1202 do_div(temp, mp->t_clk);
1204 return (unsigned int)temp;
1207 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1211 temp = (u64)usec * mp->t_clk;
1213 do_div(temp, 64000000);
1218 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1222 /* ethtool ******************************************************************/
1223 struct mv643xx_eth_stats {
1224 char stat_string[ETH_GSTRING_LEN];
1231 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1232 offsetof(struct net_device, stats.m), -1 }
1234 #define MIBSTAT(m) \
1235 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1236 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1238 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1247 MIBSTAT(good_octets_received),
1248 MIBSTAT(bad_octets_received),
1249 MIBSTAT(internal_mac_transmit_err),
1250 MIBSTAT(good_frames_received),
1251 MIBSTAT(bad_frames_received),
1252 MIBSTAT(broadcast_frames_received),
1253 MIBSTAT(multicast_frames_received),
1254 MIBSTAT(frames_64_octets),
1255 MIBSTAT(frames_65_to_127_octets),
1256 MIBSTAT(frames_128_to_255_octets),
1257 MIBSTAT(frames_256_to_511_octets),
1258 MIBSTAT(frames_512_to_1023_octets),
1259 MIBSTAT(frames_1024_to_max_octets),
1260 MIBSTAT(good_octets_sent),
1261 MIBSTAT(good_frames_sent),
1262 MIBSTAT(excessive_collision),
1263 MIBSTAT(multicast_frames_sent),
1264 MIBSTAT(broadcast_frames_sent),
1265 MIBSTAT(unrec_mac_control_received),
1267 MIBSTAT(good_fc_received),
1268 MIBSTAT(bad_fc_received),
1269 MIBSTAT(undersize_received),
1270 MIBSTAT(fragments_received),
1271 MIBSTAT(oversize_received),
1272 MIBSTAT(jabber_received),
1273 MIBSTAT(mac_receive_error),
1274 MIBSTAT(bad_crc_event),
1276 MIBSTAT(late_collision),
1277 MIBSTAT(rx_discard),
1278 MIBSTAT(rx_overrun),
1282 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1283 struct ethtool_cmd *cmd)
1287 err = phy_read_status(mp->phy);
1289 err = phy_ethtool_gset(mp->phy, cmd);
1292 * The MAC does not support 1000baseT_Half.
1294 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1295 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1301 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1302 struct ethtool_cmd *cmd)
1306 port_status = rdlp(mp, PORT_STATUS);
1308 cmd->supported = SUPPORTED_MII;
1309 cmd->advertising = ADVERTISED_MII;
1310 switch (port_status & PORT_SPEED_MASK) {
1312 ethtool_cmd_speed_set(cmd, SPEED_10);
1314 case PORT_SPEED_100:
1315 ethtool_cmd_speed_set(cmd, SPEED_100);
1317 case PORT_SPEED_1000:
1318 ethtool_cmd_speed_set(cmd, SPEED_1000);
1324 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1325 cmd->port = PORT_MII;
1326 cmd->phy_address = 0;
1327 cmd->transceiver = XCVR_INTERNAL;
1328 cmd->autoneg = AUTONEG_DISABLE;
1336 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1338 struct mv643xx_eth_private *mp = netdev_priv(dev);
1342 phy_ethtool_get_wol(mp->phy, wol);
1346 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1348 struct mv643xx_eth_private *mp = netdev_priv(dev);
1351 if (mp->phy == NULL)
1354 err = phy_ethtool_set_wol(mp->phy, wol);
1355 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1356 * this debugging hint is useful to have.
1358 if (err == -EOPNOTSUPP)
1359 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1364 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1366 struct mv643xx_eth_private *mp = netdev_priv(dev);
1368 if (mp->phy != NULL)
1369 return mv643xx_eth_get_settings_phy(mp, cmd);
1371 return mv643xx_eth_get_settings_phyless(mp, cmd);
1375 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1377 struct mv643xx_eth_private *mp = netdev_priv(dev);
1380 if (mp->phy == NULL)
1384 * The MAC does not support 1000baseT_Half.
1386 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1388 ret = phy_ethtool_sset(mp->phy, cmd);
1390 mv643xx_adjust_pscr(mp);
1394 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1395 struct ethtool_drvinfo *drvinfo)
1397 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1398 sizeof(drvinfo->driver));
1399 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1400 sizeof(drvinfo->version));
1401 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1402 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1403 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1406 static int mv643xx_eth_nway_reset(struct net_device *dev)
1408 struct mv643xx_eth_private *mp = netdev_priv(dev);
1410 if (mp->phy == NULL)
1413 return genphy_restart_aneg(mp->phy);
1417 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1419 struct mv643xx_eth_private *mp = netdev_priv(dev);
1421 ec->rx_coalesce_usecs = get_rx_coal(mp);
1422 ec->tx_coalesce_usecs = get_tx_coal(mp);
1428 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1430 struct mv643xx_eth_private *mp = netdev_priv(dev);
1432 set_rx_coal(mp, ec->rx_coalesce_usecs);
1433 set_tx_coal(mp, ec->tx_coalesce_usecs);
1439 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1441 struct mv643xx_eth_private *mp = netdev_priv(dev);
1443 er->rx_max_pending = 4096;
1444 er->tx_max_pending = 4096;
1446 er->rx_pending = mp->rx_ring_size;
1447 er->tx_pending = mp->tx_ring_size;
1451 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1453 struct mv643xx_eth_private *mp = netdev_priv(dev);
1455 if (er->rx_mini_pending || er->rx_jumbo_pending)
1458 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1459 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1461 if (netif_running(dev)) {
1462 mv643xx_eth_stop(dev);
1463 if (mv643xx_eth_open(dev)) {
1465 "fatal error on re-opening device after ring param change\n");
1475 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1477 struct mv643xx_eth_private *mp = netdev_priv(dev);
1478 bool rx_csum = features & NETIF_F_RXCSUM;
1480 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1485 static void mv643xx_eth_get_strings(struct net_device *dev,
1486 uint32_t stringset, uint8_t *data)
1490 if (stringset == ETH_SS_STATS) {
1491 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1492 memcpy(data + i * ETH_GSTRING_LEN,
1493 mv643xx_eth_stats[i].stat_string,
1499 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1500 struct ethtool_stats *stats,
1503 struct mv643xx_eth_private *mp = netdev_priv(dev);
1506 mv643xx_eth_get_stats(dev);
1507 mib_counters_update(mp);
1509 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1510 const struct mv643xx_eth_stats *stat;
1513 stat = mv643xx_eth_stats + i;
1515 if (stat->netdev_off >= 0)
1516 p = ((void *)mp->dev) + stat->netdev_off;
1518 p = ((void *)mp) + stat->mp_off;
1520 data[i] = (stat->sizeof_stat == 8) ?
1521 *(uint64_t *)p : *(uint32_t *)p;
1525 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1527 if (sset == ETH_SS_STATS)
1528 return ARRAY_SIZE(mv643xx_eth_stats);
1533 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1534 .get_settings = mv643xx_eth_get_settings,
1535 .set_settings = mv643xx_eth_set_settings,
1536 .get_drvinfo = mv643xx_eth_get_drvinfo,
1537 .nway_reset = mv643xx_eth_nway_reset,
1538 .get_link = ethtool_op_get_link,
1539 .get_coalesce = mv643xx_eth_get_coalesce,
1540 .set_coalesce = mv643xx_eth_set_coalesce,
1541 .get_ringparam = mv643xx_eth_get_ringparam,
1542 .set_ringparam = mv643xx_eth_set_ringparam,
1543 .get_strings = mv643xx_eth_get_strings,
1544 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1545 .get_sset_count = mv643xx_eth_get_sset_count,
1546 .get_ts_info = ethtool_op_get_ts_info,
1547 .get_wol = mv643xx_eth_get_wol,
1548 .set_wol = mv643xx_eth_set_wol,
1552 /* address handling *********************************************************/
1553 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1555 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1556 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1558 addr[0] = (mac_h >> 24) & 0xff;
1559 addr[1] = (mac_h >> 16) & 0xff;
1560 addr[2] = (mac_h >> 8) & 0xff;
1561 addr[3] = mac_h & 0xff;
1562 addr[4] = (mac_l >> 8) & 0xff;
1563 addr[5] = mac_l & 0xff;
1566 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1568 wrlp(mp, MAC_ADDR_HIGH,
1569 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1570 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1573 static u32 uc_addr_filter_mask(struct net_device *dev)
1575 struct netdev_hw_addr *ha;
1578 if (dev->flags & IFF_PROMISC)
1581 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1582 netdev_for_each_uc_addr(ha, dev) {
1583 if (memcmp(dev->dev_addr, ha->addr, 5))
1585 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1588 nibbles |= 1 << (ha->addr[5] & 0x0f);
1594 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1596 struct mv643xx_eth_private *mp = netdev_priv(dev);
1601 uc_addr_set(mp, dev->dev_addr);
1603 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1605 nibbles = uc_addr_filter_mask(dev);
1607 port_config |= UNICAST_PROMISCUOUS_MODE;
1611 for (i = 0; i < 16; i += 4) {
1612 int off = UNICAST_TABLE(mp->port_num) + i;
1629 wrlp(mp, PORT_CONFIG, port_config);
1632 static int addr_crc(unsigned char *addr)
1637 for (i = 0; i < 6; i++) {
1640 crc = (crc ^ addr[i]) << 8;
1641 for (j = 7; j >= 0; j--) {
1642 if (crc & (0x100 << j))
1650 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1652 struct mv643xx_eth_private *mp = netdev_priv(dev);
1655 struct netdev_hw_addr *ha;
1658 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1663 port_num = mp->port_num;
1664 accept = 0x01010101;
1665 for (i = 0; i < 0x100; i += 4) {
1666 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1667 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1672 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1673 if (mc_spec == NULL)
1675 mc_other = mc_spec + (0x100 >> 2);
1677 memset(mc_spec, 0, 0x100);
1678 memset(mc_other, 0, 0x100);
1680 netdev_for_each_mc_addr(ha, dev) {
1685 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1690 entry = addr_crc(a);
1693 table[entry >> 2] |= 1 << (8 * (entry & 3));
1696 for (i = 0; i < 0x100; i += 4) {
1697 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1698 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1704 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1706 mv643xx_eth_program_unicast_filter(dev);
1707 mv643xx_eth_program_multicast_filter(dev);
1710 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1712 struct sockaddr *sa = addr;
1714 if (!is_valid_ether_addr(sa->sa_data))
1715 return -EADDRNOTAVAIL;
1717 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1719 netif_addr_lock_bh(dev);
1720 mv643xx_eth_program_unicast_filter(dev);
1721 netif_addr_unlock_bh(dev);
1727 /* rx/tx queue initialisation ***********************************************/
1728 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1730 struct rx_queue *rxq = mp->rxq + index;
1731 struct rx_desc *rx_desc;
1737 rxq->rx_ring_size = mp->rx_ring_size;
1739 rxq->rx_desc_count = 0;
1740 rxq->rx_curr_desc = 0;
1741 rxq->rx_used_desc = 0;
1743 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1745 if (index == 0 && size <= mp->rx_desc_sram_size) {
1746 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1747 mp->rx_desc_sram_size);
1748 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1750 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1751 size, &rxq->rx_desc_dma,
1755 if (rxq->rx_desc_area == NULL) {
1757 "can't allocate rx ring (%d bytes)\n", size);
1760 memset(rxq->rx_desc_area, 0, size);
1762 rxq->rx_desc_area_size = size;
1763 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1765 if (rxq->rx_skb == NULL)
1768 rx_desc = rxq->rx_desc_area;
1769 for (i = 0; i < rxq->rx_ring_size; i++) {
1773 if (nexti == rxq->rx_ring_size)
1776 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1777 nexti * sizeof(struct rx_desc);
1784 if (index == 0 && size <= mp->rx_desc_sram_size)
1785 iounmap(rxq->rx_desc_area);
1787 dma_free_coherent(mp->dev->dev.parent, size,
1795 static void rxq_deinit(struct rx_queue *rxq)
1797 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1802 for (i = 0; i < rxq->rx_ring_size; i++) {
1803 if (rxq->rx_skb[i]) {
1804 dev_kfree_skb(rxq->rx_skb[i]);
1805 rxq->rx_desc_count--;
1809 if (rxq->rx_desc_count) {
1810 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1811 rxq->rx_desc_count);
1814 if (rxq->index == 0 &&
1815 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1816 iounmap(rxq->rx_desc_area);
1818 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1819 rxq->rx_desc_area, rxq->rx_desc_dma);
1824 static int txq_init(struct mv643xx_eth_private *mp, int index)
1826 struct tx_queue *txq = mp->txq + index;
1827 struct tx_desc *tx_desc;
1833 txq->tx_ring_size = mp->tx_ring_size;
1835 txq->tx_desc_count = 0;
1836 txq->tx_curr_desc = 0;
1837 txq->tx_used_desc = 0;
1839 size = txq->tx_ring_size * sizeof(struct tx_desc);
1841 if (index == 0 && size <= mp->tx_desc_sram_size) {
1842 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1843 mp->tx_desc_sram_size);
1844 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1846 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1847 size, &txq->tx_desc_dma,
1851 if (txq->tx_desc_area == NULL) {
1853 "can't allocate tx ring (%d bytes)\n", size);
1856 memset(txq->tx_desc_area, 0, size);
1858 txq->tx_desc_area_size = size;
1860 tx_desc = txq->tx_desc_area;
1861 for (i = 0; i < txq->tx_ring_size; i++) {
1862 struct tx_desc *txd = tx_desc + i;
1866 if (nexti == txq->tx_ring_size)
1870 txd->next_desc_ptr = txq->tx_desc_dma +
1871 nexti * sizeof(struct tx_desc);
1874 skb_queue_head_init(&txq->tx_skb);
1879 static void txq_deinit(struct tx_queue *txq)
1881 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1884 txq_reclaim(txq, txq->tx_ring_size, 1);
1886 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1888 if (txq->index == 0 &&
1889 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1890 iounmap(txq->tx_desc_area);
1892 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
1893 txq->tx_desc_area, txq->tx_desc_dma);
1897 /* netdev ops and related ***************************************************/
1898 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1903 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1908 if (int_cause & INT_EXT) {
1909 int_cause &= ~INT_EXT;
1910 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1914 wrlp(mp, INT_CAUSE, ~int_cause);
1915 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1916 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1917 mp->work_rx |= (int_cause & INT_RX) >> 2;
1920 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1921 if (int_cause_ext) {
1922 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1923 if (int_cause_ext & INT_EXT_LINK_PHY)
1925 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1931 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1933 struct net_device *dev = (struct net_device *)dev_id;
1934 struct mv643xx_eth_private *mp = netdev_priv(dev);
1936 if (unlikely(!mv643xx_eth_collect_events(mp)))
1939 wrlp(mp, INT_MASK, 0);
1940 napi_schedule(&mp->napi);
1945 static void handle_link_event(struct mv643xx_eth_private *mp)
1947 struct net_device *dev = mp->dev;
1953 port_status = rdlp(mp, PORT_STATUS);
1954 if (!(port_status & LINK_UP)) {
1955 if (netif_carrier_ok(dev)) {
1958 netdev_info(dev, "link down\n");
1960 netif_carrier_off(dev);
1962 for (i = 0; i < mp->txq_count; i++) {
1963 struct tx_queue *txq = mp->txq + i;
1965 txq_reclaim(txq, txq->tx_ring_size, 1);
1966 txq_reset_hw_ptr(txq);
1972 switch (port_status & PORT_SPEED_MASK) {
1976 case PORT_SPEED_100:
1979 case PORT_SPEED_1000:
1986 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1987 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1989 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
1990 speed, duplex ? "full" : "half", fc ? "en" : "dis");
1992 if (!netif_carrier_ok(dev))
1993 netif_carrier_on(dev);
1996 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1998 struct mv643xx_eth_private *mp;
2001 mp = container_of(napi, struct mv643xx_eth_private, napi);
2003 if (unlikely(mp->oom)) {
2005 del_timer(&mp->rx_oom);
2009 while (work_done < budget) {
2014 if (mp->work_link) {
2016 handle_link_event(mp);
2021 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2022 if (likely(!mp->oom))
2023 queue_mask |= mp->work_rx_refill;
2026 if (mv643xx_eth_collect_events(mp))
2031 queue = fls(queue_mask) - 1;
2032 queue_mask = 1 << queue;
2034 work_tbd = budget - work_done;
2038 if (mp->work_tx_end & queue_mask) {
2039 txq_kick(mp->txq + queue);
2040 } else if (mp->work_tx & queue_mask) {
2041 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2042 txq_maybe_wake(mp->txq + queue);
2043 } else if (mp->work_rx & queue_mask) {
2044 work_done += rxq_process(mp->rxq + queue, work_tbd);
2045 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2046 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2052 if (work_done < budget) {
2054 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2055 napi_complete(napi);
2056 wrlp(mp, INT_MASK, mp->int_mask);
2062 static inline void oom_timer_wrapper(unsigned long data)
2064 struct mv643xx_eth_private *mp = (void *)data;
2066 napi_schedule(&mp->napi);
2069 static void port_start(struct mv643xx_eth_private *mp)
2075 * Perform PHY reset, if there is a PHY.
2077 if (mp->phy != NULL) {
2078 struct ethtool_cmd cmd;
2080 mv643xx_eth_get_settings(mp->dev, &cmd);
2081 phy_init_hw(mp->phy);
2082 mv643xx_eth_set_settings(mp->dev, &cmd);
2087 * Configure basic link parameters.
2089 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2091 pscr |= SERIAL_PORT_ENABLE;
2092 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2094 pscr |= DO_NOT_FORCE_LINK_FAIL;
2095 if (mp->phy == NULL)
2096 pscr |= FORCE_LINK_PASS;
2097 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2100 * Configure TX path and queues.
2102 tx_set_rate(mp, 1000000000, 16777216);
2103 for (i = 0; i < mp->txq_count; i++) {
2104 struct tx_queue *txq = mp->txq + i;
2106 txq_reset_hw_ptr(txq);
2107 txq_set_rate(txq, 1000000000, 16777216);
2108 txq_set_fixed_prio_mode(txq);
2112 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2113 * frames to RX queue #0, and include the pseudo-header when
2114 * calculating receive checksums.
2116 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2119 * Treat BPDUs as normal multicasts, and disable partition mode.
2121 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2124 * Add configured unicast addresses to address filter table.
2126 mv643xx_eth_program_unicast_filter(mp->dev);
2129 * Enable the receive queues.
2131 for (i = 0; i < mp->rxq_count; i++) {
2132 struct rx_queue *rxq = mp->rxq + i;
2135 addr = (u32)rxq->rx_desc_dma;
2136 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2137 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2143 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2148 * Reserve 2+14 bytes for an ethernet header (the hardware
2149 * automatically prepends 2 bytes of dummy data to each
2150 * received packet), 16 bytes for up to four VLAN tags, and
2151 * 4 bytes for the trailing FCS -- 36 bytes total.
2153 skb_size = mp->dev->mtu + 36;
2156 * Make sure that the skb size is a multiple of 8 bytes, as
2157 * the lower three bits of the receive descriptor's buffer
2158 * size field are ignored by the hardware.
2160 mp->skb_size = (skb_size + 7) & ~7;
2163 * If NET_SKB_PAD is smaller than a cache line,
2164 * netdev_alloc_skb() will cause skb->data to be misaligned
2165 * to a cache line boundary. If this is the case, include
2166 * some extra space to allow re-aligning the data area.
2168 mp->skb_size += SKB_DMA_REALIGN;
2171 static int mv643xx_eth_open(struct net_device *dev)
2173 struct mv643xx_eth_private *mp = netdev_priv(dev);
2177 wrlp(mp, INT_CAUSE, 0);
2178 wrlp(mp, INT_CAUSE_EXT, 0);
2179 rdlp(mp, INT_CAUSE_EXT);
2181 err = request_irq(dev->irq, mv643xx_eth_irq,
2182 IRQF_SHARED, dev->name, dev);
2184 netdev_err(dev, "can't assign irq\n");
2188 mv643xx_eth_recalc_skb_size(mp);
2190 napi_enable(&mp->napi);
2192 mp->int_mask = INT_EXT;
2194 for (i = 0; i < mp->rxq_count; i++) {
2195 err = rxq_init(mp, i);
2198 rxq_deinit(mp->rxq + i);
2202 rxq_refill(mp->rxq + i, INT_MAX);
2203 mp->int_mask |= INT_RX_0 << i;
2207 mp->rx_oom.expires = jiffies + (HZ / 10);
2208 add_timer(&mp->rx_oom);
2211 for (i = 0; i < mp->txq_count; i++) {
2212 err = txq_init(mp, i);
2215 txq_deinit(mp->txq + i);
2218 mp->int_mask |= INT_TX_END_0 << i;
2221 add_timer(&mp->mib_counters_timer);
2224 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2225 wrlp(mp, INT_MASK, mp->int_mask);
2231 for (i = 0; i < mp->rxq_count; i++)
2232 rxq_deinit(mp->rxq + i);
2234 free_irq(dev->irq, dev);
2239 static void port_reset(struct mv643xx_eth_private *mp)
2244 for (i = 0; i < mp->rxq_count; i++)
2245 rxq_disable(mp->rxq + i);
2246 for (i = 0; i < mp->txq_count; i++)
2247 txq_disable(mp->txq + i);
2250 u32 ps = rdlp(mp, PORT_STATUS);
2252 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2257 /* Reset the Enable bit in the Configuration Register */
2258 data = rdlp(mp, PORT_SERIAL_CONTROL);
2259 data &= ~(SERIAL_PORT_ENABLE |
2260 DO_NOT_FORCE_LINK_FAIL |
2262 wrlp(mp, PORT_SERIAL_CONTROL, data);
2265 static int mv643xx_eth_stop(struct net_device *dev)
2267 struct mv643xx_eth_private *mp = netdev_priv(dev);
2270 wrlp(mp, INT_MASK_EXT, 0x00000000);
2271 wrlp(mp, INT_MASK, 0x00000000);
2274 napi_disable(&mp->napi);
2276 del_timer_sync(&mp->rx_oom);
2278 netif_carrier_off(dev);
2281 free_irq(dev->irq, dev);
2284 mv643xx_eth_get_stats(dev);
2285 mib_counters_update(mp);
2286 del_timer_sync(&mp->mib_counters_timer);
2288 for (i = 0; i < mp->rxq_count; i++)
2289 rxq_deinit(mp->rxq + i);
2290 for (i = 0; i < mp->txq_count; i++)
2291 txq_deinit(mp->txq + i);
2296 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2298 struct mv643xx_eth_private *mp = netdev_priv(dev);
2301 if (mp->phy == NULL)
2304 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2306 mv643xx_adjust_pscr(mp);
2310 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2312 struct mv643xx_eth_private *mp = netdev_priv(dev);
2314 if (new_mtu < 64 || new_mtu > 9500)
2318 mv643xx_eth_recalc_skb_size(mp);
2319 tx_set_rate(mp, 1000000000, 16777216);
2321 if (!netif_running(dev))
2325 * Stop and then re-open the interface. This will allocate RX
2326 * skbs of the new MTU.
2327 * There is a possible danger that the open will not succeed,
2328 * due to memory being full.
2330 mv643xx_eth_stop(dev);
2331 if (mv643xx_eth_open(dev)) {
2333 "fatal error on re-opening device after MTU change\n");
2339 static void tx_timeout_task(struct work_struct *ugly)
2341 struct mv643xx_eth_private *mp;
2343 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2344 if (netif_running(mp->dev)) {
2345 netif_tx_stop_all_queues(mp->dev);
2348 netif_tx_wake_all_queues(mp->dev);
2352 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2354 struct mv643xx_eth_private *mp = netdev_priv(dev);
2356 netdev_info(dev, "tx timeout\n");
2358 schedule_work(&mp->tx_timeout_task);
2361 #ifdef CONFIG_NET_POLL_CONTROLLER
2362 static void mv643xx_eth_netpoll(struct net_device *dev)
2364 struct mv643xx_eth_private *mp = netdev_priv(dev);
2366 wrlp(mp, INT_MASK, 0x00000000);
2369 mv643xx_eth_irq(dev->irq, dev);
2371 wrlp(mp, INT_MASK, mp->int_mask);
2376 /* platform glue ************************************************************/
2378 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2379 const struct mbus_dram_target_info *dram)
2381 void __iomem *base = msp->base;
2386 for (i = 0; i < 6; i++) {
2387 writel(0, base + WINDOW_BASE(i));
2388 writel(0, base + WINDOW_SIZE(i));
2390 writel(0, base + WINDOW_REMAP_HIGH(i));
2396 for (i = 0; i < dram->num_cs; i++) {
2397 const struct mbus_dram_window *cs = dram->cs + i;
2399 writel((cs->base & 0xffff0000) |
2400 (cs->mbus_attr << 8) |
2401 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2402 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2404 win_enable &= ~(1 << i);
2405 win_protect |= 3 << (2 * i);
2408 writel(win_enable, base + WINDOW_BAR_ENABLE);
2409 msp->win_protect = win_protect;
2412 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2415 * Check whether we have a 14-bit coal limit field in bits
2416 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2417 * SDMA config register.
2419 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2420 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2421 msp->extended_rx_coal_limit = 1;
2423 msp->extended_rx_coal_limit = 0;
2426 * Check whether the MAC supports TX rate control, and if
2427 * yes, whether its associated registers are in the old or
2430 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2431 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2432 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2434 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2435 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2436 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2438 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2442 #if defined(CONFIG_OF)
2443 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2444 { .compatible = "marvell,orion-eth", },
2445 { .compatible = "marvell,kirkwood-eth", },
2448 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2451 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2452 #define mv643xx_eth_property(_np, _name, _v) \
2455 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2459 static struct platform_device *port_platdev[3];
2461 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2462 struct device_node *pnp)
2464 struct platform_device *ppdev;
2465 struct mv643xx_eth_platform_data ppd;
2466 struct resource res;
2467 const char *mac_addr;
2471 memset(&ppd, 0, sizeof(ppd));
2474 memset(&res, 0, sizeof(res));
2475 if (!of_irq_to_resource(pnp, 0, &res)) {
2476 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2480 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2481 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2485 if (ppd.port_number >= 3) {
2486 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2490 while (dev_num < 3 && port_platdev[dev_num])
2494 dev_err(&pdev->dev, "too many ports registered\n");
2498 mac_addr = of_get_mac_address(pnp);
2500 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2502 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2503 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2504 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2505 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2506 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2507 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2509 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2510 if (!ppd.phy_node) {
2511 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2512 of_property_read_u32(pnp, "speed", &ppd.speed);
2513 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2516 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2519 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2520 ppdev->dev.of_node = pnp;
2522 ret = platform_device_add_resources(ppdev, &res, 1);
2526 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2530 ret = platform_device_add(ppdev);
2534 port_platdev[dev_num] = ppdev;
2539 platform_device_put(ppdev);
2543 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2545 struct mv643xx_eth_shared_platform_data *pd;
2546 struct device_node *pnp, *np = pdev->dev.of_node;
2549 /* bail out if not registered from DT */
2553 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2556 pdev->dev.platform_data = pd;
2558 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2560 for_each_available_child_of_node(np, pnp) {
2561 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2568 static void mv643xx_eth_shared_of_remove(void)
2572 for (n = 0; n < 3; n++) {
2573 platform_device_del(port_platdev[n]);
2574 port_platdev[n] = NULL;
2578 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2583 static inline void mv643xx_eth_shared_of_remove(void)
2588 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2590 static int mv643xx_eth_version_printed;
2591 struct mv643xx_eth_shared_platform_data *pd;
2592 struct mv643xx_eth_shared_private *msp;
2593 const struct mbus_dram_target_info *dram;
2594 struct resource *res;
2597 if (!mv643xx_eth_version_printed++)
2598 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2599 mv643xx_eth_driver_version);
2601 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2605 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2608 platform_set_drvdata(pdev, msp);
2610 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2611 if (msp->base == NULL)
2614 msp->clk = devm_clk_get(&pdev->dev, NULL);
2615 if (!IS_ERR(msp->clk))
2616 clk_prepare_enable(msp->clk);
2619 * (Re-)program MBUS remapping windows if we are asked to.
2621 dram = mv_mbus_dram_info();
2623 mv643xx_eth_conf_mbus_windows(msp, dram);
2625 ret = mv643xx_eth_shared_of_probe(pdev);
2628 pd = dev_get_platdata(&pdev->dev);
2630 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2631 pd->tx_csum_limit : 9 * 1024;
2632 infer_hw_params(msp);
2637 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2639 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2641 mv643xx_eth_shared_of_remove();
2642 if (!IS_ERR(msp->clk))
2643 clk_disable_unprepare(msp->clk);
2647 static struct platform_driver mv643xx_eth_shared_driver = {
2648 .probe = mv643xx_eth_shared_probe,
2649 .remove = mv643xx_eth_shared_remove,
2651 .name = MV643XX_ETH_SHARED_NAME,
2652 .owner = THIS_MODULE,
2653 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2657 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2659 int addr_shift = 5 * mp->port_num;
2662 data = rdl(mp, PHY_ADDR);
2663 data &= ~(0x1f << addr_shift);
2664 data |= (phy_addr & 0x1f) << addr_shift;
2665 wrl(mp, PHY_ADDR, data);
2668 static int phy_addr_get(struct mv643xx_eth_private *mp)
2672 data = rdl(mp, PHY_ADDR);
2674 return (data >> (5 * mp->port_num)) & 0x1f;
2677 static void set_params(struct mv643xx_eth_private *mp,
2678 struct mv643xx_eth_platform_data *pd)
2680 struct net_device *dev = mp->dev;
2682 if (is_valid_ether_addr(pd->mac_addr))
2683 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2685 uc_addr_get(mp, dev->dev_addr);
2687 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2688 if (pd->rx_queue_size)
2689 mp->rx_ring_size = pd->rx_queue_size;
2690 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2691 mp->rx_desc_sram_size = pd->rx_sram_size;
2693 mp->rxq_count = pd->rx_queue_count ? : 1;
2695 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2696 if (pd->tx_queue_size)
2697 mp->tx_ring_size = pd->tx_queue_size;
2698 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2699 mp->tx_desc_sram_size = pd->tx_sram_size;
2701 mp->txq_count = pd->tx_queue_count ? : 1;
2704 static void mv643xx_eth_adjust_link(struct net_device *dev)
2706 struct mv643xx_eth_private *mp = netdev_priv(dev);
2708 mv643xx_adjust_pscr(mp);
2711 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2714 struct phy_device *phydev;
2718 char phy_id[MII_BUS_ID_SIZE + 3];
2720 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2721 start = phy_addr_get(mp) & 0x1f;
2724 start = phy_addr & 0x1f;
2728 /* Attempt to connect to the PHY using orion-mdio */
2729 phydev = ERR_PTR(-ENODEV);
2730 for (i = 0; i < num; i++) {
2731 int addr = (start + i) & 0x1f;
2733 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2734 "orion-mdio-mii", addr);
2736 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2737 PHY_INTERFACE_MODE_GMII);
2738 if (!IS_ERR(phydev)) {
2739 phy_addr_set(mp, addr);
2747 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2749 struct phy_device *phy = mp->phy;
2752 phy->autoneg = AUTONEG_ENABLE;
2755 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2757 phy->autoneg = AUTONEG_DISABLE;
2758 phy->advertising = 0;
2760 phy->duplex = duplex;
2762 phy_start_aneg(phy);
2765 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2769 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2770 if (pscr & SERIAL_PORT_ENABLE) {
2771 pscr &= ~SERIAL_PORT_ENABLE;
2772 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2775 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2776 if (mp->phy == NULL) {
2777 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2778 if (speed == SPEED_1000)
2779 pscr |= SET_GMII_SPEED_TO_1000;
2780 else if (speed == SPEED_100)
2781 pscr |= SET_MII_SPEED_TO_100;
2783 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2785 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2786 if (duplex == DUPLEX_FULL)
2787 pscr |= SET_FULL_DUPLEX_MODE;
2790 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2793 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2794 .ndo_open = mv643xx_eth_open,
2795 .ndo_stop = mv643xx_eth_stop,
2796 .ndo_start_xmit = mv643xx_eth_xmit,
2797 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2798 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2799 .ndo_validate_addr = eth_validate_addr,
2800 .ndo_do_ioctl = mv643xx_eth_ioctl,
2801 .ndo_change_mtu = mv643xx_eth_change_mtu,
2802 .ndo_set_features = mv643xx_eth_set_features,
2803 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2804 .ndo_get_stats = mv643xx_eth_get_stats,
2805 #ifdef CONFIG_NET_POLL_CONTROLLER
2806 .ndo_poll_controller = mv643xx_eth_netpoll,
2810 static int mv643xx_eth_probe(struct platform_device *pdev)
2812 struct mv643xx_eth_platform_data *pd;
2813 struct mv643xx_eth_private *mp;
2814 struct net_device *dev;
2815 struct resource *res;
2818 pd = dev_get_platdata(&pdev->dev);
2820 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2824 if (pd->shared == NULL) {
2825 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2829 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2833 mp = netdev_priv(dev);
2834 platform_set_drvdata(pdev, mp);
2836 mp->shared = platform_get_drvdata(pd->shared);
2837 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2838 mp->port_num = pd->port_number;
2842 /* Kirkwood resets some registers on gated clocks. Especially
2843 * CLK125_BYPASS_EN must be cleared but is not available on
2844 * all other SoCs/System Controllers using this driver.
2846 if (of_device_is_compatible(pdev->dev.of_node,
2847 "marvell,kirkwood-eth-port"))
2848 wrlp(mp, PORT_SERIAL_CONTROL1,
2849 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
2852 * Start with a default rate, and if there is a clock, allow
2853 * it to override the default.
2855 mp->t_clk = 133000000;
2856 mp->clk = devm_clk_get(&pdev->dev, NULL);
2857 if (!IS_ERR(mp->clk)) {
2858 clk_prepare_enable(mp->clk);
2859 mp->t_clk = clk_get_rate(mp->clk);
2860 } else if (!IS_ERR(mp->shared->clk)) {
2861 mp->t_clk = clk_get_rate(mp->shared->clk);
2865 netif_set_real_num_tx_queues(dev, mp->txq_count);
2866 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2870 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
2871 mv643xx_eth_adjust_link, 0,
2872 PHY_INTERFACE_MODE_GMII);
2876 phy_addr_set(mp, mp->phy->addr);
2877 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
2878 mp->phy = phy_scan(mp, pd->phy_addr);
2880 if (IS_ERR(mp->phy))
2881 err = PTR_ERR(mp->phy);
2883 phy_init(mp, pd->speed, pd->duplex);
2885 if (err == -ENODEV) {
2886 err = -EPROBE_DEFER;
2892 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2894 init_pscr(mp, pd->speed, pd->duplex);
2897 mib_counters_clear(mp);
2899 init_timer(&mp->mib_counters_timer);
2900 mp->mib_counters_timer.data = (unsigned long)mp;
2901 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2902 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2904 spin_lock_init(&mp->mib_counters_lock);
2906 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2908 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
2910 init_timer(&mp->rx_oom);
2911 mp->rx_oom.data = (unsigned long)mp;
2912 mp->rx_oom.function = oom_timer_wrapper;
2915 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2917 dev->irq = res->start;
2919 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2921 dev->watchdog_timeo = 2 * HZ;
2924 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2925 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2926 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2928 dev->priv_flags |= IFF_UNICAST_FLT;
2930 SET_NETDEV_DEV(dev, &pdev->dev);
2932 if (mp->shared->win_protect)
2933 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2935 netif_carrier_off(dev);
2937 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2939 set_rx_coal(mp, 250);
2942 err = register_netdev(dev);
2946 netdev_notice(dev, "port %d with MAC address %pM\n",
2947 mp->port_num, dev->dev_addr);
2949 if (mp->tx_desc_sram_size > 0)
2950 netdev_notice(dev, "configured with sram\n");
2955 if (!IS_ERR(mp->clk))
2956 clk_disable_unprepare(mp->clk);
2962 static int mv643xx_eth_remove(struct platform_device *pdev)
2964 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2966 unregister_netdev(mp->dev);
2967 if (mp->phy != NULL)
2968 phy_disconnect(mp->phy);
2969 cancel_work_sync(&mp->tx_timeout_task);
2971 if (!IS_ERR(mp->clk))
2972 clk_disable_unprepare(mp->clk);
2974 free_netdev(mp->dev);
2979 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2981 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2983 /* Mask all interrupts on ethernet port */
2984 wrlp(mp, INT_MASK, 0);
2987 if (netif_running(mp->dev))
2991 static struct platform_driver mv643xx_eth_driver = {
2992 .probe = mv643xx_eth_probe,
2993 .remove = mv643xx_eth_remove,
2994 .shutdown = mv643xx_eth_shutdown,
2996 .name = MV643XX_ETH_NAME,
2997 .owner = THIS_MODULE,
3001 static int __init mv643xx_eth_init_module(void)
3005 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3007 rc = platform_driver_register(&mv643xx_eth_driver);
3009 platform_driver_unregister(&mv643xx_eth_shared_driver);
3014 module_init(mv643xx_eth_init_module);
3016 static void __exit mv643xx_eth_cleanup_module(void)
3018 platform_driver_unregister(&mv643xx_eth_driver);
3019 platform_driver_unregister(&mv643xx_eth_shared_driver);
3021 module_exit(mv643xx_eth_cleanup_module);
3023 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3024 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3025 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3026 MODULE_LICENSE("GPL");
3027 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3028 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);