2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40 #include <linux/init.h>
41 #include <linux/dma-mapping.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/etherdevice.h>
47 #include <linux/delay.h>
48 #include <linux/ethtool.h>
49 #include <linux/platform_device.h>
50 #include <linux/module.h>
51 #include <linux/kernel.h>
52 #include <linux/spinlock.h>
53 #include <linux/workqueue.h>
54 #include <linux/phy.h>
55 #include <linux/mv643xx_eth.h>
57 #include <linux/types.h>
58 #include <linux/inet_lro.h>
59 #include <linux/slab.h>
60 #include <linux/clk.h>
62 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
63 static char mv643xx_eth_driver_version[] = "1.4";
67 * Registers shared between all ports.
69 #define PHY_ADDR 0x0000
70 #define SMI_REG 0x0004
71 #define SMI_BUSY 0x10000000
72 #define SMI_READ_VALID 0x08000000
73 #define SMI_OPCODE_READ 0x04000000
74 #define SMI_OPCODE_WRITE 0x00000000
75 #define ERR_INT_CAUSE 0x0080
76 #define ERR_INT_SMI_DONE 0x00000010
77 #define ERR_INT_MASK 0x0084
78 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
79 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
80 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
81 #define WINDOW_BAR_ENABLE 0x0290
82 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
85 * Main per-port registers. These live at offset 0x0400 for
86 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
88 #define PORT_CONFIG 0x0000
89 #define UNICAST_PROMISCUOUS_MODE 0x00000001
90 #define PORT_CONFIG_EXT 0x0004
91 #define MAC_ADDR_LOW 0x0014
92 #define MAC_ADDR_HIGH 0x0018
93 #define SDMA_CONFIG 0x001c
94 #define TX_BURST_SIZE_16_64BIT 0x01000000
95 #define TX_BURST_SIZE_4_64BIT 0x00800000
96 #define BLM_TX_NO_SWAP 0x00000020
97 #define BLM_RX_NO_SWAP 0x00000010
98 #define RX_BURST_SIZE_16_64BIT 0x00000008
99 #define RX_BURST_SIZE_4_64BIT 0x00000004
100 #define PORT_SERIAL_CONTROL 0x003c
101 #define SET_MII_SPEED_TO_100 0x01000000
102 #define SET_GMII_SPEED_TO_1000 0x00800000
103 #define SET_FULL_DUPLEX_MODE 0x00200000
104 #define MAX_RX_PACKET_9700BYTE 0x000a0000
105 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
106 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
107 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
108 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
109 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
110 #define FORCE_LINK_PASS 0x00000002
111 #define SERIAL_PORT_ENABLE 0x00000001
112 #define PORT_STATUS 0x0044
113 #define TX_FIFO_EMPTY 0x00000400
114 #define TX_IN_PROGRESS 0x00000080
115 #define PORT_SPEED_MASK 0x00000030
116 #define PORT_SPEED_1000 0x00000010
117 #define PORT_SPEED_100 0x00000020
118 #define PORT_SPEED_10 0x00000000
119 #define FLOW_CONTROL_ENABLED 0x00000008
120 #define FULL_DUPLEX 0x00000004
121 #define LINK_UP 0x00000002
122 #define TXQ_COMMAND 0x0048
123 #define TXQ_FIX_PRIO_CONF 0x004c
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
153 * Misc per-port registers.
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
162 * SDMA configuration register default value.
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
173 TX_BURST_SIZE_4_64BIT)
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 256
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
190 #if defined(__BIG_ENDIAN)
192 u16 byte_cnt; /* Descriptor buffer byte count */
193 u16 buf_size; /* Buffer size */
194 u32 cmd_sts; /* Descriptor command status */
195 u32 next_desc_ptr; /* Next descriptor pointer */
196 u32 buf_ptr; /* Descriptor buffer pointer */
200 u16 byte_cnt; /* buffer byte count */
201 u16 l4i_chk; /* CPU provided TCP checksum */
202 u32 cmd_sts; /* Command/status field */
203 u32 next_desc_ptr; /* Pointer to next descriptor */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
206 #elif defined(__LITTLE_ENDIAN)
208 u32 cmd_sts; /* Descriptor command status */
209 u16 buf_size; /* Buffer size */
210 u16 byte_cnt; /* Descriptor buffer byte count */
211 u32 buf_ptr; /* Descriptor buffer pointer */
212 u32 next_desc_ptr; /* Next descriptor pointer */
216 u32 cmd_sts; /* Command/status field */
217 u16 l4i_chk; /* CPU provided TCP checksum */
218 u16 byte_cnt; /* buffer byte count */
219 u32 buf_ptr; /* pointer to buffer for this descriptor*/
220 u32 next_desc_ptr; /* Pointer to next descriptor */
223 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
226 /* RX & TX descriptor command */
227 #define BUFFER_OWNED_BY_DMA 0x80000000
229 /* RX & TX descriptor status */
230 #define ERROR_SUMMARY 0x00000001
232 /* RX descriptor status */
233 #define LAYER_4_CHECKSUM_OK 0x40000000
234 #define RX_ENABLE_INTERRUPT 0x20000000
235 #define RX_FIRST_DESC 0x08000000
236 #define RX_LAST_DESC 0x04000000
237 #define RX_IP_HDR_OK 0x02000000
238 #define RX_PKT_IS_IPV4 0x01000000
239 #define RX_PKT_IS_ETHERNETV2 0x00800000
240 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
241 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
242 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
244 /* TX descriptor command */
245 #define TX_ENABLE_INTERRUPT 0x00800000
246 #define GEN_CRC 0x00400000
247 #define TX_FIRST_DESC 0x00200000
248 #define TX_LAST_DESC 0x00100000
249 #define ZERO_PADDING 0x00080000
250 #define GEN_IP_V4_CHECKSUM 0x00040000
251 #define GEN_TCP_UDP_CHECKSUM 0x00020000
252 #define UDP_FRAME 0x00010000
253 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
256 #define TX_IHL_SHIFT 11
259 /* global *******************************************************************/
260 struct mv643xx_eth_shared_private {
262 * Ethernet controller base address.
267 * Points at the right SMI instance to use.
269 struct mv643xx_eth_shared_private *smi;
272 * Provides access to local SMI interface.
274 struct mii_bus *smi_bus;
277 * If we have access to the error interrupt pin (which is
278 * somewhat misnamed as it not only reflects internal errors
279 * but also reflects SMI completion), use that to wait for
280 * SMI access completion instead of polling the SMI busy bit.
283 wait_queue_head_t smi_busy_wait;
286 * Per-port MBUS window access register value.
291 * Hardware-specific parameters.
293 int extended_rx_coal_limit;
299 #define TX_BW_CONTROL_ABSENT 0
300 #define TX_BW_CONTROL_OLD_LAYOUT 1
301 #define TX_BW_CONTROL_NEW_LAYOUT 2
303 static int mv643xx_eth_open(struct net_device *dev);
304 static int mv643xx_eth_stop(struct net_device *dev);
307 /* per-port *****************************************************************/
308 struct mib_counters {
309 u64 good_octets_received;
310 u32 bad_octets_received;
311 u32 internal_mac_transmit_err;
312 u32 good_frames_received;
313 u32 bad_frames_received;
314 u32 broadcast_frames_received;
315 u32 multicast_frames_received;
316 u32 frames_64_octets;
317 u32 frames_65_to_127_octets;
318 u32 frames_128_to_255_octets;
319 u32 frames_256_to_511_octets;
320 u32 frames_512_to_1023_octets;
321 u32 frames_1024_to_max_octets;
322 u64 good_octets_sent;
323 u32 good_frames_sent;
324 u32 excessive_collision;
325 u32 multicast_frames_sent;
326 u32 broadcast_frames_sent;
327 u32 unrec_mac_control_received;
329 u32 good_fc_received;
331 u32 undersize_received;
332 u32 fragments_received;
333 u32 oversize_received;
335 u32 mac_receive_error;
339 /* Non MIB hardware counters */
344 struct lro_counters {
359 struct rx_desc *rx_desc_area;
360 dma_addr_t rx_desc_dma;
361 int rx_desc_area_size;
362 struct sk_buff **rx_skb;
364 struct net_lro_mgr lro_mgr;
365 struct net_lro_desc lro_arr[8];
377 struct tx_desc *tx_desc_area;
378 dma_addr_t tx_desc_dma;
379 int tx_desc_area_size;
381 struct sk_buff_head tx_skb;
383 unsigned long tx_packets;
384 unsigned long tx_bytes;
385 unsigned long tx_dropped;
388 struct mv643xx_eth_private {
389 struct mv643xx_eth_shared_private *shared;
393 struct net_device *dev;
395 struct phy_device *phy;
397 struct timer_list mib_counters_timer;
398 spinlock_t mib_counters_lock;
399 struct mib_counters mib_counters;
401 struct lro_counters lro_counters;
403 struct work_struct tx_timeout_task;
405 struct napi_struct napi;
420 unsigned long rx_desc_sram_addr;
421 int rx_desc_sram_size;
423 struct timer_list rx_oom;
424 struct rx_queue rxq[8];
430 unsigned long tx_desc_sram_addr;
431 int tx_desc_sram_size;
433 struct tx_queue txq[8];
436 * Hardware-specific parameters.
438 #if defined(CONFIG_HAVE_CLK)
445 /* port register accessors **************************************************/
446 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
448 return readl(mp->shared->base + offset);
451 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
453 return readl(mp->base + offset);
456 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
458 writel(data, mp->shared->base + offset);
461 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
463 writel(data, mp->base + offset);
467 /* rxq/txq helper functions *************************************************/
468 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
470 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
473 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
475 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
478 static void rxq_enable(struct rx_queue *rxq)
480 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
481 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
484 static void rxq_disable(struct rx_queue *rxq)
486 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
487 u8 mask = 1 << rxq->index;
489 wrlp(mp, RXQ_COMMAND, mask << 8);
490 while (rdlp(mp, RXQ_COMMAND) & mask)
494 static void txq_reset_hw_ptr(struct tx_queue *txq)
496 struct mv643xx_eth_private *mp = txq_to_mp(txq);
499 addr = (u32)txq->tx_desc_dma;
500 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
501 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
504 static void txq_enable(struct tx_queue *txq)
506 struct mv643xx_eth_private *mp = txq_to_mp(txq);
507 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
510 static void txq_disable(struct tx_queue *txq)
512 struct mv643xx_eth_private *mp = txq_to_mp(txq);
513 u8 mask = 1 << txq->index;
515 wrlp(mp, TXQ_COMMAND, mask << 8);
516 while (rdlp(mp, TXQ_COMMAND) & mask)
520 static void txq_maybe_wake(struct tx_queue *txq)
522 struct mv643xx_eth_private *mp = txq_to_mp(txq);
523 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
525 if (netif_tx_queue_stopped(nq)) {
526 __netif_tx_lock(nq, smp_processor_id());
527 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
528 netif_tx_wake_queue(nq);
529 __netif_tx_unlock(nq);
534 /* rx napi ******************************************************************/
536 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
537 u64 *hdr_flags, void *priv)
539 unsigned long cmd_sts = (unsigned long)priv;
542 * Make sure that this packet is Ethernet II, is not VLAN
543 * tagged, is IPv4, has a valid IP header, and is TCP.
545 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
546 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
547 RX_PKT_IS_VLAN_TAGGED)) !=
548 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
549 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
552 skb_reset_network_header(skb);
553 skb_set_transport_header(skb, ip_hdrlen(skb));
554 *iphdr = ip_hdr(skb);
555 *tcph = tcp_hdr(skb);
556 *hdr_flags = LRO_IPV4 | LRO_TCP;
561 static int rxq_process(struct rx_queue *rxq, int budget)
563 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
564 struct net_device_stats *stats = &mp->dev->stats;
565 int lro_flush_needed;
568 lro_flush_needed = 0;
570 while (rx < budget && rxq->rx_desc_count) {
571 struct rx_desc *rx_desc;
572 unsigned int cmd_sts;
576 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
578 cmd_sts = rx_desc->cmd_sts;
579 if (cmd_sts & BUFFER_OWNED_BY_DMA)
583 skb = rxq->rx_skb[rxq->rx_curr_desc];
584 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
587 if (rxq->rx_curr_desc == rxq->rx_ring_size)
588 rxq->rx_curr_desc = 0;
590 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
591 rx_desc->buf_size, DMA_FROM_DEVICE);
592 rxq->rx_desc_count--;
595 mp->work_rx_refill |= 1 << rxq->index;
597 byte_cnt = rx_desc->byte_cnt;
602 * Note that the descriptor byte count includes 2 dummy
603 * bytes automatically inserted by the hardware at the
604 * start of the packet (which we don't count), and a 4
605 * byte CRC at the end of the packet (which we do count).
608 stats->rx_bytes += byte_cnt - 2;
611 * In case we received a packet without first / last bits
612 * on, or the error summary bit is set, the packet needs
615 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
616 != (RX_FIRST_DESC | RX_LAST_DESC))
620 * The -4 is for the CRC in the trailer of the
623 skb_put(skb, byte_cnt - 2 - 4);
625 if (cmd_sts & LAYER_4_CHECKSUM_OK)
626 skb->ip_summed = CHECKSUM_UNNECESSARY;
627 skb->protocol = eth_type_trans(skb, mp->dev);
629 if (skb->dev->features & NETIF_F_LRO &&
630 skb->ip_summed == CHECKSUM_UNNECESSARY) {
631 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
632 lro_flush_needed = 1;
634 netif_receive_skb(skb);
641 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
642 (RX_FIRST_DESC | RX_LAST_DESC)) {
645 "received packet spanning multiple descriptors\n");
648 if (cmd_sts & ERROR_SUMMARY)
654 if (lro_flush_needed)
655 lro_flush_all(&rxq->lro_mgr);
658 mp->work_rx &= ~(1 << rxq->index);
663 static int rxq_refill(struct rx_queue *rxq, int budget)
665 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
669 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
672 struct rx_desc *rx_desc;
675 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
683 skb_reserve(skb, SKB_DMA_REALIGN);
686 rxq->rx_desc_count++;
688 rx = rxq->rx_used_desc++;
689 if (rxq->rx_used_desc == rxq->rx_ring_size)
690 rxq->rx_used_desc = 0;
692 rx_desc = rxq->rx_desc_area + rx;
694 size = skb->end - skb->data;
695 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
698 rx_desc->buf_size = size;
699 rxq->rx_skb[rx] = skb;
701 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
705 * The hardware automatically prepends 2 bytes of
706 * dummy data to each received packet, so that the
707 * IP header ends up 16-byte aligned.
712 if (refilled < budget)
713 mp->work_rx_refill &= ~(1 << rxq->index);
720 /* tx ***********************************************************************/
721 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
725 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
726 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
728 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
735 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
737 struct mv643xx_eth_private *mp = txq_to_mp(txq);
738 int nr_frags = skb_shinfo(skb)->nr_frags;
741 for (frag = 0; frag < nr_frags; frag++) {
742 skb_frag_t *this_frag;
744 struct tx_desc *desc;
746 this_frag = &skb_shinfo(skb)->frags[frag];
747 tx_index = txq->tx_curr_desc++;
748 if (txq->tx_curr_desc == txq->tx_ring_size)
749 txq->tx_curr_desc = 0;
750 desc = &txq->tx_desc_area[tx_index];
753 * The last fragment will generate an interrupt
754 * which will free the skb on TX completion.
756 if (frag == nr_frags - 1) {
757 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
758 ZERO_PADDING | TX_LAST_DESC |
761 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
765 desc->byte_cnt = skb_frag_size(this_frag);
766 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
768 skb_frag_size(this_frag),
773 static inline __be16 sum16_as_be(__sum16 sum)
775 return (__force __be16)sum;
778 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
780 struct mv643xx_eth_private *mp = txq_to_mp(txq);
781 int nr_frags = skb_shinfo(skb)->nr_frags;
783 struct tx_desc *desc;
788 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
791 if (skb->ip_summed == CHECKSUM_PARTIAL) {
795 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
796 skb->protocol != htons(ETH_P_8021Q));
798 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
799 tag_bytes = hdr_len - ETH_HLEN;
800 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
801 unlikely(tag_bytes & ~12)) {
802 if (skb_checksum_help(skb) == 0)
809 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
811 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
813 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
815 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
817 switch (ip_hdr(skb)->protocol) {
819 cmd_sts |= UDP_FRAME;
820 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
823 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
830 /* Errata BTS #50, IHL must be 5 if no HW checksum */
831 cmd_sts |= 5 << TX_IHL_SHIFT;
834 tx_index = txq->tx_curr_desc++;
835 if (txq->tx_curr_desc == txq->tx_ring_size)
836 txq->tx_curr_desc = 0;
837 desc = &txq->tx_desc_area[tx_index];
840 txq_submit_frag_skb(txq, skb);
841 length = skb_headlen(skb);
843 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
847 desc->l4i_chk = l4i_chk;
848 desc->byte_cnt = length;
849 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
850 length, DMA_TO_DEVICE);
852 __skb_queue_tail(&txq->tx_skb, skb);
854 skb_tx_timestamp(skb);
856 /* ensure all other descriptors are written before first cmd_sts */
858 desc->cmd_sts = cmd_sts;
860 /* clear TX_END status */
861 mp->work_tx_end &= ~(1 << txq->index);
863 /* ensure all descriptors are written before poking hardware */
867 txq->tx_desc_count += nr_frags + 1;
872 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
874 struct mv643xx_eth_private *mp = netdev_priv(dev);
876 struct tx_queue *txq;
877 struct netdev_queue *nq;
879 queue = skb_get_queue_mapping(skb);
880 txq = mp->txq + queue;
881 nq = netdev_get_tx_queue(dev, queue);
883 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
885 netdev_printk(KERN_DEBUG, dev,
886 "failed to linearize skb with tiny unaligned fragment\n");
887 return NETDEV_TX_BUSY;
890 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
892 netdev_err(dev, "tx queue full?!\n");
899 if (!txq_submit_skb(txq, skb)) {
902 txq->tx_bytes += length;
905 entries_left = txq->tx_ring_size - txq->tx_desc_count;
906 if (entries_left < MAX_SKB_FRAGS + 1)
907 netif_tx_stop_queue(nq);
914 /* tx napi ******************************************************************/
915 static void txq_kick(struct tx_queue *txq)
917 struct mv643xx_eth_private *mp = txq_to_mp(txq);
918 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
922 __netif_tx_lock(nq, smp_processor_id());
924 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
927 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
928 expected_ptr = (u32)txq->tx_desc_dma +
929 txq->tx_curr_desc * sizeof(struct tx_desc);
931 if (hw_desc_ptr != expected_ptr)
935 __netif_tx_unlock(nq);
937 mp->work_tx_end &= ~(1 << txq->index);
940 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
942 struct mv643xx_eth_private *mp = txq_to_mp(txq);
943 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
946 __netif_tx_lock(nq, smp_processor_id());
949 while (reclaimed < budget && txq->tx_desc_count > 0) {
951 struct tx_desc *desc;
955 tx_index = txq->tx_used_desc;
956 desc = &txq->tx_desc_area[tx_index];
957 cmd_sts = desc->cmd_sts;
959 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
962 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
965 txq->tx_used_desc = tx_index + 1;
966 if (txq->tx_used_desc == txq->tx_ring_size)
967 txq->tx_used_desc = 0;
970 txq->tx_desc_count--;
973 if (cmd_sts & TX_LAST_DESC)
974 skb = __skb_dequeue(&txq->tx_skb);
976 if (cmd_sts & ERROR_SUMMARY) {
977 netdev_info(mp->dev, "tx error\n");
978 mp->dev->stats.tx_errors++;
981 if (cmd_sts & TX_FIRST_DESC) {
982 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
983 desc->byte_cnt, DMA_TO_DEVICE);
985 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
986 desc->byte_cnt, DMA_TO_DEVICE);
992 __netif_tx_unlock(nq);
994 if (reclaimed < budget)
995 mp->work_tx &= ~(1 << txq->index);
1001 /* tx rate control **********************************************************/
1003 * Set total maximum TX rate (shared by all TX queues for this port)
1004 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1006 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1012 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1013 if (token_rate > 1023)
1016 mtu = (mp->dev->mtu + 255) >> 8;
1020 bucket_size = (burst + 255) >> 8;
1021 if (bucket_size > 65535)
1022 bucket_size = 65535;
1024 switch (mp->shared->tx_bw_control) {
1025 case TX_BW_CONTROL_OLD_LAYOUT:
1026 wrlp(mp, TX_BW_RATE, token_rate);
1027 wrlp(mp, TX_BW_MTU, mtu);
1028 wrlp(mp, TX_BW_BURST, bucket_size);
1030 case TX_BW_CONTROL_NEW_LAYOUT:
1031 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1032 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1033 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1038 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1040 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1044 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1045 if (token_rate > 1023)
1048 bucket_size = (burst + 255) >> 8;
1049 if (bucket_size > 65535)
1050 bucket_size = 65535;
1052 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1053 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1056 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1058 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1063 * Turn on fixed priority mode.
1066 switch (mp->shared->tx_bw_control) {
1067 case TX_BW_CONTROL_OLD_LAYOUT:
1068 off = TXQ_FIX_PRIO_CONF;
1070 case TX_BW_CONTROL_NEW_LAYOUT:
1071 off = TXQ_FIX_PRIO_CONF_MOVED;
1076 val = rdlp(mp, off);
1077 val |= 1 << txq->index;
1083 /* mii management interface *************************************************/
1084 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1086 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1087 u32 autoneg_disable = FORCE_LINK_PASS |
1088 DISABLE_AUTO_NEG_SPEED_GMII |
1089 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1090 DISABLE_AUTO_NEG_FOR_DUPLEX;
1092 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1093 /* enable auto negotiation */
1094 pscr &= ~autoneg_disable;
1098 pscr |= autoneg_disable;
1100 if (mp->phy->speed == SPEED_1000) {
1101 /* force gigabit, half duplex not supported */
1102 pscr |= SET_GMII_SPEED_TO_1000;
1103 pscr |= SET_FULL_DUPLEX_MODE;
1107 pscr &= ~SET_GMII_SPEED_TO_1000;
1109 if (mp->phy->speed == SPEED_100)
1110 pscr |= SET_MII_SPEED_TO_100;
1112 pscr &= ~SET_MII_SPEED_TO_100;
1114 if (mp->phy->duplex == DUPLEX_FULL)
1115 pscr |= SET_FULL_DUPLEX_MODE;
1117 pscr &= ~SET_FULL_DUPLEX_MODE;
1120 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1123 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1125 struct mv643xx_eth_shared_private *msp = dev_id;
1127 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1128 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1129 wake_up(&msp->smi_busy_wait);
1136 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1138 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1141 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1143 if (msp->err_interrupt == NO_IRQ) {
1146 for (i = 0; !smi_is_done(msp); i++) {
1155 if (!smi_is_done(msp)) {
1156 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1157 msecs_to_jiffies(100));
1158 if (!smi_is_done(msp))
1165 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1167 struct mv643xx_eth_shared_private *msp = bus->priv;
1168 void __iomem *smi_reg = msp->base + SMI_REG;
1171 if (smi_wait_ready(msp)) {
1172 pr_warn("SMI bus busy timeout\n");
1176 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1178 if (smi_wait_ready(msp)) {
1179 pr_warn("SMI bus busy timeout\n");
1183 ret = readl(smi_reg);
1184 if (!(ret & SMI_READ_VALID)) {
1185 pr_warn("SMI bus read not valid\n");
1189 return ret & 0xffff;
1192 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1194 struct mv643xx_eth_shared_private *msp = bus->priv;
1195 void __iomem *smi_reg = msp->base + SMI_REG;
1197 if (smi_wait_ready(msp)) {
1198 pr_warn("SMI bus busy timeout\n");
1202 writel(SMI_OPCODE_WRITE | (reg << 21) |
1203 (addr << 16) | (val & 0xffff), smi_reg);
1205 if (smi_wait_ready(msp)) {
1206 pr_warn("SMI bus busy timeout\n");
1214 /* statistics ***************************************************************/
1215 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1217 struct mv643xx_eth_private *mp = netdev_priv(dev);
1218 struct net_device_stats *stats = &dev->stats;
1219 unsigned long tx_packets = 0;
1220 unsigned long tx_bytes = 0;
1221 unsigned long tx_dropped = 0;
1224 for (i = 0; i < mp->txq_count; i++) {
1225 struct tx_queue *txq = mp->txq + i;
1227 tx_packets += txq->tx_packets;
1228 tx_bytes += txq->tx_bytes;
1229 tx_dropped += txq->tx_dropped;
1232 stats->tx_packets = tx_packets;
1233 stats->tx_bytes = tx_bytes;
1234 stats->tx_dropped = tx_dropped;
1239 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1241 u32 lro_aggregated = 0;
1242 u32 lro_flushed = 0;
1243 u32 lro_no_desc = 0;
1246 for (i = 0; i < mp->rxq_count; i++) {
1247 struct rx_queue *rxq = mp->rxq + i;
1249 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1250 lro_flushed += rxq->lro_mgr.stats.flushed;
1251 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1254 mp->lro_counters.lro_aggregated = lro_aggregated;
1255 mp->lro_counters.lro_flushed = lro_flushed;
1256 mp->lro_counters.lro_no_desc = lro_no_desc;
1259 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1261 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1264 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1268 for (i = 0; i < 0x80; i += 4)
1271 /* Clear non MIB hw counters also */
1272 rdlp(mp, RX_DISCARD_FRAME_CNT);
1273 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1276 static void mib_counters_update(struct mv643xx_eth_private *mp)
1278 struct mib_counters *p = &mp->mib_counters;
1280 spin_lock_bh(&mp->mib_counters_lock);
1281 p->good_octets_received += mib_read(mp, 0x00);
1282 p->bad_octets_received += mib_read(mp, 0x08);
1283 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1284 p->good_frames_received += mib_read(mp, 0x10);
1285 p->bad_frames_received += mib_read(mp, 0x14);
1286 p->broadcast_frames_received += mib_read(mp, 0x18);
1287 p->multicast_frames_received += mib_read(mp, 0x1c);
1288 p->frames_64_octets += mib_read(mp, 0x20);
1289 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1290 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1291 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1292 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1293 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1294 p->good_octets_sent += mib_read(mp, 0x38);
1295 p->good_frames_sent += mib_read(mp, 0x40);
1296 p->excessive_collision += mib_read(mp, 0x44);
1297 p->multicast_frames_sent += mib_read(mp, 0x48);
1298 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1299 p->unrec_mac_control_received += mib_read(mp, 0x50);
1300 p->fc_sent += mib_read(mp, 0x54);
1301 p->good_fc_received += mib_read(mp, 0x58);
1302 p->bad_fc_received += mib_read(mp, 0x5c);
1303 p->undersize_received += mib_read(mp, 0x60);
1304 p->fragments_received += mib_read(mp, 0x64);
1305 p->oversize_received += mib_read(mp, 0x68);
1306 p->jabber_received += mib_read(mp, 0x6c);
1307 p->mac_receive_error += mib_read(mp, 0x70);
1308 p->bad_crc_event += mib_read(mp, 0x74);
1309 p->collision += mib_read(mp, 0x78);
1310 p->late_collision += mib_read(mp, 0x7c);
1311 /* Non MIB hardware counters */
1312 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1313 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1314 spin_unlock_bh(&mp->mib_counters_lock);
1316 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1319 static void mib_counters_timer_wrapper(unsigned long _mp)
1321 struct mv643xx_eth_private *mp = (void *)_mp;
1323 mib_counters_update(mp);
1327 /* interrupt coalescing *****************************************************/
1329 * Hardware coalescing parameters are set in units of 64 t_clk
1332 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1334 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1336 * In the ->set*() methods, we round the computed register value
1337 * to the nearest integer.
1339 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1341 u32 val = rdlp(mp, SDMA_CONFIG);
1344 if (mp->shared->extended_rx_coal_limit)
1345 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1347 temp = (val & 0x003fff00) >> 8;
1350 do_div(temp, mp->t_clk);
1352 return (unsigned int)temp;
1355 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1360 temp = (u64)usec * mp->t_clk;
1362 do_div(temp, 64000000);
1364 val = rdlp(mp, SDMA_CONFIG);
1365 if (mp->shared->extended_rx_coal_limit) {
1369 val |= (temp & 0x8000) << 10;
1370 val |= (temp & 0x7fff) << 7;
1375 val |= (temp & 0x3fff) << 8;
1377 wrlp(mp, SDMA_CONFIG, val);
1380 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1384 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1386 do_div(temp, mp->t_clk);
1388 return (unsigned int)temp;
1391 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1395 temp = (u64)usec * mp->t_clk;
1397 do_div(temp, 64000000);
1402 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1406 /* ethtool ******************************************************************/
1407 struct mv643xx_eth_stats {
1408 char stat_string[ETH_GSTRING_LEN];
1415 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1416 offsetof(struct net_device, stats.m), -1 }
1418 #define MIBSTAT(m) \
1419 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1420 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1422 #define LROSTAT(m) \
1423 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1424 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1426 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1435 MIBSTAT(good_octets_received),
1436 MIBSTAT(bad_octets_received),
1437 MIBSTAT(internal_mac_transmit_err),
1438 MIBSTAT(good_frames_received),
1439 MIBSTAT(bad_frames_received),
1440 MIBSTAT(broadcast_frames_received),
1441 MIBSTAT(multicast_frames_received),
1442 MIBSTAT(frames_64_octets),
1443 MIBSTAT(frames_65_to_127_octets),
1444 MIBSTAT(frames_128_to_255_octets),
1445 MIBSTAT(frames_256_to_511_octets),
1446 MIBSTAT(frames_512_to_1023_octets),
1447 MIBSTAT(frames_1024_to_max_octets),
1448 MIBSTAT(good_octets_sent),
1449 MIBSTAT(good_frames_sent),
1450 MIBSTAT(excessive_collision),
1451 MIBSTAT(multicast_frames_sent),
1452 MIBSTAT(broadcast_frames_sent),
1453 MIBSTAT(unrec_mac_control_received),
1455 MIBSTAT(good_fc_received),
1456 MIBSTAT(bad_fc_received),
1457 MIBSTAT(undersize_received),
1458 MIBSTAT(fragments_received),
1459 MIBSTAT(oversize_received),
1460 MIBSTAT(jabber_received),
1461 MIBSTAT(mac_receive_error),
1462 MIBSTAT(bad_crc_event),
1464 MIBSTAT(late_collision),
1465 MIBSTAT(rx_discard),
1466 MIBSTAT(rx_overrun),
1467 LROSTAT(lro_aggregated),
1468 LROSTAT(lro_flushed),
1469 LROSTAT(lro_no_desc),
1473 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1474 struct ethtool_cmd *cmd)
1478 err = phy_read_status(mp->phy);
1480 err = phy_ethtool_gset(mp->phy, cmd);
1483 * The MAC does not support 1000baseT_Half.
1485 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1486 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1492 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1493 struct ethtool_cmd *cmd)
1497 port_status = rdlp(mp, PORT_STATUS);
1499 cmd->supported = SUPPORTED_MII;
1500 cmd->advertising = ADVERTISED_MII;
1501 switch (port_status & PORT_SPEED_MASK) {
1503 ethtool_cmd_speed_set(cmd, SPEED_10);
1505 case PORT_SPEED_100:
1506 ethtool_cmd_speed_set(cmd, SPEED_100);
1508 case PORT_SPEED_1000:
1509 ethtool_cmd_speed_set(cmd, SPEED_1000);
1515 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1516 cmd->port = PORT_MII;
1517 cmd->phy_address = 0;
1518 cmd->transceiver = XCVR_INTERNAL;
1519 cmd->autoneg = AUTONEG_DISABLE;
1527 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1529 struct mv643xx_eth_private *mp = netdev_priv(dev);
1531 if (mp->phy != NULL)
1532 return mv643xx_eth_get_settings_phy(mp, cmd);
1534 return mv643xx_eth_get_settings_phyless(mp, cmd);
1538 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1540 struct mv643xx_eth_private *mp = netdev_priv(dev);
1543 if (mp->phy == NULL)
1547 * The MAC does not support 1000baseT_Half.
1549 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1551 ret = phy_ethtool_sset(mp->phy, cmd);
1553 mv643xx_adjust_pscr(mp);
1557 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1558 struct ethtool_drvinfo *drvinfo)
1560 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1561 sizeof(drvinfo->driver));
1562 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1563 sizeof(drvinfo->version));
1564 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1565 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1566 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1569 static int mv643xx_eth_nway_reset(struct net_device *dev)
1571 struct mv643xx_eth_private *mp = netdev_priv(dev);
1573 if (mp->phy == NULL)
1576 return genphy_restart_aneg(mp->phy);
1580 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1582 struct mv643xx_eth_private *mp = netdev_priv(dev);
1584 ec->rx_coalesce_usecs = get_rx_coal(mp);
1585 ec->tx_coalesce_usecs = get_tx_coal(mp);
1591 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1593 struct mv643xx_eth_private *mp = netdev_priv(dev);
1595 set_rx_coal(mp, ec->rx_coalesce_usecs);
1596 set_tx_coal(mp, ec->tx_coalesce_usecs);
1602 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1604 struct mv643xx_eth_private *mp = netdev_priv(dev);
1606 er->rx_max_pending = 4096;
1607 er->tx_max_pending = 4096;
1609 er->rx_pending = mp->rx_ring_size;
1610 er->tx_pending = mp->tx_ring_size;
1614 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1616 struct mv643xx_eth_private *mp = netdev_priv(dev);
1618 if (er->rx_mini_pending || er->rx_jumbo_pending)
1621 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1622 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1624 if (netif_running(dev)) {
1625 mv643xx_eth_stop(dev);
1626 if (mv643xx_eth_open(dev)) {
1628 "fatal error on re-opening device after ring param change\n");
1638 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1640 struct mv643xx_eth_private *mp = netdev_priv(dev);
1641 bool rx_csum = features & NETIF_F_RXCSUM;
1643 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1648 static void mv643xx_eth_get_strings(struct net_device *dev,
1649 uint32_t stringset, uint8_t *data)
1653 if (stringset == ETH_SS_STATS) {
1654 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1655 memcpy(data + i * ETH_GSTRING_LEN,
1656 mv643xx_eth_stats[i].stat_string,
1662 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1663 struct ethtool_stats *stats,
1666 struct mv643xx_eth_private *mp = netdev_priv(dev);
1669 mv643xx_eth_get_stats(dev);
1670 mib_counters_update(mp);
1671 mv643xx_eth_grab_lro_stats(mp);
1673 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1674 const struct mv643xx_eth_stats *stat;
1677 stat = mv643xx_eth_stats + i;
1679 if (stat->netdev_off >= 0)
1680 p = ((void *)mp->dev) + stat->netdev_off;
1682 p = ((void *)mp) + stat->mp_off;
1684 data[i] = (stat->sizeof_stat == 8) ?
1685 *(uint64_t *)p : *(uint32_t *)p;
1689 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1691 if (sset == ETH_SS_STATS)
1692 return ARRAY_SIZE(mv643xx_eth_stats);
1697 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1698 .get_settings = mv643xx_eth_get_settings,
1699 .set_settings = mv643xx_eth_set_settings,
1700 .get_drvinfo = mv643xx_eth_get_drvinfo,
1701 .nway_reset = mv643xx_eth_nway_reset,
1702 .get_link = ethtool_op_get_link,
1703 .get_coalesce = mv643xx_eth_get_coalesce,
1704 .set_coalesce = mv643xx_eth_set_coalesce,
1705 .get_ringparam = mv643xx_eth_get_ringparam,
1706 .set_ringparam = mv643xx_eth_set_ringparam,
1707 .get_strings = mv643xx_eth_get_strings,
1708 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1709 .get_sset_count = mv643xx_eth_get_sset_count,
1710 .get_ts_info = ethtool_op_get_ts_info,
1714 /* address handling *********************************************************/
1715 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1717 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1718 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1720 addr[0] = (mac_h >> 24) & 0xff;
1721 addr[1] = (mac_h >> 16) & 0xff;
1722 addr[2] = (mac_h >> 8) & 0xff;
1723 addr[3] = mac_h & 0xff;
1724 addr[4] = (mac_l >> 8) & 0xff;
1725 addr[5] = mac_l & 0xff;
1728 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1730 wrlp(mp, MAC_ADDR_HIGH,
1731 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1732 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1735 static u32 uc_addr_filter_mask(struct net_device *dev)
1737 struct netdev_hw_addr *ha;
1740 if (dev->flags & IFF_PROMISC)
1743 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1744 netdev_for_each_uc_addr(ha, dev) {
1745 if (memcmp(dev->dev_addr, ha->addr, 5))
1747 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1750 nibbles |= 1 << (ha->addr[5] & 0x0f);
1756 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1758 struct mv643xx_eth_private *mp = netdev_priv(dev);
1763 uc_addr_set(mp, dev->dev_addr);
1765 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1767 nibbles = uc_addr_filter_mask(dev);
1769 port_config |= UNICAST_PROMISCUOUS_MODE;
1773 for (i = 0; i < 16; i += 4) {
1774 int off = UNICAST_TABLE(mp->port_num) + i;
1791 wrlp(mp, PORT_CONFIG, port_config);
1794 static int addr_crc(unsigned char *addr)
1799 for (i = 0; i < 6; i++) {
1802 crc = (crc ^ addr[i]) << 8;
1803 for (j = 7; j >= 0; j--) {
1804 if (crc & (0x100 << j))
1812 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1814 struct mv643xx_eth_private *mp = netdev_priv(dev);
1817 struct netdev_hw_addr *ha;
1820 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1825 port_num = mp->port_num;
1826 accept = 0x01010101;
1827 for (i = 0; i < 0x100; i += 4) {
1828 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1829 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1834 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1835 if (mc_spec == NULL)
1837 mc_other = mc_spec + (0x100 >> 2);
1839 memset(mc_spec, 0, 0x100);
1840 memset(mc_other, 0, 0x100);
1842 netdev_for_each_mc_addr(ha, dev) {
1847 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1852 entry = addr_crc(a);
1855 table[entry >> 2] |= 1 << (8 * (entry & 3));
1858 for (i = 0; i < 0x100; i += 4) {
1859 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1860 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1866 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1868 mv643xx_eth_program_unicast_filter(dev);
1869 mv643xx_eth_program_multicast_filter(dev);
1872 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1874 struct sockaddr *sa = addr;
1876 if (!is_valid_ether_addr(sa->sa_data))
1877 return -EADDRNOTAVAIL;
1879 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1881 netif_addr_lock_bh(dev);
1882 mv643xx_eth_program_unicast_filter(dev);
1883 netif_addr_unlock_bh(dev);
1889 /* rx/tx queue initialisation ***********************************************/
1890 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1892 struct rx_queue *rxq = mp->rxq + index;
1893 struct rx_desc *rx_desc;
1899 rxq->rx_ring_size = mp->rx_ring_size;
1901 rxq->rx_desc_count = 0;
1902 rxq->rx_curr_desc = 0;
1903 rxq->rx_used_desc = 0;
1905 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1907 if (index == 0 && size <= mp->rx_desc_sram_size) {
1908 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1909 mp->rx_desc_sram_size);
1910 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1912 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1913 size, &rxq->rx_desc_dma,
1917 if (rxq->rx_desc_area == NULL) {
1919 "can't allocate rx ring (%d bytes)\n", size);
1922 memset(rxq->rx_desc_area, 0, size);
1924 rxq->rx_desc_area_size = size;
1925 rxq->rx_skb = kmalloc_array(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1927 if (rxq->rx_skb == NULL)
1930 rx_desc = rxq->rx_desc_area;
1931 for (i = 0; i < rxq->rx_ring_size; i++) {
1935 if (nexti == rxq->rx_ring_size)
1938 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1939 nexti * sizeof(struct rx_desc);
1942 rxq->lro_mgr.dev = mp->dev;
1943 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1944 rxq->lro_mgr.features = LRO_F_NAPI;
1945 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1946 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1947 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1948 rxq->lro_mgr.max_aggr = 32;
1949 rxq->lro_mgr.frag_align_pad = 0;
1950 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1951 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1953 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1959 if (index == 0 && size <= mp->rx_desc_sram_size)
1960 iounmap(rxq->rx_desc_area);
1962 dma_free_coherent(mp->dev->dev.parent, size,
1970 static void rxq_deinit(struct rx_queue *rxq)
1972 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1977 for (i = 0; i < rxq->rx_ring_size; i++) {
1978 if (rxq->rx_skb[i]) {
1979 dev_kfree_skb(rxq->rx_skb[i]);
1980 rxq->rx_desc_count--;
1984 if (rxq->rx_desc_count) {
1985 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1986 rxq->rx_desc_count);
1989 if (rxq->index == 0 &&
1990 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1991 iounmap(rxq->rx_desc_area);
1993 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1994 rxq->rx_desc_area, rxq->rx_desc_dma);
1999 static int txq_init(struct mv643xx_eth_private *mp, int index)
2001 struct tx_queue *txq = mp->txq + index;
2002 struct tx_desc *tx_desc;
2008 txq->tx_ring_size = mp->tx_ring_size;
2010 txq->tx_desc_count = 0;
2011 txq->tx_curr_desc = 0;
2012 txq->tx_used_desc = 0;
2014 size = txq->tx_ring_size * sizeof(struct tx_desc);
2016 if (index == 0 && size <= mp->tx_desc_sram_size) {
2017 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2018 mp->tx_desc_sram_size);
2019 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2021 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2022 size, &txq->tx_desc_dma,
2026 if (txq->tx_desc_area == NULL) {
2028 "can't allocate tx ring (%d bytes)\n", size);
2031 memset(txq->tx_desc_area, 0, size);
2033 txq->tx_desc_area_size = size;
2035 tx_desc = txq->tx_desc_area;
2036 for (i = 0; i < txq->tx_ring_size; i++) {
2037 struct tx_desc *txd = tx_desc + i;
2041 if (nexti == txq->tx_ring_size)
2045 txd->next_desc_ptr = txq->tx_desc_dma +
2046 nexti * sizeof(struct tx_desc);
2049 skb_queue_head_init(&txq->tx_skb);
2054 static void txq_deinit(struct tx_queue *txq)
2056 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2059 txq_reclaim(txq, txq->tx_ring_size, 1);
2061 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2063 if (txq->index == 0 &&
2064 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2065 iounmap(txq->tx_desc_area);
2067 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2068 txq->tx_desc_area, txq->tx_desc_dma);
2072 /* netdev ops and related ***************************************************/
2073 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2078 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2083 if (int_cause & INT_EXT) {
2084 int_cause &= ~INT_EXT;
2085 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2089 wrlp(mp, INT_CAUSE, ~int_cause);
2090 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2091 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2092 mp->work_rx |= (int_cause & INT_RX) >> 2;
2095 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2096 if (int_cause_ext) {
2097 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2098 if (int_cause_ext & INT_EXT_LINK_PHY)
2100 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2106 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2108 struct net_device *dev = (struct net_device *)dev_id;
2109 struct mv643xx_eth_private *mp = netdev_priv(dev);
2111 if (unlikely(!mv643xx_eth_collect_events(mp)))
2114 wrlp(mp, INT_MASK, 0);
2115 napi_schedule(&mp->napi);
2120 static void handle_link_event(struct mv643xx_eth_private *mp)
2122 struct net_device *dev = mp->dev;
2128 port_status = rdlp(mp, PORT_STATUS);
2129 if (!(port_status & LINK_UP)) {
2130 if (netif_carrier_ok(dev)) {
2133 netdev_info(dev, "link down\n");
2135 netif_carrier_off(dev);
2137 for (i = 0; i < mp->txq_count; i++) {
2138 struct tx_queue *txq = mp->txq + i;
2140 txq_reclaim(txq, txq->tx_ring_size, 1);
2141 txq_reset_hw_ptr(txq);
2147 switch (port_status & PORT_SPEED_MASK) {
2151 case PORT_SPEED_100:
2154 case PORT_SPEED_1000:
2161 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2162 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2164 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2165 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2167 if (!netif_carrier_ok(dev))
2168 netif_carrier_on(dev);
2171 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2173 struct mv643xx_eth_private *mp;
2176 mp = container_of(napi, struct mv643xx_eth_private, napi);
2178 if (unlikely(mp->oom)) {
2180 del_timer(&mp->rx_oom);
2184 while (work_done < budget) {
2189 if (mp->work_link) {
2191 handle_link_event(mp);
2196 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2197 if (likely(!mp->oom))
2198 queue_mask |= mp->work_rx_refill;
2201 if (mv643xx_eth_collect_events(mp))
2206 queue = fls(queue_mask) - 1;
2207 queue_mask = 1 << queue;
2209 work_tbd = budget - work_done;
2213 if (mp->work_tx_end & queue_mask) {
2214 txq_kick(mp->txq + queue);
2215 } else if (mp->work_tx & queue_mask) {
2216 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2217 txq_maybe_wake(mp->txq + queue);
2218 } else if (mp->work_rx & queue_mask) {
2219 work_done += rxq_process(mp->rxq + queue, work_tbd);
2220 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2221 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2227 if (work_done < budget) {
2229 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2230 napi_complete(napi);
2231 wrlp(mp, INT_MASK, mp->int_mask);
2237 static inline void oom_timer_wrapper(unsigned long data)
2239 struct mv643xx_eth_private *mp = (void *)data;
2241 napi_schedule(&mp->napi);
2244 static void phy_reset(struct mv643xx_eth_private *mp)
2248 data = phy_read(mp->phy, MII_BMCR);
2253 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2257 data = phy_read(mp->phy, MII_BMCR);
2258 } while (data >= 0 && data & BMCR_RESET);
2261 static void port_start(struct mv643xx_eth_private *mp)
2267 * Perform PHY reset, if there is a PHY.
2269 if (mp->phy != NULL) {
2270 struct ethtool_cmd cmd;
2272 mv643xx_eth_get_settings(mp->dev, &cmd);
2274 mv643xx_eth_set_settings(mp->dev, &cmd);
2278 * Configure basic link parameters.
2280 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2282 pscr |= SERIAL_PORT_ENABLE;
2283 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2285 pscr |= DO_NOT_FORCE_LINK_FAIL;
2286 if (mp->phy == NULL)
2287 pscr |= FORCE_LINK_PASS;
2288 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2291 * Configure TX path and queues.
2293 tx_set_rate(mp, 1000000000, 16777216);
2294 for (i = 0; i < mp->txq_count; i++) {
2295 struct tx_queue *txq = mp->txq + i;
2297 txq_reset_hw_ptr(txq);
2298 txq_set_rate(txq, 1000000000, 16777216);
2299 txq_set_fixed_prio_mode(txq);
2303 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2304 * frames to RX queue #0, and include the pseudo-header when
2305 * calculating receive checksums.
2307 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2310 * Treat BPDUs as normal multicasts, and disable partition mode.
2312 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2315 * Add configured unicast addresses to address filter table.
2317 mv643xx_eth_program_unicast_filter(mp->dev);
2320 * Enable the receive queues.
2322 for (i = 0; i < mp->rxq_count; i++) {
2323 struct rx_queue *rxq = mp->rxq + i;
2326 addr = (u32)rxq->rx_desc_dma;
2327 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2328 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2334 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2339 * Reserve 2+14 bytes for an ethernet header (the hardware
2340 * automatically prepends 2 bytes of dummy data to each
2341 * received packet), 16 bytes for up to four VLAN tags, and
2342 * 4 bytes for the trailing FCS -- 36 bytes total.
2344 skb_size = mp->dev->mtu + 36;
2347 * Make sure that the skb size is a multiple of 8 bytes, as
2348 * the lower three bits of the receive descriptor's buffer
2349 * size field are ignored by the hardware.
2351 mp->skb_size = (skb_size + 7) & ~7;
2354 * If NET_SKB_PAD is smaller than a cache line,
2355 * netdev_alloc_skb() will cause skb->data to be misaligned
2356 * to a cache line boundary. If this is the case, include
2357 * some extra space to allow re-aligning the data area.
2359 mp->skb_size += SKB_DMA_REALIGN;
2362 static int mv643xx_eth_open(struct net_device *dev)
2364 struct mv643xx_eth_private *mp = netdev_priv(dev);
2368 wrlp(mp, INT_CAUSE, 0);
2369 wrlp(mp, INT_CAUSE_EXT, 0);
2370 rdlp(mp, INT_CAUSE_EXT);
2372 err = request_irq(dev->irq, mv643xx_eth_irq,
2373 IRQF_SHARED, dev->name, dev);
2375 netdev_err(dev, "can't assign irq\n");
2379 mv643xx_eth_recalc_skb_size(mp);
2381 napi_enable(&mp->napi);
2383 mp->int_mask = INT_EXT;
2385 for (i = 0; i < mp->rxq_count; i++) {
2386 err = rxq_init(mp, i);
2389 rxq_deinit(mp->rxq + i);
2393 rxq_refill(mp->rxq + i, INT_MAX);
2394 mp->int_mask |= INT_RX_0 << i;
2398 mp->rx_oom.expires = jiffies + (HZ / 10);
2399 add_timer(&mp->rx_oom);
2402 for (i = 0; i < mp->txq_count; i++) {
2403 err = txq_init(mp, i);
2406 txq_deinit(mp->txq + i);
2409 mp->int_mask |= INT_TX_END_0 << i;
2414 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2415 wrlp(mp, INT_MASK, mp->int_mask);
2421 for (i = 0; i < mp->rxq_count; i++)
2422 rxq_deinit(mp->rxq + i);
2424 free_irq(dev->irq, dev);
2429 static void port_reset(struct mv643xx_eth_private *mp)
2434 for (i = 0; i < mp->rxq_count; i++)
2435 rxq_disable(mp->rxq + i);
2436 for (i = 0; i < mp->txq_count; i++)
2437 txq_disable(mp->txq + i);
2440 u32 ps = rdlp(mp, PORT_STATUS);
2442 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2447 /* Reset the Enable bit in the Configuration Register */
2448 data = rdlp(mp, PORT_SERIAL_CONTROL);
2449 data &= ~(SERIAL_PORT_ENABLE |
2450 DO_NOT_FORCE_LINK_FAIL |
2452 wrlp(mp, PORT_SERIAL_CONTROL, data);
2455 static int mv643xx_eth_stop(struct net_device *dev)
2457 struct mv643xx_eth_private *mp = netdev_priv(dev);
2460 wrlp(mp, INT_MASK_EXT, 0x00000000);
2461 wrlp(mp, INT_MASK, 0x00000000);
2464 napi_disable(&mp->napi);
2466 del_timer_sync(&mp->rx_oom);
2468 netif_carrier_off(dev);
2470 free_irq(dev->irq, dev);
2473 mv643xx_eth_get_stats(dev);
2474 mib_counters_update(mp);
2475 del_timer_sync(&mp->mib_counters_timer);
2477 for (i = 0; i < mp->rxq_count; i++)
2478 rxq_deinit(mp->rxq + i);
2479 for (i = 0; i < mp->txq_count; i++)
2480 txq_deinit(mp->txq + i);
2485 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2487 struct mv643xx_eth_private *mp = netdev_priv(dev);
2490 if (mp->phy == NULL)
2493 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2495 mv643xx_adjust_pscr(mp);
2499 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2501 struct mv643xx_eth_private *mp = netdev_priv(dev);
2503 if (new_mtu < 64 || new_mtu > 9500)
2507 mv643xx_eth_recalc_skb_size(mp);
2508 tx_set_rate(mp, 1000000000, 16777216);
2510 if (!netif_running(dev))
2514 * Stop and then re-open the interface. This will allocate RX
2515 * skbs of the new MTU.
2516 * There is a possible danger that the open will not succeed,
2517 * due to memory being full.
2519 mv643xx_eth_stop(dev);
2520 if (mv643xx_eth_open(dev)) {
2522 "fatal error on re-opening device after MTU change\n");
2528 static void tx_timeout_task(struct work_struct *ugly)
2530 struct mv643xx_eth_private *mp;
2532 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2533 if (netif_running(mp->dev)) {
2534 netif_tx_stop_all_queues(mp->dev);
2537 netif_tx_wake_all_queues(mp->dev);
2541 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2543 struct mv643xx_eth_private *mp = netdev_priv(dev);
2545 netdev_info(dev, "tx timeout\n");
2547 schedule_work(&mp->tx_timeout_task);
2550 #ifdef CONFIG_NET_POLL_CONTROLLER
2551 static void mv643xx_eth_netpoll(struct net_device *dev)
2553 struct mv643xx_eth_private *mp = netdev_priv(dev);
2555 wrlp(mp, INT_MASK, 0x00000000);
2558 mv643xx_eth_irq(dev->irq, dev);
2560 wrlp(mp, INT_MASK, mp->int_mask);
2565 /* platform glue ************************************************************/
2567 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2568 const struct mbus_dram_target_info *dram)
2570 void __iomem *base = msp->base;
2575 for (i = 0; i < 6; i++) {
2576 writel(0, base + WINDOW_BASE(i));
2577 writel(0, base + WINDOW_SIZE(i));
2579 writel(0, base + WINDOW_REMAP_HIGH(i));
2585 for (i = 0; i < dram->num_cs; i++) {
2586 const struct mbus_dram_window *cs = dram->cs + i;
2588 writel((cs->base & 0xffff0000) |
2589 (cs->mbus_attr << 8) |
2590 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2591 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2593 win_enable &= ~(1 << i);
2594 win_protect |= 3 << (2 * i);
2597 writel(win_enable, base + WINDOW_BAR_ENABLE);
2598 msp->win_protect = win_protect;
2601 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2604 * Check whether we have a 14-bit coal limit field in bits
2605 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2606 * SDMA config register.
2608 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2609 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2610 msp->extended_rx_coal_limit = 1;
2612 msp->extended_rx_coal_limit = 0;
2615 * Check whether the MAC supports TX rate control, and if
2616 * yes, whether its associated registers are in the old or
2619 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2620 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2621 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2623 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2624 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2625 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2627 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2631 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2633 static int mv643xx_eth_version_printed;
2634 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2635 struct mv643xx_eth_shared_private *msp;
2636 const struct mbus_dram_target_info *dram;
2637 struct resource *res;
2640 if (!mv643xx_eth_version_printed++)
2641 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2642 mv643xx_eth_driver_version);
2645 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2650 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
2654 msp->base = ioremap(res->start, resource_size(res));
2655 if (msp->base == NULL)
2659 * Set up and register SMI bus.
2661 if (pd == NULL || pd->shared_smi == NULL) {
2662 msp->smi_bus = mdiobus_alloc();
2663 if (msp->smi_bus == NULL)
2666 msp->smi_bus->priv = msp;
2667 msp->smi_bus->name = "mv643xx_eth smi";
2668 msp->smi_bus->read = smi_bus_read;
2669 msp->smi_bus->write = smi_bus_write,
2670 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
2671 pdev->name, pdev->id);
2672 msp->smi_bus->parent = &pdev->dev;
2673 msp->smi_bus->phy_mask = 0xffffffff;
2674 if (mdiobus_register(msp->smi_bus) < 0)
2675 goto out_free_mii_bus;
2678 msp->smi = platform_get_drvdata(pd->shared_smi);
2681 msp->err_interrupt = NO_IRQ;
2682 init_waitqueue_head(&msp->smi_busy_wait);
2685 * Check whether the error interrupt is hooked up.
2687 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2691 err = request_irq(res->start, mv643xx_eth_err_irq,
2692 IRQF_SHARED, "mv643xx_eth", msp);
2694 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2695 msp->err_interrupt = res->start;
2700 * (Re-)program MBUS remapping windows if we are asked to.
2702 dram = mv_mbus_dram_info();
2704 mv643xx_eth_conf_mbus_windows(msp, dram);
2706 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2707 pd->tx_csum_limit : 9 * 1024;
2708 infer_hw_params(msp);
2710 platform_set_drvdata(pdev, msp);
2715 mdiobus_free(msp->smi_bus);
2724 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2726 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2727 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2729 if (pd == NULL || pd->shared_smi == NULL) {
2730 mdiobus_unregister(msp->smi_bus);
2731 mdiobus_free(msp->smi_bus);
2733 if (msp->err_interrupt != NO_IRQ)
2734 free_irq(msp->err_interrupt, msp);
2741 static struct platform_driver mv643xx_eth_shared_driver = {
2742 .probe = mv643xx_eth_shared_probe,
2743 .remove = mv643xx_eth_shared_remove,
2745 .name = MV643XX_ETH_SHARED_NAME,
2746 .owner = THIS_MODULE,
2750 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2752 int addr_shift = 5 * mp->port_num;
2755 data = rdl(mp, PHY_ADDR);
2756 data &= ~(0x1f << addr_shift);
2757 data |= (phy_addr & 0x1f) << addr_shift;
2758 wrl(mp, PHY_ADDR, data);
2761 static int phy_addr_get(struct mv643xx_eth_private *mp)
2765 data = rdl(mp, PHY_ADDR);
2767 return (data >> (5 * mp->port_num)) & 0x1f;
2770 static void set_params(struct mv643xx_eth_private *mp,
2771 struct mv643xx_eth_platform_data *pd)
2773 struct net_device *dev = mp->dev;
2775 if (is_valid_ether_addr(pd->mac_addr))
2776 memcpy(dev->dev_addr, pd->mac_addr, 6);
2778 uc_addr_get(mp, dev->dev_addr);
2780 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2781 if (pd->rx_queue_size)
2782 mp->rx_ring_size = pd->rx_queue_size;
2783 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2784 mp->rx_desc_sram_size = pd->rx_sram_size;
2786 mp->rxq_count = pd->rx_queue_count ? : 1;
2788 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2789 if (pd->tx_queue_size)
2790 mp->tx_ring_size = pd->tx_queue_size;
2791 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2792 mp->tx_desc_sram_size = pd->tx_sram_size;
2794 mp->txq_count = pd->tx_queue_count ? : 1;
2797 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2800 struct mii_bus *bus = mp->shared->smi->smi_bus;
2801 struct phy_device *phydev;
2806 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2807 start = phy_addr_get(mp) & 0x1f;
2810 start = phy_addr & 0x1f;
2815 for (i = 0; i < num; i++) {
2816 int addr = (start + i) & 0x1f;
2818 if (bus->phy_map[addr] == NULL)
2819 mdiobus_scan(bus, addr);
2821 if (phydev == NULL) {
2822 phydev = bus->phy_map[addr];
2824 phy_addr_set(mp, addr);
2831 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2833 struct phy_device *phy = mp->phy;
2837 phy_attach(mp->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_GMII);
2840 phy->autoneg = AUTONEG_ENABLE;
2843 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2845 phy->autoneg = AUTONEG_DISABLE;
2846 phy->advertising = 0;
2848 phy->duplex = duplex;
2850 phy_start_aneg(phy);
2853 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2857 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2858 if (pscr & SERIAL_PORT_ENABLE) {
2859 pscr &= ~SERIAL_PORT_ENABLE;
2860 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2863 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2864 if (mp->phy == NULL) {
2865 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2866 if (speed == SPEED_1000)
2867 pscr |= SET_GMII_SPEED_TO_1000;
2868 else if (speed == SPEED_100)
2869 pscr |= SET_MII_SPEED_TO_100;
2871 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2873 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2874 if (duplex == DUPLEX_FULL)
2875 pscr |= SET_FULL_DUPLEX_MODE;
2878 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2881 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2882 .ndo_open = mv643xx_eth_open,
2883 .ndo_stop = mv643xx_eth_stop,
2884 .ndo_start_xmit = mv643xx_eth_xmit,
2885 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2886 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2887 .ndo_validate_addr = eth_validate_addr,
2888 .ndo_do_ioctl = mv643xx_eth_ioctl,
2889 .ndo_change_mtu = mv643xx_eth_change_mtu,
2890 .ndo_set_features = mv643xx_eth_set_features,
2891 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2892 .ndo_get_stats = mv643xx_eth_get_stats,
2893 #ifdef CONFIG_NET_POLL_CONTROLLER
2894 .ndo_poll_controller = mv643xx_eth_netpoll,
2898 static int mv643xx_eth_probe(struct platform_device *pdev)
2900 struct mv643xx_eth_platform_data *pd;
2901 struct mv643xx_eth_private *mp;
2902 struct net_device *dev;
2903 struct resource *res;
2906 pd = pdev->dev.platform_data;
2908 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2912 if (pd->shared == NULL) {
2913 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2917 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2921 mp = netdev_priv(dev);
2922 platform_set_drvdata(pdev, mp);
2924 mp->shared = platform_get_drvdata(pd->shared);
2925 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2926 mp->port_num = pd->port_number;
2931 * Start with a default rate, and if there is a clock, allow
2932 * it to override the default.
2934 mp->t_clk = 133000000;
2935 #if defined(CONFIG_HAVE_CLK)
2936 mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
2937 if (!IS_ERR(mp->clk)) {
2938 clk_prepare_enable(mp->clk);
2939 mp->t_clk = clk_get_rate(mp->clk);
2943 netif_set_real_num_tx_queues(dev, mp->txq_count);
2944 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2946 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2947 mp->phy = phy_scan(mp, pd->phy_addr);
2949 if (mp->phy != NULL)
2950 phy_init(mp, pd->speed, pd->duplex);
2952 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2954 init_pscr(mp, pd->speed, pd->duplex);
2957 mib_counters_clear(mp);
2959 init_timer(&mp->mib_counters_timer);
2960 mp->mib_counters_timer.data = (unsigned long)mp;
2961 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2962 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2963 add_timer(&mp->mib_counters_timer);
2965 spin_lock_init(&mp->mib_counters_lock);
2967 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2969 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2971 init_timer(&mp->rx_oom);
2972 mp->rx_oom.data = (unsigned long)mp;
2973 mp->rx_oom.function = oom_timer_wrapper;
2976 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2978 dev->irq = res->start;
2980 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2982 dev->watchdog_timeo = 2 * HZ;
2985 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2986 NETIF_F_RXCSUM | NETIF_F_LRO;
2987 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2988 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2990 dev->priv_flags |= IFF_UNICAST_FLT;
2992 SET_NETDEV_DEV(dev, &pdev->dev);
2994 if (mp->shared->win_protect)
2995 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2997 netif_carrier_off(dev);
2999 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3001 set_rx_coal(mp, 250);
3004 err = register_netdev(dev);
3008 netdev_notice(dev, "port %d with MAC address %pM\n",
3009 mp->port_num, dev->dev_addr);
3011 if (mp->tx_desc_sram_size > 0)
3012 netdev_notice(dev, "configured with sram\n");
3017 #if defined(CONFIG_HAVE_CLK)
3018 if (!IS_ERR(mp->clk)) {
3019 clk_disable_unprepare(mp->clk);
3028 static int mv643xx_eth_remove(struct platform_device *pdev)
3030 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3032 unregister_netdev(mp->dev);
3033 if (mp->phy != NULL)
3034 phy_detach(mp->phy);
3035 cancel_work_sync(&mp->tx_timeout_task);
3037 #if defined(CONFIG_HAVE_CLK)
3038 if (!IS_ERR(mp->clk)) {
3039 clk_disable_unprepare(mp->clk);
3044 free_netdev(mp->dev);
3046 platform_set_drvdata(pdev, NULL);
3051 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3053 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3055 /* Mask all interrupts on ethernet port */
3056 wrlp(mp, INT_MASK, 0);
3059 if (netif_running(mp->dev))
3063 static struct platform_driver mv643xx_eth_driver = {
3064 .probe = mv643xx_eth_probe,
3065 .remove = mv643xx_eth_remove,
3066 .shutdown = mv643xx_eth_shutdown,
3068 .name = MV643XX_ETH_NAME,
3069 .owner = THIS_MODULE,
3073 static int __init mv643xx_eth_init_module(void)
3077 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3079 rc = platform_driver_register(&mv643xx_eth_driver);
3081 platform_driver_unregister(&mv643xx_eth_shared_driver);
3086 module_init(mv643xx_eth_init_module);
3088 static void __exit mv643xx_eth_cleanup_module(void)
3090 platform_driver_unregister(&mv643xx_eth_driver);
3091 platform_driver_unregister(&mv643xx_eth_shared_driver);
3093 module_exit(mv643xx_eth_cleanup_module);
3095 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3096 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3097 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3098 MODULE_LICENSE("GPL");
3099 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3100 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);