2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/of_address.h>
31 #include <linux/phy.h>
32 #include <linux/clk.h>
35 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
36 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
37 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
38 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
39 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
40 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
41 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
42 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
43 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
44 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
45 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
46 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
47 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
48 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
49 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
50 #define MVNETA_PORT_RX_RESET 0x1cc0
51 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
52 #define MVNETA_PHY_ADDR 0x2000
53 #define MVNETA_PHY_ADDR_MASK 0x1f
54 #define MVNETA_MBUS_RETRY 0x2010
55 #define MVNETA_UNIT_INTR_CAUSE 0x2080
56 #define MVNETA_UNIT_CONTROL 0x20B0
57 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
58 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
59 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
60 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
61 #define MVNETA_BASE_ADDR_ENABLE 0x2290
62 #define MVNETA_PORT_CONFIG 0x2400
63 #define MVNETA_UNI_PROMISC_MODE BIT(0)
64 #define MVNETA_DEF_RXQ(q) ((q) << 1)
65 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
66 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
67 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
68 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
69 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
70 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
71 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
72 MVNETA_DEF_RXQ_ARP(q) | \
73 MVNETA_DEF_RXQ_TCP(q) | \
74 MVNETA_DEF_RXQ_UDP(q) | \
75 MVNETA_DEF_RXQ_BPDU(q) | \
76 MVNETA_TX_UNSET_ERR_SUM | \
77 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
78 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
79 #define MVNETA_MAC_ADDR_LOW 0x2414
80 #define MVNETA_MAC_ADDR_HIGH 0x2418
81 #define MVNETA_SDMA_CONFIG 0x241c
82 #define MVNETA_SDMA_BRST_SIZE_16 4
83 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
84 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
85 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
86 #define MVNETA_DESC_SWAP BIT(6)
87 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
88 #define MVNETA_PORT_STATUS 0x2444
89 #define MVNETA_TX_IN_PRGRS BIT(1)
90 #define MVNETA_TX_FIFO_EMPTY BIT(8)
91 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
92 #define MVNETA_SERDES_CFG 0x24A0
93 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
94 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
95 #define MVNETA_TYPE_PRIO 0x24bc
96 #define MVNETA_FORCE_UNI BIT(21)
97 #define MVNETA_TXQ_CMD_1 0x24e4
98 #define MVNETA_TXQ_CMD 0x2448
99 #define MVNETA_TXQ_DISABLE_SHIFT 8
100 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
101 #define MVNETA_ACC_MODE 0x2500
102 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
103 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
104 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
105 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
107 /* Exception Interrupt Port/Queue Cause register */
109 #define MVNETA_INTR_NEW_CAUSE 0x25a0
110 #define MVNETA_INTR_NEW_MASK 0x25a4
112 /* bits 0..7 = TXQ SENT, one bit per queue.
113 * bits 8..15 = RXQ OCCUP, one bit per queue.
114 * bits 16..23 = RXQ FREE, one bit per queue.
115 * bit 29 = OLD_REG_SUM, see old reg ?
116 * bit 30 = TX_ERR_SUM, one bit for 4 ports
117 * bit 31 = MISC_SUM, one bit for 4 ports
119 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
120 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
121 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
122 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
124 #define MVNETA_INTR_OLD_CAUSE 0x25a8
125 #define MVNETA_INTR_OLD_MASK 0x25ac
127 /* Data Path Port/Queue Cause Register */
128 #define MVNETA_INTR_MISC_CAUSE 0x25b0
129 #define MVNETA_INTR_MISC_MASK 0x25b4
131 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
132 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
133 #define MVNETA_CAUSE_PTP BIT(4)
135 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
136 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
137 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
138 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
139 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
140 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
141 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
142 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
144 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
145 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
146 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
148 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
149 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
150 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
152 #define MVNETA_INTR_ENABLE 0x25b8
153 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
154 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF
156 #define MVNETA_RXQ_CMD 0x2680
157 #define MVNETA_RXQ_DISABLE_SHIFT 8
158 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
159 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
160 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
161 #define MVNETA_GMAC_CTRL_0 0x2c00
162 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
163 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
164 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
165 #define MVNETA_GMAC_CTRL_2 0x2c08
166 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
167 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
168 #define MVNETA_GMAC2_PORT_RESET BIT(6)
169 #define MVNETA_GMAC_STATUS 0x2c10
170 #define MVNETA_GMAC_LINK_UP BIT(0)
171 #define MVNETA_GMAC_SPEED_1000 BIT(1)
172 #define MVNETA_GMAC_SPEED_100 BIT(2)
173 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
174 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
175 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
176 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
177 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
178 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
179 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
180 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
181 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
182 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
183 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
184 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
185 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
186 #define MVNETA_MIB_COUNTERS_BASE 0x3080
187 #define MVNETA_MIB_LATE_COLLISION 0x7c
188 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
189 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
190 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
191 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
192 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
193 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
194 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
195 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
196 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
197 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
198 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
199 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
200 #define MVNETA_PORT_TX_RESET 0x3cf0
201 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
202 #define MVNETA_TX_MTU 0x3e0c
203 #define MVNETA_TX_TOKEN_SIZE 0x3e14
204 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
205 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
206 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
208 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
210 /* Descriptor ring Macros */
211 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
212 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
214 /* Various constants */
217 #define MVNETA_TXDONE_COAL_PKTS 16
218 #define MVNETA_RX_COAL_PKTS 32
219 #define MVNETA_RX_COAL_USEC 100
221 /* Napi polling weight */
222 #define MVNETA_RX_POLL_WEIGHT 64
224 /* The two bytes Marvell header. Either contains a special value used
225 * by Marvell switches when a specific hardware mode is enabled (not
226 * supported by this driver) or is filled automatically by zeroes on
227 * the RX side. Those two bytes being at the front of the Ethernet
228 * header, they allow to have the IP header aligned on a 4 bytes
229 * boundary automatically: the hardware skips those two bytes on its
232 #define MVNETA_MH_SIZE 2
234 #define MVNETA_VLAN_TAG_LEN 4
236 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
237 #define MVNETA_TX_CSUM_MAX_SIZE 9800
238 #define MVNETA_ACC_MODE_EXT 1
240 /* Timeout constants */
241 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
242 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
243 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
245 #define MVNETA_TX_MTU_MAX 0x3ffff
247 /* Max number of Rx descriptors */
248 #define MVNETA_MAX_RXD 128
250 /* Max number of Tx descriptors */
251 #define MVNETA_MAX_TXD 532
253 /* descriptor aligned size */
254 #define MVNETA_DESC_ALIGNED_SIZE 32
256 #define MVNETA_RX_PKT_SIZE(mtu) \
257 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
258 ETH_HLEN + ETH_FCS_LEN, \
259 MVNETA_CPU_D_CACHE_LINE_SIZE)
261 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
263 struct mvneta_pcpu_stats {
264 struct u64_stats_sync syncp;
273 unsigned int frag_size;
275 struct mvneta_rx_queue *rxqs;
276 struct mvneta_tx_queue *txqs;
277 struct net_device *dev;
280 struct napi_struct napi;
290 struct mvneta_pcpu_stats *stats;
292 struct mii_bus *mii_bus;
293 struct phy_device *phy_dev;
294 phy_interface_t phy_interface;
295 struct device_node *phy_node;
301 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
302 * layout of the transmit and reception DMA descriptors, and their
303 * layout is therefore defined by the hardware design
306 #define MVNETA_TX_L3_OFF_SHIFT 0
307 #define MVNETA_TX_IP_HLEN_SHIFT 8
308 #define MVNETA_TX_L4_UDP BIT(16)
309 #define MVNETA_TX_L3_IP6 BIT(17)
310 #define MVNETA_TXD_IP_CSUM BIT(18)
311 #define MVNETA_TXD_Z_PAD BIT(19)
312 #define MVNETA_TXD_L_DESC BIT(20)
313 #define MVNETA_TXD_F_DESC BIT(21)
314 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
315 MVNETA_TXD_L_DESC | \
317 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
318 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
320 #define MVNETA_RXD_ERR_CRC 0x0
321 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
322 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
323 #define MVNETA_RXD_ERR_LEN BIT(18)
324 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
325 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
326 #define MVNETA_RXD_L3_IP4 BIT(25)
327 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
328 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
330 #if defined(__LITTLE_ENDIAN)
331 struct mvneta_tx_desc {
332 u32 command; /* Options used by HW for packet transmitting.*/
333 u16 reserverd1; /* csum_l4 (for future use) */
334 u16 data_size; /* Data size of transmitted packet in bytes */
335 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
336 u32 reserved2; /* hw_cmd - (for future use, PMT) */
337 u32 reserved3[4]; /* Reserved - (for future use) */
340 struct mvneta_rx_desc {
341 u32 status; /* Info about received packet */
342 u16 reserved1; /* pnc_info - (for future use, PnC) */
343 u16 data_size; /* Size of received packet in bytes */
345 u32 buf_phys_addr; /* Physical address of the buffer */
346 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
348 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
349 u16 reserved3; /* prefetch_cmd, for future use */
350 u16 reserved4; /* csum_l4 - (for future use, PnC) */
352 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
353 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
356 struct mvneta_tx_desc {
357 u16 data_size; /* Data size of transmitted packet in bytes */
358 u16 reserverd1; /* csum_l4 (for future use) */
359 u32 command; /* Options used by HW for packet transmitting.*/
360 u32 reserved2; /* hw_cmd - (for future use, PMT) */
361 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
362 u32 reserved3[4]; /* Reserved - (for future use) */
365 struct mvneta_rx_desc {
366 u16 data_size; /* Size of received packet in bytes */
367 u16 reserved1; /* pnc_info - (for future use, PnC) */
368 u32 status; /* Info about received packet */
370 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
371 u32 buf_phys_addr; /* Physical address of the buffer */
373 u16 reserved4; /* csum_l4 - (for future use, PnC) */
374 u16 reserved3; /* prefetch_cmd, for future use */
375 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
377 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
378 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
382 struct mvneta_tx_queue {
383 /* Number of this TX queue, in the range 0-7 */
386 /* Number of TX DMA descriptors in the descriptor ring */
389 /* Number of currently used TX DMA descriptor in the
394 /* Array of transmitted skb */
395 struct sk_buff **tx_skb;
397 /* Index of last TX DMA descriptor that was inserted */
400 /* Index of the TX DMA descriptor to be cleaned up */
405 /* Virtual address of the TX DMA descriptors array */
406 struct mvneta_tx_desc *descs;
408 /* DMA address of the TX DMA descriptors array */
409 dma_addr_t descs_phys;
411 /* Index of the last TX DMA descriptor */
414 /* Index of the next TX DMA descriptor to process */
415 int next_desc_to_proc;
418 struct mvneta_rx_queue {
419 /* rx queue number, in the range 0-7 */
422 /* num of rx descriptors in the rx descriptor ring */
425 /* counter of times when mvneta_refill() failed */
431 /* Virtual address of the RX DMA descriptors array */
432 struct mvneta_rx_desc *descs;
434 /* DMA address of the RX DMA descriptors array */
435 dma_addr_t descs_phys;
437 /* Index of the last RX DMA descriptor */
440 /* Index of the next RX DMA descriptor to process */
441 int next_desc_to_proc;
444 static int rxq_number = 8;
445 static int txq_number = 8;
449 static int rx_copybreak __read_mostly = 256;
451 #define MVNETA_DRIVER_NAME "mvneta"
452 #define MVNETA_DRIVER_VERSION "1.0"
454 /* Utility/helper methods */
456 /* Write helper method */
457 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
459 writel(data, pp->base + offset);
462 /* Read helper method */
463 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
465 return readl(pp->base + offset);
468 /* Increment txq get counter */
469 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
471 txq->txq_get_index++;
472 if (txq->txq_get_index == txq->size)
473 txq->txq_get_index = 0;
476 /* Increment txq put counter */
477 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
479 txq->txq_put_index++;
480 if (txq->txq_put_index == txq->size)
481 txq->txq_put_index = 0;
485 /* Clear all MIB counters */
486 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
491 /* Perform dummy reads from MIB counters */
492 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
493 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
496 /* Get System Network Statistics */
497 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
498 struct rtnl_link_stats64 *stats)
500 struct mvneta_port *pp = netdev_priv(dev);
504 for_each_possible_cpu(cpu) {
505 struct mvneta_pcpu_stats *cpu_stats;
511 cpu_stats = per_cpu_ptr(pp->stats, cpu);
513 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
514 rx_packets = cpu_stats->rx_packets;
515 rx_bytes = cpu_stats->rx_bytes;
516 tx_packets = cpu_stats->tx_packets;
517 tx_bytes = cpu_stats->tx_bytes;
518 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
520 stats->rx_packets += rx_packets;
521 stats->rx_bytes += rx_bytes;
522 stats->tx_packets += tx_packets;
523 stats->tx_bytes += tx_bytes;
526 stats->rx_errors = dev->stats.rx_errors;
527 stats->rx_dropped = dev->stats.rx_dropped;
529 stats->tx_dropped = dev->stats.tx_dropped;
534 /* Rx descriptors helper methods */
536 /* Checks whether the RX descriptor having this status is both the first
537 * and the last descriptor for the RX packet. Each RX packet is currently
538 * received through a single RX descriptor, so not having each RX
539 * descriptor with its first and last bits set is an error
541 static int mvneta_rxq_desc_is_first_last(u32 status)
543 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
544 MVNETA_RXD_FIRST_LAST_DESC;
547 /* Add number of descriptors ready to receive new packets */
548 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
549 struct mvneta_rx_queue *rxq,
552 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
555 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
556 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
557 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
558 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
559 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
562 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
563 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
566 /* Get number of RX descriptors occupied by received packets */
567 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
568 struct mvneta_rx_queue *rxq)
572 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
573 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
576 /* Update num of rx desc called upon return from rx path or
577 * from mvneta_rxq_drop_pkts().
579 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
580 struct mvneta_rx_queue *rxq,
581 int rx_done, int rx_filled)
585 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
587 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
588 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
592 /* Only 255 descriptors can be added at once */
593 while ((rx_done > 0) || (rx_filled > 0)) {
594 if (rx_done <= 0xff) {
601 if (rx_filled <= 0xff) {
602 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
605 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
608 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
612 /* Get pointer to next RX descriptor to be processed by SW */
613 static struct mvneta_rx_desc *
614 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
616 int rx_desc = rxq->next_desc_to_proc;
618 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
619 prefetch(rxq->descs + rxq->next_desc_to_proc);
620 return rxq->descs + rx_desc;
623 /* Change maximum receive size of the port. */
624 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
628 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
629 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
630 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
631 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
632 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
636 /* Set rx queue offset */
637 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
638 struct mvneta_rx_queue *rxq,
643 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
644 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
647 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
648 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
652 /* Tx descriptors helper methods */
654 /* Update HW with number of TX descriptors to be sent */
655 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
656 struct mvneta_tx_queue *txq,
661 /* Only 255 descriptors can be added at once ; Assume caller
662 * process TX desriptors in quanta less than 256
665 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
668 /* Get pointer to next TX descriptor to be processed (send) by HW */
669 static struct mvneta_tx_desc *
670 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
672 int tx_desc = txq->next_desc_to_proc;
674 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
675 return txq->descs + tx_desc;
678 /* Release the last allocated TX descriptor. Useful to handle DMA
679 * mapping failures in the TX path.
681 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
683 if (txq->next_desc_to_proc == 0)
684 txq->next_desc_to_proc = txq->last_desc - 1;
686 txq->next_desc_to_proc--;
689 /* Set rxq buf size */
690 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
691 struct mvneta_rx_queue *rxq,
696 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
698 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
699 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
701 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
704 /* Disable buffer management (BM) */
705 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
706 struct mvneta_rx_queue *rxq)
710 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
711 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
712 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
715 /* Start the Ethernet port RX and TX activity */
716 static void mvneta_port_up(struct mvneta_port *pp)
721 /* Enable all initialized TXs. */
722 mvneta_mib_counters_clear(pp);
724 for (queue = 0; queue < txq_number; queue++) {
725 struct mvneta_tx_queue *txq = &pp->txqs[queue];
726 if (txq->descs != NULL)
727 q_map |= (1 << queue);
729 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
731 /* Enable all initialized RXQs. */
733 for (queue = 0; queue < rxq_number; queue++) {
734 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
735 if (rxq->descs != NULL)
736 q_map |= (1 << queue);
739 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
742 /* Stop the Ethernet port activity */
743 static void mvneta_port_down(struct mvneta_port *pp)
748 /* Stop Rx port activity. Check port Rx activity. */
749 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
751 /* Issue stop command for active channels only */
753 mvreg_write(pp, MVNETA_RXQ_CMD,
754 val << MVNETA_RXQ_DISABLE_SHIFT);
756 /* Wait for all Rx activity to terminate. */
759 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
761 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
767 val = mvreg_read(pp, MVNETA_RXQ_CMD);
768 } while (val & 0xff);
770 /* Stop Tx port activity. Check port Tx activity. Issue stop
771 * command for active channels only
773 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
776 mvreg_write(pp, MVNETA_TXQ_CMD,
777 (val << MVNETA_TXQ_DISABLE_SHIFT));
779 /* Wait for all Tx activity to terminate. */
782 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
784 "TIMEOUT for TX stopped status=0x%08x\n",
790 /* Check TX Command reg that all Txqs are stopped */
791 val = mvreg_read(pp, MVNETA_TXQ_CMD);
793 } while (val & 0xff);
795 /* Double check to verify that TX FIFO is empty */
798 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
800 "TX FIFO empty timeout status=0x08%x\n",
806 val = mvreg_read(pp, MVNETA_PORT_STATUS);
807 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
808 (val & MVNETA_TX_IN_PRGRS));
813 /* Enable the port by setting the port enable bit of the MAC control register */
814 static void mvneta_port_enable(struct mvneta_port *pp)
819 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
820 val |= MVNETA_GMAC0_PORT_ENABLE;
821 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
824 /* Disable the port and wait for about 200 usec before retuning */
825 static void mvneta_port_disable(struct mvneta_port *pp)
829 /* Reset the Enable bit in the Serial Control Register */
830 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
831 val &= ~MVNETA_GMAC0_PORT_ENABLE;
832 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
837 /* Multicast tables methods */
839 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
840 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
848 val = 0x1 | (queue << 1);
849 val |= (val << 24) | (val << 16) | (val << 8);
852 for (offset = 0; offset <= 0xc; offset += 4)
853 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
856 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
857 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
865 val = 0x1 | (queue << 1);
866 val |= (val << 24) | (val << 16) | (val << 8);
869 for (offset = 0; offset <= 0xfc; offset += 4)
870 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
874 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
875 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
881 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
884 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
885 val = 0x1 | (queue << 1);
886 val |= (val << 24) | (val << 16) | (val << 8);
889 for (offset = 0; offset <= 0xfc; offset += 4)
890 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
893 /* This method sets defaults to the NETA port:
894 * Clears interrupt Cause and Mask registers.
895 * Clears all MAC tables.
896 * Sets defaults to all registers.
897 * Resets RX and TX descriptor rings.
899 * This method can be called after mvneta_port_down() to return the port
900 * settings to defaults.
902 static void mvneta_defaults_set(struct mvneta_port *pp)
908 /* Clear all Cause registers */
909 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
910 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
911 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
913 /* Mask all interrupts */
914 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
915 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
916 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
917 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
919 /* Enable MBUS Retry bit16 */
920 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
922 /* Set CPU queue access map - all CPUs have access to all RX
923 * queues and to all TX queues
925 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
926 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
927 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
928 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
930 /* Reset RX and TX DMAs */
931 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
932 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
934 /* Disable Legacy WRR, Disable EJP, Release from reset */
935 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
936 for (queue = 0; queue < txq_number; queue++) {
937 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
938 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
941 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
942 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
944 /* Set Port Acceleration Mode */
945 val = MVNETA_ACC_MODE_EXT;
946 mvreg_write(pp, MVNETA_ACC_MODE, val);
948 /* Update val of portCfg register accordingly with all RxQueue types */
949 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
950 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
953 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
954 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
956 /* Build PORT_SDMA_CONFIG_REG */
959 /* Default burst size */
960 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
961 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
962 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
964 #if defined(__BIG_ENDIAN)
965 val |= MVNETA_DESC_SWAP;
968 /* Assign port SDMA configuration */
969 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
971 /* Disable PHY polling in hardware, since we're using the
972 * kernel phylib to do this.
974 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
975 val &= ~MVNETA_PHY_POLLING_ENABLE;
976 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
978 mvneta_set_ucast_table(pp, -1);
979 mvneta_set_special_mcast_table(pp, -1);
980 mvneta_set_other_mcast_table(pp, -1);
982 /* Set port interrupt enable register - default enable all */
983 mvreg_write(pp, MVNETA_INTR_ENABLE,
984 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
985 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
988 /* Set max sizes for tx queues */
989 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
995 mtu = max_tx_size * 8;
996 if (mtu > MVNETA_TX_MTU_MAX)
997 mtu = MVNETA_TX_MTU_MAX;
1000 val = mvreg_read(pp, MVNETA_TX_MTU);
1001 val &= ~MVNETA_TX_MTU_MAX;
1003 mvreg_write(pp, MVNETA_TX_MTU, val);
1005 /* TX token size and all TXQs token size must be larger that MTU */
1006 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1008 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1011 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1013 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1015 for (queue = 0; queue < txq_number; queue++) {
1016 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1018 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1021 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1023 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1028 /* Set unicast address */
1029 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1032 unsigned int unicast_reg;
1033 unsigned int tbl_offset;
1034 unsigned int reg_offset;
1036 /* Locate the Unicast table entry */
1037 last_nibble = (0xf & last_nibble);
1039 /* offset from unicast tbl base */
1040 tbl_offset = (last_nibble / 4) * 4;
1042 /* offset within the above reg */
1043 reg_offset = last_nibble % 4;
1045 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1048 /* Clear accepts frame bit at specified unicast DA tbl entry */
1049 unicast_reg &= ~(0xff << (8 * reg_offset));
1051 unicast_reg &= ~(0xff << (8 * reg_offset));
1052 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1055 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1058 /* Set mac address */
1059 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1066 mac_l = (addr[4] << 8) | (addr[5]);
1067 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1068 (addr[2] << 8) | (addr[3] << 0);
1070 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1071 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1074 /* Accept frames of this address */
1075 mvneta_set_ucast_addr(pp, addr[5], queue);
1078 /* Set the number of packets that will be received before RX interrupt
1079 * will be generated by HW.
1081 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1082 struct mvneta_rx_queue *rxq, u32 value)
1084 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1085 value | MVNETA_RXQ_NON_OCCUPIED(0));
1086 rxq->pkts_coal = value;
1089 /* Set the time delay in usec before RX interrupt will be generated by
1092 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1093 struct mvneta_rx_queue *rxq, u32 value)
1096 unsigned long clk_rate;
1098 clk_rate = clk_get_rate(pp->clk);
1099 val = (clk_rate / 1000000) * value;
1101 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1102 rxq->time_coal = value;
1105 /* Set threshold for TX_DONE pkts coalescing */
1106 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1107 struct mvneta_tx_queue *txq, u32 value)
1111 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1113 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1114 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1116 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1118 txq->done_pkts_coal = value;
1121 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1122 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1123 u32 phys_addr, u32 cookie)
1125 rx_desc->buf_cookie = cookie;
1126 rx_desc->buf_phys_addr = phys_addr;
1129 /* Decrement sent descriptors counter */
1130 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1131 struct mvneta_tx_queue *txq,
1136 /* Only 255 TX descriptors can be updated at once */
1137 while (sent_desc > 0xff) {
1138 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1139 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1140 sent_desc = sent_desc - 0xff;
1143 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1144 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1147 /* Get number of TX descriptors already sent by HW */
1148 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1149 struct mvneta_tx_queue *txq)
1154 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1155 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1156 MVNETA_TXQ_SENT_DESC_SHIFT;
1161 /* Get number of sent descriptors and decrement counter.
1162 * The number of sent descriptors is returned.
1164 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1165 struct mvneta_tx_queue *txq)
1169 /* Get number of sent descriptors */
1170 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1172 /* Decrement sent descriptors counter */
1174 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1179 /* Set TXQ descriptors fields relevant for CSUM calculation */
1180 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1181 int ip_hdr_len, int l4_proto)
1185 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1186 * G_L4_chk, L4_type; required only for checksum
1189 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1190 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1192 if (l3_proto == swab16(ETH_P_IP))
1193 command |= MVNETA_TXD_IP_CSUM;
1195 command |= MVNETA_TX_L3_IP6;
1197 if (l4_proto == IPPROTO_TCP)
1198 command |= MVNETA_TX_L4_CSUM_FULL;
1199 else if (l4_proto == IPPROTO_UDP)
1200 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1202 command |= MVNETA_TX_L4_CSUM_NOT;
1208 /* Display more error info */
1209 static void mvneta_rx_error(struct mvneta_port *pp,
1210 struct mvneta_rx_desc *rx_desc)
1212 u32 status = rx_desc->status;
1214 if (!mvneta_rxq_desc_is_first_last(status)) {
1216 "bad rx status %08x (buffer oversize), size=%d\n",
1217 status, rx_desc->data_size);
1221 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1222 case MVNETA_RXD_ERR_CRC:
1223 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1224 status, rx_desc->data_size);
1226 case MVNETA_RXD_ERR_OVERRUN:
1227 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1228 status, rx_desc->data_size);
1230 case MVNETA_RXD_ERR_LEN:
1231 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1232 status, rx_desc->data_size);
1234 case MVNETA_RXD_ERR_RESOURCE:
1235 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1236 status, rx_desc->data_size);
1241 /* Handle RX checksum offload based on the descriptor's status */
1242 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1243 struct sk_buff *skb)
1245 if ((status & MVNETA_RXD_L3_IP4) &&
1246 (status & MVNETA_RXD_L4_CSUM_OK)) {
1248 skb->ip_summed = CHECKSUM_UNNECESSARY;
1252 skb->ip_summed = CHECKSUM_NONE;
1255 /* Return tx queue pointer (find last set bit) according to <cause> returned
1256 * form tx_done reg. <cause> must not be null. The return value is always a
1257 * valid queue for matching the first one found in <cause>.
1259 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1262 int queue = fls(cause) - 1;
1264 return &pp->txqs[queue];
1267 /* Free tx queue skbuffs */
1268 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1269 struct mvneta_tx_queue *txq, int num)
1273 for (i = 0; i < num; i++) {
1274 struct mvneta_tx_desc *tx_desc = txq->descs +
1276 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1278 mvneta_txq_inc_get(txq);
1283 dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr,
1284 tx_desc->data_size, DMA_TO_DEVICE);
1285 dev_kfree_skb_any(skb);
1289 /* Handle end of transmission */
1290 static void mvneta_txq_done(struct mvneta_port *pp,
1291 struct mvneta_tx_queue *txq)
1293 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1296 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1300 mvneta_txq_bufs_free(pp, txq, tx_done);
1302 txq->count -= tx_done;
1304 if (netif_tx_queue_stopped(nq)) {
1305 if (txq->size - txq->count >= MAX_SKB_FRAGS + 1)
1306 netif_tx_wake_queue(nq);
1310 static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1312 if (likely(pp->frag_size <= PAGE_SIZE))
1313 return netdev_alloc_frag(pp->frag_size);
1315 return kmalloc(pp->frag_size, GFP_ATOMIC);
1318 static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1320 if (likely(pp->frag_size <= PAGE_SIZE))
1321 put_page(virt_to_head_page(data));
1326 /* Refill processing */
1327 static int mvneta_rx_refill(struct mvneta_port *pp,
1328 struct mvneta_rx_desc *rx_desc)
1331 dma_addr_t phys_addr;
1334 data = mvneta_frag_alloc(pp);
1338 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1339 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1341 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1342 mvneta_frag_free(pp, data);
1346 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1350 /* Handle tx checksum */
1351 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1353 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1357 if (skb->protocol == htons(ETH_P_IP)) {
1358 struct iphdr *ip4h = ip_hdr(skb);
1360 /* Calculate IPv4 checksum and L4 checksum */
1361 ip_hdr_len = ip4h->ihl;
1362 l4_proto = ip4h->protocol;
1363 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1364 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1366 /* Read l4_protocol from one of IPv6 extra headers */
1367 if (skb_network_header_len(skb) > 0)
1368 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1369 l4_proto = ip6h->nexthdr;
1371 return MVNETA_TX_L4_CSUM_NOT;
1373 return mvneta_txq_desc_csum(skb_network_offset(skb),
1374 skb->protocol, ip_hdr_len, l4_proto);
1377 return MVNETA_TX_L4_CSUM_NOT;
1380 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1383 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1386 int queue = fls(cause >> 8) - 1;
1388 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1391 /* Drop packets received by the RXQ and free buffers */
1392 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1393 struct mvneta_rx_queue *rxq)
1397 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1398 for (i = 0; i < rxq->size; i++) {
1399 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1400 void *data = (void *)rx_desc->buf_cookie;
1402 mvneta_frag_free(pp, data);
1403 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1404 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1408 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1411 /* Main rx processing */
1412 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1413 struct mvneta_rx_queue *rxq)
1415 struct net_device *dev = pp->dev;
1416 int rx_done, rx_filled;
1420 /* Get number of received packets */
1421 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1423 if (rx_todo > rx_done)
1429 /* Fairness NAPI loop */
1430 while (rx_done < rx_todo) {
1431 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1432 struct sk_buff *skb;
1433 unsigned char *data;
1439 rx_status = rx_desc->status;
1440 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1441 data = (unsigned char *)rx_desc->buf_cookie;
1443 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1444 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1446 dev->stats.rx_errors++;
1447 mvneta_rx_error(pp, rx_desc);
1448 /* leave the descriptor untouched */
1452 if (rx_bytes <= rx_copybreak) {
1453 /* better copy a small frame and not unmap the DMA region */
1454 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1456 goto err_drop_frame;
1458 dma_sync_single_range_for_cpu(dev->dev.parent,
1459 rx_desc->buf_phys_addr,
1460 MVNETA_MH_SIZE + NET_SKB_PAD,
1463 memcpy(skb_put(skb, rx_bytes),
1464 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1467 skb->protocol = eth_type_trans(skb, dev);
1468 mvneta_rx_csum(pp, rx_status, skb);
1469 napi_gro_receive(&pp->napi, skb);
1472 rcvd_bytes += rx_bytes;
1474 /* leave the descriptor and buffer untouched */
1478 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
1480 goto err_drop_frame;
1482 dma_unmap_single(dev->dev.parent, rx_desc->buf_phys_addr,
1483 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1486 rcvd_bytes += rx_bytes;
1488 /* Linux processing */
1489 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1490 skb_put(skb, rx_bytes);
1492 skb->protocol = eth_type_trans(skb, dev);
1494 mvneta_rx_csum(pp, rx_status, skb);
1496 napi_gro_receive(&pp->napi, skb);
1498 /* Refill processing */
1499 err = mvneta_rx_refill(pp, rx_desc);
1501 netdev_err(dev, "Linux processing - Can't refill\n");
1508 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1510 u64_stats_update_begin(&stats->syncp);
1511 stats->rx_packets += rcvd_pkts;
1512 stats->rx_bytes += rcvd_bytes;
1513 u64_stats_update_end(&stats->syncp);
1516 /* Update rxq management counters */
1517 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1522 /* Handle tx fragmentation processing */
1523 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1524 struct mvneta_tx_queue *txq)
1526 struct mvneta_tx_desc *tx_desc;
1529 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1530 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1531 void *addr = page_address(frag->page.p) + frag->page_offset;
1533 tx_desc = mvneta_txq_next_desc_get(txq);
1534 tx_desc->data_size = frag->size;
1536 tx_desc->buf_phys_addr =
1537 dma_map_single(pp->dev->dev.parent, addr,
1538 tx_desc->data_size, DMA_TO_DEVICE);
1540 if (dma_mapping_error(pp->dev->dev.parent,
1541 tx_desc->buf_phys_addr)) {
1542 mvneta_txq_desc_put(txq);
1546 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
1547 /* Last descriptor */
1548 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1550 txq->tx_skb[txq->txq_put_index] = skb;
1552 mvneta_txq_inc_put(txq);
1554 /* Descriptor in the middle: Not First, Not Last */
1555 tx_desc->command = 0;
1557 txq->tx_skb[txq->txq_put_index] = NULL;
1558 mvneta_txq_inc_put(txq);
1565 /* Release all descriptors that were used to map fragments of
1566 * this packet, as well as the corresponding DMA mappings
1568 for (i = i - 1; i >= 0; i--) {
1569 tx_desc = txq->descs + i;
1570 dma_unmap_single(pp->dev->dev.parent,
1571 tx_desc->buf_phys_addr,
1574 mvneta_txq_desc_put(txq);
1580 /* Main tx processing */
1581 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1583 struct mvneta_port *pp = netdev_priv(dev);
1584 u16 txq_id = skb_get_queue_mapping(skb);
1585 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1586 struct mvneta_tx_desc *tx_desc;
1587 struct netdev_queue *nq;
1591 if (!netif_running(dev))
1594 frags = skb_shinfo(skb)->nr_frags + 1;
1595 nq = netdev_get_tx_queue(dev, txq_id);
1597 /* Get a descriptor for the first part of the packet */
1598 tx_desc = mvneta_txq_next_desc_get(txq);
1600 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1602 tx_desc->data_size = skb_headlen(skb);
1604 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1607 if (unlikely(dma_mapping_error(dev->dev.parent,
1608 tx_desc->buf_phys_addr))) {
1609 mvneta_txq_desc_put(txq);
1615 /* First and Last descriptor */
1616 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1617 tx_desc->command = tx_cmd;
1618 txq->tx_skb[txq->txq_put_index] = skb;
1619 mvneta_txq_inc_put(txq);
1621 /* First but not Last */
1622 tx_cmd |= MVNETA_TXD_F_DESC;
1623 txq->tx_skb[txq->txq_put_index] = NULL;
1624 mvneta_txq_inc_put(txq);
1625 tx_desc->command = tx_cmd;
1626 /* Continue with other skb fragments */
1627 if (mvneta_tx_frag_process(pp, skb, txq)) {
1628 dma_unmap_single(dev->dev.parent,
1629 tx_desc->buf_phys_addr,
1632 mvneta_txq_desc_put(txq);
1638 txq->count += frags;
1639 mvneta_txq_pend_desc_add(pp, txq, frags);
1641 if (txq->size - txq->count < MAX_SKB_FRAGS + 1)
1642 netif_tx_stop_queue(nq);
1646 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1648 u64_stats_update_begin(&stats->syncp);
1649 stats->tx_packets++;
1650 stats->tx_bytes += skb->len;
1651 u64_stats_update_end(&stats->syncp);
1653 dev->stats.tx_dropped++;
1654 dev_kfree_skb_any(skb);
1657 return NETDEV_TX_OK;
1661 /* Free tx resources, when resetting a port */
1662 static void mvneta_txq_done_force(struct mvneta_port *pp,
1663 struct mvneta_tx_queue *txq)
1666 int tx_done = txq->count;
1668 mvneta_txq_bufs_free(pp, txq, tx_done);
1672 txq->txq_put_index = 0;
1673 txq->txq_get_index = 0;
1676 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
1677 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1679 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
1681 struct mvneta_tx_queue *txq;
1682 struct netdev_queue *nq;
1684 while (cause_tx_done) {
1685 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1687 nq = netdev_get_tx_queue(pp->dev, txq->id);
1688 __netif_tx_lock(nq, smp_processor_id());
1691 mvneta_txq_done(pp, txq);
1693 __netif_tx_unlock(nq);
1694 cause_tx_done &= ~((1 << txq->id));
1698 /* Compute crc8 of the specified address, using a unique algorithm ,
1699 * according to hw spec, different than generic crc8 algorithm
1701 static int mvneta_addr_crc(unsigned char *addr)
1706 for (i = 0; i < ETH_ALEN; i++) {
1709 crc = (crc ^ addr[i]) << 8;
1710 for (j = 7; j >= 0; j--) {
1711 if (crc & (0x100 << j))
1719 /* This method controls the net device special MAC multicast support.
1720 * The Special Multicast Table for MAC addresses supports MAC of the form
1721 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1722 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1723 * Table entries in the DA-Filter table. This method set the Special
1724 * Multicast Table appropriate entry.
1726 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1727 unsigned char last_byte,
1730 unsigned int smc_table_reg;
1731 unsigned int tbl_offset;
1732 unsigned int reg_offset;
1734 /* Register offset from SMC table base */
1735 tbl_offset = (last_byte / 4);
1736 /* Entry offset within the above reg */
1737 reg_offset = last_byte % 4;
1739 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1743 smc_table_reg &= ~(0xff << (8 * reg_offset));
1745 smc_table_reg &= ~(0xff << (8 * reg_offset));
1746 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1749 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1753 /* This method controls the network device Other MAC multicast support.
1754 * The Other Multicast Table is used for multicast of another type.
1755 * A CRC-8 is used as an index to the Other Multicast Table entries
1756 * in the DA-Filter table.
1757 * The method gets the CRC-8 value from the calling routine and
1758 * sets the Other Multicast Table appropriate entry according to the
1761 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1765 unsigned int omc_table_reg;
1766 unsigned int tbl_offset;
1767 unsigned int reg_offset;
1769 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1770 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1772 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1775 /* Clear accepts frame bit at specified Other DA table entry */
1776 omc_table_reg &= ~(0xff << (8 * reg_offset));
1778 omc_table_reg &= ~(0xff << (8 * reg_offset));
1779 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1782 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1785 /* The network device supports multicast using two tables:
1786 * 1) Special Multicast Table for MAC addresses of the form
1787 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1788 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1789 * Table entries in the DA-Filter table.
1790 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1791 * is used as an index to the Other Multicast Table entries in the
1794 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1797 unsigned char crc_result = 0;
1799 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1800 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1804 crc_result = mvneta_addr_crc(p_addr);
1806 if (pp->mcast_count[crc_result] == 0) {
1807 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1812 pp->mcast_count[crc_result]--;
1813 if (pp->mcast_count[crc_result] != 0) {
1814 netdev_info(pp->dev,
1815 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1816 pp->mcast_count[crc_result], crc_result);
1820 pp->mcast_count[crc_result]++;
1822 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1827 /* Configure Fitering mode of Ethernet port */
1828 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1831 u32 port_cfg_reg, val;
1833 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1835 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
1837 /* Set / Clear UPM bit in port configuration register */
1839 /* Accept all Unicast addresses */
1840 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
1841 val |= MVNETA_FORCE_UNI;
1842 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
1843 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
1845 /* Reject all Unicast addresses */
1846 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
1847 val &= ~MVNETA_FORCE_UNI;
1850 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
1851 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
1854 /* register unicast and multicast addresses */
1855 static void mvneta_set_rx_mode(struct net_device *dev)
1857 struct mvneta_port *pp = netdev_priv(dev);
1858 struct netdev_hw_addr *ha;
1860 if (dev->flags & IFF_PROMISC) {
1861 /* Accept all: Multicast + Unicast */
1862 mvneta_rx_unicast_promisc_set(pp, 1);
1863 mvneta_set_ucast_table(pp, rxq_def);
1864 mvneta_set_special_mcast_table(pp, rxq_def);
1865 mvneta_set_other_mcast_table(pp, rxq_def);
1867 /* Accept single Unicast */
1868 mvneta_rx_unicast_promisc_set(pp, 0);
1869 mvneta_set_ucast_table(pp, -1);
1870 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
1872 if (dev->flags & IFF_ALLMULTI) {
1873 /* Accept all multicast */
1874 mvneta_set_special_mcast_table(pp, rxq_def);
1875 mvneta_set_other_mcast_table(pp, rxq_def);
1877 /* Accept only initialized multicast */
1878 mvneta_set_special_mcast_table(pp, -1);
1879 mvneta_set_other_mcast_table(pp, -1);
1881 if (!netdev_mc_empty(dev)) {
1882 netdev_for_each_mc_addr(ha, dev) {
1883 mvneta_mcast_addr_set(pp, ha->addr,
1891 /* Interrupt handling - the callback for request_irq() */
1892 static irqreturn_t mvneta_isr(int irq, void *dev_id)
1894 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
1896 /* Mask all interrupts */
1897 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1899 napi_schedule(&pp->napi);
1905 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
1906 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
1907 * Bits 8 -15 of the cause Rx Tx register indicate that are received
1908 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
1909 * Each CPU has its own causeRxTx register
1911 static int mvneta_poll(struct napi_struct *napi, int budget)
1915 unsigned long flags;
1916 struct mvneta_port *pp = netdev_priv(napi->dev);
1918 if (!netif_running(pp->dev)) {
1919 napi_complete(napi);
1923 /* Read cause register */
1924 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
1925 (MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
1927 /* Release Tx descriptors */
1928 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
1929 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
1930 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
1933 /* For the case where the last mvneta_poll did not process all
1936 cause_rx_tx |= pp->cause_rx_tx;
1937 if (rxq_number > 1) {
1938 while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) {
1940 struct mvneta_rx_queue *rxq;
1941 /* get rx queue number from cause_rx_tx */
1942 rxq = mvneta_rx_policy(pp, cause_rx_tx);
1946 /* process the packet in that rx queue */
1947 count = mvneta_rx(pp, budget, rxq);
1951 /* set off the rx bit of the
1952 * corresponding bit in the cause rx
1953 * tx register, so that next iteration
1954 * will find the next rx queue where
1955 * packets are received on
1957 cause_rx_tx &= ~((1 << rxq->id) << 8);
1961 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
1967 napi_complete(napi);
1968 local_irq_save(flags);
1969 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1970 MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
1971 local_irq_restore(flags);
1974 pp->cause_rx_tx = cause_rx_tx;
1978 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1979 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1984 for (i = 0; i < num; i++) {
1985 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
1986 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
1987 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
1988 __func__, rxq->id, i, num);
1993 /* Add this number of RX descriptors as non occupied (ready to
1996 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2001 /* Free all packets pending transmit from all TXQs and reset TX port */
2002 static void mvneta_tx_reset(struct mvneta_port *pp)
2006 /* free the skb's in the hal tx ring */
2007 for (queue = 0; queue < txq_number; queue++)
2008 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2010 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2011 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2014 static void mvneta_rx_reset(struct mvneta_port *pp)
2016 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2017 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2020 /* Rx/Tx queue initialization/cleanup methods */
2022 /* Create a specified RX queue */
2023 static int mvneta_rxq_init(struct mvneta_port *pp,
2024 struct mvneta_rx_queue *rxq)
2027 rxq->size = pp->rx_ring_size;
2029 /* Allocate memory for RX descriptors */
2030 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2031 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2032 &rxq->descs_phys, GFP_KERNEL);
2033 if (rxq->descs == NULL)
2036 BUG_ON(rxq->descs !=
2037 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2039 rxq->last_desc = rxq->size - 1;
2041 /* Set Rx descriptors queue starting address */
2042 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2043 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2046 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2048 /* Set coalescing pkts and time */
2049 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2050 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2052 /* Fill RXQ with buffers from RX pool */
2053 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2054 mvneta_rxq_bm_disable(pp, rxq);
2055 mvneta_rxq_fill(pp, rxq, rxq->size);
2060 /* Cleanup Rx queue */
2061 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2062 struct mvneta_rx_queue *rxq)
2064 mvneta_rxq_drop_pkts(pp, rxq);
2067 dma_free_coherent(pp->dev->dev.parent,
2068 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2074 rxq->next_desc_to_proc = 0;
2075 rxq->descs_phys = 0;
2078 /* Create and initialize a tx queue */
2079 static int mvneta_txq_init(struct mvneta_port *pp,
2080 struct mvneta_tx_queue *txq)
2082 txq->size = pp->tx_ring_size;
2084 /* Allocate memory for TX descriptors */
2085 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2086 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2087 &txq->descs_phys, GFP_KERNEL);
2088 if (txq->descs == NULL)
2091 /* Make sure descriptor address is cache line size aligned */
2092 BUG_ON(txq->descs !=
2093 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2095 txq->last_desc = txq->size - 1;
2097 /* Set maximum bandwidth for enabled TXQs */
2098 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2099 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2101 /* Set Tx descriptors queue starting address */
2102 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2103 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2105 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2106 if (txq->tx_skb == NULL) {
2107 dma_free_coherent(pp->dev->dev.parent,
2108 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2109 txq->descs, txq->descs_phys);
2112 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2117 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2118 static void mvneta_txq_deinit(struct mvneta_port *pp,
2119 struct mvneta_tx_queue *txq)
2124 dma_free_coherent(pp->dev->dev.parent,
2125 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2126 txq->descs, txq->descs_phys);
2130 txq->next_desc_to_proc = 0;
2131 txq->descs_phys = 0;
2133 /* Set minimum bandwidth for disabled TXQs */
2134 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2135 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2137 /* Set Tx descriptors queue starting address and size */
2138 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2139 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2142 /* Cleanup all Tx queues */
2143 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2147 for (queue = 0; queue < txq_number; queue++)
2148 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2151 /* Cleanup all Rx queues */
2152 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2156 for (queue = 0; queue < rxq_number; queue++)
2157 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2161 /* Init all Rx queues */
2162 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2166 for (queue = 0; queue < rxq_number; queue++) {
2167 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2169 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2171 mvneta_cleanup_rxqs(pp);
2179 /* Init all tx queues */
2180 static int mvneta_setup_txqs(struct mvneta_port *pp)
2184 for (queue = 0; queue < txq_number; queue++) {
2185 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2187 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2189 mvneta_cleanup_txqs(pp);
2197 static void mvneta_start_dev(struct mvneta_port *pp)
2199 mvneta_max_rx_size_set(pp, pp->pkt_size);
2200 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2202 /* start the Rx/Tx activity */
2203 mvneta_port_enable(pp);
2205 /* Enable polling on the port */
2206 napi_enable(&pp->napi);
2208 /* Unmask interrupts */
2209 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2210 MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
2212 phy_start(pp->phy_dev);
2213 netif_tx_start_all_queues(pp->dev);
2216 static void mvneta_stop_dev(struct mvneta_port *pp)
2218 phy_stop(pp->phy_dev);
2220 napi_disable(&pp->napi);
2222 netif_carrier_off(pp->dev);
2224 mvneta_port_down(pp);
2225 netif_tx_stop_all_queues(pp->dev);
2227 /* Stop the port activity */
2228 mvneta_port_disable(pp);
2230 /* Clear all ethernet port interrupts */
2231 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2232 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2234 /* Mask all ethernet port interrupts */
2235 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2236 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2237 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2239 mvneta_tx_reset(pp);
2240 mvneta_rx_reset(pp);
2243 /* Return positive if MTU is valid */
2244 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2247 netdev_err(dev, "cannot change mtu to less than 68\n");
2251 /* 9676 == 9700 - 20 and rounding to 8 */
2253 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2257 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2258 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2259 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2260 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2266 /* Change the device mtu */
2267 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2269 struct mvneta_port *pp = netdev_priv(dev);
2272 mtu = mvneta_check_mtu_valid(dev, mtu);
2278 if (!netif_running(dev))
2281 /* The interface is running, so we have to force a
2282 * reallocation of the RXQs
2284 mvneta_stop_dev(pp);
2286 mvneta_cleanup_txqs(pp);
2287 mvneta_cleanup_rxqs(pp);
2289 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2290 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2291 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2293 ret = mvneta_setup_rxqs(pp);
2295 netdev_err(pp->dev, "unable to setup rxqs after MTU change\n");
2299 mvneta_setup_txqs(pp);
2301 mvneta_start_dev(pp);
2307 /* Get mac address */
2308 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2310 u32 mac_addr_l, mac_addr_h;
2312 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2313 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2314 addr[0] = (mac_addr_h >> 24) & 0xFF;
2315 addr[1] = (mac_addr_h >> 16) & 0xFF;
2316 addr[2] = (mac_addr_h >> 8) & 0xFF;
2317 addr[3] = mac_addr_h & 0xFF;
2318 addr[4] = (mac_addr_l >> 8) & 0xFF;
2319 addr[5] = mac_addr_l & 0xFF;
2322 /* Handle setting mac address */
2323 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2325 struct mvneta_port *pp = netdev_priv(dev);
2329 if (netif_running(dev))
2332 /* Remove previous address table entry */
2333 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2335 /* Set new addr in hw */
2336 mvneta_mac_addr_set(pp, mac, rxq_def);
2338 /* Set addr in the device */
2339 for (i = 0; i < ETH_ALEN; i++)
2340 dev->dev_addr[i] = mac[i];
2345 static void mvneta_adjust_link(struct net_device *ndev)
2347 struct mvneta_port *pp = netdev_priv(ndev);
2348 struct phy_device *phydev = pp->phy_dev;
2349 int status_change = 0;
2352 if ((pp->speed != phydev->speed) ||
2353 (pp->duplex != phydev->duplex)) {
2356 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2357 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2358 MVNETA_GMAC_CONFIG_GMII_SPEED |
2359 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
2360 MVNETA_GMAC_AN_SPEED_EN |
2361 MVNETA_GMAC_AN_DUPLEX_EN);
2364 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2366 if (phydev->speed == SPEED_1000)
2367 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2369 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2371 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2373 pp->duplex = phydev->duplex;
2374 pp->speed = phydev->speed;
2378 if (phydev->link != pp->link) {
2379 if (!phydev->link) {
2384 pp->link = phydev->link;
2388 if (status_change) {
2390 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2391 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
2392 MVNETA_GMAC_FORCE_LINK_DOWN);
2393 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2395 netdev_info(pp->dev, "link up\n");
2397 mvneta_port_down(pp);
2398 netdev_info(pp->dev, "link down\n");
2403 static int mvneta_mdio_probe(struct mvneta_port *pp)
2405 struct phy_device *phy_dev;
2407 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2410 netdev_err(pp->dev, "could not find the PHY\n");
2414 phy_dev->supported &= PHY_GBIT_FEATURES;
2415 phy_dev->advertising = phy_dev->supported;
2417 pp->phy_dev = phy_dev;
2425 static void mvneta_mdio_remove(struct mvneta_port *pp)
2427 phy_disconnect(pp->phy_dev);
2431 static int mvneta_open(struct net_device *dev)
2433 struct mvneta_port *pp = netdev_priv(dev);
2436 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2438 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2439 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2440 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2442 ret = mvneta_setup_rxqs(pp);
2446 ret = mvneta_setup_txqs(pp);
2448 goto err_cleanup_rxqs;
2450 /* Connect to port interrupt line */
2451 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2452 MVNETA_DRIVER_NAME, pp);
2454 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2455 goto err_cleanup_txqs;
2458 /* In default link is down */
2459 netif_carrier_off(pp->dev);
2461 ret = mvneta_mdio_probe(pp);
2463 netdev_err(dev, "cannot probe MDIO bus\n");
2467 mvneta_start_dev(pp);
2472 free_irq(pp->dev->irq, pp);
2474 mvneta_cleanup_txqs(pp);
2476 mvneta_cleanup_rxqs(pp);
2480 /* Stop the port, free port interrupt line */
2481 static int mvneta_stop(struct net_device *dev)
2483 struct mvneta_port *pp = netdev_priv(dev);
2485 mvneta_stop_dev(pp);
2486 mvneta_mdio_remove(pp);
2487 free_irq(dev->irq, pp);
2488 mvneta_cleanup_rxqs(pp);
2489 mvneta_cleanup_txqs(pp);
2494 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2496 struct mvneta_port *pp = netdev_priv(dev);
2502 ret = phy_mii_ioctl(pp->phy_dev, ifr, cmd);
2504 mvneta_adjust_link(dev);
2509 /* Ethtool methods */
2511 /* Get settings (phy address, speed) for ethtools */
2512 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2514 struct mvneta_port *pp = netdev_priv(dev);
2519 return phy_ethtool_gset(pp->phy_dev, cmd);
2522 /* Set settings (phy address, speed) for ethtools */
2523 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2525 struct mvneta_port *pp = netdev_priv(dev);
2530 return phy_ethtool_sset(pp->phy_dev, cmd);
2533 /* Set interrupt coalescing for ethtools */
2534 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2535 struct ethtool_coalesce *c)
2537 struct mvneta_port *pp = netdev_priv(dev);
2540 for (queue = 0; queue < rxq_number; queue++) {
2541 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2542 rxq->time_coal = c->rx_coalesce_usecs;
2543 rxq->pkts_coal = c->rx_max_coalesced_frames;
2544 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2545 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2548 for (queue = 0; queue < txq_number; queue++) {
2549 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2550 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2551 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2557 /* get coalescing for ethtools */
2558 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2559 struct ethtool_coalesce *c)
2561 struct mvneta_port *pp = netdev_priv(dev);
2563 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2564 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2566 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2571 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2572 struct ethtool_drvinfo *drvinfo)
2574 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2575 sizeof(drvinfo->driver));
2576 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2577 sizeof(drvinfo->version));
2578 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2579 sizeof(drvinfo->bus_info));
2583 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2584 struct ethtool_ringparam *ring)
2586 struct mvneta_port *pp = netdev_priv(netdev);
2588 ring->rx_max_pending = MVNETA_MAX_RXD;
2589 ring->tx_max_pending = MVNETA_MAX_TXD;
2590 ring->rx_pending = pp->rx_ring_size;
2591 ring->tx_pending = pp->tx_ring_size;
2594 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2595 struct ethtool_ringparam *ring)
2597 struct mvneta_port *pp = netdev_priv(dev);
2599 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2601 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2602 ring->rx_pending : MVNETA_MAX_RXD;
2603 pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ?
2604 ring->tx_pending : MVNETA_MAX_TXD;
2606 if (netif_running(dev)) {
2608 if (mvneta_open(dev)) {
2610 "error on opening device after ring param change\n");
2618 static const struct net_device_ops mvneta_netdev_ops = {
2619 .ndo_open = mvneta_open,
2620 .ndo_stop = mvneta_stop,
2621 .ndo_start_xmit = mvneta_tx,
2622 .ndo_set_rx_mode = mvneta_set_rx_mode,
2623 .ndo_set_mac_address = mvneta_set_mac_addr,
2624 .ndo_change_mtu = mvneta_change_mtu,
2625 .ndo_get_stats64 = mvneta_get_stats64,
2626 .ndo_do_ioctl = mvneta_ioctl,
2629 const struct ethtool_ops mvneta_eth_tool_ops = {
2630 .get_link = ethtool_op_get_link,
2631 .get_settings = mvneta_ethtool_get_settings,
2632 .set_settings = mvneta_ethtool_set_settings,
2633 .set_coalesce = mvneta_ethtool_set_coalesce,
2634 .get_coalesce = mvneta_ethtool_get_coalesce,
2635 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2636 .get_ringparam = mvneta_ethtool_get_ringparam,
2637 .set_ringparam = mvneta_ethtool_set_ringparam,
2641 static int mvneta_init(struct mvneta_port *pp, int phy_addr)
2646 mvneta_port_disable(pp);
2648 /* Set port default values */
2649 mvneta_defaults_set(pp);
2651 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
2656 /* Initialize TX descriptor rings */
2657 for (queue = 0; queue < txq_number; queue++) {
2658 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2660 txq->size = pp->tx_ring_size;
2661 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2664 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
2671 /* Create Rx descriptor rings */
2672 for (queue = 0; queue < rxq_number; queue++) {
2673 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2675 rxq->size = pp->rx_ring_size;
2676 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2677 rxq->time_coal = MVNETA_RX_COAL_USEC;
2683 static void mvneta_deinit(struct mvneta_port *pp)
2689 /* platform glue : initialize decoding windows */
2690 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2691 const struct mbus_dram_target_info *dram)
2697 for (i = 0; i < 6; i++) {
2698 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2699 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2702 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2708 for (i = 0; i < dram->num_cs; i++) {
2709 const struct mbus_dram_window *cs = dram->cs + i;
2710 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2711 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2713 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2714 (cs->size - 1) & 0xffff0000);
2716 win_enable &= ~(1 << i);
2717 win_protect |= 3 << (2 * i);
2720 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2723 /* Power up the port */
2724 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2728 /* MAC Cause register should be cleared */
2729 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2731 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2733 /* Even though it might look weird, when we're configured in
2734 * SGMII or QSGMII mode, the RGMII bit needs to be set.
2737 case PHY_INTERFACE_MODE_QSGMII:
2738 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
2739 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
2741 case PHY_INTERFACE_MODE_SGMII:
2742 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
2743 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
2745 case PHY_INTERFACE_MODE_RGMII:
2746 case PHY_INTERFACE_MODE_RGMII_ID:
2747 ctrl |= MVNETA_GMAC2_PORT_RGMII;
2753 /* Cancel Port Reset */
2754 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
2755 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
2757 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2758 MVNETA_GMAC2_PORT_RESET) != 0)
2764 /* Device initialization routine */
2765 static int mvneta_probe(struct platform_device *pdev)
2767 const struct mbus_dram_target_info *dram_target_info;
2768 struct resource *res;
2769 struct device_node *dn = pdev->dev.of_node;
2770 struct device_node *phy_node;
2772 struct mvneta_port *pp;
2773 struct net_device *dev;
2774 const char *dt_mac_addr;
2775 char hw_mac_addr[ETH_ALEN];
2776 const char *mac_from;
2780 /* Our multiqueue support is not complete, so for now, only
2781 * allow the usage of the first RX queue
2784 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
2788 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
2792 dev->irq = irq_of_parse_and_map(dn, 0);
2793 if (dev->irq == 0) {
2795 goto err_free_netdev;
2798 phy_node = of_parse_phandle(dn, "phy", 0);
2800 if (!of_phy_is_fixed_link(dn)) {
2801 dev_err(&pdev->dev, "no PHY specified\n");
2806 err = of_phy_register_fixed_link(dn);
2808 dev_err(&pdev->dev, "cannot register fixed PHY\n");
2812 /* In the case of a fixed PHY, the DT node associated
2813 * to the PHY is the Ethernet MAC DT node.
2818 phy_mode = of_get_phy_mode(dn);
2820 dev_err(&pdev->dev, "incorrect phy-mode\n");
2825 dev->tx_queue_len = MVNETA_MAX_TXD;
2826 dev->watchdog_timeo = 5 * HZ;
2827 dev->netdev_ops = &mvneta_netdev_ops;
2829 dev->ethtool_ops = &mvneta_eth_tool_ops;
2831 pp = netdev_priv(dev);
2833 pp->weight = MVNETA_RX_POLL_WEIGHT;
2834 pp->phy_node = phy_node;
2835 pp->phy_interface = phy_mode;
2837 pp->clk = devm_clk_get(&pdev->dev, NULL);
2838 if (IS_ERR(pp->clk)) {
2839 err = PTR_ERR(pp->clk);
2843 clk_prepare_enable(pp->clk);
2845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2846 pp->base = devm_ioremap_resource(&pdev->dev, res);
2847 if (IS_ERR(pp->base)) {
2848 err = PTR_ERR(pp->base);
2852 /* Alloc per-cpu stats */
2853 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
2859 dt_mac_addr = of_get_mac_address(dn);
2861 mac_from = "device tree";
2862 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
2864 mvneta_get_mac_addr(pp, hw_mac_addr);
2865 if (is_valid_ether_addr(hw_mac_addr)) {
2866 mac_from = "hardware";
2867 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
2869 mac_from = "random";
2870 eth_hw_addr_random(dev);
2874 pp->tx_ring_size = MVNETA_MAX_TXD;
2875 pp->rx_ring_size = MVNETA_MAX_RXD;
2878 SET_NETDEV_DEV(dev, &pdev->dev);
2880 err = mvneta_init(pp, phy_addr);
2882 dev_err(&pdev->dev, "can't init eth hal\n");
2883 goto err_free_stats;
2886 err = mvneta_port_power_up(pp, phy_mode);
2888 dev_err(&pdev->dev, "can't power up port\n");
2892 dram_target_info = mv_mbus_dram_info();
2893 if (dram_target_info)
2894 mvneta_conf_mbus_windows(pp, dram_target_info);
2896 netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight);
2898 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2899 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2900 dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2901 dev->priv_flags |= IFF_UNICAST_FLT;
2903 err = register_netdev(dev);
2905 dev_err(&pdev->dev, "failed to register\n");
2909 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
2912 platform_set_drvdata(pdev, pp->dev);
2919 free_percpu(pp->stats);
2921 clk_disable_unprepare(pp->clk);
2923 irq_dispose_mapping(dev->irq);
2929 /* Device removal routine */
2930 static int mvneta_remove(struct platform_device *pdev)
2932 struct net_device *dev = platform_get_drvdata(pdev);
2933 struct mvneta_port *pp = netdev_priv(dev);
2935 unregister_netdev(dev);
2937 clk_disable_unprepare(pp->clk);
2938 free_percpu(pp->stats);
2939 irq_dispose_mapping(dev->irq);
2945 static const struct of_device_id mvneta_match[] = {
2946 { .compatible = "marvell,armada-370-neta" },
2949 MODULE_DEVICE_TABLE(of, mvneta_match);
2951 static struct platform_driver mvneta_driver = {
2952 .probe = mvneta_probe,
2953 .remove = mvneta_remove,
2955 .name = MVNETA_DRIVER_NAME,
2956 .of_match_table = mvneta_match,
2960 module_platform_driver(mvneta_driver);
2962 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
2963 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
2964 MODULE_LICENSE("GPL");
2966 module_param(rxq_number, int, S_IRUGO);
2967 module_param(txq_number, int, S_IRUGO);
2969 module_param(rxq_def, int, S_IRUGO);
2970 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);