2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/of_address.h>
32 #include <linux/phy.h>
33 #include <linux/clk.h>
36 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
37 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
38 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
39 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
40 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
41 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
42 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
43 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
44 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
45 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
46 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
47 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
48 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
49 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
50 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
51 #define MVNETA_PORT_RX_RESET 0x1cc0
52 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
53 #define MVNETA_PHY_ADDR 0x2000
54 #define MVNETA_PHY_ADDR_MASK 0x1f
55 #define MVNETA_MBUS_RETRY 0x2010
56 #define MVNETA_UNIT_INTR_CAUSE 0x2080
57 #define MVNETA_UNIT_CONTROL 0x20B0
58 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
59 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
60 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
61 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
62 #define MVNETA_BASE_ADDR_ENABLE 0x2290
63 #define MVNETA_PORT_CONFIG 0x2400
64 #define MVNETA_UNI_PROMISC_MODE BIT(0)
65 #define MVNETA_DEF_RXQ(q) ((q) << 1)
66 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
67 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
68 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
69 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
70 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
71 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
72 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
73 MVNETA_DEF_RXQ_ARP(q) | \
74 MVNETA_DEF_RXQ_TCP(q) | \
75 MVNETA_DEF_RXQ_UDP(q) | \
76 MVNETA_DEF_RXQ_BPDU(q) | \
77 MVNETA_TX_UNSET_ERR_SUM | \
78 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
79 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
80 #define MVNETA_MAC_ADDR_LOW 0x2414
81 #define MVNETA_MAC_ADDR_HIGH 0x2418
82 #define MVNETA_SDMA_CONFIG 0x241c
83 #define MVNETA_SDMA_BRST_SIZE_16 4
84 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
85 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
86 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
87 #define MVNETA_DESC_SWAP BIT(6)
88 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
89 #define MVNETA_PORT_STATUS 0x2444
90 #define MVNETA_TX_IN_PRGRS BIT(1)
91 #define MVNETA_TX_FIFO_EMPTY BIT(8)
92 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
93 #define MVNETA_SERDES_CFG 0x24A0
94 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
95 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
96 #define MVNETA_TYPE_PRIO 0x24bc
97 #define MVNETA_FORCE_UNI BIT(21)
98 #define MVNETA_TXQ_CMD_1 0x24e4
99 #define MVNETA_TXQ_CMD 0x2448
100 #define MVNETA_TXQ_DISABLE_SHIFT 8
101 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
102 #define MVNETA_ACC_MODE 0x2500
103 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
104 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
105 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
106 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
108 /* Exception Interrupt Port/Queue Cause register */
110 #define MVNETA_INTR_NEW_CAUSE 0x25a0
111 #define MVNETA_INTR_NEW_MASK 0x25a4
113 /* bits 0..7 = TXQ SENT, one bit per queue.
114 * bits 8..15 = RXQ OCCUP, one bit per queue.
115 * bits 16..23 = RXQ FREE, one bit per queue.
116 * bit 29 = OLD_REG_SUM, see old reg ?
117 * bit 30 = TX_ERR_SUM, one bit for 4 ports
118 * bit 31 = MISC_SUM, one bit for 4 ports
120 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
121 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
122 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
123 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
125 #define MVNETA_INTR_OLD_CAUSE 0x25a8
126 #define MVNETA_INTR_OLD_MASK 0x25ac
128 /* Data Path Port/Queue Cause Register */
129 #define MVNETA_INTR_MISC_CAUSE 0x25b0
130 #define MVNETA_INTR_MISC_MASK 0x25b4
132 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
133 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
134 #define MVNETA_CAUSE_PTP BIT(4)
136 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
137 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
138 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
139 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
140 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
141 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
142 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
143 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
145 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
146 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
147 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
149 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
150 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
151 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
153 #define MVNETA_INTR_ENABLE 0x25b8
154 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
155 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF
157 #define MVNETA_RXQ_CMD 0x2680
158 #define MVNETA_RXQ_DISABLE_SHIFT 8
159 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
160 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
161 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
162 #define MVNETA_GMAC_CTRL_0 0x2c00
163 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
164 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
165 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
166 #define MVNETA_GMAC_CTRL_2 0x2c08
167 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
168 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
169 #define MVNETA_GMAC2_PORT_RESET BIT(6)
170 #define MVNETA_GMAC_STATUS 0x2c10
171 #define MVNETA_GMAC_LINK_UP BIT(0)
172 #define MVNETA_GMAC_SPEED_1000 BIT(1)
173 #define MVNETA_GMAC_SPEED_100 BIT(2)
174 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
175 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
176 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
177 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
178 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
179 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
180 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
181 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
182 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
183 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
184 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
185 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
186 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
187 #define MVNETA_MIB_COUNTERS_BASE 0x3080
188 #define MVNETA_MIB_LATE_COLLISION 0x7c
189 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
190 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
191 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
192 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
193 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
194 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
195 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
196 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
197 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
198 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
199 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
200 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
201 #define MVNETA_PORT_TX_RESET 0x3cf0
202 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
203 #define MVNETA_TX_MTU 0x3e0c
204 #define MVNETA_TX_TOKEN_SIZE 0x3e14
205 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
206 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
207 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
209 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
211 /* Descriptor ring Macros */
212 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
213 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
215 /* Various constants */
218 #define MVNETA_TXDONE_COAL_PKTS 16
219 #define MVNETA_RX_COAL_PKTS 32
220 #define MVNETA_RX_COAL_USEC 100
222 /* The two bytes Marvell header. Either contains a special value used
223 * by Marvell switches when a specific hardware mode is enabled (not
224 * supported by this driver) or is filled automatically by zeroes on
225 * the RX side. Those two bytes being at the front of the Ethernet
226 * header, they allow to have the IP header aligned on a 4 bytes
227 * boundary automatically: the hardware skips those two bytes on its
230 #define MVNETA_MH_SIZE 2
232 #define MVNETA_VLAN_TAG_LEN 4
234 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
235 #define MVNETA_TX_CSUM_MAX_SIZE 9800
236 #define MVNETA_ACC_MODE_EXT 1
238 /* Timeout constants */
239 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
240 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
241 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
243 #define MVNETA_TX_MTU_MAX 0x3ffff
245 /* TSO header size */
246 #define TSO_HEADER_SIZE 128
248 /* Max number of Rx descriptors */
249 #define MVNETA_MAX_RXD 128
251 /* Max number of Tx descriptors */
252 #define MVNETA_MAX_TXD 532
254 /* Max number of allowed TCP segments for software TSO */
255 #define MVNETA_MAX_TSO_SEGS 100
257 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
259 /* descriptor aligned size */
260 #define MVNETA_DESC_ALIGNED_SIZE 32
262 #define MVNETA_RX_PKT_SIZE(mtu) \
263 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
264 ETH_HLEN + ETH_FCS_LEN, \
265 MVNETA_CPU_D_CACHE_LINE_SIZE)
267 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
269 struct mvneta_pcpu_stats {
270 struct u64_stats_sync syncp;
279 unsigned int frag_size;
281 struct mvneta_rx_queue *rxqs;
282 struct mvneta_tx_queue *txqs;
283 struct net_device *dev;
286 struct napi_struct napi;
293 struct mvneta_pcpu_stats *stats;
295 struct mii_bus *mii_bus;
296 struct phy_device *phy_dev;
297 phy_interface_t phy_interface;
298 struct device_node *phy_node;
304 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
305 * layout of the transmit and reception DMA descriptors, and their
306 * layout is therefore defined by the hardware design
309 #define MVNETA_TX_L3_OFF_SHIFT 0
310 #define MVNETA_TX_IP_HLEN_SHIFT 8
311 #define MVNETA_TX_L4_UDP BIT(16)
312 #define MVNETA_TX_L3_IP6 BIT(17)
313 #define MVNETA_TXD_IP_CSUM BIT(18)
314 #define MVNETA_TXD_Z_PAD BIT(19)
315 #define MVNETA_TXD_L_DESC BIT(20)
316 #define MVNETA_TXD_F_DESC BIT(21)
317 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
318 MVNETA_TXD_L_DESC | \
320 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
321 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
323 #define MVNETA_RXD_ERR_CRC 0x0
324 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
325 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
326 #define MVNETA_RXD_ERR_LEN BIT(18)
327 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
328 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
329 #define MVNETA_RXD_L3_IP4 BIT(25)
330 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
331 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
333 #if defined(__LITTLE_ENDIAN)
334 struct mvneta_tx_desc {
335 u32 command; /* Options used by HW for packet transmitting.*/
336 u16 reserverd1; /* csum_l4 (for future use) */
337 u16 data_size; /* Data size of transmitted packet in bytes */
338 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
339 u32 reserved2; /* hw_cmd - (for future use, PMT) */
340 u32 reserved3[4]; /* Reserved - (for future use) */
343 struct mvneta_rx_desc {
344 u32 status; /* Info about received packet */
345 u16 reserved1; /* pnc_info - (for future use, PnC) */
346 u16 data_size; /* Size of received packet in bytes */
348 u32 buf_phys_addr; /* Physical address of the buffer */
349 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
351 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
352 u16 reserved3; /* prefetch_cmd, for future use */
353 u16 reserved4; /* csum_l4 - (for future use, PnC) */
355 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
356 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
359 struct mvneta_tx_desc {
360 u16 data_size; /* Data size of transmitted packet in bytes */
361 u16 reserverd1; /* csum_l4 (for future use) */
362 u32 command; /* Options used by HW for packet transmitting.*/
363 u32 reserved2; /* hw_cmd - (for future use, PMT) */
364 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
365 u32 reserved3[4]; /* Reserved - (for future use) */
368 struct mvneta_rx_desc {
369 u16 data_size; /* Size of received packet in bytes */
370 u16 reserved1; /* pnc_info - (for future use, PnC) */
371 u32 status; /* Info about received packet */
373 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
374 u32 buf_phys_addr; /* Physical address of the buffer */
376 u16 reserved4; /* csum_l4 - (for future use, PnC) */
377 u16 reserved3; /* prefetch_cmd, for future use */
378 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
380 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
381 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
385 struct mvneta_tx_queue {
386 /* Number of this TX queue, in the range 0-7 */
389 /* Number of TX DMA descriptors in the descriptor ring */
392 /* Number of currently used TX DMA descriptor in the
396 int tx_stop_threshold;
397 int tx_wake_threshold;
399 /* Array of transmitted skb */
400 struct sk_buff **tx_skb;
402 /* Index of last TX DMA descriptor that was inserted */
405 /* Index of the TX DMA descriptor to be cleaned up */
410 /* Virtual address of the TX DMA descriptors array */
411 struct mvneta_tx_desc *descs;
413 /* DMA address of the TX DMA descriptors array */
414 dma_addr_t descs_phys;
416 /* Index of the last TX DMA descriptor */
419 /* Index of the next TX DMA descriptor to process */
420 int next_desc_to_proc;
422 /* DMA buffers for TSO headers */
425 /* DMA address of TSO headers */
426 dma_addr_t tso_hdrs_phys;
429 struct mvneta_rx_queue {
430 /* rx queue number, in the range 0-7 */
433 /* num of rx descriptors in the rx descriptor ring */
436 /* counter of times when mvneta_refill() failed */
442 /* Virtual address of the RX DMA descriptors array */
443 struct mvneta_rx_desc *descs;
445 /* DMA address of the RX DMA descriptors array */
446 dma_addr_t descs_phys;
448 /* Index of the last RX DMA descriptor */
451 /* Index of the next RX DMA descriptor to process */
452 int next_desc_to_proc;
455 /* The hardware supports eight (8) rx queues, but we are only allowing
456 * the first one to be used. Therefore, let's just allocate one queue.
458 static int rxq_number = 1;
459 static int txq_number = 8;
463 static int rx_copybreak __read_mostly = 256;
465 #define MVNETA_DRIVER_NAME "mvneta"
466 #define MVNETA_DRIVER_VERSION "1.0"
468 /* Utility/helper methods */
470 /* Write helper method */
471 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
473 writel(data, pp->base + offset);
476 /* Read helper method */
477 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
479 return readl(pp->base + offset);
482 /* Increment txq get counter */
483 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
485 txq->txq_get_index++;
486 if (txq->txq_get_index == txq->size)
487 txq->txq_get_index = 0;
490 /* Increment txq put counter */
491 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
493 txq->txq_put_index++;
494 if (txq->txq_put_index == txq->size)
495 txq->txq_put_index = 0;
499 /* Clear all MIB counters */
500 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
505 /* Perform dummy reads from MIB counters */
506 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
507 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
510 /* Get System Network Statistics */
511 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
512 struct rtnl_link_stats64 *stats)
514 struct mvneta_port *pp = netdev_priv(dev);
518 for_each_possible_cpu(cpu) {
519 struct mvneta_pcpu_stats *cpu_stats;
525 cpu_stats = per_cpu_ptr(pp->stats, cpu);
527 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
528 rx_packets = cpu_stats->rx_packets;
529 rx_bytes = cpu_stats->rx_bytes;
530 tx_packets = cpu_stats->tx_packets;
531 tx_bytes = cpu_stats->tx_bytes;
532 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
534 stats->rx_packets += rx_packets;
535 stats->rx_bytes += rx_bytes;
536 stats->tx_packets += tx_packets;
537 stats->tx_bytes += tx_bytes;
540 stats->rx_errors = dev->stats.rx_errors;
541 stats->rx_dropped = dev->stats.rx_dropped;
543 stats->tx_dropped = dev->stats.tx_dropped;
548 /* Rx descriptors helper methods */
550 /* Checks whether the RX descriptor having this status is both the first
551 * and the last descriptor for the RX packet. Each RX packet is currently
552 * received through a single RX descriptor, so not having each RX
553 * descriptor with its first and last bits set is an error
555 static int mvneta_rxq_desc_is_first_last(u32 status)
557 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
558 MVNETA_RXD_FIRST_LAST_DESC;
561 /* Add number of descriptors ready to receive new packets */
562 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
563 struct mvneta_rx_queue *rxq,
566 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
569 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
570 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
571 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
572 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
573 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
576 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
577 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
580 /* Get number of RX descriptors occupied by received packets */
581 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
582 struct mvneta_rx_queue *rxq)
586 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
587 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
590 /* Update num of rx desc called upon return from rx path or
591 * from mvneta_rxq_drop_pkts().
593 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
594 struct mvneta_rx_queue *rxq,
595 int rx_done, int rx_filled)
599 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
601 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
602 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
606 /* Only 255 descriptors can be added at once */
607 while ((rx_done > 0) || (rx_filled > 0)) {
608 if (rx_done <= 0xff) {
615 if (rx_filled <= 0xff) {
616 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
619 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
622 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
626 /* Get pointer to next RX descriptor to be processed by SW */
627 static struct mvneta_rx_desc *
628 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
630 int rx_desc = rxq->next_desc_to_proc;
632 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
633 prefetch(rxq->descs + rxq->next_desc_to_proc);
634 return rxq->descs + rx_desc;
637 /* Change maximum receive size of the port. */
638 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
642 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
643 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
644 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
645 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
646 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
650 /* Set rx queue offset */
651 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
652 struct mvneta_rx_queue *rxq,
657 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
658 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
661 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
662 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
666 /* Tx descriptors helper methods */
668 /* Update HW with number of TX descriptors to be sent */
669 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
670 struct mvneta_tx_queue *txq,
675 /* Only 255 descriptors can be added at once ; Assume caller
676 * process TX desriptors in quanta less than 256
679 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
682 /* Get pointer to next TX descriptor to be processed (send) by HW */
683 static struct mvneta_tx_desc *
684 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
686 int tx_desc = txq->next_desc_to_proc;
688 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
689 return txq->descs + tx_desc;
692 /* Release the last allocated TX descriptor. Useful to handle DMA
693 * mapping failures in the TX path.
695 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
697 if (txq->next_desc_to_proc == 0)
698 txq->next_desc_to_proc = txq->last_desc - 1;
700 txq->next_desc_to_proc--;
703 /* Set rxq buf size */
704 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
705 struct mvneta_rx_queue *rxq,
710 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
712 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
713 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
715 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
718 /* Disable buffer management (BM) */
719 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
720 struct mvneta_rx_queue *rxq)
724 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
725 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
726 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
729 /* Start the Ethernet port RX and TX activity */
730 static void mvneta_port_up(struct mvneta_port *pp)
735 /* Enable all initialized TXs. */
736 mvneta_mib_counters_clear(pp);
738 for (queue = 0; queue < txq_number; queue++) {
739 struct mvneta_tx_queue *txq = &pp->txqs[queue];
740 if (txq->descs != NULL)
741 q_map |= (1 << queue);
743 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
745 /* Enable all initialized RXQs. */
747 for (queue = 0; queue < rxq_number; queue++) {
748 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
749 if (rxq->descs != NULL)
750 q_map |= (1 << queue);
753 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
756 /* Stop the Ethernet port activity */
757 static void mvneta_port_down(struct mvneta_port *pp)
762 /* Stop Rx port activity. Check port Rx activity. */
763 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
765 /* Issue stop command for active channels only */
767 mvreg_write(pp, MVNETA_RXQ_CMD,
768 val << MVNETA_RXQ_DISABLE_SHIFT);
770 /* Wait for all Rx activity to terminate. */
773 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
775 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
781 val = mvreg_read(pp, MVNETA_RXQ_CMD);
782 } while (val & 0xff);
784 /* Stop Tx port activity. Check port Tx activity. Issue stop
785 * command for active channels only
787 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
790 mvreg_write(pp, MVNETA_TXQ_CMD,
791 (val << MVNETA_TXQ_DISABLE_SHIFT));
793 /* Wait for all Tx activity to terminate. */
796 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
798 "TIMEOUT for TX stopped status=0x%08x\n",
804 /* Check TX Command reg that all Txqs are stopped */
805 val = mvreg_read(pp, MVNETA_TXQ_CMD);
807 } while (val & 0xff);
809 /* Double check to verify that TX FIFO is empty */
812 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
814 "TX FIFO empty timeout status=0x08%x\n",
820 val = mvreg_read(pp, MVNETA_PORT_STATUS);
821 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
822 (val & MVNETA_TX_IN_PRGRS));
827 /* Enable the port by setting the port enable bit of the MAC control register */
828 static void mvneta_port_enable(struct mvneta_port *pp)
833 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
834 val |= MVNETA_GMAC0_PORT_ENABLE;
835 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
838 /* Disable the port and wait for about 200 usec before retuning */
839 static void mvneta_port_disable(struct mvneta_port *pp)
843 /* Reset the Enable bit in the Serial Control Register */
844 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
845 val &= ~MVNETA_GMAC0_PORT_ENABLE;
846 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
851 /* Multicast tables methods */
853 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
854 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
862 val = 0x1 | (queue << 1);
863 val |= (val << 24) | (val << 16) | (val << 8);
866 for (offset = 0; offset <= 0xc; offset += 4)
867 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
870 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
871 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
879 val = 0x1 | (queue << 1);
880 val |= (val << 24) | (val << 16) | (val << 8);
883 for (offset = 0; offset <= 0xfc; offset += 4)
884 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
888 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
889 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
895 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
898 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
899 val = 0x1 | (queue << 1);
900 val |= (val << 24) | (val << 16) | (val << 8);
903 for (offset = 0; offset <= 0xfc; offset += 4)
904 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
907 /* This method sets defaults to the NETA port:
908 * Clears interrupt Cause and Mask registers.
909 * Clears all MAC tables.
910 * Sets defaults to all registers.
911 * Resets RX and TX descriptor rings.
913 * This method can be called after mvneta_port_down() to return the port
914 * settings to defaults.
916 static void mvneta_defaults_set(struct mvneta_port *pp)
922 /* Clear all Cause registers */
923 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
924 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
925 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
927 /* Mask all interrupts */
928 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
929 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
930 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
931 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
933 /* Enable MBUS Retry bit16 */
934 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
936 /* Set CPU queue access map - all CPUs have access to all RX
937 * queues and to all TX queues
939 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
940 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
941 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
942 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
944 /* Reset RX and TX DMAs */
945 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
946 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
948 /* Disable Legacy WRR, Disable EJP, Release from reset */
949 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
950 for (queue = 0; queue < txq_number; queue++) {
951 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
952 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
955 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
956 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
958 /* Set Port Acceleration Mode */
959 val = MVNETA_ACC_MODE_EXT;
960 mvreg_write(pp, MVNETA_ACC_MODE, val);
962 /* Update val of portCfg register accordingly with all RxQueue types */
963 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
964 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
967 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
968 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
970 /* Build PORT_SDMA_CONFIG_REG */
973 /* Default burst size */
974 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
975 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
976 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
978 #if defined(__BIG_ENDIAN)
979 val |= MVNETA_DESC_SWAP;
982 /* Assign port SDMA configuration */
983 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
985 /* Disable PHY polling in hardware, since we're using the
986 * kernel phylib to do this.
988 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
989 val &= ~MVNETA_PHY_POLLING_ENABLE;
990 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
992 mvneta_set_ucast_table(pp, -1);
993 mvneta_set_special_mcast_table(pp, -1);
994 mvneta_set_other_mcast_table(pp, -1);
996 /* Set port interrupt enable register - default enable all */
997 mvreg_write(pp, MVNETA_INTR_ENABLE,
998 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
999 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1002 /* Set max sizes for tx queues */
1003 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1009 mtu = max_tx_size * 8;
1010 if (mtu > MVNETA_TX_MTU_MAX)
1011 mtu = MVNETA_TX_MTU_MAX;
1014 val = mvreg_read(pp, MVNETA_TX_MTU);
1015 val &= ~MVNETA_TX_MTU_MAX;
1017 mvreg_write(pp, MVNETA_TX_MTU, val);
1019 /* TX token size and all TXQs token size must be larger that MTU */
1020 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1022 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1025 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1027 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1029 for (queue = 0; queue < txq_number; queue++) {
1030 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1032 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1035 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1037 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1042 /* Set unicast address */
1043 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1046 unsigned int unicast_reg;
1047 unsigned int tbl_offset;
1048 unsigned int reg_offset;
1050 /* Locate the Unicast table entry */
1051 last_nibble = (0xf & last_nibble);
1053 /* offset from unicast tbl base */
1054 tbl_offset = (last_nibble / 4) * 4;
1056 /* offset within the above reg */
1057 reg_offset = last_nibble % 4;
1059 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1062 /* Clear accepts frame bit at specified unicast DA tbl entry */
1063 unicast_reg &= ~(0xff << (8 * reg_offset));
1065 unicast_reg &= ~(0xff << (8 * reg_offset));
1066 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1069 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1072 /* Set mac address */
1073 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1080 mac_l = (addr[4] << 8) | (addr[5]);
1081 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1082 (addr[2] << 8) | (addr[3] << 0);
1084 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1085 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1088 /* Accept frames of this address */
1089 mvneta_set_ucast_addr(pp, addr[5], queue);
1092 /* Set the number of packets that will be received before RX interrupt
1093 * will be generated by HW.
1095 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1096 struct mvneta_rx_queue *rxq, u32 value)
1098 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1099 value | MVNETA_RXQ_NON_OCCUPIED(0));
1100 rxq->pkts_coal = value;
1103 /* Set the time delay in usec before RX interrupt will be generated by
1106 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1107 struct mvneta_rx_queue *rxq, u32 value)
1110 unsigned long clk_rate;
1112 clk_rate = clk_get_rate(pp->clk);
1113 val = (clk_rate / 1000000) * value;
1115 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1116 rxq->time_coal = value;
1119 /* Set threshold for TX_DONE pkts coalescing */
1120 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1121 struct mvneta_tx_queue *txq, u32 value)
1125 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1127 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1128 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1130 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1132 txq->done_pkts_coal = value;
1135 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1136 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1137 u32 phys_addr, u32 cookie)
1139 rx_desc->buf_cookie = cookie;
1140 rx_desc->buf_phys_addr = phys_addr;
1143 /* Decrement sent descriptors counter */
1144 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1145 struct mvneta_tx_queue *txq,
1150 /* Only 255 TX descriptors can be updated at once */
1151 while (sent_desc > 0xff) {
1152 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1153 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1154 sent_desc = sent_desc - 0xff;
1157 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1158 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1161 /* Get number of TX descriptors already sent by HW */
1162 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1163 struct mvneta_tx_queue *txq)
1168 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1169 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1170 MVNETA_TXQ_SENT_DESC_SHIFT;
1175 /* Get number of sent descriptors and decrement counter.
1176 * The number of sent descriptors is returned.
1178 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1179 struct mvneta_tx_queue *txq)
1183 /* Get number of sent descriptors */
1184 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1186 /* Decrement sent descriptors counter */
1188 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1193 /* Set TXQ descriptors fields relevant for CSUM calculation */
1194 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1195 int ip_hdr_len, int l4_proto)
1199 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1200 * G_L4_chk, L4_type; required only for checksum
1203 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1204 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1206 if (l3_proto == swab16(ETH_P_IP))
1207 command |= MVNETA_TXD_IP_CSUM;
1209 command |= MVNETA_TX_L3_IP6;
1211 if (l4_proto == IPPROTO_TCP)
1212 command |= MVNETA_TX_L4_CSUM_FULL;
1213 else if (l4_proto == IPPROTO_UDP)
1214 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1216 command |= MVNETA_TX_L4_CSUM_NOT;
1222 /* Display more error info */
1223 static void mvneta_rx_error(struct mvneta_port *pp,
1224 struct mvneta_rx_desc *rx_desc)
1226 u32 status = rx_desc->status;
1228 if (!mvneta_rxq_desc_is_first_last(status)) {
1230 "bad rx status %08x (buffer oversize), size=%d\n",
1231 status, rx_desc->data_size);
1235 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1236 case MVNETA_RXD_ERR_CRC:
1237 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1238 status, rx_desc->data_size);
1240 case MVNETA_RXD_ERR_OVERRUN:
1241 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1242 status, rx_desc->data_size);
1244 case MVNETA_RXD_ERR_LEN:
1245 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1246 status, rx_desc->data_size);
1248 case MVNETA_RXD_ERR_RESOURCE:
1249 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1250 status, rx_desc->data_size);
1255 /* Handle RX checksum offload based on the descriptor's status */
1256 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1257 struct sk_buff *skb)
1259 if ((status & MVNETA_RXD_L3_IP4) &&
1260 (status & MVNETA_RXD_L4_CSUM_OK)) {
1262 skb->ip_summed = CHECKSUM_UNNECESSARY;
1266 skb->ip_summed = CHECKSUM_NONE;
1269 /* Return tx queue pointer (find last set bit) according to <cause> returned
1270 * form tx_done reg. <cause> must not be null. The return value is always a
1271 * valid queue for matching the first one found in <cause>.
1273 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1276 int queue = fls(cause) - 1;
1278 return &pp->txqs[queue];
1281 /* Free tx queue skbuffs */
1282 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1283 struct mvneta_tx_queue *txq, int num)
1287 for (i = 0; i < num; i++) {
1288 struct mvneta_tx_desc *tx_desc = txq->descs +
1290 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1292 mvneta_txq_inc_get(txq);
1294 dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr,
1295 tx_desc->data_size, DMA_TO_DEVICE);
1298 dev_kfree_skb_any(skb);
1302 /* Handle end of transmission */
1303 static void mvneta_txq_done(struct mvneta_port *pp,
1304 struct mvneta_tx_queue *txq)
1306 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1309 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1313 mvneta_txq_bufs_free(pp, txq, tx_done);
1315 txq->count -= tx_done;
1317 if (netif_tx_queue_stopped(nq)) {
1318 if (txq->count <= txq->tx_wake_threshold)
1319 netif_tx_wake_queue(nq);
1323 static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1325 if (likely(pp->frag_size <= PAGE_SIZE))
1326 return netdev_alloc_frag(pp->frag_size);
1328 return kmalloc(pp->frag_size, GFP_ATOMIC);
1331 static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1333 if (likely(pp->frag_size <= PAGE_SIZE))
1334 put_page(virt_to_head_page(data));
1339 /* Refill processing */
1340 static int mvneta_rx_refill(struct mvneta_port *pp,
1341 struct mvneta_rx_desc *rx_desc)
1344 dma_addr_t phys_addr;
1347 data = mvneta_frag_alloc(pp);
1351 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1352 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1354 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1355 mvneta_frag_free(pp, data);
1359 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1363 /* Handle tx checksum */
1364 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1366 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1370 if (skb->protocol == htons(ETH_P_IP)) {
1371 struct iphdr *ip4h = ip_hdr(skb);
1373 /* Calculate IPv4 checksum and L4 checksum */
1374 ip_hdr_len = ip4h->ihl;
1375 l4_proto = ip4h->protocol;
1376 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1377 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1379 /* Read l4_protocol from one of IPv6 extra headers */
1380 if (skb_network_header_len(skb) > 0)
1381 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1382 l4_proto = ip6h->nexthdr;
1384 return MVNETA_TX_L4_CSUM_NOT;
1386 return mvneta_txq_desc_csum(skb_network_offset(skb),
1387 skb->protocol, ip_hdr_len, l4_proto);
1390 return MVNETA_TX_L4_CSUM_NOT;
1393 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1396 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1399 int queue = fls(cause >> 8) - 1;
1401 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1404 /* Drop packets received by the RXQ and free buffers */
1405 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1406 struct mvneta_rx_queue *rxq)
1410 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1411 for (i = 0; i < rxq->size; i++) {
1412 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1413 void *data = (void *)rx_desc->buf_cookie;
1415 mvneta_frag_free(pp, data);
1416 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1417 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1421 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1424 /* Main rx processing */
1425 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1426 struct mvneta_rx_queue *rxq)
1428 struct net_device *dev = pp->dev;
1429 int rx_done, rx_filled;
1433 /* Get number of received packets */
1434 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1436 if (rx_todo > rx_done)
1442 /* Fairness NAPI loop */
1443 while (rx_done < rx_todo) {
1444 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1445 struct sk_buff *skb;
1446 unsigned char *data;
1452 rx_status = rx_desc->status;
1453 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1454 data = (unsigned char *)rx_desc->buf_cookie;
1456 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1457 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1459 dev->stats.rx_errors++;
1460 mvneta_rx_error(pp, rx_desc);
1461 /* leave the descriptor untouched */
1465 if (rx_bytes <= rx_copybreak) {
1466 /* better copy a small frame and not unmap the DMA region */
1467 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1469 goto err_drop_frame;
1471 dma_sync_single_range_for_cpu(dev->dev.parent,
1472 rx_desc->buf_phys_addr,
1473 MVNETA_MH_SIZE + NET_SKB_PAD,
1476 memcpy(skb_put(skb, rx_bytes),
1477 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1480 skb->protocol = eth_type_trans(skb, dev);
1481 mvneta_rx_csum(pp, rx_status, skb);
1482 napi_gro_receive(&pp->napi, skb);
1485 rcvd_bytes += rx_bytes;
1487 /* leave the descriptor and buffer untouched */
1491 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
1493 goto err_drop_frame;
1495 dma_unmap_single(dev->dev.parent, rx_desc->buf_phys_addr,
1496 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1499 rcvd_bytes += rx_bytes;
1501 /* Linux processing */
1502 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1503 skb_put(skb, rx_bytes);
1505 skb->protocol = eth_type_trans(skb, dev);
1507 mvneta_rx_csum(pp, rx_status, skb);
1509 napi_gro_receive(&pp->napi, skb);
1511 /* Refill processing */
1512 err = mvneta_rx_refill(pp, rx_desc);
1514 netdev_err(dev, "Linux processing - Can't refill\n");
1521 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1523 u64_stats_update_begin(&stats->syncp);
1524 stats->rx_packets += rcvd_pkts;
1525 stats->rx_bytes += rcvd_bytes;
1526 u64_stats_update_end(&stats->syncp);
1529 /* Update rxq management counters */
1530 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1536 mvneta_tso_put_hdr(struct sk_buff *skb,
1537 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
1539 struct mvneta_tx_desc *tx_desc;
1540 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1542 txq->tx_skb[txq->txq_put_index] = NULL;
1543 tx_desc = mvneta_txq_next_desc_get(txq);
1544 tx_desc->data_size = hdr_len;
1545 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
1546 tx_desc->command |= MVNETA_TXD_F_DESC;
1547 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
1548 txq->txq_put_index * TSO_HEADER_SIZE;
1549 mvneta_txq_inc_put(txq);
1553 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
1554 struct sk_buff *skb, char *data, int size,
1555 bool last_tcp, bool is_last)
1557 struct mvneta_tx_desc *tx_desc;
1559 tx_desc = mvneta_txq_next_desc_get(txq);
1560 tx_desc->data_size = size;
1561 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
1562 size, DMA_TO_DEVICE);
1563 if (unlikely(dma_mapping_error(dev->dev.parent,
1564 tx_desc->buf_phys_addr))) {
1565 mvneta_txq_desc_put(txq);
1569 tx_desc->command = 0;
1570 txq->tx_skb[txq->txq_put_index] = NULL;
1573 /* last descriptor in the TCP packet */
1574 tx_desc->command = MVNETA_TXD_L_DESC;
1576 /* last descriptor in SKB */
1578 txq->tx_skb[txq->txq_put_index] = skb;
1580 mvneta_txq_inc_put(txq);
1584 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
1585 struct mvneta_tx_queue *txq)
1587 int total_len, data_left;
1589 struct mvneta_port *pp = netdev_priv(dev);
1591 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1594 /* Count needed descriptors */
1595 if ((txq->count + tso_count_descs(skb)) >= txq->size)
1598 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
1599 pr_info("*** Is this even possible???!?!?\n");
1603 /* Initialize the TSO handler, and prepare the first payload */
1604 tso_start(skb, &tso);
1606 total_len = skb->len - hdr_len;
1607 while (total_len > 0) {
1610 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1611 total_len -= data_left;
1614 /* prepare packet headers: MAC + IP + TCP */
1615 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
1616 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1618 mvneta_tso_put_hdr(skb, pp, txq);
1620 while (data_left > 0) {
1624 size = min_t(int, tso.size, data_left);
1626 if (mvneta_tso_put_data(dev, txq, skb,
1633 tso_build_data(skb, &tso, size);
1640 /* Release all used data descriptors; header descriptors must not
1643 for (i = desc_count - 1; i >= 0; i--) {
1644 struct mvneta_tx_desc *tx_desc = txq->descs + i;
1645 if (!(tx_desc->command & MVNETA_TXD_F_DESC))
1646 dma_unmap_single(pp->dev->dev.parent,
1647 tx_desc->buf_phys_addr,
1650 mvneta_txq_desc_put(txq);
1655 /* Handle tx fragmentation processing */
1656 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1657 struct mvneta_tx_queue *txq)
1659 struct mvneta_tx_desc *tx_desc;
1660 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1662 for (i = 0; i < nr_frags; i++) {
1663 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1664 void *addr = page_address(frag->page.p) + frag->page_offset;
1666 tx_desc = mvneta_txq_next_desc_get(txq);
1667 tx_desc->data_size = frag->size;
1669 tx_desc->buf_phys_addr =
1670 dma_map_single(pp->dev->dev.parent, addr,
1671 tx_desc->data_size, DMA_TO_DEVICE);
1673 if (dma_mapping_error(pp->dev->dev.parent,
1674 tx_desc->buf_phys_addr)) {
1675 mvneta_txq_desc_put(txq);
1679 if (i == nr_frags - 1) {
1680 /* Last descriptor */
1681 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1682 txq->tx_skb[txq->txq_put_index] = skb;
1684 /* Descriptor in the middle: Not First, Not Last */
1685 tx_desc->command = 0;
1686 txq->tx_skb[txq->txq_put_index] = NULL;
1688 mvneta_txq_inc_put(txq);
1694 /* Release all descriptors that were used to map fragments of
1695 * this packet, as well as the corresponding DMA mappings
1697 for (i = i - 1; i >= 0; i--) {
1698 tx_desc = txq->descs + i;
1699 dma_unmap_single(pp->dev->dev.parent,
1700 tx_desc->buf_phys_addr,
1703 mvneta_txq_desc_put(txq);
1709 /* Main tx processing */
1710 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1712 struct mvneta_port *pp = netdev_priv(dev);
1713 u16 txq_id = skb_get_queue_mapping(skb);
1714 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1715 struct mvneta_tx_desc *tx_desc;
1719 if (!netif_running(dev))
1722 if (skb_is_gso(skb)) {
1723 frags = mvneta_tx_tso(skb, dev, txq);
1727 frags = skb_shinfo(skb)->nr_frags + 1;
1729 /* Get a descriptor for the first part of the packet */
1730 tx_desc = mvneta_txq_next_desc_get(txq);
1732 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1734 tx_desc->data_size = skb_headlen(skb);
1736 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1739 if (unlikely(dma_mapping_error(dev->dev.parent,
1740 tx_desc->buf_phys_addr))) {
1741 mvneta_txq_desc_put(txq);
1747 /* First and Last descriptor */
1748 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1749 tx_desc->command = tx_cmd;
1750 txq->tx_skb[txq->txq_put_index] = skb;
1751 mvneta_txq_inc_put(txq);
1753 /* First but not Last */
1754 tx_cmd |= MVNETA_TXD_F_DESC;
1755 txq->tx_skb[txq->txq_put_index] = NULL;
1756 mvneta_txq_inc_put(txq);
1757 tx_desc->command = tx_cmd;
1758 /* Continue with other skb fragments */
1759 if (mvneta_tx_frag_process(pp, skb, txq)) {
1760 dma_unmap_single(dev->dev.parent,
1761 tx_desc->buf_phys_addr,
1764 mvneta_txq_desc_put(txq);
1772 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1773 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
1775 txq->count += frags;
1776 mvneta_txq_pend_desc_add(pp, txq, frags);
1778 if (txq->count >= txq->tx_stop_threshold)
1779 netif_tx_stop_queue(nq);
1781 u64_stats_update_begin(&stats->syncp);
1782 stats->tx_packets++;
1783 stats->tx_bytes += skb->len;
1784 u64_stats_update_end(&stats->syncp);
1786 dev->stats.tx_dropped++;
1787 dev_kfree_skb_any(skb);
1790 return NETDEV_TX_OK;
1794 /* Free tx resources, when resetting a port */
1795 static void mvneta_txq_done_force(struct mvneta_port *pp,
1796 struct mvneta_tx_queue *txq)
1799 int tx_done = txq->count;
1801 mvneta_txq_bufs_free(pp, txq, tx_done);
1805 txq->txq_put_index = 0;
1806 txq->txq_get_index = 0;
1809 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
1810 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1812 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
1814 struct mvneta_tx_queue *txq;
1815 struct netdev_queue *nq;
1817 while (cause_tx_done) {
1818 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1820 nq = netdev_get_tx_queue(pp->dev, txq->id);
1821 __netif_tx_lock(nq, smp_processor_id());
1824 mvneta_txq_done(pp, txq);
1826 __netif_tx_unlock(nq);
1827 cause_tx_done &= ~((1 << txq->id));
1831 /* Compute crc8 of the specified address, using a unique algorithm ,
1832 * according to hw spec, different than generic crc8 algorithm
1834 static int mvneta_addr_crc(unsigned char *addr)
1839 for (i = 0; i < ETH_ALEN; i++) {
1842 crc = (crc ^ addr[i]) << 8;
1843 for (j = 7; j >= 0; j--) {
1844 if (crc & (0x100 << j))
1852 /* This method controls the net device special MAC multicast support.
1853 * The Special Multicast Table for MAC addresses supports MAC of the form
1854 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1855 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1856 * Table entries in the DA-Filter table. This method set the Special
1857 * Multicast Table appropriate entry.
1859 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1860 unsigned char last_byte,
1863 unsigned int smc_table_reg;
1864 unsigned int tbl_offset;
1865 unsigned int reg_offset;
1867 /* Register offset from SMC table base */
1868 tbl_offset = (last_byte / 4);
1869 /* Entry offset within the above reg */
1870 reg_offset = last_byte % 4;
1872 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1876 smc_table_reg &= ~(0xff << (8 * reg_offset));
1878 smc_table_reg &= ~(0xff << (8 * reg_offset));
1879 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1882 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1886 /* This method controls the network device Other MAC multicast support.
1887 * The Other Multicast Table is used for multicast of another type.
1888 * A CRC-8 is used as an index to the Other Multicast Table entries
1889 * in the DA-Filter table.
1890 * The method gets the CRC-8 value from the calling routine and
1891 * sets the Other Multicast Table appropriate entry according to the
1894 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1898 unsigned int omc_table_reg;
1899 unsigned int tbl_offset;
1900 unsigned int reg_offset;
1902 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1903 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1905 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1908 /* Clear accepts frame bit at specified Other DA table entry */
1909 omc_table_reg &= ~(0xff << (8 * reg_offset));
1911 omc_table_reg &= ~(0xff << (8 * reg_offset));
1912 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1915 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1918 /* The network device supports multicast using two tables:
1919 * 1) Special Multicast Table for MAC addresses of the form
1920 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1921 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1922 * Table entries in the DA-Filter table.
1923 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1924 * is used as an index to the Other Multicast Table entries in the
1927 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1930 unsigned char crc_result = 0;
1932 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1933 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1937 crc_result = mvneta_addr_crc(p_addr);
1939 if (pp->mcast_count[crc_result] == 0) {
1940 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1945 pp->mcast_count[crc_result]--;
1946 if (pp->mcast_count[crc_result] != 0) {
1947 netdev_info(pp->dev,
1948 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1949 pp->mcast_count[crc_result], crc_result);
1953 pp->mcast_count[crc_result]++;
1955 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1960 /* Configure Fitering mode of Ethernet port */
1961 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1964 u32 port_cfg_reg, val;
1966 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1968 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
1970 /* Set / Clear UPM bit in port configuration register */
1972 /* Accept all Unicast addresses */
1973 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
1974 val |= MVNETA_FORCE_UNI;
1975 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
1976 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
1978 /* Reject all Unicast addresses */
1979 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
1980 val &= ~MVNETA_FORCE_UNI;
1983 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
1984 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
1987 /* register unicast and multicast addresses */
1988 static void mvneta_set_rx_mode(struct net_device *dev)
1990 struct mvneta_port *pp = netdev_priv(dev);
1991 struct netdev_hw_addr *ha;
1993 if (dev->flags & IFF_PROMISC) {
1994 /* Accept all: Multicast + Unicast */
1995 mvneta_rx_unicast_promisc_set(pp, 1);
1996 mvneta_set_ucast_table(pp, rxq_def);
1997 mvneta_set_special_mcast_table(pp, rxq_def);
1998 mvneta_set_other_mcast_table(pp, rxq_def);
2000 /* Accept single Unicast */
2001 mvneta_rx_unicast_promisc_set(pp, 0);
2002 mvneta_set_ucast_table(pp, -1);
2003 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2005 if (dev->flags & IFF_ALLMULTI) {
2006 /* Accept all multicast */
2007 mvneta_set_special_mcast_table(pp, rxq_def);
2008 mvneta_set_other_mcast_table(pp, rxq_def);
2010 /* Accept only initialized multicast */
2011 mvneta_set_special_mcast_table(pp, -1);
2012 mvneta_set_other_mcast_table(pp, -1);
2014 if (!netdev_mc_empty(dev)) {
2015 netdev_for_each_mc_addr(ha, dev) {
2016 mvneta_mcast_addr_set(pp, ha->addr,
2024 /* Interrupt handling - the callback for request_irq() */
2025 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2027 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
2029 /* Mask all interrupts */
2030 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2032 napi_schedule(&pp->napi);
2038 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2039 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2040 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2041 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2042 * Each CPU has its own causeRxTx register
2044 static int mvneta_poll(struct napi_struct *napi, int budget)
2048 unsigned long flags;
2049 struct mvneta_port *pp = netdev_priv(napi->dev);
2051 if (!netif_running(pp->dev)) {
2052 napi_complete(napi);
2056 /* Read cause register */
2057 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
2058 (MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
2060 /* Release Tx descriptors */
2061 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2062 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2063 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2066 /* For the case where the last mvneta_poll did not process all
2069 cause_rx_tx |= pp->cause_rx_tx;
2070 if (rxq_number > 1) {
2071 while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) {
2073 struct mvneta_rx_queue *rxq;
2074 /* get rx queue number from cause_rx_tx */
2075 rxq = mvneta_rx_policy(pp, cause_rx_tx);
2079 /* process the packet in that rx queue */
2080 count = mvneta_rx(pp, budget, rxq);
2084 /* set off the rx bit of the
2085 * corresponding bit in the cause rx
2086 * tx register, so that next iteration
2087 * will find the next rx queue where
2088 * packets are received on
2090 cause_rx_tx &= ~((1 << rxq->id) << 8);
2094 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
2100 napi_complete(napi);
2101 local_irq_save(flags);
2102 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2103 MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
2104 local_irq_restore(flags);
2107 pp->cause_rx_tx = cause_rx_tx;
2111 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2112 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2117 for (i = 0; i < num; i++) {
2118 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2119 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2120 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2121 __func__, rxq->id, i, num);
2126 /* Add this number of RX descriptors as non occupied (ready to
2129 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2134 /* Free all packets pending transmit from all TXQs and reset TX port */
2135 static void mvneta_tx_reset(struct mvneta_port *pp)
2139 /* free the skb's in the tx ring */
2140 for (queue = 0; queue < txq_number; queue++)
2141 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2143 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2144 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2147 static void mvneta_rx_reset(struct mvneta_port *pp)
2149 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2150 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2153 /* Rx/Tx queue initialization/cleanup methods */
2155 /* Create a specified RX queue */
2156 static int mvneta_rxq_init(struct mvneta_port *pp,
2157 struct mvneta_rx_queue *rxq)
2160 rxq->size = pp->rx_ring_size;
2162 /* Allocate memory for RX descriptors */
2163 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2164 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2165 &rxq->descs_phys, GFP_KERNEL);
2166 if (rxq->descs == NULL)
2169 BUG_ON(rxq->descs !=
2170 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2172 rxq->last_desc = rxq->size - 1;
2174 /* Set Rx descriptors queue starting address */
2175 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2176 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2179 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2181 /* Set coalescing pkts and time */
2182 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2183 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2185 /* Fill RXQ with buffers from RX pool */
2186 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2187 mvneta_rxq_bm_disable(pp, rxq);
2188 mvneta_rxq_fill(pp, rxq, rxq->size);
2193 /* Cleanup Rx queue */
2194 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2195 struct mvneta_rx_queue *rxq)
2197 mvneta_rxq_drop_pkts(pp, rxq);
2200 dma_free_coherent(pp->dev->dev.parent,
2201 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2207 rxq->next_desc_to_proc = 0;
2208 rxq->descs_phys = 0;
2211 /* Create and initialize a tx queue */
2212 static int mvneta_txq_init(struct mvneta_port *pp,
2213 struct mvneta_tx_queue *txq)
2215 txq->size = pp->tx_ring_size;
2217 /* A queue must always have room for at least one skb.
2218 * Therefore, stop the queue when the free entries reaches
2219 * the maximum number of descriptors per skb.
2221 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2222 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2225 /* Allocate memory for TX descriptors */
2226 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2227 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2228 &txq->descs_phys, GFP_KERNEL);
2229 if (txq->descs == NULL)
2232 /* Make sure descriptor address is cache line size aligned */
2233 BUG_ON(txq->descs !=
2234 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2236 txq->last_desc = txq->size - 1;
2238 /* Set maximum bandwidth for enabled TXQs */
2239 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2240 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2242 /* Set Tx descriptors queue starting address */
2243 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2244 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2246 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2247 if (txq->tx_skb == NULL) {
2248 dma_free_coherent(pp->dev->dev.parent,
2249 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2250 txq->descs, txq->descs_phys);
2254 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2255 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2256 txq->size * TSO_HEADER_SIZE,
2257 &txq->tso_hdrs_phys, GFP_KERNEL);
2258 if (txq->tso_hdrs == NULL) {
2260 dma_free_coherent(pp->dev->dev.parent,
2261 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2262 txq->descs, txq->descs_phys);
2265 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2270 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2271 static void mvneta_txq_deinit(struct mvneta_port *pp,
2272 struct mvneta_tx_queue *txq)
2277 dma_free_coherent(pp->dev->dev.parent,
2278 txq->size * TSO_HEADER_SIZE,
2279 txq->tso_hdrs, txq->tso_hdrs_phys);
2281 dma_free_coherent(pp->dev->dev.parent,
2282 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2283 txq->descs, txq->descs_phys);
2287 txq->next_desc_to_proc = 0;
2288 txq->descs_phys = 0;
2290 /* Set minimum bandwidth for disabled TXQs */
2291 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2292 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2294 /* Set Tx descriptors queue starting address and size */
2295 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2296 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2299 /* Cleanup all Tx queues */
2300 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2304 for (queue = 0; queue < txq_number; queue++)
2305 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2308 /* Cleanup all Rx queues */
2309 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2313 for (queue = 0; queue < rxq_number; queue++)
2314 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2318 /* Init all Rx queues */
2319 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2323 for (queue = 0; queue < rxq_number; queue++) {
2324 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2326 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2328 mvneta_cleanup_rxqs(pp);
2336 /* Init all tx queues */
2337 static int mvneta_setup_txqs(struct mvneta_port *pp)
2341 for (queue = 0; queue < txq_number; queue++) {
2342 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2344 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2346 mvneta_cleanup_txqs(pp);
2354 static void mvneta_start_dev(struct mvneta_port *pp)
2356 mvneta_max_rx_size_set(pp, pp->pkt_size);
2357 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2359 /* start the Rx/Tx activity */
2360 mvneta_port_enable(pp);
2362 /* Enable polling on the port */
2363 napi_enable(&pp->napi);
2365 /* Unmask interrupts */
2366 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2367 MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
2369 phy_start(pp->phy_dev);
2370 netif_tx_start_all_queues(pp->dev);
2373 static void mvneta_stop_dev(struct mvneta_port *pp)
2375 phy_stop(pp->phy_dev);
2377 napi_disable(&pp->napi);
2379 netif_carrier_off(pp->dev);
2381 mvneta_port_down(pp);
2382 netif_tx_stop_all_queues(pp->dev);
2384 /* Stop the port activity */
2385 mvneta_port_disable(pp);
2387 /* Clear all ethernet port interrupts */
2388 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2389 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2391 /* Mask all ethernet port interrupts */
2392 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2393 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2394 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2396 mvneta_tx_reset(pp);
2397 mvneta_rx_reset(pp);
2400 /* Return positive if MTU is valid */
2401 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2404 netdev_err(dev, "cannot change mtu to less than 68\n");
2408 /* 9676 == 9700 - 20 and rounding to 8 */
2410 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2414 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2415 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2416 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2417 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2423 /* Change the device mtu */
2424 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2426 struct mvneta_port *pp = netdev_priv(dev);
2429 mtu = mvneta_check_mtu_valid(dev, mtu);
2435 if (!netif_running(dev))
2438 /* The interface is running, so we have to force a
2439 * reallocation of the queues
2441 mvneta_stop_dev(pp);
2443 mvneta_cleanup_txqs(pp);
2444 mvneta_cleanup_rxqs(pp);
2446 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
2447 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2448 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2450 ret = mvneta_setup_rxqs(pp);
2452 netdev_err(dev, "unable to setup rxqs after MTU change\n");
2456 ret = mvneta_setup_txqs(pp);
2458 netdev_err(dev, "unable to setup txqs after MTU change\n");
2462 mvneta_start_dev(pp);
2468 /* Get mac address */
2469 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2471 u32 mac_addr_l, mac_addr_h;
2473 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2474 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2475 addr[0] = (mac_addr_h >> 24) & 0xFF;
2476 addr[1] = (mac_addr_h >> 16) & 0xFF;
2477 addr[2] = (mac_addr_h >> 8) & 0xFF;
2478 addr[3] = mac_addr_h & 0xFF;
2479 addr[4] = (mac_addr_l >> 8) & 0xFF;
2480 addr[5] = mac_addr_l & 0xFF;
2483 /* Handle setting mac address */
2484 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2486 struct mvneta_port *pp = netdev_priv(dev);
2487 struct sockaddr *sockaddr = addr;
2490 ret = eth_prepare_mac_addr_change(dev, addr);
2493 /* Remove previous address table entry */
2494 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2496 /* Set new addr in hw */
2497 mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def);
2499 eth_commit_mac_addr_change(dev, addr);
2503 static void mvneta_adjust_link(struct net_device *ndev)
2505 struct mvneta_port *pp = netdev_priv(ndev);
2506 struct phy_device *phydev = pp->phy_dev;
2507 int status_change = 0;
2510 if ((pp->speed != phydev->speed) ||
2511 (pp->duplex != phydev->duplex)) {
2514 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2515 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2516 MVNETA_GMAC_CONFIG_GMII_SPEED |
2517 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
2518 MVNETA_GMAC_AN_SPEED_EN |
2519 MVNETA_GMAC_AN_DUPLEX_EN);
2522 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2524 if (phydev->speed == SPEED_1000)
2525 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2527 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2529 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2531 pp->duplex = phydev->duplex;
2532 pp->speed = phydev->speed;
2536 if (phydev->link != pp->link) {
2537 if (!phydev->link) {
2542 pp->link = phydev->link;
2546 if (status_change) {
2548 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2549 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
2550 MVNETA_GMAC_FORCE_LINK_DOWN);
2551 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2553 netdev_info(pp->dev, "link up\n");
2555 mvneta_port_down(pp);
2556 netdev_info(pp->dev, "link down\n");
2561 static int mvneta_mdio_probe(struct mvneta_port *pp)
2563 struct phy_device *phy_dev;
2565 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2568 netdev_err(pp->dev, "could not find the PHY\n");
2572 phy_dev->supported &= PHY_GBIT_FEATURES;
2573 phy_dev->advertising = phy_dev->supported;
2575 pp->phy_dev = phy_dev;
2583 static void mvneta_mdio_remove(struct mvneta_port *pp)
2585 phy_disconnect(pp->phy_dev);
2589 static int mvneta_open(struct net_device *dev)
2591 struct mvneta_port *pp = netdev_priv(dev);
2594 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2595 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2596 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2598 ret = mvneta_setup_rxqs(pp);
2602 ret = mvneta_setup_txqs(pp);
2604 goto err_cleanup_rxqs;
2606 /* Connect to port interrupt line */
2607 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2608 MVNETA_DRIVER_NAME, pp);
2610 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2611 goto err_cleanup_txqs;
2614 /* In default link is down */
2615 netif_carrier_off(pp->dev);
2617 ret = mvneta_mdio_probe(pp);
2619 netdev_err(dev, "cannot probe MDIO bus\n");
2623 mvneta_start_dev(pp);
2628 free_irq(pp->dev->irq, pp);
2630 mvneta_cleanup_txqs(pp);
2632 mvneta_cleanup_rxqs(pp);
2636 /* Stop the port, free port interrupt line */
2637 static int mvneta_stop(struct net_device *dev)
2639 struct mvneta_port *pp = netdev_priv(dev);
2641 mvneta_stop_dev(pp);
2642 mvneta_mdio_remove(pp);
2643 free_irq(dev->irq, pp);
2644 mvneta_cleanup_rxqs(pp);
2645 mvneta_cleanup_txqs(pp);
2650 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2652 struct mvneta_port *pp = netdev_priv(dev);
2658 ret = phy_mii_ioctl(pp->phy_dev, ifr, cmd);
2660 mvneta_adjust_link(dev);
2665 /* Ethtool methods */
2667 /* Get settings (phy address, speed) for ethtools */
2668 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2670 struct mvneta_port *pp = netdev_priv(dev);
2675 return phy_ethtool_gset(pp->phy_dev, cmd);
2678 /* Set settings (phy address, speed) for ethtools */
2679 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2681 struct mvneta_port *pp = netdev_priv(dev);
2686 return phy_ethtool_sset(pp->phy_dev, cmd);
2689 /* Set interrupt coalescing for ethtools */
2690 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2691 struct ethtool_coalesce *c)
2693 struct mvneta_port *pp = netdev_priv(dev);
2696 for (queue = 0; queue < rxq_number; queue++) {
2697 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2698 rxq->time_coal = c->rx_coalesce_usecs;
2699 rxq->pkts_coal = c->rx_max_coalesced_frames;
2700 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2701 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2704 for (queue = 0; queue < txq_number; queue++) {
2705 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2706 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2707 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2713 /* get coalescing for ethtools */
2714 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2715 struct ethtool_coalesce *c)
2717 struct mvneta_port *pp = netdev_priv(dev);
2719 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2720 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2722 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2727 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2728 struct ethtool_drvinfo *drvinfo)
2730 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2731 sizeof(drvinfo->driver));
2732 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2733 sizeof(drvinfo->version));
2734 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2735 sizeof(drvinfo->bus_info));
2739 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2740 struct ethtool_ringparam *ring)
2742 struct mvneta_port *pp = netdev_priv(netdev);
2744 ring->rx_max_pending = MVNETA_MAX_RXD;
2745 ring->tx_max_pending = MVNETA_MAX_TXD;
2746 ring->rx_pending = pp->rx_ring_size;
2747 ring->tx_pending = pp->tx_ring_size;
2750 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2751 struct ethtool_ringparam *ring)
2753 struct mvneta_port *pp = netdev_priv(dev);
2755 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2757 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2758 ring->rx_pending : MVNETA_MAX_RXD;
2760 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
2761 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
2762 if (pp->tx_ring_size != ring->tx_pending)
2763 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2764 pp->tx_ring_size, ring->tx_pending);
2766 if (netif_running(dev)) {
2768 if (mvneta_open(dev)) {
2770 "error on opening device after ring param change\n");
2778 static const struct net_device_ops mvneta_netdev_ops = {
2779 .ndo_open = mvneta_open,
2780 .ndo_stop = mvneta_stop,
2781 .ndo_start_xmit = mvneta_tx,
2782 .ndo_set_rx_mode = mvneta_set_rx_mode,
2783 .ndo_set_mac_address = mvneta_set_mac_addr,
2784 .ndo_change_mtu = mvneta_change_mtu,
2785 .ndo_get_stats64 = mvneta_get_stats64,
2786 .ndo_do_ioctl = mvneta_ioctl,
2789 const struct ethtool_ops mvneta_eth_tool_ops = {
2790 .get_link = ethtool_op_get_link,
2791 .get_settings = mvneta_ethtool_get_settings,
2792 .set_settings = mvneta_ethtool_set_settings,
2793 .set_coalesce = mvneta_ethtool_set_coalesce,
2794 .get_coalesce = mvneta_ethtool_get_coalesce,
2795 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2796 .get_ringparam = mvneta_ethtool_get_ringparam,
2797 .set_ringparam = mvneta_ethtool_set_ringparam,
2801 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
2806 mvneta_port_disable(pp);
2808 /* Set port default values */
2809 mvneta_defaults_set(pp);
2811 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
2816 /* Initialize TX descriptor rings */
2817 for (queue = 0; queue < txq_number; queue++) {
2818 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2820 txq->size = pp->tx_ring_size;
2821 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2824 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
2829 /* Create Rx descriptor rings */
2830 for (queue = 0; queue < rxq_number; queue++) {
2831 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2833 rxq->size = pp->rx_ring_size;
2834 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2835 rxq->time_coal = MVNETA_RX_COAL_USEC;
2841 /* platform glue : initialize decoding windows */
2842 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2843 const struct mbus_dram_target_info *dram)
2849 for (i = 0; i < 6; i++) {
2850 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2851 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2854 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2860 for (i = 0; i < dram->num_cs; i++) {
2861 const struct mbus_dram_window *cs = dram->cs + i;
2862 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2863 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2865 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2866 (cs->size - 1) & 0xffff0000);
2868 win_enable &= ~(1 << i);
2869 win_protect |= 3 << (2 * i);
2872 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2875 /* Power up the port */
2876 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2880 /* MAC Cause register should be cleared */
2881 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2883 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2885 /* Even though it might look weird, when we're configured in
2886 * SGMII or QSGMII mode, the RGMII bit needs to be set.
2889 case PHY_INTERFACE_MODE_QSGMII:
2890 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
2891 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
2893 case PHY_INTERFACE_MODE_SGMII:
2894 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
2895 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
2897 case PHY_INTERFACE_MODE_RGMII:
2898 case PHY_INTERFACE_MODE_RGMII_ID:
2899 ctrl |= MVNETA_GMAC2_PORT_RGMII;
2905 /* Cancel Port Reset */
2906 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
2907 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
2909 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2910 MVNETA_GMAC2_PORT_RESET) != 0)
2916 /* Device initialization routine */
2917 static int mvneta_probe(struct platform_device *pdev)
2919 const struct mbus_dram_target_info *dram_target_info;
2920 struct resource *res;
2921 struct device_node *dn = pdev->dev.of_node;
2922 struct device_node *phy_node;
2923 struct mvneta_port *pp;
2924 struct net_device *dev;
2925 const char *dt_mac_addr;
2926 char hw_mac_addr[ETH_ALEN];
2927 const char *mac_from;
2931 /* Our multiqueue support is not complete, so for now, only
2932 * allow the usage of the first RX queue
2935 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
2939 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
2943 dev->irq = irq_of_parse_and_map(dn, 0);
2944 if (dev->irq == 0) {
2946 goto err_free_netdev;
2949 phy_node = of_parse_phandle(dn, "phy", 0);
2951 if (!of_phy_is_fixed_link(dn)) {
2952 dev_err(&pdev->dev, "no PHY specified\n");
2957 err = of_phy_register_fixed_link(dn);
2959 dev_err(&pdev->dev, "cannot register fixed PHY\n");
2963 /* In the case of a fixed PHY, the DT node associated
2964 * to the PHY is the Ethernet MAC DT node.
2969 phy_mode = of_get_phy_mode(dn);
2971 dev_err(&pdev->dev, "incorrect phy-mode\n");
2976 dev->tx_queue_len = MVNETA_MAX_TXD;
2977 dev->watchdog_timeo = 5 * HZ;
2978 dev->netdev_ops = &mvneta_netdev_ops;
2980 dev->ethtool_ops = &mvneta_eth_tool_ops;
2982 pp = netdev_priv(dev);
2983 pp->phy_node = phy_node;
2984 pp->phy_interface = phy_mode;
2986 pp->clk = devm_clk_get(&pdev->dev, NULL);
2987 if (IS_ERR(pp->clk)) {
2988 err = PTR_ERR(pp->clk);
2992 clk_prepare_enable(pp->clk);
2994 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2995 pp->base = devm_ioremap_resource(&pdev->dev, res);
2996 if (IS_ERR(pp->base)) {
2997 err = PTR_ERR(pp->base);
3001 /* Alloc per-cpu stats */
3002 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
3008 dt_mac_addr = of_get_mac_address(dn);
3010 mac_from = "device tree";
3011 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
3013 mvneta_get_mac_addr(pp, hw_mac_addr);
3014 if (is_valid_ether_addr(hw_mac_addr)) {
3015 mac_from = "hardware";
3016 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
3018 mac_from = "random";
3019 eth_hw_addr_random(dev);
3023 pp->tx_ring_size = MVNETA_MAX_TXD;
3024 pp->rx_ring_size = MVNETA_MAX_RXD;
3027 SET_NETDEV_DEV(dev, &pdev->dev);
3029 err = mvneta_init(&pdev->dev, pp);
3031 goto err_free_stats;
3033 err = mvneta_port_power_up(pp, phy_mode);
3035 dev_err(&pdev->dev, "can't power up port\n");
3036 goto err_free_stats;
3039 dram_target_info = mv_mbus_dram_info();
3040 if (dram_target_info)
3041 mvneta_conf_mbus_windows(pp, dram_target_info);
3043 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
3045 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3046 dev->hw_features |= dev->features;
3047 dev->vlan_features |= dev->features;
3048 dev->priv_flags |= IFF_UNICAST_FLT;
3049 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
3051 err = register_netdev(dev);
3053 dev_err(&pdev->dev, "failed to register\n");
3054 goto err_free_stats;
3057 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
3060 platform_set_drvdata(pdev, pp->dev);
3065 free_percpu(pp->stats);
3067 clk_disable_unprepare(pp->clk);
3069 irq_dispose_mapping(dev->irq);
3075 /* Device removal routine */
3076 static int mvneta_remove(struct platform_device *pdev)
3078 struct net_device *dev = platform_get_drvdata(pdev);
3079 struct mvneta_port *pp = netdev_priv(dev);
3081 unregister_netdev(dev);
3082 clk_disable_unprepare(pp->clk);
3083 free_percpu(pp->stats);
3084 irq_dispose_mapping(dev->irq);
3090 static const struct of_device_id mvneta_match[] = {
3091 { .compatible = "marvell,armada-370-neta" },
3094 MODULE_DEVICE_TABLE(of, mvneta_match);
3096 static struct platform_driver mvneta_driver = {
3097 .probe = mvneta_probe,
3098 .remove = mvneta_remove,
3100 .name = MVNETA_DRIVER_NAME,
3101 .of_match_table = mvneta_match,
3105 module_platform_driver(mvneta_driver);
3107 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
3108 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
3109 MODULE_LICENSE("GPL");
3111 module_param(rxq_number, int, S_IRUGO);
3112 module_param(txq_number, int, S_IRUGO);
3114 module_param(rxq_def, int, S_IRUGO);
3115 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);