2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_address.h>
30 #include <linux/phy.h>
31 #include <linux/clk.h>
34 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
35 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
36 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
37 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
38 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
39 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
40 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
41 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
42 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
43 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
44 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
45 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
46 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
47 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
48 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
49 #define MVNETA_PORT_RX_RESET 0x1cc0
50 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
51 #define MVNETA_PHY_ADDR 0x2000
52 #define MVNETA_PHY_ADDR_MASK 0x1f
53 #define MVNETA_MBUS_RETRY 0x2010
54 #define MVNETA_UNIT_INTR_CAUSE 0x2080
55 #define MVNETA_UNIT_CONTROL 0x20B0
56 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
57 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
58 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
59 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
60 #define MVNETA_BASE_ADDR_ENABLE 0x2290
61 #define MVNETA_PORT_CONFIG 0x2400
62 #define MVNETA_UNI_PROMISC_MODE BIT(0)
63 #define MVNETA_DEF_RXQ(q) ((q) << 1)
64 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
65 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
66 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
67 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
68 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
69 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
70 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
71 MVNETA_DEF_RXQ_ARP(q) | \
72 MVNETA_DEF_RXQ_TCP(q) | \
73 MVNETA_DEF_RXQ_UDP(q) | \
74 MVNETA_DEF_RXQ_BPDU(q) | \
75 MVNETA_TX_UNSET_ERR_SUM | \
76 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
77 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
78 #define MVNETA_MAC_ADDR_LOW 0x2414
79 #define MVNETA_MAC_ADDR_HIGH 0x2418
80 #define MVNETA_SDMA_CONFIG 0x241c
81 #define MVNETA_SDMA_BRST_SIZE_16 4
82 #define MVNETA_NO_DESC_SWAP 0x0
83 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
84 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
85 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
86 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
87 #define MVNETA_PORT_STATUS 0x2444
88 #define MVNETA_TX_IN_PRGRS BIT(1)
89 #define MVNETA_TX_FIFO_EMPTY BIT(8)
90 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
91 #define MVNETA_TYPE_PRIO 0x24bc
92 #define MVNETA_FORCE_UNI BIT(21)
93 #define MVNETA_TXQ_CMD_1 0x24e4
94 #define MVNETA_TXQ_CMD 0x2448
95 #define MVNETA_TXQ_DISABLE_SHIFT 8
96 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
97 #define MVNETA_ACC_MODE 0x2500
98 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
99 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
100 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
101 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
102 #define MVNETA_INTR_NEW_CAUSE 0x25a0
103 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
104 #define MVNETA_INTR_NEW_MASK 0x25a4
105 #define MVNETA_INTR_OLD_CAUSE 0x25a8
106 #define MVNETA_INTR_OLD_MASK 0x25ac
107 #define MVNETA_INTR_MISC_CAUSE 0x25b0
108 #define MVNETA_INTR_MISC_MASK 0x25b4
109 #define MVNETA_INTR_ENABLE 0x25b8
110 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
111 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000
112 #define MVNETA_RXQ_CMD 0x2680
113 #define MVNETA_RXQ_DISABLE_SHIFT 8
114 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
115 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
116 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
117 #define MVNETA_GMAC_CTRL_0 0x2c00
118 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
119 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
120 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
121 #define MVNETA_GMAC_CTRL_2 0x2c08
122 #define MVNETA_GMAC2_PSC_ENABLE BIT(3)
123 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
124 #define MVNETA_GMAC2_PORT_RESET BIT(6)
125 #define MVNETA_GMAC_STATUS 0x2c10
126 #define MVNETA_GMAC_LINK_UP BIT(0)
127 #define MVNETA_GMAC_SPEED_1000 BIT(1)
128 #define MVNETA_GMAC_SPEED_100 BIT(2)
129 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
130 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
131 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
132 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
133 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
134 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
135 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
136 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
137 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
138 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
139 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
140 #define MVNETA_MIB_COUNTERS_BASE 0x3080
141 #define MVNETA_MIB_LATE_COLLISION 0x7c
142 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
143 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
144 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
145 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
146 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
147 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
148 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
149 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
150 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
151 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
152 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
153 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
154 #define MVNETA_PORT_TX_RESET 0x3cf0
155 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
156 #define MVNETA_TX_MTU 0x3e0c
157 #define MVNETA_TX_TOKEN_SIZE 0x3e14
158 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
159 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
160 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
162 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
164 /* Descriptor ring Macros */
165 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
166 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
168 /* Various constants */
171 #define MVNETA_TXDONE_COAL_PKTS 16
172 #define MVNETA_RX_COAL_PKTS 32
173 #define MVNETA_RX_COAL_USEC 100
176 #define MVNETA_TX_DONE_TIMER_PERIOD 10
178 /* Napi polling weight */
179 #define MVNETA_RX_POLL_WEIGHT 64
181 /* The two bytes Marvell header. Either contains a special value used
182 * by Marvell switches when a specific hardware mode is enabled (not
183 * supported by this driver) or is filled automatically by zeroes on
184 * the RX side. Those two bytes being at the front of the Ethernet
185 * header, they allow to have the IP header aligned on a 4 bytes
186 * boundary automatically: the hardware skips those two bytes on its
189 #define MVNETA_MH_SIZE 2
191 #define MVNETA_VLAN_TAG_LEN 4
193 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
194 #define MVNETA_TX_CSUM_MAX_SIZE 9800
195 #define MVNETA_ACC_MODE_EXT 1
197 /* Timeout constants */
198 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
199 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
200 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
202 #define MVNETA_TX_MTU_MAX 0x3ffff
204 /* Max number of Rx descriptors */
205 #define MVNETA_MAX_RXD 128
207 /* Max number of Tx descriptors */
208 #define MVNETA_MAX_TXD 532
210 /* descriptor aligned size */
211 #define MVNETA_DESC_ALIGNED_SIZE 32
213 #define MVNETA_RX_PKT_SIZE(mtu) \
214 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
215 ETH_HLEN + ETH_FCS_LEN, \
216 MVNETA_CPU_D_CACHE_LINE_SIZE)
218 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
220 struct mvneta_stats {
221 struct u64_stats_sync syncp;
229 struct mvneta_rx_queue *rxqs;
230 struct mvneta_tx_queue *txqs;
231 struct timer_list tx_done_timer;
232 struct net_device *dev;
235 struct napi_struct napi;
239 #define MVNETA_F_TX_DONE_TIMER_BIT 0
249 struct mvneta_stats tx_stats;
250 struct mvneta_stats rx_stats;
252 struct mii_bus *mii_bus;
253 struct phy_device *phy_dev;
254 phy_interface_t phy_interface;
255 struct device_node *phy_node;
261 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
262 * layout of the transmit and reception DMA descriptors, and their
263 * layout is therefore defined by the hardware design
265 struct mvneta_tx_desc {
266 u32 command; /* Options used by HW for packet transmitting.*/
267 #define MVNETA_TX_L3_OFF_SHIFT 0
268 #define MVNETA_TX_IP_HLEN_SHIFT 8
269 #define MVNETA_TX_L4_UDP BIT(16)
270 #define MVNETA_TX_L3_IP6 BIT(17)
271 #define MVNETA_TXD_IP_CSUM BIT(18)
272 #define MVNETA_TXD_Z_PAD BIT(19)
273 #define MVNETA_TXD_L_DESC BIT(20)
274 #define MVNETA_TXD_F_DESC BIT(21)
275 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
276 MVNETA_TXD_L_DESC | \
278 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
279 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
281 u16 reserverd1; /* csum_l4 (for future use) */
282 u16 data_size; /* Data size of transmitted packet in bytes */
283 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
284 u32 reserved2; /* hw_cmd - (for future use, PMT) */
285 u32 reserved3[4]; /* Reserved - (for future use) */
288 struct mvneta_rx_desc {
289 u32 status; /* Info about received packet */
290 #define MVNETA_RXD_ERR_CRC 0x0
291 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
292 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
293 #define MVNETA_RXD_ERR_LEN BIT(18)
294 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
295 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
296 #define MVNETA_RXD_L3_IP4 BIT(25)
297 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
298 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
300 u16 reserved1; /* pnc_info - (for future use, PnC) */
301 u16 data_size; /* Size of received packet in bytes */
302 u32 buf_phys_addr; /* Physical address of the buffer */
303 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
304 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
305 u16 reserved3; /* prefetch_cmd, for future use */
306 u16 reserved4; /* csum_l4 - (for future use, PnC) */
307 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
308 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
311 struct mvneta_tx_queue {
312 /* Number of this TX queue, in the range 0-7 */
315 /* Number of TX DMA descriptors in the descriptor ring */
318 /* Number of currently used TX DMA descriptor in the
323 /* Array of transmitted skb */
324 struct sk_buff **tx_skb;
326 /* Index of last TX DMA descriptor that was inserted */
329 /* Index of the TX DMA descriptor to be cleaned up */
334 /* Virtual address of the TX DMA descriptors array */
335 struct mvneta_tx_desc *descs;
337 /* DMA address of the TX DMA descriptors array */
338 dma_addr_t descs_phys;
340 /* Index of the last TX DMA descriptor */
343 /* Index of the next TX DMA descriptor to process */
344 int next_desc_to_proc;
347 struct mvneta_rx_queue {
348 /* rx queue number, in the range 0-7 */
351 /* num of rx descriptors in the rx descriptor ring */
354 /* counter of times when mvneta_refill() failed */
360 /* Virtual address of the RX DMA descriptors array */
361 struct mvneta_rx_desc *descs;
363 /* DMA address of the RX DMA descriptors array */
364 dma_addr_t descs_phys;
366 /* Index of the last RX DMA descriptor */
369 /* Index of the next RX DMA descriptor to process */
370 int next_desc_to_proc;
373 static int rxq_number = 8;
374 static int txq_number = 8;
379 #define MVNETA_DRIVER_NAME "mvneta"
380 #define MVNETA_DRIVER_VERSION "1.0"
382 /* Utility/helper methods */
384 /* Write helper method */
385 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
387 writel(data, pp->base + offset);
390 /* Read helper method */
391 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
393 return readl(pp->base + offset);
396 /* Increment txq get counter */
397 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
399 txq->txq_get_index++;
400 if (txq->txq_get_index == txq->size)
401 txq->txq_get_index = 0;
404 /* Increment txq put counter */
405 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
407 txq->txq_put_index++;
408 if (txq->txq_put_index == txq->size)
409 txq->txq_put_index = 0;
413 /* Clear all MIB counters */
414 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
419 /* Perform dummy reads from MIB counters */
420 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
421 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
424 /* Get System Network Statistics */
425 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
426 struct rtnl_link_stats64 *stats)
428 struct mvneta_port *pp = netdev_priv(dev);
431 memset(stats, 0, sizeof(struct rtnl_link_stats64));
434 start = u64_stats_fetch_begin_bh(&pp->rx_stats.syncp);
435 stats->rx_packets = pp->rx_stats.packets;
436 stats->rx_bytes = pp->rx_stats.bytes;
437 } while (u64_stats_fetch_retry_bh(&pp->rx_stats.syncp, start));
441 start = u64_stats_fetch_begin_bh(&pp->tx_stats.syncp);
442 stats->tx_packets = pp->tx_stats.packets;
443 stats->tx_bytes = pp->tx_stats.bytes;
444 } while (u64_stats_fetch_retry_bh(&pp->tx_stats.syncp, start));
446 stats->rx_errors = dev->stats.rx_errors;
447 stats->rx_dropped = dev->stats.rx_dropped;
449 stats->tx_dropped = dev->stats.tx_dropped;
454 /* Rx descriptors helper methods */
456 /* Checks whether the given RX descriptor is both the first and the
457 * last descriptor for the RX packet. Each RX packet is currently
458 * received through a single RX descriptor, so not having each RX
459 * descriptor with its first and last bits set is an error
461 static int mvneta_rxq_desc_is_first_last(struct mvneta_rx_desc *desc)
463 return (desc->status & MVNETA_RXD_FIRST_LAST_DESC) ==
464 MVNETA_RXD_FIRST_LAST_DESC;
467 /* Add number of descriptors ready to receive new packets */
468 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
469 struct mvneta_rx_queue *rxq,
472 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
475 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
476 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
477 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
478 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
479 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
482 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
483 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
486 /* Get number of RX descriptors occupied by received packets */
487 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
488 struct mvneta_rx_queue *rxq)
492 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
493 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
496 /* Update num of rx desc called upon return from rx path or
497 * from mvneta_rxq_drop_pkts().
499 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
500 struct mvneta_rx_queue *rxq,
501 int rx_done, int rx_filled)
505 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
507 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
508 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
512 /* Only 255 descriptors can be added at once */
513 while ((rx_done > 0) || (rx_filled > 0)) {
514 if (rx_done <= 0xff) {
521 if (rx_filled <= 0xff) {
522 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
525 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
528 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
532 /* Get pointer to next RX descriptor to be processed by SW */
533 static struct mvneta_rx_desc *
534 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
536 int rx_desc = rxq->next_desc_to_proc;
538 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
539 return rxq->descs + rx_desc;
542 /* Change maximum receive size of the port. */
543 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
547 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
548 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
549 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
550 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
551 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
555 /* Set rx queue offset */
556 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
557 struct mvneta_rx_queue *rxq,
562 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
563 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
566 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
567 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
571 /* Tx descriptors helper methods */
573 /* Update HW with number of TX descriptors to be sent */
574 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
575 struct mvneta_tx_queue *txq,
580 /* Only 255 descriptors can be added at once ; Assume caller
581 * process TX desriptors in quanta less than 256
584 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
587 /* Get pointer to next TX descriptor to be processed (send) by HW */
588 static struct mvneta_tx_desc *
589 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
591 int tx_desc = txq->next_desc_to_proc;
593 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
594 return txq->descs + tx_desc;
597 /* Release the last allocated TX descriptor. Useful to handle DMA
598 * mapping failures in the TX path.
600 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
602 if (txq->next_desc_to_proc == 0)
603 txq->next_desc_to_proc = txq->last_desc - 1;
605 txq->next_desc_to_proc--;
608 /* Set rxq buf size */
609 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
610 struct mvneta_rx_queue *rxq,
615 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
617 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
618 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
620 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
623 /* Disable buffer management (BM) */
624 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
625 struct mvneta_rx_queue *rxq)
629 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
630 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
631 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
636 /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */
637 static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable)
641 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
644 val |= MVNETA_GMAC2_PORT_RGMII;
646 val &= ~MVNETA_GMAC2_PORT_RGMII;
648 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
651 /* Config SGMII port */
652 static void mvneta_port_sgmii_config(struct mvneta_port *pp)
656 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
657 val |= MVNETA_GMAC2_PSC_ENABLE;
658 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
661 /* Start the Ethernet port RX and TX activity */
662 static void mvneta_port_up(struct mvneta_port *pp)
667 /* Enable all initialized TXs. */
668 mvneta_mib_counters_clear(pp);
670 for (queue = 0; queue < txq_number; queue++) {
671 struct mvneta_tx_queue *txq = &pp->txqs[queue];
672 if (txq->descs != NULL)
673 q_map |= (1 << queue);
675 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
677 /* Enable all initialized RXQs. */
679 for (queue = 0; queue < rxq_number; queue++) {
680 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
681 if (rxq->descs != NULL)
682 q_map |= (1 << queue);
685 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
688 /* Stop the Ethernet port activity */
689 static void mvneta_port_down(struct mvneta_port *pp)
694 /* Stop Rx port activity. Check port Rx activity. */
695 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
697 /* Issue stop command for active channels only */
699 mvreg_write(pp, MVNETA_RXQ_CMD,
700 val << MVNETA_RXQ_DISABLE_SHIFT);
702 /* Wait for all Rx activity to terminate. */
705 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
707 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
713 val = mvreg_read(pp, MVNETA_RXQ_CMD);
714 } while (val & 0xff);
716 /* Stop Tx port activity. Check port Tx activity. Issue stop
717 * command for active channels only
719 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
722 mvreg_write(pp, MVNETA_TXQ_CMD,
723 (val << MVNETA_TXQ_DISABLE_SHIFT));
725 /* Wait for all Tx activity to terminate. */
728 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
730 "TIMEOUT for TX stopped status=0x%08x\n",
736 /* Check TX Command reg that all Txqs are stopped */
737 val = mvreg_read(pp, MVNETA_TXQ_CMD);
739 } while (val & 0xff);
741 /* Double check to verify that TX FIFO is empty */
744 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
746 "TX FIFO empty timeout status=0x08%x\n",
752 val = mvreg_read(pp, MVNETA_PORT_STATUS);
753 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
754 (val & MVNETA_TX_IN_PRGRS));
759 /* Enable the port by setting the port enable bit of the MAC control register */
760 static void mvneta_port_enable(struct mvneta_port *pp)
765 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
766 val |= MVNETA_GMAC0_PORT_ENABLE;
767 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
770 /* Disable the port and wait for about 200 usec before retuning */
771 static void mvneta_port_disable(struct mvneta_port *pp)
775 /* Reset the Enable bit in the Serial Control Register */
776 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
777 val &= ~MVNETA_GMAC0_PORT_ENABLE;
778 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
783 /* Multicast tables methods */
785 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
786 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
794 val = 0x1 | (queue << 1);
795 val |= (val << 24) | (val << 16) | (val << 8);
798 for (offset = 0; offset <= 0xc; offset += 4)
799 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
802 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
803 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
811 val = 0x1 | (queue << 1);
812 val |= (val << 24) | (val << 16) | (val << 8);
815 for (offset = 0; offset <= 0xfc; offset += 4)
816 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
820 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
821 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
827 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
830 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
831 val = 0x1 | (queue << 1);
832 val |= (val << 24) | (val << 16) | (val << 8);
835 for (offset = 0; offset <= 0xfc; offset += 4)
836 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
839 /* This method sets defaults to the NETA port:
840 * Clears interrupt Cause and Mask registers.
841 * Clears all MAC tables.
842 * Sets defaults to all registers.
843 * Resets RX and TX descriptor rings.
845 * This method can be called after mvneta_port_down() to return the port
846 * settings to defaults.
848 static void mvneta_defaults_set(struct mvneta_port *pp)
854 /* Clear all Cause registers */
855 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
856 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
857 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
859 /* Mask all interrupts */
860 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
861 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
862 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
863 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
865 /* Enable MBUS Retry bit16 */
866 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
868 /* Set CPU queue access map - all CPUs have access to all RX
869 * queues and to all TX queues
871 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
872 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
873 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
874 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
876 /* Reset RX and TX DMAs */
877 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
878 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
880 /* Disable Legacy WRR, Disable EJP, Release from reset */
881 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
882 for (queue = 0; queue < txq_number; queue++) {
883 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
884 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
887 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
888 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
890 /* Set Port Acceleration Mode */
891 val = MVNETA_ACC_MODE_EXT;
892 mvreg_write(pp, MVNETA_ACC_MODE, val);
894 /* Update val of portCfg register accordingly with all RxQueue types */
895 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
896 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
899 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
900 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
902 /* Build PORT_SDMA_CONFIG_REG */
905 /* Default burst size */
906 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
907 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
909 val |= (MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP |
910 MVNETA_NO_DESC_SWAP);
912 /* Assign port SDMA configuration */
913 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
915 mvneta_set_ucast_table(pp, -1);
916 mvneta_set_special_mcast_table(pp, -1);
917 mvneta_set_other_mcast_table(pp, -1);
919 /* Set port interrupt enable register - default enable all */
920 mvreg_write(pp, MVNETA_INTR_ENABLE,
921 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
922 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
925 /* Set max sizes for tx queues */
926 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
932 mtu = max_tx_size * 8;
933 if (mtu > MVNETA_TX_MTU_MAX)
934 mtu = MVNETA_TX_MTU_MAX;
937 val = mvreg_read(pp, MVNETA_TX_MTU);
938 val &= ~MVNETA_TX_MTU_MAX;
940 mvreg_write(pp, MVNETA_TX_MTU, val);
942 /* TX token size and all TXQs token size must be larger that MTU */
943 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
945 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
948 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
950 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
952 for (queue = 0; queue < txq_number; queue++) {
953 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
955 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
958 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
960 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
965 /* Set unicast address */
966 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
969 unsigned int unicast_reg;
970 unsigned int tbl_offset;
971 unsigned int reg_offset;
973 /* Locate the Unicast table entry */
974 last_nibble = (0xf & last_nibble);
976 /* offset from unicast tbl base */
977 tbl_offset = (last_nibble / 4) * 4;
979 /* offset within the above reg */
980 reg_offset = last_nibble % 4;
982 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
985 /* Clear accepts frame bit at specified unicast DA tbl entry */
986 unicast_reg &= ~(0xff << (8 * reg_offset));
988 unicast_reg &= ~(0xff << (8 * reg_offset));
989 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
992 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
995 /* Set mac address */
996 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1003 mac_l = (addr[4] << 8) | (addr[5]);
1004 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1005 (addr[2] << 8) | (addr[3] << 0);
1007 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1008 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1011 /* Accept frames of this address */
1012 mvneta_set_ucast_addr(pp, addr[5], queue);
1015 /* Set the number of packets that will be received before RX interrupt
1016 * will be generated by HW.
1018 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1019 struct mvneta_rx_queue *rxq, u32 value)
1021 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1022 value | MVNETA_RXQ_NON_OCCUPIED(0));
1023 rxq->pkts_coal = value;
1026 /* Set the time delay in usec before RX interrupt will be generated by
1029 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1030 struct mvneta_rx_queue *rxq, u32 value)
1033 unsigned long clk_rate;
1035 clk_rate = clk_get_rate(pp->clk);
1036 val = (clk_rate / 1000000) * value;
1038 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1039 rxq->time_coal = value;
1042 /* Set threshold for TX_DONE pkts coalescing */
1043 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1044 struct mvneta_tx_queue *txq, u32 value)
1048 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1050 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1051 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1053 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1055 txq->done_pkts_coal = value;
1058 /* Trigger tx done timer in MVNETA_TX_DONE_TIMER_PERIOD msecs */
1059 static void mvneta_add_tx_done_timer(struct mvneta_port *pp)
1061 if (test_and_set_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags) == 0) {
1062 pp->tx_done_timer.expires = jiffies +
1063 msecs_to_jiffies(MVNETA_TX_DONE_TIMER_PERIOD);
1064 add_timer(&pp->tx_done_timer);
1069 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1070 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1071 u32 phys_addr, u32 cookie)
1073 rx_desc->buf_cookie = cookie;
1074 rx_desc->buf_phys_addr = phys_addr;
1077 /* Decrement sent descriptors counter */
1078 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1079 struct mvneta_tx_queue *txq,
1084 /* Only 255 TX descriptors can be updated at once */
1085 while (sent_desc > 0xff) {
1086 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1087 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1088 sent_desc = sent_desc - 0xff;
1091 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1092 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1095 /* Get number of TX descriptors already sent by HW */
1096 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1097 struct mvneta_tx_queue *txq)
1102 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1103 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1104 MVNETA_TXQ_SENT_DESC_SHIFT;
1109 /* Get number of sent descriptors and decrement counter.
1110 * The number of sent descriptors is returned.
1112 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1113 struct mvneta_tx_queue *txq)
1117 /* Get number of sent descriptors */
1118 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1120 /* Decrement sent descriptors counter */
1122 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1127 /* Set TXQ descriptors fields relevant for CSUM calculation */
1128 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1129 int ip_hdr_len, int l4_proto)
1133 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1134 * G_L4_chk, L4_type; required only for checksum
1137 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1138 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1140 if (l3_proto == swab16(ETH_P_IP))
1141 command |= MVNETA_TXD_IP_CSUM;
1143 command |= MVNETA_TX_L3_IP6;
1145 if (l4_proto == IPPROTO_TCP)
1146 command |= MVNETA_TX_L4_CSUM_FULL;
1147 else if (l4_proto == IPPROTO_UDP)
1148 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1150 command |= MVNETA_TX_L4_CSUM_NOT;
1156 /* Display more error info */
1157 static void mvneta_rx_error(struct mvneta_port *pp,
1158 struct mvneta_rx_desc *rx_desc)
1160 u32 status = rx_desc->status;
1162 if (!mvneta_rxq_desc_is_first_last(rx_desc)) {
1164 "bad rx status %08x (buffer oversize), size=%d\n",
1165 rx_desc->status, rx_desc->data_size);
1169 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1170 case MVNETA_RXD_ERR_CRC:
1171 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1172 status, rx_desc->data_size);
1174 case MVNETA_RXD_ERR_OVERRUN:
1175 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1176 status, rx_desc->data_size);
1178 case MVNETA_RXD_ERR_LEN:
1179 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1180 status, rx_desc->data_size);
1182 case MVNETA_RXD_ERR_RESOURCE:
1183 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1184 status, rx_desc->data_size);
1189 /* Handle RX checksum offload */
1190 static void mvneta_rx_csum(struct mvneta_port *pp,
1191 struct mvneta_rx_desc *rx_desc,
1192 struct sk_buff *skb)
1194 if ((rx_desc->status & MVNETA_RXD_L3_IP4) &&
1195 (rx_desc->status & MVNETA_RXD_L4_CSUM_OK)) {
1197 skb->ip_summed = CHECKSUM_UNNECESSARY;
1201 skb->ip_summed = CHECKSUM_NONE;
1204 /* Return tx queue pointer (find last set bit) according to causeTxDone reg */
1205 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1208 int queue = fls(cause) - 1;
1210 return (queue < 0 || queue >= txq_number) ? NULL : &pp->txqs[queue];
1213 /* Free tx queue skbuffs */
1214 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1215 struct mvneta_tx_queue *txq, int num)
1219 for (i = 0; i < num; i++) {
1220 struct mvneta_tx_desc *tx_desc = txq->descs +
1222 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1224 mvneta_txq_inc_get(txq);
1229 dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr,
1230 tx_desc->data_size, DMA_TO_DEVICE);
1231 dev_kfree_skb_any(skb);
1235 /* Handle end of transmission */
1236 static int mvneta_txq_done(struct mvneta_port *pp,
1237 struct mvneta_tx_queue *txq)
1239 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1242 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1245 mvneta_txq_bufs_free(pp, txq, tx_done);
1247 txq->count -= tx_done;
1249 if (netif_tx_queue_stopped(nq)) {
1250 if (txq->size - txq->count >= MAX_SKB_FRAGS + 1)
1251 netif_tx_wake_queue(nq);
1257 /* Refill processing */
1258 static int mvneta_rx_refill(struct mvneta_port *pp,
1259 struct mvneta_rx_desc *rx_desc)
1262 dma_addr_t phys_addr;
1263 struct sk_buff *skb;
1265 skb = netdev_alloc_skb(pp->dev, pp->pkt_size);
1269 phys_addr = dma_map_single(pp->dev->dev.parent, skb->head,
1270 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1272 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1277 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1282 /* Handle tx checksum */
1283 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1285 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1289 if (skb->protocol == htons(ETH_P_IP)) {
1290 struct iphdr *ip4h = ip_hdr(skb);
1292 /* Calculate IPv4 checksum and L4 checksum */
1293 ip_hdr_len = ip4h->ihl;
1294 l4_proto = ip4h->protocol;
1295 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1296 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1298 /* Read l4_protocol from one of IPv6 extra headers */
1299 if (skb_network_header_len(skb) > 0)
1300 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1301 l4_proto = ip6h->nexthdr;
1303 return MVNETA_TX_L4_CSUM_NOT;
1305 return mvneta_txq_desc_csum(skb_network_offset(skb),
1306 skb->protocol, ip_hdr_len, l4_proto);
1309 return MVNETA_TX_L4_CSUM_NOT;
1312 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1315 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1318 int queue = fls(cause >> 8) - 1;
1320 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1323 /* Drop packets received by the RXQ and free buffers */
1324 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1325 struct mvneta_rx_queue *rxq)
1329 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1330 for (i = 0; i < rxq->size; i++) {
1331 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1332 struct sk_buff *skb = (struct sk_buff *)rx_desc->buf_cookie;
1334 dev_kfree_skb_any(skb);
1335 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1336 rx_desc->data_size, DMA_FROM_DEVICE);
1340 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1343 /* Main rx processing */
1344 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1345 struct mvneta_rx_queue *rxq)
1347 struct net_device *dev = pp->dev;
1348 int rx_done, rx_filled;
1350 /* Get number of received packets */
1351 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1353 if (rx_todo > rx_done)
1359 /* Fairness NAPI loop */
1360 while (rx_done < rx_todo) {
1361 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1362 struct sk_buff *skb;
1369 rx_status = rx_desc->status;
1370 skb = (struct sk_buff *)rx_desc->buf_cookie;
1372 if (!mvneta_rxq_desc_is_first_last(rx_desc) ||
1373 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1374 dev->stats.rx_errors++;
1375 mvneta_rx_error(pp, rx_desc);
1376 mvneta_rx_desc_fill(rx_desc, rx_desc->buf_phys_addr,
1381 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1382 rx_desc->data_size, DMA_FROM_DEVICE);
1384 rx_bytes = rx_desc->data_size -
1385 (ETH_FCS_LEN + MVNETA_MH_SIZE);
1386 u64_stats_update_begin(&pp->rx_stats.syncp);
1387 pp->rx_stats.packets++;
1388 pp->rx_stats.bytes += rx_bytes;
1389 u64_stats_update_end(&pp->rx_stats.syncp);
1391 /* Linux processing */
1392 skb_reserve(skb, MVNETA_MH_SIZE);
1393 skb_put(skb, rx_bytes);
1395 skb->protocol = eth_type_trans(skb, dev);
1397 mvneta_rx_csum(pp, rx_desc, skb);
1399 napi_gro_receive(&pp->napi, skb);
1401 /* Refill processing */
1402 err = mvneta_rx_refill(pp, rx_desc);
1404 netdev_err(pp->dev, "Linux processing - Can't refill\n");
1410 /* Update rxq management counters */
1411 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1416 /* Handle tx fragmentation processing */
1417 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1418 struct mvneta_tx_queue *txq)
1420 struct mvneta_tx_desc *tx_desc;
1423 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1424 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1425 void *addr = page_address(frag->page.p) + frag->page_offset;
1427 tx_desc = mvneta_txq_next_desc_get(txq);
1428 tx_desc->data_size = frag->size;
1430 tx_desc->buf_phys_addr =
1431 dma_map_single(pp->dev->dev.parent, addr,
1432 tx_desc->data_size, DMA_TO_DEVICE);
1434 if (dma_mapping_error(pp->dev->dev.parent,
1435 tx_desc->buf_phys_addr)) {
1436 mvneta_txq_desc_put(txq);
1440 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
1441 /* Last descriptor */
1442 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1444 txq->tx_skb[txq->txq_put_index] = skb;
1446 mvneta_txq_inc_put(txq);
1448 /* Descriptor in the middle: Not First, Not Last */
1449 tx_desc->command = 0;
1451 txq->tx_skb[txq->txq_put_index] = NULL;
1452 mvneta_txq_inc_put(txq);
1459 /* Release all descriptors that were used to map fragments of
1460 * this packet, as well as the corresponding DMA mappings
1462 for (i = i - 1; i >= 0; i--) {
1463 tx_desc = txq->descs + i;
1464 dma_unmap_single(pp->dev->dev.parent,
1465 tx_desc->buf_phys_addr,
1468 mvneta_txq_desc_put(txq);
1474 /* Main tx processing */
1475 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1477 struct mvneta_port *pp = netdev_priv(dev);
1478 struct mvneta_tx_queue *txq = &pp->txqs[txq_def];
1479 struct mvneta_tx_desc *tx_desc;
1480 struct netdev_queue *nq;
1484 if (!netif_running(dev))
1487 frags = skb_shinfo(skb)->nr_frags + 1;
1488 nq = netdev_get_tx_queue(dev, txq_def);
1490 /* Get a descriptor for the first part of the packet */
1491 tx_desc = mvneta_txq_next_desc_get(txq);
1493 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1495 tx_desc->data_size = skb_headlen(skb);
1497 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1500 if (unlikely(dma_mapping_error(dev->dev.parent,
1501 tx_desc->buf_phys_addr))) {
1502 mvneta_txq_desc_put(txq);
1508 /* First and Last descriptor */
1509 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1510 tx_desc->command = tx_cmd;
1511 txq->tx_skb[txq->txq_put_index] = skb;
1512 mvneta_txq_inc_put(txq);
1514 /* First but not Last */
1515 tx_cmd |= MVNETA_TXD_F_DESC;
1516 txq->tx_skb[txq->txq_put_index] = NULL;
1517 mvneta_txq_inc_put(txq);
1518 tx_desc->command = tx_cmd;
1519 /* Continue with other skb fragments */
1520 if (mvneta_tx_frag_process(pp, skb, txq)) {
1521 dma_unmap_single(dev->dev.parent,
1522 tx_desc->buf_phys_addr,
1525 mvneta_txq_desc_put(txq);
1531 txq->count += frags;
1532 mvneta_txq_pend_desc_add(pp, txq, frags);
1534 if (txq->size - txq->count < MAX_SKB_FRAGS + 1)
1535 netif_tx_stop_queue(nq);
1539 u64_stats_update_begin(&pp->tx_stats.syncp);
1540 pp->tx_stats.packets++;
1541 pp->tx_stats.bytes += skb->len;
1542 u64_stats_update_end(&pp->tx_stats.syncp);
1545 dev->stats.tx_dropped++;
1546 dev_kfree_skb_any(skb);
1549 if (txq->count >= MVNETA_TXDONE_COAL_PKTS)
1550 mvneta_txq_done(pp, txq);
1552 /* If after calling mvneta_txq_done, count equals
1553 * frags, we need to set the timer
1555 if (txq->count == frags && frags > 0)
1556 mvneta_add_tx_done_timer(pp);
1558 return NETDEV_TX_OK;
1562 /* Free tx resources, when resetting a port */
1563 static void mvneta_txq_done_force(struct mvneta_port *pp,
1564 struct mvneta_tx_queue *txq)
1567 int tx_done = txq->count;
1569 mvneta_txq_bufs_free(pp, txq, tx_done);
1573 txq->txq_put_index = 0;
1574 txq->txq_get_index = 0;
1577 /* handle tx done - called from tx done timer callback */
1578 static u32 mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done,
1581 struct mvneta_tx_queue *txq;
1583 struct netdev_queue *nq;
1586 while (cause_tx_done != 0) {
1587 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1591 nq = netdev_get_tx_queue(pp->dev, txq->id);
1592 __netif_tx_lock(nq, smp_processor_id());
1595 tx_done += mvneta_txq_done(pp, txq);
1596 *tx_todo += txq->count;
1599 __netif_tx_unlock(nq);
1600 cause_tx_done &= ~((1 << txq->id));
1606 /* Compute crc8 of the specified address, using a unique algorithm ,
1607 * according to hw spec, different than generic crc8 algorithm
1609 static int mvneta_addr_crc(unsigned char *addr)
1614 for (i = 0; i < ETH_ALEN; i++) {
1617 crc = (crc ^ addr[i]) << 8;
1618 for (j = 7; j >= 0; j--) {
1619 if (crc & (0x100 << j))
1627 /* This method controls the net device special MAC multicast support.
1628 * The Special Multicast Table for MAC addresses supports MAC of the form
1629 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1630 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1631 * Table entries in the DA-Filter table. This method set the Special
1632 * Multicast Table appropriate entry.
1634 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1635 unsigned char last_byte,
1638 unsigned int smc_table_reg;
1639 unsigned int tbl_offset;
1640 unsigned int reg_offset;
1642 /* Register offset from SMC table base */
1643 tbl_offset = (last_byte / 4);
1644 /* Entry offset within the above reg */
1645 reg_offset = last_byte % 4;
1647 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1651 smc_table_reg &= ~(0xff << (8 * reg_offset));
1653 smc_table_reg &= ~(0xff << (8 * reg_offset));
1654 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1657 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1661 /* This method controls the network device Other MAC multicast support.
1662 * The Other Multicast Table is used for multicast of another type.
1663 * A CRC-8 is used as an index to the Other Multicast Table entries
1664 * in the DA-Filter table.
1665 * The method gets the CRC-8 value from the calling routine and
1666 * sets the Other Multicast Table appropriate entry according to the
1669 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1673 unsigned int omc_table_reg;
1674 unsigned int tbl_offset;
1675 unsigned int reg_offset;
1677 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1678 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1680 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1683 /* Clear accepts frame bit at specified Other DA table entry */
1684 omc_table_reg &= ~(0xff << (8 * reg_offset));
1686 omc_table_reg &= ~(0xff << (8 * reg_offset));
1687 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1690 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1693 /* The network device supports multicast using two tables:
1694 * 1) Special Multicast Table for MAC addresses of the form
1695 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1696 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1697 * Table entries in the DA-Filter table.
1698 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1699 * is used as an index to the Other Multicast Table entries in the
1702 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1705 unsigned char crc_result = 0;
1707 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1708 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1712 crc_result = mvneta_addr_crc(p_addr);
1714 if (pp->mcast_count[crc_result] == 0) {
1715 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1720 pp->mcast_count[crc_result]--;
1721 if (pp->mcast_count[crc_result] != 0) {
1722 netdev_info(pp->dev,
1723 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1724 pp->mcast_count[crc_result], crc_result);
1728 pp->mcast_count[crc_result]++;
1730 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1735 /* Configure Fitering mode of Ethernet port */
1736 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1739 u32 port_cfg_reg, val;
1741 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1743 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
1745 /* Set / Clear UPM bit in port configuration register */
1747 /* Accept all Unicast addresses */
1748 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
1749 val |= MVNETA_FORCE_UNI;
1750 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
1751 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
1753 /* Reject all Unicast addresses */
1754 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
1755 val &= ~MVNETA_FORCE_UNI;
1758 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
1759 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
1762 /* register unicast and multicast addresses */
1763 static void mvneta_set_rx_mode(struct net_device *dev)
1765 struct mvneta_port *pp = netdev_priv(dev);
1766 struct netdev_hw_addr *ha;
1768 if (dev->flags & IFF_PROMISC) {
1769 /* Accept all: Multicast + Unicast */
1770 mvneta_rx_unicast_promisc_set(pp, 1);
1771 mvneta_set_ucast_table(pp, rxq_def);
1772 mvneta_set_special_mcast_table(pp, rxq_def);
1773 mvneta_set_other_mcast_table(pp, rxq_def);
1775 /* Accept single Unicast */
1776 mvneta_rx_unicast_promisc_set(pp, 0);
1777 mvneta_set_ucast_table(pp, -1);
1778 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
1780 if (dev->flags & IFF_ALLMULTI) {
1781 /* Accept all multicast */
1782 mvneta_set_special_mcast_table(pp, rxq_def);
1783 mvneta_set_other_mcast_table(pp, rxq_def);
1785 /* Accept only initialized multicast */
1786 mvneta_set_special_mcast_table(pp, -1);
1787 mvneta_set_other_mcast_table(pp, -1);
1789 if (!netdev_mc_empty(dev)) {
1790 netdev_for_each_mc_addr(ha, dev) {
1791 mvneta_mcast_addr_set(pp, ha->addr,
1799 /* Interrupt handling - the callback for request_irq() */
1800 static irqreturn_t mvneta_isr(int irq, void *dev_id)
1802 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
1804 /* Mask all interrupts */
1805 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1807 napi_schedule(&pp->napi);
1813 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
1814 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
1815 * Bits 8 -15 of the cause Rx Tx register indicate that are received
1816 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
1817 * Each CPU has its own causeRxTx register
1819 static int mvneta_poll(struct napi_struct *napi, int budget)
1823 unsigned long flags;
1824 struct mvneta_port *pp = netdev_priv(napi->dev);
1826 if (!netif_running(pp->dev)) {
1827 napi_complete(napi);
1831 /* Read cause register */
1832 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
1833 MVNETA_RX_INTR_MASK(rxq_number);
1835 /* For the case where the last mvneta_poll did not process all
1838 cause_rx_tx |= pp->cause_rx_tx;
1839 if (rxq_number > 1) {
1840 while ((cause_rx_tx != 0) && (budget > 0)) {
1842 struct mvneta_rx_queue *rxq;
1843 /* get rx queue number from cause_rx_tx */
1844 rxq = mvneta_rx_policy(pp, cause_rx_tx);
1848 /* process the packet in that rx queue */
1849 count = mvneta_rx(pp, budget, rxq);
1853 /* set off the rx bit of the
1854 * corresponding bit in the cause rx
1855 * tx register, so that next iteration
1856 * will find the next rx queue where
1857 * packets are received on
1859 cause_rx_tx &= ~((1 << rxq->id) << 8);
1863 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
1869 napi_complete(napi);
1870 local_irq_save(flags);
1871 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1872 MVNETA_RX_INTR_MASK(rxq_number));
1873 local_irq_restore(flags);
1876 pp->cause_rx_tx = cause_rx_tx;
1880 /* tx done timer callback */
1881 static void mvneta_tx_done_timer_callback(unsigned long data)
1883 struct net_device *dev = (struct net_device *)data;
1884 struct mvneta_port *pp = netdev_priv(dev);
1885 int tx_done = 0, tx_todo = 0;
1887 if (!netif_running(dev))
1890 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
1892 tx_done = mvneta_tx_done_gbe(pp,
1893 (((1 << txq_number) - 1) &
1894 MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK),
1897 mvneta_add_tx_done_timer(pp);
1900 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1901 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1904 struct net_device *dev = pp->dev;
1907 for (i = 0; i < num; i++) {
1908 struct sk_buff *skb;
1909 struct mvneta_rx_desc *rx_desc;
1910 unsigned long phys_addr;
1912 skb = dev_alloc_skb(pp->pkt_size);
1914 netdev_err(dev, "%s:rxq %d, %d of %d buffs filled\n",
1915 __func__, rxq->id, i, num);
1919 rx_desc = rxq->descs + i;
1920 memset(rx_desc, 0, sizeof(struct mvneta_rx_desc));
1921 phys_addr = dma_map_single(dev->dev.parent, skb->head,
1922 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1924 if (unlikely(dma_mapping_error(dev->dev.parent, phys_addr))) {
1929 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1932 /* Add this number of RX descriptors as non occupied (ready to
1935 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1940 /* Free all packets pending transmit from all TXQs and reset TX port */
1941 static void mvneta_tx_reset(struct mvneta_port *pp)
1945 /* free the skb's in the hal tx ring */
1946 for (queue = 0; queue < txq_number; queue++)
1947 mvneta_txq_done_force(pp, &pp->txqs[queue]);
1949 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1950 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1953 static void mvneta_rx_reset(struct mvneta_port *pp)
1955 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1956 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1959 /* Rx/Tx queue initialization/cleanup methods */
1961 /* Create a specified RX queue */
1962 static int mvneta_rxq_init(struct mvneta_port *pp,
1963 struct mvneta_rx_queue *rxq)
1966 rxq->size = pp->rx_ring_size;
1968 /* Allocate memory for RX descriptors */
1969 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
1970 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
1971 &rxq->descs_phys, GFP_KERNEL);
1972 if (rxq->descs == NULL)
1975 BUG_ON(rxq->descs !=
1976 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
1978 rxq->last_desc = rxq->size - 1;
1980 /* Set Rx descriptors queue starting address */
1981 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1982 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1985 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
1987 /* Set coalescing pkts and time */
1988 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
1989 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
1991 /* Fill RXQ with buffers from RX pool */
1992 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
1993 mvneta_rxq_bm_disable(pp, rxq);
1994 mvneta_rxq_fill(pp, rxq, rxq->size);
1999 /* Cleanup Rx queue */
2000 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2001 struct mvneta_rx_queue *rxq)
2003 mvneta_rxq_drop_pkts(pp, rxq);
2006 dma_free_coherent(pp->dev->dev.parent,
2007 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2013 rxq->next_desc_to_proc = 0;
2014 rxq->descs_phys = 0;
2017 /* Create and initialize a tx queue */
2018 static int mvneta_txq_init(struct mvneta_port *pp,
2019 struct mvneta_tx_queue *txq)
2021 txq->size = pp->tx_ring_size;
2023 /* Allocate memory for TX descriptors */
2024 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2025 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2026 &txq->descs_phys, GFP_KERNEL);
2027 if (txq->descs == NULL)
2030 /* Make sure descriptor address is cache line size aligned */
2031 BUG_ON(txq->descs !=
2032 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2034 txq->last_desc = txq->size - 1;
2036 /* Set maximum bandwidth for enabled TXQs */
2037 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2038 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2040 /* Set Tx descriptors queue starting address */
2041 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2042 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2044 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2045 if (txq->tx_skb == NULL) {
2046 dma_free_coherent(pp->dev->dev.parent,
2047 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2048 txq->descs, txq->descs_phys);
2051 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2056 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2057 static void mvneta_txq_deinit(struct mvneta_port *pp,
2058 struct mvneta_tx_queue *txq)
2063 dma_free_coherent(pp->dev->dev.parent,
2064 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2065 txq->descs, txq->descs_phys);
2069 txq->next_desc_to_proc = 0;
2070 txq->descs_phys = 0;
2072 /* Set minimum bandwidth for disabled TXQs */
2073 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2074 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2076 /* Set Tx descriptors queue starting address and size */
2077 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2078 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2081 /* Cleanup all Tx queues */
2082 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2086 for (queue = 0; queue < txq_number; queue++)
2087 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2090 /* Cleanup all Rx queues */
2091 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2095 for (queue = 0; queue < rxq_number; queue++)
2096 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2100 /* Init all Rx queues */
2101 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2105 for (queue = 0; queue < rxq_number; queue++) {
2106 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2108 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2110 mvneta_cleanup_rxqs(pp);
2118 /* Init all tx queues */
2119 static int mvneta_setup_txqs(struct mvneta_port *pp)
2123 for (queue = 0; queue < txq_number; queue++) {
2124 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2126 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2128 mvneta_cleanup_txqs(pp);
2136 static void mvneta_start_dev(struct mvneta_port *pp)
2138 mvneta_max_rx_size_set(pp, pp->pkt_size);
2139 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2141 /* start the Rx/Tx activity */
2142 mvneta_port_enable(pp);
2144 /* Enable polling on the port */
2145 napi_enable(&pp->napi);
2147 /* Unmask interrupts */
2148 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2149 MVNETA_RX_INTR_MASK(rxq_number));
2151 phy_start(pp->phy_dev);
2152 netif_tx_start_all_queues(pp->dev);
2155 static void mvneta_stop_dev(struct mvneta_port *pp)
2157 phy_stop(pp->phy_dev);
2159 napi_disable(&pp->napi);
2161 netif_carrier_off(pp->dev);
2163 mvneta_port_down(pp);
2164 netif_tx_stop_all_queues(pp->dev);
2166 /* Stop the port activity */
2167 mvneta_port_disable(pp);
2169 /* Clear all ethernet port interrupts */
2170 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2171 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2173 /* Mask all ethernet port interrupts */
2174 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2175 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2176 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2178 mvneta_tx_reset(pp);
2179 mvneta_rx_reset(pp);
2182 /* tx timeout callback - display a message and stop/start the network device */
2183 static void mvneta_tx_timeout(struct net_device *dev)
2185 struct mvneta_port *pp = netdev_priv(dev);
2187 netdev_info(dev, "tx timeout\n");
2188 mvneta_stop_dev(pp);
2189 mvneta_start_dev(pp);
2192 /* Return positive if MTU is valid */
2193 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2196 netdev_err(dev, "cannot change mtu to less than 68\n");
2200 /* 9676 == 9700 - 20 and rounding to 8 */
2202 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2206 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2207 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2208 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2209 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2215 /* Change the device mtu */
2216 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2218 struct mvneta_port *pp = netdev_priv(dev);
2221 mtu = mvneta_check_mtu_valid(dev, mtu);
2227 if (!netif_running(dev))
2230 /* The interface is running, so we have to force a
2231 * reallocation of the RXQs
2233 mvneta_stop_dev(pp);
2235 mvneta_cleanup_txqs(pp);
2236 mvneta_cleanup_rxqs(pp);
2238 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2240 ret = mvneta_setup_rxqs(pp);
2242 netdev_err(pp->dev, "unable to setup rxqs after MTU change\n");
2246 mvneta_setup_txqs(pp);
2248 mvneta_start_dev(pp);
2254 /* Handle setting mac address */
2255 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2257 struct mvneta_port *pp = netdev_priv(dev);
2261 if (netif_running(dev))
2264 /* Remove previous address table entry */
2265 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2267 /* Set new addr in hw */
2268 mvneta_mac_addr_set(pp, mac, rxq_def);
2270 /* Set addr in the device */
2271 for (i = 0; i < ETH_ALEN; i++)
2272 dev->dev_addr[i] = mac[i];
2277 static void mvneta_adjust_link(struct net_device *ndev)
2279 struct mvneta_port *pp = netdev_priv(ndev);
2280 struct phy_device *phydev = pp->phy_dev;
2281 int status_change = 0;
2284 if ((pp->speed != phydev->speed) ||
2285 (pp->duplex != phydev->duplex)) {
2288 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2289 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2290 MVNETA_GMAC_CONFIG_GMII_SPEED |
2291 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
2294 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2296 if (phydev->speed == SPEED_1000)
2297 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2299 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2301 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2303 pp->duplex = phydev->duplex;
2304 pp->speed = phydev->speed;
2308 if (phydev->link != pp->link) {
2309 if (!phydev->link) {
2314 pp->link = phydev->link;
2318 if (status_change) {
2320 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2321 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
2322 MVNETA_GMAC_FORCE_LINK_DOWN);
2323 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2325 netdev_info(pp->dev, "link up\n");
2327 mvneta_port_down(pp);
2328 netdev_info(pp->dev, "link down\n");
2333 static int mvneta_mdio_probe(struct mvneta_port *pp)
2335 struct phy_device *phy_dev;
2337 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2340 netdev_err(pp->dev, "could not find the PHY\n");
2344 phy_dev->supported &= PHY_GBIT_FEATURES;
2345 phy_dev->advertising = phy_dev->supported;
2347 pp->phy_dev = phy_dev;
2355 static void mvneta_mdio_remove(struct mvneta_port *pp)
2357 phy_disconnect(pp->phy_dev);
2361 static int mvneta_open(struct net_device *dev)
2363 struct mvneta_port *pp = netdev_priv(dev);
2366 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2368 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2370 ret = mvneta_setup_rxqs(pp);
2374 ret = mvneta_setup_txqs(pp);
2376 goto err_cleanup_rxqs;
2378 /* Connect to port interrupt line */
2379 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2380 MVNETA_DRIVER_NAME, pp);
2382 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2383 goto err_cleanup_txqs;
2386 /* In default link is down */
2387 netif_carrier_off(pp->dev);
2389 ret = mvneta_mdio_probe(pp);
2391 netdev_err(dev, "cannot probe MDIO bus\n");
2395 mvneta_start_dev(pp);
2400 free_irq(pp->dev->irq, pp);
2402 mvneta_cleanup_txqs(pp);
2404 mvneta_cleanup_rxqs(pp);
2408 /* Stop the port, free port interrupt line */
2409 static int mvneta_stop(struct net_device *dev)
2411 struct mvneta_port *pp = netdev_priv(dev);
2413 mvneta_stop_dev(pp);
2414 mvneta_mdio_remove(pp);
2415 free_irq(dev->irq, pp);
2416 mvneta_cleanup_rxqs(pp);
2417 mvneta_cleanup_txqs(pp);
2418 del_timer(&pp->tx_done_timer);
2419 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2424 /* Ethtool methods */
2426 /* Get settings (phy address, speed) for ethtools */
2427 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2429 struct mvneta_port *pp = netdev_priv(dev);
2434 return phy_ethtool_gset(pp->phy_dev, cmd);
2437 /* Set settings (phy address, speed) for ethtools */
2438 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2440 struct mvneta_port *pp = netdev_priv(dev);
2445 return phy_ethtool_sset(pp->phy_dev, cmd);
2448 /* Set interrupt coalescing for ethtools */
2449 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2450 struct ethtool_coalesce *c)
2452 struct mvneta_port *pp = netdev_priv(dev);
2455 for (queue = 0; queue < rxq_number; queue++) {
2456 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2457 rxq->time_coal = c->rx_coalesce_usecs;
2458 rxq->pkts_coal = c->rx_max_coalesced_frames;
2459 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2460 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2463 for (queue = 0; queue < txq_number; queue++) {
2464 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2465 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2466 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2472 /* get coalescing for ethtools */
2473 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2474 struct ethtool_coalesce *c)
2476 struct mvneta_port *pp = netdev_priv(dev);
2478 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2479 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2481 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2486 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2487 struct ethtool_drvinfo *drvinfo)
2489 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2490 sizeof(drvinfo->driver));
2491 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2492 sizeof(drvinfo->version));
2493 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2494 sizeof(drvinfo->bus_info));
2498 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2499 struct ethtool_ringparam *ring)
2501 struct mvneta_port *pp = netdev_priv(netdev);
2503 ring->rx_max_pending = MVNETA_MAX_RXD;
2504 ring->tx_max_pending = MVNETA_MAX_TXD;
2505 ring->rx_pending = pp->rx_ring_size;
2506 ring->tx_pending = pp->tx_ring_size;
2509 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2510 struct ethtool_ringparam *ring)
2512 struct mvneta_port *pp = netdev_priv(dev);
2514 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2516 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2517 ring->rx_pending : MVNETA_MAX_RXD;
2518 pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ?
2519 ring->tx_pending : MVNETA_MAX_TXD;
2521 if (netif_running(dev)) {
2523 if (mvneta_open(dev)) {
2525 "error on opening device after ring param change\n");
2533 static const struct net_device_ops mvneta_netdev_ops = {
2534 .ndo_open = mvneta_open,
2535 .ndo_stop = mvneta_stop,
2536 .ndo_start_xmit = mvneta_tx,
2537 .ndo_set_rx_mode = mvneta_set_rx_mode,
2538 .ndo_set_mac_address = mvneta_set_mac_addr,
2539 .ndo_change_mtu = mvneta_change_mtu,
2540 .ndo_tx_timeout = mvneta_tx_timeout,
2541 .ndo_get_stats64 = mvneta_get_stats64,
2544 const struct ethtool_ops mvneta_eth_tool_ops = {
2545 .get_link = ethtool_op_get_link,
2546 .get_settings = mvneta_ethtool_get_settings,
2547 .set_settings = mvneta_ethtool_set_settings,
2548 .set_coalesce = mvneta_ethtool_set_coalesce,
2549 .get_coalesce = mvneta_ethtool_get_coalesce,
2550 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2551 .get_ringparam = mvneta_ethtool_get_ringparam,
2552 .set_ringparam = mvneta_ethtool_set_ringparam,
2556 static int mvneta_init(struct mvneta_port *pp, int phy_addr)
2561 mvneta_port_disable(pp);
2563 /* Set port default values */
2564 mvneta_defaults_set(pp);
2566 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
2571 /* Initialize TX descriptor rings */
2572 for (queue = 0; queue < txq_number; queue++) {
2573 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2575 txq->size = pp->tx_ring_size;
2576 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2579 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
2586 /* Create Rx descriptor rings */
2587 for (queue = 0; queue < rxq_number; queue++) {
2588 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2590 rxq->size = pp->rx_ring_size;
2591 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2592 rxq->time_coal = MVNETA_RX_COAL_USEC;
2598 static void mvneta_deinit(struct mvneta_port *pp)
2604 /* platform glue : initialize decoding windows */
2605 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2606 const struct mbus_dram_target_info *dram)
2612 for (i = 0; i < 6; i++) {
2613 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2614 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2617 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2623 for (i = 0; i < dram->num_cs; i++) {
2624 const struct mbus_dram_window *cs = dram->cs + i;
2625 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2626 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2628 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2629 (cs->size - 1) & 0xffff0000);
2631 win_enable &= ~(1 << i);
2632 win_protect |= 3 << (2 * i);
2635 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2638 /* Power up the port */
2639 static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2643 /* MAC Cause register should be cleared */
2644 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2646 if (phy_mode == PHY_INTERFACE_MODE_SGMII)
2647 mvneta_port_sgmii_config(pp);
2649 mvneta_gmac_rgmii_set(pp, 1);
2651 /* Cancel Port Reset */
2652 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2653 val &= ~MVNETA_GMAC2_PORT_RESET;
2654 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
2656 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2657 MVNETA_GMAC2_PORT_RESET) != 0)
2661 /* Device initialization routine */
2662 static int mvneta_probe(struct platform_device *pdev)
2664 const struct mbus_dram_target_info *dram_target_info;
2665 struct device_node *dn = pdev->dev.of_node;
2666 struct device_node *phy_node;
2668 struct mvneta_port *pp;
2669 struct net_device *dev;
2670 const char *mac_addr;
2674 /* Our multiqueue support is not complete, so for now, only
2675 * allow the usage of the first RX queue
2678 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
2682 dev = alloc_etherdev_mq(sizeof(struct mvneta_port), 8);
2686 dev->irq = irq_of_parse_and_map(dn, 0);
2687 if (dev->irq == 0) {
2689 goto err_free_netdev;
2692 phy_node = of_parse_phandle(dn, "phy", 0);
2694 dev_err(&pdev->dev, "no associated PHY\n");
2699 phy_mode = of_get_phy_mode(dn);
2701 dev_err(&pdev->dev, "incorrect phy-mode\n");
2706 mac_addr = of_get_mac_address(dn);
2708 if (!mac_addr || !is_valid_ether_addr(mac_addr))
2709 eth_hw_addr_random(dev);
2711 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
2713 dev->tx_queue_len = MVNETA_MAX_TXD;
2714 dev->watchdog_timeo = 5 * HZ;
2715 dev->netdev_ops = &mvneta_netdev_ops;
2717 SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops);
2719 pp = netdev_priv(dev);
2721 pp->tx_done_timer.function = mvneta_tx_done_timer_callback;
2722 init_timer(&pp->tx_done_timer);
2723 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2725 pp->weight = MVNETA_RX_POLL_WEIGHT;
2726 pp->phy_node = phy_node;
2727 pp->phy_interface = phy_mode;
2729 pp->base = of_iomap(dn, 0);
2730 if (pp->base == NULL) {
2735 pp->clk = devm_clk_get(&pdev->dev, NULL);
2736 if (IS_ERR(pp->clk)) {
2737 err = PTR_ERR(pp->clk);
2741 clk_prepare_enable(pp->clk);
2743 pp->tx_done_timer.data = (unsigned long)dev;
2745 pp->tx_ring_size = MVNETA_MAX_TXD;
2746 pp->rx_ring_size = MVNETA_MAX_RXD;
2749 SET_NETDEV_DEV(dev, &pdev->dev);
2751 err = mvneta_init(pp, phy_addr);
2753 dev_err(&pdev->dev, "can't init eth hal\n");
2756 mvneta_port_power_up(pp, phy_mode);
2758 dram_target_info = mv_mbus_dram_info();
2759 if (dram_target_info)
2760 mvneta_conf_mbus_windows(pp, dram_target_info);
2762 netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight);
2764 err = register_netdev(dev);
2766 dev_err(&pdev->dev, "failed to register\n");
2770 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2771 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2772 dev->priv_flags |= IFF_UNICAST_FLT;
2774 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
2776 platform_set_drvdata(pdev, pp->dev);
2783 clk_disable_unprepare(pp->clk);
2787 irq_dispose_mapping(dev->irq);
2793 /* Device removal routine */
2794 static int mvneta_remove(struct platform_device *pdev)
2796 struct net_device *dev = platform_get_drvdata(pdev);
2797 struct mvneta_port *pp = netdev_priv(dev);
2799 unregister_netdev(dev);
2801 clk_disable_unprepare(pp->clk);
2803 irq_dispose_mapping(dev->irq);
2806 platform_set_drvdata(pdev, NULL);
2811 static const struct of_device_id mvneta_match[] = {
2812 { .compatible = "marvell,armada-370-neta" },
2815 MODULE_DEVICE_TABLE(of, mvneta_match);
2817 static struct platform_driver mvneta_driver = {
2818 .probe = mvneta_probe,
2819 .remove = mvneta_remove,
2821 .name = MVNETA_DRIVER_NAME,
2822 .of_match_table = mvneta_match,
2826 module_platform_driver(mvneta_driver);
2828 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
2829 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
2830 MODULE_LICENSE("GPL");
2832 module_param(rxq_number, int, S_IRUGO);
2833 module_param(txq_number, int, S_IRUGO);
2835 module_param(rxq_def, int, S_IRUGO);
2836 module_param(txq_def, int, S_IRUGO);