2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
45 #include <linux/delay.h>
53 #define CMD_POLL_TOKEN 0xffff
54 #define INBOX_MASK 0xffffffffffffff00ULL
56 #define CMD_CHAN_VER 1
57 #define CMD_CHAN_IF_REV 1
60 /* command completed successfully: */
62 /* Internal error (such as a bus error) occurred while processing command: */
63 CMD_STAT_INTERNAL_ERR = 0x01,
64 /* Operation/command not supported or opcode modifier not supported: */
65 CMD_STAT_BAD_OP = 0x02,
66 /* Parameter not supported or parameter out of range: */
67 CMD_STAT_BAD_PARAM = 0x03,
68 /* System not enabled or bad system state: */
69 CMD_STAT_BAD_SYS_STATE = 0x04,
70 /* Attempt to access reserved or unallocaterd resource: */
71 CMD_STAT_BAD_RESOURCE = 0x05,
72 /* Requested resource is currently executing a command, or is otherwise busy: */
73 CMD_STAT_RESOURCE_BUSY = 0x06,
74 /* Required capability exceeds device limits: */
75 CMD_STAT_EXCEED_LIM = 0x08,
76 /* Resource is not in the appropriate state or ownership: */
77 CMD_STAT_BAD_RES_STATE = 0x09,
78 /* Index out of range: */
79 CMD_STAT_BAD_INDEX = 0x0a,
80 /* FW image corrupted: */
81 CMD_STAT_BAD_NVMEM = 0x0b,
82 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
83 CMD_STAT_ICM_ERROR = 0x0c,
84 /* Attempt to modify a QP/EE which is not in the presumed state: */
85 CMD_STAT_BAD_QP_STATE = 0x10,
86 /* Bad segment parameters (Address/Size): */
87 CMD_STAT_BAD_SEG_PARAM = 0x20,
88 /* Memory Region has Memory Windows bound to: */
89 CMD_STAT_REG_BOUND = 0x21,
90 /* HCA local attached memory not present: */
91 CMD_STAT_LAM_NOT_PRE = 0x22,
92 /* Bad management packet (silently discarded): */
93 CMD_STAT_BAD_PKT = 0x30,
94 /* More outstanding CQEs in CQ than new CQ size: */
95 CMD_STAT_BAD_SIZE = 0x40,
96 /* Multi Function device support required: */
97 CMD_STAT_MULTI_FUNC_REQ = 0x50,
101 HCR_IN_PARAM_OFFSET = 0x00,
102 HCR_IN_MODIFIER_OFFSET = 0x08,
103 HCR_OUT_PARAM_OFFSET = 0x0c,
104 HCR_TOKEN_OFFSET = 0x14,
105 HCR_STATUS_OFFSET = 0x18,
107 HCR_OPMOD_SHIFT = 12,
114 GO_BIT_TIMEOUT_MSECS = 10000
117 enum mlx4_vlan_transition {
118 MLX4_VLAN_TRANSITION_VST_VST = 0,
119 MLX4_VLAN_TRANSITION_VST_VGT = 1,
120 MLX4_VLAN_TRANSITION_VGT_VST = 2,
121 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
125 struct mlx4_cmd_context {
126 struct completion done;
134 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
135 struct mlx4_vhcr_cmd *in_vhcr);
137 static int mlx4_status_to_errno(u8 status)
139 static const int trans_table[] = {
140 [CMD_STAT_INTERNAL_ERR] = -EIO,
141 [CMD_STAT_BAD_OP] = -EPERM,
142 [CMD_STAT_BAD_PARAM] = -EINVAL,
143 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
144 [CMD_STAT_BAD_RESOURCE] = -EBADF,
145 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
146 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
147 [CMD_STAT_BAD_RES_STATE] = -EBADF,
148 [CMD_STAT_BAD_INDEX] = -EBADF,
149 [CMD_STAT_BAD_NVMEM] = -EFAULT,
150 [CMD_STAT_ICM_ERROR] = -ENFILE,
151 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
152 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
153 [CMD_STAT_REG_BOUND] = -EBUSY,
154 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
155 [CMD_STAT_BAD_PKT] = -EINVAL,
156 [CMD_STAT_BAD_SIZE] = -ENOMEM,
157 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
160 if (status >= ARRAY_SIZE(trans_table) ||
161 (status != CMD_STAT_OK && trans_table[status] == 0))
164 return trans_table[status];
167 static u8 mlx4_errno_to_status(int errno)
171 return CMD_STAT_BAD_OP;
173 return CMD_STAT_BAD_PARAM;
175 return CMD_STAT_BAD_SYS_STATE;
177 return CMD_STAT_RESOURCE_BUSY;
179 return CMD_STAT_EXCEED_LIM;
181 return CMD_STAT_ICM_ERROR;
183 return CMD_STAT_INTERNAL_ERR;
187 static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
191 case MLX4_CMD_UNMAP_ICM:
192 case MLX4_CMD_UNMAP_ICM_AUX:
193 case MLX4_CMD_UNMAP_FA:
194 case MLX4_CMD_2RST_QP:
195 case MLX4_CMD_HW2SW_EQ:
196 case MLX4_CMD_HW2SW_CQ:
197 case MLX4_CMD_HW2SW_SRQ:
198 case MLX4_CMD_HW2SW_MPT:
199 case MLX4_CMD_CLOSE_HCA:
200 case MLX4_QP_FLOW_STEERING_DETACH:
201 case MLX4_CMD_FREE_RES:
202 case MLX4_CMD_CLOSE_PORT:
205 case MLX4_CMD_QP_ATTACH:
206 /* On Detach case return success */
207 if (op_modifier == 0)
209 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
212 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
216 static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
218 /* Any error during the closing commands below is considered fatal */
219 if (op == MLX4_CMD_CLOSE_HCA ||
220 op == MLX4_CMD_HW2SW_EQ ||
221 op == MLX4_CMD_HW2SW_CQ ||
222 op == MLX4_CMD_2RST_QP ||
223 op == MLX4_CMD_HW2SW_SRQ ||
224 op == MLX4_CMD_SYNC_TPT ||
225 op == MLX4_CMD_UNMAP_ICM ||
226 op == MLX4_CMD_UNMAP_ICM_AUX ||
227 op == MLX4_CMD_UNMAP_FA)
229 /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
230 * CMD_STAT_REG_BOUND.
231 * This status indicates that memory region has memory windows bound to it
232 * which may result from invalid user space usage and is not fatal.
234 if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
239 static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
242 /* Only if reset flow is really active return code is based on
243 * command, otherwise current error code is returned.
245 if (mlx4_internal_err_reset) {
246 mlx4_enter_error_state(dev->persist);
247 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
253 static int comm_pending(struct mlx4_dev *dev)
255 struct mlx4_priv *priv = mlx4_priv(dev);
256 u32 status = readl(&priv->mfunc.comm->slave_read);
258 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
261 static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
263 struct mlx4_priv *priv = mlx4_priv(dev);
266 /* To avoid writing to unknown addresses after the device state was
267 * changed to internal error and the function was rest,
268 * check the INTERNAL_ERROR flag which is updated under
269 * device_state_mutex lock.
271 mutex_lock(&dev->persist->device_state_mutex);
273 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
274 mutex_unlock(&dev->persist->device_state_mutex);
278 priv->cmd.comm_toggle ^= 1;
279 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
280 __raw_writel((__force u32) cpu_to_be32(val),
281 &priv->mfunc.comm->slave_write);
283 mutex_unlock(&dev->persist->device_state_mutex);
287 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
288 unsigned long timeout)
290 struct mlx4_priv *priv = mlx4_priv(dev);
293 int ret_from_pending = 0;
295 /* First, verify that the master reports correct status */
296 if (comm_pending(dev)) {
297 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
298 priv->cmd.comm_toggle, cmd);
303 down(&priv->cmd.poll_sem);
304 if (mlx4_comm_cmd_post(dev, cmd, param)) {
305 /* Only in case the device state is INTERNAL_ERROR,
306 * mlx4_comm_cmd_post returns with an error
308 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
312 end = msecs_to_jiffies(timeout) + jiffies;
313 while (comm_pending(dev) && time_before(jiffies, end))
315 ret_from_pending = comm_pending(dev);
316 if (ret_from_pending) {
317 /* check if the slave is trying to boot in the middle of
318 * FLR process. The only non-zero result in the RESET command
319 * is MLX4_DELAY_RESET_SLAVE*/
320 if ((MLX4_COMM_CMD_RESET == cmd)) {
321 err = MLX4_DELAY_RESET_SLAVE;
324 mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
326 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
331 mlx4_enter_error_state(dev->persist);
333 up(&priv->cmd.poll_sem);
337 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
338 u16 param, u16 op, unsigned long timeout)
340 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
341 struct mlx4_cmd_context *context;
345 down(&cmd->event_sem);
347 spin_lock(&cmd->context_lock);
348 BUG_ON(cmd->free_head < 0);
349 context = &cmd->context[cmd->free_head];
350 context->token += cmd->token_mask + 1;
351 cmd->free_head = context->next;
352 spin_unlock(&cmd->context_lock);
354 reinit_completion(&context->done);
356 if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
357 /* Only in case the device state is INTERNAL_ERROR,
358 * mlx4_comm_cmd_post returns with an error
360 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
364 if (!wait_for_completion_timeout(&context->done,
365 msecs_to_jiffies(timeout))) {
366 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
371 err = context->result;
372 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
373 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
374 vhcr_cmd, context->fw_status);
375 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
379 /* wait for comm channel ready
380 * this is necessary for prevention the race
381 * when switching between event to polling mode
382 * Skipping this section in case the device is in FATAL_ERROR state,
383 * In this state, no commands are sent via the comm channel until
384 * the device has returned from reset.
386 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
387 end = msecs_to_jiffies(timeout) + jiffies;
388 while (comm_pending(dev) && time_before(jiffies, end))
394 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
395 mlx4_enter_error_state(dev->persist);
397 spin_lock(&cmd->context_lock);
398 context->next = cmd->free_head;
399 cmd->free_head = context - cmd->context;
400 spin_unlock(&cmd->context_lock);
406 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
407 u16 op, unsigned long timeout)
409 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
410 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
412 if (mlx4_priv(dev)->cmd.use_events)
413 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
414 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
417 static int cmd_pending(struct mlx4_dev *dev)
421 if (pci_channel_offline(dev->persist->pdev))
424 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
426 return (status & swab32(1 << HCR_GO_BIT)) ||
427 (mlx4_priv(dev)->cmd.toggle ==
428 !!(status & swab32(1 << HCR_T_BIT)));
431 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
432 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
435 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
436 u32 __iomem *hcr = cmd->hcr;
440 mutex_lock(&dev->persist->device_state_mutex);
441 /* To avoid writing to unknown addresses after the device state was
442 * changed to internal error and the chip was reset,
443 * check the INTERNAL_ERROR flag which is updated under
444 * device_state_mutex lock.
446 if (pci_channel_offline(dev->persist->pdev) ||
447 (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
449 * Device is going through error recovery
450 * and cannot accept commands.
457 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
459 while (cmd_pending(dev)) {
460 if (pci_channel_offline(dev->persist->pdev)) {
462 * Device is going through error recovery
463 * and cannot accept commands.
468 if (time_after_eq(jiffies, end)) {
469 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
476 * We use writel (instead of something like memcpy_toio)
477 * because writes of less than 32 bits to the HCR don't work
478 * (and some architectures such as ia64 implement memcpy_toio
479 * in terms of writeb).
481 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
482 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
483 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
484 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
485 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
486 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
488 /* __raw_writel may not order writes. */
491 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
492 (cmd->toggle << HCR_T_BIT) |
493 (event ? (1 << HCR_E_BIT) : 0) |
494 (op_modifier << HCR_OPMOD_SHIFT) |
498 * Make sure that our HCR writes don't get mixed in with
499 * writes from another CPU starting a FW command.
503 cmd->toggle = cmd->toggle ^ 1;
509 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
510 op, ret, in_param, in_modifier, op_modifier);
511 mutex_unlock(&dev->persist->device_state_mutex);
516 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
517 int out_is_imm, u32 in_modifier, u8 op_modifier,
518 u16 op, unsigned long timeout)
520 struct mlx4_priv *priv = mlx4_priv(dev);
521 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
524 mutex_lock(&priv->cmd.slave_cmd_mutex);
526 vhcr->in_param = cpu_to_be64(in_param);
527 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
528 vhcr->in_modifier = cpu_to_be32(in_modifier);
529 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
530 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
532 vhcr->flags = !!(priv->cmd.use_events) << 6;
534 if (mlx4_is_master(dev)) {
535 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
540 be64_to_cpu(vhcr->out_param);
542 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
544 vhcr->status = CMD_STAT_BAD_PARAM;
547 ret = mlx4_status_to_errno(vhcr->status);
550 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
551 ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
553 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
554 MLX4_COMM_TIME + timeout);
559 be64_to_cpu(vhcr->out_param);
561 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
563 vhcr->status = CMD_STAT_BAD_PARAM;
566 ret = mlx4_status_to_errno(vhcr->status);
568 if (dev->persist->state &
569 MLX4_DEVICE_STATE_INTERNAL_ERROR)
570 ret = mlx4_internal_err_ret_value(dev, op,
573 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
577 mutex_unlock(&priv->cmd.slave_cmd_mutex);
581 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
582 int out_is_imm, u32 in_modifier, u8 op_modifier,
583 u16 op, unsigned long timeout)
585 struct mlx4_priv *priv = mlx4_priv(dev);
586 void __iomem *hcr = priv->cmd.hcr;
591 down(&priv->cmd.poll_sem);
593 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
595 * Device is going through error recovery
596 * and cannot accept commands.
598 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
602 if (out_is_imm && !out_param) {
603 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
609 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
610 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
614 end = msecs_to_jiffies(timeout) + jiffies;
615 while (cmd_pending(dev) && time_before(jiffies, end)) {
616 if (pci_channel_offline(dev->persist->pdev)) {
618 * Device is going through error recovery
619 * and cannot accept commands.
625 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
626 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
633 if (cmd_pending(dev)) {
634 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
642 (u64) be32_to_cpu((__force __be32)
643 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
644 (u64) be32_to_cpu((__force __be32)
645 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
646 stat = be32_to_cpu((__force __be32)
647 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
648 err = mlx4_status_to_errno(stat);
650 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
652 if (mlx4_closing_cmd_fatal_error(op, stat))
659 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
661 up(&priv->cmd.poll_sem);
665 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
667 struct mlx4_priv *priv = mlx4_priv(dev);
668 struct mlx4_cmd_context *context =
669 &priv->cmd.context[token & priv->cmd.token_mask];
671 /* previously timed out command completing at long last */
672 if (token != context->token)
675 context->fw_status = status;
676 context->result = mlx4_status_to_errno(status);
677 context->out_param = out_param;
679 complete(&context->done);
682 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
683 int out_is_imm, u32 in_modifier, u8 op_modifier,
684 u16 op, unsigned long timeout)
686 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
687 struct mlx4_cmd_context *context;
690 down(&cmd->event_sem);
692 spin_lock(&cmd->context_lock);
693 BUG_ON(cmd->free_head < 0);
694 context = &cmd->context[cmd->free_head];
695 context->token += cmd->token_mask + 1;
696 cmd->free_head = context->next;
697 spin_unlock(&cmd->context_lock);
699 if (out_is_imm && !out_param) {
700 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
706 reinit_completion(&context->done);
708 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
709 in_modifier, op_modifier, op, context->token, 1);
713 if (!wait_for_completion_timeout(&context->done,
714 msecs_to_jiffies(timeout))) {
715 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
721 err = context->result;
723 /* Since we do not want to have this error message always
724 * displayed at driver start when there are ConnectX2 HCAs
725 * on the host, we deprecate the error message for this
726 * specific command/input_mod/opcode_mod/fw-status to be debug.
728 if (op == MLX4_CMD_SET_PORT &&
729 (in_modifier == 1 || in_modifier == 2) &&
730 op_modifier == MLX4_SET_PORT_IB_OPCODE &&
731 context->fw_status == CMD_STAT_BAD_SIZE)
732 mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
733 op, context->fw_status);
735 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
736 op, context->fw_status);
737 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
738 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
739 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
746 *out_param = context->out_param;
750 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
752 spin_lock(&cmd->context_lock);
753 context->next = cmd->free_head;
754 cmd->free_head = context - cmd->context;
755 spin_unlock(&cmd->context_lock);
761 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
762 int out_is_imm, u32 in_modifier, u8 op_modifier,
763 u16 op, unsigned long timeout, int native)
765 if (pci_channel_offline(dev->persist->pdev))
766 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
768 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
769 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
770 return mlx4_internal_err_ret_value(dev, op,
772 if (mlx4_priv(dev)->cmd.use_events)
773 return mlx4_cmd_wait(dev, in_param, out_param,
774 out_is_imm, in_modifier,
775 op_modifier, op, timeout);
777 return mlx4_cmd_poll(dev, in_param, out_param,
778 out_is_imm, in_modifier,
779 op_modifier, op, timeout);
781 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
782 in_modifier, op_modifier, op, timeout);
784 EXPORT_SYMBOL_GPL(__mlx4_cmd);
787 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
789 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
790 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
793 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
794 int slave, u64 slave_addr,
795 int size, int is_read)
800 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
801 (slave & ~0x7f) | (size & 0xff)) {
802 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
803 slave_addr, master_addr, slave, size);
808 in_param = (u64) slave | slave_addr;
809 out_param = (u64) dev->caps.function | master_addr;
811 in_param = (u64) dev->caps.function | master_addr;
812 out_param = (u64) slave | slave_addr;
815 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
817 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
820 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
821 struct mlx4_cmd_mailbox *inbox,
822 struct mlx4_cmd_mailbox *outbox)
824 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
825 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
832 in_mad->attr_mod = cpu_to_be32(index / 32);
834 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
835 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
840 for (i = 0; i < 32; ++i)
841 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
846 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
847 struct mlx4_cmd_mailbox *inbox,
848 struct mlx4_cmd_mailbox *outbox)
853 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
854 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
861 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
862 #define PORT_STATE_OFFSET 32
864 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
866 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
867 return IB_PORT_ACTIVE;
872 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
873 struct mlx4_vhcr *vhcr,
874 struct mlx4_cmd_mailbox *inbox,
875 struct mlx4_cmd_mailbox *outbox,
876 struct mlx4_cmd_info *cmd)
878 struct ib_smp *smp = inbox->buf;
886 struct mlx4_priv *priv = mlx4_priv(dev);
887 struct ib_smp *outsmp = outbox->buf;
888 __be16 *outtab = (__be16 *)(outsmp->data);
889 __be32 slave_cap_mask;
890 __be64 slave_node_guid;
892 port = vhcr->in_modifier;
894 /* network-view bit is for driver use only, and should not be passed to FW */
895 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
896 network_view = !!(vhcr->op_modifier & 0x8);
898 if (smp->base_version == 1 &&
899 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
900 smp->class_version == 1) {
901 /* host view is paravirtualized */
902 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
903 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
904 index = be32_to_cpu(smp->attr_mod);
905 if (port < 1 || port > dev->caps.num_ports)
907 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
908 sizeof(*table) * 32, GFP_KERNEL);
912 /* need to get the full pkey table because the paravirtualized
913 * pkeys may be scattered among several pkey blocks.
915 err = get_full_pkey_table(dev, port, table, inbox, outbox);
917 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
918 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
919 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
925 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
926 /*get the slave specific caps:*/
928 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
929 vhcr->in_modifier, opcode_modifier,
930 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
931 /* modify the response for slaves */
932 if (!err && slave != mlx4_master_func_num(dev)) {
933 u8 *state = outsmp->data + PORT_STATE_OFFSET;
935 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
936 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
937 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
941 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
942 /* compute slave's gid block */
943 smp->attr_mod = cpu_to_be32(slave / 8);
945 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
946 vhcr->in_modifier, opcode_modifier,
947 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
949 /* if needed, move slave gid to index 0 */
952 outsmp->data + (slave % 8) * 8, 8);
953 /* delete all other gids */
954 memset(outsmp->data + 8, 0, 56);
958 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
959 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
960 vhcr->in_modifier, opcode_modifier,
961 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
963 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
964 memcpy(outsmp->data + 12, &slave_node_guid, 8);
971 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
972 * These are the MADs used by ib verbs (such as ib_query_gids).
974 if (slave != mlx4_master_func_num(dev) &&
975 !mlx4_vf_smi_enabled(dev, slave, port)) {
976 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
977 smp->method == IB_MGMT_METHOD_GET) || network_view) {
978 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
979 slave, smp->method, smp->mgmt_class,
980 network_view ? "Network" : "Host",
981 be16_to_cpu(smp->attr_id));
986 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
987 vhcr->in_modifier, opcode_modifier,
988 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
991 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
992 struct mlx4_vhcr *vhcr,
993 struct mlx4_cmd_mailbox *inbox,
994 struct mlx4_cmd_mailbox *outbox,
995 struct mlx4_cmd_info *cmd)
1000 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1001 struct mlx4_vhcr *vhcr,
1002 struct mlx4_cmd_mailbox *inbox,
1003 struct mlx4_cmd_mailbox *outbox,
1004 struct mlx4_cmd_info *cmd)
1010 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1011 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1012 if (cmd->encode_slave_id) {
1013 in_param &= 0xffffffffffffff00ll;
1017 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1018 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1019 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1021 if (cmd->out_is_imm)
1022 vhcr->out_param = out_param;
1027 static struct mlx4_cmd_info cmd_info[] = {
1029 .opcode = MLX4_CMD_QUERY_FW,
1032 .out_is_imm = false,
1033 .encode_slave_id = false,
1035 .wrapper = mlx4_QUERY_FW_wrapper
1038 .opcode = MLX4_CMD_QUERY_HCA,
1041 .out_is_imm = false,
1042 .encode_slave_id = false,
1047 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1050 .out_is_imm = false,
1051 .encode_slave_id = false,
1053 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
1056 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1059 .out_is_imm = false,
1060 .encode_slave_id = false,
1062 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1065 .opcode = MLX4_CMD_QUERY_ADAPTER,
1068 .out_is_imm = false,
1069 .encode_slave_id = false,
1074 .opcode = MLX4_CMD_INIT_PORT,
1076 .has_outbox = false,
1077 .out_is_imm = false,
1078 .encode_slave_id = false,
1080 .wrapper = mlx4_INIT_PORT_wrapper
1083 .opcode = MLX4_CMD_CLOSE_PORT,
1085 .has_outbox = false,
1086 .out_is_imm = false,
1087 .encode_slave_id = false,
1089 .wrapper = mlx4_CLOSE_PORT_wrapper
1092 .opcode = MLX4_CMD_QUERY_PORT,
1095 .out_is_imm = false,
1096 .encode_slave_id = false,
1098 .wrapper = mlx4_QUERY_PORT_wrapper
1101 .opcode = MLX4_CMD_SET_PORT,
1103 .has_outbox = false,
1104 .out_is_imm = false,
1105 .encode_slave_id = false,
1107 .wrapper = mlx4_SET_PORT_wrapper
1110 .opcode = MLX4_CMD_MAP_EQ,
1112 .has_outbox = false,
1113 .out_is_imm = false,
1114 .encode_slave_id = false,
1116 .wrapper = mlx4_MAP_EQ_wrapper
1119 .opcode = MLX4_CMD_SW2HW_EQ,
1121 .has_outbox = false,
1122 .out_is_imm = false,
1123 .encode_slave_id = true,
1125 .wrapper = mlx4_SW2HW_EQ_wrapper
1128 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1130 .has_outbox = false,
1131 .out_is_imm = false,
1132 .encode_slave_id = false,
1137 .opcode = MLX4_CMD_NOP,
1139 .has_outbox = false,
1140 .out_is_imm = false,
1141 .encode_slave_id = false,
1146 .opcode = MLX4_CMD_CONFIG_DEV,
1149 .out_is_imm = false,
1150 .encode_slave_id = false,
1152 .wrapper = mlx4_CONFIG_DEV_wrapper
1155 .opcode = MLX4_CMD_ALLOC_RES,
1157 .has_outbox = false,
1159 .encode_slave_id = false,
1161 .wrapper = mlx4_ALLOC_RES_wrapper
1164 .opcode = MLX4_CMD_FREE_RES,
1166 .has_outbox = false,
1167 .out_is_imm = false,
1168 .encode_slave_id = false,
1170 .wrapper = mlx4_FREE_RES_wrapper
1173 .opcode = MLX4_CMD_SW2HW_MPT,
1175 .has_outbox = false,
1176 .out_is_imm = false,
1177 .encode_slave_id = true,
1179 .wrapper = mlx4_SW2HW_MPT_wrapper
1182 .opcode = MLX4_CMD_QUERY_MPT,
1185 .out_is_imm = false,
1186 .encode_slave_id = false,
1188 .wrapper = mlx4_QUERY_MPT_wrapper
1191 .opcode = MLX4_CMD_HW2SW_MPT,
1193 .has_outbox = false,
1194 .out_is_imm = false,
1195 .encode_slave_id = false,
1197 .wrapper = mlx4_HW2SW_MPT_wrapper
1200 .opcode = MLX4_CMD_READ_MTT,
1203 .out_is_imm = false,
1204 .encode_slave_id = false,
1209 .opcode = MLX4_CMD_WRITE_MTT,
1211 .has_outbox = false,
1212 .out_is_imm = false,
1213 .encode_slave_id = false,
1215 .wrapper = mlx4_WRITE_MTT_wrapper
1218 .opcode = MLX4_CMD_SYNC_TPT,
1220 .has_outbox = false,
1221 .out_is_imm = false,
1222 .encode_slave_id = false,
1227 .opcode = MLX4_CMD_HW2SW_EQ,
1229 .has_outbox = false,
1230 .out_is_imm = false,
1231 .encode_slave_id = true,
1233 .wrapper = mlx4_HW2SW_EQ_wrapper
1236 .opcode = MLX4_CMD_QUERY_EQ,
1239 .out_is_imm = false,
1240 .encode_slave_id = true,
1242 .wrapper = mlx4_QUERY_EQ_wrapper
1245 .opcode = MLX4_CMD_SW2HW_CQ,
1247 .has_outbox = false,
1248 .out_is_imm = false,
1249 .encode_slave_id = true,
1251 .wrapper = mlx4_SW2HW_CQ_wrapper
1254 .opcode = MLX4_CMD_HW2SW_CQ,
1256 .has_outbox = false,
1257 .out_is_imm = false,
1258 .encode_slave_id = false,
1260 .wrapper = mlx4_HW2SW_CQ_wrapper
1263 .opcode = MLX4_CMD_QUERY_CQ,
1266 .out_is_imm = false,
1267 .encode_slave_id = false,
1269 .wrapper = mlx4_QUERY_CQ_wrapper
1272 .opcode = MLX4_CMD_MODIFY_CQ,
1274 .has_outbox = false,
1276 .encode_slave_id = false,
1278 .wrapper = mlx4_MODIFY_CQ_wrapper
1281 .opcode = MLX4_CMD_SW2HW_SRQ,
1283 .has_outbox = false,
1284 .out_is_imm = false,
1285 .encode_slave_id = true,
1287 .wrapper = mlx4_SW2HW_SRQ_wrapper
1290 .opcode = MLX4_CMD_HW2SW_SRQ,
1292 .has_outbox = false,
1293 .out_is_imm = false,
1294 .encode_slave_id = false,
1296 .wrapper = mlx4_HW2SW_SRQ_wrapper
1299 .opcode = MLX4_CMD_QUERY_SRQ,
1302 .out_is_imm = false,
1303 .encode_slave_id = false,
1305 .wrapper = mlx4_QUERY_SRQ_wrapper
1308 .opcode = MLX4_CMD_ARM_SRQ,
1310 .has_outbox = false,
1311 .out_is_imm = false,
1312 .encode_slave_id = false,
1314 .wrapper = mlx4_ARM_SRQ_wrapper
1317 .opcode = MLX4_CMD_RST2INIT_QP,
1319 .has_outbox = false,
1320 .out_is_imm = false,
1321 .encode_slave_id = true,
1323 .wrapper = mlx4_RST2INIT_QP_wrapper
1326 .opcode = MLX4_CMD_INIT2INIT_QP,
1328 .has_outbox = false,
1329 .out_is_imm = false,
1330 .encode_slave_id = false,
1332 .wrapper = mlx4_INIT2INIT_QP_wrapper
1335 .opcode = MLX4_CMD_INIT2RTR_QP,
1337 .has_outbox = false,
1338 .out_is_imm = false,
1339 .encode_slave_id = false,
1341 .wrapper = mlx4_INIT2RTR_QP_wrapper
1344 .opcode = MLX4_CMD_RTR2RTS_QP,
1346 .has_outbox = false,
1347 .out_is_imm = false,
1348 .encode_slave_id = false,
1350 .wrapper = mlx4_RTR2RTS_QP_wrapper
1353 .opcode = MLX4_CMD_RTS2RTS_QP,
1355 .has_outbox = false,
1356 .out_is_imm = false,
1357 .encode_slave_id = false,
1359 .wrapper = mlx4_RTS2RTS_QP_wrapper
1362 .opcode = MLX4_CMD_SQERR2RTS_QP,
1364 .has_outbox = false,
1365 .out_is_imm = false,
1366 .encode_slave_id = false,
1368 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1371 .opcode = MLX4_CMD_2ERR_QP,
1373 .has_outbox = false,
1374 .out_is_imm = false,
1375 .encode_slave_id = false,
1377 .wrapper = mlx4_GEN_QP_wrapper
1380 .opcode = MLX4_CMD_RTS2SQD_QP,
1382 .has_outbox = false,
1383 .out_is_imm = false,
1384 .encode_slave_id = false,
1386 .wrapper = mlx4_GEN_QP_wrapper
1389 .opcode = MLX4_CMD_SQD2SQD_QP,
1391 .has_outbox = false,
1392 .out_is_imm = false,
1393 .encode_slave_id = false,
1395 .wrapper = mlx4_SQD2SQD_QP_wrapper
1398 .opcode = MLX4_CMD_SQD2RTS_QP,
1400 .has_outbox = false,
1401 .out_is_imm = false,
1402 .encode_slave_id = false,
1404 .wrapper = mlx4_SQD2RTS_QP_wrapper
1407 .opcode = MLX4_CMD_2RST_QP,
1409 .has_outbox = false,
1410 .out_is_imm = false,
1411 .encode_slave_id = false,
1413 .wrapper = mlx4_2RST_QP_wrapper
1416 .opcode = MLX4_CMD_QUERY_QP,
1419 .out_is_imm = false,
1420 .encode_slave_id = false,
1422 .wrapper = mlx4_GEN_QP_wrapper
1425 .opcode = MLX4_CMD_SUSPEND_QP,
1427 .has_outbox = false,
1428 .out_is_imm = false,
1429 .encode_slave_id = false,
1431 .wrapper = mlx4_GEN_QP_wrapper
1434 .opcode = MLX4_CMD_UNSUSPEND_QP,
1436 .has_outbox = false,
1437 .out_is_imm = false,
1438 .encode_slave_id = false,
1440 .wrapper = mlx4_GEN_QP_wrapper
1443 .opcode = MLX4_CMD_UPDATE_QP,
1445 .has_outbox = false,
1446 .out_is_imm = false,
1447 .encode_slave_id = false,
1449 .wrapper = mlx4_UPDATE_QP_wrapper
1452 .opcode = MLX4_CMD_GET_OP_REQ,
1454 .has_outbox = false,
1455 .out_is_imm = false,
1456 .encode_slave_id = false,
1458 .wrapper = mlx4_CMD_EPERM_wrapper,
1461 .opcode = MLX4_CMD_ALLOCATE_VPP,
1464 .out_is_imm = false,
1465 .encode_slave_id = false,
1467 .wrapper = mlx4_CMD_EPERM_wrapper,
1470 .opcode = MLX4_CMD_SET_VPORT_QOS,
1473 .out_is_imm = false,
1474 .encode_slave_id = false,
1476 .wrapper = mlx4_CMD_EPERM_wrapper,
1479 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1481 .has_outbox = false,
1482 .out_is_imm = false,
1483 .encode_slave_id = false,
1484 .verify = NULL, /* XXX verify: only demux can do this */
1488 .opcode = MLX4_CMD_MAD_IFC,
1491 .out_is_imm = false,
1492 .encode_slave_id = false,
1494 .wrapper = mlx4_MAD_IFC_wrapper
1497 .opcode = MLX4_CMD_MAD_DEMUX,
1499 .has_outbox = false,
1500 .out_is_imm = false,
1501 .encode_slave_id = false,
1503 .wrapper = mlx4_CMD_EPERM_wrapper
1506 .opcode = MLX4_CMD_QUERY_IF_STAT,
1509 .out_is_imm = false,
1510 .encode_slave_id = false,
1512 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1515 .opcode = MLX4_CMD_ACCESS_REG,
1518 .out_is_imm = false,
1519 .encode_slave_id = false,
1521 .wrapper = mlx4_ACCESS_REG_wrapper,
1524 .opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
1526 .has_outbox = false,
1527 .out_is_imm = false,
1528 .encode_slave_id = false,
1530 .wrapper = mlx4_CMD_EPERM_wrapper,
1532 /* Native multicast commands are not available for guests */
1534 .opcode = MLX4_CMD_QP_ATTACH,
1536 .has_outbox = false,
1537 .out_is_imm = false,
1538 .encode_slave_id = false,
1540 .wrapper = mlx4_QP_ATTACH_wrapper
1543 .opcode = MLX4_CMD_PROMISC,
1545 .has_outbox = false,
1546 .out_is_imm = false,
1547 .encode_slave_id = false,
1549 .wrapper = mlx4_PROMISC_wrapper
1551 /* Ethernet specific commands */
1553 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1555 .has_outbox = false,
1556 .out_is_imm = false,
1557 .encode_slave_id = false,
1559 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1562 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1564 .has_outbox = false,
1565 .out_is_imm = false,
1566 .encode_slave_id = false,
1568 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1571 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1574 .out_is_imm = false,
1575 .encode_slave_id = false,
1577 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1580 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1582 .has_outbox = false,
1583 .out_is_imm = false,
1584 .encode_slave_id = false,
1588 /* flow steering commands */
1590 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1592 .has_outbox = false,
1594 .encode_slave_id = false,
1596 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1599 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1601 .has_outbox = false,
1602 .out_is_imm = false,
1603 .encode_slave_id = false,
1605 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1608 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1610 .has_outbox = false,
1611 .out_is_imm = false,
1612 .encode_slave_id = false,
1614 .wrapper = mlx4_CMD_EPERM_wrapper
1617 .opcode = MLX4_CMD_VIRT_PORT_MAP,
1619 .has_outbox = false,
1620 .out_is_imm = false,
1621 .encode_slave_id = false,
1623 .wrapper = mlx4_CMD_EPERM_wrapper
1627 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1628 struct mlx4_vhcr_cmd *in_vhcr)
1630 struct mlx4_priv *priv = mlx4_priv(dev);
1631 struct mlx4_cmd_info *cmd = NULL;
1632 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1633 struct mlx4_vhcr *vhcr;
1634 struct mlx4_cmd_mailbox *inbox = NULL;
1635 struct mlx4_cmd_mailbox *outbox = NULL;
1642 /* Create sw representation of Virtual HCR */
1643 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1647 /* DMA in the vHCR */
1649 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1650 priv->mfunc.master.slave_state[slave].vhcr_dma,
1651 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1652 MLX4_ACCESS_MEM_ALIGN), 1);
1654 if (!(dev->persist->state &
1655 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1656 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1663 /* Fill SW VHCR fields */
1664 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1665 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1666 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1667 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1668 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1669 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1670 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1672 /* Lookup command */
1673 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1674 if (vhcr->op == cmd_info[i].opcode) {
1680 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1682 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1687 if (cmd->has_inbox) {
1688 vhcr->in_param &= INBOX_MASK;
1689 inbox = mlx4_alloc_cmd_mailbox(dev);
1690 if (IS_ERR(inbox)) {
1691 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1696 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1698 MLX4_MAILBOX_SIZE, 1);
1700 if (!(dev->persist->state &
1701 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1702 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1703 __func__, cmd->opcode);
1704 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1709 /* Apply permission and bound checks if applicable */
1710 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1711 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1712 vhcr->op, slave, vhcr->in_modifier);
1713 vhcr_cmd->status = CMD_STAT_BAD_OP;
1717 /* Allocate outbox */
1718 if (cmd->has_outbox) {
1719 outbox = mlx4_alloc_cmd_mailbox(dev);
1720 if (IS_ERR(outbox)) {
1721 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1727 /* Execute the command! */
1729 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1731 if (cmd->out_is_imm)
1732 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1734 in_param = cmd->has_inbox ? (u64) inbox->dma :
1736 out_param = cmd->has_outbox ? (u64) outbox->dma :
1738 err = __mlx4_cmd(dev, in_param, &out_param,
1739 cmd->out_is_imm, vhcr->in_modifier,
1740 vhcr->op_modifier, vhcr->op,
1741 MLX4_CMD_TIME_CLASS_A,
1744 if (cmd->out_is_imm) {
1745 vhcr->out_param = out_param;
1746 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1751 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR))
1752 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1753 vhcr->op, slave, vhcr->errno, err);
1754 vhcr_cmd->status = mlx4_errno_to_status(err);
1759 /* Write outbox if command completed successfully */
1760 if (cmd->has_outbox && !vhcr_cmd->status) {
1761 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1763 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1765 /* If we failed to write back the outbox after the
1766 *command was successfully executed, we must fail this
1767 * slave, as it is now in undefined state */
1768 if (!(dev->persist->state &
1769 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1770 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1776 /* DMA back vhcr result */
1778 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1779 priv->mfunc.master.slave_state[slave].vhcr_dma,
1780 ALIGN(sizeof(struct mlx4_vhcr),
1781 MLX4_ACCESS_MEM_ALIGN),
1784 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1786 else if (vhcr->e_bit &&
1787 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1788 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1794 mlx4_free_cmd_mailbox(dev, inbox);
1795 mlx4_free_cmd_mailbox(dev, outbox);
1799 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1800 int slave, int port)
1802 struct mlx4_vport_oper_state *vp_oper;
1803 struct mlx4_vport_state *vp_admin;
1804 struct mlx4_vf_immed_vlan_work *work;
1805 struct mlx4_dev *dev = &(priv->dev);
1807 int admin_vlan_ix = NO_INDX;
1809 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1810 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1812 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1813 vp_oper->state.default_qos == vp_admin->default_qos &&
1814 vp_oper->state.link_state == vp_admin->link_state &&
1815 vp_oper->state.qos_vport == vp_admin->qos_vport)
1818 if (!(priv->mfunc.master.slave_state[slave].active &&
1819 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1820 /* even if the UPDATE_QP command isn't supported, we still want
1821 * to set this VF link according to the admin directive
1823 vp_oper->state.link_state = vp_admin->link_state;
1827 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1829 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1830 vp_admin->default_vlan, vp_admin->default_qos,
1831 vp_admin->link_state);
1833 work = kzalloc(sizeof(*work), GFP_KERNEL);
1837 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1838 if (MLX4_VGT != vp_admin->default_vlan) {
1839 err = __mlx4_register_vlan(&priv->dev, port,
1840 vp_admin->default_vlan,
1844 mlx4_warn(&priv->dev,
1845 "No vlan resources slave %d, port %d\n",
1850 admin_vlan_ix = NO_INDX;
1852 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1853 mlx4_dbg(&priv->dev,
1854 "alloc vlan %d idx %d slave %d port %d\n",
1855 (int)(vp_admin->default_vlan),
1856 admin_vlan_ix, slave, port);
1859 /* save original vlan ix and vlan id */
1860 work->orig_vlan_id = vp_oper->state.default_vlan;
1861 work->orig_vlan_ix = vp_oper->vlan_idx;
1863 /* handle new qos */
1864 if (vp_oper->state.default_qos != vp_admin->default_qos)
1865 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1867 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1868 vp_oper->vlan_idx = admin_vlan_ix;
1870 vp_oper->state.default_vlan = vp_admin->default_vlan;
1871 vp_oper->state.default_qos = vp_admin->default_qos;
1872 vp_oper->state.link_state = vp_admin->link_state;
1873 vp_oper->state.qos_vport = vp_admin->qos_vport;
1875 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1876 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1878 /* iterate over QPs owned by this slave, using UPDATE_QP */
1880 work->slave = slave;
1881 work->qos = vp_oper->state.default_qos;
1882 work->qos_vport = vp_oper->state.qos_vport;
1883 work->vlan_id = vp_oper->state.default_vlan;
1884 work->vlan_ix = vp_oper->vlan_idx;
1886 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1887 queue_work(priv->mfunc.master.comm_wq, &work->work);
1892 static void mlx4_set_default_port_qos(struct mlx4_dev *dev, int port)
1894 struct mlx4_qos_manager *port_qos_ctl;
1895 struct mlx4_priv *priv = mlx4_priv(dev);
1897 port_qos_ctl = &priv->mfunc.master.qos_ctl[port];
1898 bitmap_zero(port_qos_ctl->priority_bm, MLX4_NUM_UP);
1900 /* Enable only default prio at PF init routine */
1901 set_bit(MLX4_DEFAULT_QOS_PRIO, port_qos_ctl->priority_bm);
1904 static void mlx4_allocate_port_vpps(struct mlx4_dev *dev, int port)
1910 u8 vpp_param[MLX4_NUM_UP];
1911 struct mlx4_qos_manager *port_qos;
1912 struct mlx4_priv *priv = mlx4_priv(dev);
1914 err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1916 mlx4_info(dev, "Failed query availible VPPs\n");
1920 port_qos = &priv->mfunc.master.qos_ctl[port];
1921 num_vfs = (availible_vpp /
1922 bitmap_weight(port_qos->priority_bm, MLX4_NUM_UP));
1924 for (i = 0; i < MLX4_NUM_UP; i++) {
1925 if (test_bit(i, port_qos->priority_bm))
1926 vpp_param[i] = num_vfs;
1929 err = mlx4_ALLOCATE_VPP_set(dev, port, vpp_param);
1931 mlx4_info(dev, "Failed allocating VPPs\n");
1935 /* Query actual allocated VPP, just to make sure */
1936 err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1938 mlx4_info(dev, "Failed query availible VPPs\n");
1942 port_qos->num_of_qos_vfs = num_vfs;
1943 mlx4_dbg(dev, "Port %d Availible VPPs %d\n", port, availible_vpp);
1945 for (i = 0; i < MLX4_NUM_UP; i++)
1946 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1950 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1953 struct mlx4_vport_state *vp_admin;
1954 struct mlx4_vport_oper_state *vp_oper;
1955 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1957 int min_port = find_first_bit(actv_ports.ports,
1958 priv->dev.caps.num_ports) + 1;
1959 int max_port = min_port - 1 +
1960 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1962 for (port = min_port; port <= max_port; port++) {
1963 if (!test_bit(port - 1, actv_ports.ports))
1965 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1966 priv->mfunc.master.vf_admin[slave].enable_smi[port];
1967 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1968 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1969 vp_oper->state = *vp_admin;
1970 if (MLX4_VGT != vp_admin->default_vlan) {
1971 err = __mlx4_register_vlan(&priv->dev, port,
1972 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1974 vp_oper->vlan_idx = NO_INDX;
1975 mlx4_warn(&priv->dev,
1976 "No vlan resources slave %d, port %d\n",
1980 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
1981 (int)(vp_oper->state.default_vlan),
1982 vp_oper->vlan_idx, slave, port);
1984 if (vp_admin->spoofchk) {
1985 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1988 if (0 > vp_oper->mac_idx) {
1989 err = vp_oper->mac_idx;
1990 vp_oper->mac_idx = NO_INDX;
1991 mlx4_warn(&priv->dev,
1992 "No mac resources slave %d, port %d\n",
1996 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
1997 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
2003 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2006 struct mlx4_vport_oper_state *vp_oper;
2007 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2009 int min_port = find_first_bit(actv_ports.ports,
2010 priv->dev.caps.num_ports) + 1;
2011 int max_port = min_port - 1 +
2012 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2015 for (port = min_port; port <= max_port; port++) {
2016 if (!test_bit(port - 1, actv_ports.ports))
2018 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2019 MLX4_VF_SMI_DISABLED;
2020 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2021 if (NO_INDX != vp_oper->vlan_idx) {
2022 __mlx4_unregister_vlan(&priv->dev,
2023 port, vp_oper->state.default_vlan);
2024 vp_oper->vlan_idx = NO_INDX;
2026 if (NO_INDX != vp_oper->mac_idx) {
2027 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
2028 vp_oper->mac_idx = NO_INDX;
2034 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
2035 u16 param, u8 toggle)
2037 struct mlx4_priv *priv = mlx4_priv(dev);
2038 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2040 u8 is_going_down = 0;
2042 unsigned long flags;
2044 slave_state[slave].comm_toggle ^= 1;
2045 reply = (u32) slave_state[slave].comm_toggle << 31;
2046 if (toggle != slave_state[slave].comm_toggle) {
2047 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
2051 if (cmd == MLX4_COMM_CMD_RESET) {
2052 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
2053 slave_state[slave].active = false;
2054 slave_state[slave].old_vlan_api = false;
2055 mlx4_master_deactivate_admin_state(priv, slave);
2056 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
2057 slave_state[slave].event_eq[i].eqn = -1;
2058 slave_state[slave].event_eq[i].token = 0;
2060 /*check if we are in the middle of FLR process,
2061 if so return "retry" status to the slave*/
2062 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
2063 goto inform_slave_state;
2065 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
2067 /* write the version in the event field */
2068 reply |= mlx4_comm_get_version();
2072 /*command from slave in the middle of FLR*/
2073 if (cmd != MLX4_COMM_CMD_RESET &&
2074 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
2075 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
2081 case MLX4_COMM_CMD_VHCR0:
2082 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
2084 slave_state[slave].vhcr_dma = ((u64) param) << 48;
2085 priv->mfunc.master.slave_state[slave].cookie = 0;
2087 case MLX4_COMM_CMD_VHCR1:
2088 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
2090 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
2092 case MLX4_COMM_CMD_VHCR2:
2093 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
2095 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
2097 case MLX4_COMM_CMD_VHCR_EN:
2098 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
2100 slave_state[slave].vhcr_dma |= param;
2101 if (mlx4_master_activate_admin_state(priv, slave))
2103 slave_state[slave].active = true;
2104 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
2106 case MLX4_COMM_CMD_VHCR_POST:
2107 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
2108 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2109 mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2110 slave, cmd, slave_state[slave].last_cmd);
2114 mutex_lock(&priv->cmd.slave_cmd_mutex);
2115 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
2116 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2118 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2121 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2124 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2127 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2128 if (!slave_state[slave].is_slave_going_down)
2129 slave_state[slave].last_cmd = cmd;
2132 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2133 if (is_going_down) {
2134 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
2138 __raw_writel((__force u32) cpu_to_be32(reply),
2139 &priv->mfunc.comm[slave].slave_read);
2145 /* cleanup any slave resources */
2146 if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2147 mlx4_delete_all_resources_for_slave(dev, slave);
2149 if (cmd != MLX4_COMM_CMD_RESET) {
2150 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2152 /* Turn on internal error letting slave reset itself immeditaly,
2153 * otherwise it might take till timeout on command is passed
2155 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2158 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2159 if (!slave_state[slave].is_slave_going_down)
2160 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
2161 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2162 /*with slave in the middle of flr, no need to clean resources again.*/
2164 memset(&slave_state[slave].event_eq, 0,
2165 sizeof(struct mlx4_slave_event_eq_info));
2166 __raw_writel((__force u32) cpu_to_be32(reply),
2167 &priv->mfunc.comm[slave].slave_read);
2171 /* master command processing */
2172 void mlx4_master_comm_channel(struct work_struct *work)
2174 struct mlx4_mfunc_master_ctx *master =
2176 struct mlx4_mfunc_master_ctx,
2178 struct mlx4_mfunc *mfunc =
2179 container_of(master, struct mlx4_mfunc, master);
2180 struct mlx4_priv *priv =
2181 container_of(mfunc, struct mlx4_priv, mfunc);
2182 struct mlx4_dev *dev = &priv->dev;
2192 bit_vec = master->comm_arm_bit_vector;
2193 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
2194 vec = be32_to_cpu(bit_vec[i]);
2195 for (j = 0; j < 32; j++) {
2196 if (!(vec & (1 << j)))
2199 slave = (i * 32) + j;
2200 comm_cmd = swab32(readl(
2201 &mfunc->comm[slave].slave_write));
2202 slt = swab32(readl(&mfunc->comm[slave].slave_read))
2204 toggle = comm_cmd >> 31;
2205 if (toggle != slt) {
2206 if (master->slave_state[slave].comm_toggle
2208 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2210 master->slave_state[slave].comm_toggle);
2211 master->slave_state[slave].comm_toggle =
2214 mlx4_master_do_cmd(dev, slave,
2215 comm_cmd >> 16 & 0xff,
2216 comm_cmd & 0xffff, toggle);
2222 if (reported && reported != served)
2223 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
2226 if (mlx4_ARM_COMM_CHANNEL(dev))
2227 mlx4_warn(dev, "Failed to arm comm channel events\n");
2230 static int sync_toggles(struct mlx4_dev *dev)
2232 struct mlx4_priv *priv = mlx4_priv(dev);
2237 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2238 if (wr_toggle == 0xffffffff)
2239 end = jiffies + msecs_to_jiffies(30000);
2241 end = jiffies + msecs_to_jiffies(5000);
2243 while (time_before(jiffies, end)) {
2244 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2245 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2246 /* PCI might be offline */
2248 wr_toggle = swab32(readl(&priv->mfunc.comm->
2253 if (rd_toggle >> 31 == wr_toggle >> 31) {
2254 priv->cmd.comm_toggle = rd_toggle >> 31;
2262 * we could reach here if for example the previous VM using this
2263 * function misbehaved and left the channel with unsynced state. We
2264 * should fix this here and give this VM a chance to use a properly
2267 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2268 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2269 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2270 priv->cmd.comm_toggle = 0;
2275 int mlx4_multi_func_init(struct mlx4_dev *dev)
2277 struct mlx4_priv *priv = mlx4_priv(dev);
2278 struct mlx4_slave_state *s_state;
2279 int i, j, err, port;
2281 if (mlx4_is_master(dev))
2283 ioremap(pci_resource_start(dev->persist->pdev,
2284 priv->fw.comm_bar) +
2285 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2288 ioremap(pci_resource_start(dev->persist->pdev, 2) +
2289 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2290 if (!priv->mfunc.comm) {
2291 mlx4_err(dev, "Couldn't map communication vector\n");
2295 if (mlx4_is_master(dev)) {
2296 struct mlx4_vf_oper_state *vf_oper;
2297 struct mlx4_vf_admin_state *vf_admin;
2299 priv->mfunc.master.slave_state =
2300 kzalloc(dev->num_slaves *
2301 sizeof(struct mlx4_slave_state), GFP_KERNEL);
2302 if (!priv->mfunc.master.slave_state)
2305 priv->mfunc.master.vf_admin =
2306 kzalloc(dev->num_slaves *
2307 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2308 if (!priv->mfunc.master.vf_admin)
2309 goto err_comm_admin;
2311 priv->mfunc.master.vf_oper =
2312 kzalloc(dev->num_slaves *
2313 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2314 if (!priv->mfunc.master.vf_oper)
2317 for (i = 0; i < dev->num_slaves; ++i) {
2318 vf_admin = &priv->mfunc.master.vf_admin[i];
2319 vf_oper = &priv->mfunc.master.vf_oper[i];
2320 s_state = &priv->mfunc.master.slave_state[i];
2321 s_state->last_cmd = MLX4_COMM_CMD_RESET;
2322 mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]);
2323 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2324 s_state->event_eq[j].eqn = -1;
2325 __raw_writel((__force u32) 0,
2326 &priv->mfunc.comm[i].slave_write);
2327 __raw_writel((__force u32) 0,
2328 &priv->mfunc.comm[i].slave_read);
2330 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2331 struct mlx4_vport_state *admin_vport;
2332 struct mlx4_vport_state *oper_vport;
2334 s_state->vlan_filter[port] =
2335 kzalloc(sizeof(struct mlx4_vlan_fltr),
2337 if (!s_state->vlan_filter[port]) {
2339 kfree(s_state->vlan_filter[port]);
2343 admin_vport = &vf_admin->vport[port];
2344 oper_vport = &vf_oper->vport[port].state;
2345 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2346 admin_vport->default_vlan = MLX4_VGT;
2347 oper_vport->default_vlan = MLX4_VGT;
2348 admin_vport->qos_vport =
2349 MLX4_VPP_DEFAULT_VPORT;
2350 oper_vport->qos_vport = MLX4_VPP_DEFAULT_VPORT;
2351 vf_oper->vport[port].vlan_idx = NO_INDX;
2352 vf_oper->vport[port].mac_idx = NO_INDX;
2354 spin_lock_init(&s_state->lock);
2357 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP) {
2358 for (port = 1; port <= dev->caps.num_ports; port++) {
2359 if (mlx4_is_eth(dev, port)) {
2360 mlx4_set_default_port_qos(dev, port);
2361 mlx4_allocate_port_vpps(dev, port);
2366 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
2367 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2368 INIT_WORK(&priv->mfunc.master.comm_work,
2369 mlx4_master_comm_channel);
2370 INIT_WORK(&priv->mfunc.master.slave_event_work,
2371 mlx4_gen_slave_eqe);
2372 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2373 mlx4_master_handle_slave_flr);
2374 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2375 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2376 priv->mfunc.master.comm_wq =
2377 create_singlethread_workqueue("mlx4_comm");
2378 if (!priv->mfunc.master.comm_wq)
2381 if (mlx4_init_resource_tracker(dev))
2385 err = sync_toggles(dev);
2387 mlx4_err(dev, "Couldn't sync toggles\n");
2394 flush_workqueue(priv->mfunc.master.comm_wq);
2395 destroy_workqueue(priv->mfunc.master.comm_wq);
2398 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2399 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2401 kfree(priv->mfunc.master.vf_oper);
2403 kfree(priv->mfunc.master.vf_admin);
2405 kfree(priv->mfunc.master.slave_state);
2407 iounmap(priv->mfunc.comm);
2409 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2411 priv->mfunc.vhcr_dma);
2412 priv->mfunc.vhcr = NULL;
2416 int mlx4_cmd_init(struct mlx4_dev *dev)
2418 struct mlx4_priv *priv = mlx4_priv(dev);
2421 if (!priv->cmd.initialized) {
2422 mutex_init(&priv->cmd.slave_cmd_mutex);
2423 sema_init(&priv->cmd.poll_sem, 1);
2424 priv->cmd.use_events = 0;
2425 priv->cmd.toggle = 1;
2426 priv->cmd.initialized = 1;
2427 flags |= MLX4_CMD_CLEANUP_STRUCT;
2430 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
2431 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2432 0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
2433 if (!priv->cmd.hcr) {
2434 mlx4_err(dev, "Couldn't map command register\n");
2437 flags |= MLX4_CMD_CLEANUP_HCR;
2440 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
2441 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2443 &priv->mfunc.vhcr_dma,
2445 if (!priv->mfunc.vhcr)
2448 flags |= MLX4_CMD_CLEANUP_VHCR;
2451 if (!priv->cmd.pool) {
2452 priv->cmd.pool = pci_pool_create("mlx4_cmd",
2455 MLX4_MAILBOX_SIZE, 0);
2456 if (!priv->cmd.pool)
2459 flags |= MLX4_CMD_CLEANUP_POOL;
2465 mlx4_cmd_cleanup(dev, flags);
2469 void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2471 struct mlx4_priv *priv = mlx4_priv(dev);
2475 /* Report an internal error event to all
2476 * communication channels.
2478 for (slave = 0; slave < dev->num_slaves; slave++) {
2479 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2480 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2481 __raw_writel((__force u32)cpu_to_be32(slave_read),
2482 &priv->mfunc.comm[slave].slave_read);
2483 /* Make sure that our comm channel write doesn't
2484 * get mixed in with writes from another CPU.
2490 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2492 struct mlx4_priv *priv = mlx4_priv(dev);
2495 if (mlx4_is_master(dev)) {
2496 flush_workqueue(priv->mfunc.master.comm_wq);
2497 destroy_workqueue(priv->mfunc.master.comm_wq);
2498 for (i = 0; i < dev->num_slaves; i++) {
2499 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2500 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2502 kfree(priv->mfunc.master.slave_state);
2503 kfree(priv->mfunc.master.vf_admin);
2504 kfree(priv->mfunc.master.vf_oper);
2505 dev->num_slaves = 0;
2508 iounmap(priv->mfunc.comm);
2511 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
2513 struct mlx4_priv *priv = mlx4_priv(dev);
2515 if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2516 pci_pool_destroy(priv->cmd.pool);
2517 priv->cmd.pool = NULL;
2520 if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2521 (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
2522 iounmap(priv->cmd.hcr);
2523 priv->cmd.hcr = NULL;
2525 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2526 (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
2527 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2528 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2529 priv->mfunc.vhcr = NULL;
2531 if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2532 priv->cmd.initialized = 0;
2536 * Switch to using events to issue FW commands (can only be called
2537 * after event queue for command events has been initialized).
2539 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2541 struct mlx4_priv *priv = mlx4_priv(dev);
2545 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2546 sizeof (struct mlx4_cmd_context),
2548 if (!priv->cmd.context)
2551 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2552 priv->cmd.context[i].token = i;
2553 priv->cmd.context[i].next = i + 1;
2554 /* To support fatal error flow, initialize all
2555 * cmd contexts to allow simulating completions
2556 * with complete() at any time.
2558 init_completion(&priv->cmd.context[i].done);
2561 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2562 priv->cmd.free_head = 0;
2564 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2565 spin_lock_init(&priv->cmd.context_lock);
2567 for (priv->cmd.token_mask = 1;
2568 priv->cmd.token_mask < priv->cmd.max_cmds;
2569 priv->cmd.token_mask <<= 1)
2571 --priv->cmd.token_mask;
2573 down(&priv->cmd.poll_sem);
2574 priv->cmd.use_events = 1;
2580 * Switch back to polling (used when shutting down the device)
2582 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2584 struct mlx4_priv *priv = mlx4_priv(dev);
2587 priv->cmd.use_events = 0;
2589 for (i = 0; i < priv->cmd.max_cmds; ++i)
2590 down(&priv->cmd.event_sem);
2592 kfree(priv->cmd.context);
2594 up(&priv->cmd.poll_sem);
2597 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2599 struct mlx4_cmd_mailbox *mailbox;
2601 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2603 return ERR_PTR(-ENOMEM);
2605 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2607 if (!mailbox->buf) {
2609 return ERR_PTR(-ENOMEM);
2612 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2616 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2618 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2619 struct mlx4_cmd_mailbox *mailbox)
2624 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2627 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2629 u32 mlx4_comm_get_version(void)
2631 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2634 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2636 if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2637 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2638 vf, dev->persist->num_vfs);
2645 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2647 if (slave < 1 || slave > dev->persist->num_vfs) {
2649 "Bad slave number:%d (number of activated slaves: %lu)\n",
2650 slave, dev->num_slaves);
2656 void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2658 struct mlx4_priv *priv = mlx4_priv(dev);
2659 struct mlx4_cmd_context *context;
2662 spin_lock(&priv->cmd.context_lock);
2663 if (priv->cmd.context) {
2664 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2665 context = &priv->cmd.context[i];
2666 context->fw_status = CMD_STAT_INTERNAL_ERR;
2668 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2669 complete(&context->done);
2672 spin_unlock(&priv->cmd.context_lock);
2675 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2677 struct mlx4_active_ports actv_ports;
2680 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2683 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2687 vf = mlx4_get_vf_indx(dev, slave);
2691 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2692 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2693 dev->caps.num_ports));
2697 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2699 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2702 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2703 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2705 if (port <= 0 || port > m)
2708 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2714 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2716 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2718 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2719 if (test_bit(port - 1, actv_ports.ports))
2721 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2725 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2727 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2731 struct mlx4_slaves_pport slaves_pport;
2733 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2735 if (port <= 0 || port > dev->caps.num_ports)
2736 return slaves_pport;
2738 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2739 struct mlx4_active_ports actv_ports =
2740 mlx4_get_active_ports(dev, i);
2741 if (test_bit(port - 1, actv_ports.ports))
2742 set_bit(i, slaves_pport.slaves);
2745 return slaves_pport;
2747 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2749 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2750 struct mlx4_dev *dev,
2751 const struct mlx4_active_ports *crit_ports)
2754 struct mlx4_slaves_pport slaves_pport;
2756 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2758 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2759 struct mlx4_active_ports actv_ports =
2760 mlx4_get_active_ports(dev, i);
2761 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2762 dev->caps.num_ports))
2763 set_bit(i, slaves_pport.slaves);
2766 return slaves_pport;
2768 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2770 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2772 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2773 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2775 int max_port = min_port +
2776 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2778 if (port < min_port)
2780 else if (port >= max_port)
2781 port = max_port - 1;
2786 static int mlx4_set_vport_qos(struct mlx4_priv *priv, int slave, int port,
2791 struct mlx4_qos_manager *port_qos;
2792 struct mlx4_dev *dev = &priv->dev;
2793 struct mlx4_vport_qos_param vpp_qos[MLX4_NUM_UP];
2795 port_qos = &priv->mfunc.master.qos_ctl[port];
2796 memset(vpp_qos, 0, sizeof(struct mlx4_vport_qos_param) * MLX4_NUM_UP);
2798 if (slave > port_qos->num_of_qos_vfs) {
2799 mlx4_info(dev, "No availible VPP resources for this VF\n");
2803 /* Query for default QoS values from Vport 0 is needed */
2804 err = mlx4_SET_VPORT_QOS_get(dev, port, 0, vpp_qos);
2806 mlx4_info(dev, "Failed to query Vport 0 QoS values\n");
2810 for (i = 0; i < MLX4_NUM_UP; i++) {
2811 if (test_bit(i, port_qos->priority_bm) && max_tx_rate) {
2812 vpp_qos[i].max_avg_bw = max_tx_rate;
2813 vpp_qos[i].enable = 1;
2815 /* if user supplied tx_rate == 0, meaning no rate limit
2816 * configuration is required. so we are leaving the
2817 * value of max_avg_bw as queried from Vport 0.
2819 vpp_qos[i].enable = 0;
2823 err = mlx4_SET_VPORT_QOS_set(dev, port, slave, vpp_qos);
2825 mlx4_info(dev, "Failed to set Vport %d QoS values\n", slave);
2832 static bool mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev *dev, int port,
2833 struct mlx4_vport_state *vf_admin)
2835 struct mlx4_qos_manager *info;
2836 struct mlx4_priv *priv = mlx4_priv(dev);
2838 if (!mlx4_is_master(dev) ||
2839 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2842 info = &priv->mfunc.master.qos_ctl[port];
2844 if (vf_admin->default_vlan != MLX4_VGT &&
2845 test_bit(vf_admin->default_qos, info->priority_bm))
2851 static bool mlx4_valid_vf_state_change(struct mlx4_dev *dev, int port,
2852 struct mlx4_vport_state *vf_admin,
2855 struct mlx4_vport_state dummy_admin = {0};
2857 if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) ||
2861 dummy_admin.default_qos = qos;
2862 dummy_admin.default_vlan = vlan;
2864 /* VF wants to move to other VST state which is valid with current
2865 * rate limit. Either differnt default vlan in VST or other
2866 * supported QoS priority. Otherwise we don't allow this change when
2867 * the TX rate is still configured.
2869 if (mlx4_is_vf_vst_and_prio_qos(dev, port, &dummy_admin))
2872 mlx4_info(dev, "Cannot change VF state to %s while rate is set\n",
2873 (vlan == MLX4_VGT) ? "VGT" : "VST");
2875 if (vlan != MLX4_VGT)
2876 mlx4_info(dev, "VST priority %d not supported for QoS\n", qos);
2878 mlx4_info(dev, "Please set rate to 0 prior to this VF state change\n");
2883 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2885 struct mlx4_priv *priv = mlx4_priv(dev);
2886 struct mlx4_vport_state *s_info;
2889 if (!mlx4_is_master(dev))
2890 return -EPROTONOSUPPORT;
2892 slave = mlx4_get_slave_indx(dev, vf);
2896 port = mlx4_slaves_closest_port(dev, slave, port);
2897 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2899 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2900 vf, port, s_info->mac);
2903 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2906 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2908 struct mlx4_priv *priv = mlx4_priv(dev);
2909 struct mlx4_vport_state *vf_admin;
2912 if ((!mlx4_is_master(dev)) ||
2913 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2914 return -EPROTONOSUPPORT;
2916 if ((vlan > 4095) || (qos > 7))
2919 slave = mlx4_get_slave_indx(dev, vf);
2923 port = mlx4_slaves_closest_port(dev, slave, port);
2924 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2926 if (!mlx4_valid_vf_state_change(dev, port, vf_admin, vlan, qos))
2929 if ((0 == vlan) && (0 == qos))
2930 vf_admin->default_vlan = MLX4_VGT;
2932 vf_admin->default_vlan = vlan;
2933 vf_admin->default_qos = qos;
2935 /* If rate was configured prior to VST, we saved the configured rate
2936 * in vf_admin->rate and now, if priority supported we enforce the QoS
2938 if (mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) &&
2940 vf_admin->qos_vport = slave;
2942 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2944 "updating vf %d port %d config will take effect on next VF restart\n",
2948 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2950 int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate,
2955 struct mlx4_vport_state *vf_admin;
2956 struct mlx4_priv *priv = mlx4_priv(dev);
2958 if (!mlx4_is_master(dev) ||
2959 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2960 return -EPROTONOSUPPORT;
2963 mlx4_info(dev, "Minimum BW share not supported\n");
2964 return -EPROTONOSUPPORT;
2967 slave = mlx4_get_slave_indx(dev, vf);
2971 port = mlx4_slaves_closest_port(dev, slave, port);
2972 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2974 err = mlx4_set_vport_qos(priv, slave, port, max_tx_rate);
2976 mlx4_info(dev, "vf %d failed to set rate %d\n", vf,
2981 vf_admin->tx_rate = max_tx_rate;
2982 /* if VF is not in supported mode (VST with supported prio),
2983 * we do not change vport configuration for its QPs, but save
2984 * the rate, so it will be enforced when it moves to supported
2987 if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin)) {
2989 "rate set for VF %d when not in valid state\n", vf);
2991 if (vf_admin->default_vlan != MLX4_VGT)
2992 mlx4_info(dev, "VST priority not supported by QoS\n");
2994 mlx4_info(dev, "VF in VGT mode (needed VST)\n");
2997 "rate %d take affect when VF moves to valid state\n",
3002 /* If user sets rate 0 assigning default vport for its QPs */
3003 vf_admin->qos_vport = max_tx_rate ? slave : MLX4_VPP_DEFAULT_VPORT;
3005 if (priv->mfunc.master.slave_state[slave].active &&
3006 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)
3007 mlx4_master_immediate_activate_vlan_qos(priv, slave, port);
3011 EXPORT_SYMBOL_GPL(mlx4_set_vf_rate);
3013 /* mlx4_get_slave_default_vlan -
3014 * return true if VST ( default vlan)
3015 * if VST, will return vlan & qos (if not NULL)
3017 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
3020 struct mlx4_vport_oper_state *vp_oper;
3021 struct mlx4_priv *priv;
3023 priv = mlx4_priv(dev);
3024 port = mlx4_slaves_closest_port(dev, slave, port);
3025 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3027 if (MLX4_VGT != vp_oper->state.default_vlan) {
3029 *vlan = vp_oper->state.default_vlan;
3031 *qos = vp_oper->state.default_qos;
3036 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
3038 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
3040 struct mlx4_priv *priv = mlx4_priv(dev);
3041 struct mlx4_vport_state *s_info;
3044 if ((!mlx4_is_master(dev)) ||
3045 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
3046 return -EPROTONOSUPPORT;
3048 slave = mlx4_get_slave_indx(dev, vf);
3052 port = mlx4_slaves_closest_port(dev, slave, port);
3053 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3054 s_info->spoofchk = setting;
3058 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
3060 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
3062 struct mlx4_priv *priv = mlx4_priv(dev);
3063 struct mlx4_vport_state *s_info;
3066 if (!mlx4_is_master(dev))
3067 return -EPROTONOSUPPORT;
3069 slave = mlx4_get_slave_indx(dev, vf);
3073 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3076 /* need to convert it to a func */
3077 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
3078 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
3079 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
3080 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
3081 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
3082 ivf->mac[5] = ((s_info->mac) & 0xff);
3084 ivf->vlan = s_info->default_vlan;
3085 ivf->qos = s_info->default_qos;
3087 if (mlx4_is_vf_vst_and_prio_qos(dev, port, s_info))
3088 ivf->max_tx_rate = s_info->tx_rate;
3090 ivf->max_tx_rate = 0;
3092 ivf->min_tx_rate = 0;
3093 ivf->spoofchk = s_info->spoofchk;
3094 ivf->linkstate = s_info->link_state;
3098 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
3100 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
3102 struct mlx4_priv *priv = mlx4_priv(dev);
3103 struct mlx4_vport_state *s_info;
3107 slave = mlx4_get_slave_indx(dev, vf);
3111 port = mlx4_slaves_closest_port(dev, slave, port);
3112 switch (link_state) {
3113 case IFLA_VF_LINK_STATE_AUTO:
3114 /* get current link state */
3115 if (!priv->sense.do_sense_port[port])
3116 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3118 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3121 case IFLA_VF_LINK_STATE_ENABLE:
3122 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3125 case IFLA_VF_LINK_STATE_DISABLE:
3126 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3130 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
3131 link_state, slave, port);
3134 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3135 s_info->link_state = link_state;
3138 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
3140 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3142 "updating vf %d port %d no link state HW enforcment\n",
3146 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
3148 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
3150 struct mlx4_priv *priv = mlx4_priv(dev);
3152 if (slave < 1 || slave >= dev->num_slaves ||
3153 port < 1 || port > MLX4_MAX_PORTS)
3156 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
3157 MLX4_VF_SMI_ENABLED;
3159 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
3161 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
3163 struct mlx4_priv *priv = mlx4_priv(dev);
3165 if (slave == mlx4_master_func_num(dev))
3168 if (slave < 1 || slave >= dev->num_slaves ||
3169 port < 1 || port > MLX4_MAX_PORTS)
3172 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
3173 MLX4_VF_SMI_ENABLED;
3175 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
3177 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
3180 struct mlx4_priv *priv = mlx4_priv(dev);
3182 if (slave == mlx4_master_func_num(dev))
3185 if (slave < 1 || slave >= dev->num_slaves ||
3186 port < 1 || port > MLX4_MAX_PORTS ||
3187 enabled < 0 || enabled > 1)
3190 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
3193 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);