drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/mlx4/device.h>
  43 #include <linux/semaphore.h>
  44 #include <rdma/ib_smi.h>
  45 #include <linux/delay.h>
  46
  47 #include <asm/io.h>
  48
  49 #include "mlx4.h"
  50 #include "fw.h"
  51 #include "fw_qos.h"
  52
  53 #define CMD_POLL_TOKEN 0xffff
  54 #define INBOX_MASK      0xffffffffffffff00ULL
  55
  56 #define CMD_CHAN_VER 1
  57 #define CMD_CHAN_IF_REV 1
  58
  59 enum {
  60         /* command completed successfully: */
  61         CMD_STAT_OK             = 0x00,
  62         /* Internal error (such as a bus error) occurred while processing command: */
  63         CMD_STAT_INTERNAL_ERR   = 0x01,
  64         /* Operation/command not supported or opcode modifier not supported: */
  65         CMD_STAT_BAD_OP         = 0x02,
  66         /* Parameter not supported or parameter out of range: */
  67         CMD_STAT_BAD_PARAM      = 0x03,
  68         /* System not enabled or bad system state: */
  69         CMD_STAT_BAD_SYS_STATE  = 0x04,
  70         /* Attempt to access reserved or unallocaterd resource: */
  71         CMD_STAT_BAD_RESOURCE   = 0x05,
  72         /* Requested resource is currently executing a command, or is otherwise busy: */
  73         CMD_STAT_RESOURCE_BUSY  = 0x06,
  74         /* Required capability exceeds device limits: */
  75         CMD_STAT_EXCEED_LIM     = 0x08,
  76         /* Resource is not in the appropriate state or ownership: */
  77         CMD_STAT_BAD_RES_STATE  = 0x09,
  78         /* Index out of range: */
  79         CMD_STAT_BAD_INDEX      = 0x0a,
  80         /* FW image corrupted: */
  81         CMD_STAT_BAD_NVMEM      = 0x0b,
  82         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  83         CMD_STAT_ICM_ERROR      = 0x0c,
  84         /* Attempt to modify a QP/EE which is not in the presumed state: */
  85         CMD_STAT_BAD_QP_STATE   = 0x10,
  86         /* Bad segment parameters (Address/Size): */
  87         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  88         /* Memory Region has Memory Windows bound to: */
  89         CMD_STAT_REG_BOUND      = 0x21,
  90         /* HCA local attached memory not present: */
  91         CMD_STAT_LAM_NOT_PRE    = 0x22,
  92         /* Bad management packet (silently discarded): */
  93         CMD_STAT_BAD_PKT        = 0x30,
  94         /* More outstanding CQEs in CQ than new CQ size: */
  95         CMD_STAT_BAD_SIZE       = 0x40,
  96         /* Multi Function device support required: */
  97         CMD_STAT_MULTI_FUNC_REQ = 0x50,
  98 };
  99
 100 enum {
 101         HCR_IN_PARAM_OFFSET     = 0x00,
 102         HCR_IN_MODIFIER_OFFSET  = 0x08,
 103         HCR_OUT_PARAM_OFFSET    = 0x0c,
 104         HCR_TOKEN_OFFSET        = 0x14,
 105         HCR_STATUS_OFFSET       = 0x18,
 106
 107         HCR_OPMOD_SHIFT         = 12,
 108         HCR_T_BIT               = 21,
 109         HCR_E_BIT               = 22,
 110         HCR_GO_BIT              = 23
 111 };
 112
 113 enum {
 114         GO_BIT_TIMEOUT_MSECS    = 10000
 115 };
 116
 117 enum mlx4_vlan_transition {
 118         MLX4_VLAN_TRANSITION_VST_VST = 0,
 119         MLX4_VLAN_TRANSITION_VST_VGT = 1,
 120         MLX4_VLAN_TRANSITION_VGT_VST = 2,
 121         MLX4_VLAN_TRANSITION_VGT_VGT = 3,
 122 };
 123
 124
 125 struct mlx4_cmd_context {
 126         struct completion       done;
 127         int                     result;
 128         int                     next;
 129         u64                     out_param;
 130         u16                     token;
 131         u8                      fw_status;
 132 };
 133
 134 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 135                                     struct mlx4_vhcr_cmd *in_vhcr);
 136
 137 static int mlx4_status_to_errno(u8 status)
 138 {
 139         static const int trans_table[] = {
 140                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 141                 [CMD_STAT_BAD_OP]         = -EPERM,
 142                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 143                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 144                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 145                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 146                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 147                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 148                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 149                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 150                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 151                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 152                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 153                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 154                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 155                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 156                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 157                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 158         };
 159
 160         if (status >= ARRAY_SIZE(trans_table) ||
 161             (status != CMD_STAT_OK && trans_table[status] == 0))
 162                 return -EIO;
 163
 164         return trans_table[status];
 165 }
 166
 167 static u8 mlx4_errno_to_status(int errno)
 168 {
 169         switch (errno) {
 170         case -EPERM:
 171                 return CMD_STAT_BAD_OP;
 172         case -EINVAL:
 173                 return CMD_STAT_BAD_PARAM;
 174         case -ENXIO:
 175                 return CMD_STAT_BAD_SYS_STATE;
 176         case -EBUSY:
 177                 return CMD_STAT_RESOURCE_BUSY;
 178         case -ENOMEM:
 179                 return CMD_STAT_EXCEED_LIM;
 180         case -ENFILE:
 181                 return CMD_STAT_ICM_ERROR;
 182         default:
 183                 return CMD_STAT_INTERNAL_ERR;
 184         }
 185 }
 186
 187 static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
 188                                        u8 op_modifier)
 189 {
 190         switch (op) {
 191         case MLX4_CMD_UNMAP_ICM:
 192         case MLX4_CMD_UNMAP_ICM_AUX:
 193         case MLX4_CMD_UNMAP_FA:
 194         case MLX4_CMD_2RST_QP:
 195         case MLX4_CMD_HW2SW_EQ:
 196         case MLX4_CMD_HW2SW_CQ:
 197         case MLX4_CMD_HW2SW_SRQ:
 198         case MLX4_CMD_HW2SW_MPT:
 199         case MLX4_CMD_CLOSE_HCA:
 200         case MLX4_QP_FLOW_STEERING_DETACH:
 201         case MLX4_CMD_FREE_RES:
 202         case MLX4_CMD_CLOSE_PORT:
 203                 return CMD_STAT_OK;
 204
 205         case MLX4_CMD_QP_ATTACH:
 206                 /* On Detach case return success */
 207                 if (op_modifier == 0)
 208                         return CMD_STAT_OK;
 209                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 210
 211         default:
 212                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 213         }
 214 }
 215
 216 static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
 217 {
 218         /* Any error during the closing commands below is considered fatal */
 219         if (op == MLX4_CMD_CLOSE_HCA ||
 220             op == MLX4_CMD_HW2SW_EQ ||
 221             op == MLX4_CMD_HW2SW_CQ ||
 222             op == MLX4_CMD_2RST_QP ||
 223             op == MLX4_CMD_HW2SW_SRQ ||
 224             op == MLX4_CMD_SYNC_TPT ||
 225             op == MLX4_CMD_UNMAP_ICM ||
 226             op == MLX4_CMD_UNMAP_ICM_AUX ||
 227             op == MLX4_CMD_UNMAP_FA)
 228                 return 1;
 229         /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
 230           * CMD_STAT_REG_BOUND.
 231           * This status indicates that memory region has memory windows bound to it
 232           * which may result from invalid user space usage and is not fatal.
 233           */
 234         if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
 235                 return 1;
 236         return 0;
 237 }
 238
 239 static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
 240                                int err)
 241 {
 242         /* Only if reset flow is really active return code is based on
 243           * command, otherwise current error code is returned.
 244           */
 245         if (mlx4_internal_err_reset) {
 246                 mlx4_enter_error_state(dev->persist);
 247                 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 248         }
 249
 250         return err;
 251 }
 252
 253 static int comm_pending(struct mlx4_dev *dev)
 254 {
 255         struct mlx4_priv *priv = mlx4_priv(dev);
 256         u32 status = readl(&priv->mfunc.comm->slave_read);
 257
 258         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 259 }
 260
 261 static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 262 {
 263         struct mlx4_priv *priv = mlx4_priv(dev);
 264         u32 val;
 265
 266         /* To avoid writing to unknown addresses after the device state was
 267          * changed to internal error and the function was rest,
 268          * check the INTERNAL_ERROR flag which is updated under
 269          * device_state_mutex lock.
 270          */
 271         mutex_lock(&dev->persist->device_state_mutex);
 272
 273         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 274                 mutex_unlock(&dev->persist->device_state_mutex);
 275                 return -EIO;
 276         }
 277
 278         priv->cmd.comm_toggle ^= 1;
 279         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 280         __raw_writel((__force u32) cpu_to_be32(val),
 281                      &priv->mfunc.comm->slave_write);
 282         mmiowb();
 283         mutex_unlock(&dev->persist->device_state_mutex);
 284         return 0;
 285 }
 286
 287 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 288                        unsigned long timeout)
 289 {
 290         struct mlx4_priv *priv = mlx4_priv(dev);
 291         unsigned long end;
 292         int err = 0;
 293         int ret_from_pending = 0;
 294
 295         /* First, verify that the master reports correct status */
 296         if (comm_pending(dev)) {
 297                 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
 298                           priv->cmd.comm_toggle, cmd);
 299                 return -EAGAIN;
 300         }
 301
 302         /* Write command */
 303         down(&priv->cmd.poll_sem);
 304         if (mlx4_comm_cmd_post(dev, cmd, param)) {
 305                 /* Only in case the device state is INTERNAL_ERROR,
 306                  * mlx4_comm_cmd_post returns with an error
 307                  */
 308                 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 309                 goto out;
 310         }
 311
 312         end = msecs_to_jiffies(timeout) + jiffies;
 313         while (comm_pending(dev) && time_before(jiffies, end))
 314                 cond_resched();
 315         ret_from_pending = comm_pending(dev);
 316         if (ret_from_pending) {
 317                 /* check if the slave is trying to boot in the middle of
 318                  * FLR process. The only non-zero result in the RESET command
 319                  * is MLX4_DELAY_RESET_SLAVE*/
 320                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 321                         err = MLX4_DELAY_RESET_SLAVE;
 322                         goto out;
 323                 } else {
 324                         mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
 325                                   cmd);
 326                         err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 327                 }
 328         }
 329
 330         if (err)
 331                 mlx4_enter_error_state(dev->persist);
 332 out:
 333         up(&priv->cmd.poll_sem);
 334         return err;
 335 }
 336
 337 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
 338                               u16 param, u16 op, unsigned long timeout)
 339 {
 340         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 341         struct mlx4_cmd_context *context;
 342         unsigned long end;
 343         int err = 0;
 344
 345         down(&cmd->event_sem);
 346
 347         spin_lock(&cmd->context_lock);
 348         BUG_ON(cmd->free_head < 0);
 349         context = &cmd->context[cmd->free_head];
 350         context->token += cmd->token_mask + 1;
 351         cmd->free_head = context->next;
 352         spin_unlock(&cmd->context_lock);
 353
 354         reinit_completion(&context->done);
 355
 356         if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
 357                 /* Only in case the device state is INTERNAL_ERROR,
 358                  * mlx4_comm_cmd_post returns with an error
 359                  */
 360                 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 361                 goto out;
 362         }
 363
 364         if (!wait_for_completion_timeout(&context->done,
 365                                          msecs_to_jiffies(timeout))) {
 366                 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
 367                           vhcr_cmd, op);
 368                 goto out_reset;
 369         }
 370
 371         err = context->result;
 372         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 373                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 374                          vhcr_cmd, context->fw_status);
 375                 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
 376                         goto out_reset;
 377         }
 378
 379         /* wait for comm channel ready
 380          * this is necessary for prevention the race
 381          * when switching between event to polling mode
 382          * Skipping this section in case the device is in FATAL_ERROR state,
 383          * In this state, no commands are sent via the comm channel until
 384          * the device has returned from reset.
 385          */
 386         if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
 387                 end = msecs_to_jiffies(timeout) + jiffies;
 388                 while (comm_pending(dev) && time_before(jiffies, end))
 389                         cond_resched();
 390         }
 391         goto out;
 392
 393 out_reset:
 394         err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 395         mlx4_enter_error_state(dev->persist);
 396 out:
 397         spin_lock(&cmd->context_lock);
 398         context->next = cmd->free_head;
 399         cmd->free_head = context - cmd->context;
 400         spin_unlock(&cmd->context_lock);
 401
 402         up(&cmd->event_sem);
 403         return err;
 404 }
 405
 406 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 407                   u16 op, unsigned long timeout)
 408 {
 409         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 410                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 411
 412         if (mlx4_priv(dev)->cmd.use_events)
 413                 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
 414         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 415 }
 416
 417 static int cmd_pending(struct mlx4_dev *dev)
 418 {
 419         u32 status;
 420
 421         if (pci_channel_offline(dev->persist->pdev))
 422                 return -EIO;
 423
 424         status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 425
 426         return (status & swab32(1 << HCR_GO_BIT)) ||
 427                 (mlx4_priv(dev)->cmd.toggle ==
 428                  !!(status & swab32(1 << HCR_T_BIT)));
 429 }
 430
 431 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 432                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 433                          int event)
 434 {
 435         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 436         u32 __iomem *hcr = cmd->hcr;
 437         int ret = -EIO;
 438         unsigned long end;
 439
 440         mutex_lock(&dev->persist->device_state_mutex);
 441         /* To avoid writing to unknown addresses after the device state was
 442           * changed to internal error and the chip was reset,
 443           * check the INTERNAL_ERROR flag which is updated under
 444           * device_state_mutex lock.
 445           */
 446         if (pci_channel_offline(dev->persist->pdev) ||
 447             (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
 448                 /*
 449                  * Device is going through error recovery
 450                  * and cannot accept commands.
 451                  */
 452                 goto out;
 453         }
 454
 455         end = jiffies;
 456         if (event)
 457                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 458
 459         while (cmd_pending(dev)) {
 460                 if (pci_channel_offline(dev->persist->pdev)) {
 461                         /*
 462                          * Device is going through error recovery
 463                          * and cannot accept commands.
 464                          */
 465                         goto out;
 466                 }
 467
 468                 if (time_after_eq(jiffies, end)) {
 469                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 470                         goto out;
 471                 }
 472                 cond_resched();
 473         }
 474
 475         /*
 476          * We use writel (instead of something like memcpy_toio)
 477          * because writes of less than 32 bits to the HCR don't work
 478          * (and some architectures such as ia64 implement memcpy_toio
 479          * in terms of writeb).
 480          */
 481         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 482         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 483         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 484         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 485         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 486         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 487
 488         /* __raw_writel may not order writes. */
 489         wmb();
 490
 491         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 492                                                (cmd->toggle << HCR_T_BIT)       |
 493                                                (event ? (1 << HCR_E_BIT) : 0)   |
 494                                                (op_modifier << HCR_OPMOD_SHIFT) |
 495                                                op), hcr + 6);
 496
 497         /*
 498          * Make sure that our HCR writes don't get mixed in with
 499          * writes from another CPU starting a FW command.
 500          */
 501         mmiowb();
 502
 503         cmd->toggle = cmd->toggle ^ 1;
 504
 505         ret = 0;
 506
 507 out:
 508         if (ret)
 509                 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
 510                           op, ret, in_param, in_modifier, op_modifier);
 511         mutex_unlock(&dev->persist->device_state_mutex);
 512
 513         return ret;
 514 }
 515
 516 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 517                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 518                           u16 op, unsigned long timeout)
 519 {
 520         struct mlx4_priv *priv = mlx4_priv(dev);
 521         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 522         int ret;
 523
 524         mutex_lock(&priv->cmd.slave_cmd_mutex);
 525
 526         vhcr->in_param = cpu_to_be64(in_param);
 527         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 528         vhcr->in_modifier = cpu_to_be32(in_modifier);
 529         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 530         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 531         vhcr->status = 0;
 532         vhcr->flags = !!(priv->cmd.use_events) << 6;
 533
 534         if (mlx4_is_master(dev)) {
 535                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 536                 if (!ret) {
 537                         if (out_is_imm) {
 538                                 if (out_param)
 539                                         *out_param =
 540                                                 be64_to_cpu(vhcr->out_param);
 541                                 else {
 542                                         mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 543                                                  op);
 544                                         vhcr->status = CMD_STAT_BAD_PARAM;
 545                                 }
 546                         }
 547                         ret = mlx4_status_to_errno(vhcr->status);
 548                 }
 549                 if (ret &&
 550                     dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 551                         ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
 552         } else {
 553                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
 554                                     MLX4_COMM_TIME + timeout);
 555                 if (!ret) {
 556                         if (out_is_imm) {
 557                                 if (out_param)
 558                                         *out_param =
 559                                                 be64_to_cpu(vhcr->out_param);
 560                                 else {
 561                                         mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 562                                                  op);
 563                                         vhcr->status = CMD_STAT_BAD_PARAM;
 564                                 }
 565                         }
 566                         ret = mlx4_status_to_errno(vhcr->status);
 567                 } else {
 568                         if (dev->persist->state &
 569                             MLX4_DEVICE_STATE_INTERNAL_ERROR)
 570                                 ret = mlx4_internal_err_ret_value(dev, op,
 571                                                                   op_modifier);
 572                         else
 573                                 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
 574                 }
 575         }
 576
 577         mutex_unlock(&priv->cmd.slave_cmd_mutex);
 578         return ret;
 579 }
 580
 581 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 582                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 583                          u16 op, unsigned long timeout)
 584 {
 585         struct mlx4_priv *priv = mlx4_priv(dev);
 586         void __iomem *hcr = priv->cmd.hcr;
 587         int err = 0;
 588         unsigned long end;
 589         u32 stat;
 590
 591         down(&priv->cmd.poll_sem);
 592
 593         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 594                 /*
 595                  * Device is going through error recovery
 596                  * and cannot accept commands.
 597                  */
 598                 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 599                 goto out;
 600         }
 601
 602         if (out_is_imm && !out_param) {
 603                 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 604                          op);
 605                 err = -EINVAL;
 606                 goto out;
 607         }
 608
 609         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 610                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 611         if (err)
 612                 goto out_reset;
 613
 614         end = msecs_to_jiffies(timeout) + jiffies;
 615         while (cmd_pending(dev) && time_before(jiffies, end)) {
 616                 if (pci_channel_offline(dev->persist->pdev)) {
 617                         /*
 618                          * Device is going through error recovery
 619                          * and cannot accept commands.
 620                          */
 621                         err = -EIO;
 622                         goto out_reset;
 623                 }
 624
 625                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 626                         err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 627                         goto out;
 628                 }
 629
 630                 cond_resched();
 631         }
 632
 633         if (cmd_pending(dev)) {
 634                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 635                           op);
 636                 err = -EIO;
 637                 goto out_reset;
 638         }
 639
 640         if (out_is_imm)
 641                 *out_param =
 642                         (u64) be32_to_cpu((__force __be32)
 643                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 644                         (u64) be32_to_cpu((__force __be32)
 645                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 646         stat = be32_to_cpu((__force __be32)
 647                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 648         err = mlx4_status_to_errno(stat);
 649         if (err) {
 650                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 651                          op, stat);
 652                 if (mlx4_closing_cmd_fatal_error(op, stat))
 653                         goto out_reset;
 654                 goto out;
 655         }
 656
 657 out_reset:
 658         if (err)
 659                 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
 660 out:
 661         up(&priv->cmd.poll_sem);
 662         return err;
 663 }
 664
 665 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 666 {
 667         struct mlx4_priv *priv = mlx4_priv(dev);
 668         struct mlx4_cmd_context *context =
 669                 &priv->cmd.context[token & priv->cmd.token_mask];
 670
 671         /* previously timed out command completing at long last */
 672         if (token != context->token)
 673                 return;
 674
 675         context->fw_status = status;
 676         context->result    = mlx4_status_to_errno(status);
 677         context->out_param = out_param;
 678
 679         complete(&context->done);
 680 }
 681
 682 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 683                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 684                          u16 op, unsigned long timeout)
 685 {
 686         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 687         struct mlx4_cmd_context *context;
 688         int err = 0;
 689
 690         down(&cmd->event_sem);
 691
 692         spin_lock(&cmd->context_lock);
 693         BUG_ON(cmd->free_head < 0);
 694         context = &cmd->context[cmd->free_head];
 695         context->token += cmd->token_mask + 1;
 696         cmd->free_head = context->next;
 697         spin_unlock(&cmd->context_lock);
 698
 699         if (out_is_imm && !out_param) {
 700                 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 701                          op);
 702                 err = -EINVAL;
 703                 goto out;
 704         }
 705
 706         reinit_completion(&context->done);
 707
 708         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 709                             in_modifier, op_modifier, op, context->token, 1);
 710         if (err)
 711                 goto out_reset;
 712
 713         if (!wait_for_completion_timeout(&context->done,
 714                                          msecs_to_jiffies(timeout))) {
 715                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 716                           op);
 717                 err = -EIO;
 718                 goto out_reset;
 719         }
 720
 721         err = context->result;
 722         if (err) {
 723                 /* Since we do not want to have this error message always
 724                  * displayed at driver start when there are ConnectX2 HCAs
 725                  * on the host, we deprecate the error message for this
 726                  * specific command/input_mod/opcode_mod/fw-status to be debug.
 727                  */
 728                 if (op == MLX4_CMD_SET_PORT &&
 729                     (in_modifier == 1 || in_modifier == 2) &&
 730                     op_modifier == MLX4_SET_PORT_IB_OPCODE &&
 731                     context->fw_status == CMD_STAT_BAD_SIZE)
 732                         mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
 733                                  op, context->fw_status);
 734                 else
 735                         mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 736                                  op, context->fw_status);
 737                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 738                         err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 739                 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
 740                         goto out_reset;
 741
 742                 goto out;
 743         }
 744
 745         if (out_is_imm)
 746                 *out_param = context->out_param;
 747
 748 out_reset:
 749         if (err)
 750                 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
 751 out:
 752         spin_lock(&cmd->context_lock);
 753         context->next = cmd->free_head;
 754         cmd->free_head = context - cmd->context;
 755         spin_unlock(&cmd->context_lock);
 756
 757         up(&cmd->event_sem);
 758         return err;
 759 }
 760
 761 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 762                int out_is_imm, u32 in_modifier, u8 op_modifier,
 763                u16 op, unsigned long timeout, int native)
 764 {
 765         if (pci_channel_offline(dev->persist->pdev))
 766                 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
 767
 768         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 769                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 770                         return mlx4_internal_err_ret_value(dev, op,
 771                                                           op_modifier);
 772                 if (mlx4_priv(dev)->cmd.use_events)
 773                         return mlx4_cmd_wait(dev, in_param, out_param,
 774                                              out_is_imm, in_modifier,
 775                                              op_modifier, op, timeout);
 776                 else
 777                         return mlx4_cmd_poll(dev, in_param, out_param,
 778                                              out_is_imm, in_modifier,
 779                                              op_modifier, op, timeout);
 780         }
 781         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 782                               in_modifier, op_modifier, op, timeout);
 783 }
 784 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 785
 786
 787 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 788 {
 789         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 790                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 791 }
 792
 793 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 794                            int slave, u64 slave_addr,
 795                            int size, int is_read)
 796 {
 797         u64 in_param;
 798         u64 out_param;
 799
 800         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 801             (slave & ~0x7f) | (size & 0xff)) {
 802                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
 803                          slave_addr, master_addr, slave, size);
 804                 return -EINVAL;
 805         }
 806
 807         if (is_read) {
 808                 in_param = (u64) slave | slave_addr;
 809                 out_param = (u64) dev->caps.function | master_addr;
 810         } else {
 811                 in_param = (u64) dev->caps.function | master_addr;
 812                 out_param = (u64) slave | slave_addr;
 813         }
 814
 815         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 816                             MLX4_CMD_ACCESS_MEM,
 817                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 818 }
 819
 820 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 821                                struct mlx4_cmd_mailbox *inbox,
 822                                struct mlx4_cmd_mailbox *outbox)
 823 {
 824         struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 825         struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 826         int err;
 827         int i;
 828
 829         if (index & 0x1f)
 830                 return -EINVAL;
 831
 832         in_mad->attr_mod = cpu_to_be32(index / 32);
 833
 834         err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 835                            MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 836                            MLX4_CMD_NATIVE);
 837         if (err)
 838                 return err;
 839
 840         for (i = 0; i < 32; ++i)
 841                 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 842
 843         return err;
 844 }
 845
 846 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 847                                struct mlx4_cmd_mailbox *inbox,
 848                                struct mlx4_cmd_mailbox *outbox)
 849 {
 850         int i;
 851         int err;
 852
 853         for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 854                 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 855                 if (err)
 856                         return err;
 857         }
 858
 859         return 0;
 860 }
 861 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
 862 #define PORT_STATE_OFFSET 32
 863
 864 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 865 {
 866         if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 867                 return IB_PORT_ACTIVE;
 868         else
 869                 return IB_PORT_DOWN;
 870 }
 871
 872 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 873                                 struct mlx4_vhcr *vhcr,
 874                                 struct mlx4_cmd_mailbox *inbox,
 875                                 struct mlx4_cmd_mailbox *outbox,
 876                                 struct mlx4_cmd_info *cmd)
 877 {
 878         struct ib_smp *smp = inbox->buf;
 879         u32 index;
 880         u8 port;
 881         u8 opcode_modifier;
 882         u16 *table;
 883         int err;
 884         int vidx, pidx;
 885         int network_view;
 886         struct mlx4_priv *priv = mlx4_priv(dev);
 887         struct ib_smp *outsmp = outbox->buf;
 888         __be16 *outtab = (__be16 *)(outsmp->data);
 889         __be32 slave_cap_mask;
 890         __be64 slave_node_guid;
 891
 892         port = vhcr->in_modifier;
 893
 894         /* network-view bit is for driver use only, and should not be passed to FW */
 895         opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
 896         network_view = !!(vhcr->op_modifier & 0x8);
 897
 898         if (smp->base_version == 1 &&
 899             smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 900             smp->class_version == 1) {
 901                 /* host view is paravirtualized */
 902                 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
 903                         if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 904                                 index = be32_to_cpu(smp->attr_mod);
 905                                 if (port < 1 || port > dev->caps.num_ports)
 906                                         return -EINVAL;
 907                                 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
 908                                                 sizeof(*table) * 32, GFP_KERNEL);
 909
 910                                 if (!table)
 911                                         return -ENOMEM;
 912                                 /* need to get the full pkey table because the paravirtualized
 913                                  * pkeys may be scattered among several pkey blocks.
 914                                  */
 915                                 err = get_full_pkey_table(dev, port, table, inbox, outbox);
 916                                 if (!err) {
 917                                         for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 918                                                 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 919                                                 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 920                                         }
 921                                 }
 922                                 kfree(table);
 923                                 return err;
 924                         }
 925                         if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 926                                 /*get the slave specific caps:*/
 927                                 /*do the command */
 928                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 929                                             vhcr->in_modifier, opcode_modifier,
 930                                             vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 931                                 /* modify the response for slaves */
 932                                 if (!err && slave != mlx4_master_func_num(dev)) {
 933                                         u8 *state = outsmp->data + PORT_STATE_OFFSET;
 934
 935                                         *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 936                                         slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 937                                         memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 938                                 }
 939                                 return err;
 940                         }
 941                         if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 942                                 /* compute slave's gid block */
 943                                 smp->attr_mod = cpu_to_be32(slave / 8);
 944                                 /* execute cmd */
 945                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 946                                              vhcr->in_modifier, opcode_modifier,
 947                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 948                                 if (!err) {
 949                                         /* if needed, move slave gid to index 0 */
 950                                         if (slave % 8)
 951                                                 memcpy(outsmp->data,
 952                                                        outsmp->data + (slave % 8) * 8, 8);
 953                                         /* delete all other gids */
 954                                         memset(outsmp->data + 8, 0, 56);
 955                                 }
 956                                 return err;
 957                         }
 958                         if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
 959                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 960                                              vhcr->in_modifier, opcode_modifier,
 961                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 962                                 if (!err) {
 963                                         slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
 964                                         memcpy(outsmp->data + 12, &slave_node_guid, 8);
 965                                 }
 966                                 return err;
 967                         }
 968                 }
 969         }
 970
 971         /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
 972          * These are the MADs used by ib verbs (such as ib_query_gids).
 973          */
 974         if (slave != mlx4_master_func_num(dev) &&
 975             !mlx4_vf_smi_enabled(dev, slave, port)) {
 976                 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 977                       smp->method == IB_MGMT_METHOD_GET) || network_view) {
 978                         mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
 979                                  slave, smp->method, smp->mgmt_class,
 980                                  network_view ? "Network" : "Host",
 981                                  be16_to_cpu(smp->attr_id));
 982                         return -EPERM;
 983                 }
 984         }
 985
 986         return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 987                                     vhcr->in_modifier, opcode_modifier,
 988                                     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 989 }
 990
 991 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
 992                      struct mlx4_vhcr *vhcr,
 993                      struct mlx4_cmd_mailbox *inbox,
 994                      struct mlx4_cmd_mailbox *outbox,
 995                      struct mlx4_cmd_info *cmd)
 996 {
 997         return -EPERM;
 998 }
 999
1000 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1001                      struct mlx4_vhcr *vhcr,
1002                      struct mlx4_cmd_mailbox *inbox,
1003                      struct mlx4_cmd_mailbox *outbox,
1004                      struct mlx4_cmd_info *cmd)
1005 {
1006         u64 in_param;
1007         u64 out_param;
1008         int err;
1009
1010         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1011         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1012         if (cmd->encode_slave_id) {
1013                 in_param &= 0xffffffffffffff00ll;
1014                 in_param |= slave;
1015         }
1016
1017         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1018                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1019                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1020
1021         if (cmd->out_is_imm)
1022                 vhcr->out_param = out_param;
1023
1024         return err;
1025 }
1026
1027 static struct mlx4_cmd_info cmd_info[] = {
1028         {
1029                 .opcode = MLX4_CMD_QUERY_FW,
1030                 .has_inbox = false,
1031                 .has_outbox = true,
1032                 .out_is_imm = false,
1033                 .encode_slave_id = false,
1034                 .verify = NULL,
1035                 .wrapper = mlx4_QUERY_FW_wrapper
1036         },
1037         {
1038                 .opcode = MLX4_CMD_QUERY_HCA,
1039                 .has_inbox = false,
1040                 .has_outbox = true,
1041                 .out_is_imm = false,
1042                 .encode_slave_id = false,
1043                 .verify = NULL,
1044                 .wrapper = NULL
1045         },
1046         {
1047                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1048                 .has_inbox = false,
1049                 .has_outbox = true,
1050                 .out_is_imm = false,
1051                 .encode_slave_id = false,
1052                 .verify = NULL,
1053                 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
1054         },
1055         {
1056                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1057                 .has_inbox = false,
1058                 .has_outbox = true,
1059                 .out_is_imm = false,
1060                 .encode_slave_id = false,
1061                 .verify = NULL,
1062                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1063         },
1064         {
1065                 .opcode = MLX4_CMD_QUERY_ADAPTER,
1066                 .has_inbox = false,
1067                 .has_outbox = true,
1068                 .out_is_imm = false,
1069                 .encode_slave_id = false,
1070                 .verify = NULL,
1071                 .wrapper = NULL
1072         },
1073         {
1074                 .opcode = MLX4_CMD_INIT_PORT,
1075                 .has_inbox = false,
1076                 .has_outbox = false,
1077                 .out_is_imm = false,
1078                 .encode_slave_id = false,
1079                 .verify = NULL,
1080                 .wrapper = mlx4_INIT_PORT_wrapper
1081         },
1082         {
1083                 .opcode = MLX4_CMD_CLOSE_PORT,
1084                 .has_inbox = false,
1085                 .has_outbox = false,
1086                 .out_is_imm  = false,
1087                 .encode_slave_id = false,
1088                 .verify = NULL,
1089                 .wrapper = mlx4_CLOSE_PORT_wrapper
1090         },
1091         {
1092                 .opcode = MLX4_CMD_QUERY_PORT,
1093                 .has_inbox = false,
1094                 .has_outbox = true,
1095                 .out_is_imm = false,
1096                 .encode_slave_id = false,
1097                 .verify = NULL,
1098                 .wrapper = mlx4_QUERY_PORT_wrapper
1099         },
1100         {
1101                 .opcode = MLX4_CMD_SET_PORT,
1102                 .has_inbox = true,
1103                 .has_outbox = false,
1104                 .out_is_imm = false,
1105                 .encode_slave_id = false,
1106                 .verify = NULL,
1107                 .wrapper = mlx4_SET_PORT_wrapper
1108         },
1109         {
1110                 .opcode = MLX4_CMD_MAP_EQ,
1111                 .has_inbox = false,
1112                 .has_outbox = false,
1113                 .out_is_imm = false,
1114                 .encode_slave_id = false,
1115                 .verify = NULL,
1116                 .wrapper = mlx4_MAP_EQ_wrapper
1117         },
1118         {
1119                 .opcode = MLX4_CMD_SW2HW_EQ,
1120                 .has_inbox = true,
1121                 .has_outbox = false,
1122                 .out_is_imm = false,
1123                 .encode_slave_id = true,
1124                 .verify = NULL,
1125                 .wrapper = mlx4_SW2HW_EQ_wrapper
1126         },
1127         {
1128                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1129                 .has_inbox = false,
1130                 .has_outbox = false,
1131                 .out_is_imm = false,
1132                 .encode_slave_id = false,
1133                 .verify = NULL,
1134                 .wrapper = NULL
1135         },
1136         {
1137                 .opcode = MLX4_CMD_NOP,
1138                 .has_inbox = false,
1139                 .has_outbox = false,
1140                 .out_is_imm = false,
1141                 .encode_slave_id = false,
1142                 .verify = NULL,
1143                 .wrapper = NULL
1144         },
1145         {
1146                 .opcode = MLX4_CMD_CONFIG_DEV,
1147                 .has_inbox = false,
1148                 .has_outbox = true,
1149                 .out_is_imm = false,
1150                 .encode_slave_id = false,
1151                 .verify = NULL,
1152                 .wrapper = mlx4_CONFIG_DEV_wrapper
1153         },
1154         {
1155                 .opcode = MLX4_CMD_ALLOC_RES,
1156                 .has_inbox = false,
1157                 .has_outbox = false,
1158                 .out_is_imm = true,
1159                 .encode_slave_id = false,
1160                 .verify = NULL,
1161                 .wrapper = mlx4_ALLOC_RES_wrapper
1162         },
1163         {
1164                 .opcode = MLX4_CMD_FREE_RES,
1165                 .has_inbox = false,
1166                 .has_outbox = false,
1167                 .out_is_imm = false,
1168                 .encode_slave_id = false,
1169                 .verify = NULL,
1170                 .wrapper = mlx4_FREE_RES_wrapper
1171         },
1172         {
1173                 .opcode = MLX4_CMD_SW2HW_MPT,
1174                 .has_inbox = true,
1175                 .has_outbox = false,
1176                 .out_is_imm = false,
1177                 .encode_slave_id = true,
1178                 .verify = NULL,
1179                 .wrapper = mlx4_SW2HW_MPT_wrapper
1180         },
1181         {
1182                 .opcode = MLX4_CMD_QUERY_MPT,
1183                 .has_inbox = false,
1184                 .has_outbox = true,
1185                 .out_is_imm = false,
1186                 .encode_slave_id = false,
1187                 .verify = NULL,
1188                 .wrapper = mlx4_QUERY_MPT_wrapper
1189         },
1190         {
1191                 .opcode = MLX4_CMD_HW2SW_MPT,
1192                 .has_inbox = false,
1193                 .has_outbox = false,
1194                 .out_is_imm = false,
1195                 .encode_slave_id = false,
1196                 .verify = NULL,
1197                 .wrapper = mlx4_HW2SW_MPT_wrapper
1198         },
1199         {
1200                 .opcode = MLX4_CMD_READ_MTT,
1201                 .has_inbox = false,
1202                 .has_outbox = true,
1203                 .out_is_imm = false,
1204                 .encode_slave_id = false,
1205                 .verify = NULL,
1206                 .wrapper = NULL
1207         },
1208         {
1209                 .opcode = MLX4_CMD_WRITE_MTT,
1210                 .has_inbox = true,
1211                 .has_outbox = false,
1212                 .out_is_imm = false,
1213                 .encode_slave_id = false,
1214                 .verify = NULL,
1215                 .wrapper = mlx4_WRITE_MTT_wrapper
1216         },
1217         {
1218                 .opcode = MLX4_CMD_SYNC_TPT,
1219                 .has_inbox = true,
1220                 .has_outbox = false,
1221                 .out_is_imm = false,
1222                 .encode_slave_id = false,
1223                 .verify = NULL,
1224                 .wrapper = NULL
1225         },
1226         {
1227                 .opcode = MLX4_CMD_HW2SW_EQ,
1228                 .has_inbox = false,
1229                 .has_outbox = false,
1230                 .out_is_imm = false,
1231                 .encode_slave_id = true,
1232                 .verify = NULL,
1233                 .wrapper = mlx4_HW2SW_EQ_wrapper
1234         },
1235         {
1236                 .opcode = MLX4_CMD_QUERY_EQ,
1237                 .has_inbox = false,
1238                 .has_outbox = true,
1239                 .out_is_imm = false,
1240                 .encode_slave_id = true,
1241                 .verify = NULL,
1242                 .wrapper = mlx4_QUERY_EQ_wrapper
1243         },
1244         {
1245                 .opcode = MLX4_CMD_SW2HW_CQ,
1246                 .has_inbox = true,
1247                 .has_outbox = false,
1248                 .out_is_imm = false,
1249                 .encode_slave_id = true,
1250                 .verify = NULL,
1251                 .wrapper = mlx4_SW2HW_CQ_wrapper
1252         },
1253         {
1254                 .opcode = MLX4_CMD_HW2SW_CQ,
1255                 .has_inbox = false,
1256                 .has_outbox = false,
1257                 .out_is_imm = false,
1258                 .encode_slave_id = false,
1259                 .verify = NULL,
1260                 .wrapper = mlx4_HW2SW_CQ_wrapper
1261         },
1262         {
1263                 .opcode = MLX4_CMD_QUERY_CQ,
1264                 .has_inbox = false,
1265                 .has_outbox = true,
1266                 .out_is_imm = false,
1267                 .encode_slave_id = false,
1268                 .verify = NULL,
1269                 .wrapper = mlx4_QUERY_CQ_wrapper
1270         },
1271         {
1272                 .opcode = MLX4_CMD_MODIFY_CQ,
1273                 .has_inbox = true,
1274                 .has_outbox = false,
1275                 .out_is_imm = true,
1276                 .encode_slave_id = false,
1277                 .verify = NULL,
1278                 .wrapper = mlx4_MODIFY_CQ_wrapper
1279         },
1280         {
1281                 .opcode = MLX4_CMD_SW2HW_SRQ,
1282                 .has_inbox = true,
1283                 .has_outbox = false,
1284                 .out_is_imm = false,
1285                 .encode_slave_id = true,
1286                 .verify = NULL,
1287                 .wrapper = mlx4_SW2HW_SRQ_wrapper
1288         },
1289         {
1290                 .opcode = MLX4_CMD_HW2SW_SRQ,
1291                 .has_inbox = false,
1292                 .has_outbox = false,
1293                 .out_is_imm = false,
1294                 .encode_slave_id = false,
1295                 .verify = NULL,
1296                 .wrapper = mlx4_HW2SW_SRQ_wrapper
1297         },
1298         {
1299                 .opcode = MLX4_CMD_QUERY_SRQ,
1300                 .has_inbox = false,
1301                 .has_outbox = true,
1302                 .out_is_imm = false,
1303                 .encode_slave_id = false,
1304                 .verify = NULL,
1305                 .wrapper = mlx4_QUERY_SRQ_wrapper
1306         },
1307         {
1308                 .opcode = MLX4_CMD_ARM_SRQ,
1309                 .has_inbox = false,
1310                 .has_outbox = false,
1311                 .out_is_imm = false,
1312                 .encode_slave_id = false,
1313                 .verify = NULL,
1314                 .wrapper = mlx4_ARM_SRQ_wrapper
1315         },
1316         {
1317                 .opcode = MLX4_CMD_RST2INIT_QP,
1318                 .has_inbox = true,
1319                 .has_outbox = false,
1320                 .out_is_imm = false,
1321                 .encode_slave_id = true,
1322                 .verify = NULL,
1323                 .wrapper = mlx4_RST2INIT_QP_wrapper
1324         },
1325         {
1326                 .opcode = MLX4_CMD_INIT2INIT_QP,
1327                 .has_inbox = true,
1328                 .has_outbox = false,
1329                 .out_is_imm = false,
1330                 .encode_slave_id = false,
1331                 .verify = NULL,
1332                 .wrapper = mlx4_INIT2INIT_QP_wrapper
1333         },
1334         {
1335                 .opcode = MLX4_CMD_INIT2RTR_QP,
1336                 .has_inbox = true,
1337                 .has_outbox = false,
1338                 .out_is_imm = false,
1339                 .encode_slave_id = false,
1340                 .verify = NULL,
1341                 .wrapper = mlx4_INIT2RTR_QP_wrapper
1342         },
1343         {
1344                 .opcode = MLX4_CMD_RTR2RTS_QP,
1345                 .has_inbox = true,
1346                 .has_outbox = false,
1347                 .out_is_imm = false,
1348                 .encode_slave_id = false,
1349                 .verify = NULL,
1350                 .wrapper = mlx4_RTR2RTS_QP_wrapper
1351         },
1352         {
1353                 .opcode = MLX4_CMD_RTS2RTS_QP,
1354                 .has_inbox = true,
1355                 .has_outbox = false,
1356                 .out_is_imm = false,
1357                 .encode_slave_id = false,
1358                 .verify = NULL,
1359                 .wrapper = mlx4_RTS2RTS_QP_wrapper
1360         },
1361         {
1362                 .opcode = MLX4_CMD_SQERR2RTS_QP,
1363                 .has_inbox = true,
1364                 .has_outbox = false,
1365                 .out_is_imm = false,
1366                 .encode_slave_id = false,
1367                 .verify = NULL,
1368                 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1369         },
1370         {
1371                 .opcode = MLX4_CMD_2ERR_QP,
1372                 .has_inbox = false,
1373                 .has_outbox = false,
1374                 .out_is_imm = false,
1375                 .encode_slave_id = false,
1376                 .verify = NULL,
1377                 .wrapper = mlx4_GEN_QP_wrapper
1378         },
1379         {
1380                 .opcode = MLX4_CMD_RTS2SQD_QP,
1381                 .has_inbox = false,
1382                 .has_outbox = false,
1383                 .out_is_imm = false,
1384                 .encode_slave_id = false,
1385                 .verify = NULL,
1386                 .wrapper = mlx4_GEN_QP_wrapper
1387         },
1388         {
1389                 .opcode = MLX4_CMD_SQD2SQD_QP,
1390                 .has_inbox = true,
1391                 .has_outbox = false,
1392                 .out_is_imm = false,
1393                 .encode_slave_id = false,
1394                 .verify = NULL,
1395                 .wrapper = mlx4_SQD2SQD_QP_wrapper
1396         },
1397         {
1398                 .opcode = MLX4_CMD_SQD2RTS_QP,
1399                 .has_inbox = true,
1400                 .has_outbox = false,
1401                 .out_is_imm = false,
1402                 .encode_slave_id = false,
1403                 .verify = NULL,
1404                 .wrapper = mlx4_SQD2RTS_QP_wrapper
1405         },
1406         {
1407                 .opcode = MLX4_CMD_2RST_QP,
1408                 .has_inbox = false,
1409                 .has_outbox = false,
1410                 .out_is_imm = false,
1411                 .encode_slave_id = false,
1412                 .verify = NULL,
1413                 .wrapper = mlx4_2RST_QP_wrapper
1414         },
1415         {
1416                 .opcode = MLX4_CMD_QUERY_QP,
1417                 .has_inbox = false,
1418                 .has_outbox = true,
1419                 .out_is_imm = false,
1420                 .encode_slave_id = false,
1421                 .verify = NULL,
1422                 .wrapper = mlx4_GEN_QP_wrapper
1423         },
1424         {
1425                 .opcode = MLX4_CMD_SUSPEND_QP,
1426                 .has_inbox = false,
1427                 .has_outbox = false,
1428                 .out_is_imm = false,
1429                 .encode_slave_id = false,
1430                 .verify = NULL,
1431                 .wrapper = mlx4_GEN_QP_wrapper
1432         },
1433         {
1434                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1435                 .has_inbox = false,
1436                 .has_outbox = false,
1437                 .out_is_imm = false,
1438                 .encode_slave_id = false,
1439                 .verify = NULL,
1440                 .wrapper = mlx4_GEN_QP_wrapper
1441         },
1442         {
1443                 .opcode = MLX4_CMD_UPDATE_QP,
1444                 .has_inbox = true,
1445                 .has_outbox = false,
1446                 .out_is_imm = false,
1447                 .encode_slave_id = false,
1448                 .verify = NULL,
1449                 .wrapper = mlx4_UPDATE_QP_wrapper
1450         },
1451         {
1452                 .opcode = MLX4_CMD_GET_OP_REQ,
1453                 .has_inbox = false,
1454                 .has_outbox = false,
1455                 .out_is_imm = false,
1456                 .encode_slave_id = false,
1457                 .verify = NULL,
1458                 .wrapper = mlx4_CMD_EPERM_wrapper,
1459         },
1460         {
1461                 .opcode = MLX4_CMD_ALLOCATE_VPP,
1462                 .has_inbox = false,
1463                 .has_outbox = true,
1464                 .out_is_imm = false,
1465                 .encode_slave_id = false,
1466                 .verify = NULL,
1467                 .wrapper = mlx4_CMD_EPERM_wrapper,
1468         },
1469         {
1470                 .opcode = MLX4_CMD_SET_VPORT_QOS,
1471                 .has_inbox = false,
1472                 .has_outbox = true,
1473                 .out_is_imm = false,
1474                 .encode_slave_id = false,
1475                 .verify = NULL,
1476                 .wrapper = mlx4_CMD_EPERM_wrapper,
1477         },
1478         {
1479                 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1480                 .has_inbox = false,
1481                 .has_outbox = false,
1482                 .out_is_imm = false,
1483                 .encode_slave_id = false,
1484                 .verify = NULL, /* XXX verify: only demux can do this */
1485                 .wrapper = NULL
1486         },
1487         {
1488                 .opcode = MLX4_CMD_MAD_IFC,
1489                 .has_inbox = true,
1490                 .has_outbox = true,
1491                 .out_is_imm = false,
1492                 .encode_slave_id = false,
1493                 .verify = NULL,
1494                 .wrapper = mlx4_MAD_IFC_wrapper
1495         },
1496         {
1497                 .opcode = MLX4_CMD_MAD_DEMUX,
1498                 .has_inbox = false,
1499                 .has_outbox = false,
1500                 .out_is_imm = false,
1501                 .encode_slave_id = false,
1502                 .verify = NULL,
1503                 .wrapper = mlx4_CMD_EPERM_wrapper
1504         },
1505         {
1506                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1507                 .has_inbox = false,
1508                 .has_outbox = true,
1509                 .out_is_imm = false,
1510                 .encode_slave_id = false,
1511                 .verify = NULL,
1512                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1513         },
1514         {
1515                 .opcode = MLX4_CMD_ACCESS_REG,
1516                 .has_inbox = true,
1517                 .has_outbox = true,
1518                 .out_is_imm = false,
1519                 .encode_slave_id = false,
1520                 .verify = NULL,
1521                 .wrapper = mlx4_ACCESS_REG_wrapper,
1522         },
1523         {
1524                 .opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
1525                 .has_inbox = false,
1526                 .has_outbox = false,
1527                 .out_is_imm = false,
1528                 .encode_slave_id = false,
1529                 .verify = NULL,
1530                 .wrapper = mlx4_CMD_EPERM_wrapper,
1531         },
1532         /* Native multicast commands are not available for guests */
1533         {
1534                 .opcode = MLX4_CMD_QP_ATTACH,
1535                 .has_inbox = true,
1536                 .has_outbox = false,
1537                 .out_is_imm = false,
1538                 .encode_slave_id = false,
1539                 .verify = NULL,
1540                 .wrapper = mlx4_QP_ATTACH_wrapper
1541         },
1542         {
1543                 .opcode = MLX4_CMD_PROMISC,
1544                 .has_inbox = false,
1545                 .has_outbox = false,
1546                 .out_is_imm = false,
1547                 .encode_slave_id = false,
1548                 .verify = NULL,
1549                 .wrapper = mlx4_PROMISC_wrapper
1550         },
1551         /* Ethernet specific commands */
1552         {
1553                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1554                 .has_inbox = true,
1555                 .has_outbox = false,
1556                 .out_is_imm = false,
1557                 .encode_slave_id = false,
1558                 .verify = NULL,
1559                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1560         },
1561         {
1562                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1563                 .has_inbox = false,
1564                 .has_outbox = false,
1565                 .out_is_imm = false,
1566                 .encode_slave_id = false,
1567                 .verify = NULL,
1568                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1569         },
1570         {
1571                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1572                 .has_inbox = false,
1573                 .has_outbox = true,
1574                 .out_is_imm = false,
1575                 .encode_slave_id = false,
1576                 .verify = NULL,
1577                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1578         },
1579         {
1580                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1581                 .has_inbox = false,
1582                 .has_outbox = false,
1583                 .out_is_imm = false,
1584                 .encode_slave_id = false,
1585                 .verify = NULL,
1586                 .wrapper = NULL
1587         },
1588         /* flow steering commands */
1589         {
1590                 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1591                 .has_inbox = true,
1592                 .has_outbox = false,
1593                 .out_is_imm = true,
1594                 .encode_slave_id = false,
1595                 .verify = NULL,
1596                 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1597         },
1598         {
1599                 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1600                 .has_inbox = false,
1601                 .has_outbox = false,
1602                 .out_is_imm = false,
1603                 .encode_slave_id = false,
1604                 .verify = NULL,
1605                 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1606         },
1607         {
1608                 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1609                 .has_inbox = false,
1610                 .has_outbox = false,
1611                 .out_is_imm = false,
1612                 .encode_slave_id = false,
1613                 .verify = NULL,
1614                 .wrapper = mlx4_CMD_EPERM_wrapper
1615         },
1616         {
1617                 .opcode = MLX4_CMD_VIRT_PORT_MAP,
1618                 .has_inbox = false,
1619                 .has_outbox = false,
1620                 .out_is_imm = false,
1621                 .encode_slave_id = false,
1622                 .verify = NULL,
1623                 .wrapper = mlx4_CMD_EPERM_wrapper
1624         },
1625 };
1626
1627 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1628                                     struct mlx4_vhcr_cmd *in_vhcr)
1629 {
1630         struct mlx4_priv *priv = mlx4_priv(dev);
1631         struct mlx4_cmd_info *cmd = NULL;
1632         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1633         struct mlx4_vhcr *vhcr;
1634         struct mlx4_cmd_mailbox *inbox = NULL;
1635         struct mlx4_cmd_mailbox *outbox = NULL;
1636         u64 in_param;
1637         u64 out_param;
1638         int ret = 0;
1639         int i;
1640         int err = 0;
1641
1642         /* Create sw representation of Virtual HCR */
1643         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1644         if (!vhcr)
1645                 return -ENOMEM;
1646
1647         /* DMA in the vHCR */
1648         if (!in_vhcr) {
1649                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1650                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1651                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1652                                             MLX4_ACCESS_MEM_ALIGN), 1);
1653                 if (ret) {
1654                         if (!(dev->persist->state &
1655                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1656                                 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1657                                          __func__, ret);
1658                         kfree(vhcr);
1659                         return ret;
1660                 }
1661         }
1662
1663         /* Fill SW VHCR fields */
1664         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1665         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1666         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1667         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1668         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1669         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1670         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1671
1672         /* Lookup command */
1673         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1674                 if (vhcr->op == cmd_info[i].opcode) {
1675                         cmd = &cmd_info[i];
1676                         break;
1677                 }
1678         }
1679         if (!cmd) {
1680                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1681                          vhcr->op, slave);
1682                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1683                 goto out_status;
1684         }
1685
1686         /* Read inbox */
1687         if (cmd->has_inbox) {
1688                 vhcr->in_param &= INBOX_MASK;
1689                 inbox = mlx4_alloc_cmd_mailbox(dev);
1690                 if (IS_ERR(inbox)) {
1691                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1692                         inbox = NULL;
1693                         goto out_status;
1694                 }
1695
1696                 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1697                                       vhcr->in_param,
1698                                       MLX4_MAILBOX_SIZE, 1);
1699                 if (ret) {
1700                         if (!(dev->persist->state &
1701                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1702                                 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1703                                          __func__, cmd->opcode);
1704                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1705                         goto out_status;
1706                 }
1707         }
1708
1709         /* Apply permission and bound checks if applicable */
1710         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1711                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1712                           vhcr->op, slave, vhcr->in_modifier);
1713                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1714                 goto out_status;
1715         }
1716
1717         /* Allocate outbox */
1718         if (cmd->has_outbox) {
1719                 outbox = mlx4_alloc_cmd_mailbox(dev);
1720                 if (IS_ERR(outbox)) {
1721                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1722                         outbox = NULL;
1723                         goto out_status;
1724                 }
1725         }
1726
1727         /* Execute the command! */
1728         if (cmd->wrapper) {
1729                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1730                                    cmd);
1731                 if (cmd->out_is_imm)
1732                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1733         } else {
1734                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1735                         vhcr->in_param;
1736                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1737                         vhcr->out_param;
1738                 err = __mlx4_cmd(dev, in_param, &out_param,
1739                                  cmd->out_is_imm, vhcr->in_modifier,
1740                                  vhcr->op_modifier, vhcr->op,
1741                                  MLX4_CMD_TIME_CLASS_A,
1742                                  MLX4_CMD_NATIVE);
1743
1744                 if (cmd->out_is_imm) {
1745                         vhcr->out_param = out_param;
1746                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1747                 }
1748         }
1749
1750         if (err) {
1751                 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR))
1752                         mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1753                                   vhcr->op, slave, vhcr->errno, err);
1754                 vhcr_cmd->status = mlx4_errno_to_status(err);
1755                 goto out_status;
1756         }
1757
1758
1759         /* Write outbox if command completed successfully */
1760         if (cmd->has_outbox && !vhcr_cmd->status) {
1761                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1762                                       vhcr->out_param,
1763                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1764                 if (ret) {
1765                         /* If we failed to write back the outbox after the
1766                          *command was successfully executed, we must fail this
1767                          * slave, as it is now in undefined state */
1768                         if (!(dev->persist->state &
1769                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1770                                 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1771                         goto out;
1772                 }
1773         }
1774
1775 out_status:
1776         /* DMA back vhcr result */
1777         if (!in_vhcr) {
1778                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1779                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1780                                       ALIGN(sizeof(struct mlx4_vhcr),
1781                                             MLX4_ACCESS_MEM_ALIGN),
1782                                       MLX4_CMD_WRAPPED);
1783                 if (ret)
1784                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1785                                  __func__);
1786                 else if (vhcr->e_bit &&
1787                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1788                                 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1789                                           slave);
1790         }
1791
1792 out:
1793         kfree(vhcr);
1794         mlx4_free_cmd_mailbox(dev, inbox);
1795         mlx4_free_cmd_mailbox(dev, outbox);
1796         return ret;
1797 }
1798
1799 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1800                                             int slave, int port)
1801 {
1802         struct mlx4_vport_oper_state *vp_oper;
1803         struct mlx4_vport_state *vp_admin;
1804         struct mlx4_vf_immed_vlan_work *work;
1805         struct mlx4_dev *dev = &(priv->dev);
1806         int err;
1807         int admin_vlan_ix = NO_INDX;
1808
1809         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1810         vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1811
1812         if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1813             vp_oper->state.default_qos == vp_admin->default_qos &&
1814             vp_oper->state.link_state == vp_admin->link_state &&
1815             vp_oper->state.qos_vport == vp_admin->qos_vport)
1816                 return 0;
1817
1818         if (!(priv->mfunc.master.slave_state[slave].active &&
1819               dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1820                 /* even if the UPDATE_QP command isn't supported, we still want
1821                  * to set this VF link according to the admin directive
1822                  */
1823                 vp_oper->state.link_state = vp_admin->link_state;
1824                 return -1;
1825         }
1826
1827         mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1828                  slave, port);
1829         mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1830                  vp_admin->default_vlan, vp_admin->default_qos,
1831                  vp_admin->link_state);
1832
1833         work = kzalloc(sizeof(*work), GFP_KERNEL);
1834         if (!work)
1835                 return -ENOMEM;
1836
1837         if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1838                 if (MLX4_VGT != vp_admin->default_vlan) {
1839                         err = __mlx4_register_vlan(&priv->dev, port,
1840                                                    vp_admin->default_vlan,
1841                                                    &admin_vlan_ix);
1842                         if (err) {
1843                                 kfree(work);
1844                                 mlx4_warn(&priv->dev,
1845                                           "No vlan resources slave %d, port %d\n",
1846                                           slave, port);
1847                                 return err;
1848                         }
1849                 } else {
1850                         admin_vlan_ix = NO_INDX;
1851                 }
1852                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1853                 mlx4_dbg(&priv->dev,
1854                          "alloc vlan %d idx  %d slave %d port %d\n",
1855                          (int)(vp_admin->default_vlan),
1856                          admin_vlan_ix, slave, port);
1857         }
1858
1859         /* save original vlan ix and vlan id */
1860         work->orig_vlan_id = vp_oper->state.default_vlan;
1861         work->orig_vlan_ix = vp_oper->vlan_idx;
1862
1863         /* handle new qos */
1864         if (vp_oper->state.default_qos != vp_admin->default_qos)
1865                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1866
1867         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1868                 vp_oper->vlan_idx = admin_vlan_ix;
1869
1870         vp_oper->state.default_vlan = vp_admin->default_vlan;
1871         vp_oper->state.default_qos = vp_admin->default_qos;
1872         vp_oper->state.link_state = vp_admin->link_state;
1873         vp_oper->state.qos_vport = vp_admin->qos_vport;
1874
1875         if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1876                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1877
1878         /* iterate over QPs owned by this slave, using UPDATE_QP */
1879         work->port = port;
1880         work->slave = slave;
1881         work->qos = vp_oper->state.default_qos;
1882         work->qos_vport = vp_oper->state.qos_vport;
1883         work->vlan_id = vp_oper->state.default_vlan;
1884         work->vlan_ix = vp_oper->vlan_idx;
1885         work->priv = priv;
1886         INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1887         queue_work(priv->mfunc.master.comm_wq, &work->work);
1888
1889         return 0;
1890 }
1891
1892 static void mlx4_set_default_port_qos(struct mlx4_dev *dev, int port)
1893 {
1894         struct mlx4_qos_manager *port_qos_ctl;
1895         struct mlx4_priv *priv = mlx4_priv(dev);
1896
1897         port_qos_ctl = &priv->mfunc.master.qos_ctl[port];
1898         bitmap_zero(port_qos_ctl->priority_bm, MLX4_NUM_UP);
1899
1900         /* Enable only default prio at PF init routine */
1901         set_bit(MLX4_DEFAULT_QOS_PRIO, port_qos_ctl->priority_bm);
1902 }
1903
1904 static void mlx4_allocate_port_vpps(struct mlx4_dev *dev, int port)
1905 {
1906         int i;
1907         int err;
1908         int num_vfs;
1909         u16 availible_vpp;
1910         u8 vpp_param[MLX4_NUM_UP];
1911         struct mlx4_qos_manager *port_qos;
1912         struct mlx4_priv *priv = mlx4_priv(dev);
1913
1914         err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1915         if (err) {
1916                 mlx4_info(dev, "Failed query availible VPPs\n");
1917                 return;
1918         }
1919
1920         port_qos = &priv->mfunc.master.qos_ctl[port];
1921         num_vfs = (availible_vpp /
1922                    bitmap_weight(port_qos->priority_bm, MLX4_NUM_UP));
1923
1924         for (i = 0; i < MLX4_NUM_UP; i++) {
1925                 if (test_bit(i, port_qos->priority_bm))
1926                         vpp_param[i] = num_vfs;
1927         }
1928
1929         err = mlx4_ALLOCATE_VPP_set(dev, port, vpp_param);
1930         if (err) {
1931                 mlx4_info(dev, "Failed allocating VPPs\n");
1932                 return;
1933         }
1934
1935         /* Query actual allocated VPP, just to make sure */
1936         err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1937         if (err) {
1938                 mlx4_info(dev, "Failed query availible VPPs\n");
1939                 return;
1940         }
1941
1942         port_qos->num_of_qos_vfs = num_vfs;
1943         mlx4_dbg(dev, "Port %d Availible VPPs %d\n", port, availible_vpp);
1944
1945         for (i = 0; i < MLX4_NUM_UP; i++)
1946                 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1947                          vpp_param[i]);
1948 }
1949
1950 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1951 {
1952         int port, err;
1953         struct mlx4_vport_state *vp_admin;
1954         struct mlx4_vport_oper_state *vp_oper;
1955         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1956                         &priv->dev, slave);
1957         int min_port = find_first_bit(actv_ports.ports,
1958                                       priv->dev.caps.num_ports) + 1;
1959         int max_port = min_port - 1 +
1960                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1961
1962         for (port = min_port; port <= max_port; port++) {
1963                 if (!test_bit(port - 1, actv_ports.ports))
1964                         continue;
1965                 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1966                         priv->mfunc.master.vf_admin[slave].enable_smi[port];
1967                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1968                 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1969                 vp_oper->state = *vp_admin;
1970                 if (MLX4_VGT != vp_admin->default_vlan) {
1971                         err = __mlx4_register_vlan(&priv->dev, port,
1972                                                    vp_admin->default_vlan, &(vp_oper->vlan_idx));
1973                         if (err) {
1974                                 vp_oper->vlan_idx = NO_INDX;
1975                                 mlx4_warn(&priv->dev,
1976                                           "No vlan resources slave %d, port %d\n",
1977                                           slave, port);
1978                                 return err;
1979                         }
1980                         mlx4_dbg(&priv->dev, "alloc vlan %d idx  %d slave %d port %d\n",
1981                                  (int)(vp_oper->state.default_vlan),
1982                                  vp_oper->vlan_idx, slave, port);
1983                 }
1984                 if (vp_admin->spoofchk) {
1985                         vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1986                                                                port,
1987                                                                vp_admin->mac);
1988                         if (0 > vp_oper->mac_idx) {
1989                                 err = vp_oper->mac_idx;
1990                                 vp_oper->mac_idx = NO_INDX;
1991                                 mlx4_warn(&priv->dev,
1992                                           "No mac resources slave %d, port %d\n",
1993                                           slave, port);
1994                                 return err;
1995                         }
1996                         mlx4_dbg(&priv->dev, "alloc mac %llx idx  %d slave %d port %d\n",
1997                                  vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1998                 }
1999         }
2000         return 0;
2001 }
2002
2003 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2004 {
2005         int port;
2006         struct mlx4_vport_oper_state *vp_oper;
2007         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2008                         &priv->dev, slave);
2009         int min_port = find_first_bit(actv_ports.ports,
2010                                       priv->dev.caps.num_ports) + 1;
2011         int max_port = min_port - 1 +
2012                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2013
2014
2015         for (port = min_port; port <= max_port; port++) {
2016                 if (!test_bit(port - 1, actv_ports.ports))
2017                         continue;
2018                 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2019                         MLX4_VF_SMI_DISABLED;
2020                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2021                 if (NO_INDX != vp_oper->vlan_idx) {
2022                         __mlx4_unregister_vlan(&priv->dev,
2023                                                port, vp_oper->state.default_vlan);
2024                         vp_oper->vlan_idx = NO_INDX;
2025                 }
2026                 if (NO_INDX != vp_oper->mac_idx) {
2027                         __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
2028                         vp_oper->mac_idx = NO_INDX;
2029                 }
2030         }
2031         return;
2032 }
2033
2034 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
2035                                u16 param, u8 toggle)
2036 {
2037         struct mlx4_priv *priv = mlx4_priv(dev);
2038         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2039         u32 reply;
2040         u8 is_going_down = 0;
2041         int i;
2042         unsigned long flags;
2043
2044         slave_state[slave].comm_toggle ^= 1;
2045         reply = (u32) slave_state[slave].comm_toggle << 31;
2046         if (toggle != slave_state[slave].comm_toggle) {
2047                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
2048                           toggle, slave);
2049                 goto reset_slave;
2050         }
2051         if (cmd == MLX4_COMM_CMD_RESET) {
2052                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
2053                 slave_state[slave].active = false;
2054                 slave_state[slave].old_vlan_api = false;
2055                 mlx4_master_deactivate_admin_state(priv, slave);
2056                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
2057                                 slave_state[slave].event_eq[i].eqn = -1;
2058                                 slave_state[slave].event_eq[i].token = 0;
2059                 }
2060                 /*check if we are in the middle of FLR process,
2061                 if so return "retry" status to the slave*/
2062                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
2063                         goto inform_slave_state;
2064
2065                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
2066
2067                 /* write the version in the event field */
2068                 reply |= mlx4_comm_get_version();
2069
2070                 goto reset_slave;
2071         }
2072         /*command from slave in the middle of FLR*/
2073         if (cmd != MLX4_COMM_CMD_RESET &&
2074             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
2075                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
2076                           slave, cmd);
2077                 return;
2078         }
2079
2080         switch (cmd) {
2081         case MLX4_COMM_CMD_VHCR0:
2082                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
2083                         goto reset_slave;
2084                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
2085                 priv->mfunc.master.slave_state[slave].cookie = 0;
2086                 break;
2087         case MLX4_COMM_CMD_VHCR1:
2088                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
2089                         goto reset_slave;
2090                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
2091                 break;
2092         case MLX4_COMM_CMD_VHCR2:
2093                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
2094                         goto reset_slave;
2095                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
2096                 break;
2097         case MLX4_COMM_CMD_VHCR_EN:
2098                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
2099                         goto reset_slave;
2100                 slave_state[slave].vhcr_dma |= param;
2101                 if (mlx4_master_activate_admin_state(priv, slave))
2102                                 goto reset_slave;
2103                 slave_state[slave].active = true;
2104                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
2105                 break;
2106         case MLX4_COMM_CMD_VHCR_POST:
2107                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
2108                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2109                         mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2110                                   slave, cmd, slave_state[slave].last_cmd);
2111                         goto reset_slave;
2112                 }
2113
2114                 mutex_lock(&priv->cmd.slave_cmd_mutex);
2115                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
2116                         mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2117                                  slave);
2118                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2119                         goto reset_slave;
2120                 }
2121                 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2122                 break;
2123         default:
2124                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2125                 goto reset_slave;
2126         }
2127         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2128         if (!slave_state[slave].is_slave_going_down)
2129                 slave_state[slave].last_cmd = cmd;
2130         else
2131                 is_going_down = 1;
2132         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2133         if (is_going_down) {
2134                 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
2135                           cmd, slave);
2136                 return;
2137         }
2138         __raw_writel((__force u32) cpu_to_be32(reply),
2139                      &priv->mfunc.comm[slave].slave_read);
2140         mmiowb();
2141
2142         return;
2143
2144 reset_slave:
2145         /* cleanup any slave resources */
2146         if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2147                 mlx4_delete_all_resources_for_slave(dev, slave);
2148
2149         if (cmd != MLX4_COMM_CMD_RESET) {
2150                 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2151                           slave, cmd);
2152                 /* Turn on internal error letting slave reset itself immeditaly,
2153                  * otherwise it might take till timeout on command is passed
2154                  */
2155                 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2156         }
2157
2158         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2159         if (!slave_state[slave].is_slave_going_down)
2160                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
2161         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2162         /*with slave in the middle of flr, no need to clean resources again.*/
2163 inform_slave_state:
2164         memset(&slave_state[slave].event_eq, 0,
2165                sizeof(struct mlx4_slave_event_eq_info));
2166         __raw_writel((__force u32) cpu_to_be32(reply),
2167                      &priv->mfunc.comm[slave].slave_read);
2168         wmb();
2169 }
2170
2171 /* master command processing */
2172 void mlx4_master_comm_channel(struct work_struct *work)
2173 {
2174         struct mlx4_mfunc_master_ctx *master =
2175                 container_of(work,
2176                              struct mlx4_mfunc_master_ctx,
2177                              comm_work);
2178         struct mlx4_mfunc *mfunc =
2179                 container_of(master, struct mlx4_mfunc, master);
2180         struct mlx4_priv *priv =
2181                 container_of(mfunc, struct mlx4_priv, mfunc);
2182         struct mlx4_dev *dev = &priv->dev;
2183         __be32 *bit_vec;
2184         u32 comm_cmd;
2185         u32 vec;
2186         int i, j, slave;
2187         int toggle;
2188         int served = 0;
2189         int reported = 0;
2190         u32 slt;
2191
2192         bit_vec = master->comm_arm_bit_vector;
2193         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
2194                 vec = be32_to_cpu(bit_vec[i]);
2195                 for (j = 0; j < 32; j++) {
2196                         if (!(vec & (1 << j)))
2197                                 continue;
2198                         ++reported;
2199                         slave = (i * 32) + j;
2200                         comm_cmd = swab32(readl(
2201                                           &mfunc->comm[slave].slave_write));
2202                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
2203                                      >> 31;
2204                         toggle = comm_cmd >> 31;
2205                         if (toggle != slt) {
2206                                 if (master->slave_state[slave].comm_toggle
2207                                     != slt) {
2208                                         pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2209                                                 slave, slt,
2210                                                 master->slave_state[slave].comm_toggle);
2211                                         master->slave_state[slave].comm_toggle =
2212                                                 slt;
2213                                 }
2214                                 mlx4_master_do_cmd(dev, slave,
2215                                                    comm_cmd >> 16 & 0xff,
2216                                                    comm_cmd & 0xffff, toggle);
2217                                 ++served;
2218                         }
2219                 }
2220         }
2221
2222         if (reported && reported != served)
2223                 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
2224                           reported, served);
2225
2226         if (mlx4_ARM_COMM_CHANNEL(dev))
2227                 mlx4_warn(dev, "Failed to arm comm channel events\n");
2228 }
2229
2230 static int sync_toggles(struct mlx4_dev *dev)
2231 {
2232         struct mlx4_priv *priv = mlx4_priv(dev);
2233         u32 wr_toggle;
2234         u32 rd_toggle;
2235         unsigned long end;
2236
2237         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2238         if (wr_toggle == 0xffffffff)
2239                 end = jiffies + msecs_to_jiffies(30000);
2240         else
2241                 end = jiffies + msecs_to_jiffies(5000);
2242
2243         while (time_before(jiffies, end)) {
2244                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2245                 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2246                         /* PCI might be offline */
2247                         msleep(100);
2248                         wr_toggle = swab32(readl(&priv->mfunc.comm->
2249                                            slave_write));
2250                         continue;
2251                 }
2252
2253                 if (rd_toggle >> 31 == wr_toggle >> 31) {
2254                         priv->cmd.comm_toggle = rd_toggle >> 31;
2255                         return 0;
2256                 }
2257
2258                 cond_resched();
2259         }
2260
2261         /*
2262          * we could reach here if for example the previous VM using this
2263          * function misbehaved and left the channel with unsynced state. We
2264          * should fix this here and give this VM a chance to use a properly
2265          * synced channel
2266          */
2267         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2268         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2269         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2270         priv->cmd.comm_toggle = 0;
2271
2272         return 0;
2273 }
2274
2275 int mlx4_multi_func_init(struct mlx4_dev *dev)
2276 {
2277         struct mlx4_priv *priv = mlx4_priv(dev);
2278         struct mlx4_slave_state *s_state;
2279         int i, j, err, port;
2280
2281         if (mlx4_is_master(dev))
2282                 priv->mfunc.comm =
2283                 ioremap(pci_resource_start(dev->persist->pdev,
2284                                            priv->fw.comm_bar) +
2285                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2286         else
2287                 priv->mfunc.comm =
2288                 ioremap(pci_resource_start(dev->persist->pdev, 2) +
2289                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2290         if (!priv->mfunc.comm) {
2291                 mlx4_err(dev, "Couldn't map communication vector\n");
2292                 goto err_vhcr;
2293         }
2294
2295         if (mlx4_is_master(dev)) {
2296                 struct mlx4_vf_oper_state *vf_oper;
2297                 struct mlx4_vf_admin_state *vf_admin;
2298
2299                 priv->mfunc.master.slave_state =
2300                         kzalloc(dev->num_slaves *
2301                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
2302                 if (!priv->mfunc.master.slave_state)
2303                         goto err_comm;
2304
2305                 priv->mfunc.master.vf_admin =
2306                         kzalloc(dev->num_slaves *
2307                                 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2308                 if (!priv->mfunc.master.vf_admin)
2309                         goto err_comm_admin;
2310
2311                 priv->mfunc.master.vf_oper =
2312                         kzalloc(dev->num_slaves *
2313                                 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2314                 if (!priv->mfunc.master.vf_oper)
2315                         goto err_comm_oper;
2316
2317                 for (i = 0; i < dev->num_slaves; ++i) {
2318                         vf_admin = &priv->mfunc.master.vf_admin[i];
2319                         vf_oper = &priv->mfunc.master.vf_oper[i];
2320                         s_state = &priv->mfunc.master.slave_state[i];
2321                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
2322                         mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]);
2323                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2324                                 s_state->event_eq[j].eqn = -1;
2325                         __raw_writel((__force u32) 0,
2326                                      &priv->mfunc.comm[i].slave_write);
2327                         __raw_writel((__force u32) 0,
2328                                      &priv->mfunc.comm[i].slave_read);
2329                         mmiowb();
2330                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2331                                 struct mlx4_vport_state *admin_vport;
2332                                 struct mlx4_vport_state *oper_vport;
2333
2334                                 s_state->vlan_filter[port] =
2335                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
2336                                                 GFP_KERNEL);
2337                                 if (!s_state->vlan_filter[port]) {
2338                                         if (--port)
2339                                                 kfree(s_state->vlan_filter[port]);
2340                                         goto err_slaves;
2341                                 }
2342
2343                                 admin_vport = &vf_admin->vport[port];
2344                                 oper_vport = &vf_oper->vport[port].state;
2345                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2346                                 admin_vport->default_vlan = MLX4_VGT;
2347                                 oper_vport->default_vlan = MLX4_VGT;
2348                                 admin_vport->qos_vport =
2349                                                 MLX4_VPP_DEFAULT_VPORT;
2350                                 oper_vport->qos_vport = MLX4_VPP_DEFAULT_VPORT;
2351                                 vf_oper->vport[port].vlan_idx = NO_INDX;
2352                                 vf_oper->vport[port].mac_idx = NO_INDX;
2353                         }
2354                         spin_lock_init(&s_state->lock);
2355                 }
2356
2357                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP) {
2358                         for (port = 1; port <= dev->caps.num_ports; port++) {
2359                                 if (mlx4_is_eth(dev, port)) {
2360                                         mlx4_set_default_port_qos(dev, port);
2361                                         mlx4_allocate_port_vpps(dev, port);
2362                                 }
2363                         }
2364                 }
2365
2366                 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
2367                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2368                 INIT_WORK(&priv->mfunc.master.comm_work,
2369                           mlx4_master_comm_channel);
2370                 INIT_WORK(&priv->mfunc.master.slave_event_work,
2371                           mlx4_gen_slave_eqe);
2372                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2373                           mlx4_master_handle_slave_flr);
2374                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2375                 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2376                 priv->mfunc.master.comm_wq =
2377                         create_singlethread_workqueue("mlx4_comm");
2378                 if (!priv->mfunc.master.comm_wq)
2379                         goto err_slaves;
2380
2381                 if (mlx4_init_resource_tracker(dev))
2382                         goto err_thread;
2383
2384         } else {
2385                 err = sync_toggles(dev);
2386                 if (err) {
2387                         mlx4_err(dev, "Couldn't sync toggles\n");
2388                         goto err_comm;
2389                 }
2390         }
2391         return 0;
2392
2393 err_thread:
2394         flush_workqueue(priv->mfunc.master.comm_wq);
2395         destroy_workqueue(priv->mfunc.master.comm_wq);
2396 err_slaves:
2397         while (--i) {
2398                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2399                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2400         }
2401         kfree(priv->mfunc.master.vf_oper);
2402 err_comm_oper:
2403         kfree(priv->mfunc.master.vf_admin);
2404 err_comm_admin:
2405         kfree(priv->mfunc.master.slave_state);
2406 err_comm:
2407         iounmap(priv->mfunc.comm);
2408 err_vhcr:
2409         dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2410                           priv->mfunc.vhcr,
2411                           priv->mfunc.vhcr_dma);
2412         priv->mfunc.vhcr = NULL;
2413         return -ENOMEM;
2414 }
2415
2416 int mlx4_cmd_init(struct mlx4_dev *dev)
2417 {
2418         struct mlx4_priv *priv = mlx4_priv(dev);
2419         int flags = 0;
2420
2421         if (!priv->cmd.initialized) {
2422                 mutex_init(&priv->cmd.slave_cmd_mutex);
2423                 sema_init(&priv->cmd.poll_sem, 1);
2424                 priv->cmd.use_events = 0;
2425                 priv->cmd.toggle     = 1;
2426                 priv->cmd.initialized = 1;
2427                 flags |= MLX4_CMD_CLEANUP_STRUCT;
2428         }
2429
2430         if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
2431                 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2432                                         0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
2433                 if (!priv->cmd.hcr) {
2434                         mlx4_err(dev, "Couldn't map command register\n");
2435                         goto err;
2436                 }
2437                 flags |= MLX4_CMD_CLEANUP_HCR;
2438         }
2439
2440         if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
2441                 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2442                                                       PAGE_SIZE,
2443                                                       &priv->mfunc.vhcr_dma,
2444                                                       GFP_KERNEL);
2445                 if (!priv->mfunc.vhcr)
2446                         goto err;
2447
2448                 flags |= MLX4_CMD_CLEANUP_VHCR;
2449         }
2450
2451         if (!priv->cmd.pool) {
2452                 priv->cmd.pool = pci_pool_create("mlx4_cmd",
2453                                                  dev->persist->pdev,
2454                                                  MLX4_MAILBOX_SIZE,
2455                                                  MLX4_MAILBOX_SIZE, 0);
2456                 if (!priv->cmd.pool)
2457                         goto err;
2458
2459                 flags |= MLX4_CMD_CLEANUP_POOL;
2460         }
2461
2462         return 0;
2463
2464 err:
2465         mlx4_cmd_cleanup(dev, flags);
2466         return -ENOMEM;
2467 }
2468
2469 void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2470 {
2471         struct mlx4_priv *priv = mlx4_priv(dev);
2472         int slave;
2473         u32 slave_read;
2474
2475         /* Report an internal error event to all
2476          * communication channels.
2477          */
2478         for (slave = 0; slave < dev->num_slaves; slave++) {
2479                 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2480                 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2481                 __raw_writel((__force u32)cpu_to_be32(slave_read),
2482                              &priv->mfunc.comm[slave].slave_read);
2483                 /* Make sure that our comm channel write doesn't
2484                  * get mixed in with writes from another CPU.
2485                  */
2486                 mmiowb();
2487         }
2488 }
2489
2490 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2491 {
2492         struct mlx4_priv *priv = mlx4_priv(dev);
2493         int i, port;
2494
2495         if (mlx4_is_master(dev)) {
2496                 flush_workqueue(priv->mfunc.master.comm_wq);
2497                 destroy_workqueue(priv->mfunc.master.comm_wq);
2498                 for (i = 0; i < dev->num_slaves; i++) {
2499                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
2500                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2501                 }
2502                 kfree(priv->mfunc.master.slave_state);
2503                 kfree(priv->mfunc.master.vf_admin);
2504                 kfree(priv->mfunc.master.vf_oper);
2505                 dev->num_slaves = 0;
2506         }
2507
2508         iounmap(priv->mfunc.comm);
2509 }
2510
2511 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
2512 {
2513         struct mlx4_priv *priv = mlx4_priv(dev);
2514
2515         if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2516                 pci_pool_destroy(priv->cmd.pool);
2517                 priv->cmd.pool = NULL;
2518         }
2519
2520         if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2521             (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
2522                 iounmap(priv->cmd.hcr);
2523                 priv->cmd.hcr = NULL;
2524         }
2525         if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2526             (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
2527                 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2528                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2529                 priv->mfunc.vhcr = NULL;
2530         }
2531         if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2532                 priv->cmd.initialized = 0;
2533 }
2534
2535 /*
2536  * Switch to using events to issue FW commands (can only be called
2537  * after event queue for command events has been initialized).
2538  */
2539 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2540 {
2541         struct mlx4_priv *priv = mlx4_priv(dev);
2542         int i;
2543         int err = 0;
2544
2545         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2546                                    sizeof (struct mlx4_cmd_context),
2547                                    GFP_KERNEL);
2548         if (!priv->cmd.context)
2549                 return -ENOMEM;
2550
2551         for (i = 0; i < priv->cmd.max_cmds; ++i) {
2552                 priv->cmd.context[i].token = i;
2553                 priv->cmd.context[i].next  = i + 1;
2554                 /* To support fatal error flow, initialize all
2555                  * cmd contexts to allow simulating completions
2556                  * with complete() at any time.
2557                  */
2558                 init_completion(&priv->cmd.context[i].done);
2559         }
2560
2561         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2562         priv->cmd.free_head = 0;
2563
2564         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2565         spin_lock_init(&priv->cmd.context_lock);
2566
2567         for (priv->cmd.token_mask = 1;
2568              priv->cmd.token_mask < priv->cmd.max_cmds;
2569              priv->cmd.token_mask <<= 1)
2570                 ; /* nothing */
2571         --priv->cmd.token_mask;
2572
2573         down(&priv->cmd.poll_sem);
2574         priv->cmd.use_events = 1;
2575
2576         return err;
2577 }
2578
2579 /*
2580  * Switch back to polling (used when shutting down the device)
2581  */
2582 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2583 {
2584         struct mlx4_priv *priv = mlx4_priv(dev);
2585         int i;
2586
2587         priv->cmd.use_events = 0;
2588
2589         for (i = 0; i < priv->cmd.max_cmds; ++i)
2590                 down(&priv->cmd.event_sem);
2591
2592         kfree(priv->cmd.context);
2593
2594         up(&priv->cmd.poll_sem);
2595 }
2596
2597 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2598 {
2599         struct mlx4_cmd_mailbox *mailbox;
2600
2601         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2602         if (!mailbox)
2603                 return ERR_PTR(-ENOMEM);
2604
2605         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2606                                       &mailbox->dma);
2607         if (!mailbox->buf) {
2608                 kfree(mailbox);
2609                 return ERR_PTR(-ENOMEM);
2610         }
2611
2612         memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2613
2614         return mailbox;
2615 }
2616 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2617
2618 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2619                            struct mlx4_cmd_mailbox *mailbox)
2620 {
2621         if (!mailbox)
2622                 return;
2623
2624         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2625         kfree(mailbox);
2626 }
2627 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2628
2629 u32 mlx4_comm_get_version(void)
2630 {
2631          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2632 }
2633
2634 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2635 {
2636         if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2637                 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2638                          vf, dev->persist->num_vfs);
2639                 return -EINVAL;
2640         }
2641
2642         return vf+1;
2643 }
2644
2645 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2646 {
2647         if (slave < 1 || slave > dev->persist->num_vfs) {
2648                 mlx4_err(dev,
2649                          "Bad slave number:%d (number of activated slaves: %lu)\n",
2650                          slave, dev->num_slaves);
2651                 return -EINVAL;
2652         }
2653         return slave - 1;
2654 }
2655
2656 void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2657 {
2658         struct mlx4_priv *priv = mlx4_priv(dev);
2659         struct mlx4_cmd_context *context;
2660         int i;
2661
2662         spin_lock(&priv->cmd.context_lock);
2663         if (priv->cmd.context) {
2664                 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2665                         context = &priv->cmd.context[i];
2666                         context->fw_status = CMD_STAT_INTERNAL_ERR;
2667                         context->result    =
2668                                 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2669                         complete(&context->done);
2670                 }
2671         }
2672         spin_unlock(&priv->cmd.context_lock);
2673 }
2674
2675 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2676 {
2677         struct mlx4_active_ports actv_ports;
2678         int vf;
2679
2680         bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2681
2682         if (slave == 0) {
2683                 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2684                 return actv_ports;
2685         }
2686
2687         vf = mlx4_get_vf_indx(dev, slave);
2688         if (vf < 0)
2689                 return actv_ports;
2690
2691         bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2692                    min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2693                    dev->caps.num_ports));
2694
2695         return actv_ports;
2696 }
2697 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2698
2699 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2700 {
2701         unsigned n;
2702         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2703         unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2704
2705         if (port <= 0 || port > m)
2706                 return -EINVAL;
2707
2708         n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2709         if (port <= n)
2710                 port = n + 1;
2711
2712         return port;
2713 }
2714 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2715
2716 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2717 {
2718         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2719         if (test_bit(port - 1, actv_ports.ports))
2720                 return port -
2721                         find_first_bit(actv_ports.ports, dev->caps.num_ports);
2722
2723         return -1;
2724 }
2725 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2726
2727 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2728                                                    int port)
2729 {
2730         unsigned i;
2731         struct mlx4_slaves_pport slaves_pport;
2732
2733         bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2734
2735         if (port <= 0 || port > dev->caps.num_ports)
2736                 return slaves_pport;
2737
2738         for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2739                 struct mlx4_active_ports actv_ports =
2740                         mlx4_get_active_ports(dev, i);
2741                 if (test_bit(port - 1, actv_ports.ports))
2742                         set_bit(i, slaves_pport.slaves);
2743         }
2744
2745         return slaves_pport;
2746 }
2747 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2748
2749 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2750                 struct mlx4_dev *dev,
2751                 const struct mlx4_active_ports *crit_ports)
2752 {
2753         unsigned i;
2754         struct mlx4_slaves_pport slaves_pport;
2755
2756         bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2757
2758         for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2759                 struct mlx4_active_ports actv_ports =
2760                         mlx4_get_active_ports(dev, i);
2761                 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2762                                  dev->caps.num_ports))
2763                         set_bit(i, slaves_pport.slaves);
2764         }
2765
2766         return slaves_pport;
2767 }
2768 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2769
2770 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2771 {
2772         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2773         int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2774                         + 1;
2775         int max_port = min_port +
2776                 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2777
2778         if (port < min_port)
2779                 port = min_port;
2780         else if (port >= max_port)
2781                 port = max_port - 1;
2782
2783         return port;
2784 }
2785
2786 static int mlx4_set_vport_qos(struct mlx4_priv *priv, int slave, int port,
2787                               int max_tx_rate)
2788 {
2789         int i;
2790         int err;
2791         struct mlx4_qos_manager *port_qos;
2792         struct mlx4_dev *dev = &priv->dev;
2793         struct mlx4_vport_qos_param vpp_qos[MLX4_NUM_UP];
2794
2795         port_qos = &priv->mfunc.master.qos_ctl[port];
2796         memset(vpp_qos, 0, sizeof(struct mlx4_vport_qos_param) * MLX4_NUM_UP);
2797
2798         if (slave > port_qos->num_of_qos_vfs) {
2799                 mlx4_info(dev, "No availible VPP resources for this VF\n");
2800                 return -EINVAL;
2801         }
2802
2803         /* Query for default QoS values from Vport 0 is needed */
2804         err = mlx4_SET_VPORT_QOS_get(dev, port, 0, vpp_qos);
2805         if (err) {
2806                 mlx4_info(dev, "Failed to query Vport 0 QoS values\n");
2807                 return err;
2808         }
2809
2810         for (i = 0; i < MLX4_NUM_UP; i++) {
2811                 if (test_bit(i, port_qos->priority_bm) && max_tx_rate) {
2812                         vpp_qos[i].max_avg_bw = max_tx_rate;
2813                         vpp_qos[i].enable = 1;
2814                 } else {
2815                         /* if user supplied tx_rate == 0, meaning no rate limit
2816                          * configuration is required. so we are leaving the
2817                          * value of max_avg_bw as queried from Vport 0.
2818                          */
2819                         vpp_qos[i].enable = 0;
2820                 }
2821         }
2822
2823         err = mlx4_SET_VPORT_QOS_set(dev, port, slave, vpp_qos);
2824         if (err) {
2825                 mlx4_info(dev, "Failed to set Vport %d QoS values\n", slave);
2826                 return err;
2827         }
2828
2829         return 0;
2830 }
2831
2832 static bool mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev *dev, int port,
2833                                         struct mlx4_vport_state *vf_admin)
2834 {
2835         struct mlx4_qos_manager *info;
2836         struct mlx4_priv *priv = mlx4_priv(dev);
2837
2838         if (!mlx4_is_master(dev) ||
2839             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2840                 return false;
2841
2842         info = &priv->mfunc.master.qos_ctl[port];
2843
2844         if (vf_admin->default_vlan != MLX4_VGT &&
2845             test_bit(vf_admin->default_qos, info->priority_bm))
2846                 return true;
2847
2848         return false;
2849 }
2850
2851 static bool mlx4_valid_vf_state_change(struct mlx4_dev *dev, int port,
2852                                        struct mlx4_vport_state *vf_admin,
2853                                        int vlan, int qos)
2854 {
2855         struct mlx4_vport_state dummy_admin = {0};
2856
2857         if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) ||
2858             !vf_admin->tx_rate)
2859                 return true;
2860
2861         dummy_admin.default_qos = qos;
2862         dummy_admin.default_vlan = vlan;
2863
2864         /* VF wants to move to other VST state which is valid with current
2865          * rate limit. Either differnt default vlan in VST or other
2866          * supported QoS priority. Otherwise we don't allow this change when
2867          * the TX rate is still configured.
2868          */
2869         if (mlx4_is_vf_vst_and_prio_qos(dev, port, &dummy_admin))
2870                 return true;
2871
2872         mlx4_info(dev, "Cannot change VF state to %s while rate is set\n",
2873                   (vlan == MLX4_VGT) ? "VGT" : "VST");
2874
2875         if (vlan != MLX4_VGT)
2876                 mlx4_info(dev, "VST priority %d not supported for QoS\n", qos);
2877
2878         mlx4_info(dev, "Please set rate to 0 prior to this VF state change\n");
2879
2880         return false;
2881 }
2882
2883 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2884 {
2885         struct mlx4_priv *priv = mlx4_priv(dev);
2886         struct mlx4_vport_state *s_info;
2887         int slave;
2888
2889         if (!mlx4_is_master(dev))
2890                 return -EPROTONOSUPPORT;
2891
2892         slave = mlx4_get_slave_indx(dev, vf);
2893         if (slave < 0)
2894                 return -EINVAL;
2895
2896         port = mlx4_slaves_closest_port(dev, slave, port);
2897         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2898         s_info->mac = mac;
2899         mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2900                   vf, port, s_info->mac);
2901         return 0;
2902 }
2903 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2904
2905
2906 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2907 {
2908         struct mlx4_priv *priv = mlx4_priv(dev);
2909         struct mlx4_vport_state *vf_admin;
2910         int slave;
2911
2912         if ((!mlx4_is_master(dev)) ||
2913             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2914                 return -EPROTONOSUPPORT;
2915
2916         if ((vlan > 4095) || (qos > 7))
2917                 return -EINVAL;
2918
2919         slave = mlx4_get_slave_indx(dev, vf);
2920         if (slave < 0)
2921                 return -EINVAL;
2922
2923         port = mlx4_slaves_closest_port(dev, slave, port);
2924         vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2925
2926         if (!mlx4_valid_vf_state_change(dev, port, vf_admin, vlan, qos))
2927                 return -EPERM;
2928
2929         if ((0 == vlan) && (0 == qos))
2930                 vf_admin->default_vlan = MLX4_VGT;
2931         else
2932                 vf_admin->default_vlan = vlan;
2933         vf_admin->default_qos = qos;
2934
2935         /* If rate was configured prior to VST, we saved the configured rate
2936          * in vf_admin->rate and now, if priority supported we enforce the QoS
2937          */
2938         if (mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) &&
2939             vf_admin->tx_rate)
2940                 vf_admin->qos_vport = slave;
2941
2942         if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2943                 mlx4_info(dev,
2944                           "updating vf %d port %d config will take effect on next VF restart\n",
2945                           vf, port);
2946         return 0;
2947 }
2948 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2949
2950 int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate,
2951                      int max_tx_rate)
2952 {
2953         int err;
2954         int slave;
2955         struct mlx4_vport_state *vf_admin;
2956         struct mlx4_priv *priv = mlx4_priv(dev);
2957
2958         if (!mlx4_is_master(dev) ||
2959             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2960                 return -EPROTONOSUPPORT;
2961
2962         if (min_tx_rate) {
2963                 mlx4_info(dev, "Minimum BW share not supported\n");
2964                 return -EPROTONOSUPPORT;
2965         }
2966
2967         slave = mlx4_get_slave_indx(dev, vf);
2968         if (slave < 0)
2969                 return -EINVAL;
2970
2971         port = mlx4_slaves_closest_port(dev, slave, port);
2972         vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2973
2974         err = mlx4_set_vport_qos(priv, slave, port, max_tx_rate);
2975         if (err) {
2976                 mlx4_info(dev, "vf %d failed to set rate %d\n", vf,
2977                           max_tx_rate);
2978                 return err;
2979         }
2980
2981         vf_admin->tx_rate = max_tx_rate;
2982         /* if VF is not in supported mode (VST with supported prio),
2983          * we do not change vport configuration for its QPs, but save
2984          * the rate, so it will be enforced when it moves to supported
2985          * mode next time.
2986          */
2987         if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin)) {
2988                 mlx4_info(dev,
2989                           "rate set for VF %d when not in valid state\n", vf);
2990
2991                 if (vf_admin->default_vlan != MLX4_VGT)
2992                         mlx4_info(dev, "VST priority not supported by QoS\n");
2993                 else
2994                         mlx4_info(dev, "VF in VGT mode (needed VST)\n");
2995
2996                 mlx4_info(dev,
2997                           "rate %d take affect when VF moves to valid state\n",
2998                           max_tx_rate);
2999                 return 0;
3000         }
3001
3002         /* If user sets rate 0 assigning default vport for its QPs */
3003         vf_admin->qos_vport = max_tx_rate ? slave : MLX4_VPP_DEFAULT_VPORT;
3004
3005         if (priv->mfunc.master.slave_state[slave].active &&
3006             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)
3007                 mlx4_master_immediate_activate_vlan_qos(priv, slave, port);
3008
3009         return 0;
3010 }
3011 EXPORT_SYMBOL_GPL(mlx4_set_vf_rate);
3012
3013  /* mlx4_get_slave_default_vlan -
3014  * return true if VST ( default vlan)
3015  * if VST, will return vlan & qos (if not NULL)
3016  */
3017 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
3018                                  u16 *vlan, u8 *qos)
3019 {
3020         struct mlx4_vport_oper_state *vp_oper;
3021         struct mlx4_priv *priv;
3022
3023         priv = mlx4_priv(dev);
3024         port = mlx4_slaves_closest_port(dev, slave, port);
3025         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3026
3027         if (MLX4_VGT != vp_oper->state.default_vlan) {
3028                 if (vlan)
3029                         *vlan = vp_oper->state.default_vlan;
3030                 if (qos)
3031                         *qos = vp_oper->state.default_qos;
3032                 return true;
3033         }
3034         return false;
3035 }
3036 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
3037
3038 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
3039 {
3040         struct mlx4_priv *priv = mlx4_priv(dev);
3041         struct mlx4_vport_state *s_info;
3042         int slave;
3043
3044         if ((!mlx4_is_master(dev)) ||
3045             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
3046                 return -EPROTONOSUPPORT;
3047
3048         slave = mlx4_get_slave_indx(dev, vf);
3049         if (slave < 0)
3050                 return -EINVAL;
3051
3052         port = mlx4_slaves_closest_port(dev, slave, port);
3053         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3054         s_info->spoofchk = setting;
3055
3056         return 0;
3057 }
3058 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
3059
3060 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
3061 {
3062         struct mlx4_priv *priv = mlx4_priv(dev);
3063         struct mlx4_vport_state *s_info;
3064         int slave;
3065
3066         if (!mlx4_is_master(dev))
3067                 return -EPROTONOSUPPORT;
3068
3069         slave = mlx4_get_slave_indx(dev, vf);
3070         if (slave < 0)
3071                 return -EINVAL;
3072
3073         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3074         ivf->vf = vf;
3075
3076         /* need to convert it to a func */
3077         ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
3078         ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
3079         ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
3080         ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
3081         ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
3082         ivf->mac[5] = ((s_info->mac)  & 0xff);
3083
3084         ivf->vlan               = s_info->default_vlan;
3085         ivf->qos                = s_info->default_qos;
3086
3087         if (mlx4_is_vf_vst_and_prio_qos(dev, port, s_info))
3088                 ivf->max_tx_rate = s_info->tx_rate;
3089         else
3090                 ivf->max_tx_rate = 0;
3091
3092         ivf->min_tx_rate        = 0;
3093         ivf->spoofchk           = s_info->spoofchk;
3094         ivf->linkstate          = s_info->link_state;
3095
3096         return 0;
3097 }
3098 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
3099
3100 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
3101 {
3102         struct mlx4_priv *priv = mlx4_priv(dev);
3103         struct mlx4_vport_state *s_info;
3104         int slave;
3105         u8 link_stat_event;
3106
3107         slave = mlx4_get_slave_indx(dev, vf);
3108         if (slave < 0)
3109                 return -EINVAL;
3110
3111         port = mlx4_slaves_closest_port(dev, slave, port);
3112         switch (link_state) {
3113         case IFLA_VF_LINK_STATE_AUTO:
3114                 /* get current link state */
3115                 if (!priv->sense.do_sense_port[port])
3116                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3117                 else
3118                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3119             break;
3120
3121         case IFLA_VF_LINK_STATE_ENABLE:
3122                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3123             break;
3124
3125         case IFLA_VF_LINK_STATE_DISABLE:
3126                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3127             break;
3128
3129         default:
3130                 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
3131                           link_state, slave, port);
3132                 return -EINVAL;
3133         };
3134         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3135         s_info->link_state = link_state;
3136
3137         /* send event */
3138         mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
3139
3140         if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3141                 mlx4_dbg(dev,
3142                          "updating vf %d port %d no link state HW enforcment\n",
3143                          vf, port);
3144         return 0;
3145 }
3146 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
3147
3148 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
3149 {
3150         struct mlx4_priv *priv = mlx4_priv(dev);
3151
3152         if (slave < 1 || slave >= dev->num_slaves ||
3153             port < 1 || port > MLX4_MAX_PORTS)
3154                 return 0;
3155
3156         return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
3157                 MLX4_VF_SMI_ENABLED;
3158 }
3159 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
3160
3161 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
3162 {
3163         struct mlx4_priv *priv = mlx4_priv(dev);
3164
3165         if (slave == mlx4_master_func_num(dev))
3166                 return 1;
3167
3168         if (slave < 1 || slave >= dev->num_slaves ||
3169             port < 1 || port > MLX4_MAX_PORTS)
3170                 return 0;
3171
3172         return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
3173                 MLX4_VF_SMI_ENABLED;
3174 }
3175 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
3176
3177 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
3178                                  int enabled)
3179 {
3180         struct mlx4_priv *priv = mlx4_priv(dev);
3181
3182         if (slave == mlx4_master_func_num(dev))
3183                 return 0;
3184
3185         if (slave < 1 || slave >= dev->num_slaves ||
3186             port < 1 || port > MLX4_MAX_PORTS ||
3187             enabled < 0 || enabled > 1)
3188                 return -EINVAL;
3189
3190         priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
3191         return 0;
3192 }
3193 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);