2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/semaphore.h>
43 #include <rdma/ib_smi.h>
50 #define CMD_POLL_TOKEN 0xffff
51 #define INBOX_MASK 0xffffffffffffff00ULL
53 #define CMD_CHAN_VER 1
54 #define CMD_CHAN_IF_REV 1
57 /* command completed successfully: */
59 /* Internal error (such as a bus error) occurred while processing command: */
60 CMD_STAT_INTERNAL_ERR = 0x01,
61 /* Operation/command not supported or opcode modifier not supported: */
62 CMD_STAT_BAD_OP = 0x02,
63 /* Parameter not supported or parameter out of range: */
64 CMD_STAT_BAD_PARAM = 0x03,
65 /* System not enabled or bad system state: */
66 CMD_STAT_BAD_SYS_STATE = 0x04,
67 /* Attempt to access reserved or unallocaterd resource: */
68 CMD_STAT_BAD_RESOURCE = 0x05,
69 /* Requested resource is currently executing a command, or is otherwise busy: */
70 CMD_STAT_RESOURCE_BUSY = 0x06,
71 /* Required capability exceeds device limits: */
72 CMD_STAT_EXCEED_LIM = 0x08,
73 /* Resource is not in the appropriate state or ownership: */
74 CMD_STAT_BAD_RES_STATE = 0x09,
75 /* Index out of range: */
76 CMD_STAT_BAD_INDEX = 0x0a,
77 /* FW image corrupted: */
78 CMD_STAT_BAD_NVMEM = 0x0b,
79 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
80 CMD_STAT_ICM_ERROR = 0x0c,
81 /* Attempt to modify a QP/EE which is not in the presumed state: */
82 CMD_STAT_BAD_QP_STATE = 0x10,
83 /* Bad segment parameters (Address/Size): */
84 CMD_STAT_BAD_SEG_PARAM = 0x20,
85 /* Memory Region has Memory Windows bound to: */
86 CMD_STAT_REG_BOUND = 0x21,
87 /* HCA local attached memory not present: */
88 CMD_STAT_LAM_NOT_PRE = 0x22,
89 /* Bad management packet (silently discarded): */
90 CMD_STAT_BAD_PKT = 0x30,
91 /* More outstanding CQEs in CQ than new CQ size: */
92 CMD_STAT_BAD_SIZE = 0x40,
93 /* Multi Function device support required: */
94 CMD_STAT_MULTI_FUNC_REQ = 0x50,
98 HCR_IN_PARAM_OFFSET = 0x00,
99 HCR_IN_MODIFIER_OFFSET = 0x08,
100 HCR_OUT_PARAM_OFFSET = 0x0c,
101 HCR_TOKEN_OFFSET = 0x14,
102 HCR_STATUS_OFFSET = 0x18,
104 HCR_OPMOD_SHIFT = 12,
111 GO_BIT_TIMEOUT_MSECS = 10000
114 struct mlx4_cmd_context {
115 struct completion done;
123 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
124 struct mlx4_vhcr_cmd *in_vhcr);
126 static int mlx4_status_to_errno(u8 status)
128 static const int trans_table[] = {
129 [CMD_STAT_INTERNAL_ERR] = -EIO,
130 [CMD_STAT_BAD_OP] = -EPERM,
131 [CMD_STAT_BAD_PARAM] = -EINVAL,
132 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
133 [CMD_STAT_BAD_RESOURCE] = -EBADF,
134 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
135 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
136 [CMD_STAT_BAD_RES_STATE] = -EBADF,
137 [CMD_STAT_BAD_INDEX] = -EBADF,
138 [CMD_STAT_BAD_NVMEM] = -EFAULT,
139 [CMD_STAT_ICM_ERROR] = -ENFILE,
140 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
141 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
142 [CMD_STAT_REG_BOUND] = -EBUSY,
143 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
144 [CMD_STAT_BAD_PKT] = -EINVAL,
145 [CMD_STAT_BAD_SIZE] = -ENOMEM,
146 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
149 if (status >= ARRAY_SIZE(trans_table) ||
150 (status != CMD_STAT_OK && trans_table[status] == 0))
153 return trans_table[status];
156 static u8 mlx4_errno_to_status(int errno)
160 return CMD_STAT_BAD_OP;
162 return CMD_STAT_BAD_PARAM;
164 return CMD_STAT_BAD_SYS_STATE;
166 return CMD_STAT_RESOURCE_BUSY;
168 return CMD_STAT_EXCEED_LIM;
170 return CMD_STAT_ICM_ERROR;
172 return CMD_STAT_INTERNAL_ERR;
176 static int comm_pending(struct mlx4_dev *dev)
178 struct mlx4_priv *priv = mlx4_priv(dev);
179 u32 status = readl(&priv->mfunc.comm->slave_read);
181 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
184 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
186 struct mlx4_priv *priv = mlx4_priv(dev);
189 priv->cmd.comm_toggle ^= 1;
190 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
191 __raw_writel((__force u32) cpu_to_be32(val),
192 &priv->mfunc.comm->slave_write);
196 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
197 unsigned long timeout)
199 struct mlx4_priv *priv = mlx4_priv(dev);
202 int ret_from_pending = 0;
204 /* First, verify that the master reports correct status */
205 if (comm_pending(dev)) {
206 mlx4_warn(dev, "Communication channel is not idle."
207 "my toggle is %d (cmd:0x%x)\n",
208 priv->cmd.comm_toggle, cmd);
213 down(&priv->cmd.poll_sem);
214 mlx4_comm_cmd_post(dev, cmd, param);
216 end = msecs_to_jiffies(timeout) + jiffies;
217 while (comm_pending(dev) && time_before(jiffies, end))
219 ret_from_pending = comm_pending(dev);
220 if (ret_from_pending) {
221 /* check if the slave is trying to boot in the middle of
222 * FLR process. The only non-zero result in the RESET command
223 * is MLX4_DELAY_RESET_SLAVE*/
224 if ((MLX4_COMM_CMD_RESET == cmd)) {
225 mlx4_warn(dev, "Got slave FLRed from Communication"
226 " channel (ret:0x%x)\n", ret_from_pending);
227 err = MLX4_DELAY_RESET_SLAVE;
229 mlx4_warn(dev, "Communication channel timed out\n");
234 up(&priv->cmd.poll_sem);
238 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
239 u16 param, unsigned long timeout)
241 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
242 struct mlx4_cmd_context *context;
246 down(&cmd->event_sem);
248 spin_lock(&cmd->context_lock);
249 BUG_ON(cmd->free_head < 0);
250 context = &cmd->context[cmd->free_head];
251 context->token += cmd->token_mask + 1;
252 cmd->free_head = context->next;
253 spin_unlock(&cmd->context_lock);
255 init_completion(&context->done);
257 mlx4_comm_cmd_post(dev, op, param);
259 if (!wait_for_completion_timeout(&context->done,
260 msecs_to_jiffies(timeout))) {
265 err = context->result;
266 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
267 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
268 op, context->fw_status);
273 /* wait for comm channel ready
274 * this is necessary for prevention the race
275 * when switching between event to polling mode
277 end = msecs_to_jiffies(timeout) + jiffies;
278 while (comm_pending(dev) && time_before(jiffies, end))
281 spin_lock(&cmd->context_lock);
282 context->next = cmd->free_head;
283 cmd->free_head = context - cmd->context;
284 spin_unlock(&cmd->context_lock);
290 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
291 unsigned long timeout)
293 if (mlx4_priv(dev)->cmd.use_events)
294 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
295 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
298 static int cmd_pending(struct mlx4_dev *dev)
302 if (pci_channel_offline(dev->pdev))
305 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
307 return (status & swab32(1 << HCR_GO_BIT)) ||
308 (mlx4_priv(dev)->cmd.toggle ==
309 !!(status & swab32(1 << HCR_T_BIT)));
312 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
313 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
316 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
317 u32 __iomem *hcr = cmd->hcr;
321 mutex_lock(&cmd->hcr_mutex);
323 if (pci_channel_offline(dev->pdev)) {
325 * Device is going through error recovery
326 * and cannot accept commands.
334 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
336 while (cmd_pending(dev)) {
337 if (pci_channel_offline(dev->pdev)) {
339 * Device is going through error recovery
340 * and cannot accept commands.
346 if (time_after_eq(jiffies, end)) {
347 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
354 * We use writel (instead of something like memcpy_toio)
355 * because writes of less than 32 bits to the HCR don't work
356 * (and some architectures such as ia64 implement memcpy_toio
357 * in terms of writeb).
359 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
360 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
361 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
362 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
363 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
364 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
366 /* __raw_writel may not order writes. */
369 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
370 (cmd->toggle << HCR_T_BIT) |
371 (event ? (1 << HCR_E_BIT) : 0) |
372 (op_modifier << HCR_OPMOD_SHIFT) |
376 * Make sure that our HCR writes don't get mixed in with
377 * writes from another CPU starting a FW command.
381 cmd->toggle = cmd->toggle ^ 1;
386 mutex_unlock(&cmd->hcr_mutex);
390 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
391 int out_is_imm, u32 in_modifier, u8 op_modifier,
392 u16 op, unsigned long timeout)
394 struct mlx4_priv *priv = mlx4_priv(dev);
395 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
398 mutex_lock(&priv->cmd.slave_cmd_mutex);
400 vhcr->in_param = cpu_to_be64(in_param);
401 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
402 vhcr->in_modifier = cpu_to_be32(in_modifier);
403 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
404 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
406 vhcr->flags = !!(priv->cmd.use_events) << 6;
408 if (mlx4_is_master(dev)) {
409 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
414 be64_to_cpu(vhcr->out_param);
416 mlx4_err(dev, "response expected while"
417 "output mailbox is NULL for "
418 "command 0x%x\n", op);
419 vhcr->status = CMD_STAT_BAD_PARAM;
422 ret = mlx4_status_to_errno(vhcr->status);
425 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
426 MLX4_COMM_TIME + timeout);
431 be64_to_cpu(vhcr->out_param);
433 mlx4_err(dev, "response expected while"
434 "output mailbox is NULL for "
435 "command 0x%x\n", op);
436 vhcr->status = CMD_STAT_BAD_PARAM;
439 ret = mlx4_status_to_errno(vhcr->status);
441 mlx4_err(dev, "failed execution of VHCR_POST command"
442 "opcode 0x%x\n", op);
445 mutex_unlock(&priv->cmd.slave_cmd_mutex);
449 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
450 int out_is_imm, u32 in_modifier, u8 op_modifier,
451 u16 op, unsigned long timeout)
453 struct mlx4_priv *priv = mlx4_priv(dev);
454 void __iomem *hcr = priv->cmd.hcr;
459 down(&priv->cmd.poll_sem);
461 if (pci_channel_offline(dev->pdev)) {
463 * Device is going through error recovery
464 * and cannot accept commands.
470 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
471 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
475 end = msecs_to_jiffies(timeout) + jiffies;
476 while (cmd_pending(dev) && time_before(jiffies, end)) {
477 if (pci_channel_offline(dev->pdev)) {
479 * Device is going through error recovery
480 * and cannot accept commands.
489 if (cmd_pending(dev)) {
496 (u64) be32_to_cpu((__force __be32)
497 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
498 (u64) be32_to_cpu((__force __be32)
499 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
500 stat = be32_to_cpu((__force __be32)
501 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
502 err = mlx4_status_to_errno(stat);
504 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
508 up(&priv->cmd.poll_sem);
512 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
514 struct mlx4_priv *priv = mlx4_priv(dev);
515 struct mlx4_cmd_context *context =
516 &priv->cmd.context[token & priv->cmd.token_mask];
518 /* previously timed out command completing at long last */
519 if (token != context->token)
522 context->fw_status = status;
523 context->result = mlx4_status_to_errno(status);
524 context->out_param = out_param;
526 complete(&context->done);
529 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
530 int out_is_imm, u32 in_modifier, u8 op_modifier,
531 u16 op, unsigned long timeout)
533 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
534 struct mlx4_cmd_context *context;
537 down(&cmd->event_sem);
539 spin_lock(&cmd->context_lock);
540 BUG_ON(cmd->free_head < 0);
541 context = &cmd->context[cmd->free_head];
542 context->token += cmd->token_mask + 1;
543 cmd->free_head = context->next;
544 spin_unlock(&cmd->context_lock);
546 init_completion(&context->done);
548 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
549 in_modifier, op_modifier, op, context->token, 1);
551 if (!wait_for_completion_timeout(&context->done,
552 msecs_to_jiffies(timeout))) {
557 err = context->result;
559 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
560 op, context->fw_status);
565 *out_param = context->out_param;
568 spin_lock(&cmd->context_lock);
569 context->next = cmd->free_head;
570 cmd->free_head = context - cmd->context;
571 spin_unlock(&cmd->context_lock);
577 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
578 int out_is_imm, u32 in_modifier, u8 op_modifier,
579 u16 op, unsigned long timeout, int native)
581 if (pci_channel_offline(dev->pdev))
584 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
585 if (mlx4_priv(dev)->cmd.use_events)
586 return mlx4_cmd_wait(dev, in_param, out_param,
587 out_is_imm, in_modifier,
588 op_modifier, op, timeout);
590 return mlx4_cmd_poll(dev, in_param, out_param,
591 out_is_imm, in_modifier,
592 op_modifier, op, timeout);
594 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
595 in_modifier, op_modifier, op, timeout);
597 EXPORT_SYMBOL_GPL(__mlx4_cmd);
600 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
602 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
603 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
606 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
607 int slave, u64 slave_addr,
608 int size, int is_read)
613 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
614 (slave & ~0x7f) | (size & 0xff)) {
615 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
616 "master_addr:0x%llx slave_id:%d size:%d\n",
617 slave_addr, master_addr, slave, size);
622 in_param = (u64) slave | slave_addr;
623 out_param = (u64) dev->caps.function | master_addr;
625 in_param = (u64) dev->caps.function | master_addr;
626 out_param = (u64) slave | slave_addr;
629 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
631 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
634 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
635 struct mlx4_cmd_mailbox *inbox,
636 struct mlx4_cmd_mailbox *outbox)
638 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
639 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
646 in_mad->attr_mod = cpu_to_be32(index / 32);
648 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
649 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
654 for (i = 0; i < 32; ++i)
655 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
660 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
661 struct mlx4_cmd_mailbox *inbox,
662 struct mlx4_cmd_mailbox *outbox)
667 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
668 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
675 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
676 #define PORT_STATE_OFFSET 32
678 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
680 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
681 return IB_PORT_ACTIVE;
686 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
687 struct mlx4_vhcr *vhcr,
688 struct mlx4_cmd_mailbox *inbox,
689 struct mlx4_cmd_mailbox *outbox,
690 struct mlx4_cmd_info *cmd)
692 struct ib_smp *smp = inbox->buf;
698 struct mlx4_priv *priv = mlx4_priv(dev);
699 struct ib_smp *outsmp = outbox->buf;
700 __be16 *outtab = (__be16 *)(outsmp->data);
701 __be32 slave_cap_mask;
702 __be64 slave_node_guid;
703 port = vhcr->in_modifier;
705 if (smp->base_version == 1 &&
706 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
707 smp->class_version == 1) {
708 if (smp->method == IB_MGMT_METHOD_GET) {
709 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
710 index = be32_to_cpu(smp->attr_mod);
711 if (port < 1 || port > dev->caps.num_ports)
713 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
716 /* need to get the full pkey table because the paravirtualized
717 * pkeys may be scattered among several pkey blocks.
719 err = get_full_pkey_table(dev, port, table, inbox, outbox);
721 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
722 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
723 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
729 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
730 /*get the slave specific caps:*/
732 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
733 vhcr->in_modifier, vhcr->op_modifier,
734 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
735 /* modify the response for slaves */
736 if (!err && slave != mlx4_master_func_num(dev)) {
737 u8 *state = outsmp->data + PORT_STATE_OFFSET;
739 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
740 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
741 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
745 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
746 /* compute slave's gid block */
747 smp->attr_mod = cpu_to_be32(slave / 8);
749 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
750 vhcr->in_modifier, vhcr->op_modifier,
751 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
753 /* if needed, move slave gid to index 0 */
756 outsmp->data + (slave % 8) * 8, 8);
757 /* delete all other gids */
758 memset(outsmp->data + 8, 0, 56);
762 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
763 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
764 vhcr->in_modifier, vhcr->op_modifier,
765 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
767 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
768 memcpy(outsmp->data + 12, &slave_node_guid, 8);
774 if (slave != mlx4_master_func_num(dev) &&
775 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
776 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
777 smp->method == IB_MGMT_METHOD_SET))) {
778 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
779 "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
780 slave, smp->method, smp->mgmt_class,
781 be16_to_cpu(smp->attr_id));
785 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
786 vhcr->in_modifier, vhcr->op_modifier,
787 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
790 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
791 struct mlx4_vhcr *vhcr,
792 struct mlx4_cmd_mailbox *inbox,
793 struct mlx4_cmd_mailbox *outbox,
794 struct mlx4_cmd_info *cmd)
800 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
801 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
802 if (cmd->encode_slave_id) {
803 in_param &= 0xffffffffffffff00ll;
807 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
808 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
809 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
812 vhcr->out_param = out_param;
817 static struct mlx4_cmd_info cmd_info[] = {
819 .opcode = MLX4_CMD_QUERY_FW,
823 .encode_slave_id = false,
825 .wrapper = mlx4_QUERY_FW_wrapper
828 .opcode = MLX4_CMD_QUERY_HCA,
832 .encode_slave_id = false,
837 .opcode = MLX4_CMD_QUERY_DEV_CAP,
841 .encode_slave_id = false,
843 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
846 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
850 .encode_slave_id = false,
852 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
855 .opcode = MLX4_CMD_QUERY_ADAPTER,
859 .encode_slave_id = false,
864 .opcode = MLX4_CMD_INIT_PORT,
868 .encode_slave_id = false,
870 .wrapper = mlx4_INIT_PORT_wrapper
873 .opcode = MLX4_CMD_CLOSE_PORT,
877 .encode_slave_id = false,
879 .wrapper = mlx4_CLOSE_PORT_wrapper
882 .opcode = MLX4_CMD_QUERY_PORT,
886 .encode_slave_id = false,
888 .wrapper = mlx4_QUERY_PORT_wrapper
891 .opcode = MLX4_CMD_SET_PORT,
895 .encode_slave_id = false,
897 .wrapper = mlx4_SET_PORT_wrapper
900 .opcode = MLX4_CMD_MAP_EQ,
904 .encode_slave_id = false,
906 .wrapper = mlx4_MAP_EQ_wrapper
909 .opcode = MLX4_CMD_SW2HW_EQ,
913 .encode_slave_id = true,
915 .wrapper = mlx4_SW2HW_EQ_wrapper
918 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
922 .encode_slave_id = false,
927 .opcode = MLX4_CMD_NOP,
931 .encode_slave_id = false,
936 .opcode = MLX4_CMD_ALLOC_RES,
940 .encode_slave_id = false,
942 .wrapper = mlx4_ALLOC_RES_wrapper
945 .opcode = MLX4_CMD_FREE_RES,
949 .encode_slave_id = false,
951 .wrapper = mlx4_FREE_RES_wrapper
954 .opcode = MLX4_CMD_SW2HW_MPT,
958 .encode_slave_id = true,
960 .wrapper = mlx4_SW2HW_MPT_wrapper
963 .opcode = MLX4_CMD_QUERY_MPT,
967 .encode_slave_id = false,
969 .wrapper = mlx4_QUERY_MPT_wrapper
972 .opcode = MLX4_CMD_HW2SW_MPT,
976 .encode_slave_id = false,
978 .wrapper = mlx4_HW2SW_MPT_wrapper
981 .opcode = MLX4_CMD_READ_MTT,
985 .encode_slave_id = false,
990 .opcode = MLX4_CMD_WRITE_MTT,
994 .encode_slave_id = false,
996 .wrapper = mlx4_WRITE_MTT_wrapper
999 .opcode = MLX4_CMD_SYNC_TPT,
1001 .has_outbox = false,
1002 .out_is_imm = false,
1003 .encode_slave_id = false,
1008 .opcode = MLX4_CMD_HW2SW_EQ,
1011 .out_is_imm = false,
1012 .encode_slave_id = true,
1014 .wrapper = mlx4_HW2SW_EQ_wrapper
1017 .opcode = MLX4_CMD_QUERY_EQ,
1020 .out_is_imm = false,
1021 .encode_slave_id = true,
1023 .wrapper = mlx4_QUERY_EQ_wrapper
1026 .opcode = MLX4_CMD_SW2HW_CQ,
1028 .has_outbox = false,
1029 .out_is_imm = false,
1030 .encode_slave_id = true,
1032 .wrapper = mlx4_SW2HW_CQ_wrapper
1035 .opcode = MLX4_CMD_HW2SW_CQ,
1037 .has_outbox = false,
1038 .out_is_imm = false,
1039 .encode_slave_id = false,
1041 .wrapper = mlx4_HW2SW_CQ_wrapper
1044 .opcode = MLX4_CMD_QUERY_CQ,
1047 .out_is_imm = false,
1048 .encode_slave_id = false,
1050 .wrapper = mlx4_QUERY_CQ_wrapper
1053 .opcode = MLX4_CMD_MODIFY_CQ,
1055 .has_outbox = false,
1057 .encode_slave_id = false,
1059 .wrapper = mlx4_MODIFY_CQ_wrapper
1062 .opcode = MLX4_CMD_SW2HW_SRQ,
1064 .has_outbox = false,
1065 .out_is_imm = false,
1066 .encode_slave_id = true,
1068 .wrapper = mlx4_SW2HW_SRQ_wrapper
1071 .opcode = MLX4_CMD_HW2SW_SRQ,
1073 .has_outbox = false,
1074 .out_is_imm = false,
1075 .encode_slave_id = false,
1077 .wrapper = mlx4_HW2SW_SRQ_wrapper
1080 .opcode = MLX4_CMD_QUERY_SRQ,
1083 .out_is_imm = false,
1084 .encode_slave_id = false,
1086 .wrapper = mlx4_QUERY_SRQ_wrapper
1089 .opcode = MLX4_CMD_ARM_SRQ,
1091 .has_outbox = false,
1092 .out_is_imm = false,
1093 .encode_slave_id = false,
1095 .wrapper = mlx4_ARM_SRQ_wrapper
1098 .opcode = MLX4_CMD_RST2INIT_QP,
1100 .has_outbox = false,
1101 .out_is_imm = false,
1102 .encode_slave_id = true,
1104 .wrapper = mlx4_RST2INIT_QP_wrapper
1107 .opcode = MLX4_CMD_INIT2INIT_QP,
1109 .has_outbox = false,
1110 .out_is_imm = false,
1111 .encode_slave_id = false,
1113 .wrapper = mlx4_INIT2INIT_QP_wrapper
1116 .opcode = MLX4_CMD_INIT2RTR_QP,
1118 .has_outbox = false,
1119 .out_is_imm = false,
1120 .encode_slave_id = false,
1122 .wrapper = mlx4_INIT2RTR_QP_wrapper
1125 .opcode = MLX4_CMD_RTR2RTS_QP,
1127 .has_outbox = false,
1128 .out_is_imm = false,
1129 .encode_slave_id = false,
1131 .wrapper = mlx4_RTR2RTS_QP_wrapper
1134 .opcode = MLX4_CMD_RTS2RTS_QP,
1136 .has_outbox = false,
1137 .out_is_imm = false,
1138 .encode_slave_id = false,
1140 .wrapper = mlx4_RTS2RTS_QP_wrapper
1143 .opcode = MLX4_CMD_SQERR2RTS_QP,
1145 .has_outbox = false,
1146 .out_is_imm = false,
1147 .encode_slave_id = false,
1149 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1152 .opcode = MLX4_CMD_2ERR_QP,
1154 .has_outbox = false,
1155 .out_is_imm = false,
1156 .encode_slave_id = false,
1158 .wrapper = mlx4_GEN_QP_wrapper
1161 .opcode = MLX4_CMD_RTS2SQD_QP,
1163 .has_outbox = false,
1164 .out_is_imm = false,
1165 .encode_slave_id = false,
1167 .wrapper = mlx4_GEN_QP_wrapper
1170 .opcode = MLX4_CMD_SQD2SQD_QP,
1172 .has_outbox = false,
1173 .out_is_imm = false,
1174 .encode_slave_id = false,
1176 .wrapper = mlx4_SQD2SQD_QP_wrapper
1179 .opcode = MLX4_CMD_SQD2RTS_QP,
1181 .has_outbox = false,
1182 .out_is_imm = false,
1183 .encode_slave_id = false,
1185 .wrapper = mlx4_SQD2RTS_QP_wrapper
1188 .opcode = MLX4_CMD_2RST_QP,
1190 .has_outbox = false,
1191 .out_is_imm = false,
1192 .encode_slave_id = false,
1194 .wrapper = mlx4_2RST_QP_wrapper
1197 .opcode = MLX4_CMD_QUERY_QP,
1200 .out_is_imm = false,
1201 .encode_slave_id = false,
1203 .wrapper = mlx4_GEN_QP_wrapper
1206 .opcode = MLX4_CMD_SUSPEND_QP,
1208 .has_outbox = false,
1209 .out_is_imm = false,
1210 .encode_slave_id = false,
1212 .wrapper = mlx4_GEN_QP_wrapper
1215 .opcode = MLX4_CMD_UNSUSPEND_QP,
1217 .has_outbox = false,
1218 .out_is_imm = false,
1219 .encode_slave_id = false,
1221 .wrapper = mlx4_GEN_QP_wrapper
1224 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1226 .has_outbox = false,
1227 .out_is_imm = false,
1228 .encode_slave_id = false,
1229 .verify = NULL, /* XXX verify: only demux can do this */
1233 .opcode = MLX4_CMD_MAD_IFC,
1236 .out_is_imm = false,
1237 .encode_slave_id = false,
1239 .wrapper = mlx4_MAD_IFC_wrapper
1242 .opcode = MLX4_CMD_QUERY_IF_STAT,
1245 .out_is_imm = false,
1246 .encode_slave_id = false,
1248 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1250 /* Native multicast commands are not available for guests */
1252 .opcode = MLX4_CMD_QP_ATTACH,
1254 .has_outbox = false,
1255 .out_is_imm = false,
1256 .encode_slave_id = false,
1258 .wrapper = mlx4_QP_ATTACH_wrapper
1261 .opcode = MLX4_CMD_PROMISC,
1263 .has_outbox = false,
1264 .out_is_imm = false,
1265 .encode_slave_id = false,
1267 .wrapper = mlx4_PROMISC_wrapper
1269 /* Ethernet specific commands */
1271 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1273 .has_outbox = false,
1274 .out_is_imm = false,
1275 .encode_slave_id = false,
1277 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1280 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1282 .has_outbox = false,
1283 .out_is_imm = false,
1284 .encode_slave_id = false,
1286 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1289 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1292 .out_is_imm = false,
1293 .encode_slave_id = false,
1295 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1298 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1300 .has_outbox = false,
1301 .out_is_imm = false,
1302 .encode_slave_id = false,
1306 /* flow steering commands */
1308 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1310 .has_outbox = false,
1312 .encode_slave_id = false,
1314 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1317 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1319 .has_outbox = false,
1320 .out_is_imm = false,
1321 .encode_slave_id = false,
1323 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1327 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1328 struct mlx4_vhcr_cmd *in_vhcr)
1330 struct mlx4_priv *priv = mlx4_priv(dev);
1331 struct mlx4_cmd_info *cmd = NULL;
1332 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1333 struct mlx4_vhcr *vhcr;
1334 struct mlx4_cmd_mailbox *inbox = NULL;
1335 struct mlx4_cmd_mailbox *outbox = NULL;
1342 /* Create sw representation of Virtual HCR */
1343 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1347 /* DMA in the vHCR */
1349 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1350 priv->mfunc.master.slave_state[slave].vhcr_dma,
1351 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1352 MLX4_ACCESS_MEM_ALIGN), 1);
1354 mlx4_err(dev, "%s:Failed reading vhcr"
1355 "ret: 0x%x\n", __func__, ret);
1361 /* Fill SW VHCR fields */
1362 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1363 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1364 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1365 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1366 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1367 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1368 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1370 /* Lookup command */
1371 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1372 if (vhcr->op == cmd_info[i].opcode) {
1378 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1380 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1385 if (cmd->has_inbox) {
1386 vhcr->in_param &= INBOX_MASK;
1387 inbox = mlx4_alloc_cmd_mailbox(dev);
1388 if (IS_ERR(inbox)) {
1389 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1394 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1396 MLX4_MAILBOX_SIZE, 1)) {
1397 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1398 __func__, cmd->opcode);
1399 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1404 /* Apply permission and bound checks if applicable */
1405 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1406 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1407 "checks for resource_id:%d\n", vhcr->op, slave,
1409 vhcr_cmd->status = CMD_STAT_BAD_OP;
1413 /* Allocate outbox */
1414 if (cmd->has_outbox) {
1415 outbox = mlx4_alloc_cmd_mailbox(dev);
1416 if (IS_ERR(outbox)) {
1417 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1423 /* Execute the command! */
1425 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1427 if (cmd->out_is_imm)
1428 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1430 in_param = cmd->has_inbox ? (u64) inbox->dma :
1432 out_param = cmd->has_outbox ? (u64) outbox->dma :
1434 err = __mlx4_cmd(dev, in_param, &out_param,
1435 cmd->out_is_imm, vhcr->in_modifier,
1436 vhcr->op_modifier, vhcr->op,
1437 MLX4_CMD_TIME_CLASS_A,
1440 if (cmd->out_is_imm) {
1441 vhcr->out_param = out_param;
1442 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1447 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1448 " error:%d, status %d\n",
1449 vhcr->op, slave, vhcr->errno, err);
1450 vhcr_cmd->status = mlx4_errno_to_status(err);
1455 /* Write outbox if command completed successfully */
1456 if (cmd->has_outbox && !vhcr_cmd->status) {
1457 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1459 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1461 /* If we failed to write back the outbox after the
1462 *command was successfully executed, we must fail this
1463 * slave, as it is now in undefined state */
1464 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1470 /* DMA back vhcr result */
1472 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1473 priv->mfunc.master.slave_state[slave].vhcr_dma,
1474 ALIGN(sizeof(struct mlx4_vhcr),
1475 MLX4_ACCESS_MEM_ALIGN),
1478 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1480 else if (vhcr->e_bit &&
1481 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1482 mlx4_warn(dev, "Failed to generate command completion "
1483 "eqe for slave %d\n", slave);
1488 mlx4_free_cmd_mailbox(dev, inbox);
1489 mlx4_free_cmd_mailbox(dev, outbox);
1493 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1494 u16 param, u8 toggle)
1496 struct mlx4_priv *priv = mlx4_priv(dev);
1497 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1499 u8 is_going_down = 0;
1501 unsigned long flags;
1503 slave_state[slave].comm_toggle ^= 1;
1504 reply = (u32) slave_state[slave].comm_toggle << 31;
1505 if (toggle != slave_state[slave].comm_toggle) {
1506 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1507 "STATE COMPROMISIED ***\n", toggle, slave);
1510 if (cmd == MLX4_COMM_CMD_RESET) {
1511 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1512 slave_state[slave].active = false;
1513 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1514 slave_state[slave].event_eq[i].eqn = -1;
1515 slave_state[slave].event_eq[i].token = 0;
1517 /*check if we are in the middle of FLR process,
1518 if so return "retry" status to the slave*/
1519 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1520 goto inform_slave_state;
1522 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1524 /* write the version in the event field */
1525 reply |= mlx4_comm_get_version();
1529 /*command from slave in the middle of FLR*/
1530 if (cmd != MLX4_COMM_CMD_RESET &&
1531 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1532 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1533 "in the middle of FLR\n", slave, cmd);
1538 case MLX4_COMM_CMD_VHCR0:
1539 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1541 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1542 priv->mfunc.master.slave_state[slave].cookie = 0;
1543 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1545 case MLX4_COMM_CMD_VHCR1:
1546 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1548 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1550 case MLX4_COMM_CMD_VHCR2:
1551 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1553 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1555 case MLX4_COMM_CMD_VHCR_EN:
1556 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1558 slave_state[slave].vhcr_dma |= param;
1559 slave_state[slave].active = true;
1560 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1562 case MLX4_COMM_CMD_VHCR_POST:
1563 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1564 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1567 mutex_lock(&priv->cmd.slave_cmd_mutex);
1568 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1569 mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1570 " resetting slave.\n", slave);
1571 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1574 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1577 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1580 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1581 if (!slave_state[slave].is_slave_going_down)
1582 slave_state[slave].last_cmd = cmd;
1585 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1586 if (is_going_down) {
1587 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1588 " executing from slave:%d\n",
1592 __raw_writel((__force u32) cpu_to_be32(reply),
1593 &priv->mfunc.comm[slave].slave_read);
1599 /* cleanup any slave resources */
1600 mlx4_delete_all_resources_for_slave(dev, slave);
1601 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1602 if (!slave_state[slave].is_slave_going_down)
1603 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1604 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1605 /*with slave in the middle of flr, no need to clean resources again.*/
1607 memset(&slave_state[slave].event_eq, 0,
1608 sizeof(struct mlx4_slave_event_eq_info));
1609 __raw_writel((__force u32) cpu_to_be32(reply),
1610 &priv->mfunc.comm[slave].slave_read);
1614 /* master command processing */
1615 void mlx4_master_comm_channel(struct work_struct *work)
1617 struct mlx4_mfunc_master_ctx *master =
1619 struct mlx4_mfunc_master_ctx,
1621 struct mlx4_mfunc *mfunc =
1622 container_of(master, struct mlx4_mfunc, master);
1623 struct mlx4_priv *priv =
1624 container_of(mfunc, struct mlx4_priv, mfunc);
1625 struct mlx4_dev *dev = &priv->dev;
1635 bit_vec = master->comm_arm_bit_vector;
1636 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1637 vec = be32_to_cpu(bit_vec[i]);
1638 for (j = 0; j < 32; j++) {
1639 if (!(vec & (1 << j)))
1642 slave = (i * 32) + j;
1643 comm_cmd = swab32(readl(
1644 &mfunc->comm[slave].slave_write));
1645 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1647 toggle = comm_cmd >> 31;
1648 if (toggle != slt) {
1649 if (master->slave_state[slave].comm_toggle
1651 printk(KERN_INFO "slave %d out of sync."
1652 " read toggle %d, state toggle %d. "
1653 "Resynching.\n", slave, slt,
1654 master->slave_state[slave].comm_toggle);
1655 master->slave_state[slave].comm_toggle =
1658 mlx4_master_do_cmd(dev, slave,
1659 comm_cmd >> 16 & 0xff,
1660 comm_cmd & 0xffff, toggle);
1666 if (reported && reported != served)
1667 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1668 " but %d were served\n",
1671 if (mlx4_ARM_COMM_CHANNEL(dev))
1672 mlx4_warn(dev, "Failed to arm comm channel events\n");
1675 static int sync_toggles(struct mlx4_dev *dev)
1677 struct mlx4_priv *priv = mlx4_priv(dev);
1682 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1683 end = jiffies + msecs_to_jiffies(5000);
1685 while (time_before(jiffies, end)) {
1686 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1687 if (rd_toggle == wr_toggle) {
1688 priv->cmd.comm_toggle = rd_toggle;
1696 * we could reach here if for example the previous VM using this
1697 * function misbehaved and left the channel with unsynced state. We
1698 * should fix this here and give this VM a chance to use a properly
1701 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1702 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1703 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1704 priv->cmd.comm_toggle = 0;
1709 int mlx4_multi_func_init(struct mlx4_dev *dev)
1711 struct mlx4_priv *priv = mlx4_priv(dev);
1712 struct mlx4_slave_state *s_state;
1713 int i, j, err, port;
1715 if (mlx4_is_master(dev))
1717 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1718 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1721 ioremap(pci_resource_start(dev->pdev, 2) +
1722 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1723 if (!priv->mfunc.comm) {
1724 mlx4_err(dev, "Couldn't map communication vector.\n");
1728 if (mlx4_is_master(dev)) {
1729 priv->mfunc.master.slave_state =
1730 kzalloc(dev->num_slaves *
1731 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1732 if (!priv->mfunc.master.slave_state)
1735 for (i = 0; i < dev->num_slaves; ++i) {
1736 s_state = &priv->mfunc.master.slave_state[i];
1737 s_state->last_cmd = MLX4_COMM_CMD_RESET;
1738 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1739 s_state->event_eq[j].eqn = -1;
1740 __raw_writel((__force u32) 0,
1741 &priv->mfunc.comm[i].slave_write);
1742 __raw_writel((__force u32) 0,
1743 &priv->mfunc.comm[i].slave_read);
1745 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1746 s_state->vlan_filter[port] =
1747 kzalloc(sizeof(struct mlx4_vlan_fltr),
1749 if (!s_state->vlan_filter[port]) {
1751 kfree(s_state->vlan_filter[port]);
1754 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1756 spin_lock_init(&s_state->lock);
1759 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
1760 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1761 INIT_WORK(&priv->mfunc.master.comm_work,
1762 mlx4_master_comm_channel);
1763 INIT_WORK(&priv->mfunc.master.slave_event_work,
1764 mlx4_gen_slave_eqe);
1765 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1766 mlx4_master_handle_slave_flr);
1767 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1768 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1769 priv->mfunc.master.comm_wq =
1770 create_singlethread_workqueue("mlx4_comm");
1771 if (!priv->mfunc.master.comm_wq)
1774 if (mlx4_init_resource_tracker(dev))
1777 err = mlx4_ARM_COMM_CHANNEL(dev);
1779 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1785 err = sync_toggles(dev);
1787 mlx4_err(dev, "Couldn't sync toggles\n");
1794 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1796 flush_workqueue(priv->mfunc.master.comm_wq);
1797 destroy_workqueue(priv->mfunc.master.comm_wq);
1800 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1801 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1803 kfree(priv->mfunc.master.slave_state);
1805 iounmap(priv->mfunc.comm);
1807 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1809 priv->mfunc.vhcr_dma);
1810 priv->mfunc.vhcr = NULL;
1814 int mlx4_cmd_init(struct mlx4_dev *dev)
1816 struct mlx4_priv *priv = mlx4_priv(dev);
1818 mutex_init(&priv->cmd.hcr_mutex);
1819 mutex_init(&priv->cmd.slave_cmd_mutex);
1820 sema_init(&priv->cmd.poll_sem, 1);
1821 priv->cmd.use_events = 0;
1822 priv->cmd.toggle = 1;
1824 priv->cmd.hcr = NULL;
1825 priv->mfunc.vhcr = NULL;
1827 if (!mlx4_is_slave(dev)) {
1828 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1829 MLX4_HCR_BASE, MLX4_HCR_SIZE);
1830 if (!priv->cmd.hcr) {
1831 mlx4_err(dev, "Couldn't map command register.\n");
1836 if (mlx4_is_mfunc(dev)) {
1837 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1838 &priv->mfunc.vhcr_dma,
1840 if (!priv->mfunc.vhcr) {
1841 mlx4_err(dev, "Couldn't allocate VHCR.\n");
1846 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1848 MLX4_MAILBOX_SIZE, 0);
1849 if (!priv->cmd.pool)
1855 if (mlx4_is_mfunc(dev))
1856 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1857 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1858 priv->mfunc.vhcr = NULL;
1861 if (!mlx4_is_slave(dev))
1862 iounmap(priv->cmd.hcr);
1866 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1868 struct mlx4_priv *priv = mlx4_priv(dev);
1871 if (mlx4_is_master(dev)) {
1872 flush_workqueue(priv->mfunc.master.comm_wq);
1873 destroy_workqueue(priv->mfunc.master.comm_wq);
1874 for (i = 0; i < dev->num_slaves; i++) {
1875 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1876 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1878 kfree(priv->mfunc.master.slave_state);
1881 iounmap(priv->mfunc.comm);
1884 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
1886 struct mlx4_priv *priv = mlx4_priv(dev);
1888 pci_pool_destroy(priv->cmd.pool);
1890 if (!mlx4_is_slave(dev))
1891 iounmap(priv->cmd.hcr);
1892 if (mlx4_is_mfunc(dev))
1893 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1894 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1895 priv->mfunc.vhcr = NULL;
1899 * Switch to using events to issue FW commands (can only be called
1900 * after event queue for command events has been initialized).
1902 int mlx4_cmd_use_events(struct mlx4_dev *dev)
1904 struct mlx4_priv *priv = mlx4_priv(dev);
1908 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
1909 sizeof (struct mlx4_cmd_context),
1911 if (!priv->cmd.context)
1914 for (i = 0; i < priv->cmd.max_cmds; ++i) {
1915 priv->cmd.context[i].token = i;
1916 priv->cmd.context[i].next = i + 1;
1919 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
1920 priv->cmd.free_head = 0;
1922 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
1923 spin_lock_init(&priv->cmd.context_lock);
1925 for (priv->cmd.token_mask = 1;
1926 priv->cmd.token_mask < priv->cmd.max_cmds;
1927 priv->cmd.token_mask <<= 1)
1929 --priv->cmd.token_mask;
1931 down(&priv->cmd.poll_sem);
1932 priv->cmd.use_events = 1;
1938 * Switch back to polling (used when shutting down the device)
1940 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
1942 struct mlx4_priv *priv = mlx4_priv(dev);
1945 priv->cmd.use_events = 0;
1947 for (i = 0; i < priv->cmd.max_cmds; ++i)
1948 down(&priv->cmd.event_sem);
1950 kfree(priv->cmd.context);
1952 up(&priv->cmd.poll_sem);
1955 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
1957 struct mlx4_cmd_mailbox *mailbox;
1959 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
1961 return ERR_PTR(-ENOMEM);
1963 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
1965 if (!mailbox->buf) {
1967 return ERR_PTR(-ENOMEM);
1972 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
1974 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
1975 struct mlx4_cmd_mailbox *mailbox)
1980 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
1983 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
1985 u32 mlx4_comm_get_version(void)
1987 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;