2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <net/busy_poll.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/rculist.h>
40 #include <linux/if_ether.h>
41 #include <linux/if_vlan.h>
42 #include <linux/vmalloc.h>
46 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
47 struct mlx4_en_rx_alloc *page_alloc,
48 const struct mlx4_en_frag_info *frag_info,
55 for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
59 gfp |= __GFP_COMP | __GFP_NOWARN;
60 page = alloc_pages(gfp, order);
64 ((PAGE_SIZE << order) < frag_info->frag_size))
67 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
69 if (dma_mapping_error(priv->ddev, dma)) {
73 page_alloc->page_size = PAGE_SIZE << order;
74 page_alloc->page = page;
75 page_alloc->dma = dma;
76 page_alloc->page_offset = frag_info->frag_align;
77 /* Not doing get_page() for each frag is a big win
78 * on asymetric workloads.
80 atomic_set(&page->_count,
81 page_alloc->page_size / frag_info->frag_stride);
85 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
86 struct mlx4_en_rx_desc *rx_desc,
87 struct mlx4_en_rx_alloc *frags,
88 struct mlx4_en_rx_alloc *ring_alloc,
91 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
92 const struct mlx4_en_frag_info *frag_info;
97 for (i = 0; i < priv->num_frags; i++) {
98 frag_info = &priv->frag_info[i];
99 page_alloc[i] = ring_alloc[i];
100 page_alloc[i].page_offset += frag_info->frag_stride;
102 if (page_alloc[i].page_offset + frag_info->frag_stride <=
103 ring_alloc[i].page_size)
106 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
110 for (i = 0; i < priv->num_frags; i++) {
111 frags[i] = ring_alloc[i];
112 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
113 ring_alloc[i] = page_alloc[i];
114 rx_desc->data[i].addr = cpu_to_be64(dma);
121 frag_info = &priv->frag_info[i];
122 if (page_alloc[i].page != ring_alloc[i].page) {
123 dma_unmap_page(priv->ddev, page_alloc[i].dma,
124 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
125 page = page_alloc[i].page;
126 atomic_set(&page->_count, 1);
133 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
134 struct mlx4_en_rx_alloc *frags,
137 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
138 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
141 if (next_frag_end > frags[i].page_size)
142 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
146 put_page(frags[i].page);
149 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
150 struct mlx4_en_rx_ring *ring)
153 struct mlx4_en_rx_alloc *page_alloc;
155 for (i = 0; i < priv->num_frags; i++) {
156 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
158 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
159 frag_info, GFP_KERNEL))
168 page_alloc = &ring->page_alloc[i];
169 dma_unmap_page(priv->ddev, page_alloc->dma,
170 page_alloc->page_size, PCI_DMA_FROMDEVICE);
171 page = page_alloc->page;
172 atomic_set(&page->_count, 1);
174 page_alloc->page = NULL;
179 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
180 struct mlx4_en_rx_ring *ring)
182 struct mlx4_en_rx_alloc *page_alloc;
185 for (i = 0; i < priv->num_frags; i++) {
186 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
188 page_alloc = &ring->page_alloc[i];
189 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
190 i, page_count(page_alloc->page));
192 dma_unmap_page(priv->ddev, page_alloc->dma,
193 page_alloc->page_size, PCI_DMA_FROMDEVICE);
194 while (page_alloc->page_offset + frag_info->frag_stride <
195 page_alloc->page_size) {
196 put_page(page_alloc->page);
197 page_alloc->page_offset += frag_info->frag_stride;
199 page_alloc->page = NULL;
203 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
204 struct mlx4_en_rx_ring *ring, int index)
206 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
210 /* Set size and memtype fields */
211 for (i = 0; i < priv->num_frags; i++) {
212 rx_desc->data[i].byte_count =
213 cpu_to_be32(priv->frag_info[i].frag_size);
214 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
217 /* If the number of used fragments does not fill up the ring stride,
218 * remaining (unused) fragments must be padded with null address/size
219 * and a special memory key */
220 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
221 for (i = priv->num_frags; i < possible_frags; i++) {
222 rx_desc->data[i].byte_count = 0;
223 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
224 rx_desc->data[i].addr = 0;
228 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
229 struct mlx4_en_rx_ring *ring, int index,
232 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
233 struct mlx4_en_rx_alloc *frags = ring->rx_info +
234 (index << priv->log_rx_info);
236 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
239 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
241 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
244 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
245 struct mlx4_en_rx_ring *ring,
248 struct mlx4_en_rx_alloc *frags;
251 frags = ring->rx_info + (index << priv->log_rx_info);
252 for (nr = 0; nr < priv->num_frags; nr++) {
253 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
254 mlx4_en_free_frag(priv, frags, nr);
258 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
260 struct mlx4_en_rx_ring *ring;
265 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
266 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
267 ring = priv->rx_ring[ring_ind];
269 if (mlx4_en_prepare_rx_desc(priv, ring,
272 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
273 en_err(priv, "Failed to allocate enough rx buffers\n");
276 new_size = rounddown_pow_of_two(ring->actual_size);
277 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
278 ring->actual_size, new_size);
289 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
290 ring = priv->rx_ring[ring_ind];
291 while (ring->actual_size > new_size) {
294 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
301 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
302 struct mlx4_en_rx_ring *ring)
306 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
307 ring->cons, ring->prod);
309 /* Unmap and free Rx buffers */
310 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
311 while (ring->cons != ring->prod) {
312 index = ring->cons & ring->size_mask;
313 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
314 mlx4_en_free_rx_desc(priv, ring, index);
319 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
324 struct mlx4_dev *dev = mdev->dev;
326 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
327 if (!dev->caps.comp_pool)
328 num_of_eqs = max_t(int, MIN_RX_RINGS,
330 dev->caps.num_comp_vectors,
333 num_of_eqs = min_t(int, MAX_MSIX_P_PORT,
335 dev->caps.num_ports) - 1;
337 num_rx_rings = min_t(int, num_of_eqs,
338 netif_get_num_default_rss_queues());
339 mdev->profile.prof[i].rx_ring_num =
340 rounddown_pow_of_two(num_rx_rings);
344 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
345 struct mlx4_en_rx_ring **pring,
346 u32 size, u16 stride, int node)
348 struct mlx4_en_dev *mdev = priv->mdev;
349 struct mlx4_en_rx_ring *ring;
353 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
355 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
357 en_err(priv, "Failed to allocate RX ring structure\n");
365 ring->size_mask = size - 1;
366 ring->stride = stride;
367 ring->log_stride = ffs(ring->stride) - 1;
368 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
370 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
371 sizeof(struct mlx4_en_rx_alloc));
372 ring->rx_info = vmalloc_node(tmp, node);
373 if (!ring->rx_info) {
374 ring->rx_info = vmalloc(tmp);
375 if (!ring->rx_info) {
381 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
384 /* Allocate HW buffers on provided NUMA node */
385 set_dev_node(&mdev->dev->pdev->dev, node);
386 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
387 ring->buf_size, 2 * PAGE_SIZE);
388 set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
392 err = mlx4_en_map_buffer(&ring->wqres.buf);
394 en_err(priv, "Failed to map RX buffer\n");
397 ring->buf = ring->wqres.buf.direct.buf;
399 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
405 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
407 vfree(ring->rx_info);
408 ring->rx_info = NULL;
416 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
418 struct mlx4_en_rx_ring *ring;
422 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
423 DS_SIZE * priv->num_frags);
425 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
426 ring = priv->rx_ring[ring_ind];
430 ring->actual_size = 0;
431 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
433 ring->stride = stride;
434 if (ring->stride <= TXBB_SIZE)
435 ring->buf += TXBB_SIZE;
437 ring->log_stride = ffs(ring->stride) - 1;
438 ring->buf_size = ring->size * ring->stride;
440 memset(ring->buf, 0, ring->buf_size);
441 mlx4_en_update_rx_prod_db(ring);
443 /* Initialize all descriptors */
444 for (i = 0; i < ring->size; i++)
445 mlx4_en_init_rx_desc(priv, ring, i);
447 /* Initialize page allocators */
448 err = mlx4_en_init_allocator(priv, ring);
450 en_err(priv, "Failed initializing ring allocator\n");
451 if (ring->stride <= TXBB_SIZE)
452 ring->buf -= TXBB_SIZE;
457 err = mlx4_en_fill_rx_buffers(priv);
461 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
462 ring = priv->rx_ring[ring_ind];
464 ring->size_mask = ring->actual_size - 1;
465 mlx4_en_update_rx_prod_db(ring);
471 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
472 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
474 ring_ind = priv->rx_ring_num - 1;
476 while (ring_ind >= 0) {
477 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
478 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
479 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
485 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
486 struct mlx4_en_rx_ring **pring,
487 u32 size, u16 stride)
489 struct mlx4_en_dev *mdev = priv->mdev;
490 struct mlx4_en_rx_ring *ring = *pring;
492 mlx4_en_unmap_buffer(&ring->wqres.buf);
493 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
494 vfree(ring->rx_info);
495 ring->rx_info = NULL;
498 #ifdef CONFIG_RFS_ACCEL
499 mlx4_en_cleanup_filters(priv);
503 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
504 struct mlx4_en_rx_ring *ring)
506 mlx4_en_free_rx_buf(priv, ring);
507 if (ring->stride <= TXBB_SIZE)
508 ring->buf -= TXBB_SIZE;
509 mlx4_en_destroy_allocator(priv, ring);
513 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
514 struct mlx4_en_rx_desc *rx_desc,
515 struct mlx4_en_rx_alloc *frags,
519 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
520 struct mlx4_en_frag_info *frag_info;
524 /* Collect used fragments while replacing them in the HW descriptors */
525 for (nr = 0; nr < priv->num_frags; nr++) {
526 frag_info = &priv->frag_info[nr];
527 if (length <= frag_info->frag_prefix_size)
532 dma = be64_to_cpu(rx_desc->data[nr].addr);
533 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
536 /* Save page reference in skb */
537 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
538 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
539 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
540 skb->truesize += frag_info->frag_stride;
541 frags[nr].page = NULL;
543 /* Adjust size of last fragment to match actual length */
545 skb_frag_size_set(&skb_frags_rx[nr - 1],
546 length - priv->frag_info[nr - 1].frag_prefix_size);
552 __skb_frag_unref(&skb_frags_rx[nr]);
558 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
559 struct mlx4_en_rx_desc *rx_desc,
560 struct mlx4_en_rx_alloc *frags,
568 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
570 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
573 skb_reserve(skb, NET_IP_ALIGN);
576 /* Get pointer to first fragment so we could copy the headers into the
577 * (linear part of the) skb */
578 va = page_address(frags[0].page) + frags[0].page_offset;
580 if (length <= SMALL_PACKET_SIZE) {
581 /* We are copying all relevant data to the skb - temporarily
582 * sync buffers for the copy */
583 dma = be64_to_cpu(rx_desc->data[0].addr);
584 dma_sync_single_for_cpu(priv->ddev, dma, length,
586 skb_copy_to_linear_data(skb, va, length);
589 /* Move relevant fragments to skb */
590 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
592 if (unlikely(!used_frags)) {
596 skb_shinfo(skb)->nr_frags = used_frags;
598 /* Copy headers into the skb linear buffer */
599 memcpy(skb->data, va, HEADER_COPY_SIZE);
600 skb->tail += HEADER_COPY_SIZE;
602 /* Skip headers in first fragment */
603 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
605 /* Adjust size of first fragment */
606 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
607 skb->data_len = length - HEADER_COPY_SIZE;
612 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
615 int offset = ETH_HLEN;
617 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
618 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
622 priv->loopback_ok = 1;
625 dev_kfree_skb_any(skb);
628 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
629 struct mlx4_en_rx_ring *ring)
631 int index = ring->prod & ring->size_mask;
633 while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
634 if (mlx4_en_prepare_rx_desc(priv, ring, index, GFP_ATOMIC))
637 index = ring->prod & ring->size_mask;
641 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
643 struct mlx4_en_priv *priv = netdev_priv(dev);
644 struct mlx4_en_dev *mdev = priv->mdev;
645 struct mlx4_cqe *cqe;
646 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
647 struct mlx4_en_rx_alloc *frags;
648 struct mlx4_en_rx_desc *rx_desc;
655 int factor = priv->cqe_factor;
665 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
666 * descriptor offset can be deduced from the CQE index instead of
667 * reading 'cqe->index' */
668 index = cq->mcq.cons_index & ring->size_mask;
669 cqe = &cq->buf[(index << factor) + factor];
671 /* Process all completed CQEs */
672 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
673 cq->mcq.cons_index & cq->size)) {
675 frags = ring->rx_info + (index << priv->log_rx_info);
676 rx_desc = ring->buf + (index << ring->log_stride);
679 * make sure we read the CQE after we read the ownership bit
683 /* Drop packet on bad receive or bad checksum */
684 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
685 MLX4_CQE_OPCODE_ERROR)) {
686 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
687 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
688 ((struct mlx4_err_cqe *)cqe)->syndrome);
691 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
692 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
696 /* Check if we need to drop the packet if SRIOV is not enabled
697 * and not performing the selftest or flb disabled
699 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
702 /* Get pointer to first fragment since we haven't
703 * skb yet and cast it to ethhdr struct
705 dma = be64_to_cpu(rx_desc->data[0].addr);
706 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
708 ethh = (struct ethhdr *)(page_address(frags[0].page) +
709 frags[0].page_offset);
711 if (is_multicast_ether_addr(ethh->h_dest)) {
712 struct mlx4_mac_entry *entry;
713 struct hlist_head *bucket;
714 unsigned int mac_hash;
716 /* Drop the packet, since HW loopback-ed it */
717 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
718 bucket = &priv->mac_hash[mac_hash];
720 hlist_for_each_entry_rcu(entry, bucket, hlist) {
721 if (ether_addr_equal_64bits(entry->mac,
732 * Packet is OK - process it.
734 length = be32_to_cpu(cqe->byte_cnt);
735 length -= ring->fcs_del;
736 ring->bytes += length;
738 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
739 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
741 if (likely(dev->features & NETIF_F_RXCSUM)) {
742 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
743 (cqe->checksum == cpu_to_be16(0xffff))) {
745 /* This packet is eligible for GRO if it is:
746 * - DIX Ethernet (type interpretation)
748 * - without IP options
749 * - not an IP fragment
750 * - no LLS polling in progress
752 if (!mlx4_en_cq_busy_polling(cq) &&
753 (dev->features & NETIF_F_GRO)) {
754 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
758 nr = mlx4_en_complete_rx_desc(priv,
759 rx_desc, frags, gro_skb,
764 skb_shinfo(gro_skb)->nr_frags = nr;
765 gro_skb->len = length;
766 gro_skb->data_len = length;
767 gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
770 gro_skb->encapsulation = 1;
771 if ((cqe->vlan_my_qpn &
772 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
773 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
774 u16 vid = be16_to_cpu(cqe->sl_vid);
776 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
779 if (dev->features & NETIF_F_RXHASH)
780 skb_set_hash(gro_skb,
781 be32_to_cpu(cqe->immed_rss_invalid),
784 skb_record_rx_queue(gro_skb, cq->ring);
786 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
787 timestamp = mlx4_en_get_cqe_ts(cqe);
788 mlx4_en_fill_hwtstamps(mdev,
789 skb_hwtstamps(gro_skb),
793 napi_gro_frags(&cq->napi);
797 /* GRO not possible, complete processing here */
798 ip_summed = CHECKSUM_UNNECESSARY;
800 ip_summed = CHECKSUM_NONE;
804 ip_summed = CHECKSUM_NONE;
808 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
810 priv->stats.rx_dropped++;
814 if (unlikely(priv->validate_loopback)) {
815 validate_loopback(priv, skb);
819 skb->ip_summed = ip_summed;
820 skb->protocol = eth_type_trans(skb, dev);
821 skb_record_rx_queue(skb, cq->ring);
824 skb->encapsulation = 1;
826 if (dev->features & NETIF_F_RXHASH)
828 be32_to_cpu(cqe->immed_rss_invalid),
831 if ((be32_to_cpu(cqe->vlan_my_qpn) &
832 MLX4_CQE_VLAN_PRESENT_MASK) &&
833 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
834 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
836 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
837 timestamp = mlx4_en_get_cqe_ts(cqe);
838 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
842 skb_mark_napi_id(skb, &cq->napi);
844 if (!mlx4_en_cq_busy_polling(cq))
845 napi_gro_receive(&cq->napi, skb);
847 netif_receive_skb(skb);
850 for (nr = 0; nr < priv->num_frags; nr++)
851 mlx4_en_free_frag(priv, frags, nr);
853 ++cq->mcq.cons_index;
854 index = (cq->mcq.cons_index) & ring->size_mask;
855 cqe = &cq->buf[(index << factor) + factor];
856 if (++polled == budget)
861 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
862 mlx4_cq_set_ci(&cq->mcq);
863 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
864 ring->cons = cq->mcq.cons_index;
865 mlx4_en_refill_rx_buffers(priv, ring);
866 mlx4_en_update_rx_prod_db(ring);
871 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
873 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
874 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
877 napi_schedule(&cq->napi);
879 mlx4_en_arm_cq(priv, cq);
882 /* Rx CQ polling - called by NAPI */
883 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
885 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
886 struct net_device *dev = cq->dev;
887 struct mlx4_en_priv *priv = netdev_priv(dev);
890 if (!mlx4_en_cq_lock_napi(cq))
893 done = mlx4_en_process_rx_cq(dev, cq, budget);
895 mlx4_en_cq_unlock_napi(cq);
897 /* If we used up all the quota - we're probably not done yet... */
899 INC_PERF_COUNTER(priv->pstats.napi_quota);
903 mlx4_en_arm_cq(priv, cq);
908 static const int frag_sizes[] = {
915 void mlx4_en_calc_rx_buf(struct net_device *dev)
917 struct mlx4_en_priv *priv = netdev_priv(dev);
918 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
922 while (buf_size < eff_mtu) {
923 priv->frag_info[i].frag_size =
924 (eff_mtu > buf_size + frag_sizes[i]) ?
925 frag_sizes[i] : eff_mtu - buf_size;
926 priv->frag_info[i].frag_prefix_size = buf_size;
928 priv->frag_info[i].frag_align = NET_IP_ALIGN;
929 priv->frag_info[i].frag_stride =
930 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
932 priv->frag_info[i].frag_align = 0;
933 priv->frag_info[i].frag_stride =
934 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
936 buf_size += priv->frag_info[i].frag_size;
941 priv->rx_skb_size = eff_mtu;
942 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
944 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
945 eff_mtu, priv->num_frags);
946 for (i = 0; i < priv->num_frags; i++) {
948 " frag:%d - size:%d prefix:%d align:%d stride:%d\n",
950 priv->frag_info[i].frag_size,
951 priv->frag_info[i].frag_prefix_size,
952 priv->frag_info[i].frag_align,
953 priv->frag_info[i].frag_stride);
957 /* RSS related functions */
959 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
960 struct mlx4_en_rx_ring *ring,
961 enum mlx4_qp_state *state,
964 struct mlx4_en_dev *mdev = priv->mdev;
965 struct mlx4_qp_context *context;
968 context = kmalloc(sizeof(*context), GFP_KERNEL);
972 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
974 en_err(priv, "Failed to allocate qp #%x\n", qpn);
977 qp->event = mlx4_en_sqp_event;
979 memset(context, 0, sizeof *context);
980 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
981 qpn, ring->cqn, -1, context);
982 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
984 /* Cancel FCS removal if FW allows */
985 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
986 context->param3 |= cpu_to_be32(1 << 29);
987 ring->fcs_del = ETH_FCS_LEN;
991 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
993 mlx4_qp_remove(mdev->dev, qp);
994 mlx4_qp_free(mdev->dev, qp);
996 mlx4_en_update_rx_prod_db(ring);
1002 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1007 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn);
1009 en_err(priv, "Failed reserving drop qpn\n");
1012 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
1014 en_err(priv, "Failed allocating drop qp\n");
1015 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1022 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1026 qpn = priv->drop_qp.qpn;
1027 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1028 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1029 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1032 /* Allocate rx qp's and configure them according to rss map */
1033 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1035 struct mlx4_en_dev *mdev = priv->mdev;
1036 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1037 struct mlx4_qp_context context;
1038 struct mlx4_rss_context *rss_context;
1041 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1046 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
1047 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
1048 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
1050 en_dbg(DRV, priv, "Configuring rss steering\n");
1051 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1053 &rss_map->base_qpn);
1055 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1059 for (i = 0; i < priv->rx_ring_num; i++) {
1060 qpn = rss_map->base_qpn + i;
1061 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1070 /* Configure RSS indirection qp */
1071 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
1073 en_err(priv, "Failed to allocate RSS indirection QP\n");
1076 rss_map->indir_qp.event = mlx4_en_sqp_event;
1077 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1078 priv->rx_ring[0]->cqn, -1, &context);
1080 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1081 rss_rings = priv->rx_ring_num;
1083 rss_rings = priv->prof->rss_rings;
1085 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1086 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1088 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1089 (rss_map->base_qpn));
1090 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1091 if (priv->mdev->profile.udp_rss) {
1092 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1093 rss_context->base_qpn_udp = rss_context->default_qpn;
1096 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1097 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1098 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1101 rss_context->flags = rss_mask;
1102 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1103 for (i = 0; i < 10; i++)
1104 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
1106 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1107 &rss_map->indir_qp, &rss_map->indir_state);
1114 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1115 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1116 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1117 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1119 for (i = 0; i < good_qps; i++) {
1120 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1121 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1122 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1123 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1125 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1129 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1131 struct mlx4_en_dev *mdev = priv->mdev;
1132 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1135 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1136 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1137 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1138 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1140 for (i = 0; i < priv->rx_ring_num; i++) {
1141 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1142 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1143 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1144 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1146 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);