2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/mlx4/cq.h>
35 #include <linux/slab.h>
36 #include <linux/mlx4/qp.h>
37 #include <linux/skbuff.h>
38 #include <linux/rculist.h>
39 #include <linux/if_ether.h>
40 #include <linux/if_vlan.h>
41 #include <linux/vmalloc.h>
45 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
46 struct mlx4_en_rx_desc *rx_desc,
47 struct mlx4_en_rx_alloc *frags,
48 struct mlx4_en_rx_alloc *ring_alloc)
50 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
51 struct mlx4_en_frag_info *frag_info;
56 for (i = 0; i < priv->num_frags; i++) {
57 frag_info = &priv->frag_info[i];
58 if (ring_alloc[i].offset == frag_info->last_offset) {
59 page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
63 dma = dma_map_page(priv->ddev, page, 0,
64 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
65 if (dma_mapping_error(priv->ddev, dma)) {
69 page_alloc[i].page = page;
70 page_alloc[i].dma = dma;
71 page_alloc[i].offset = frag_info->frag_align;
73 page_alloc[i].page = ring_alloc[i].page;
74 get_page(ring_alloc[i].page);
75 page_alloc[i].dma = ring_alloc[i].dma;
76 page_alloc[i].offset = ring_alloc[i].offset +
77 frag_info->frag_stride;
81 for (i = 0; i < priv->num_frags; i++) {
82 frags[i] = ring_alloc[i];
83 dma = ring_alloc[i].dma + ring_alloc[i].offset;
84 ring_alloc[i] = page_alloc[i];
85 rx_desc->data[i].addr = cpu_to_be64(dma);
93 frag_info = &priv->frag_info[i];
94 if (ring_alloc[i].offset == frag_info->last_offset)
95 dma_unmap_page(priv->ddev, page_alloc[i].dma,
96 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
97 put_page(page_alloc[i].page);
102 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
103 struct mlx4_en_rx_alloc *frags,
106 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
108 if (frags[i].offset == frag_info->last_offset) {
109 dma_unmap_page(priv->ddev, frags[i].dma, MLX4_EN_ALLOC_SIZE,
113 put_page(frags[i].page);
116 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
117 struct mlx4_en_rx_ring *ring)
119 struct mlx4_en_rx_alloc *page_alloc;
122 for (i = 0; i < priv->num_frags; i++) {
123 page_alloc = &ring->page_alloc[i];
124 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
125 MLX4_EN_ALLOC_ORDER);
126 if (!page_alloc->page)
129 page_alloc->dma = dma_map_page(priv->ddev, page_alloc->page, 0,
130 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
131 if (dma_mapping_error(priv->ddev, page_alloc->dma)) {
132 put_page(page_alloc->page);
133 page_alloc->page = NULL;
136 page_alloc->offset = priv->frag_info[i].frag_align;
137 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
138 i, page_alloc->page);
144 page_alloc = &ring->page_alloc[i];
145 dma_unmap_page(priv->ddev, page_alloc->dma,
146 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
147 put_page(page_alloc->page);
148 page_alloc->page = NULL;
153 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
154 struct mlx4_en_rx_ring *ring)
156 struct mlx4_en_rx_alloc *page_alloc;
159 for (i = 0; i < priv->num_frags; i++) {
160 page_alloc = &ring->page_alloc[i];
161 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
162 i, page_count(page_alloc->page));
164 dma_unmap_page(priv->ddev, page_alloc->dma,
165 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
166 put_page(page_alloc->page);
167 page_alloc->page = NULL;
171 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
172 struct mlx4_en_rx_ring *ring, int index)
174 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
178 /* Set size and memtype fields */
179 for (i = 0; i < priv->num_frags; i++) {
180 rx_desc->data[i].byte_count =
181 cpu_to_be32(priv->frag_info[i].frag_size);
182 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
185 /* If the number of used fragments does not fill up the ring stride,
186 * remaining (unused) fragments must be padded with null address/size
187 * and a special memory key */
188 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
189 for (i = priv->num_frags; i < possible_frags; i++) {
190 rx_desc->data[i].byte_count = 0;
191 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
192 rx_desc->data[i].addr = 0;
196 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
197 struct mlx4_en_rx_ring *ring, int index)
199 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
200 struct mlx4_en_rx_alloc *frags = ring->rx_info +
201 (index << priv->log_rx_info);
203 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc);
206 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
208 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
211 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
212 struct mlx4_en_rx_ring *ring,
215 struct mlx4_en_rx_alloc *frags;
218 frags = ring->rx_info + (index << priv->log_rx_info);
219 for (nr = 0; nr < priv->num_frags; nr++) {
220 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
221 mlx4_en_free_frag(priv, frags, nr);
225 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
227 struct mlx4_en_rx_ring *ring;
232 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
233 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
234 ring = &priv->rx_ring[ring_ind];
236 if (mlx4_en_prepare_rx_desc(priv, ring,
237 ring->actual_size)) {
238 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
239 en_err(priv, "Failed to allocate "
240 "enough rx buffers\n");
243 new_size = rounddown_pow_of_two(ring->actual_size);
244 en_warn(priv, "Only %d buffers allocated "
245 "reducing ring size to %d",
246 ring->actual_size, new_size);
257 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
258 ring = &priv->rx_ring[ring_ind];
259 while (ring->actual_size > new_size) {
262 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
269 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
270 struct mlx4_en_rx_ring *ring)
274 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
275 ring->cons, ring->prod);
277 /* Unmap and free Rx buffers */
278 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
279 while (ring->cons != ring->prod) {
280 index = ring->cons & ring->size_mask;
281 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
282 mlx4_en_free_rx_desc(priv, ring, index);
287 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
288 struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
290 struct mlx4_en_dev *mdev = priv->mdev;
297 ring->size_mask = size - 1;
298 ring->stride = stride;
299 ring->log_stride = ffs(ring->stride) - 1;
300 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
302 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
303 sizeof(struct mlx4_en_rx_alloc));
304 ring->rx_info = vmalloc(tmp);
308 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
311 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
312 ring->buf_size, 2 * PAGE_SIZE);
316 err = mlx4_en_map_buffer(&ring->wqres.buf);
318 en_err(priv, "Failed to map RX buffer\n");
321 ring->buf = ring->wqres.buf.direct.buf;
326 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
328 vfree(ring->rx_info);
329 ring->rx_info = NULL;
333 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
335 struct mlx4_en_rx_ring *ring;
339 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
340 DS_SIZE * priv->num_frags);
342 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
343 ring = &priv->rx_ring[ring_ind];
347 ring->actual_size = 0;
348 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
350 ring->stride = stride;
351 if (ring->stride <= TXBB_SIZE)
352 ring->buf += TXBB_SIZE;
354 ring->log_stride = ffs(ring->stride) - 1;
355 ring->buf_size = ring->size * ring->stride;
357 memset(ring->buf, 0, ring->buf_size);
358 mlx4_en_update_rx_prod_db(ring);
360 /* Initialize all descriptors */
361 for (i = 0; i < ring->size; i++)
362 mlx4_en_init_rx_desc(priv, ring, i);
364 /* Initialize page allocators */
365 err = mlx4_en_init_allocator(priv, ring);
367 en_err(priv, "Failed initializing ring allocator\n");
368 if (ring->stride <= TXBB_SIZE)
369 ring->buf -= TXBB_SIZE;
374 err = mlx4_en_fill_rx_buffers(priv);
378 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
379 ring = &priv->rx_ring[ring_ind];
381 ring->size_mask = ring->actual_size - 1;
382 mlx4_en_update_rx_prod_db(ring);
388 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
389 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
391 ring_ind = priv->rx_ring_num - 1;
393 while (ring_ind >= 0) {
394 if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE)
395 priv->rx_ring[ring_ind].buf -= TXBB_SIZE;
396 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
402 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
403 struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
405 struct mlx4_en_dev *mdev = priv->mdev;
407 mlx4_en_unmap_buffer(&ring->wqres.buf);
408 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
409 vfree(ring->rx_info);
410 ring->rx_info = NULL;
411 #ifdef CONFIG_RFS_ACCEL
412 mlx4_en_cleanup_filters(priv, ring);
416 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
417 struct mlx4_en_rx_ring *ring)
419 mlx4_en_free_rx_buf(priv, ring);
420 if (ring->stride <= TXBB_SIZE)
421 ring->buf -= TXBB_SIZE;
422 mlx4_en_destroy_allocator(priv, ring);
426 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
427 struct mlx4_en_rx_desc *rx_desc,
428 struct mlx4_en_rx_alloc *frags,
432 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
433 struct mlx4_en_frag_info *frag_info;
437 /* Collect used fragments while replacing them in the HW descriptors */
438 for (nr = 0; nr < priv->num_frags; nr++) {
439 frag_info = &priv->frag_info[nr];
440 if (length <= frag_info->frag_prefix_size)
445 dma = be64_to_cpu(rx_desc->data[nr].addr);
446 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
449 /* Save page reference in skb */
450 get_page(frags[nr].page);
451 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
452 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
453 skb_frags_rx[nr].page_offset = frags[nr].offset;
454 skb->truesize += frag_info->frag_stride;
456 /* Adjust size of last fragment to match actual length */
458 skb_frag_size_set(&skb_frags_rx[nr - 1],
459 length - priv->frag_info[nr - 1].frag_prefix_size);
465 __skb_frag_unref(&skb_frags_rx[nr]);
471 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
472 struct mlx4_en_rx_desc *rx_desc,
473 struct mlx4_en_rx_alloc *frags,
481 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
483 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
486 skb_reserve(skb, NET_IP_ALIGN);
489 /* Get pointer to first fragment so we could copy the headers into the
490 * (linear part of the) skb */
491 va = page_address(frags[0].page) + frags[0].offset;
493 if (length <= SMALL_PACKET_SIZE) {
494 /* We are copying all relevant data to the skb - temporarily
495 * sync buffers for the copy */
496 dma = be64_to_cpu(rx_desc->data[0].addr);
497 dma_sync_single_for_cpu(priv->ddev, dma, length,
499 skb_copy_to_linear_data(skb, va, length);
502 /* Move relevant fragments to skb */
503 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
505 if (unlikely(!used_frags)) {
509 skb_shinfo(skb)->nr_frags = used_frags;
511 /* Copy headers into the skb linear buffer */
512 memcpy(skb->data, va, HEADER_COPY_SIZE);
513 skb->tail += HEADER_COPY_SIZE;
515 /* Skip headers in first fragment */
516 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
518 /* Adjust size of first fragment */
519 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
520 skb->data_len = length - HEADER_COPY_SIZE;
525 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
528 int offset = ETH_HLEN;
530 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
531 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
535 priv->loopback_ok = 1;
538 dev_kfree_skb_any(skb);
541 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
542 struct mlx4_en_rx_ring *ring)
544 int index = ring->prod & ring->size_mask;
546 while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
547 if (mlx4_en_prepare_rx_desc(priv, ring, index))
550 index = ring->prod & ring->size_mask;
554 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
556 struct mlx4_en_priv *priv = netdev_priv(dev);
557 struct mlx4_cqe *cqe;
558 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
559 struct mlx4_en_rx_alloc *frags;
560 struct mlx4_en_rx_desc *rx_desc;
567 int factor = priv->cqe_factor;
572 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
573 * descriptor offset can be deduced from the CQE index instead of
574 * reading 'cqe->index' */
575 index = cq->mcq.cons_index & ring->size_mask;
576 cqe = &cq->buf[(index << factor) + factor];
578 /* Process all completed CQEs */
579 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
580 cq->mcq.cons_index & cq->size)) {
582 frags = ring->rx_info + (index << priv->log_rx_info);
583 rx_desc = ring->buf + (index << ring->log_stride);
586 * make sure we read the CQE after we read the ownership bit
590 /* Drop packet on bad receive or bad checksum */
591 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
592 MLX4_CQE_OPCODE_ERROR)) {
593 en_err(priv, "CQE completed in error - vendor "
594 "syndrom:%d syndrom:%d\n",
595 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
596 ((struct mlx4_err_cqe *) cqe)->syndrome);
599 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
600 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
604 /* Check if we need to drop the packet if SRIOV is not enabled
605 * and not performing the selftest or flb disabled
607 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
610 /* Get pointer to first fragment since we haven't
611 * skb yet and cast it to ethhdr struct
613 dma = be64_to_cpu(rx_desc->data[0].addr);
614 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
616 ethh = (struct ethhdr *)(page_address(frags[0].page) +
619 if (is_multicast_ether_addr(ethh->h_dest)) {
620 struct mlx4_mac_entry *entry;
621 struct hlist_head *bucket;
622 unsigned int mac_hash;
624 /* Drop the packet, since HW loopback-ed it */
625 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
626 bucket = &priv->mac_hash[mac_hash];
628 hlist_for_each_entry_rcu(entry, bucket, hlist) {
629 if (ether_addr_equal_64bits(entry->mac,
640 * Packet is OK - process it.
642 length = be32_to_cpu(cqe->byte_cnt);
643 length -= ring->fcs_del;
644 ring->bytes += length;
647 if (likely(dev->features & NETIF_F_RXCSUM)) {
648 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
649 (cqe->checksum == cpu_to_be16(0xffff))) {
651 /* This packet is eligible for GRO if it is:
652 * - DIX Ethernet (type interpretation)
654 * - without IP options
655 * - not an IP fragment */
656 if (dev->features & NETIF_F_GRO) {
657 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
661 nr = mlx4_en_complete_rx_desc(priv,
662 rx_desc, frags, gro_skb,
667 skb_shinfo(gro_skb)->nr_frags = nr;
668 gro_skb->len = length;
669 gro_skb->data_len = length;
670 gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
672 if (cqe->vlan_my_qpn &
673 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) {
674 u16 vid = be16_to_cpu(cqe->sl_vid);
676 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
679 if (dev->features & NETIF_F_RXHASH)
680 gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
682 skb_record_rx_queue(gro_skb, cq->ring);
683 napi_gro_frags(&cq->napi);
688 /* GRO not possible, complete processing here */
689 ip_summed = CHECKSUM_UNNECESSARY;
691 ip_summed = CHECKSUM_NONE;
695 ip_summed = CHECKSUM_NONE;
699 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
701 priv->stats.rx_dropped++;
705 if (unlikely(priv->validate_loopback)) {
706 validate_loopback(priv, skb);
710 skb->ip_summed = ip_summed;
711 skb->protocol = eth_type_trans(skb, dev);
712 skb_record_rx_queue(skb, cq->ring);
714 if (dev->features & NETIF_F_RXHASH)
715 skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
717 if (be32_to_cpu(cqe->vlan_my_qpn) &
718 MLX4_CQE_VLAN_PRESENT_MASK)
719 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
721 /* Push it up the stack */
722 netif_receive_skb(skb);
725 for (nr = 0; nr < priv->num_frags; nr++)
726 mlx4_en_free_frag(priv, frags, nr);
728 ++cq->mcq.cons_index;
729 index = (cq->mcq.cons_index) & ring->size_mask;
730 cqe = &cq->buf[(index << factor) + factor];
731 if (++polled == budget)
736 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
737 mlx4_cq_set_ci(&cq->mcq);
738 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
739 ring->cons = cq->mcq.cons_index;
740 mlx4_en_refill_rx_buffers(priv, ring);
741 mlx4_en_update_rx_prod_db(ring);
746 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
748 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
749 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
752 napi_schedule(&cq->napi);
754 mlx4_en_arm_cq(priv, cq);
757 /* Rx CQ polling - called by NAPI */
758 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
760 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
761 struct net_device *dev = cq->dev;
762 struct mlx4_en_priv *priv = netdev_priv(dev);
765 done = mlx4_en_process_rx_cq(dev, cq, budget);
767 /* If we used up all the quota - we're probably not done yet... */
769 INC_PERF_COUNTER(priv->pstats.napi_quota);
773 mlx4_en_arm_cq(priv, cq);
779 /* Calculate the last offset position that accommodates a full fragment
780 * (assuming fagment size = stride-align) */
781 static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
783 u16 res = MLX4_EN_ALLOC_SIZE % stride;
784 u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
786 en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
787 "res:%d offset:%d\n", stride, align, res, offset);
792 static int frag_sizes[] = {
799 void mlx4_en_calc_rx_buf(struct net_device *dev)
801 struct mlx4_en_priv *priv = netdev_priv(dev);
802 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
806 while (buf_size < eff_mtu) {
807 priv->frag_info[i].frag_size =
808 (eff_mtu > buf_size + frag_sizes[i]) ?
809 frag_sizes[i] : eff_mtu - buf_size;
810 priv->frag_info[i].frag_prefix_size = buf_size;
812 priv->frag_info[i].frag_align = NET_IP_ALIGN;
813 priv->frag_info[i].frag_stride =
814 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
816 priv->frag_info[i].frag_align = 0;
817 priv->frag_info[i].frag_stride =
818 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
820 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
821 priv, priv->frag_info[i].frag_stride,
822 priv->frag_info[i].frag_align);
823 buf_size += priv->frag_info[i].frag_size;
828 priv->rx_skb_size = eff_mtu;
829 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
831 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
832 "num_frags:%d):\n", eff_mtu, priv->num_frags);
833 for (i = 0; i < priv->num_frags; i++) {
834 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
835 "stride:%d last_offset:%d\n", i,
836 priv->frag_info[i].frag_size,
837 priv->frag_info[i].frag_prefix_size,
838 priv->frag_info[i].frag_align,
839 priv->frag_info[i].frag_stride,
840 priv->frag_info[i].last_offset);
844 /* RSS related functions */
846 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
847 struct mlx4_en_rx_ring *ring,
848 enum mlx4_qp_state *state,
851 struct mlx4_en_dev *mdev = priv->mdev;
852 struct mlx4_qp_context *context;
855 context = kmalloc(sizeof(*context), GFP_KERNEL);
859 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
861 en_err(priv, "Failed to allocate qp #%x\n", qpn);
864 qp->event = mlx4_en_sqp_event;
866 memset(context, 0, sizeof *context);
867 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
868 qpn, ring->cqn, -1, context);
869 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
871 /* Cancel FCS removal if FW allows */
872 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
873 context->param3 |= cpu_to_be32(1 << 29);
874 ring->fcs_del = ETH_FCS_LEN;
878 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
880 mlx4_qp_remove(mdev->dev, qp);
881 mlx4_qp_free(mdev->dev, qp);
883 mlx4_en_update_rx_prod_db(ring);
889 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
894 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn);
896 en_err(priv, "Failed reserving drop qpn\n");
899 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
901 en_err(priv, "Failed allocating drop qp\n");
902 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
909 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
913 qpn = priv->drop_qp.qpn;
914 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
915 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
916 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
919 /* Allocate rx qp's and configure them according to rss map */
920 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
922 struct mlx4_en_dev *mdev = priv->mdev;
923 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
924 struct mlx4_qp_context context;
925 struct mlx4_rss_context *rss_context;
928 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
933 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
934 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
935 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
937 en_dbg(DRV, priv, "Configuring rss steering\n");
938 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
942 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
946 for (i = 0; i < priv->rx_ring_num; i++) {
947 qpn = rss_map->base_qpn + i;
948 err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
957 /* Configure RSS indirection qp */
958 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
960 en_err(priv, "Failed to allocate RSS indirection QP\n");
963 rss_map->indir_qp.event = mlx4_en_sqp_event;
964 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
965 priv->rx_ring[0].cqn, -1, &context);
967 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
968 rss_rings = priv->rx_ring_num;
970 rss_rings = priv->prof->rss_rings;
972 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
973 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
975 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
976 (rss_map->base_qpn));
977 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
978 if (priv->mdev->profile.udp_rss) {
979 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
980 rss_context->base_qpn_udp = rss_context->default_qpn;
982 rss_context->flags = rss_mask;
983 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
984 for (i = 0; i < 10; i++)
985 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
987 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
988 &rss_map->indir_qp, &rss_map->indir_state);
995 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
996 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
997 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
998 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1000 for (i = 0; i < good_qps; i++) {
1001 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1002 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1003 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1004 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1006 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1010 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1012 struct mlx4_en_dev *mdev = priv->mdev;
1013 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1016 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1017 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1018 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1019 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1021 for (i = 0; i < priv->rx_ring_num; i++) {
1022 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1023 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1024 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1025 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1027 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);