2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/vmalloc.h>
41 #include <linux/tcp.h>
42 #include <linux/moduleparam.h>
47 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
51 static int inline_thold __read_mostly = MAX_INLINE;
53 module_param_named(inline_thold, inline_thold, int, 0444);
54 MODULE_PARM_DESC(inline_thold, "threshold for using inline data");
56 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
57 struct mlx4_en_tx_ring *ring, int qpn, u32 size,
60 struct mlx4_en_dev *mdev = priv->mdev;
65 ring->size_mask = size - 1;
66 ring->stride = stride;
68 inline_thold = min(inline_thold, MAX_INLINE);
70 tmp = size * sizeof(struct mlx4_en_tx_info);
71 ring->tx_info = vmalloc(tmp);
75 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
78 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
79 if (!ring->bounce_buf) {
83 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
85 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
88 en_err(priv, "Failed allocating hwq resources\n");
92 err = mlx4_en_map_buffer(&ring->wqres.buf);
94 en_err(priv, "Failed to map TX buffer\n");
98 ring->buf = ring->wqres.buf.direct.buf;
100 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
101 "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
102 ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
105 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
107 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
110 ring->qp.event = mlx4_en_sqp_event;
112 err = mlx4_bf_alloc(mdev->dev, &ring->bf);
114 en_dbg(DRV, priv, "working without blueflame (%d)", err);
115 ring->bf.uar = &mdev->priv_uar;
116 ring->bf.uar->map = mdev->uar_map;
117 ring->bf_enabled = false;
119 ring->bf_enabled = true;
124 mlx4_en_unmap_buffer(&ring->wqres.buf);
126 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
128 kfree(ring->bounce_buf);
129 ring->bounce_buf = NULL;
131 vfree(ring->tx_info);
132 ring->tx_info = NULL;
136 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
137 struct mlx4_en_tx_ring *ring)
139 struct mlx4_en_dev *mdev = priv->mdev;
140 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
142 if (ring->bf_enabled)
143 mlx4_bf_free(mdev->dev, &ring->bf);
144 mlx4_qp_remove(mdev->dev, &ring->qp);
145 mlx4_qp_free(mdev->dev, &ring->qp);
146 mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
147 mlx4_en_unmap_buffer(&ring->wqres.buf);
148 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
149 kfree(ring->bounce_buf);
150 ring->bounce_buf = NULL;
151 vfree(ring->tx_info);
152 ring->tx_info = NULL;
155 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
156 struct mlx4_en_tx_ring *ring,
157 int cq, int user_prio)
159 struct mlx4_en_dev *mdev = priv->mdev;
164 ring->cons = 0xffffffff;
165 ring->last_nr_txbb = 1;
167 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
168 memset(ring->buf, 0, ring->buf_size);
170 ring->qp_state = MLX4_QP_STATE_RST;
171 ring->doorbell_qpn = ring->qp.qpn << 8;
173 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
174 ring->cqn, user_prio, &ring->context);
175 if (ring->bf_enabled)
176 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
178 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
179 &ring->qp, &ring->qp_state);
184 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
185 struct mlx4_en_tx_ring *ring)
187 struct mlx4_en_dev *mdev = priv->mdev;
189 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
190 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
194 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
195 struct mlx4_en_tx_ring *ring,
198 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
199 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
200 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
201 struct sk_buff *skb = tx_info->skb;
202 struct skb_frag_struct *frag;
203 void *end = ring->buf + ring->buf_size;
204 int frags = skb_shinfo(skb)->nr_frags;
206 __be32 *ptr = (__be32 *)tx_desc;
207 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
209 /* Optimize the common case when there are no wraparounds */
210 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
212 if (tx_info->linear) {
213 dma_unmap_single(priv->ddev,
214 (dma_addr_t) be64_to_cpu(data->addr),
215 be32_to_cpu(data->byte_count),
220 for (i = 0; i < frags; i++) {
221 frag = &skb_shinfo(skb)->frags[i];
222 dma_unmap_page(priv->ddev,
223 (dma_addr_t) be64_to_cpu(data[i].addr),
224 skb_frag_size(frag), PCI_DMA_TODEVICE);
227 /* Stamp the freed descriptor */
228 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
235 if ((void *) data >= end) {
236 data = ring->buf + ((void *)data - end);
239 if (tx_info->linear) {
240 dma_unmap_single(priv->ddev,
241 (dma_addr_t) be64_to_cpu(data->addr),
242 be32_to_cpu(data->byte_count),
247 for (i = 0; i < frags; i++) {
248 /* Check for wraparound before unmapping */
249 if ((void *) data >= end)
251 frag = &skb_shinfo(skb)->frags[i];
252 dma_unmap_page(priv->ddev,
253 (dma_addr_t) be64_to_cpu(data->addr),
254 skb_frag_size(frag), PCI_DMA_TODEVICE);
258 /* Stamp the freed descriptor */
259 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
262 if ((void *) ptr >= end) {
264 stamp ^= cpu_to_be32(0x80000000);
269 dev_kfree_skb_any(skb);
270 return tx_info->nr_txbb;
274 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
276 struct mlx4_en_priv *priv = netdev_priv(dev);
279 /* Skip last polled descriptor */
280 ring->cons += ring->last_nr_txbb;
281 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
282 ring->cons, ring->prod);
284 if ((u32) (ring->prod - ring->cons) > ring->size) {
285 if (netif_msg_tx_err(priv))
286 en_warn(priv, "Tx consumer passed producer!\n");
290 while (ring->cons != ring->prod) {
291 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
292 ring->cons & ring->size_mask,
293 !!(ring->cons & ring->size));
294 ring->cons += ring->last_nr_txbb;
299 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
304 static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq)
306 struct mlx4_en_priv *priv = netdev_priv(dev);
307 struct mlx4_cq *mcq = &cq->mcq;
308 struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
309 struct mlx4_cqe *cqe;
311 u16 new_index, ring_index;
312 u32 txbbs_skipped = 0;
313 u32 cons_index = mcq->cons_index;
315 u32 size_mask = ring->size_mask;
316 struct mlx4_cqe *buf = cq->buf;
323 index = cons_index & size_mask;
325 ring_index = ring->cons & size_mask;
327 /* Process all completed CQEs */
328 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
329 cons_index & size)) {
331 * make sure we read the CQE after we read the
336 /* Skip over last polled CQE */
337 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
340 txbbs_skipped += ring->last_nr_txbb;
341 ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
342 /* free next descriptor */
343 ring->last_nr_txbb = mlx4_en_free_tx_desc(
344 priv, ring, ring_index,
345 !!((ring->cons + txbbs_skipped) &
348 bytes += ring->tx_info[ring_index].nr_bytes;
349 } while (ring_index != new_index);
352 index = cons_index & size_mask;
358 * To prevent CQ overflow we first update CQ consumer and only then
361 mcq->cons_index = cons_index;
364 ring->cons += txbbs_skipped;
365 netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
368 * Wakeup Tx queue if this stopped, and at least 1 packet
371 if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) {
372 netif_tx_wake_queue(ring->tx_queue);
373 priv->port_stats.wake_queue++;
377 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
379 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
380 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
382 mlx4_en_process_tx_cq(cq->dev, cq);
383 mlx4_en_arm_cq(priv, cq);
387 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
388 struct mlx4_en_tx_ring *ring,
390 unsigned int desc_size)
392 u32 copy = (ring->size - index) * TXBB_SIZE;
395 for (i = desc_size - copy - 4; i >= 0; i -= 4) {
396 if ((i & (TXBB_SIZE - 1)) == 0)
399 *((u32 *) (ring->buf + i)) =
400 *((u32 *) (ring->bounce_buf + copy + i));
403 for (i = copy - 4; i >= 4 ; i -= 4) {
404 if ((i & (TXBB_SIZE - 1)) == 0)
407 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
408 *((u32 *) (ring->bounce_buf + i));
411 /* Return real descriptor location */
412 return ring->buf + index * TXBB_SIZE;
415 static int is_inline(struct sk_buff *skb, void **pfrag)
419 if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) {
420 if (skb_shinfo(skb)->nr_frags == 1) {
421 ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]);
429 } else if (unlikely(skb_shinfo(skb)->nr_frags))
438 static int inline_size(struct sk_buff *skb)
440 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
441 <= MLX4_INLINE_ALIGN)
442 return ALIGN(skb->len + CTRL_SIZE +
443 sizeof(struct mlx4_wqe_inline_seg), 16);
445 return ALIGN(skb->len + CTRL_SIZE + 2 *
446 sizeof(struct mlx4_wqe_inline_seg), 16);
449 static int get_real_size(struct sk_buff *skb, struct net_device *dev,
450 int *lso_header_size)
452 struct mlx4_en_priv *priv = netdev_priv(dev);
455 if (skb_is_gso(skb)) {
456 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
457 real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE +
458 ALIGN(*lso_header_size + 4, DS_SIZE);
459 if (unlikely(*lso_header_size != skb_headlen(skb))) {
460 /* We add a segment for the skb linear buffer only if
461 * it contains data */
462 if (*lso_header_size < skb_headlen(skb))
463 real_size += DS_SIZE;
465 if (netif_msg_tx_err(priv))
466 en_warn(priv, "Non-linear headers\n");
471 *lso_header_size = 0;
472 if (!is_inline(skb, NULL))
473 real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE;
475 real_size = inline_size(skb);
481 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb,
482 int real_size, u16 *vlan_tag, int tx_ind, void *fragptr)
484 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
485 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
487 if (skb->len <= spc) {
488 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
489 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
490 if (skb_shinfo(skb)->nr_frags)
491 memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr,
492 skb_frag_size(&skb_shinfo(skb)->frags[0]));
495 inl->byte_count = cpu_to_be32(1 << 31 | spc);
496 if (skb_headlen(skb) <= spc) {
497 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
498 if (skb_headlen(skb) < spc) {
499 memcpy(((void *)(inl + 1)) + skb_headlen(skb),
500 fragptr, spc - skb_headlen(skb));
501 fragptr += spc - skb_headlen(skb);
503 inl = (void *) (inl + 1) + spc;
504 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
506 skb_copy_from_linear_data(skb, inl + 1, spc);
507 inl = (void *) (inl + 1) + spc;
508 skb_copy_from_linear_data_offset(skb, spc, inl + 1,
509 skb_headlen(skb) - spc);
510 if (skb_shinfo(skb)->nr_frags)
511 memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc,
512 fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0]));
516 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
518 tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag);
519 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
520 (!!vlan_tx_tag_present(skb));
521 tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
524 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb)
526 struct mlx4_en_priv *priv = netdev_priv(dev);
527 u16 rings_p_up = priv->mdev->profile.num_tx_rings_p_up;
531 return skb_tx_hash(dev, skb);
533 if (vlan_tx_tag_present(skb))
534 up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT;
536 return __skb_tx_hash(dev, skb, rings_p_up) + up * rings_p_up;
539 static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt)
541 __iowrite64_copy(dst, src, bytecnt / 8);
544 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
546 struct mlx4_en_priv *priv = netdev_priv(dev);
547 struct mlx4_en_dev *mdev = priv->mdev;
548 struct mlx4_en_tx_ring *ring;
549 struct mlx4_en_tx_desc *tx_desc;
550 struct mlx4_wqe_data_seg *data;
551 struct skb_frag_struct *frag;
552 struct mlx4_en_tx_info *tx_info;
570 real_size = get_real_size(skb, dev, &lso_header_size);
571 if (unlikely(!real_size))
574 /* Align descriptor to TXBB size */
575 desc_size = ALIGN(real_size, TXBB_SIZE);
576 nr_txbb = desc_size / TXBB_SIZE;
577 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
578 if (netif_msg_tx_err(priv))
579 en_warn(priv, "Oversized header or SG list\n");
583 tx_ind = skb->queue_mapping;
584 ring = &priv->tx_ring[tx_ind];
585 if (vlan_tx_tag_present(skb))
586 vlan_tag = vlan_tx_tag_get(skb);
588 /* Check available TXBBs And 2K spare for prefetch */
589 if (unlikely(((int)(ring->prod - ring->cons)) >
590 ring->size - HEADROOM - MAX_DESC_TXBBS)) {
591 /* every full Tx ring stops queue */
592 netif_tx_stop_queue(ring->tx_queue);
593 priv->port_stats.queue_stopped++;
595 return NETDEV_TX_BUSY;
598 /* Track current inflight packets for performance analysis */
599 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
600 (u32) (ring->prod - ring->cons - 1));
602 /* Packet is good - grab an index and transmit it */
603 index = ring->prod & ring->size_mask;
604 bf_index = ring->prod;
606 /* See if we have enough space for whole descriptor TXBB for setting
607 * SW ownership on next descriptor; if not, use a bounce buffer. */
608 if (likely(index + nr_txbb <= ring->size))
609 tx_desc = ring->buf + index * TXBB_SIZE;
611 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
615 /* Save skb in tx_info ring */
616 tx_info = &ring->tx_info[index];
618 tx_info->nr_txbb = nr_txbb;
620 /* Prepare ctrl segement apart opcode+ownership, which depends on
621 * whether LSO is used */
622 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
623 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
624 !!vlan_tx_tag_present(skb);
625 tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
626 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
627 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
628 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
629 MLX4_WQE_CTRL_TCP_UDP_CSUM);
633 /* Copy dst mac address to wqe */
634 ethh = (struct ethhdr *)skb->data;
635 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
636 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
637 /* Handle LSO (TSO) packets */
638 if (lso_header_size) {
639 /* Mark opcode as LSO */
640 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
641 ((ring->prod & ring->size) ?
642 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
644 /* Fill in the LSO prefix */
645 tx_desc->lso.mss_hdr_size = cpu_to_be32(
646 skb_shinfo(skb)->gso_size << 16 | lso_header_size);
649 * note that we already verified that it is linear */
650 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
651 data = ((void *) &tx_desc->lso +
652 ALIGN(lso_header_size + 4, DS_SIZE));
654 priv->port_stats.tso_packets++;
655 i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) +
656 !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size);
657 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
660 /* Normal (Non LSO) packet */
661 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
662 ((ring->prod & ring->size) ?
663 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
664 data = &tx_desc->data;
665 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
669 ring->bytes += tx_info->nr_bytes;
670 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
671 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
674 /* valid only for none inline segments */
675 tx_info->data_offset = (void *) data - (void *) tx_desc;
677 tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0;
678 data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1;
680 if (!is_inline(skb, &fragptr)) {
682 for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) {
683 frag = &skb_shinfo(skb)->frags[i];
684 dma = skb_frag_dma_map(priv->ddev, frag,
685 0, skb_frag_size(frag),
687 data->addr = cpu_to_be64(dma);
688 data->lkey = cpu_to_be32(mdev->mr.key);
690 data->byte_count = cpu_to_be32(skb_frag_size(frag));
694 /* Map linear part */
695 if (tx_info->linear) {
696 dma = dma_map_single(priv->ddev, skb->data + lso_header_size,
697 skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE);
698 data->addr = cpu_to_be64(dma);
699 data->lkey = cpu_to_be32(mdev->mr.key);
701 data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size);
705 build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr);
709 ring->prod += nr_txbb;
711 /* If we used a bounce buffer then copy descriptor back into place */
713 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
715 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tag) {
716 *(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
717 op_own |= htonl((bf_index & 0xffff) << 8);
718 /* Ensure new descirptor hits memory
719 * before setting ownership of this descriptor to HW */
721 tx_desc->ctrl.owner_opcode = op_own;
725 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl,
730 ring->bf.offset ^= ring->bf.buf_size;
732 /* Ensure new descirptor hits memory
733 * before setting ownership of this descriptor to HW */
735 tx_desc->ctrl.owner_opcode = op_own;
737 iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL);
743 dev_kfree_skb_any(skb);
744 priv->stats.tx_dropped++;