2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/interrupt.h>
35 #include <linux/slab.h>
36 #include <linux/export.h>
38 #include <linux/dma-mapping.h>
40 #include <linux/mlx4/cmd.h>
41 #include <linux/cpu_rmap.h>
47 MLX4_IRQNAME_SIZE = 32
51 MLX4_NUM_ASYNC_EQE = 0x100,
52 MLX4_NUM_SPARE_EQE = 0x80,
53 MLX4_EQ_ENTRY_SIZE = 0x20
56 #define MLX4_EQ_STATUS_OK ( 0 << 28)
57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
58 #define MLX4_EQ_OWNER_SW ( 0 << 24)
59 #define MLX4_EQ_OWNER_HW ( 1 << 24)
60 #define MLX4_EQ_FLAG_EC ( 1 << 18)
61 #define MLX4_EQ_FLAG_OI ( 1 << 17)
62 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
63 #define MLX4_EQ_STATE_FIRED (10 << 8)
64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
80 (1ull << MLX4_EVENT_TYPE_CMD) | \
81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
95 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
100 /* We still want ordering, just not swabbing, so add a barrier */
104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor)
106 /* (entry & (eq->nent - 1)) gives us a cyclic array */
107 unsigned long offset = (entry & (eq->nent - 1)) * (MLX4_EQ_ENTRY_SIZE << eqe_factor);
108 /* CX3 is capable of extending the EQE from 32 to 64 bytes.
109 * When this feature is enabled, the first (in the lower addresses)
110 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
111 * contain the legacy EQE information.
113 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
116 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor)
118 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor);
119 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
122 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
124 struct mlx4_eqe *eqe =
125 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
126 return (!!(eqe->owner & 0x80) ^
127 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
131 void mlx4_gen_slave_eqe(struct work_struct *work)
133 struct mlx4_mfunc_master_ctx *master =
134 container_of(work, struct mlx4_mfunc_master_ctx,
136 struct mlx4_mfunc *mfunc =
137 container_of(master, struct mlx4_mfunc, master);
138 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
139 struct mlx4_dev *dev = &priv->dev;
140 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
141 struct mlx4_eqe *eqe;
145 for (eqe = next_slave_event_eqe(slave_eq); eqe;
146 eqe = next_slave_event_eqe(slave_eq)) {
147 slave = eqe->slave_id;
149 /* All active slaves need to receive the event */
150 if (slave == ALL_SLAVES) {
151 for (i = 0; i < dev->num_slaves; i++) {
152 if (i != dev->caps.function &&
153 master->slave_state[i].active)
154 if (mlx4_GEN_EQE(dev, i, eqe))
155 mlx4_warn(dev, "Failed to "
157 "for slave %d\n", i);
160 if (mlx4_GEN_EQE(dev, slave, eqe))
161 mlx4_warn(dev, "Failed to generate event "
162 "for slave %d\n", slave);
169 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
171 struct mlx4_priv *priv = mlx4_priv(dev);
172 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
173 struct mlx4_eqe *s_eqe;
176 spin_lock_irqsave(&slave_eq->event_lock, flags);
177 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
178 if ((!!(s_eqe->owner & 0x80)) ^
179 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
180 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. "
181 "No free EQE on slave events queue\n", slave);
182 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
186 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1);
187 s_eqe->slave_id = slave;
188 /* ensure all information is written before setting the ownersip bit */
190 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
193 queue_work(priv->mfunc.master.comm_wq,
194 &priv->mfunc.master.slave_event_work);
195 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
198 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
199 struct mlx4_eqe *eqe)
201 struct mlx4_priv *priv = mlx4_priv(dev);
202 struct mlx4_slave_state *s_slave =
203 &priv->mfunc.master.slave_state[slave];
205 if (!s_slave->active) {
206 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/
210 slave_event(dev, slave, eqe);
213 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
217 struct mlx4_priv *priv = mlx4_priv(dev);
218 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
220 if (!s_slave->active)
223 memset(&eqe, 0, sizeof eqe);
225 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
226 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
227 eqe.event.port_mgmt_change.port = port;
229 return mlx4_GEN_EQE(dev, slave, &eqe);
231 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
233 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
237 /*don't send if we don't have the that slave */
238 if (dev->num_vfs < slave)
240 memset(&eqe, 0, sizeof eqe);
242 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
243 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
244 eqe.event.port_mgmt_change.port = port;
246 return mlx4_GEN_EQE(dev, slave, &eqe);
248 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
250 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
251 u8 port_subtype_change)
255 /*don't send if we don't have the that slave */
256 if (dev->num_vfs < slave)
258 memset(&eqe, 0, sizeof eqe);
260 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
261 eqe.subtype = port_subtype_change;
262 eqe.event.port_change.port = cpu_to_be32(port << 28);
264 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
265 port_subtype_change, slave, port);
266 return mlx4_GEN_EQE(dev, slave, &eqe);
268 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
270 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
272 struct mlx4_priv *priv = mlx4_priv(dev);
273 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
274 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
276 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
277 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
278 pr_err("%s: Error: asking for slave:%d, port:%d\n",
279 __func__, slave, port);
280 return SLAVE_PORT_DOWN;
282 return s_state[slave].port_state[port];
284 EXPORT_SYMBOL(mlx4_get_slave_port_state);
286 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
287 enum slave_port_state state)
289 struct mlx4_priv *priv = mlx4_priv(dev);
290 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
291 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
293 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
294 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
295 pr_err("%s: Error: asking for slave:%d, port:%d\n",
296 __func__, slave, port);
299 s_state[slave].port_state[port] = state;
304 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
307 enum slave_port_gen_event gen_event;
308 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev,
311 for (i = 0; i < dev->num_vfs + 1; i++)
312 if (test_bit(i, slaves_pport.slaves))
313 set_and_calc_slave_port_state(dev, i, port,
316 /**************************************************************************
317 The function get as input the new event to that port,
318 and according to the prev state change the slave's port state.
320 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
321 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
322 MLX4_PORT_STATE_IB_EVENT_GID_VALID
323 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
324 ***************************************************************************/
325 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
327 enum slave_port_gen_event *gen_event)
329 struct mlx4_priv *priv = mlx4_priv(dev);
330 struct mlx4_slave_state *ctx = NULL;
333 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
334 enum slave_port_state cur_state =
335 mlx4_get_slave_port_state(dev, slave, port);
337 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
339 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
340 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
341 pr_err("%s: Error: asking for slave:%d, port:%d\n",
342 __func__, slave, port);
346 ctx = &priv->mfunc.master.slave_state[slave];
347 spin_lock_irqsave(&ctx->lock, flags);
350 case SLAVE_PORT_DOWN:
351 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
352 mlx4_set_slave_port_state(dev, slave, port,
355 case SLAVE_PENDING_UP:
356 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
357 mlx4_set_slave_port_state(dev, slave, port,
359 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
360 mlx4_set_slave_port_state(dev, slave, port,
362 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
366 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
367 mlx4_set_slave_port_state(dev, slave, port,
369 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
370 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
372 mlx4_set_slave_port_state(dev, slave, port,
374 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
378 pr_err("%s: BUG!!! UNKNOWN state: "
379 "slave:%d, port:%d\n", __func__, slave, port);
382 ret = mlx4_get_slave_port_state(dev, slave, port);
385 spin_unlock_irqrestore(&ctx->lock, flags);
389 EXPORT_SYMBOL(set_and_calc_slave_port_state);
391 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
395 memset(&eqe, 0, sizeof eqe);
397 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
398 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
399 eqe.event.port_mgmt_change.port = port;
400 eqe.event.port_mgmt_change.params.port_info.changed_attr =
401 cpu_to_be32((u32) attr);
403 slave_event(dev, ALL_SLAVES, &eqe);
406 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
408 void mlx4_master_handle_slave_flr(struct work_struct *work)
410 struct mlx4_mfunc_master_ctx *master =
411 container_of(work, struct mlx4_mfunc_master_ctx,
412 slave_flr_event_work);
413 struct mlx4_mfunc *mfunc =
414 container_of(master, struct mlx4_mfunc, master);
415 struct mlx4_priv *priv =
416 container_of(mfunc, struct mlx4_priv, mfunc);
417 struct mlx4_dev *dev = &priv->dev;
418 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
423 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
425 for (i = 0 ; i < dev->num_slaves; i++) {
427 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
428 mlx4_dbg(dev, "mlx4_handle_slave_flr: "
429 "clean slave: %d\n", i);
431 mlx4_delete_all_resources_for_slave(dev, i);
432 /*return the slave to running mode*/
433 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
434 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
435 slave_state[i].is_slave_going_down = 0;
436 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
438 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
439 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
441 mlx4_warn(dev, "Failed to notify FW on "
442 "FLR done (slave:%d)\n", i);
447 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
449 struct mlx4_priv *priv = mlx4_priv(dev);
450 struct mlx4_eqe *eqe;
458 u8 update_slave_state;
460 enum slave_port_gen_event gen_event;
462 struct mlx4_vport_state *s_info;
464 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor))) {
466 * Make sure we read EQ entry contents after we've
467 * checked the ownership bit.
472 case MLX4_EVENT_TYPE_COMP:
473 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
474 mlx4_cq_completion(dev, cqn);
477 case MLX4_EVENT_TYPE_PATH_MIG:
478 case MLX4_EVENT_TYPE_COMM_EST:
479 case MLX4_EVENT_TYPE_SQ_DRAINED:
480 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
481 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
482 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
483 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
484 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
485 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
486 if (mlx4_is_master(dev)) {
487 /* forward only to slave owning the QP */
488 ret = mlx4_get_slave_from_resource_id(dev,
490 be32_to_cpu(eqe->event.qp.qpn)
492 if (ret && ret != -ENOENT) {
493 mlx4_dbg(dev, "QP event %02x(%02x) on "
494 "EQ %d at index %u: could "
495 "not get slave id (%d)\n",
496 eqe->type, eqe->subtype,
497 eq->eqn, eq->cons_index, ret);
501 if (!ret && slave != dev->caps.function) {
502 mlx4_slave_event(dev, slave, eqe);
507 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
508 0xffffff, eqe->type);
511 case MLX4_EVENT_TYPE_SRQ_LIMIT:
512 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
514 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
515 if (mlx4_is_master(dev)) {
516 /* forward only to slave owning the SRQ */
517 ret = mlx4_get_slave_from_resource_id(dev,
519 be32_to_cpu(eqe->event.srq.srqn)
522 if (ret && ret != -ENOENT) {
523 mlx4_warn(dev, "SRQ event %02x(%02x) "
524 "on EQ %d at index %u: could"
525 " not get slave id (%d)\n",
526 eqe->type, eqe->subtype,
527 eq->eqn, eq->cons_index, ret);
530 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x,"
531 " event: %02x(%02x)\n", __func__,
533 be32_to_cpu(eqe->event.srq.srqn),
534 eqe->type, eqe->subtype);
536 if (!ret && slave != dev->caps.function) {
537 mlx4_warn(dev, "%s: sending event "
538 "%02x(%02x) to slave:%d\n",
540 eqe->subtype, slave);
541 mlx4_slave_event(dev, slave, eqe);
545 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
546 0xffffff, eqe->type);
549 case MLX4_EVENT_TYPE_CMD:
551 be16_to_cpu(eqe->event.cmd.token),
552 eqe->event.cmd.status,
553 be64_to_cpu(eqe->event.cmd.out_param));
556 case MLX4_EVENT_TYPE_PORT_CHANGE: {
557 struct mlx4_slaves_pport slaves_port;
558 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
559 slaves_port = mlx4_phys_to_slaves_pport(dev, port);
560 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
561 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
563 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
564 if (!mlx4_is_master(dev))
566 for (i = 0; i < dev->num_vfs + 1; i++) {
567 if (!test_bit(i, slaves_port.slaves))
569 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
570 if (i == mlx4_master_func_num(dev))
572 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN"
573 " to slave: %d, port:%d\n",
575 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
576 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
577 eqe->event.port_change.port =
579 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
580 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
581 mlx4_slave_event(dev, i, eqe);
583 } else { /* IB port */
584 set_and_calc_slave_port_state(dev, i, port,
585 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
587 /*we can be in pending state, then do not send port_down event*/
588 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
589 if (i == mlx4_master_func_num(dev))
591 mlx4_slave_event(dev, i, eqe);
596 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
598 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
600 if (!mlx4_is_master(dev))
602 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
603 for (i = 0; i < dev->num_vfs + 1; i++) {
604 if (!test_bit(i, slaves_port.slaves))
606 if (i == mlx4_master_func_num(dev))
608 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
609 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
610 eqe->event.port_change.port =
612 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
613 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
614 mlx4_slave_event(dev, i, eqe);
618 /* port-up event will be sent to a slave when the
619 * slave's alias-guid is set. This is done in alias_GUID.c
621 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
626 case MLX4_EVENT_TYPE_CQ_ERROR:
627 mlx4_warn(dev, "CQ %s on CQN %06x\n",
628 eqe->event.cq_err.syndrome == 1 ?
629 "overrun" : "access violation",
630 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
631 if (mlx4_is_master(dev)) {
632 ret = mlx4_get_slave_from_resource_id(dev,
634 be32_to_cpu(eqe->event.cq_err.cqn)
636 if (ret && ret != -ENOENT) {
637 mlx4_dbg(dev, "CQ event %02x(%02x) on "
638 "EQ %d at index %u: could "
639 "not get slave id (%d)\n",
640 eqe->type, eqe->subtype,
641 eq->eqn, eq->cons_index, ret);
645 if (!ret && slave != dev->caps.function) {
646 mlx4_slave_event(dev, slave, eqe);
651 be32_to_cpu(eqe->event.cq_err.cqn)
656 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
657 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
660 case MLX4_EVENT_TYPE_OP_REQUIRED:
661 atomic_inc(&priv->opreq_count);
662 /* FW commands can't be executed from interrupt context
663 * working in deferred task
665 queue_work(mlx4_wq, &priv->opreq_task);
668 case MLX4_EVENT_TYPE_COMM_CHANNEL:
669 if (!mlx4_is_master(dev)) {
670 mlx4_warn(dev, "Received comm channel event "
671 "for non master device\n");
674 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
675 eqe->event.comm_channel_arm.bit_vec,
676 sizeof eqe->event.comm_channel_arm.bit_vec);
677 queue_work(priv->mfunc.master.comm_wq,
678 &priv->mfunc.master.comm_work);
681 case MLX4_EVENT_TYPE_FLR_EVENT:
682 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
683 if (!mlx4_is_master(dev)) {
684 mlx4_warn(dev, "Non-master function received"
689 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
691 if (flr_slave >= dev->num_slaves) {
693 "Got FLR for unknown function: %d\n",
695 update_slave_state = 0;
697 update_slave_state = 1;
699 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
700 if (update_slave_state) {
701 priv->mfunc.master.slave_state[flr_slave].active = false;
702 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
703 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
705 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
706 queue_work(priv->mfunc.master.comm_wq,
707 &priv->mfunc.master.slave_flr_event_work);
710 case MLX4_EVENT_TYPE_FATAL_WARNING:
711 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
712 if (mlx4_is_master(dev))
713 for (i = 0; i < dev->num_slaves; i++) {
714 mlx4_dbg(dev, "%s: Sending "
715 "MLX4_FATAL_WARNING_SUBTYPE_WARMING"
716 " to slave: %d\n", __func__, i);
717 if (i == dev->caps.function)
719 mlx4_slave_event(dev, i, eqe);
721 mlx4_err(dev, "Temperature Threshold was reached! "
722 "Threshold: %d celsius degrees; "
723 "Current Temperature: %d\n",
724 be16_to_cpu(eqe->event.warming.warning_threshold),
725 be16_to_cpu(eqe->event.warming.current_temperature));
727 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), "
728 "subtype %02x on EQ %d at index %u. owner=%x, "
729 "nent=0x%x, slave=%x, ownership=%s\n",
730 eqe->type, eqe->subtype, eq->eqn,
731 eq->cons_index, eqe->owner, eq->nent,
733 !!(eqe->owner & 0x80) ^
734 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
738 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
739 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
740 (unsigned long) eqe);
743 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
744 case MLX4_EVENT_TYPE_ECC_DETECT:
746 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at "
747 "index %u. owner=%x, nent=0x%x, slave=%x, "
749 eqe->type, eqe->subtype, eq->eqn,
750 eq->cons_index, eqe->owner, eq->nent,
752 !!(eqe->owner & 0x80) ^
753 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
762 * The HCA will think the queue has overflowed if we
763 * don't tell it we've been processing events. We
764 * create our EQs with MLX4_NUM_SPARE_EQE extra
765 * entries, so we must update our consumer index at
768 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
779 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
781 struct mlx4_dev *dev = dev_ptr;
782 struct mlx4_priv *priv = mlx4_priv(dev);
786 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
788 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
789 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
791 return IRQ_RETVAL(work);
794 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
796 struct mlx4_eq *eq = eq_ptr;
797 struct mlx4_dev *dev = eq->dev;
799 mlx4_eq_int(dev, eq);
801 /* MSI-X vectors always belong to us */
805 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
806 struct mlx4_vhcr *vhcr,
807 struct mlx4_cmd_mailbox *inbox,
808 struct mlx4_cmd_mailbox *outbox,
809 struct mlx4_cmd_info *cmd)
811 struct mlx4_priv *priv = mlx4_priv(dev);
812 struct mlx4_slave_event_eq_info *event_eq =
813 priv->mfunc.master.slave_state[slave].event_eq;
814 u32 in_modifier = vhcr->in_modifier;
815 u32 eqn = in_modifier & 0x3FF;
816 u64 in_param = vhcr->in_param;
820 if (slave == dev->caps.function)
821 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
822 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
825 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
826 if (in_param & (1LL << i))
827 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
832 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
835 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
836 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
840 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
843 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
844 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
848 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
851 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
852 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
856 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
859 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
860 * we need to map, take the difference of highest index and
861 * the lowest index we'll use and add 1.
863 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
864 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
867 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
869 struct mlx4_priv *priv = mlx4_priv(dev);
872 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
874 if (!priv->eq_table.uar_map[index]) {
875 priv->eq_table.uar_map[index] =
876 ioremap(pci_resource_start(dev->pdev, 2) +
877 ((eq->eqn / 4) << PAGE_SHIFT),
879 if (!priv->eq_table.uar_map[index]) {
880 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
886 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
889 static void mlx4_unmap_uar(struct mlx4_dev *dev)
891 struct mlx4_priv *priv = mlx4_priv(dev);
894 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
895 if (priv->eq_table.uar_map[i]) {
896 iounmap(priv->eq_table.uar_map[i]);
897 priv->eq_table.uar_map[i] = NULL;
901 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
902 u8 intr, struct mlx4_eq *eq)
904 struct mlx4_priv *priv = mlx4_priv(dev);
905 struct mlx4_cmd_mailbox *mailbox;
906 struct mlx4_eq_context *eq_context;
908 u64 *dma_list = NULL;
915 eq->nent = roundup_pow_of_two(max(nent, 2));
916 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */
917 npages = PAGE_ALIGN(eq->nent * (MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor)) / PAGE_SIZE;
919 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
924 for (i = 0; i < npages; ++i)
925 eq->page_list[i].buf = NULL;
927 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
931 mailbox = mlx4_alloc_cmd_mailbox(dev);
934 eq_context = mailbox->buf;
936 for (i = 0; i < npages; ++i) {
937 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
938 PAGE_SIZE, &t, GFP_KERNEL);
939 if (!eq->page_list[i].buf)
940 goto err_out_free_pages;
943 eq->page_list[i].map = t;
945 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
948 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
950 goto err_out_free_pages;
952 eq->doorbell = mlx4_get_eq_uar(dev, eq);
955 goto err_out_free_eq;
958 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
960 goto err_out_free_eq;
962 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
964 goto err_out_free_mtt;
966 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
967 MLX4_EQ_STATE_ARMED);
968 eq_context->log_eq_size = ilog2(eq->nent);
969 eq_context->intr = intr;
970 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
972 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
973 eq_context->mtt_base_addr_h = mtt_addr >> 32;
974 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
976 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
978 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
979 goto err_out_free_mtt;
983 mlx4_free_cmd_mailbox(dev, mailbox);
990 mlx4_mtt_cleanup(dev, &eq->mtt);
993 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
996 for (i = 0; i < npages; ++i)
997 if (eq->page_list[i].buf)
998 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
999 eq->page_list[i].buf,
1000 eq->page_list[i].map);
1002 mlx4_free_cmd_mailbox(dev, mailbox);
1005 kfree(eq->page_list);
1012 static void mlx4_free_eq(struct mlx4_dev *dev,
1015 struct mlx4_priv *priv = mlx4_priv(dev);
1016 struct mlx4_cmd_mailbox *mailbox;
1019 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */
1020 int npages = PAGE_ALIGN((MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor) * eq->nent) / PAGE_SIZE;
1022 mailbox = mlx4_alloc_cmd_mailbox(dev);
1023 if (IS_ERR(mailbox))
1026 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
1028 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1031 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
1032 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
1034 pr_cont("[%02x] ", i * 4);
1035 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
1036 if ((i + 1) % 4 == 0)
1041 mlx4_mtt_cleanup(dev, &eq->mtt);
1042 for (i = 0; i < npages; ++i)
1043 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1044 eq->page_list[i].buf,
1045 eq->page_list[i].map);
1047 kfree(eq->page_list);
1048 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1049 mlx4_free_cmd_mailbox(dev, mailbox);
1052 static void mlx4_free_irqs(struct mlx4_dev *dev)
1054 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1055 struct mlx4_priv *priv = mlx4_priv(dev);
1058 if (eq_table->have_irq)
1059 free_irq(dev->pdev->irq, dev);
1061 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1062 if (eq_table->eq[i].have_irq) {
1063 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1064 eq_table->eq[i].have_irq = 0;
1067 for (i = 0; i < dev->caps.comp_pool; i++) {
1069 * Freeing the assigned irq's
1070 * all bits should be 0, but we need to validate
1072 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1073 /* NO need protecting*/
1074 vec = dev->caps.num_comp_vectors + 1 + i;
1075 free_irq(priv->eq_table.eq[vec].irq,
1076 &priv->eq_table.eq[vec]);
1081 kfree(eq_table->irq_names);
1084 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1086 struct mlx4_priv *priv = mlx4_priv(dev);
1088 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
1089 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1090 if (!priv->clr_base) {
1091 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
1098 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1100 struct mlx4_priv *priv = mlx4_priv(dev);
1102 iounmap(priv->clr_base);
1105 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1107 struct mlx4_priv *priv = mlx4_priv(dev);
1109 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1110 sizeof *priv->eq_table.eq, GFP_KERNEL);
1111 if (!priv->eq_table.eq)
1117 void mlx4_free_eq_table(struct mlx4_dev *dev)
1119 kfree(mlx4_priv(dev)->eq_table.eq);
1122 int mlx4_init_eq_table(struct mlx4_dev *dev)
1124 struct mlx4_priv *priv = mlx4_priv(dev);
1128 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1129 sizeof *priv->eq_table.uar_map,
1131 if (!priv->eq_table.uar_map) {
1136 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
1137 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
1141 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1142 priv->eq_table.uar_map[i] = NULL;
1144 if (!mlx4_is_slave(dev)) {
1145 err = mlx4_map_clr_int(dev);
1147 goto err_out_bitmap;
1149 priv->eq_table.clr_mask =
1150 swab32(1 << (priv->eq_table.inta_pin & 31));
1151 priv->eq_table.clr_int = priv->clr_base +
1152 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1155 priv->eq_table.irq_names =
1156 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1157 dev->caps.comp_pool),
1159 if (!priv->eq_table.irq_names) {
1161 goto err_out_bitmap;
1164 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1165 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1166 dev->caps.reserved_cqs +
1168 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1169 &priv->eq_table.eq[i]);
1176 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1177 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1178 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1182 /*if additional completion vectors poolsize is 0 this loop will not run*/
1183 for (i = dev->caps.num_comp_vectors + 1;
1184 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1186 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1187 dev->caps.reserved_cqs +
1189 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1190 &priv->eq_table.eq[i]);
1198 if (dev->flags & MLX4_FLAG_MSI_X) {
1199 const char *eq_name;
1201 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1202 if (i < dev->caps.num_comp_vectors) {
1203 snprintf(priv->eq_table.irq_names +
1204 i * MLX4_IRQNAME_SIZE,
1206 "mlx4-comp-%d@pci:%s", i,
1207 pci_name(dev->pdev));
1209 snprintf(priv->eq_table.irq_names +
1210 i * MLX4_IRQNAME_SIZE,
1212 "mlx4-async@pci:%s",
1213 pci_name(dev->pdev));
1216 eq_name = priv->eq_table.irq_names +
1217 i * MLX4_IRQNAME_SIZE;
1218 err = request_irq(priv->eq_table.eq[i].irq,
1219 mlx4_msi_x_interrupt, 0, eq_name,
1220 priv->eq_table.eq + i);
1224 priv->eq_table.eq[i].have_irq = 1;
1227 snprintf(priv->eq_table.irq_names,
1230 pci_name(dev->pdev));
1231 err = request_irq(dev->pdev->irq, mlx4_interrupt,
1232 IRQF_SHARED, priv->eq_table.irq_names, dev);
1236 priv->eq_table.have_irq = 1;
1239 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1240 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1242 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1243 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1245 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1246 eq_set_ci(&priv->eq_table.eq[i], 1);
1251 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1254 i = dev->caps.num_comp_vectors - 1;
1258 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1261 if (!mlx4_is_slave(dev))
1262 mlx4_unmap_clr_int(dev);
1263 mlx4_free_irqs(dev);
1266 mlx4_unmap_uar(dev);
1267 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1270 kfree(priv->eq_table.uar_map);
1275 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1277 struct mlx4_priv *priv = mlx4_priv(dev);
1280 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1281 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1283 mlx4_free_irqs(dev);
1285 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1286 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1288 if (!mlx4_is_slave(dev))
1289 mlx4_unmap_clr_int(dev);
1291 mlx4_unmap_uar(dev);
1292 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1294 kfree(priv->eq_table.uar_map);
1297 /* A test that verifies that we can accept interrupts on all
1298 * the irq vectors of the device.
1299 * Interrupts are checked using the NOP command.
1301 int mlx4_test_interrupts(struct mlx4_dev *dev)
1303 struct mlx4_priv *priv = mlx4_priv(dev);
1307 err = mlx4_NOP(dev);
1308 /* When not in MSI_X, there is only one irq to check */
1309 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1312 /* A loop over all completion vectors, for each vector we will check
1313 * whether it works by mapping command completions to that vector
1314 * and performing a NOP command
1316 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1317 /* Temporary use polling for command completions */
1318 mlx4_cmd_use_polling(dev);
1320 /* Map the new eq to handle all asynchronous events */
1321 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1322 priv->eq_table.eq[i].eqn);
1324 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1325 mlx4_cmd_use_events(dev);
1329 /* Go back to using events */
1330 mlx4_cmd_use_events(dev);
1331 err = mlx4_NOP(dev);
1334 /* Return to default */
1335 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1336 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1339 EXPORT_SYMBOL(mlx4_test_interrupts);
1341 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1345 struct mlx4_priv *priv = mlx4_priv(dev);
1346 int vec = 0, err = 0, i;
1348 mutex_lock(&priv->msix_ctl.pool_lock);
1349 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1350 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1351 priv->msix_ctl.pool_bm |= 1ULL << i;
1352 vec = dev->caps.num_comp_vectors + 1 + i;
1353 snprintf(priv->eq_table.irq_names +
1354 vec * MLX4_IRQNAME_SIZE,
1355 MLX4_IRQNAME_SIZE, "%s", name);
1356 #ifdef CONFIG_RFS_ACCEL
1358 err = irq_cpu_rmap_add(rmap,
1359 priv->eq_table.eq[vec].irq);
1361 mlx4_warn(dev, "Failed adding irq rmap\n");
1364 err = request_irq(priv->eq_table.eq[vec].irq,
1365 mlx4_msi_x_interrupt, 0,
1366 &priv->eq_table.irq_names[vec<<5],
1367 priv->eq_table.eq + vec);
1369 /*zero out bit by fliping it*/
1370 priv->msix_ctl.pool_bm ^= 1 << i;
1373 /*we dont want to break here*/
1375 eq_set_ci(&priv->eq_table.eq[vec], 1);
1378 mutex_unlock(&priv->msix_ctl.pool_lock);
1384 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1388 EXPORT_SYMBOL(mlx4_assign_eq);
1390 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1392 struct mlx4_priv *priv = mlx4_priv(dev);
1394 int i = vec - dev->caps.num_comp_vectors - 1;
1396 if (likely(i >= 0)) {
1397 /*sanity check , making sure were not trying to free irq's
1398 Belonging to a legacy EQ*/
1399 mutex_lock(&priv->msix_ctl.pool_lock);
1400 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1401 free_irq(priv->eq_table.eq[vec].irq,
1402 &priv->eq_table.eq[vec]);
1403 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1405 mutex_unlock(&priv->msix_ctl.pool_lock);
1409 EXPORT_SYMBOL(mlx4_release_eq);