2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
56 #define MLX4_GET(dest, source, offset) \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
68 #define MLX4_PUT(dest, source, offset) \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
95 [15] = "Big LSO headers",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [59] = "Port management change event support",
116 mlx4_dbg(dev, "DEV_CAP flags:\n");
117 for (i = 0; i < ARRAY_SIZE(fname); ++i)
118 if (fname[i] && (flags & (1LL << i)))
119 mlx4_dbg(dev, " %s\n", fname[i]);
122 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
124 static const char * const fname[] = {
126 [1] = "RSS Toeplitz Hash Function support",
127 [2] = "RSS XOR Hash Function support",
128 [3] = "Device manage flow steering support"
132 for (i = 0; i < ARRAY_SIZE(fname); ++i)
133 if (fname[i] && (flags & (1LL << i)))
134 mlx4_dbg(dev, " %s\n", fname[i]);
137 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
139 struct mlx4_cmd_mailbox *mailbox;
143 #define MOD_STAT_CFG_IN_SIZE 0x100
145 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
146 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
148 mailbox = mlx4_alloc_cmd_mailbox(dev);
150 return PTR_ERR(mailbox);
151 inbox = mailbox->buf;
153 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
155 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
156 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
158 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
159 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
161 mlx4_free_cmd_mailbox(dev, mailbox);
165 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
166 struct mlx4_vhcr *vhcr,
167 struct mlx4_cmd_mailbox *inbox,
168 struct mlx4_cmd_mailbox *outbox,
169 struct mlx4_cmd_info *cmd)
175 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
176 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
177 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
178 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
179 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
180 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
181 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
182 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
183 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
184 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
185 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
186 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
188 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
189 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
190 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
192 /* when opcode modifier = 1 */
193 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
194 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
195 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
197 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
198 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
200 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
202 if (vhcr->op_modifier == 1) {
203 field = vhcr->in_modifier;
204 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
207 /* ensure force vlan and force mac bits are not set */
208 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
209 /* ensure that phy_wqe_gid bit is not set */
210 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
212 } else if (vhcr->op_modifier == 0) {
213 /* enable rdma and ethernet interfaces */
214 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
215 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
217 field = dev->caps.num_ports;
218 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
220 size = 0; /* no PF behaviour is set for now */
221 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
223 field = 0; /* protected FMR support not available as yet */
224 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
226 size = dev->caps.num_qps;
227 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
229 size = dev->caps.num_srqs;
230 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
232 size = dev->caps.num_cqs;
233 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
235 size = dev->caps.num_eqs;
236 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
238 size = dev->caps.reserved_eqs;
239 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
241 size = dev->caps.num_mpts;
242 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
244 size = dev->caps.num_mtts;
245 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
247 size = dev->caps.num_mgms + dev->caps.num_amgms;
248 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
256 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
258 struct mlx4_cmd_mailbox *mailbox;
266 mailbox = mlx4_alloc_cmd_mailbox(dev);
268 return PTR_ERR(mailbox);
270 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
271 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
275 outbox = mailbox->buf;
277 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
278 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
279 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
280 err = -EPROTONOSUPPORT;
283 func_cap->flags = field;
285 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
286 func_cap->num_ports = field;
288 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
289 func_cap->pf_context_behaviour = size;
291 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
292 func_cap->qp_quota = size & 0xFFFFFF;
294 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
295 func_cap->srq_quota = size & 0xFFFFFF;
297 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
298 func_cap->cq_quota = size & 0xFFFFFF;
300 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
301 func_cap->max_eq = size & 0xFFFFFF;
303 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
304 func_cap->reserved_eq = size & 0xFFFFFF;
306 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
307 func_cap->mpt_quota = size & 0xFFFFFF;
309 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
310 func_cap->mtt_quota = size & 0xFFFFFF;
312 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
313 func_cap->mcg_quota = size & 0xFFFFFF;
315 for (i = 1; i <= func_cap->num_ports; ++i) {
316 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
317 MLX4_CMD_QUERY_FUNC_CAP,
318 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
322 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {
323 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
324 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
325 mlx4_err(dev, "VLAN is enforced on this port\n");
326 err = -EPROTONOSUPPORT;
330 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
331 mlx4_err(dev, "Force mac is enabled on this port\n");
332 err = -EPROTONOSUPPORT;
335 } else if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB) {
336 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
337 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
338 mlx4_err(dev, "phy_wqe_gid is "
339 "enforced on this ib port\n");
340 err = -EPROTONOSUPPORT;
345 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
346 func_cap->physical_port[i] = field;
349 /* All other resources are allocated by the master, but we still report
350 * 'num' and 'reserved' capabilities as follows:
351 * - num remains the maximum resource index
352 * - 'num - reserved' is the total available objects of a resource, but
353 * resource indices may be less than 'reserved'
354 * TODO: set per-resource quotas */
357 mlx4_free_cmd_mailbox(dev, mailbox);
362 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
364 struct mlx4_cmd_mailbox *mailbox;
367 u32 field32, flags, ext_flags;
373 #define QUERY_DEV_CAP_OUT_SIZE 0x100
374 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
375 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
376 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
377 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
378 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
379 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
380 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
381 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
382 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
383 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
384 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
385 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
386 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
387 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
388 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
389 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
390 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
391 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
392 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
393 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
394 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
395 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
396 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
397 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
398 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
399 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
400 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
401 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
402 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
403 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
404 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
405 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
406 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
407 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
408 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
409 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
410 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
411 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
412 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
413 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
414 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
415 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
416 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
417 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
418 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
419 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
420 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
421 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
422 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
423 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
424 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
425 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
426 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
427 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
428 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
429 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
430 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
431 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
432 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
433 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
434 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
435 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
436 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
437 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
438 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
439 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
440 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
441 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
444 mailbox = mlx4_alloc_cmd_mailbox(dev);
446 return PTR_ERR(mailbox);
447 outbox = mailbox->buf;
449 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
450 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
454 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
455 dev_cap->reserved_qps = 1 << (field & 0xf);
456 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
457 dev_cap->max_qps = 1 << (field & 0x1f);
458 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
459 dev_cap->reserved_srqs = 1 << (field >> 4);
460 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
461 dev_cap->max_srqs = 1 << (field & 0x1f);
462 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
463 dev_cap->max_cq_sz = 1 << field;
464 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
465 dev_cap->reserved_cqs = 1 << (field & 0xf);
466 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
467 dev_cap->max_cqs = 1 << (field & 0x1f);
468 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
469 dev_cap->max_mpts = 1 << (field & 0x3f);
470 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
471 dev_cap->reserved_eqs = field & 0xf;
472 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
473 dev_cap->max_eqs = 1 << (field & 0xf);
474 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
475 dev_cap->reserved_mtts = 1 << (field >> 4);
476 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
477 dev_cap->max_mrw_sz = 1 << field;
478 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
479 dev_cap->reserved_mrws = 1 << (field & 0xf);
480 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
481 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
482 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
483 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
484 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
485 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
486 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
489 dev_cap->max_gso_sz = 0;
491 dev_cap->max_gso_sz = 1 << field;
493 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
495 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
497 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
500 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
501 dev_cap->max_rss_tbl_sz = 1 << field;
503 dev_cap->max_rss_tbl_sz = 0;
504 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
505 dev_cap->max_rdma_global = 1 << (field & 0x3f);
506 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
507 dev_cap->local_ca_ack_delay = field & 0x1f;
508 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
509 dev_cap->num_ports = field & 0xf;
510 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
511 dev_cap->max_msg_sz = 1 << (field & 0x1f);
512 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
514 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
515 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
516 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
517 dev_cap->fs_max_num_qp_per_entry = field;
518 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
519 dev_cap->stat_rate_support = stat_rate;
520 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
521 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
522 dev_cap->flags = flags | (u64)ext_flags << 32;
523 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
524 dev_cap->reserved_uars = field >> 4;
525 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
526 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
527 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
528 dev_cap->min_page_sz = 1 << field;
530 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
532 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
533 dev_cap->bf_reg_size = 1 << (field & 0x1f);
534 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
535 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
537 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
538 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
539 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
541 dev_cap->bf_reg_size = 0;
542 mlx4_dbg(dev, "BlueFlame not available\n");
545 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
546 dev_cap->max_sq_sg = field;
547 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
548 dev_cap->max_sq_desc_sz = size;
550 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
551 dev_cap->max_qp_per_mcg = 1 << field;
552 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
553 dev_cap->reserved_mgms = field & 0xf;
554 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
555 dev_cap->max_mcgs = 1 << field;
556 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
557 dev_cap->reserved_pds = field >> 4;
558 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
559 dev_cap->max_pds = 1 << (field & 0x3f);
560 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
561 dev_cap->reserved_xrcds = field >> 4;
562 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
563 dev_cap->max_xrcds = 1 << (field & 0x1f);
565 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
566 dev_cap->rdmarc_entry_sz = size;
567 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
568 dev_cap->qpc_entry_sz = size;
569 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
570 dev_cap->aux_entry_sz = size;
571 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
572 dev_cap->altc_entry_sz = size;
573 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
574 dev_cap->eqc_entry_sz = size;
575 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
576 dev_cap->cqc_entry_sz = size;
577 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
578 dev_cap->srq_entry_sz = size;
579 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
580 dev_cap->cmpt_entry_sz = size;
581 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
582 dev_cap->mtt_entry_sz = size;
583 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
584 dev_cap->dmpt_entry_sz = size;
586 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
587 dev_cap->max_srq_sz = 1 << field;
588 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
589 dev_cap->max_qp_sz = 1 << field;
590 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
591 dev_cap->resize_srq = field & 1;
592 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
593 dev_cap->max_rq_sg = field;
594 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
595 dev_cap->max_rq_desc_sz = size;
597 MLX4_GET(dev_cap->bmme_flags, outbox,
598 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
599 MLX4_GET(dev_cap->reserved_lkey, outbox,
600 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
601 MLX4_GET(dev_cap->max_icm_sz, outbox,
602 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
603 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
604 MLX4_GET(dev_cap->max_counters, outbox,
605 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
607 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
608 for (i = 1; i <= dev_cap->num_ports; ++i) {
609 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
610 dev_cap->max_vl[i] = field >> 4;
611 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
612 dev_cap->ib_mtu[i] = field >> 4;
613 dev_cap->max_port_width[i] = field & 0xf;
614 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
615 dev_cap->max_gids[i] = 1 << (field & 0xf);
616 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
617 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
620 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
621 #define QUERY_PORT_MTU_OFFSET 0x01
622 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
623 #define QUERY_PORT_WIDTH_OFFSET 0x06
624 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
625 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
626 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
627 #define QUERY_PORT_MAC_OFFSET 0x10
628 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
629 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
630 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
632 for (i = 1; i <= dev_cap->num_ports; ++i) {
633 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
634 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
638 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
639 dev_cap->supported_port_types[i] = field & 3;
640 dev_cap->suggested_type[i] = (field >> 3) & 1;
641 dev_cap->default_sense[i] = (field >> 4) & 1;
642 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
643 dev_cap->ib_mtu[i] = field & 0xf;
644 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
645 dev_cap->max_port_width[i] = field & 0xf;
646 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
647 dev_cap->max_gids[i] = 1 << (field >> 4);
648 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
649 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
650 dev_cap->max_vl[i] = field & 0xf;
651 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
652 dev_cap->log_max_macs[i] = field & 0xf;
653 dev_cap->log_max_vlans[i] = field >> 4;
654 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
655 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
656 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
657 dev_cap->trans_type[i] = field32 >> 24;
658 dev_cap->vendor_oui[i] = field32 & 0xffffff;
659 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
660 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
664 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
665 dev_cap->bmme_flags, dev_cap->reserved_lkey);
668 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
669 * we can't use any EQs whose doorbell falls on that page,
670 * even if the EQ itself isn't reserved.
672 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
673 dev_cap->reserved_eqs);
675 mlx4_dbg(dev, "Max ICM size %lld MB\n",
676 (unsigned long long) dev_cap->max_icm_sz >> 20);
677 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
678 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
679 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
680 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
681 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
682 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
683 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
684 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
685 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
686 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
687 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
688 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
689 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
690 dev_cap->max_pds, dev_cap->reserved_mgms);
691 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
692 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
693 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
694 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
695 dev_cap->max_port_width[1]);
696 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
697 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
698 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
699 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
700 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
701 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
702 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
704 dump_dev_cap_flags(dev, dev_cap->flags);
705 dump_dev_cap_flags2(dev, dev_cap->flags2);
708 mlx4_free_cmd_mailbox(dev, mailbox);
712 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
713 struct mlx4_vhcr *vhcr,
714 struct mlx4_cmd_mailbox *inbox,
715 struct mlx4_cmd_mailbox *outbox,
716 struct mlx4_cmd_info *cmd)
721 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
722 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
726 /* For guests, report Blueflame disabled */
727 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
729 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
734 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
735 struct mlx4_vhcr *vhcr,
736 struct mlx4_cmd_mailbox *inbox,
737 struct mlx4_cmd_mailbox *outbox,
738 struct mlx4_cmd_info *cmd)
745 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
746 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
747 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
749 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
750 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
753 if (!err && dev->caps.function != slave) {
754 /* set slave default_mac address */
755 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
756 def_mac += slave << 8;
757 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
759 /* get port type - currently only eth is enabled */
760 MLX4_GET(port_type, outbox->buf,
761 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
763 /* No link sensing allowed */
764 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
765 /* set port type to currently operating port type */
766 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
768 MLX4_PUT(outbox->buf, port_type,
769 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
771 short_field = 1; /* slave max gids */
772 MLX4_PUT(outbox->buf, short_field,
773 QUERY_PORT_CUR_MAX_GID_OFFSET);
775 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
776 MLX4_PUT(outbox->buf, short_field,
777 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
783 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
784 int *gid_tbl_len, int *pkey_tbl_len)
786 struct mlx4_cmd_mailbox *mailbox;
791 mailbox = mlx4_alloc_cmd_mailbox(dev);
793 return PTR_ERR(mailbox);
795 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
796 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
801 outbox = mailbox->buf;
803 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
804 *gid_tbl_len = field;
806 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
807 *pkey_tbl_len = field;
810 mlx4_free_cmd_mailbox(dev, mailbox);
813 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
815 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
817 struct mlx4_cmd_mailbox *mailbox;
818 struct mlx4_icm_iter iter;
826 mailbox = mlx4_alloc_cmd_mailbox(dev);
828 return PTR_ERR(mailbox);
829 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
830 pages = mailbox->buf;
832 for (mlx4_icm_first(icm, &iter);
833 !mlx4_icm_last(&iter);
834 mlx4_icm_next(&iter)) {
836 * We have to pass pages that are aligned to their
837 * size, so find the least significant 1 in the
838 * address or size and use that as our log2 size.
840 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
841 if (lg < MLX4_ICM_PAGE_SHIFT) {
842 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
844 (unsigned long long) mlx4_icm_addr(&iter),
845 mlx4_icm_size(&iter));
850 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
852 pages[nent * 2] = cpu_to_be64(virt);
856 pages[nent * 2 + 1] =
857 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
858 (lg - MLX4_ICM_PAGE_SHIFT));
859 ts += 1 << (lg - 10);
862 if (++nent == MLX4_MAILBOX_SIZE / 16) {
863 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
864 MLX4_CMD_TIME_CLASS_B,
874 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
875 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
880 case MLX4_CMD_MAP_FA:
881 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
883 case MLX4_CMD_MAP_ICM_AUX:
884 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
886 case MLX4_CMD_MAP_ICM:
887 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
888 tc, ts, (unsigned long long) virt - (ts << 10));
893 mlx4_free_cmd_mailbox(dev, mailbox);
897 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
899 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
902 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
904 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
905 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
909 int mlx4_RUN_FW(struct mlx4_dev *dev)
911 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
912 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
915 int mlx4_QUERY_FW(struct mlx4_dev *dev)
917 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
918 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
919 struct mlx4_cmd_mailbox *mailbox;
926 #define QUERY_FW_OUT_SIZE 0x100
927 #define QUERY_FW_VER_OFFSET 0x00
928 #define QUERY_FW_PPF_ID 0x09
929 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
930 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
931 #define QUERY_FW_ERR_START_OFFSET 0x30
932 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
933 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
935 #define QUERY_FW_SIZE_OFFSET 0x00
936 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
937 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
939 #define QUERY_FW_COMM_BASE_OFFSET 0x40
940 #define QUERY_FW_COMM_BAR_OFFSET 0x48
942 mailbox = mlx4_alloc_cmd_mailbox(dev);
944 return PTR_ERR(mailbox);
945 outbox = mailbox->buf;
947 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
948 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
952 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
954 * FW subminor version is at more significant bits than minor
955 * version, so swap here.
957 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
958 ((fw_ver & 0xffff0000ull) >> 16) |
959 ((fw_ver & 0x0000ffffull) << 16);
961 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
962 dev->caps.function = lg;
964 if (mlx4_is_slave(dev))
968 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
969 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
970 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
971 mlx4_err(dev, "Installed FW has unsupported "
972 "command interface revision %d.\n",
974 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
975 (int) (dev->caps.fw_ver >> 32),
976 (int) (dev->caps.fw_ver >> 16) & 0xffff,
977 (int) dev->caps.fw_ver & 0xffff);
978 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
979 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
984 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
985 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
987 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
988 cmd->max_cmds = 1 << lg;
990 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
991 (int) (dev->caps.fw_ver >> 32),
992 (int) (dev->caps.fw_ver >> 16) & 0xffff,
993 (int) dev->caps.fw_ver & 0xffff,
994 cmd_if_rev, cmd->max_cmds);
996 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
997 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
998 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
999 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1001 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1002 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1004 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1005 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1006 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1007 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1009 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1010 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1011 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1012 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1013 fw->comm_bar, fw->comm_base);
1014 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1017 * Round up number of system pages needed in case
1018 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1021 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1022 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1024 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1025 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1028 mlx4_free_cmd_mailbox(dev, mailbox);
1032 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd)
1041 outbuf = outbox->buf;
1042 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1043 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1047 /* for slaves, set pci PPF ID to invalid and zero out everything
1048 * else except FW version */
1049 outbuf[0] = outbuf[1] = 0;
1050 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1051 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1056 static void get_board_id(void *vsd, char *board_id)
1060 #define VSD_OFFSET_SIG1 0x00
1061 #define VSD_OFFSET_SIG2 0xde
1062 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1063 #define VSD_OFFSET_TS_BOARD_ID 0x20
1065 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1067 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1069 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1070 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1071 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1074 * The board ID is a string but the firmware byte
1075 * swaps each 4-byte word before passing it back to
1076 * us. Therefore we need to swab it before printing.
1078 for (i = 0; i < 4; ++i)
1079 ((u32 *) board_id)[i] =
1080 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1084 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1086 struct mlx4_cmd_mailbox *mailbox;
1090 #define QUERY_ADAPTER_OUT_SIZE 0x100
1091 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1092 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1094 mailbox = mlx4_alloc_cmd_mailbox(dev);
1095 if (IS_ERR(mailbox))
1096 return PTR_ERR(mailbox);
1097 outbox = mailbox->buf;
1099 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1100 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1104 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1106 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1110 mlx4_free_cmd_mailbox(dev, mailbox);
1114 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1116 struct mlx4_cmd_mailbox *mailbox;
1120 #define INIT_HCA_IN_SIZE 0x200
1121 #define INIT_HCA_VERSION_OFFSET 0x000
1122 #define INIT_HCA_VERSION 2
1123 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1124 #define INIT_HCA_FLAGS_OFFSET 0x014
1125 #define INIT_HCA_QPC_OFFSET 0x020
1126 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1127 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1128 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1129 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1130 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1131 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1132 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1133 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1134 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1135 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1136 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1137 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1138 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1139 #define INIT_HCA_MCAST_OFFSET 0x0c0
1140 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1141 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1142 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1143 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1144 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1145 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1146 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1147 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1148 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1149 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1150 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1151 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1152 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1153 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1154 #define INIT_HCA_TPT_OFFSET 0x0f0
1155 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1156 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1157 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1158 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1159 #define INIT_HCA_UAR_OFFSET 0x120
1160 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1161 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1163 mailbox = mlx4_alloc_cmd_mailbox(dev);
1164 if (IS_ERR(mailbox))
1165 return PTR_ERR(mailbox);
1166 inbox = mailbox->buf;
1168 memset(inbox, 0, INIT_HCA_IN_SIZE);
1170 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1172 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1173 (ilog2(cache_line_size()) - 4) << 5;
1175 #if defined(__LITTLE_ENDIAN)
1176 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1177 #elif defined(__BIG_ENDIAN)
1178 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1180 #error Host endianness not defined
1182 /* Check port for UD address vector: */
1183 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1185 /* Enable IPoIB checksumming if we can: */
1186 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1187 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1189 /* Enable QoS support if module parameter set */
1191 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1193 /* enable counters */
1194 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1195 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1197 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1199 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1200 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1201 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1202 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1203 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1204 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1205 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1206 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1207 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1208 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1209 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1210 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1212 /* steering attributes */
1213 if (dev->caps.steering_mode ==
1214 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1215 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1217 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1219 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1220 MLX4_PUT(inbox, param->log_mc_entry_sz,
1221 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1222 MLX4_PUT(inbox, param->log_mc_table_sz,
1223 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1224 /* Enable Ethernet flow steering
1225 * with udp unicast and tcp unicast
1227 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1228 INIT_HCA_FS_ETH_BITS_OFFSET);
1229 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1230 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1231 /* Enable IPoIB flow steering
1232 * with udp unicast and tcp unicast
1234 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1235 INIT_HCA_FS_IB_BITS_OFFSET);
1236 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1237 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1239 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1240 MLX4_PUT(inbox, param->log_mc_entry_sz,
1241 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1242 MLX4_PUT(inbox, param->log_mc_hash_sz,
1243 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1244 MLX4_PUT(inbox, param->log_mc_table_sz,
1245 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1246 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1247 MLX4_PUT(inbox, (u8) (1 << 3),
1248 INIT_HCA_UC_STEERING_OFFSET);
1251 /* TPT attributes */
1253 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1254 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1255 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1256 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1258 /* UAR attributes */
1260 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1261 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1263 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1267 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1269 mlx4_free_cmd_mailbox(dev, mailbox);
1273 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1274 struct mlx4_init_hca_param *param)
1276 struct mlx4_cmd_mailbox *mailbox;
1280 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1282 mailbox = mlx4_alloc_cmd_mailbox(dev);
1283 if (IS_ERR(mailbox))
1284 return PTR_ERR(mailbox);
1285 outbox = mailbox->buf;
1287 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1289 MLX4_CMD_TIME_CLASS_B,
1290 !mlx4_is_slave(dev));
1294 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1296 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1298 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1299 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1300 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1301 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1302 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1303 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1304 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1305 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1306 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1307 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1308 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1309 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1311 /* steering attributes */
1312 if (dev->caps.steering_mode ==
1313 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1315 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1316 MLX4_GET(param->log_mc_entry_sz, outbox,
1317 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1318 MLX4_GET(param->log_mc_table_sz, outbox,
1319 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1321 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1322 MLX4_GET(param->log_mc_entry_sz, outbox,
1323 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1324 MLX4_GET(param->log_mc_hash_sz, outbox,
1325 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1326 MLX4_GET(param->log_mc_table_sz, outbox,
1327 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1330 /* TPT attributes */
1332 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1333 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1334 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1335 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1337 /* UAR attributes */
1339 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1340 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1343 mlx4_free_cmd_mailbox(dev, mailbox);
1348 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1349 struct mlx4_vhcr *vhcr,
1350 struct mlx4_cmd_mailbox *inbox,
1351 struct mlx4_cmd_mailbox *outbox,
1352 struct mlx4_cmd_info *cmd)
1354 struct mlx4_priv *priv = mlx4_priv(dev);
1355 int port = vhcr->in_modifier;
1358 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1361 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1364 /* Enable port only if it was previously disabled */
1365 if (!priv->mfunc.master.init_port_ref[port]) {
1366 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1367 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1371 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1372 ++priv->mfunc.master.init_port_ref[port];
1376 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1378 struct mlx4_cmd_mailbox *mailbox;
1384 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1385 #define INIT_PORT_IN_SIZE 256
1386 #define INIT_PORT_FLAGS_OFFSET 0x00
1387 #define INIT_PORT_FLAG_SIG (1 << 18)
1388 #define INIT_PORT_FLAG_NG (1 << 17)
1389 #define INIT_PORT_FLAG_G0 (1 << 16)
1390 #define INIT_PORT_VL_SHIFT 4
1391 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1392 #define INIT_PORT_MTU_OFFSET 0x04
1393 #define INIT_PORT_MAX_GID_OFFSET 0x06
1394 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1395 #define INIT_PORT_GUID0_OFFSET 0x10
1396 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1397 #define INIT_PORT_SI_GUID_OFFSET 0x20
1399 mailbox = mlx4_alloc_cmd_mailbox(dev);
1400 if (IS_ERR(mailbox))
1401 return PTR_ERR(mailbox);
1402 inbox = mailbox->buf;
1404 memset(inbox, 0, INIT_PORT_IN_SIZE);
1407 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1408 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1409 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1411 field = 128 << dev->caps.ib_mtu_cap[port];
1412 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1413 field = dev->caps.gid_table_len[port];
1414 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1415 field = dev->caps.pkey_table_len[port];
1416 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1418 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1419 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1421 mlx4_free_cmd_mailbox(dev, mailbox);
1423 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1424 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1428 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1430 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1431 struct mlx4_vhcr *vhcr,
1432 struct mlx4_cmd_mailbox *inbox,
1433 struct mlx4_cmd_mailbox *outbox,
1434 struct mlx4_cmd_info *cmd)
1436 struct mlx4_priv *priv = mlx4_priv(dev);
1437 int port = vhcr->in_modifier;
1440 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1444 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1446 if (priv->mfunc.master.init_port_ref[port] == 1) {
1447 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1452 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1453 --priv->mfunc.master.init_port_ref[port];
1457 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1459 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1462 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1464 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1466 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1470 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1472 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1473 MLX4_CMD_SET_ICM_SIZE,
1474 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1479 * Round up number of system pages needed in case
1480 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1482 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1483 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1488 int mlx4_NOP(struct mlx4_dev *dev)
1490 /* Input modifier of 0x1f means "finish as soon as possible." */
1491 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1494 #define MLX4_WOL_SETUP_MODE (5 << 28)
1495 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1497 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1499 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1500 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1503 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1505 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1507 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1509 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1510 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1512 EXPORT_SYMBOL_GPL(mlx4_wol_write);