2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/netdevice.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
58 struct workqueue_struct *mlx4_wq;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
81 module_param(num_vfs, int, 0444);
82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
85 module_param(probe_vf, int, 0644);
86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
88 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
89 module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 7 <="
94 " log_num_mgm_entry_size <= 12."
95 " To activate device managed"
96 " flow steering when available, set to -1");
98 static bool enable_64b_cqe_eqe;
99 module_param(enable_64b_cqe_eqe, bool, 0444);
100 MODULE_PARM_DESC(enable_64b_cqe_eqe,
101 "Enable 64 byte CQEs/EQEs when the the FW supports this");
103 #define HCA_GLOBAL_CAP_MASK 0
105 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
107 static char mlx4_version[] =
108 DRV_NAME ": Mellanox ConnectX core driver v"
109 DRV_VERSION " (" DRV_RELDATE ")\n";
111 static struct mlx4_profile default_profile = {
114 .rdmarc_per_qp = 1 << 4,
118 .num_mtt = 1 << 20, /* It is really num mtt segements */
121 static int log_num_mac = 7;
122 module_param_named(log_num_mac, log_num_mac, int, 0444);
123 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
125 static int log_num_vlan;
126 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
127 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
128 /* Log2 max number of VLANs per ETH port (0-7) */
129 #define MLX4_LOG_NUM_VLANS 7
131 static bool use_prio;
132 module_param_named(use_prio, use_prio, bool, 0444);
133 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
136 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
137 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
138 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
140 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
141 static int arr_argc = 2;
142 module_param_array(port_type_array, int, &arr_argc, 0444);
143 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
144 "1 for IB, 2 for Ethernet");
146 struct mlx4_port_config {
147 struct list_head list;
148 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
149 struct pci_dev *pdev;
152 int mlx4_check_port_params(struct mlx4_dev *dev,
153 enum mlx4_port_type *port_type)
157 for (i = 0; i < dev->caps.num_ports - 1; i++) {
158 if (port_type[i] != port_type[i + 1]) {
159 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
160 mlx4_err(dev, "Only same port types supported "
161 "on this HCA, aborting.\n");
167 for (i = 0; i < dev->caps.num_ports; i++) {
168 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
169 mlx4_err(dev, "Requested port type for port %d is not "
170 "supported on this HCA\n", i + 1);
177 static void mlx4_set_port_mask(struct mlx4_dev *dev)
181 for (i = 1; i <= dev->caps.num_ports; ++i)
182 dev->caps.port_mask[i] = dev->caps.port_type[i];
185 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
196 if (dev_cap->min_page_sz > PAGE_SIZE) {
197 mlx4_err(dev, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap->min_page_sz, PAGE_SIZE);
202 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
203 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
205 dev_cap->num_ports, MLX4_MAX_PORTS);
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
213 (unsigned long long) pci_resource_len(dev->pdev, 2));
217 dev->caps.num_ports = dev_cap->num_ports;
218 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
219 for (i = 1; i <= dev->caps.num_ports; ++i) {
220 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
221 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
222 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
223 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
224 /* set gid and pkey table operating lengths by default
225 * to non-sriov values */
226 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
227 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
228 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
229 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
230 dev->caps.def_mac[i] = dev_cap->def_mac[i];
231 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
232 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
233 dev->caps.default_sense[i] = dev_cap->default_sense[i];
234 dev->caps.trans_type[i] = dev_cap->trans_type[i];
235 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
236 dev->caps.wavelength[i] = dev_cap->wavelength[i];
237 dev->caps.trans_code[i] = dev_cap->trans_code[i];
240 dev->caps.uar_page_size = PAGE_SIZE;
241 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
242 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
243 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
244 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
245 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
246 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
247 dev->caps.max_wqes = dev_cap->max_qp_sz;
248 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
249 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
250 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
251 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
252 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
253 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
255 * Subtract 1 from the limit because we need to allocate a
256 * spare CQE so the HCA HW can tell the difference between an
257 * empty CQ and a full CQ.
259 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
260 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
261 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
262 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
263 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
265 /* The first 128 UARs are used for EQ doorbells */
266 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
267 dev->caps.reserved_pds = dev_cap->reserved_pds;
268 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->reserved_xrcds : 0;
270 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
271 dev_cap->max_xrcds : 0;
272 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
274 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
275 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
276 dev->caps.flags = dev_cap->flags;
277 dev->caps.flags2 = dev_cap->flags2;
278 dev->caps.bmme_flags = dev_cap->bmme_flags;
279 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
280 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
281 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
282 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
284 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
285 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
286 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
287 /* Don't do sense port on multifunction devices (for now at least) */
288 if (mlx4_is_mfunc(dev))
289 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
291 dev->caps.log_num_macs = log_num_mac;
292 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
293 dev->caps.log_num_prios = use_prio ? 3 : 0;
295 for (i = 1; i <= dev->caps.num_ports; ++i) {
296 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
297 if (dev->caps.supported_type[i]) {
298 /* if only ETH is supported - assign ETH */
299 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
300 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
301 /* if only IB is supported, assign IB */
302 else if (dev->caps.supported_type[i] ==
304 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
306 /* if IB and ETH are supported, we set the port
307 * type according to user selection of port type;
308 * if user selected none, take the FW hint */
309 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
310 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
311 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
313 dev->caps.port_type[i] = port_type_array[i - 1];
317 * Link sensing is allowed on the port if 3 conditions are true:
318 * 1. Both protocols are supported on the port.
319 * 2. Different types are supported on the port
320 * 3. FW declared that it supports link sensing
322 mlx4_priv(dev)->sense.sense_allowed[i] =
323 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
324 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
325 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
328 * If "default_sense" bit is set, we move the port to "AUTO" mode
329 * and perform sense_port FW command to try and set the correct
330 * port type from beginning
332 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
333 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
334 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
335 mlx4_SENSE_PORT(dev, i, &sensed_port);
336 if (sensed_port != MLX4_PORT_TYPE_NONE)
337 dev->caps.port_type[i] = sensed_port;
339 dev->caps.possible_type[i] = dev->caps.port_type[i];
342 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
343 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
344 mlx4_warn(dev, "Requested number of MACs is too much "
345 "for port %d, reducing to %d.\n",
346 i, 1 << dev->caps.log_num_macs);
348 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
349 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
350 mlx4_warn(dev, "Requested number of VLANs is too much "
351 "for port %d, reducing to %d.\n",
352 i, 1 << dev->caps.log_num_vlans);
356 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
358 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
361 (1 << dev->caps.log_num_macs) *
362 (1 << dev->caps.log_num_vlans) *
363 (1 << dev->caps.log_num_prios) *
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
367 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
369 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
372 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
374 if (!enable_64b_cqe_eqe) {
376 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
377 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
378 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
379 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
383 if ((dev->caps.flags &
384 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
386 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
390 /*The function checks if there are live vf, return the num of them*/
391 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
393 struct mlx4_priv *priv = mlx4_priv(dev);
394 struct mlx4_slave_state *s_state;
398 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
399 s_state = &priv->mfunc.master.slave_state[i];
400 if (s_state->active && s_state->last_cmd !=
401 MLX4_COMM_CMD_RESET) {
402 mlx4_warn(dev, "%s: slave: %d is still active\n",
410 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
412 u32 qk = MLX4_RESERVED_QKEY_BASE;
414 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
415 qpn < dev->phys_caps.base_proxy_sqpn)
418 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
420 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
422 qk += qpn - dev->phys_caps.base_proxy_sqpn;
426 EXPORT_SYMBOL(mlx4_get_parav_qkey);
428 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
430 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
432 if (!mlx4_is_master(dev))
435 priv->virt2phys_pkey[slave][port - 1][i] = val;
437 EXPORT_SYMBOL(mlx4_sync_pkey_table);
439 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
441 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
443 if (!mlx4_is_master(dev))
446 priv->slave_node_guids[slave] = guid;
448 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
450 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
452 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
454 if (!mlx4_is_master(dev))
457 return priv->slave_node_guids[slave];
459 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
461 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
463 struct mlx4_priv *priv = mlx4_priv(dev);
464 struct mlx4_slave_state *s_slave;
466 if (!mlx4_is_master(dev))
469 s_slave = &priv->mfunc.master.slave_state[slave];
470 return !!s_slave->active;
472 EXPORT_SYMBOL(mlx4_is_slave_active);
474 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
475 struct mlx4_dev_cap *dev_cap,
476 struct mlx4_init_hca_param *hca_param)
478 dev->caps.steering_mode = hca_param->steering_mode;
479 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
480 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
481 dev->caps.fs_log_max_ucast_qp_range_size =
482 dev_cap->fs_log_max_ucast_qp_range_size;
484 dev->caps.num_qp_per_mgm =
485 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
487 mlx4_dbg(dev, "Steering mode is: %s\n",
488 mlx4_steering_mode_str(dev->caps.steering_mode));
491 static int mlx4_slave_cap(struct mlx4_dev *dev)
495 struct mlx4_dev_cap dev_cap;
496 struct mlx4_func_cap func_cap;
497 struct mlx4_init_hca_param hca_param;
500 memset(&hca_param, 0, sizeof(hca_param));
501 err = mlx4_QUERY_HCA(dev, &hca_param);
503 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
507 /*fail if the hca has an unknown capability */
508 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
509 HCA_GLOBAL_CAP_MASK) {
510 mlx4_err(dev, "Unknown hca global capabilities\n");
514 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
516 dev->caps.hca_core_clock = hca_param.hca_core_clock;
518 memset(&dev_cap, 0, sizeof(dev_cap));
519 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
520 err = mlx4_dev_cap(dev, &dev_cap);
522 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
526 err = mlx4_QUERY_FW(dev);
528 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
530 page_size = ~dev->caps.page_size_cap + 1;
531 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
532 if (page_size > PAGE_SIZE) {
533 mlx4_err(dev, "HCA minimum page size of %d bigger than "
534 "kernel PAGE_SIZE of %ld, aborting.\n",
535 page_size, PAGE_SIZE);
539 /* slave gets uar page size from QUERY_HCA fw command */
540 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
542 /* TODO: relax this assumption */
543 if (dev->caps.uar_page_size != PAGE_SIZE) {
544 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
545 dev->caps.uar_page_size, PAGE_SIZE);
549 memset(&func_cap, 0, sizeof(func_cap));
550 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
552 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
557 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
558 PF_CONTEXT_BEHAVIOUR_MASK) {
559 mlx4_err(dev, "Unknown pf context behaviour\n");
563 dev->caps.num_ports = func_cap.num_ports;
564 dev->caps.num_qps = func_cap.qp_quota;
565 dev->caps.num_srqs = func_cap.srq_quota;
566 dev->caps.num_cqs = func_cap.cq_quota;
567 dev->caps.num_eqs = func_cap.max_eq;
568 dev->caps.reserved_eqs = func_cap.reserved_eq;
569 dev->caps.num_mpts = func_cap.mpt_quota;
570 dev->caps.num_mtts = func_cap.mtt_quota;
571 dev->caps.num_pds = MLX4_NUM_PDS;
572 dev->caps.num_mgms = 0;
573 dev->caps.num_amgms = 0;
575 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
576 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
577 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
581 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
582 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
583 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
584 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
586 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
587 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
592 for (i = 1; i <= dev->caps.num_ports; ++i) {
593 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
595 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
596 " port %d, aborting (%d).\n", i, err);
599 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
600 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
601 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
602 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
603 dev->caps.port_mask[i] = dev->caps.port_type[i];
604 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
605 &dev->caps.gid_table_len[i],
606 &dev->caps.pkey_table_len[i]))
610 if (dev->caps.uar_page_size * (dev->caps.num_uars -
611 dev->caps.reserved_uars) >
612 pci_resource_len(dev->pdev, 2)) {
613 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
614 "PCI resource 2 size of 0x%llx, aborting.\n",
615 dev->caps.uar_page_size * dev->caps.num_uars,
616 (unsigned long long) pci_resource_len(dev->pdev, 2));
620 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
621 dev->caps.eqe_size = 64;
622 dev->caps.eqe_factor = 1;
624 dev->caps.eqe_size = 32;
625 dev->caps.eqe_factor = 0;
628 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
629 dev->caps.cqe_size = 64;
630 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
632 dev->caps.cqe_size = 32;
635 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
640 kfree(dev->caps.qp0_tunnel);
641 kfree(dev->caps.qp0_proxy);
642 kfree(dev->caps.qp1_tunnel);
643 kfree(dev->caps.qp1_proxy);
644 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
645 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
651 * Change the port configuration of the device.
652 * Every user of this function must hold the port mutex.
654 int mlx4_change_port_types(struct mlx4_dev *dev,
655 enum mlx4_port_type *port_types)
661 for (port = 0; port < dev->caps.num_ports; port++) {
662 /* Change the port type only if the new type is different
663 * from the current, and not set to Auto */
664 if (port_types[port] != dev->caps.port_type[port + 1])
668 mlx4_unregister_device(dev);
669 for (port = 1; port <= dev->caps.num_ports; port++) {
670 mlx4_CLOSE_PORT(dev, port);
671 dev->caps.port_type[port] = port_types[port - 1];
672 err = mlx4_SET_PORT(dev, port, -1);
674 mlx4_err(dev, "Failed to set port %d, "
679 mlx4_set_port_mask(dev);
680 err = mlx4_register_device(dev);
687 static ssize_t show_port_type(struct device *dev,
688 struct device_attribute *attr,
691 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
693 struct mlx4_dev *mdev = info->dev;
697 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
699 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
700 sprintf(buf, "auto (%s)\n", type);
702 sprintf(buf, "%s\n", type);
707 static ssize_t set_port_type(struct device *dev,
708 struct device_attribute *attr,
709 const char *buf, size_t count)
711 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
713 struct mlx4_dev *mdev = info->dev;
714 struct mlx4_priv *priv = mlx4_priv(mdev);
715 enum mlx4_port_type types[MLX4_MAX_PORTS];
716 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
720 if (!strcmp(buf, "ib\n"))
721 info->tmp_type = MLX4_PORT_TYPE_IB;
722 else if (!strcmp(buf, "eth\n"))
723 info->tmp_type = MLX4_PORT_TYPE_ETH;
724 else if (!strcmp(buf, "auto\n"))
725 info->tmp_type = MLX4_PORT_TYPE_AUTO;
727 mlx4_err(mdev, "%s is not supported port type\n", buf);
731 mlx4_stop_sense(mdev);
732 mutex_lock(&priv->port_mutex);
733 /* Possible type is always the one that was delivered */
734 mdev->caps.possible_type[info->port] = info->tmp_type;
736 for (i = 0; i < mdev->caps.num_ports; i++) {
737 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
738 mdev->caps.possible_type[i+1];
739 if (types[i] == MLX4_PORT_TYPE_AUTO)
740 types[i] = mdev->caps.port_type[i+1];
743 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
744 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
745 for (i = 1; i <= mdev->caps.num_ports; i++) {
746 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
747 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
753 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
754 "Set only 'eth' or 'ib' for both ports "
755 "(should be the same)\n");
759 mlx4_do_sense_ports(mdev, new_types, types);
761 err = mlx4_check_port_params(mdev, new_types);
765 /* We are about to apply the changes after the configuration
766 * was verified, no need to remember the temporary types
768 for (i = 0; i < mdev->caps.num_ports; i++)
769 priv->port[i + 1].tmp_type = 0;
771 err = mlx4_change_port_types(mdev, new_types);
774 mlx4_start_sense(mdev);
775 mutex_unlock(&priv->port_mutex);
776 return err ? err : count;
787 static inline int int_to_ibta_mtu(int mtu)
790 case 256: return IB_MTU_256;
791 case 512: return IB_MTU_512;
792 case 1024: return IB_MTU_1024;
793 case 2048: return IB_MTU_2048;
794 case 4096: return IB_MTU_4096;
799 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
802 case IB_MTU_256: return 256;
803 case IB_MTU_512: return 512;
804 case IB_MTU_1024: return 1024;
805 case IB_MTU_2048: return 2048;
806 case IB_MTU_4096: return 4096;
811 static ssize_t show_port_ib_mtu(struct device *dev,
812 struct device_attribute *attr,
815 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
817 struct mlx4_dev *mdev = info->dev;
819 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
820 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
823 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
827 static ssize_t set_port_ib_mtu(struct device *dev,
828 struct device_attribute *attr,
829 const char *buf, size_t count)
831 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
833 struct mlx4_dev *mdev = info->dev;
834 struct mlx4_priv *priv = mlx4_priv(mdev);
835 int err, port, mtu, ibta_mtu = -1;
837 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
838 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
842 err = sscanf(buf, "%d", &mtu);
844 ibta_mtu = int_to_ibta_mtu(mtu);
846 if (err <= 0 || ibta_mtu < 0) {
847 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
851 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
853 mlx4_stop_sense(mdev);
854 mutex_lock(&priv->port_mutex);
855 mlx4_unregister_device(mdev);
856 for (port = 1; port <= mdev->caps.num_ports; port++) {
857 mlx4_CLOSE_PORT(mdev, port);
858 err = mlx4_SET_PORT(mdev, port, -1);
860 mlx4_err(mdev, "Failed to set port %d, "
865 err = mlx4_register_device(mdev);
867 mutex_unlock(&priv->port_mutex);
868 mlx4_start_sense(mdev);
869 return err ? err : count;
872 static int mlx4_load_fw(struct mlx4_dev *dev)
874 struct mlx4_priv *priv = mlx4_priv(dev);
877 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
878 GFP_HIGHUSER | __GFP_NOWARN, 0);
879 if (!priv->fw.fw_icm) {
880 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
884 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
886 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
890 err = mlx4_RUN_FW(dev);
892 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
902 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
906 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
909 struct mlx4_priv *priv = mlx4_priv(dev);
913 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
915 ((u64) (MLX4_CMPT_TYPE_QP *
916 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
917 cmpt_entry_sz, dev->caps.num_qps,
918 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
923 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
925 ((u64) (MLX4_CMPT_TYPE_SRQ *
926 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
927 cmpt_entry_sz, dev->caps.num_srqs,
928 dev->caps.reserved_srqs, 0, 0);
932 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
934 ((u64) (MLX4_CMPT_TYPE_CQ *
935 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
936 cmpt_entry_sz, dev->caps.num_cqs,
937 dev->caps.reserved_cqs, 0, 0);
941 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
943 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
945 ((u64) (MLX4_CMPT_TYPE_EQ *
946 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
947 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
954 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
957 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
960 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
966 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
967 struct mlx4_init_hca_param *init_hca, u64 icm_size)
969 struct mlx4_priv *priv = mlx4_priv(dev);
974 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
976 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
980 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
981 (unsigned long long) icm_size >> 10,
982 (unsigned long long) aux_pages << 2);
984 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
985 GFP_HIGHUSER | __GFP_NOWARN, 0);
986 if (!priv->fw.aux_icm) {
987 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
991 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
993 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
997 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
999 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1004 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1006 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1007 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1008 num_eqs, num_eqs, 0, 0);
1010 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1011 goto err_unmap_cmpt;
1015 * Reserved MTT entries must be aligned up to a cacheline
1016 * boundary, since the FW will write to them, while the driver
1017 * writes to all other MTT entries. (The variable
1018 * dev->caps.mtt_entry_sz below is really the MTT segment
1019 * size, not the raw entry size)
1021 dev->caps.reserved_mtts =
1022 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1023 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1025 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1027 dev->caps.mtt_entry_sz,
1029 dev->caps.reserved_mtts, 1, 0);
1031 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1035 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1036 init_hca->dmpt_base,
1037 dev_cap->dmpt_entry_sz,
1039 dev->caps.reserved_mrws, 1, 1);
1041 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1045 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1047 dev_cap->qpc_entry_sz,
1049 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1052 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1053 goto err_unmap_dmpt;
1056 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1057 init_hca->auxc_base,
1058 dev_cap->aux_entry_sz,
1060 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1063 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1067 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1068 init_hca->altc_base,
1069 dev_cap->altc_entry_sz,
1071 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1074 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1075 goto err_unmap_auxc;
1078 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1079 init_hca->rdmarc_base,
1080 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1082 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1085 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1086 goto err_unmap_altc;
1089 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1091 dev_cap->cqc_entry_sz,
1093 dev->caps.reserved_cqs, 0, 0);
1095 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1096 goto err_unmap_rdmarc;
1099 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1100 init_hca->srqc_base,
1101 dev_cap->srq_entry_sz,
1103 dev->caps.reserved_srqs, 0, 0);
1105 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1110 * For flow steering device managed mode it is required to use
1111 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1112 * required, but for simplicity just map the whole multicast
1113 * group table now. The table isn't very big and it's a lot
1114 * easier than trying to track ref counts.
1116 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1118 mlx4_get_mgm_entry_size(dev),
1119 dev->caps.num_mgms + dev->caps.num_amgms,
1120 dev->caps.num_mgms + dev->caps.num_amgms,
1123 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1130 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1133 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1136 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1139 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1142 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1145 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1148 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1151 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1154 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1157 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1158 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1159 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1160 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1163 mlx4_UNMAP_ICM_AUX(dev);
1166 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1171 static void mlx4_free_icms(struct mlx4_dev *dev)
1173 struct mlx4_priv *priv = mlx4_priv(dev);
1175 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1176 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1177 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1178 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1179 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1180 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1181 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1182 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1183 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1184 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1185 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1186 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1187 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1188 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1190 mlx4_UNMAP_ICM_AUX(dev);
1191 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1194 static void mlx4_slave_exit(struct mlx4_dev *dev)
1196 struct mlx4_priv *priv = mlx4_priv(dev);
1198 mutex_lock(&priv->cmd.slave_cmd_mutex);
1199 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1200 mlx4_warn(dev, "Failed to close slave function.\n");
1201 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1204 static int map_bf_area(struct mlx4_dev *dev)
1206 struct mlx4_priv *priv = mlx4_priv(dev);
1207 resource_size_t bf_start;
1208 resource_size_t bf_len;
1211 if (!dev->caps.bf_reg_size)
1214 bf_start = pci_resource_start(dev->pdev, 2) +
1215 (dev->caps.num_uars << PAGE_SHIFT);
1216 bf_len = pci_resource_len(dev->pdev, 2) -
1217 (dev->caps.num_uars << PAGE_SHIFT);
1218 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1219 if (!priv->bf_mapping)
1225 static void unmap_bf_area(struct mlx4_dev *dev)
1227 if (mlx4_priv(dev)->bf_mapping)
1228 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1231 static int map_internal_clock(struct mlx4_dev *dev)
1233 struct mlx4_priv *priv = mlx4_priv(dev);
1235 priv->clock_mapping =
1236 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1237 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1239 if (!priv->clock_mapping)
1245 static void unmap_internal_clock(struct mlx4_dev *dev)
1247 struct mlx4_priv *priv = mlx4_priv(dev);
1249 if (priv->clock_mapping)
1250 iounmap(priv->clock_mapping);
1253 static void mlx4_close_hca(struct mlx4_dev *dev)
1255 unmap_internal_clock(dev);
1257 if (mlx4_is_slave(dev))
1258 mlx4_slave_exit(dev);
1260 mlx4_CLOSE_HCA(dev, 0);
1261 mlx4_free_icms(dev);
1263 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1267 static int mlx4_init_slave(struct mlx4_dev *dev)
1269 struct mlx4_priv *priv = mlx4_priv(dev);
1270 u64 dma = (u64) priv->mfunc.vhcr_dma;
1271 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1272 int ret_from_reset = 0;
1274 u32 cmd_channel_ver;
1276 mutex_lock(&priv->cmd.slave_cmd_mutex);
1277 priv->cmd.max_cmds = 1;
1278 mlx4_warn(dev, "Sending reset\n");
1279 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1281 /* if we are in the middle of flr the slave will try
1282 * NUM_OF_RESET_RETRIES times before leaving.*/
1283 if (ret_from_reset) {
1284 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1285 msleep(SLEEP_TIME_IN_RESET);
1286 while (ret_from_reset && num_of_reset_retries) {
1287 mlx4_warn(dev, "slave is currently in the"
1288 "middle of FLR. retrying..."
1290 (NUM_OF_RESET_RETRIES -
1291 num_of_reset_retries + 1));
1293 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1295 num_of_reset_retries = num_of_reset_retries - 1;
1301 /* check the driver version - the slave I/F revision
1302 * must match the master's */
1303 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1304 cmd_channel_ver = mlx4_comm_get_version();
1306 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1307 MLX4_COMM_GET_IF_REV(slave_read)) {
1308 mlx4_err(dev, "slave driver version is not supported"
1309 " by the master\n");
1313 mlx4_warn(dev, "Sending vhcr0\n");
1314 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1317 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1320 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1323 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1326 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1330 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1331 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1335 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1339 for (i = 1; i <= dev->caps.num_ports; i++) {
1340 dev->caps.gid_table_len[i] = 1;
1341 dev->caps.pkey_table_len[i] =
1342 dev->phys_caps.pkey_phys_table_len[i] - 1;
1346 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1348 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1350 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1352 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1356 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1359 static void choose_steering_mode(struct mlx4_dev *dev,
1360 struct mlx4_dev_cap *dev_cap)
1362 if (mlx4_log_num_mgm_entry_size == -1 &&
1363 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1364 (!mlx4_is_mfunc(dev) ||
1365 (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1366 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1367 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1368 dev->oper_log_mgm_entry_size =
1369 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1370 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1371 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1372 dev->caps.fs_log_max_ucast_qp_range_size =
1373 dev_cap->fs_log_max_ucast_qp_range_size;
1375 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1376 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1377 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1379 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1381 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1382 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1383 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1384 "set to use B0 steering. Falling back to A0 steering mode.\n");
1386 dev->oper_log_mgm_entry_size =
1387 mlx4_log_num_mgm_entry_size > 0 ?
1388 mlx4_log_num_mgm_entry_size :
1389 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1390 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1392 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1393 "modparam log_num_mgm_entry_size = %d\n",
1394 mlx4_steering_mode_str(dev->caps.steering_mode),
1395 dev->oper_log_mgm_entry_size,
1396 mlx4_log_num_mgm_entry_size);
1399 static int mlx4_init_hca(struct mlx4_dev *dev)
1401 struct mlx4_priv *priv = mlx4_priv(dev);
1402 struct mlx4_adapter adapter;
1403 struct mlx4_dev_cap dev_cap;
1404 struct mlx4_mod_stat_cfg mlx4_cfg;
1405 struct mlx4_profile profile;
1406 struct mlx4_init_hca_param init_hca;
1410 if (!mlx4_is_slave(dev)) {
1411 err = mlx4_QUERY_FW(dev);
1414 mlx4_info(dev, "non-primary physical function, skipping.\n");
1416 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1420 err = mlx4_load_fw(dev);
1422 mlx4_err(dev, "Failed to start FW, aborting.\n");
1426 mlx4_cfg.log_pg_sz_m = 1;
1427 mlx4_cfg.log_pg_sz = 0;
1428 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1430 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1432 err = mlx4_dev_cap(dev, &dev_cap);
1434 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1438 choose_steering_mode(dev, &dev_cap);
1440 if (mlx4_is_master(dev))
1441 mlx4_parav_master_pf_caps(dev);
1443 profile = default_profile;
1444 if (dev->caps.steering_mode ==
1445 MLX4_STEERING_MODE_DEVICE_MANAGED)
1446 profile.num_mcg = MLX4_FS_NUM_MCG;
1448 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1450 if ((long long) icm_size < 0) {
1455 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1457 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1458 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1459 init_hca.mw_enabled = 0;
1460 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1461 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1462 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1464 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1468 err = mlx4_INIT_HCA(dev, &init_hca);
1470 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1474 * If TS is supported by FW
1475 * read HCA frequency by QUERY_HCA command
1477 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1478 memset(&init_hca, 0, sizeof(init_hca));
1479 err = mlx4_QUERY_HCA(dev, &init_hca);
1481 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1482 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1484 dev->caps.hca_core_clock =
1485 init_hca.hca_core_clock;
1488 /* In case we got HCA frequency 0 - disable timestamping
1489 * to avoid dividing by zero
1491 if (!dev->caps.hca_core_clock) {
1492 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1494 "HCA frequency is 0. Timestamping is not supported.");
1495 } else if (map_internal_clock(dev)) {
1497 * Map internal clock,
1498 * in case of failure disable timestamping
1500 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1501 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1505 err = mlx4_init_slave(dev);
1507 mlx4_err(dev, "Failed to initialize slave\n");
1511 err = mlx4_slave_cap(dev);
1513 mlx4_err(dev, "Failed to obtain slave caps\n");
1518 if (map_bf_area(dev))
1519 mlx4_dbg(dev, "Failed to map blue flame area\n");
1521 /*Only the master set the ports, all the rest got it from it.*/
1522 if (!mlx4_is_slave(dev))
1523 mlx4_set_port_mask(dev);
1525 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1527 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1531 priv->eq_table.inta_pin = adapter.inta_pin;
1532 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1537 unmap_internal_clock(dev);
1541 if (mlx4_is_slave(dev))
1542 mlx4_slave_exit(dev);
1544 mlx4_CLOSE_HCA(dev, 0);
1547 if (!mlx4_is_slave(dev))
1548 mlx4_free_icms(dev);
1551 if (!mlx4_is_slave(dev)) {
1553 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1558 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1560 struct mlx4_priv *priv = mlx4_priv(dev);
1563 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1566 nent = dev->caps.max_counters;
1567 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1570 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1572 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1575 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1577 struct mlx4_priv *priv = mlx4_priv(dev);
1579 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1582 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1589 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1594 if (mlx4_is_mfunc(dev)) {
1595 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1596 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1597 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1599 *idx = get_param_l(&out_param);
1603 return __mlx4_counter_alloc(dev, idx);
1605 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1607 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1609 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1613 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1617 if (mlx4_is_mfunc(dev)) {
1618 set_param_l(&in_param, idx);
1619 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1620 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1624 __mlx4_counter_free(dev, idx);
1626 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1628 static int mlx4_setup_hca(struct mlx4_dev *dev)
1630 struct mlx4_priv *priv = mlx4_priv(dev);
1633 __be32 ib_port_default_caps;
1635 err = mlx4_init_uar_table(dev);
1637 mlx4_err(dev, "Failed to initialize "
1638 "user access region table, aborting.\n");
1642 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1644 mlx4_err(dev, "Failed to allocate driver access region, "
1646 goto err_uar_table_free;
1649 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1651 mlx4_err(dev, "Couldn't map kernel access region, "
1657 err = mlx4_init_pd_table(dev);
1659 mlx4_err(dev, "Failed to initialize "
1660 "protection domain table, aborting.\n");
1664 err = mlx4_init_xrcd_table(dev);
1666 mlx4_err(dev, "Failed to initialize "
1667 "reliable connection domain table, aborting.\n");
1668 goto err_pd_table_free;
1671 err = mlx4_init_mr_table(dev);
1673 mlx4_err(dev, "Failed to initialize "
1674 "memory region table, aborting.\n");
1675 goto err_xrcd_table_free;
1678 err = mlx4_init_eq_table(dev);
1680 mlx4_err(dev, "Failed to initialize "
1681 "event queue table, aborting.\n");
1682 goto err_mr_table_free;
1685 err = mlx4_cmd_use_events(dev);
1687 mlx4_err(dev, "Failed to switch to event-driven "
1688 "firmware commands, aborting.\n");
1689 goto err_eq_table_free;
1692 err = mlx4_NOP(dev);
1694 if (dev->flags & MLX4_FLAG_MSI_X) {
1695 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1696 "interrupt IRQ %d).\n",
1697 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1698 mlx4_warn(dev, "Trying again without MSI-X.\n");
1700 mlx4_err(dev, "NOP command failed to generate interrupt "
1701 "(IRQ %d), aborting.\n",
1702 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1703 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1709 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1711 err = mlx4_init_cq_table(dev);
1713 mlx4_err(dev, "Failed to initialize "
1714 "completion queue table, aborting.\n");
1718 err = mlx4_init_srq_table(dev);
1720 mlx4_err(dev, "Failed to initialize "
1721 "shared receive queue table, aborting.\n");
1722 goto err_cq_table_free;
1725 err = mlx4_init_qp_table(dev);
1727 mlx4_err(dev, "Failed to initialize "
1728 "queue pair table, aborting.\n");
1729 goto err_srq_table_free;
1732 if (!mlx4_is_slave(dev)) {
1733 err = mlx4_init_mcg_table(dev);
1735 mlx4_err(dev, "Failed to initialize "
1736 "multicast group table, aborting.\n");
1737 goto err_qp_table_free;
1741 err = mlx4_init_counters_table(dev);
1742 if (err && err != -ENOENT) {
1743 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1744 goto err_mcg_table_free;
1747 if (!mlx4_is_slave(dev)) {
1748 for (port = 1; port <= dev->caps.num_ports; port++) {
1749 ib_port_default_caps = 0;
1750 err = mlx4_get_port_ib_caps(dev, port,
1751 &ib_port_default_caps);
1753 mlx4_warn(dev, "failed to get port %d default "
1754 "ib capabilities (%d). Continuing "
1755 "with caps = 0\n", port, err);
1756 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1758 /* initialize per-slave default ib port capabilities */
1759 if (mlx4_is_master(dev)) {
1761 for (i = 0; i < dev->num_slaves; i++) {
1762 if (i == mlx4_master_func_num(dev))
1764 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1765 ib_port_default_caps;
1769 if (mlx4_is_mfunc(dev))
1770 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1772 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1774 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1775 dev->caps.pkey_table_len[port] : -1);
1777 mlx4_err(dev, "Failed to set port %d, aborting\n",
1779 goto err_counters_table_free;
1786 err_counters_table_free:
1787 mlx4_cleanup_counters_table(dev);
1790 mlx4_cleanup_mcg_table(dev);
1793 mlx4_cleanup_qp_table(dev);
1796 mlx4_cleanup_srq_table(dev);
1799 mlx4_cleanup_cq_table(dev);
1802 mlx4_cmd_use_polling(dev);
1805 mlx4_cleanup_eq_table(dev);
1808 mlx4_cleanup_mr_table(dev);
1810 err_xrcd_table_free:
1811 mlx4_cleanup_xrcd_table(dev);
1814 mlx4_cleanup_pd_table(dev);
1820 mlx4_uar_free(dev, &priv->driver_uar);
1823 mlx4_cleanup_uar_table(dev);
1827 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1829 struct mlx4_priv *priv = mlx4_priv(dev);
1830 struct msix_entry *entries;
1831 int nreq = min_t(int, dev->caps.num_ports *
1832 min_t(int, netif_get_num_default_rss_queues() + 1,
1833 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1838 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1841 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1845 for (i = 0; i < nreq; ++i)
1846 entries[i].entry = i;
1849 err = pci_enable_msix(dev->pdev, entries, nreq);
1851 /* Try again if at least 2 vectors are available */
1853 mlx4_info(dev, "Requested %d vectors, "
1854 "but only %d MSI-X vectors available, "
1855 "trying again\n", nreq, err);
1864 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1865 /*Working in legacy mode , all EQ's shared*/
1866 dev->caps.comp_pool = 0;
1867 dev->caps.num_comp_vectors = nreq - 1;
1869 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1870 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1872 for (i = 0; i < nreq; ++i)
1873 priv->eq_table.eq[i].irq = entries[i].vector;
1875 dev->flags |= MLX4_FLAG_MSI_X;
1882 dev->caps.num_comp_vectors = 1;
1883 dev->caps.comp_pool = 0;
1885 for (i = 0; i < 2; ++i)
1886 priv->eq_table.eq[i].irq = dev->pdev->irq;
1889 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1891 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1896 if (!mlx4_is_slave(dev)) {
1897 mlx4_init_mac_table(dev, &info->mac_table);
1898 mlx4_init_vlan_table(dev, &info->vlan_table);
1899 info->base_qpn = mlx4_get_base_qpn(dev, port);
1902 sprintf(info->dev_name, "mlx4_port%d", port);
1903 info->port_attr.attr.name = info->dev_name;
1904 if (mlx4_is_mfunc(dev))
1905 info->port_attr.attr.mode = S_IRUGO;
1907 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1908 info->port_attr.store = set_port_type;
1910 info->port_attr.show = show_port_type;
1911 sysfs_attr_init(&info->port_attr.attr);
1913 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1915 mlx4_err(dev, "Failed to create file for port %d\n", port);
1919 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1920 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1921 if (mlx4_is_mfunc(dev))
1922 info->port_mtu_attr.attr.mode = S_IRUGO;
1924 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1925 info->port_mtu_attr.store = set_port_ib_mtu;
1927 info->port_mtu_attr.show = show_port_ib_mtu;
1928 sysfs_attr_init(&info->port_mtu_attr.attr);
1930 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1932 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1933 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1940 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1945 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1946 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
1949 static int mlx4_init_steering(struct mlx4_dev *dev)
1951 struct mlx4_priv *priv = mlx4_priv(dev);
1952 int num_entries = dev->caps.num_ports;
1955 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1959 for (i = 0; i < num_entries; i++)
1960 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1961 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1962 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1967 static void mlx4_clear_steering(struct mlx4_dev *dev)
1969 struct mlx4_priv *priv = mlx4_priv(dev);
1970 struct mlx4_steer_index *entry, *tmp_entry;
1971 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1972 int num_entries = dev->caps.num_ports;
1975 for (i = 0; i < num_entries; i++) {
1976 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1977 list_for_each_entry_safe(pqp, tmp_pqp,
1978 &priv->steer[i].promisc_qps[j],
1980 list_del(&pqp->list);
1983 list_for_each_entry_safe(entry, tmp_entry,
1984 &priv->steer[i].steer_entries[j],
1986 list_del(&entry->list);
1987 list_for_each_entry_safe(pqp, tmp_pqp,
1990 list_del(&pqp->list);
2000 static int extended_func_num(struct pci_dev *pdev)
2002 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2005 #define MLX4_OWNER_BASE 0x8069c
2006 #define MLX4_OWNER_SIZE 4
2008 static int mlx4_get_ownership(struct mlx4_dev *dev)
2010 void __iomem *owner;
2013 if (pci_channel_offline(dev->pdev))
2016 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2019 mlx4_err(dev, "Failed to obtain ownership bit\n");
2028 static void mlx4_free_ownership(struct mlx4_dev *dev)
2030 void __iomem *owner;
2032 if (pci_channel_offline(dev->pdev))
2035 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2038 mlx4_err(dev, "Failed to obtain ownership bit\n");
2046 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
2048 struct mlx4_priv *priv;
2049 struct mlx4_dev *dev;
2053 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2055 err = pci_enable_device(pdev);
2057 dev_err(&pdev->dev, "Cannot enable PCI device, "
2061 if (num_vfs > MLX4_MAX_NUM_VF) {
2062 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
2063 num_vfs, MLX4_MAX_NUM_VF);
2069 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2070 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2071 dev_err(&pdev->dev, "Missing DCS, aborting."
2072 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2073 pci_dev_data, pci_resource_flags(pdev, 0));
2075 goto err_disable_pdev;
2077 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2078 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2080 goto err_disable_pdev;
2083 err = pci_request_regions(pdev, DRV_NAME);
2085 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2086 goto err_disable_pdev;
2089 pci_set_master(pdev);
2091 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2093 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2094 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2096 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2097 goto err_release_regions;
2100 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2102 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2103 "consistent PCI DMA mask.\n");
2104 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2106 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2108 goto err_release_regions;
2112 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2113 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2115 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2118 goto err_release_regions;
2123 INIT_LIST_HEAD(&priv->ctx_list);
2124 spin_lock_init(&priv->ctx_lock);
2126 mutex_init(&priv->port_mutex);
2128 INIT_LIST_HEAD(&priv->pgdir_list);
2129 mutex_init(&priv->pgdir_mutex);
2131 INIT_LIST_HEAD(&priv->bf_list);
2132 mutex_init(&priv->bf_mutex);
2134 dev->rev_id = pdev->revision;
2135 /* Detect if this device is a virtual function */
2136 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2137 /* When acting as pf, we normally skip vfs unless explicitly
2138 * requested to probe them. */
2139 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2140 mlx4_warn(dev, "Skipping virtual function:%d\n",
2141 extended_func_num(pdev));
2145 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2146 dev->flags |= MLX4_FLAG_SLAVE;
2148 /* We reset the device and enable SRIOV only for physical
2149 * devices. Try to claim ownership on the device;
2150 * if already taken, skip -- do not allow multiple PFs */
2151 err = mlx4_get_ownership(dev);
2156 mlx4_warn(dev, "Multiple PFs not yet supported."
2164 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
2165 err = pci_enable_sriov(pdev, num_vfs);
2167 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2171 mlx4_warn(dev, "Running in master mode\n");
2172 dev->flags |= MLX4_FLAG_SRIOV |
2174 dev->num_vfs = num_vfs;
2179 * Now reset the HCA before we touch the PCI capabilities or
2180 * attempt a firmware command, since a boot ROM may have left
2181 * the HCA in an undefined state.
2183 err = mlx4_reset(dev);
2185 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2191 err = mlx4_cmd_init(dev);
2193 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2197 /* In slave functions, the communication channel must be initialized
2198 * before posting commands. Also, init num_slaves before calling
2200 if (mlx4_is_mfunc(dev)) {
2201 if (mlx4_is_master(dev))
2202 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2204 dev->num_slaves = 0;
2205 err = mlx4_multi_func_init(dev);
2207 mlx4_err(dev, "Failed to init slave mfunc"
2208 " interface, aborting.\n");
2214 err = mlx4_init_hca(dev);
2216 if (err == -EACCES) {
2217 /* Not primary Physical function
2218 * Running in slave mode */
2219 mlx4_cmd_cleanup(dev);
2220 dev->flags |= MLX4_FLAG_SLAVE;
2221 dev->flags &= ~MLX4_FLAG_MASTER;
2227 /* In master functions, the communication channel must be initialized
2228 * after obtaining its address from fw */
2229 if (mlx4_is_master(dev)) {
2230 err = mlx4_multi_func_init(dev);
2232 mlx4_err(dev, "Failed to init master mfunc"
2233 "interface, aborting.\n");
2238 err = mlx4_alloc_eq_table(dev);
2240 goto err_master_mfunc;
2242 priv->msix_ctl.pool_bm = 0;
2243 mutex_init(&priv->msix_ctl.pool_lock);
2245 mlx4_enable_msi_x(dev);
2246 if ((mlx4_is_mfunc(dev)) &&
2247 !(dev->flags & MLX4_FLAG_MSI_X)) {
2249 mlx4_err(dev, "INTx is not supported in multi-function mode."
2254 if (!mlx4_is_slave(dev)) {
2255 err = mlx4_init_steering(dev);
2260 err = mlx4_setup_hca(dev);
2261 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2262 !mlx4_is_mfunc(dev)) {
2263 dev->flags &= ~MLX4_FLAG_MSI_X;
2264 dev->caps.num_comp_vectors = 1;
2265 dev->caps.comp_pool = 0;
2266 pci_disable_msix(pdev);
2267 err = mlx4_setup_hca(dev);
2273 for (port = 1; port <= dev->caps.num_ports; port++) {
2274 err = mlx4_init_port_info(dev, port);
2279 err = mlx4_register_device(dev);
2283 mlx4_sense_init(dev);
2284 mlx4_start_sense(dev);
2286 priv->pci_dev_data = pci_dev_data;
2287 pci_set_drvdata(pdev, dev);
2292 for (--port; port >= 1; --port)
2293 mlx4_cleanup_port_info(&priv->port[port]);
2295 mlx4_cleanup_counters_table(dev);
2296 mlx4_cleanup_mcg_table(dev);
2297 mlx4_cleanup_qp_table(dev);
2298 mlx4_cleanup_srq_table(dev);
2299 mlx4_cleanup_cq_table(dev);
2300 mlx4_cmd_use_polling(dev);
2301 mlx4_cleanup_eq_table(dev);
2302 mlx4_cleanup_mr_table(dev);
2303 mlx4_cleanup_xrcd_table(dev);
2304 mlx4_cleanup_pd_table(dev);
2305 mlx4_cleanup_uar_table(dev);
2308 if (!mlx4_is_slave(dev))
2309 mlx4_clear_steering(dev);
2312 mlx4_free_eq_table(dev);
2315 if (mlx4_is_master(dev))
2316 mlx4_multi_func_cleanup(dev);
2319 if (dev->flags & MLX4_FLAG_MSI_X)
2320 pci_disable_msix(pdev);
2322 mlx4_close_hca(dev);
2325 if (mlx4_is_slave(dev))
2326 mlx4_multi_func_cleanup(dev);
2329 mlx4_cmd_cleanup(dev);
2332 if (dev->flags & MLX4_FLAG_SRIOV)
2333 pci_disable_sriov(pdev);
2336 if (!mlx4_is_slave(dev))
2337 mlx4_free_ownership(dev);
2342 err_release_regions:
2343 pci_release_regions(pdev);
2346 pci_disable_device(pdev);
2347 pci_set_drvdata(pdev, NULL);
2351 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2353 printk_once(KERN_INFO "%s", mlx4_version);
2355 return __mlx4_init_one(pdev, id->driver_data);
2358 static void mlx4_remove_one(struct pci_dev *pdev)
2360 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2361 struct mlx4_priv *priv = mlx4_priv(dev);
2365 /* in SRIOV it is not allowed to unload the pf's
2366 * driver while there are alive vf's */
2367 if (mlx4_is_master(dev)) {
2368 if (mlx4_how_many_lives_vf(dev))
2369 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2371 mlx4_stop_sense(dev);
2372 mlx4_unregister_device(dev);
2374 for (p = 1; p <= dev->caps.num_ports; p++) {
2375 mlx4_cleanup_port_info(&priv->port[p]);
2376 mlx4_CLOSE_PORT(dev, p);
2379 if (mlx4_is_master(dev))
2380 mlx4_free_resource_tracker(dev,
2381 RES_TR_FREE_SLAVES_ONLY);
2383 mlx4_cleanup_counters_table(dev);
2384 mlx4_cleanup_mcg_table(dev);
2385 mlx4_cleanup_qp_table(dev);
2386 mlx4_cleanup_srq_table(dev);
2387 mlx4_cleanup_cq_table(dev);
2388 mlx4_cmd_use_polling(dev);
2389 mlx4_cleanup_eq_table(dev);
2390 mlx4_cleanup_mr_table(dev);
2391 mlx4_cleanup_xrcd_table(dev);
2392 mlx4_cleanup_pd_table(dev);
2394 if (mlx4_is_master(dev))
2395 mlx4_free_resource_tracker(dev,
2396 RES_TR_FREE_STRUCTS_ONLY);
2399 mlx4_uar_free(dev, &priv->driver_uar);
2400 mlx4_cleanup_uar_table(dev);
2401 if (!mlx4_is_slave(dev))
2402 mlx4_clear_steering(dev);
2403 mlx4_free_eq_table(dev);
2404 if (mlx4_is_master(dev))
2405 mlx4_multi_func_cleanup(dev);
2406 mlx4_close_hca(dev);
2407 if (mlx4_is_slave(dev))
2408 mlx4_multi_func_cleanup(dev);
2409 mlx4_cmd_cleanup(dev);
2411 if (dev->flags & MLX4_FLAG_MSI_X)
2412 pci_disable_msix(pdev);
2413 if (dev->flags & MLX4_FLAG_SRIOV) {
2414 mlx4_warn(dev, "Disabling SR-IOV\n");
2415 pci_disable_sriov(pdev);
2418 if (!mlx4_is_slave(dev))
2419 mlx4_free_ownership(dev);
2421 kfree(dev->caps.qp0_tunnel);
2422 kfree(dev->caps.qp0_proxy);
2423 kfree(dev->caps.qp1_tunnel);
2424 kfree(dev->caps.qp1_proxy);
2427 pci_release_regions(pdev);
2428 pci_disable_device(pdev);
2429 pci_set_drvdata(pdev, NULL);
2433 int mlx4_restart_one(struct pci_dev *pdev)
2435 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2436 struct mlx4_priv *priv = mlx4_priv(dev);
2439 pci_dev_data = priv->pci_dev_data;
2440 mlx4_remove_one(pdev);
2441 return __mlx4_init_one(pdev, pci_dev_data);
2444 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2445 /* MT25408 "Hermon" SDR */
2446 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2447 /* MT25408 "Hermon" DDR */
2448 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2449 /* MT25408 "Hermon" QDR */
2450 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2451 /* MT25408 "Hermon" DDR PCIe gen2 */
2452 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2453 /* MT25408 "Hermon" QDR PCIe gen2 */
2454 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2455 /* MT25408 "Hermon" EN 10GigE */
2456 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2457 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2458 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2459 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2460 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2461 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2462 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2463 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2464 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2465 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2466 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2467 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2468 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2469 /* MT25400 Family [ConnectX-2 Virtual Function] */
2470 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2471 /* MT27500 Family [ConnectX-3] */
2472 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2473 /* MT27500 Family [ConnectX-3 Virtual Function] */
2474 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2475 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2476 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2477 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2478 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2479 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2480 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2481 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2482 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2483 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2484 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2485 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2486 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2490 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2492 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2493 pci_channel_state_t state)
2495 mlx4_remove_one(pdev);
2497 return state == pci_channel_io_perm_failure ?
2498 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2501 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2503 int ret = __mlx4_init_one(pdev, 0);
2505 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2508 static const struct pci_error_handlers mlx4_err_handler = {
2509 .error_detected = mlx4_pci_err_detected,
2510 .slot_reset = mlx4_pci_slot_reset,
2513 static struct pci_driver mlx4_driver = {
2515 .id_table = mlx4_pci_table,
2516 .probe = mlx4_init_one,
2517 .remove = mlx4_remove_one,
2518 .err_handler = &mlx4_err_handler,
2521 static int __init mlx4_verify_params(void)
2523 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2524 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2528 if (log_num_vlan != 0)
2529 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2530 MLX4_LOG_NUM_VLANS);
2532 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2533 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2537 /* Check if module param for ports type has legal combination */
2538 if (port_type_array[0] == false && port_type_array[1] == true) {
2539 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2540 port_type_array[0] = true;
2543 if (mlx4_log_num_mgm_entry_size != -1 &&
2544 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2545 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2546 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2547 "in legal range (-1 or %d..%d)\n",
2548 mlx4_log_num_mgm_entry_size,
2549 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2550 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2557 static int __init mlx4_init(void)
2561 if (mlx4_verify_params())
2566 mlx4_wq = create_singlethread_workqueue("mlx4");
2570 ret = pci_register_driver(&mlx4_driver);
2571 return ret < 0 ? ret : 0;
2574 static void __exit mlx4_cleanup(void)
2576 pci_unregister_driver(&mlx4_driver);
2577 destroy_workqueue(mlx4_wq);
2580 module_init(mlx4_init);
2581 module_exit(mlx4_cleanup);