2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
63 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
68 #define MLX4_RATELIMIT_DEFAULT 0xffff
70 struct mlx4_set_port_prio2tc_context {
74 struct mlx4_port_scheduler_tc_cfg_be {
77 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
81 struct mlx4_set_port_scheduler_context {
82 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
86 MLX4_HCR_BASE = 0x80680,
87 MLX4_HCR_SIZE = 0x0001c,
88 MLX4_CLR_INT_SIZE = 0x00008,
89 MLX4_SLAVE_COMM_BASE = 0x0,
90 MLX4_COMM_PAGESIZE = 0x1000,
91 MLX4_CLOCK_SIZE = 0x00008
95 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
96 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
97 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
98 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
103 MLX4_NUM_PDS = 1 << 15
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
119 enum mlx4_mpt_state {
120 MLX4_MPT_DISABLED = 0,
125 #define MLX4_COMM_TIME 10000
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
136 /*The flag indicates that the slave should delay the RESET cmd*/
137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138 /*indicates how many retries will be done if we are in the middle of FLR*/
139 #define NUM_OF_RESET_RETRIES 10
140 #define SLEEP_TIME_IN_RESET (2 * 1000)
153 MLX4_NUM_OF_RESOURCE_TYPE
156 enum mlx4_alloc_mode {
158 RES_OP_RESERVE_AND_MAP,
162 enum mlx4_res_tracker_free_type {
164 RES_TR_FREE_SLAVES_ONLY,
165 RES_TR_FREE_STRUCTS_ONLY,
169 *Virtual HCR structures.
170 * mlx4_vhcr is the sw representation, in machine endianess
172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173 * to FW to go through communication channel.
174 * It is big endian, and has the same structure as the physical HCR
175 * used by command interface
188 struct mlx4_vhcr_cmd {
199 struct mlx4_cmd_info {
204 bool encode_slave_id;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
213 #ifdef CONFIG_MLX4_DEBUG
214 extern int mlx4_debug_level;
215 #else /* CONFIG_MLX4_DEBUG */
216 #define mlx4_debug_level (0)
217 #endif /* CONFIG_MLX4_DEBUG */
219 #define mlx4_dbg(mdev, format, arg...) \
221 if (mlx4_debug_level) \
222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
225 #define mlx4_err(mdev, format, arg...) \
226 dev_err(&mdev->pdev->dev, format, ##arg)
227 #define mlx4_info(mdev, format, arg...) \
228 dev_info(&mdev->pdev->dev, format, ##arg)
229 #define mlx4_warn(mdev, format, arg...) \
230 dev_warn(&mdev->pdev->dev, format, ##arg)
232 extern int mlx4_log_num_mgm_entry_size;
233 extern int log_mtts_per_seg;
235 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236 #define ALL_SLAVES 0xff
246 unsigned long *table;
250 unsigned long **bits;
251 unsigned int *num_free;
258 struct mlx4_icm_table {
266 struct mlx4_icm **icm;
269 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
270 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
271 #define MLX4_MPT_FLAG_MIO (1 << 17)
272 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
273 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
274 #define MLX4_MPT_FLAG_REGION (1 << 8)
276 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
277 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
278 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
280 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
282 #define MLX4_MPT_STATUS_SW 0xF0
283 #define MLX4_MPT_STATUS_HW 0x00
286 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
288 struct mlx4_mpt_entry {
302 __be32 first_byte_offset;
306 * Must be packed because start is 64 bits but only aligned to 32 bits.
308 struct mlx4_eq_context {
322 __be32 mtt_base_addr_l;
324 __be32 consumer_index;
325 __be32 producer_index;
329 struct mlx4_cq_context {
333 __be32 logsize_usrpage;
341 __be32 mtt_base_addr_l;
342 __be32 last_notified_index;
343 __be32 solicit_producer_index;
344 __be32 consumer_index;
345 __be32 producer_index;
350 struct mlx4_srq_context {
351 __be32 state_logsize_srqn;
355 __be32 pg_offset_cqn;
360 __be32 mtt_base_addr_l;
362 __be16 limit_watermark;
371 struct mlx4_dev *dev;
372 void __iomem *doorbell;
378 struct mlx4_buf_list *page_list;
382 struct mlx4_slave_eqe {
388 struct mlx4_slave_event_eq_info {
393 struct mlx4_profile {
408 struct mlx4_icm *fw_icm;
409 struct mlx4_icm *aux_icm;
424 MLX4_MCAST_CONFIG = 0,
425 MLX4_MCAST_DISABLE = 1,
426 MLX4_MCAST_ENABLE = 2,
429 #define VLAN_FLTR_SIZE 128
431 struct mlx4_vlan_fltr {
432 __be32 entry[VLAN_FLTR_SIZE];
435 struct mlx4_mcast_entry {
436 struct list_head list;
440 struct mlx4_promisc_qp {
441 struct list_head list;
445 struct mlx4_steer_index {
446 struct list_head list;
448 struct list_head duplicates;
451 #define MLX4_EVENT_TYPES_NUM 64
453 struct mlx4_slave_state {
460 u16 mtu[MLX4_MAX_PORTS + 1];
461 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
462 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
463 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
464 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
465 /* event type to eq number lookup */
466 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
470 /*initialized via the kzalloc*/
471 u8 is_slave_going_down;
473 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
476 #define MLX4_VGT 4095
479 struct mlx4_vport_state {
487 struct mlx4_vf_admin_state {
488 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
491 struct mlx4_vport_oper_state {
492 struct mlx4_vport_state state;
496 struct mlx4_vf_oper_state {
497 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
502 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
505 struct mlx4_resource_tracker {
507 /* tree for each resources */
508 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
509 /* num_of_slave's lists, one per slave */
510 struct slave_list *slave_list;
513 #define SLAVE_EVENT_EQ_SIZE 128
514 struct mlx4_slave_event_eq {
518 spinlock_t event_lock;
519 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
522 struct mlx4_master_qp0_state {
523 int proxy_qp0_active;
528 struct mlx4_mfunc_master_ctx {
529 struct mlx4_slave_state *slave_state;
530 struct mlx4_vf_admin_state *vf_admin;
531 struct mlx4_vf_oper_state *vf_oper;
532 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
533 int init_port_ref[MLX4_MAX_PORTS + 1];
534 u16 max_mtu[MLX4_MAX_PORTS + 1];
535 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
536 struct mlx4_resource_tracker res_tracker;
537 struct workqueue_struct *comm_wq;
538 struct work_struct comm_work;
539 struct work_struct slave_event_work;
540 struct work_struct slave_flr_event_work;
541 spinlock_t slave_state_lock;
542 __be32 comm_arm_bit_vector[4];
543 struct mlx4_eqe cmd_eqe;
544 struct mlx4_slave_event_eq slave_eq;
545 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
549 struct mlx4_comm __iomem *comm;
550 struct mlx4_vhcr_cmd *vhcr;
553 struct mlx4_mfunc_master_ctx master;
557 struct pci_pool *pool;
559 struct mutex hcr_mutex;
560 struct mutex slave_cmd_mutex;
561 struct semaphore poll_sem;
562 struct semaphore event_sem;
564 spinlock_t context_lock;
566 struct mlx4_cmd_context *context;
573 struct mlx4_uar_table {
574 struct mlx4_bitmap bitmap;
577 struct mlx4_mr_table {
578 struct mlx4_bitmap mpt_bitmap;
579 struct mlx4_buddy mtt_buddy;
582 struct mlx4_icm_table mtt_table;
583 struct mlx4_icm_table dmpt_table;
586 struct mlx4_cq_table {
587 struct mlx4_bitmap bitmap;
589 struct radix_tree_root tree;
590 struct mlx4_icm_table table;
591 struct mlx4_icm_table cmpt_table;
594 struct mlx4_eq_table {
595 struct mlx4_bitmap bitmap;
597 void __iomem *clr_int;
598 void __iomem **uar_map;
601 struct mlx4_icm_table table;
602 struct mlx4_icm_table cmpt_table;
607 struct mlx4_srq_table {
608 struct mlx4_bitmap bitmap;
610 struct radix_tree_root tree;
611 struct mlx4_icm_table table;
612 struct mlx4_icm_table cmpt_table;
615 struct mlx4_qp_table {
616 struct mlx4_bitmap bitmap;
620 struct mlx4_icm_table qp_table;
621 struct mlx4_icm_table auxc_table;
622 struct mlx4_icm_table altc_table;
623 struct mlx4_icm_table rdmarc_table;
624 struct mlx4_icm_table cmpt_table;
627 struct mlx4_mcg_table {
629 struct mlx4_bitmap bitmap;
630 struct mlx4_icm_table table;
633 struct mlx4_catas_err {
635 struct timer_list timer;
636 struct list_head list;
639 #define MLX4_MAX_MAC_NUM 128
640 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
642 struct mlx4_mac_table {
643 __be64 entries[MLX4_MAX_MAC_NUM];
644 int refs[MLX4_MAX_MAC_NUM];
650 #define MLX4_MAX_VLAN_NUM 128
651 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
653 struct mlx4_vlan_table {
654 __be32 entries[MLX4_MAX_VLAN_NUM];
655 int refs[MLX4_MAX_VLAN_NUM];
661 #define SET_PORT_GEN_ALL_VALID 0x7
662 #define SET_PORT_PROMISC_SHIFT 31
663 #define SET_PORT_MC_PROMISC_SHIFT 30
666 MCAST_DIRECT_ONLY = 0,
672 struct mlx4_set_port_general_context {
685 struct mlx4_set_port_rqp_calc_context {
703 struct mlx4_port_info {
704 struct mlx4_dev *dev;
707 struct device_attribute port_attr;
708 enum mlx4_port_type tmp_type;
709 char dev_mtu_name[16];
710 struct device_attribute port_mtu_attr;
711 struct mlx4_mac_table mac_table;
712 struct mlx4_vlan_table vlan_table;
717 struct mlx4_dev *dev;
718 u8 do_sense_port[MLX4_MAX_PORTS + 1];
719 u8 sense_allowed[MLX4_MAX_PORTS + 1];
720 struct delayed_work sense_poll;
723 struct mlx4_msix_ctl {
725 struct mutex pool_lock;
729 struct list_head promisc_qps[MLX4_NUM_STEERS];
730 struct list_head steer_entries[MLX4_NUM_STEERS];
733 struct mlx4_net_trans_rule_hw_ctrl {
743 struct mlx4_net_trans_rule_hw_ib {
754 struct mlx4_net_trans_rule_hw_eth {
767 u8 ether_type_enable;
773 struct mlx4_net_trans_rule_hw_tcp_udp {
787 struct mlx4_net_trans_rule_hw_ipv4 {
805 struct mlx4_net_trans_rule_hw_eth eth;
806 struct mlx4_net_trans_rule_hw_ib ib;
807 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
808 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
813 MLX4_PCI_DEV_IS_VF = 1 << 0,
814 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
820 struct list_head dev_list;
821 struct list_head ctx_list;
826 struct list_head pgdir_list;
827 struct mutex pgdir_mutex;
831 struct mlx4_mfunc mfunc;
833 struct mlx4_bitmap pd_bitmap;
834 struct mlx4_bitmap xrcd_bitmap;
835 struct mlx4_uar_table uar_table;
836 struct mlx4_mr_table mr_table;
837 struct mlx4_cq_table cq_table;
838 struct mlx4_eq_table eq_table;
839 struct mlx4_srq_table srq_table;
840 struct mlx4_qp_table qp_table;
841 struct mlx4_mcg_table mcg_table;
842 struct mlx4_bitmap counters_bitmap;
844 struct mlx4_catas_err catas_err;
846 void __iomem *clr_base;
848 struct mlx4_uar driver_uar;
850 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
851 struct mlx4_sense sense;
852 struct mutex port_mutex;
853 struct mlx4_msix_ctl msix_ctl;
854 struct mlx4_steer *steer;
855 struct list_head bf_list;
856 struct mutex bf_mutex;
857 struct io_mapping *bf_mapping;
858 void __iomem *clock_mapping;
861 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
862 __be64 slave_node_guids[MLX4_MFUNC_MAX];
866 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
868 return container_of(dev, struct mlx4_priv, dev);
871 #define MLX4_SENSE_RANGE (HZ * 3)
873 extern struct workqueue_struct *mlx4_wq;
875 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
876 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
877 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
878 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
879 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
880 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
881 u32 reserved_bot, u32 resetrved_top);
882 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
884 int mlx4_reset(struct mlx4_dev *dev);
886 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
887 void mlx4_free_eq_table(struct mlx4_dev *dev);
889 int mlx4_init_pd_table(struct mlx4_dev *dev);
890 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
891 int mlx4_init_uar_table(struct mlx4_dev *dev);
892 int mlx4_init_mr_table(struct mlx4_dev *dev);
893 int mlx4_init_eq_table(struct mlx4_dev *dev);
894 int mlx4_init_cq_table(struct mlx4_dev *dev);
895 int mlx4_init_qp_table(struct mlx4_dev *dev);
896 int mlx4_init_srq_table(struct mlx4_dev *dev);
897 int mlx4_init_mcg_table(struct mlx4_dev *dev);
899 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
900 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
901 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
902 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
903 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
904 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
905 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
906 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
907 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
908 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
909 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
910 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
911 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
912 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
913 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
914 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
915 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
916 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
917 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
918 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
919 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
921 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
922 struct mlx4_vhcr *vhcr,
923 struct mlx4_cmd_mailbox *inbox,
924 struct mlx4_cmd_mailbox *outbox,
925 struct mlx4_cmd_info *cmd);
926 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
927 struct mlx4_vhcr *vhcr,
928 struct mlx4_cmd_mailbox *inbox,
929 struct mlx4_cmd_mailbox *outbox,
930 struct mlx4_cmd_info *cmd);
931 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
932 struct mlx4_vhcr *vhcr,
933 struct mlx4_cmd_mailbox *inbox,
934 struct mlx4_cmd_mailbox *outbox,
935 struct mlx4_cmd_info *cmd);
936 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
937 struct mlx4_vhcr *vhcr,
938 struct mlx4_cmd_mailbox *inbox,
939 struct mlx4_cmd_mailbox *outbox,
940 struct mlx4_cmd_info *cmd);
941 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
942 struct mlx4_vhcr *vhcr,
943 struct mlx4_cmd_mailbox *inbox,
944 struct mlx4_cmd_mailbox *outbox,
945 struct mlx4_cmd_info *cmd);
946 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
947 struct mlx4_vhcr *vhcr,
948 struct mlx4_cmd_mailbox *inbox,
949 struct mlx4_cmd_mailbox *outbox,
950 struct mlx4_cmd_info *cmd);
951 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
952 struct mlx4_vhcr *vhcr,
953 struct mlx4_cmd_mailbox *inbox,
954 struct mlx4_cmd_mailbox *outbox,
955 struct mlx4_cmd_info *cmd);
956 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
958 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
959 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
960 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
961 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
962 int start_index, int npages, u64 *page_list);
963 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
964 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
965 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
966 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
968 void mlx4_start_catas_poll(struct mlx4_dev *dev);
969 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
970 void mlx4_catas_init(void);
971 int mlx4_restart_one(struct pci_dev *pdev);
972 int mlx4_register_device(struct mlx4_dev *dev);
973 void mlx4_unregister_device(struct mlx4_dev *dev);
974 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
975 unsigned long param);
978 struct mlx4_init_hca_param;
980 u64 mlx4_make_profile(struct mlx4_dev *dev,
981 struct mlx4_profile *request,
982 struct mlx4_dev_cap *dev_cap,
983 struct mlx4_init_hca_param *init_hca);
984 void mlx4_master_comm_channel(struct work_struct *work);
985 void mlx4_gen_slave_eqe(struct work_struct *work);
986 void mlx4_master_handle_slave_flr(struct work_struct *work);
988 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
989 struct mlx4_vhcr *vhcr,
990 struct mlx4_cmd_mailbox *inbox,
991 struct mlx4_cmd_mailbox *outbox,
992 struct mlx4_cmd_info *cmd);
993 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
994 struct mlx4_vhcr *vhcr,
995 struct mlx4_cmd_mailbox *inbox,
996 struct mlx4_cmd_mailbox *outbox,
997 struct mlx4_cmd_info *cmd);
998 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
999 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1000 struct mlx4_cmd_mailbox *outbox,
1001 struct mlx4_cmd_info *cmd);
1002 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1003 struct mlx4_vhcr *vhcr,
1004 struct mlx4_cmd_mailbox *inbox,
1005 struct mlx4_cmd_mailbox *outbox,
1006 struct mlx4_cmd_info *cmd);
1007 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1008 struct mlx4_vhcr *vhcr,
1009 struct mlx4_cmd_mailbox *inbox,
1010 struct mlx4_cmd_mailbox *outbox,
1011 struct mlx4_cmd_info *cmd);
1012 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1013 struct mlx4_vhcr *vhcr,
1014 struct mlx4_cmd_mailbox *inbox,
1015 struct mlx4_cmd_mailbox *outbox,
1016 struct mlx4_cmd_info *cmd);
1017 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1018 struct mlx4_vhcr *vhcr,
1019 struct mlx4_cmd_mailbox *inbox,
1020 struct mlx4_cmd_mailbox *outbox,
1021 struct mlx4_cmd_info *cmd);
1022 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
1027 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1028 struct mlx4_vhcr *vhcr,
1029 struct mlx4_cmd_mailbox *inbox,
1030 struct mlx4_cmd_mailbox *outbox,
1031 struct mlx4_cmd_info *cmd);
1032 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd);
1037 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1038 struct mlx4_vhcr *vhcr,
1039 struct mlx4_cmd_mailbox *inbox,
1040 struct mlx4_cmd_mailbox *outbox,
1041 struct mlx4_cmd_info *cmd);
1042 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1043 struct mlx4_vhcr *vhcr,
1044 struct mlx4_cmd_mailbox *inbox,
1045 struct mlx4_cmd_mailbox *outbox,
1046 struct mlx4_cmd_info *cmd);
1047 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1048 struct mlx4_vhcr *vhcr,
1049 struct mlx4_cmd_mailbox *inbox,
1050 struct mlx4_cmd_mailbox *outbox,
1051 struct mlx4_cmd_info *cmd);
1052 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr,
1054 struct mlx4_cmd_mailbox *inbox,
1055 struct mlx4_cmd_mailbox *outbox,
1056 struct mlx4_cmd_info *cmd);
1057 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
1062 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1063 struct mlx4_vhcr *vhcr,
1064 struct mlx4_cmd_mailbox *inbox,
1065 struct mlx4_cmd_mailbox *outbox,
1066 struct mlx4_cmd_info *cmd);
1067 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1068 struct mlx4_vhcr *vhcr,
1069 struct mlx4_cmd_mailbox *inbox,
1070 struct mlx4_cmd_mailbox *outbox,
1071 struct mlx4_cmd_info *cmd);
1072 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1073 struct mlx4_vhcr *vhcr,
1074 struct mlx4_cmd_mailbox *inbox,
1075 struct mlx4_cmd_mailbox *outbox,
1076 struct mlx4_cmd_info *cmd);
1077 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1078 struct mlx4_vhcr *vhcr,
1079 struct mlx4_cmd_mailbox *inbox,
1080 struct mlx4_cmd_mailbox *outbox,
1081 struct mlx4_cmd_info *cmd);
1082 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1083 struct mlx4_vhcr *vhcr,
1084 struct mlx4_cmd_mailbox *inbox,
1085 struct mlx4_cmd_mailbox *outbox,
1086 struct mlx4_cmd_info *cmd);
1087 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1088 struct mlx4_vhcr *vhcr,
1089 struct mlx4_cmd_mailbox *inbox,
1090 struct mlx4_cmd_mailbox *outbox,
1091 struct mlx4_cmd_info *cmd);
1092 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1093 struct mlx4_vhcr *vhcr,
1094 struct mlx4_cmd_mailbox *inbox,
1095 struct mlx4_cmd_mailbox *outbox,
1096 struct mlx4_cmd_info *cmd);
1097 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1098 struct mlx4_vhcr *vhcr,
1099 struct mlx4_cmd_mailbox *inbox,
1100 struct mlx4_cmd_mailbox *outbox,
1101 struct mlx4_cmd_info *cmd);
1102 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1103 struct mlx4_vhcr *vhcr,
1104 struct mlx4_cmd_mailbox *inbox,
1105 struct mlx4_cmd_mailbox *outbox,
1106 struct mlx4_cmd_info *cmd);
1107 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1108 struct mlx4_vhcr *vhcr,
1109 struct mlx4_cmd_mailbox *inbox,
1110 struct mlx4_cmd_mailbox *outbox,
1111 struct mlx4_cmd_info *cmd);
1112 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1113 struct mlx4_vhcr *vhcr,
1114 struct mlx4_cmd_mailbox *inbox,
1115 struct mlx4_cmd_mailbox *outbox,
1116 struct mlx4_cmd_info *cmd);
1117 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1118 struct mlx4_vhcr *vhcr,
1119 struct mlx4_cmd_mailbox *inbox,
1120 struct mlx4_cmd_mailbox *outbox,
1121 struct mlx4_cmd_info *cmd);
1123 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1125 int mlx4_cmd_init(struct mlx4_dev *dev);
1126 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1127 int mlx4_multi_func_init(struct mlx4_dev *dev);
1128 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1129 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1130 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1131 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1133 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1134 unsigned long timeout);
1136 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1137 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1139 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1141 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1143 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1145 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1146 enum mlx4_port_type *type);
1147 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1148 enum mlx4_port_type *stype,
1149 enum mlx4_port_type *defaults);
1150 void mlx4_start_sense(struct mlx4_dev *dev);
1151 void mlx4_stop_sense(struct mlx4_dev *dev);
1152 void mlx4_sense_init(struct mlx4_dev *dev);
1153 int mlx4_check_port_params(struct mlx4_dev *dev,
1154 enum mlx4_port_type *port_type);
1155 int mlx4_change_port_types(struct mlx4_dev *dev,
1156 enum mlx4_port_type *port_types);
1158 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1159 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1160 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
1161 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1163 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1164 /* resource tracker functions*/
1165 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1166 enum mlx4_resource resource_type,
1167 u64 resource_id, int *slave);
1168 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1169 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1171 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1172 enum mlx4_res_tracker_free_type type);
1174 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1175 struct mlx4_vhcr *vhcr,
1176 struct mlx4_cmd_mailbox *inbox,
1177 struct mlx4_cmd_mailbox *outbox,
1178 struct mlx4_cmd_info *cmd);
1179 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1180 struct mlx4_vhcr *vhcr,
1181 struct mlx4_cmd_mailbox *inbox,
1182 struct mlx4_cmd_mailbox *outbox,
1183 struct mlx4_cmd_info *cmd);
1184 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1185 struct mlx4_vhcr *vhcr,
1186 struct mlx4_cmd_mailbox *inbox,
1187 struct mlx4_cmd_mailbox *outbox,
1188 struct mlx4_cmd_info *cmd);
1189 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1190 struct mlx4_vhcr *vhcr,
1191 struct mlx4_cmd_mailbox *inbox,
1192 struct mlx4_cmd_mailbox *outbox,
1193 struct mlx4_cmd_info *cmd);
1194 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1195 struct mlx4_vhcr *vhcr,
1196 struct mlx4_cmd_mailbox *inbox,
1197 struct mlx4_cmd_mailbox *outbox,
1198 struct mlx4_cmd_info *cmd);
1199 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1200 struct mlx4_vhcr *vhcr,
1201 struct mlx4_cmd_mailbox *inbox,
1202 struct mlx4_cmd_mailbox *outbox,
1203 struct mlx4_cmd_info *cmd);
1204 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1206 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1207 int *gid_tbl_len, int *pkey_tbl_len);
1209 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1210 struct mlx4_vhcr *vhcr,
1211 struct mlx4_cmd_mailbox *inbox,
1212 struct mlx4_cmd_mailbox *outbox,
1213 struct mlx4_cmd_info *cmd);
1215 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1216 struct mlx4_vhcr *vhcr,
1217 struct mlx4_cmd_mailbox *inbox,
1218 struct mlx4_cmd_mailbox *outbox,
1219 struct mlx4_cmd_info *cmd);
1220 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1221 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1222 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1223 int block_mcast_loopback, enum mlx4_protocol prot,
1224 enum mlx4_steer_type steer);
1225 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1226 u8 gid[16], u8 port,
1227 int block_mcast_loopback,
1228 enum mlx4_protocol prot, u64 *reg_id);
1229 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1230 struct mlx4_vhcr *vhcr,
1231 struct mlx4_cmd_mailbox *inbox,
1232 struct mlx4_cmd_mailbox *outbox,
1233 struct mlx4_cmd_info *cmd);
1234 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1235 struct mlx4_vhcr *vhcr,
1236 struct mlx4_cmd_mailbox *inbox,
1237 struct mlx4_cmd_mailbox *outbox,
1238 struct mlx4_cmd_info *cmd);
1239 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1240 int port, void *buf);
1241 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1242 struct mlx4_cmd_mailbox *outbox);
1243 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1244 struct mlx4_vhcr *vhcr,
1245 struct mlx4_cmd_mailbox *inbox,
1246 struct mlx4_cmd_mailbox *outbox,
1247 struct mlx4_cmd_info *cmd);
1248 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1249 struct mlx4_vhcr *vhcr,
1250 struct mlx4_cmd_mailbox *inbox,
1251 struct mlx4_cmd_mailbox *outbox,
1252 struct mlx4_cmd_info *cmd);
1253 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1254 struct mlx4_vhcr *vhcr,
1255 struct mlx4_cmd_mailbox *inbox,
1256 struct mlx4_cmd_mailbox *outbox,
1257 struct mlx4_cmd_info *cmd);
1258 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1259 struct mlx4_vhcr *vhcr,
1260 struct mlx4_cmd_mailbox *inbox,
1261 struct mlx4_cmd_mailbox *outbox,
1262 struct mlx4_cmd_info *cmd);
1263 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1264 struct mlx4_vhcr *vhcr,
1265 struct mlx4_cmd_mailbox *inbox,
1266 struct mlx4_cmd_mailbox *outbox,
1267 struct mlx4_cmd_info *cmd);
1269 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1270 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1272 static inline void set_param_l(u64 *arg, u32 val)
1274 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1277 static inline void set_param_h(u64 *arg, u32 val)
1279 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1282 static inline u32 get_param_l(u64 *arg)
1284 return (u32) (*arg & 0xffffffff);
1287 static inline u32 get_param_h(u64 *arg)
1289 return (u32)(*arg >> 32);
1292 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1294 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1297 #define NOT_MASKED_PD_BITS 17