2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/if_vlan.h>
36 #include <linux/export.h>
38 #include <linux/mlx4/cmd.h>
42 #define MLX4_MAC_VALID (1ull << 63)
44 #define MLX4_VLAN_VALID (1u << 31)
45 #define MLX4_VLAN_MASK 0xfff
47 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
48 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
49 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
50 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
52 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
56 mutex_init(&table->mutex);
57 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
58 table->entries[i] = 0;
61 table->max = 1 << dev->caps.log_num_macs;
65 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
69 mutex_init(&table->mutex);
70 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
71 table->entries[i] = 0;
74 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
78 static int validate_index(struct mlx4_dev *dev,
79 struct mlx4_mac_table *table, int index)
83 if (index < 0 || index >= table->max || !table->entries[index]) {
84 mlx4_warn(dev, "No valid Mac entry for the given index\n");
90 static int find_index(struct mlx4_dev *dev,
91 struct mlx4_mac_table *table, u64 mac)
95 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
96 if ((mac & MLX4_MAC_MASK) ==
97 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
104 static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
107 struct mlx4_cmd_mailbox *mailbox;
111 mailbox = mlx4_alloc_cmd_mailbox(dev);
113 return PTR_ERR(mailbox);
115 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
117 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
119 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
120 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
122 mlx4_free_cmd_mailbox(dev, mailbox);
126 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
128 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
129 struct mlx4_mac_table *table = &info->mac_table;
133 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
134 (unsigned long long) mac, port);
136 mutex_lock(&table->mutex);
137 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
138 if (free < 0 && !table->entries[i]) {
143 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
144 /* MAC already registered, Must not have duplicates */
150 mlx4_dbg(dev, "Free MAC index is %d\n", free);
152 if (table->total == table->max) {
153 /* No free mac entries */
158 /* Register new MAC */
159 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
161 err = mlx4_set_port_mac_table(dev, port, table->entries);
163 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
164 (unsigned long long) mac);
165 table->entries[free] = 0;
172 mutex_unlock(&table->mutex);
175 EXPORT_SYMBOL_GPL(__mlx4_register_mac);
177 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
182 if (mlx4_is_mfunc(dev)) {
183 set_param_l(&out_param, port);
184 err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
185 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
186 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
190 return get_param_l(&out_param);
192 return __mlx4_register_mac(dev, port, mac);
194 EXPORT_SYMBOL_GPL(mlx4_register_mac);
196 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port)
198 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
199 (port - 1) * (1 << dev->caps.log_num_macs);
201 EXPORT_SYMBOL_GPL(mlx4_get_base_qpn);
203 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
205 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
206 struct mlx4_mac_table *table = &info->mac_table;
209 index = find_index(dev, table, mac);
211 mutex_lock(&table->mutex);
213 if (validate_index(dev, table, index))
216 table->entries[index] = 0;
217 mlx4_set_port_mac_table(dev, port, table->entries);
220 mutex_unlock(&table->mutex);
222 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
224 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
228 if (mlx4_is_mfunc(dev)) {
229 set_param_l(&out_param, port);
230 (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
231 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
232 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
235 __mlx4_unregister_mac(dev, port, mac);
238 EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
240 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
242 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
243 struct mlx4_mac_table *table = &info->mac_table;
244 int index = qpn - info->base_qpn;
247 /* CX1 doesn't support multi-functions */
248 mutex_lock(&table->mutex);
250 err = validate_index(dev, table, index);
254 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
256 err = mlx4_set_port_mac_table(dev, port, table->entries);
258 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
259 (unsigned long long) new_mac);
260 table->entries[index] = 0;
263 mutex_unlock(&table->mutex);
266 EXPORT_SYMBOL_GPL(__mlx4_replace_mac);
268 static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
271 struct mlx4_cmd_mailbox *mailbox;
275 mailbox = mlx4_alloc_cmd_mailbox(dev);
277 return PTR_ERR(mailbox);
279 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
280 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
281 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
282 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
284 mlx4_free_cmd_mailbox(dev, mailbox);
289 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
291 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
294 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
295 if (table->refs[i] &&
296 (vid == (MLX4_VLAN_MASK &
297 be32_to_cpu(table->entries[i])))) {
298 /* VLAN already registered, increase reference count */
306 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
308 static int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
311 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
315 mutex_lock(&table->mutex);
317 if (table->total == table->max) {
318 /* No free vlan entries */
323 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
324 if (free < 0 && (table->refs[i] == 0)) {
329 if (table->refs[i] &&
330 (vlan == (MLX4_VLAN_MASK &
331 be32_to_cpu(table->entries[i])))) {
332 /* Vlan already registered, increase references count */
344 /* Register new VLAN */
345 table->refs[free] = 1;
346 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
348 err = mlx4_set_port_vlan_table(dev, port, table->entries);
350 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
351 table->refs[free] = 0;
352 table->entries[free] = 0;
359 mutex_unlock(&table->mutex);
363 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
368 if (mlx4_is_mfunc(dev)) {
369 set_param_l(&out_param, port);
370 err = mlx4_cmd_imm(dev, vlan, &out_param, RES_VLAN,
371 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
372 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
374 *index = get_param_l(&out_param);
378 return __mlx4_register_vlan(dev, port, vlan, index);
380 EXPORT_SYMBOL_GPL(mlx4_register_vlan);
382 static void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
384 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
386 if (index < MLX4_VLAN_REGULAR) {
387 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
391 mutex_lock(&table->mutex);
392 if (!table->refs[index]) {
393 mlx4_warn(dev, "No vlan entry for index %d\n", index);
396 if (--table->refs[index]) {
397 mlx4_dbg(dev, "Have more references for index %d,"
398 "no need to modify vlan table\n", index);
401 table->entries[index] = 0;
402 mlx4_set_port_vlan_table(dev, port, table->entries);
405 mutex_unlock(&table->mutex);
408 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
413 if (mlx4_is_mfunc(dev)) {
414 set_param_l(&in_param, port);
415 err = mlx4_cmd(dev, in_param, RES_VLAN, RES_OP_RESERVE_AND_MAP,
416 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
419 mlx4_warn(dev, "Failed freeing vlan at index:%d\n",
424 __mlx4_unregister_vlan(dev, port, index);
426 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
428 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
430 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
434 inmailbox = mlx4_alloc_cmd_mailbox(dev);
435 if (IS_ERR(inmailbox))
436 return PTR_ERR(inmailbox);
438 outmailbox = mlx4_alloc_cmd_mailbox(dev);
439 if (IS_ERR(outmailbox)) {
440 mlx4_free_cmd_mailbox(dev, inmailbox);
441 return PTR_ERR(outmailbox);
444 inbuf = inmailbox->buf;
445 outbuf = outmailbox->buf;
446 memset(inbuf, 0, 256);
447 memset(outbuf, 0, 256);
452 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
453 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
455 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
456 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
459 *caps = *(__be32 *) (outbuf + 84);
460 mlx4_free_cmd_mailbox(dev, inmailbox);
461 mlx4_free_cmd_mailbox(dev, outmailbox);
465 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
466 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
468 struct mlx4_priv *priv = mlx4_priv(dev);
469 struct mlx4_port_info *port_info;
470 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
471 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
472 struct mlx4_set_port_rqp_calc_context *qpn_context;
473 struct mlx4_set_port_general_context *gen_context;
474 int reset_qkey_viols;
483 __be32 slave_cap_mask;
486 port = in_mod & 0xff;
487 in_modifier = in_mod >> 8;
489 port_info = &priv->port[port];
491 /* Slaves cannot perform SET_PORT operations except changing MTU */
493 if (slave != dev->caps.function &&
494 in_modifier != MLX4_SET_PORT_GENERAL) {
495 mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
499 switch (in_modifier) {
500 case MLX4_SET_PORT_RQP_CALC:
501 qpn_context = inbox->buf;
502 qpn_context->base_qpn =
503 cpu_to_be32(port_info->base_qpn);
504 qpn_context->n_mac = 0x7;
505 promisc = be32_to_cpu(qpn_context->promisc) >>
506 SET_PORT_PROMISC_SHIFT;
507 qpn_context->promisc = cpu_to_be32(
508 promisc << SET_PORT_PROMISC_SHIFT |
509 port_info->base_qpn);
510 promisc = be32_to_cpu(qpn_context->mcast) >>
511 SET_PORT_MC_PROMISC_SHIFT;
512 qpn_context->mcast = cpu_to_be32(
513 promisc << SET_PORT_MC_PROMISC_SHIFT |
514 port_info->base_qpn);
516 case MLX4_SET_PORT_GENERAL:
517 gen_context = inbox->buf;
518 /* Mtu is configured as the max MTU among all the
519 * the functions on the port. */
520 mtu = be16_to_cpu(gen_context->mtu);
521 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] +
522 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
523 prev_mtu = slave_st->mtu[port];
524 slave_st->mtu[port] = mtu;
525 if (mtu > master->max_mtu[port])
526 master->max_mtu[port] = mtu;
527 if (mtu < prev_mtu && prev_mtu ==
528 master->max_mtu[port]) {
529 slave_st->mtu[port] = mtu;
530 master->max_mtu[port] = mtu;
531 for (i = 0; i < dev->num_slaves; i++) {
532 master->max_mtu[port] =
533 max(master->max_mtu[port],
534 master->slave_state[i].mtu[port]);
538 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
541 return mlx4_cmd(dev, inbox->dma, in_mod, op_mod,
542 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
546 /* For IB, we only consider:
547 * - The capability mask, which is set to the aggregate of all
548 * slave function capabilities
549 * - The QKey violatin counter - reset according to each request.
552 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
553 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
554 new_cap_mask = ((__be32 *) inbox->buf)[2];
556 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
557 new_cap_mask = ((__be32 *) inbox->buf)[1];
560 /* slave may not set the IS_SM capability for the port */
561 if (slave != mlx4_master_func_num(dev) &&
562 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM))
565 /* No DEV_MGMT in multifunc mode */
566 if (mlx4_is_mfunc(dev) &&
567 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP))
572 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
573 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
574 for (i = 0; i < dev->num_slaves; i++)
576 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
578 /* only clear mailbox for guests. Master may be setting
579 * MTU or PKEY table size
581 if (slave != dev->caps.function)
582 memset(inbox->buf, 0, 256);
583 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
584 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
585 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
587 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
588 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
591 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
592 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
594 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
599 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
600 struct mlx4_vhcr *vhcr,
601 struct mlx4_cmd_mailbox *inbox,
602 struct mlx4_cmd_mailbox *outbox,
603 struct mlx4_cmd_info *cmd)
605 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
606 vhcr->op_modifier, inbox);
609 /* bit locations for set port command with zero op modifier */
611 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
612 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
613 MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
614 MLX4_CHANGE_PORT_VL_CAP = 21,
615 MLX4_CHANGE_PORT_MTU_CAP = 22,
618 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
620 struct mlx4_cmd_mailbox *mailbox;
621 int err, vl_cap, pkey_tbl_flag = 0;
623 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
626 mailbox = mlx4_alloc_cmd_mailbox(dev);
628 return PTR_ERR(mailbox);
630 memset(mailbox->buf, 0, 256);
632 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
634 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
636 ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
639 /* IB VL CAP enum isn't used by the firmware, just numerical values */
640 for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) {
641 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
642 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
643 (1 << MLX4_CHANGE_PORT_VL_CAP) |
644 (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
645 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
646 (vl_cap << MLX4_SET_PORT_VL_CAP));
647 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
648 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
653 mlx4_free_cmd_mailbox(dev, mailbox);
657 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
658 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
660 struct mlx4_cmd_mailbox *mailbox;
661 struct mlx4_set_port_general_context *context;
665 mailbox = mlx4_alloc_cmd_mailbox(dev);
667 return PTR_ERR(mailbox);
668 context = mailbox->buf;
669 memset(context, 0, sizeof *context);
671 context->flags = SET_PORT_GEN_ALL_VALID;
672 context->mtu = cpu_to_be16(mtu);
673 context->pptx = (pptx * (!pfctx)) << 7;
674 context->pfctx = pfctx;
675 context->pprx = (pprx * (!pfcrx)) << 7;
676 context->pfcrx = pfcrx;
678 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
679 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
680 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
682 mlx4_free_cmd_mailbox(dev, mailbox);
685 EXPORT_SYMBOL(mlx4_SET_PORT_general);
687 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
690 struct mlx4_cmd_mailbox *mailbox;
691 struct mlx4_set_port_rqp_calc_context *context;
694 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
695 MCAST_DIRECT : MCAST_DEFAULT;
697 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
700 mailbox = mlx4_alloc_cmd_mailbox(dev);
702 return PTR_ERR(mailbox);
703 context = mailbox->buf;
704 memset(context, 0, sizeof *context);
706 context->base_qpn = cpu_to_be32(base_qpn);
707 context->n_mac = dev->caps.log_num_macs;
708 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
710 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
712 context->intra_no_vlan = 0;
713 context->no_vlan = MLX4_NO_VLAN_IDX;
714 context->intra_vlan_miss = 0;
715 context->vlan_miss = MLX4_VLAN_MISS_IDX;
717 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
718 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
719 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
721 mlx4_free_cmd_mailbox(dev, mailbox);
724 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
726 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
728 struct mlx4_cmd_mailbox *mailbox;
729 struct mlx4_set_port_prio2tc_context *context;
734 mailbox = mlx4_alloc_cmd_mailbox(dev);
736 return PTR_ERR(mailbox);
737 context = mailbox->buf;
738 memset(context, 0, sizeof *context);
740 for (i = 0; i < MLX4_NUM_UP; i += 2)
741 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
743 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
744 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
745 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
747 mlx4_free_cmd_mailbox(dev, mailbox);
750 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
752 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
753 u8 *pg, u16 *ratelimit)
755 struct mlx4_cmd_mailbox *mailbox;
756 struct mlx4_set_port_scheduler_context *context;
761 mailbox = mlx4_alloc_cmd_mailbox(dev);
763 return PTR_ERR(mailbox);
764 context = mailbox->buf;
765 memset(context, 0, sizeof *context);
767 for (i = 0; i < MLX4_NUM_TC; i++) {
768 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
769 u16 r = ratelimit && ratelimit[i] ? ratelimit[i] :
770 MLX4_RATELIMIT_DEFAULT;
772 tc->pg = htons(pg[i]);
773 tc->bw_precentage = htons(tc_tx_bw[i]);
775 tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS);
776 tc->max_bw_value = htons(r);
779 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
780 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
781 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
783 mlx4_free_cmd_mailbox(dev, mailbox);
786 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
788 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
789 struct mlx4_vhcr *vhcr,
790 struct mlx4_cmd_mailbox *inbox,
791 struct mlx4_cmd_mailbox *outbox,
792 struct mlx4_cmd_info *cmd)
799 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
800 u64 mac, u64 clear, u8 mode)
802 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
803 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
806 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
808 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
809 struct mlx4_vhcr *vhcr,
810 struct mlx4_cmd_mailbox *inbox,
811 struct mlx4_cmd_mailbox *outbox,
812 struct mlx4_cmd_info *cmd)
819 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
820 u32 in_mod, struct mlx4_cmd_mailbox *outbox)
822 return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
823 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
827 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
828 struct mlx4_vhcr *vhcr,
829 struct mlx4_cmd_mailbox *inbox,
830 struct mlx4_cmd_mailbox *outbox,
831 struct mlx4_cmd_info *cmd)
833 if (slave != dev->caps.function)
835 return mlx4_common_dump_eth_stats(dev, slave,
836 vhcr->in_modifier, outbox);
839 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap)
841 if (!mlx4_is_mfunc(dev)) {
846 *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK |
847 MLX4_STATS_TRAFFIC_DROPS_MASK |
848 MLX4_STATS_PORT_COUNTERS_MASK);
850 if (mlx4_is_master(dev))
851 *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK;
853 EXPORT_SYMBOL(mlx4_set_stats_bitmap);