2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
45 #include "mlx5_core.h"
59 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
60 MLX5_CMD_DATA_BLOCK_SIZE,
61 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
65 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
66 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
67 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
68 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
69 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
70 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
71 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
72 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
73 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
74 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
75 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
79 struct mlx5_cmd_msg *in,
80 struct mlx5_cmd_msg *out,
81 void *uout, int uout_size,
83 void *context, int page_queue)
85 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
86 struct mlx5_cmd_work_ent *ent;
88 ent = kzalloc(sizeof(*ent), alloc_flags);
90 return ERR_PTR(-ENOMEM);
95 ent->uout_size = uout_size;
97 ent->context = context;
99 ent->page_queue = page_queue;
104 static u8 alloc_token(struct mlx5_cmd *cmd)
108 spin_lock(&cmd->token_lock);
113 spin_unlock(&cmd->token_lock);
118 static int alloc_ent(struct mlx5_cmd *cmd)
123 spin_lock_irqsave(&cmd->alloc_lock, flags);
124 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
125 if (ret < cmd->max_reg_cmds)
126 clear_bit(ret, &cmd->bitmask);
127 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
129 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
132 static void free_ent(struct mlx5_cmd *cmd, int idx)
136 spin_lock_irqsave(&cmd->alloc_lock, flags);
137 set_bit(idx, &cmd->bitmask);
138 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
143 return cmd->cmd_buf + (idx << cmd->log_stride);
146 static u8 xor8_buf(void *buf, int len)
152 for (i = 0; i < len; i++)
158 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
160 if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
163 if (xor8_buf(block, sizeof(*block)) != 0xff)
169 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
172 block->token = token;
174 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
175 sizeof(block->data) - 2);
176 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
180 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
182 struct mlx5_cmd_mailbox *next = msg->next;
185 calc_block_sig(next->buf, token, csum);
190 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
192 ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
193 calc_chain_sig(ent->in, ent->token, csum);
194 calc_chain_sig(ent->out, ent->token, csum);
197 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
199 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
203 own = ent->lay->status_own;
204 if (!(own & CMD_OWNER_HW)) {
208 usleep_range(5000, 10000);
209 } while (time_before(jiffies, poll_end));
211 ent->ret = -ETIMEDOUT;
214 static void free_cmd(struct mlx5_cmd_work_ent *ent)
220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
222 struct mlx5_cmd_mailbox *next = ent->out->next;
226 sig = xor8_buf(ent->lay, sizeof(*ent->lay));
231 err = verify_block_sig(next->buf);
241 static void dump_buf(void *buf, int size, int data_only, int offset)
246 for (i = 0; i < size; i += 16) {
247 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
248 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
258 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
261 const char *mlx5_command_str(int command)
264 case MLX5_CMD_OP_QUERY_HCA_CAP:
265 return "QUERY_HCA_CAP";
267 case MLX5_CMD_OP_SET_HCA_CAP:
268 return "SET_HCA_CAP";
270 case MLX5_CMD_OP_QUERY_ADAPTER:
271 return "QUERY_ADAPTER";
273 case MLX5_CMD_OP_INIT_HCA:
276 case MLX5_CMD_OP_TEARDOWN_HCA:
277 return "TEARDOWN_HCA";
279 case MLX5_CMD_OP_ENABLE_HCA:
280 return "MLX5_CMD_OP_ENABLE_HCA";
282 case MLX5_CMD_OP_DISABLE_HCA:
283 return "MLX5_CMD_OP_DISABLE_HCA";
285 case MLX5_CMD_OP_QUERY_PAGES:
286 return "QUERY_PAGES";
288 case MLX5_CMD_OP_MANAGE_PAGES:
289 return "MANAGE_PAGES";
291 case MLX5_CMD_OP_CREATE_MKEY:
292 return "CREATE_MKEY";
294 case MLX5_CMD_OP_QUERY_MKEY:
297 case MLX5_CMD_OP_DESTROY_MKEY:
298 return "DESTROY_MKEY";
300 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
301 return "QUERY_SPECIAL_CONTEXTS";
303 case MLX5_CMD_OP_CREATE_EQ:
306 case MLX5_CMD_OP_DESTROY_EQ:
309 case MLX5_CMD_OP_QUERY_EQ:
312 case MLX5_CMD_OP_CREATE_CQ:
315 case MLX5_CMD_OP_DESTROY_CQ:
318 case MLX5_CMD_OP_QUERY_CQ:
321 case MLX5_CMD_OP_MODIFY_CQ:
324 case MLX5_CMD_OP_CREATE_QP:
327 case MLX5_CMD_OP_DESTROY_QP:
330 case MLX5_CMD_OP_RST2INIT_QP:
331 return "RST2INIT_QP";
333 case MLX5_CMD_OP_INIT2RTR_QP:
334 return "INIT2RTR_QP";
336 case MLX5_CMD_OP_RTR2RTS_QP:
339 case MLX5_CMD_OP_RTS2RTS_QP:
342 case MLX5_CMD_OP_SQERR2RTS_QP:
343 return "SQERR2RTS_QP";
345 case MLX5_CMD_OP_2ERR_QP:
348 case MLX5_CMD_OP_2RST_QP:
351 case MLX5_CMD_OP_QUERY_QP:
354 case MLX5_CMD_OP_MAD_IFC:
357 case MLX5_CMD_OP_INIT2INIT_QP:
358 return "INIT2INIT_QP";
360 case MLX5_CMD_OP_CREATE_PSV:
363 case MLX5_CMD_OP_DESTROY_PSV:
364 return "DESTROY_PSV";
366 case MLX5_CMD_OP_CREATE_SRQ:
369 case MLX5_CMD_OP_DESTROY_SRQ:
370 return "DESTROY_SRQ";
372 case MLX5_CMD_OP_QUERY_SRQ:
375 case MLX5_CMD_OP_ARM_RQ:
378 case MLX5_CMD_OP_CREATE_XRC_SRQ:
379 return "CREATE_XRC_SRQ";
381 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
382 return "DESTROY_XRC_SRQ";
384 case MLX5_CMD_OP_QUERY_XRC_SRQ:
385 return "QUERY_XRC_SRQ";
387 case MLX5_CMD_OP_ARM_XRC_SRQ:
388 return "ARM_XRC_SRQ";
390 case MLX5_CMD_OP_ALLOC_PD:
393 case MLX5_CMD_OP_DEALLOC_PD:
396 case MLX5_CMD_OP_ALLOC_UAR:
399 case MLX5_CMD_OP_DEALLOC_UAR:
400 return "DEALLOC_UAR";
402 case MLX5_CMD_OP_ATTACH_TO_MCG:
403 return "ATTACH_TO_MCG";
405 case MLX5_CMD_OP_DETTACH_FROM_MCG:
406 return "DETTACH_FROM_MCG";
408 case MLX5_CMD_OP_ALLOC_XRCD:
411 case MLX5_CMD_OP_DEALLOC_XRCD:
412 return "DEALLOC_XRCD";
414 case MLX5_CMD_OP_ACCESS_REG:
415 return "MLX5_CMD_OP_ACCESS_REG";
417 default: return "unknown command opcode";
421 static void dump_command(struct mlx5_core_dev *dev,
422 struct mlx5_cmd_work_ent *ent, int input)
424 u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
425 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
426 struct mlx5_cmd_mailbox *next = msg->next;
431 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
434 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
435 "dump command data %s(0x%x) %s\n",
436 mlx5_command_str(op), op,
437 input ? "INPUT" : "OUTPUT");
439 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
440 mlx5_command_str(op), op,
441 input ? "INPUT" : "OUTPUT");
445 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
446 offset += sizeof(ent->lay->in);
448 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
449 offset += sizeof(ent->lay->out);
452 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
453 offset += sizeof(*ent->lay);
456 while (next && offset < msg->len) {
458 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
459 dump_buf(next->buf, dump_len, 1, offset);
460 offset += MLX5_CMD_DATA_BLOCK_SIZE;
462 mlx5_core_dbg(dev, "command block:\n");
463 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
464 offset += sizeof(struct mlx5_cmd_prot_block);
473 static void cmd_work_handler(struct work_struct *work)
475 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
476 struct mlx5_cmd *cmd = ent->cmd;
477 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
478 struct mlx5_cmd_layout *lay;
479 struct semaphore *sem;
482 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
484 if (!ent->page_queue) {
485 ent->idx = alloc_ent(cmd);
487 mlx5_core_err(dev, "failed to allocate command entry\n");
492 ent->idx = cmd->max_reg_cmds;
493 spin_lock_irqsave(&cmd->alloc_lock, flags);
494 clear_bit(ent->idx, &cmd->bitmask);
495 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
498 ent->token = alloc_token(cmd);
499 cmd->ent_arr[ent->idx] = ent;
500 lay = get_inst(cmd, ent->idx);
502 memset(lay, 0, sizeof(*lay));
503 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
504 ent->op = be32_to_cpu(lay->in[0]) >> 16;
506 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
507 lay->inlen = cpu_to_be32(ent->in->len);
509 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
510 lay->outlen = cpu_to_be32(ent->out->len);
511 lay->type = MLX5_PCI_CMD_XPORT;
512 lay->token = ent->token;
513 lay->status_own = CMD_OWNER_HW;
514 set_signature(ent, !cmd->checksum_disabled);
515 dump_command(dev, ent, 1);
516 ent->ts1 = ktime_get_ns();
518 /* ring doorbell after the descriptor is valid */
519 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
521 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
523 /* if not in polling don't use ent after this point */
524 if (cmd->mode == CMD_MODE_POLLING) {
526 /* make sure we read the descriptor after ownership is SW */
528 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
532 static const char *deliv_status_to_str(u8 status)
535 case MLX5_CMD_DELIVERY_STAT_OK:
537 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
538 return "signature error";
539 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
540 return "token error";
541 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
542 return "bad block number";
543 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
544 return "output pointer not aligned to block size";
545 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
546 return "input pointer not aligned to block size";
547 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
548 return "firmware internal error";
549 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
550 return "command input length error";
551 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
552 return "command ouput length error";
553 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
554 return "reserved fields not cleared";
555 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
556 return "bad command descriptor type";
558 return "unknown status code";
562 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
564 struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
566 return be16_to_cpu(hdr->opcode);
569 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
571 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
572 struct mlx5_cmd *cmd = &dev->cmd;
575 if (cmd->mode == CMD_MODE_POLLING) {
576 wait_for_completion(&ent->done);
579 if (!wait_for_completion_timeout(&ent->done, timeout))
584 if (err == -ETIMEDOUT) {
585 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
586 mlx5_command_str(msg_to_opcode(ent->in)),
587 msg_to_opcode(ent->in));
589 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
590 err, deliv_status_to_str(ent->status), ent->status);
596 * 1. Callback functions may not sleep
597 * 2. page queue commands do not support asynchrous completion
599 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
600 struct mlx5_cmd_msg *out, void *uout, int uout_size,
601 mlx5_cmd_cbk_t callback,
602 void *context, int page_queue, u8 *status)
604 struct mlx5_cmd *cmd = &dev->cmd;
605 struct mlx5_cmd_work_ent *ent;
606 struct mlx5_cmd_stats *stats;
611 if (callback && page_queue)
614 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
620 init_completion(&ent->done);
622 INIT_WORK(&ent->work, cmd_work_handler);
624 cmd_work_handler(&ent->work);
625 } else if (!queue_work(cmd->wq, &ent->work)) {
626 mlx5_core_warn(dev, "failed to queue work\n");
632 err = wait_func(dev, ent);
633 if (err == -ETIMEDOUT)
636 ds = ent->ts2 - ent->ts1;
637 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
638 if (op < ARRAY_SIZE(cmd->stats)) {
639 stats = &cmd->stats[op];
640 spin_lock_irq(&stats->lock);
643 spin_unlock_irq(&stats->lock);
645 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
646 "fw exec time for %s is %lld nsec\n",
647 mlx5_command_str(op), ds);
648 *status = ent->status;
660 static ssize_t dbg_write(struct file *filp, const char __user *buf,
661 size_t count, loff_t *pos)
663 struct mlx5_core_dev *dev = filp->private_data;
664 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
668 if (!dbg->in_msg || !dbg->out_msg)
671 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
674 lbuf[sizeof(lbuf) - 1] = 0;
676 if (strcmp(lbuf, "go"))
679 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
681 return err ? err : count;
685 static const struct file_operations fops = {
686 .owner = THIS_MODULE,
691 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
693 struct mlx5_cmd_prot_block *block;
694 struct mlx5_cmd_mailbox *next;
700 copy = min_t(int, size, sizeof(to->first.data));
701 memcpy(to->first.data, from, copy);
712 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
714 memcpy(block->data, from, copy);
723 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
725 struct mlx5_cmd_prot_block *block;
726 struct mlx5_cmd_mailbox *next;
732 copy = min_t(int, size, sizeof(from->first.data));
733 memcpy(to, from->first.data, copy);
744 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
747 memcpy(to, block->data, copy);
756 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
759 struct mlx5_cmd_mailbox *mailbox;
761 mailbox = kmalloc(sizeof(*mailbox), flags);
763 return ERR_PTR(-ENOMEM);
765 mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
768 mlx5_core_dbg(dev, "failed allocation\n");
770 return ERR_PTR(-ENOMEM);
772 memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
773 mailbox->next = NULL;
778 static void free_cmd_box(struct mlx5_core_dev *dev,
779 struct mlx5_cmd_mailbox *mailbox)
781 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
785 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
786 gfp_t flags, int size)
788 struct mlx5_cmd_mailbox *tmp, *head = NULL;
789 struct mlx5_cmd_prot_block *block;
790 struct mlx5_cmd_msg *msg;
796 msg = kzalloc(sizeof(*msg), flags);
798 return ERR_PTR(-ENOMEM);
800 blen = size - min_t(int, sizeof(msg->first.data), size);
801 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
803 for (i = 0; i < n; i++) {
804 tmp = alloc_cmd_box(dev, flags);
806 mlx5_core_warn(dev, "failed allocating block\n");
813 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
814 block->block_num = cpu_to_be32(n - i - 1);
824 free_cmd_box(dev, head);
832 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
833 struct mlx5_cmd_msg *msg)
835 struct mlx5_cmd_mailbox *head = msg->next;
836 struct mlx5_cmd_mailbox *next;
840 free_cmd_box(dev, head);
846 static ssize_t data_write(struct file *filp, const char __user *buf,
847 size_t count, loff_t *pos)
849 struct mlx5_core_dev *dev = filp->private_data;
850 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
861 ptr = kzalloc(count, GFP_KERNEL);
865 if (copy_from_user(ptr, buf, count)) {
881 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
884 struct mlx5_core_dev *dev = filp->private_data;
885 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
894 copy = min_t(int, count, dbg->outlen);
895 if (copy_to_user(buf, dbg->out_msg, copy))
903 static const struct file_operations dfops = {
904 .owner = THIS_MODULE,
910 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
913 struct mlx5_core_dev *dev = filp->private_data;
914 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
921 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
925 if (copy_to_user(buf, &outlen, err))
933 static ssize_t outlen_write(struct file *filp, const char __user *buf,
934 size_t count, loff_t *pos)
936 struct mlx5_core_dev *dev = filp->private_data;
937 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
943 if (*pos != 0 || count > 6)
950 if (copy_from_user(outlen_str, buf, count))
955 err = sscanf(outlen_str, "%d", &outlen);
959 ptr = kzalloc(outlen, GFP_KERNEL);
964 dbg->outlen = outlen;
971 static const struct file_operations olfops = {
972 .owner = THIS_MODULE,
974 .write = outlen_write,
978 static void set_wqname(struct mlx5_core_dev *dev)
980 struct mlx5_cmd *cmd = &dev->cmd;
982 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
983 dev_name(&dev->pdev->dev));
986 static void clean_debug_files(struct mlx5_core_dev *dev)
988 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
990 if (!mlx5_debugfs_root)
993 mlx5_cmdif_debugfs_cleanup(dev);
994 debugfs_remove_recursive(dbg->dbg_root);
997 static int create_debugfs_files(struct mlx5_core_dev *dev)
999 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1002 if (!mlx5_debugfs_root)
1005 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1009 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1014 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1019 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1021 if (!dbg->dbg_outlen)
1024 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1026 if (!dbg->dbg_status)
1029 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1033 mlx5_cmdif_debugfs_init(dev);
1038 clean_debug_files(dev);
1042 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1044 struct mlx5_cmd *cmd = &dev->cmd;
1047 for (i = 0; i < cmd->max_reg_cmds; i++)
1050 down(&cmd->pages_sem);
1052 flush_workqueue(cmd->wq);
1054 cmd->mode = CMD_MODE_EVENTS;
1056 up(&cmd->pages_sem);
1057 for (i = 0; i < cmd->max_reg_cmds; i++)
1061 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1063 struct mlx5_cmd *cmd = &dev->cmd;
1066 for (i = 0; i < cmd->max_reg_cmds; i++)
1069 down(&cmd->pages_sem);
1071 flush_workqueue(cmd->wq);
1072 cmd->mode = CMD_MODE_POLLING;
1074 up(&cmd->pages_sem);
1075 for (i = 0; i < cmd->max_reg_cmds; i++)
1079 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1081 unsigned long flags;
1084 spin_lock_irqsave(&msg->cache->lock, flags);
1085 list_add_tail(&msg->list, &msg->cache->head);
1086 spin_unlock_irqrestore(&msg->cache->lock, flags);
1088 mlx5_free_cmd_msg(dev, msg);
1092 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1094 struct mlx5_cmd *cmd = &dev->cmd;
1095 struct mlx5_cmd_work_ent *ent;
1096 mlx5_cmd_cbk_t callback;
1101 struct mlx5_cmd_stats *stats;
1102 unsigned long flags;
1103 unsigned long vector;
1105 /* there can be at most 32 command queues */
1106 vector = vec & 0xffffffff;
1107 for (i = 0; i < (1 << cmd->log_sz); i++) {
1108 if (test_bit(i, &vector)) {
1109 struct semaphore *sem;
1111 ent = cmd->ent_arr[i];
1112 if (ent->page_queue)
1113 sem = &cmd->pages_sem;
1116 ent->ts2 = ktime_get_ns();
1117 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1118 dump_command(dev, ent, 0);
1120 if (!cmd->checksum_disabled)
1121 ent->ret = verify_signature(ent);
1124 if (vec & MLX5_TRIGGERED_CMD_COMP)
1125 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1127 ent->status = ent->lay->status_own >> 1;
1129 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1130 ent->ret, deliv_status_to_str(ent->status), ent->status);
1132 free_ent(cmd, ent->idx);
1134 if (ent->callback) {
1135 ds = ent->ts2 - ent->ts1;
1136 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1137 stats = &cmd->stats[ent->op];
1138 spin_lock_irqsave(&stats->lock, flags);
1141 spin_unlock_irqrestore(&stats->lock, flags);
1144 callback = ent->callback;
1145 context = ent->context;
1148 err = mlx5_copy_from_msg(ent->uout,
1152 mlx5_free_cmd_msg(dev, ent->out);
1153 free_msg(dev, ent->in);
1155 err = err ? err : ent->status;
1157 callback(err, context);
1159 complete(&ent->done);
1165 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1167 static int status_to_err(u8 status)
1169 return status ? -1 : 0; /* TBD more meaningful codes */
1172 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1175 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1176 struct mlx5_cmd *cmd = &dev->cmd;
1177 struct cache_ent *ent = NULL;
1179 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1180 ent = &cmd->cache.large;
1181 else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1182 ent = &cmd->cache.med;
1185 spin_lock_irq(&ent->lock);
1186 if (!list_empty(&ent->head)) {
1187 msg = list_entry(ent->head.next, typeof(*msg), list);
1188 /* For cached lists, we must explicitly state what is
1192 list_del(&msg->list);
1194 spin_unlock_irq(&ent->lock);
1198 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1203 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1205 return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1208 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1209 int out_size, mlx5_cmd_cbk_t callback, void *context)
1211 struct mlx5_cmd_msg *inb;
1212 struct mlx5_cmd_msg *outb;
1218 pages_queue = is_manage_pages(in);
1219 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1221 inb = alloc_msg(dev, in_size, gfp);
1227 err = mlx5_copy_to_msg(inb, in, in_size);
1229 mlx5_core_warn(dev, "err %d\n", err);
1233 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1235 err = PTR_ERR(outb);
1239 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1240 pages_queue, &status);
1244 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1246 err = status_to_err(status);
1251 err = mlx5_copy_from_msg(out, outb, out_size);
1255 mlx5_free_cmd_msg(dev, outb);
1263 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1266 return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1268 EXPORT_SYMBOL(mlx5_cmd_exec);
1270 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1271 void *out, int out_size, mlx5_cmd_cbk_t callback,
1274 return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1276 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1278 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1280 struct mlx5_cmd *cmd = &dev->cmd;
1281 struct mlx5_cmd_msg *msg;
1282 struct mlx5_cmd_msg *n;
1284 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1285 list_del(&msg->list);
1286 mlx5_free_cmd_msg(dev, msg);
1289 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1290 list_del(&msg->list);
1291 mlx5_free_cmd_msg(dev, msg);
1295 static int create_msg_cache(struct mlx5_core_dev *dev)
1297 struct mlx5_cmd *cmd = &dev->cmd;
1298 struct mlx5_cmd_msg *msg;
1302 spin_lock_init(&cmd->cache.large.lock);
1303 INIT_LIST_HEAD(&cmd->cache.large.head);
1304 spin_lock_init(&cmd->cache.med.lock);
1305 INIT_LIST_HEAD(&cmd->cache.med.head);
1307 for (i = 0; i < NUM_LONG_LISTS; i++) {
1308 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1313 msg->cache = &cmd->cache.large;
1314 list_add_tail(&msg->list, &cmd->cache.large.head);
1317 for (i = 0; i < NUM_MED_LISTS; i++) {
1318 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1323 msg->cache = &cmd->cache.med;
1324 list_add_tail(&msg->list, &cmd->cache.med.head);
1330 destroy_msg_cache(dev);
1334 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1336 struct device *ddev = &dev->pdev->dev;
1338 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1339 &cmd->alloc_dma, GFP_KERNEL);
1340 if (!cmd->cmd_alloc_buf)
1343 /* make sure it is aligned to 4K */
1344 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1345 cmd->cmd_buf = cmd->cmd_alloc_buf;
1346 cmd->dma = cmd->alloc_dma;
1347 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1351 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1353 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1354 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1355 &cmd->alloc_dma, GFP_KERNEL);
1356 if (!cmd->cmd_alloc_buf)
1359 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1360 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1361 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1365 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1367 struct device *ddev = &dev->pdev->dev;
1369 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1373 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1375 int size = sizeof(struct mlx5_cmd_prot_block);
1376 int align = roundup_pow_of_two(size);
1377 struct mlx5_cmd *cmd = &dev->cmd;
1383 memset(cmd, 0, sizeof(*cmd));
1384 cmd_if_rev = cmdif_rev(dev);
1385 if (cmd_if_rev != CMD_IF_REV) {
1386 dev_err(&dev->pdev->dev,
1387 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1388 CMD_IF_REV, cmd_if_rev);
1392 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1396 err = alloc_cmd_page(dev, cmd);
1400 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1401 cmd->log_sz = cmd_l >> 4 & 0xf;
1402 cmd->log_stride = cmd_l & 0xf;
1403 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1404 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1410 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1411 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1416 cmd->checksum_disabled = 1;
1417 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1418 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1420 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1421 if (cmd->cmdif_rev > CMD_IF_REV) {
1422 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1423 CMD_IF_REV, cmd->cmdif_rev);
1428 spin_lock_init(&cmd->alloc_lock);
1429 spin_lock_init(&cmd->token_lock);
1430 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1431 spin_lock_init(&cmd->stats[i].lock);
1433 sema_init(&cmd->sem, cmd->max_reg_cmds);
1434 sema_init(&cmd->pages_sem, 1);
1436 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1437 cmd_l = (u32)(cmd->dma);
1438 if (cmd_l & 0xfff) {
1439 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1444 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1445 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1447 /* Make sure firmware sees the complete address before we proceed */
1450 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1452 cmd->mode = CMD_MODE_POLLING;
1454 err = create_msg_cache(dev);
1456 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1461 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1463 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1468 err = create_debugfs_files(dev);
1477 destroy_workqueue(cmd->wq);
1480 destroy_msg_cache(dev);
1483 free_cmd_page(dev, cmd);
1486 pci_pool_destroy(cmd->pool);
1490 EXPORT_SYMBOL(mlx5_cmd_init);
1492 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1494 struct mlx5_cmd *cmd = &dev->cmd;
1496 clean_debug_files(dev);
1497 destroy_workqueue(cmd->wq);
1498 destroy_msg_cache(dev);
1499 free_cmd_page(dev, cmd);
1500 pci_pool_destroy(cmd->pool);
1502 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1504 static const char *cmd_status_str(u8 status)
1507 case MLX5_CMD_STAT_OK:
1509 case MLX5_CMD_STAT_INT_ERR:
1510 return "internal error";
1511 case MLX5_CMD_STAT_BAD_OP_ERR:
1512 return "bad operation";
1513 case MLX5_CMD_STAT_BAD_PARAM_ERR:
1514 return "bad parameter";
1515 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1516 return "bad system state";
1517 case MLX5_CMD_STAT_BAD_RES_ERR:
1518 return "bad resource";
1519 case MLX5_CMD_STAT_RES_BUSY:
1520 return "resource busy";
1521 case MLX5_CMD_STAT_LIM_ERR:
1522 return "limits exceeded";
1523 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1524 return "bad resource state";
1525 case MLX5_CMD_STAT_IX_ERR:
1527 case MLX5_CMD_STAT_NO_RES_ERR:
1528 return "no resources";
1529 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1530 return "bad input length";
1531 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1532 return "bad output length";
1533 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1534 return "bad QP state";
1535 case MLX5_CMD_STAT_BAD_PKT_ERR:
1536 return "bad packet (discarded)";
1537 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1538 return "bad size too many outstanding CQEs";
1540 return "unknown status";
1544 static int cmd_status_to_err(u8 status)
1547 case MLX5_CMD_STAT_OK: return 0;
1548 case MLX5_CMD_STAT_INT_ERR: return -EIO;
1549 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
1550 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
1551 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
1552 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
1553 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
1554 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
1555 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
1556 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
1557 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
1558 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
1559 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
1560 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
1561 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
1562 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
1563 default: return -EIO;
1567 /* this will be available till all the commands use set/get macros */
1568 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1573 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1574 cmd_status_str(hdr->status), hdr->status,
1575 be32_to_cpu(hdr->syndrome));
1577 return cmd_status_to_err(hdr->status);
1580 int mlx5_cmd_status_to_err_v2(void *ptr)
1585 status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1589 syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1591 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1592 cmd_status_str(status), status, syndrome);
1594 return cmd_status_to_err(status);