drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/flow_table.h>
  34 #include "en.h"
  35
  36 struct mlx5e_rq_param {
  37         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  38         struct mlx5_wq_param       wq;
  39 };
  40
  41 struct mlx5e_sq_param {
  42         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  43         struct mlx5_wq_param       wq;
  44         u16                        max_inline;
  45 };
  46
  47 struct mlx5e_cq_param {
  48         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        eq_ix;
  51 };
  52
  53 struct mlx5e_channel_param {
  54         struct mlx5e_rq_param      rq;
  55         struct mlx5e_sq_param      sq;
  56         struct mlx5e_cq_param      rx_cq;
  57         struct mlx5e_cq_param      tx_cq;
  58 };
  59
  60 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  61 {
  62         struct mlx5_core_dev *mdev = priv->mdev;
  63         u8 port_state;
  64
  65         port_state = mlx5_query_vport_state(mdev,
  66                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
  67
  68         if (port_state == VPORT_STATE_UP)
  69                 netif_carrier_on(priv->netdev);
  70         else
  71                 netif_carrier_off(priv->netdev);
  72 }
  73
  74 static void mlx5e_update_carrier_work(struct work_struct *work)
  75 {
  76         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  77                                                update_carrier_work);
  78
  79         mutex_lock(&priv->state_lock);
  80         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  81                 mlx5e_update_carrier(priv);
  82         mutex_unlock(&priv->state_lock);
  83 }
  84
  85 void mlx5e_update_stats(struct mlx5e_priv *priv)
  86 {
  87         struct mlx5_core_dev *mdev = priv->mdev;
  88         struct mlx5e_vport_stats *s = &priv->stats.vport;
  89         struct mlx5e_rq_stats *rq_stats;
  90         struct mlx5e_sq_stats *sq_stats;
  91         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
  92         u32 *out;
  93         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
  94         u64 tx_offload_none;
  95         int i, j;
  96
  97         out = mlx5_vzalloc(outlen);
  98         if (!out)
  99                 return;
 100
 101         /* Collect firts the SW counters and then HW for consistency */
 102         s->tso_packets          = 0;
 103         s->tso_bytes            = 0;
 104         s->tx_queue_stopped     = 0;
 105         s->tx_queue_wake        = 0;
 106         s->tx_queue_dropped     = 0;
 107         tx_offload_none         = 0;
 108         s->lro_packets          = 0;
 109         s->lro_bytes            = 0;
 110         s->rx_csum_none         = 0;
 111         s->rx_wqe_err           = 0;
 112         for (i = 0; i < priv->params.num_channels; i++) {
 113                 rq_stats = &priv->channel[i]->rq.stats;
 114
 115                 s->lro_packets  += rq_stats->lro_packets;
 116                 s->lro_bytes    += rq_stats->lro_bytes;
 117                 s->rx_csum_none += rq_stats->csum_none;
 118                 s->rx_wqe_err   += rq_stats->wqe_err;
 119
 120                 for (j = 0; j < priv->num_tc; j++) {
 121                         sq_stats = &priv->channel[i]->sq[j].stats;
 122
 123                         s->tso_packets          += sq_stats->tso_packets;
 124                         s->tso_bytes            += sq_stats->tso_bytes;
 125                         s->tx_queue_stopped     += sq_stats->stopped;
 126                         s->tx_queue_wake        += sq_stats->wake;
 127                         s->tx_queue_dropped     += sq_stats->dropped;
 128                         tx_offload_none         += sq_stats->csum_offload_none;
 129                 }
 130         }
 131
 132         /* HW counters */
 133         memset(in, 0, sizeof(in));
 134
 135         MLX5_SET(query_vport_counter_in, in, opcode,
 136                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 137         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 138         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 139
 140         memset(out, 0, outlen);
 141
 142         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 143                 goto free_out;
 144
 145 #define MLX5_GET_CTR(p, x) \
 146         MLX5_GET64(query_vport_counter_out, p, x)
 147
 148         s->rx_error_packets     =
 149                 MLX5_GET_CTR(out, received_errors.packets);
 150         s->rx_error_bytes       =
 151                 MLX5_GET_CTR(out, received_errors.octets);
 152         s->tx_error_packets     =
 153                 MLX5_GET_CTR(out, transmit_errors.packets);
 154         s->tx_error_bytes       =
 155                 MLX5_GET_CTR(out, transmit_errors.octets);
 156
 157         s->rx_unicast_packets   =
 158                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 159         s->rx_unicast_bytes     =
 160                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 161         s->tx_unicast_packets   =
 162                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 163         s->tx_unicast_bytes     =
 164                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 165
 166         s->rx_multicast_packets =
 167                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 168         s->rx_multicast_bytes   =
 169                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 170         s->tx_multicast_packets =
 171                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 172         s->tx_multicast_bytes   =
 173                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 174
 175         s->rx_broadcast_packets =
 176                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 177         s->rx_broadcast_bytes   =
 178                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 179         s->tx_broadcast_packets =
 180                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 181         s->tx_broadcast_bytes   =
 182                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 183
 184         s->rx_packets =
 185                 s->rx_unicast_packets +
 186                 s->rx_multicast_packets +
 187                 s->rx_broadcast_packets;
 188         s->rx_bytes =
 189                 s->rx_unicast_bytes +
 190                 s->rx_multicast_bytes +
 191                 s->rx_broadcast_bytes;
 192         s->tx_packets =
 193                 s->tx_unicast_packets +
 194                 s->tx_multicast_packets +
 195                 s->tx_broadcast_packets;
 196         s->tx_bytes =
 197                 s->tx_unicast_bytes +
 198                 s->tx_multicast_bytes +
 199                 s->tx_broadcast_bytes;
 200
 201         /* Update calculated offload counters */
 202         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 203         s->rx_csum_good    = s->rx_packets - s->rx_csum_none;
 204
 205 free_out:
 206         kvfree(out);
 207 }
 208
 209 static void mlx5e_update_stats_work(struct work_struct *work)
 210 {
 211         struct delayed_work *dwork = to_delayed_work(work);
 212         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 213                                                update_stats_work);
 214         mutex_lock(&priv->state_lock);
 215         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 216                 mlx5e_update_stats(priv);
 217                 schedule_delayed_work(dwork,
 218                                       msecs_to_jiffies(
 219                                               MLX5E_UPDATE_STATS_INTERVAL));
 220         }
 221         mutex_unlock(&priv->state_lock);
 222 }
 223
 224 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 225                                 enum mlx5_dev_event event)
 226 {
 227         switch (event) {
 228         case MLX5_DEV_EVENT_PORT_UP:
 229         case MLX5_DEV_EVENT_PORT_DOWN:
 230                 schedule_work(&priv->update_carrier_work);
 231                 break;
 232
 233         default:
 234                 break;
 235         }
 236 }
 237
 238 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 239                               enum mlx5_dev_event event, unsigned long param)
 240 {
 241         struct mlx5e_priv *priv = vpriv;
 242
 243         spin_lock(&priv->async_events_spinlock);
 244         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 245                 __mlx5e_async_event(priv, event);
 246         spin_unlock(&priv->async_events_spinlock);
 247 }
 248
 249 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 250 {
 251         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 252 }
 253
 254 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 255 {
 256         spin_lock_irq(&priv->async_events_spinlock);
 257         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 258         spin_unlock_irq(&priv->async_events_spinlock);
 259 }
 260
 261 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 262 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 263
 264 static int mlx5e_create_rq(struct mlx5e_channel *c,
 265                            struct mlx5e_rq_param *param,
 266                            struct mlx5e_rq *rq)
 267 {
 268         struct mlx5e_priv *priv = c->priv;
 269         struct mlx5_core_dev *mdev = priv->mdev;
 270         void *rqc = param->rqc;
 271         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 272         int wq_sz;
 273         int err;
 274         int i;
 275
 276         param->wq.db_numa_node = cpu_to_node(c->cpu);
 277
 278         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 279                                 &rq->wq_ctrl);
 280         if (err)
 281                 return err;
 282
 283         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 284
 285         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 286         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 287                                cpu_to_node(c->cpu));
 288         if (!rq->skb) {
 289                 err = -ENOMEM;
 290                 goto err_rq_wq_destroy;
 291         }
 292
 293         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 294                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 295         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 296
 297         for (i = 0; i < wq_sz; i++) {
 298                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 299                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 300
 301                 wqe->data.lkey       = c->mkey_be;
 302                 wqe->data.byte_count =
 303                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 304         }
 305
 306         rq->pdev    = c->pdev;
 307         rq->netdev  = c->netdev;
 308         rq->channel = c;
 309         rq->ix      = c->ix;
 310
 311         return 0;
 312
 313 err_rq_wq_destroy:
 314         mlx5_wq_destroy(&rq->wq_ctrl);
 315
 316         return err;
 317 }
 318
 319 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 320 {
 321         kfree(rq->skb);
 322         mlx5_wq_destroy(&rq->wq_ctrl);
 323 }
 324
 325 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 326 {
 327         struct mlx5e_channel *c = rq->channel;
 328         struct mlx5e_priv *priv = c->priv;
 329         struct mlx5_core_dev *mdev = priv->mdev;
 330
 331         void *in;
 332         void *rqc;
 333         void *wq;
 334         int inlen;
 335         int err;
 336
 337         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 338                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 339         in = mlx5_vzalloc(inlen);
 340         if (!in)
 341                 return -ENOMEM;
 342
 343         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 344         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 345
 346         memcpy(rqc, param->rqc, sizeof(param->rqc));
 347
 348         MLX5_SET(rqc,  rqc, cqn,                c->rq.cq.mcq.cqn);
 349         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 350         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 351         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 352                                                 PAGE_SHIFT);
 353         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 354
 355         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 356                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 357
 358         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 359
 360         kvfree(in);
 361
 362         return err;
 363 }
 364
 365 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 366 {
 367         struct mlx5e_channel *c = rq->channel;
 368         struct mlx5e_priv *priv = c->priv;
 369         struct mlx5_core_dev *mdev = priv->mdev;
 370
 371         void *in;
 372         void *rqc;
 373         int inlen;
 374         int err;
 375
 376         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 377         in = mlx5_vzalloc(inlen);
 378         if (!in)
 379                 return -ENOMEM;
 380
 381         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 382
 383         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 384         MLX5_SET(rqc, rqc, state, next_state);
 385
 386         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 387
 388         kvfree(in);
 389
 390         return err;
 391 }
 392
 393 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 394 {
 395         struct mlx5e_channel *c = rq->channel;
 396         struct mlx5e_priv *priv = c->priv;
 397         struct mlx5_core_dev *mdev = priv->mdev;
 398
 399         mlx5_core_destroy_rq(mdev, rq->rqn);
 400 }
 401
 402 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 403 {
 404         struct mlx5e_channel *c = rq->channel;
 405         struct mlx5e_priv *priv = c->priv;
 406         struct mlx5_wq_ll *wq = &rq->wq;
 407         int i;
 408
 409         for (i = 0; i < 1000; i++) {
 410                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 411                         return 0;
 412
 413                 msleep(20);
 414         }
 415
 416         return -ETIMEDOUT;
 417 }
 418
 419 static int mlx5e_open_rq(struct mlx5e_channel *c,
 420                          struct mlx5e_rq_param *param,
 421                          struct mlx5e_rq *rq)
 422 {
 423         int err;
 424
 425         err = mlx5e_create_rq(c, param, rq);
 426         if (err)
 427                 return err;
 428
 429         err = mlx5e_enable_rq(rq, param);
 430         if (err)
 431                 goto err_destroy_rq;
 432
 433         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 434         if (err)
 435                 goto err_disable_rq;
 436
 437         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 438         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 439
 440         return 0;
 441
 442 err_disable_rq:
 443         mlx5e_disable_rq(rq);
 444 err_destroy_rq:
 445         mlx5e_destroy_rq(rq);
 446
 447         return err;
 448 }
 449
 450 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 451 {
 452         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 453         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 454
 455         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 456         while (!mlx5_wq_ll_is_empty(&rq->wq))
 457                 msleep(20);
 458
 459         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 460         napi_synchronize(&rq->channel->napi);
 461
 462         mlx5e_disable_rq(rq);
 463         mlx5e_destroy_rq(rq);
 464 }
 465
 466 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 467 {
 468         kfree(sq->dma_fifo);
 469         kfree(sq->skb);
 470 }
 471
 472 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 473 {
 474         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 475         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 476
 477         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 478         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 479                                     numa);
 480
 481         if (!sq->skb || !sq->dma_fifo) {
 482                 mlx5e_free_sq_db(sq);
 483                 return -ENOMEM;
 484         }
 485
 486         sq->dma_fifo_mask = df_sz - 1;
 487
 488         return 0;
 489 }
 490
 491 static int mlx5e_create_sq(struct mlx5e_channel *c,
 492                            int tc,
 493                            struct mlx5e_sq_param *param,
 494                            struct mlx5e_sq *sq)
 495 {
 496         struct mlx5e_priv *priv = c->priv;
 497         struct mlx5_core_dev *mdev = priv->mdev;
 498
 499         void *sqc = param->sqc;
 500         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 501         int txq_ix;
 502         int err;
 503
 504         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 505         if (err)
 506                 return err;
 507
 508         param->wq.db_numa_node = cpu_to_node(c->cpu);
 509
 510         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 511                                  &sq->wq_ctrl);
 512         if (err)
 513                 goto err_unmap_free_uar;
 514
 515         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 516         sq->uar_map     = sq->uar.map;
 517         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 518         sq->max_inline  = param->max_inline;
 519
 520         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 521         if (err)
 522                 goto err_sq_wq_destroy;
 523
 524         txq_ix = c->ix + tc * priv->params.num_channels;
 525         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 526
 527         sq->pdev    = c->pdev;
 528         sq->mkey_be = c->mkey_be;
 529         sq->channel = c;
 530         sq->tc      = tc;
 531         sq->edge    = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 532         priv->txq_to_sq_map[txq_ix] = sq;
 533
 534         return 0;
 535
 536 err_sq_wq_destroy:
 537         mlx5_wq_destroy(&sq->wq_ctrl);
 538
 539 err_unmap_free_uar:
 540         mlx5_unmap_free_uar(mdev, &sq->uar);
 541
 542         return err;
 543 }
 544
 545 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 546 {
 547         struct mlx5e_channel *c = sq->channel;
 548         struct mlx5e_priv *priv = c->priv;
 549
 550         mlx5e_free_sq_db(sq);
 551         mlx5_wq_destroy(&sq->wq_ctrl);
 552         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 553 }
 554
 555 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 556 {
 557         struct mlx5e_channel *c = sq->channel;
 558         struct mlx5e_priv *priv = c->priv;
 559         struct mlx5_core_dev *mdev = priv->mdev;
 560
 561         void *in;
 562         void *sqc;
 563         void *wq;
 564         int inlen;
 565         int err;
 566
 567         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 568                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 569         in = mlx5_vzalloc(inlen);
 570         if (!in)
 571                 return -ENOMEM;
 572
 573         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 574         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 575
 576         memcpy(sqc, param->sqc, sizeof(param->sqc));
 577
 578         MLX5_SET(sqc,  sqc, user_index,         sq->tc);
 579         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 580         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 581         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 582         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 583         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 584
 585         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 586         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 587         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 588                                           PAGE_SHIFT);
 589         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 590
 591         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 592                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 593
 594         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 595
 596         kvfree(in);
 597
 598         return err;
 599 }
 600
 601 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 602 {
 603         struct mlx5e_channel *c = sq->channel;
 604         struct mlx5e_priv *priv = c->priv;
 605         struct mlx5_core_dev *mdev = priv->mdev;
 606
 607         void *in;
 608         void *sqc;
 609         int inlen;
 610         int err;
 611
 612         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 613         in = mlx5_vzalloc(inlen);
 614         if (!in)
 615                 return -ENOMEM;
 616
 617         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 618
 619         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 620         MLX5_SET(sqc, sqc, state, next_state);
 621
 622         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 623
 624         kvfree(in);
 625
 626         return err;
 627 }
 628
 629 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 630 {
 631         struct mlx5e_channel *c = sq->channel;
 632         struct mlx5e_priv *priv = c->priv;
 633         struct mlx5_core_dev *mdev = priv->mdev;
 634
 635         mlx5_core_destroy_sq(mdev, sq->sqn);
 636 }
 637
 638 static int mlx5e_open_sq(struct mlx5e_channel *c,
 639                          int tc,
 640                          struct mlx5e_sq_param *param,
 641                          struct mlx5e_sq *sq)
 642 {
 643         int err;
 644
 645         err = mlx5e_create_sq(c, tc, param, sq);
 646         if (err)
 647                 return err;
 648
 649         err = mlx5e_enable_sq(sq, param);
 650         if (err)
 651                 goto err_destroy_sq;
 652
 653         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 654         if (err)
 655                 goto err_disable_sq;
 656
 657         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 658         netdev_tx_reset_queue(sq->txq);
 659         netif_tx_start_queue(sq->txq);
 660
 661         return 0;
 662
 663 err_disable_sq:
 664         mlx5e_disable_sq(sq);
 665 err_destroy_sq:
 666         mlx5e_destroy_sq(sq);
 667
 668         return err;
 669 }
 670
 671 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 672 {
 673         __netif_tx_lock_bh(txq);
 674         netif_tx_stop_queue(txq);
 675         __netif_tx_unlock_bh(txq);
 676 }
 677
 678 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 679 {
 680         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 681         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 682         netif_tx_disable_queue(sq->txq);
 683
 684         /* ensure hw is notified of all pending wqes */
 685         if (mlx5e_sq_has_room_for(sq, 1))
 686                 mlx5e_send_nop(sq, true);
 687
 688         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 689         while (sq->cc != sq->pc) /* wait till sq is empty */
 690                 msleep(20);
 691
 692         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 693         napi_synchronize(&sq->channel->napi);
 694
 695         mlx5e_disable_sq(sq);
 696         mlx5e_destroy_sq(sq);
 697 }
 698
 699 static int mlx5e_create_cq(struct mlx5e_channel *c,
 700                            struct mlx5e_cq_param *param,
 701                            struct mlx5e_cq *cq)
 702 {
 703         struct mlx5e_priv *priv = c->priv;
 704         struct mlx5_core_dev *mdev = priv->mdev;
 705         struct mlx5_core_cq *mcq = &cq->mcq;
 706         int eqn_not_used;
 707         int irqn;
 708         int err;
 709         u32 i;
 710
 711         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 712         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 713         param->eq_ix   = c->ix;
 714
 715         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 716                                &cq->wq_ctrl);
 717         if (err)
 718                 return err;
 719
 720         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 721
 722         cq->napi        = &c->napi;
 723
 724         mcq->cqe_sz     = 64;
 725         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 726         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 727         *mcq->set_ci_db = 0;
 728         *mcq->arm_db    = 0;
 729         mcq->vector     = param->eq_ix;
 730         mcq->comp       = mlx5e_completion_event;
 731         mcq->event      = mlx5e_cq_error_event;
 732         mcq->irqn       = irqn;
 733         mcq->uar        = &priv->cq_uar;
 734
 735         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 736                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 737
 738                 cqe->op_own = 0xf1;
 739         }
 740
 741         cq->channel = c;
 742
 743         return 0;
 744 }
 745
 746 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 747 {
 748         mlx5_wq_destroy(&cq->wq_ctrl);
 749 }
 750
 751 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 752 {
 753         struct mlx5e_channel *c = cq->channel;
 754         struct mlx5e_priv *priv = c->priv;
 755         struct mlx5_core_dev *mdev = priv->mdev;
 756         struct mlx5_core_cq *mcq = &cq->mcq;
 757
 758         void *in;
 759         void *cqc;
 760         int inlen;
 761         int irqn_not_used;
 762         int eqn;
 763         int err;
 764
 765         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 766                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 767         in = mlx5_vzalloc(inlen);
 768         if (!in)
 769                 return -ENOMEM;
 770
 771         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 772
 773         memcpy(cqc, param->cqc, sizeof(param->cqc));
 774
 775         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 776                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 777
 778         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 779
 780         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 781         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 782         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 783                                             PAGE_SHIFT);
 784         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 785
 786         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 787
 788         kvfree(in);
 789
 790         if (err)
 791                 return err;
 792
 793         mlx5e_cq_arm(cq);
 794
 795         return 0;
 796 }
 797
 798 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 799 {
 800         struct mlx5e_channel *c = cq->channel;
 801         struct mlx5e_priv *priv = c->priv;
 802         struct mlx5_core_dev *mdev = priv->mdev;
 803
 804         mlx5_core_destroy_cq(mdev, &cq->mcq);
 805 }
 806
 807 static int mlx5e_open_cq(struct mlx5e_channel *c,
 808                          struct mlx5e_cq_param *param,
 809                          struct mlx5e_cq *cq,
 810                          u16 moderation_usecs,
 811                          u16 moderation_frames)
 812 {
 813         int err;
 814         struct mlx5e_priv *priv = c->priv;
 815         struct mlx5_core_dev *mdev = priv->mdev;
 816
 817         err = mlx5e_create_cq(c, param, cq);
 818         if (err)
 819                 return err;
 820
 821         err = mlx5e_enable_cq(cq, param);
 822         if (err)
 823                 goto err_destroy_cq;
 824
 825         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 826                                              moderation_usecs,
 827                                              moderation_frames);
 828         if (err)
 829                 goto err_destroy_cq;
 830
 831         return 0;
 832
 833 err_destroy_cq:
 834         mlx5e_destroy_cq(cq);
 835
 836         return err;
 837 }
 838
 839 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 840 {
 841         mlx5e_disable_cq(cq);
 842         mlx5e_destroy_cq(cq);
 843 }
 844
 845 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 846 {
 847         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 848 }
 849
 850 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 851                              struct mlx5e_channel_param *cparam)
 852 {
 853         struct mlx5e_priv *priv = c->priv;
 854         int err;
 855         int tc;
 856
 857         for (tc = 0; tc < c->num_tc; tc++) {
 858                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 859                                     priv->params.tx_cq_moderation_usec,
 860                                     priv->params.tx_cq_moderation_pkts);
 861                 if (err)
 862                         goto err_close_tx_cqs;
 863         }
 864
 865         return 0;
 866
 867 err_close_tx_cqs:
 868         for (tc--; tc >= 0; tc--)
 869                 mlx5e_close_cq(&c->sq[tc].cq);
 870
 871         return err;
 872 }
 873
 874 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 875 {
 876         int tc;
 877
 878         for (tc = 0; tc < c->num_tc; tc++)
 879                 mlx5e_close_cq(&c->sq[tc].cq);
 880 }
 881
 882 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 883                           struct mlx5e_channel_param *cparam)
 884 {
 885         int err;
 886         int tc;
 887
 888         for (tc = 0; tc < c->num_tc; tc++) {
 889                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 890                 if (err)
 891                         goto err_close_sqs;
 892         }
 893
 894         return 0;
 895
 896 err_close_sqs:
 897         for (tc--; tc >= 0; tc--)
 898                 mlx5e_close_sq(&c->sq[tc]);
 899
 900         return err;
 901 }
 902
 903 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 904 {
 905         int tc;
 906
 907         for (tc = 0; tc < c->num_tc; tc++)
 908                 mlx5e_close_sq(&c->sq[tc]);
 909 }
 910
 911 static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
 912                                       int num_channels)
 913 {
 914         int i;
 915
 916         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 917                 c->tc_to_txq_map[i] = c->ix + i * num_channels;
 918 }
 919
 920 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 921                               struct mlx5e_channel_param *cparam,
 922                               struct mlx5e_channel **cp)
 923 {
 924         struct net_device *netdev = priv->netdev;
 925         int cpu = mlx5e_get_cpu(priv, ix);
 926         struct mlx5e_channel *c;
 927         int err;
 928
 929         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 930         if (!c)
 931                 return -ENOMEM;
 932
 933         c->priv     = priv;
 934         c->ix       = ix;
 935         c->cpu      = cpu;
 936         c->pdev     = &priv->mdev->pdev->dev;
 937         c->netdev   = priv->netdev;
 938         c->mkey_be  = cpu_to_be32(priv->mr.key);
 939         c->num_tc   = priv->num_tc;
 940
 941         mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
 942
 943         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 944
 945         err = mlx5e_open_tx_cqs(c, cparam);
 946         if (err)
 947                 goto err_napi_del;
 948
 949         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 950                             priv->params.rx_cq_moderation_usec,
 951                             priv->params.rx_cq_moderation_pkts);
 952         if (err)
 953                 goto err_close_tx_cqs;
 954
 955         napi_enable(&c->napi);
 956
 957         err = mlx5e_open_sqs(c, cparam);
 958         if (err)
 959                 goto err_disable_napi;
 960
 961         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
 962         if (err)
 963                 goto err_close_sqs;
 964
 965         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
 966         *cp = c;
 967
 968         return 0;
 969
 970 err_close_sqs:
 971         mlx5e_close_sqs(c);
 972
 973 err_disable_napi:
 974         napi_disable(&c->napi);
 975         mlx5e_close_cq(&c->rq.cq);
 976
 977 err_close_tx_cqs:
 978         mlx5e_close_tx_cqs(c);
 979
 980 err_napi_del:
 981         netif_napi_del(&c->napi);
 982         kfree(c);
 983
 984         return err;
 985 }
 986
 987 static void mlx5e_close_channel(struct mlx5e_channel *c)
 988 {
 989         mlx5e_close_rq(&c->rq);
 990         mlx5e_close_sqs(c);
 991         napi_disable(&c->napi);
 992         mlx5e_close_cq(&c->rq.cq);
 993         mlx5e_close_tx_cqs(c);
 994         netif_napi_del(&c->napi);
 995         kfree(c);
 996 }
 997
 998 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
 999                                  struct mlx5e_rq_param *param)
1000 {
1001         void *rqc = param->rqc;
1002         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1003
1004         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1005         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1006         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1007         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1008         MLX5_SET(wq, wq, pd,               priv->pdn);
1009
1010         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1011         param->wq.linear = 1;
1012 }
1013
1014 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1015                                  struct mlx5e_sq_param *param)
1016 {
1017         void *sqc = param->sqc;
1018         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1019
1020         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1021         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1022         MLX5_SET(wq, wq, pd,            priv->pdn);
1023
1024         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1025         param->max_inline = priv->params.tx_max_inline;
1026 }
1027
1028 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1029                                         struct mlx5e_cq_param *param)
1030 {
1031         void *cqc = param->cqc;
1032
1033         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1034 }
1035
1036 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1037                                     struct mlx5e_cq_param *param)
1038 {
1039         void *cqc = param->cqc;
1040
1041         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1042
1043         mlx5e_build_common_cq_param(priv, param);
1044 }
1045
1046 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1047                                     struct mlx5e_cq_param *param)
1048 {
1049         void *cqc = param->cqc;
1050
1051         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1052
1053         mlx5e_build_common_cq_param(priv, param);
1054 }
1055
1056 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1057                                       struct mlx5e_channel_param *cparam)
1058 {
1059         memset(cparam, 0, sizeof(*cparam));
1060
1061         mlx5e_build_rq_param(priv, &cparam->rq);
1062         mlx5e_build_sq_param(priv, &cparam->sq);
1063         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1064         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1065 }
1066
1067 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1068 {
1069         struct mlx5e_channel_param cparam;
1070         int err = -ENOMEM;
1071         int i;
1072         int j;
1073
1074         priv->channel = kcalloc(priv->params.num_channels,
1075                                 sizeof(struct mlx5e_channel *), GFP_KERNEL);
1076
1077         priv->txq_to_sq_map = kcalloc(priv->params.num_channels * priv->num_tc,
1078                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1079
1080         if (!priv->channel || !priv->txq_to_sq_map)
1081                 goto err_free_txq_to_sq_map;
1082
1083         mlx5e_build_channel_param(priv, &cparam);
1084         for (i = 0; i < priv->params.num_channels; i++) {
1085                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1086                 if (err)
1087                         goto err_close_channels;
1088         }
1089
1090         for (j = 0; j < priv->params.num_channels; j++) {
1091                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1092                 if (err)
1093                         goto err_close_channels;
1094         }
1095
1096         return 0;
1097
1098 err_close_channels:
1099         for (i--; i >= 0; i--)
1100                 mlx5e_close_channel(priv->channel[i]);
1101
1102 err_free_txq_to_sq_map:
1103         kfree(priv->txq_to_sq_map);
1104         kfree(priv->channel);
1105
1106         return err;
1107 }
1108
1109 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1110 {
1111         int i;
1112
1113         for (i = 0; i < priv->params.num_channels; i++)
1114                 mlx5e_close_channel(priv->channel[i]);
1115
1116         kfree(priv->txq_to_sq_map);
1117         kfree(priv->channel);
1118 }
1119
1120 static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1121 {
1122         struct mlx5_core_dev *mdev = priv->mdev;
1123         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1124         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1125
1126         memset(in, 0, sizeof(in));
1127
1128         MLX5_SET(tisc, tisc, prio,  tc);
1129         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1130
1131         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1132 }
1133
1134 static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1135 {
1136         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1137 }
1138
1139 static int mlx5e_open_tises(struct mlx5e_priv *priv)
1140 {
1141         int num_tc = priv->num_tc;
1142         int err;
1143         int tc;
1144
1145         for (tc = 0; tc < num_tc; tc++) {
1146                 err = mlx5e_open_tis(priv, tc);
1147                 if (err)
1148                         goto err_close_tises;
1149         }
1150
1151         return 0;
1152
1153 err_close_tises:
1154         for (tc--; tc >= 0; tc--)
1155                 mlx5e_close_tis(priv, tc);
1156
1157         return err;
1158 }
1159
1160 static void mlx5e_close_tises(struct mlx5e_priv *priv)
1161 {
1162         int num_tc = priv->num_tc;
1163         int tc;
1164
1165         for (tc = 0; tc < num_tc; tc++)
1166                 mlx5e_close_tis(priv, tc);
1167 }
1168
1169 static int mlx5e_rx_hash_fn(int hfunc)
1170 {
1171         return (hfunc == ETH_RSS_HASH_TOP) ?
1172                MLX5_RX_HASH_FN_TOEPLITZ :
1173                MLX5_RX_HASH_FN_INVERTED_XOR8;
1174 }
1175
1176 static int mlx5e_bits_invert(unsigned long a, int size)
1177 {
1178         int inv = 0;
1179         int i;
1180
1181         for (i = 0; i < size; i++)
1182                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1183
1184         return inv;
1185 }
1186
1187 static int mlx5e_open_rqt(struct mlx5e_priv *priv)
1188 {
1189         struct mlx5_core_dev *mdev = priv->mdev;
1190         u32 *in;
1191         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1192         void *rqtc;
1193         int inlen;
1194         int err;
1195         int log_tbl_sz = priv->params.rx_hash_log_tbl_sz;
1196         int sz = 1 << log_tbl_sz;
1197         int i;
1198
1199         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1200         in = mlx5_vzalloc(inlen);
1201         if (!in)
1202                 return -ENOMEM;
1203
1204         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1205
1206         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1207         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1208
1209         for (i = 0; i < sz; i++) {
1210                 int ix = i;
1211
1212                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1213                         ix = mlx5e_bits_invert(i, log_tbl_sz);
1214
1215                 ix = ix % priv->params.num_channels;
1216                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1217         }
1218
1219         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1220
1221         memset(out, 0, sizeof(out));
1222         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1223         if (!err)
1224                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1225
1226         kvfree(in);
1227
1228         return err;
1229 }
1230
1231 static void mlx5e_close_rqt(struct mlx5e_priv *priv)
1232 {
1233         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1234         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1235
1236         memset(in, 0, sizeof(in));
1237
1238         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1239         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1240
1241         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1242                                    sizeof(out));
1243 }
1244
1245 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1246 {
1247         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1248
1249         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1250
1251 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1252
1253 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1254                           MLX5_HASH_FIELD_SEL_DST_IP)
1255
1256 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1257                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1258                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1259                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1260
1261         if (priv->params.lro_en) {
1262                 MLX5_SET(tirc, tirc, lro_enable_mask,
1263                          MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1264                          MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1265                 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1266                          (priv->params.lro_wqe_sz -
1267                           ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1268                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1269                          MLX5_CAP_ETH(priv->mdev,
1270                                       lro_timer_supported_periods[3]));
1271         }
1272
1273         switch (tt) {
1274         case MLX5E_TT_ANY:
1275                 MLX5_SET(tirc, tirc, disp_type,
1276                          MLX5_TIRC_DISP_TYPE_DIRECT);
1277                 MLX5_SET(tirc, tirc, inline_rqn,
1278                          priv->channel[0]->rq.rqn);
1279                 break;
1280         default:
1281                 MLX5_SET(tirc, tirc, disp_type,
1282                          MLX5_TIRC_DISP_TYPE_INDIRECT);
1283                 MLX5_SET(tirc, tirc, indirect_table,
1284                          priv->rqtn);
1285                 MLX5_SET(tirc, tirc, rx_hash_fn,
1286                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1287                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1288                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1289                                                      rx_hash_toeplitz_key);
1290                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1291                                                        rx_hash_toeplitz_key);
1292
1293                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1294                         netdev_rss_key_fill(rss_key, len);
1295                 }
1296                 break;
1297         }
1298
1299         switch (tt) {
1300         case MLX5E_TT_IPV4_TCP:
1301                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1302                          MLX5_L3_PROT_TYPE_IPV4);
1303                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1304                          MLX5_L4_PROT_TYPE_TCP);
1305                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1306                          MLX5_HASH_ALL);
1307                 break;
1308
1309         case MLX5E_TT_IPV6_TCP:
1310                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1311                          MLX5_L3_PROT_TYPE_IPV6);
1312                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1313                          MLX5_L4_PROT_TYPE_TCP);
1314                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1315                          MLX5_HASH_ALL);
1316                 break;
1317
1318         case MLX5E_TT_IPV4_UDP:
1319                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1320                          MLX5_L3_PROT_TYPE_IPV4);
1321                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1322                          MLX5_L4_PROT_TYPE_UDP);
1323                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1324                          MLX5_HASH_ALL);
1325                 break;
1326
1327         case MLX5E_TT_IPV6_UDP:
1328                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1329                          MLX5_L3_PROT_TYPE_IPV6);
1330                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1331                          MLX5_L4_PROT_TYPE_UDP);
1332                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1333                          MLX5_HASH_ALL);
1334                 break;
1335
1336         case MLX5E_TT_IPV4:
1337                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1338                          MLX5_L3_PROT_TYPE_IPV4);
1339                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1340                          MLX5_HASH_IP);
1341                 break;
1342
1343         case MLX5E_TT_IPV6:
1344                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1345                          MLX5_L3_PROT_TYPE_IPV6);
1346                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1347                          MLX5_HASH_IP);
1348                 break;
1349         }
1350 }
1351
1352 static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1353 {
1354         struct mlx5_core_dev *mdev = priv->mdev;
1355         u32 *in;
1356         void *tirc;
1357         int inlen;
1358         int err;
1359
1360         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1361         in = mlx5_vzalloc(inlen);
1362         if (!in)
1363                 return -ENOMEM;
1364
1365         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1366
1367         mlx5e_build_tir_ctx(priv, tirc, tt);
1368
1369         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1370
1371         kvfree(in);
1372
1373         return err;
1374 }
1375
1376 static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1377 {
1378         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1379 }
1380
1381 static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1382 {
1383         int err;
1384         int i;
1385
1386         for (i = 0; i < MLX5E_NUM_TT; i++) {
1387                 err = mlx5e_open_tir(priv, i);
1388                 if (err)
1389                         goto err_close_tirs;
1390         }
1391
1392         return 0;
1393
1394 err_close_tirs:
1395         for (i--; i >= 0; i--)
1396                 mlx5e_close_tir(priv, i);
1397
1398         return err;
1399 }
1400
1401 static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1402 {
1403         int i;
1404
1405         for (i = 0; i < MLX5E_NUM_TT; i++)
1406                 mlx5e_close_tir(priv, i);
1407 }
1408
1409 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1410 {
1411         struct mlx5e_priv *priv = netdev_priv(netdev);
1412         struct mlx5_core_dev *mdev = priv->mdev;
1413         int hw_mtu;
1414         int err;
1415
1416         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1417         if (err)
1418                 return err;
1419
1420         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1421
1422         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1423                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1424                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1425
1426         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1427         return 0;
1428 }
1429
1430 int mlx5e_open_locked(struct net_device *netdev)
1431 {
1432         struct mlx5e_priv *priv = netdev_priv(netdev);
1433         int num_txqs;
1434         int err;
1435
1436         num_txqs = priv->params.num_channels * priv->params.num_tc;
1437         netif_set_real_num_tx_queues(netdev, num_txqs);
1438         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1439
1440         err = mlx5e_set_dev_port_mtu(netdev);
1441         if (err)
1442                 return err;
1443
1444         err = mlx5e_open_tises(priv);
1445         if (err) {
1446                 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1447                            __func__, err);
1448                 return err;
1449         }
1450
1451         err = mlx5e_open_channels(priv);
1452         if (err) {
1453                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1454                            __func__, err);
1455                 goto err_close_tises;
1456         }
1457
1458         err = mlx5e_open_rqt(priv);
1459         if (err) {
1460                 netdev_err(netdev, "%s: mlx5e_open_rqt failed, %d\n",
1461                            __func__, err);
1462                 goto err_close_channels;
1463         }
1464
1465         err = mlx5e_open_tirs(priv);
1466         if (err) {
1467                 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1468                            __func__, err);
1469                 goto err_close_rqls;
1470         }
1471
1472         err = mlx5e_open_flow_table(priv);
1473         if (err) {
1474                 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1475                            __func__, err);
1476                 goto err_close_tirs;
1477         }
1478
1479         err = mlx5e_add_all_vlan_rules(priv);
1480         if (err) {
1481                 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1482                            __func__, err);
1483                 goto err_close_flow_table;
1484         }
1485
1486         mlx5e_init_eth_addr(priv);
1487
1488         set_bit(MLX5E_STATE_OPENED, &priv->state);
1489
1490         mlx5e_update_carrier(priv);
1491         mlx5e_set_rx_mode_core(priv);
1492
1493         schedule_delayed_work(&priv->update_stats_work, 0);
1494         return 0;
1495
1496 err_close_flow_table:
1497         mlx5e_close_flow_table(priv);
1498
1499 err_close_tirs:
1500         mlx5e_close_tirs(priv);
1501
1502 err_close_rqls:
1503         mlx5e_close_rqt(priv);
1504
1505 err_close_channels:
1506         mlx5e_close_channels(priv);
1507
1508 err_close_tises:
1509         mlx5e_close_tises(priv);
1510
1511         return err;
1512 }
1513
1514 static int mlx5e_open(struct net_device *netdev)
1515 {
1516         struct mlx5e_priv *priv = netdev_priv(netdev);
1517         int err;
1518
1519         mutex_lock(&priv->state_lock);
1520         err = mlx5e_open_locked(netdev);
1521         mutex_unlock(&priv->state_lock);
1522
1523         return err;
1524 }
1525
1526 int mlx5e_close_locked(struct net_device *netdev)
1527 {
1528         struct mlx5e_priv *priv = netdev_priv(netdev);
1529
1530         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1531
1532         mlx5e_set_rx_mode_core(priv);
1533         mlx5e_del_all_vlan_rules(priv);
1534         netif_carrier_off(priv->netdev);
1535         mlx5e_close_flow_table(priv);
1536         mlx5e_close_tirs(priv);
1537         mlx5e_close_rqt(priv);
1538         mlx5e_close_channels(priv);
1539         mlx5e_close_tises(priv);
1540
1541         return 0;
1542 }
1543
1544 static int mlx5e_close(struct net_device *netdev)
1545 {
1546         struct mlx5e_priv *priv = netdev_priv(netdev);
1547         int err;
1548
1549         mutex_lock(&priv->state_lock);
1550         err = mlx5e_close_locked(netdev);
1551         mutex_unlock(&priv->state_lock);
1552
1553         return err;
1554 }
1555
1556 int mlx5e_update_priv_params(struct mlx5e_priv *priv,
1557                              struct mlx5e_params *new_params)
1558 {
1559         int err = 0;
1560         int was_opened;
1561
1562         WARN_ON(!mutex_is_locked(&priv->state_lock));
1563
1564         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1565         if (was_opened)
1566                 mlx5e_close_locked(priv->netdev);
1567
1568         priv->params = *new_params;
1569
1570         if (was_opened)
1571                 err = mlx5e_open_locked(priv->netdev);
1572
1573         return err;
1574 }
1575
1576 static struct rtnl_link_stats64 *
1577 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1578 {
1579         struct mlx5e_priv *priv = netdev_priv(dev);
1580         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1581
1582         stats->rx_packets = vstats->rx_packets;
1583         stats->rx_bytes   = vstats->rx_bytes;
1584         stats->tx_packets = vstats->tx_packets;
1585         stats->tx_bytes   = vstats->tx_bytes;
1586         stats->multicast  = vstats->rx_multicast_packets +
1587                             vstats->tx_multicast_packets;
1588         stats->tx_errors  = vstats->tx_error_packets;
1589         stats->rx_errors  = vstats->rx_error_packets;
1590         stats->tx_dropped = vstats->tx_queue_dropped;
1591         stats->rx_crc_errors = 0;
1592         stats->rx_length_errors = 0;
1593
1594         return stats;
1595 }
1596
1597 static void mlx5e_set_rx_mode(struct net_device *dev)
1598 {
1599         struct mlx5e_priv *priv = netdev_priv(dev);
1600
1601         schedule_work(&priv->set_rx_mode_work);
1602 }
1603
1604 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1605 {
1606         struct mlx5e_priv *priv = netdev_priv(netdev);
1607         struct sockaddr *saddr = addr;
1608
1609         if (!is_valid_ether_addr(saddr->sa_data))
1610                 return -EADDRNOTAVAIL;
1611
1612         netif_addr_lock_bh(netdev);
1613         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1614         netif_addr_unlock_bh(netdev);
1615
1616         schedule_work(&priv->set_rx_mode_work);
1617
1618         return 0;
1619 }
1620
1621 static int mlx5e_set_features(struct net_device *netdev,
1622                               netdev_features_t features)
1623 {
1624         struct mlx5e_priv *priv = netdev_priv(netdev);
1625         netdev_features_t changes = features ^ netdev->features;
1626         struct mlx5e_params new_params;
1627         bool update_params = false;
1628
1629         mutex_lock(&priv->state_lock);
1630         new_params = priv->params;
1631
1632         if (changes & NETIF_F_LRO) {
1633                 new_params.lro_en = !!(features & NETIF_F_LRO);
1634                 update_params = true;
1635         }
1636
1637         if (update_params)
1638                 mlx5e_update_priv_params(priv, &new_params);
1639
1640         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1641                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1642                         mlx5e_enable_vlan_filter(priv);
1643                 else
1644                         mlx5e_disable_vlan_filter(priv);
1645         }
1646
1647         mutex_unlock(&priv->state_lock);
1648
1649         return 0;
1650 }
1651
1652 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1653 {
1654         struct mlx5e_priv *priv = netdev_priv(netdev);
1655         struct mlx5_core_dev *mdev = priv->mdev;
1656         int max_mtu;
1657         int err;
1658
1659         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1660
1661         if (new_mtu > max_mtu) {
1662                 netdev_err(netdev,
1663                            "%s: Bad MTU (%d) > (%d) Max\n",
1664                            __func__, new_mtu, max_mtu);
1665                 return -EINVAL;
1666         }
1667
1668         mutex_lock(&priv->state_lock);
1669         netdev->mtu = new_mtu;
1670         err = mlx5e_update_priv_params(priv, &priv->params);
1671         mutex_unlock(&priv->state_lock);
1672
1673         return err;
1674 }
1675
1676 static struct net_device_ops mlx5e_netdev_ops = {
1677         .ndo_open                = mlx5e_open,
1678         .ndo_stop                = mlx5e_close,
1679         .ndo_start_xmit          = mlx5e_xmit,
1680         .ndo_get_stats64         = mlx5e_get_stats,
1681         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
1682         .ndo_set_mac_address     = mlx5e_set_mac,
1683         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
1684         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
1685         .ndo_set_features        = mlx5e_set_features,
1686         .ndo_change_mtu          = mlx5e_change_mtu,
1687 };
1688
1689 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1690 {
1691         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1692                 return -ENOTSUPP;
1693         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1694             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1695             !MLX5_CAP_ETH(mdev, csum_cap) ||
1696             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1697             !MLX5_CAP_ETH(mdev, vlan_cap) ||
1698             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1699             MLX5_CAP_FLOWTABLE(mdev,
1700                                flow_table_properties_nic_receive.max_ft_level)
1701                                < 3) {
1702                 mlx5_core_warn(mdev,
1703                                "Not creating net device, some required device capabilities are missing\n");
1704                 return -ENOTSUPP;
1705         }
1706         return 0;
1707 }
1708
1709 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
1710 {
1711         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1712
1713         return bf_buf_size -
1714                sizeof(struct mlx5e_tx_wqe) +
1715                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
1716 }
1717
1718 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1719                                     struct net_device *netdev,
1720                                     int num_comp_vectors)
1721 {
1722         struct mlx5e_priv *priv = netdev_priv(netdev);
1723
1724         priv->params.log_sq_size           =
1725                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1726         priv->params.log_rq_size           =
1727                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1728         priv->params.rx_cq_moderation_usec =
1729                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1730         priv->params.rx_cq_moderation_pkts =
1731                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1732         priv->params.tx_cq_moderation_usec =
1733                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1734         priv->params.tx_cq_moderation_pkts =
1735                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1736         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
1737         priv->params.min_rx_wqes           =
1738                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1739         priv->params.rx_hash_log_tbl_sz    =
1740                 (order_base_2(num_comp_vectors) >
1741                  MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1742                 order_base_2(num_comp_vectors)           :
1743                 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1744         priv->params.num_tc                = 1;
1745         priv->params.default_vlan_prio     = 0;
1746         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
1747
1748         priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1749         priv->params.lro_wqe_sz            =
1750                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1751
1752         priv->mdev                         = mdev;
1753         priv->netdev                       = netdev;
1754         priv->params.num_channels          = num_comp_vectors;
1755         priv->num_tc                       = priv->params.num_tc;
1756         priv->default_vlan_prio            = priv->params.default_vlan_prio;
1757
1758         spin_lock_init(&priv->async_events_spinlock);
1759         mutex_init(&priv->state_lock);
1760
1761         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1762         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1763         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1764 }
1765
1766 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1767 {
1768         struct mlx5e_priv *priv = netdev_priv(netdev);
1769
1770         mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
1771 }
1772
1773 static void mlx5e_build_netdev(struct net_device *netdev)
1774 {
1775         struct mlx5e_priv *priv = netdev_priv(netdev);
1776         struct mlx5_core_dev *mdev = priv->mdev;
1777
1778         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1779
1780         if (priv->num_tc > 1) {
1781                 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1782         }
1783
1784         netdev->netdev_ops        = &mlx5e_netdev_ops;
1785         netdev->watchdog_timeo    = 15 * HZ;
1786
1787         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
1788
1789         netdev->vlan_features    |= NETIF_F_SG;
1790         netdev->vlan_features    |= NETIF_F_IP_CSUM;
1791         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
1792         netdev->vlan_features    |= NETIF_F_GRO;
1793         netdev->vlan_features    |= NETIF_F_TSO;
1794         netdev->vlan_features    |= NETIF_F_TSO6;
1795         netdev->vlan_features    |= NETIF_F_RXCSUM;
1796         netdev->vlan_features    |= NETIF_F_RXHASH;
1797
1798         if (!!MLX5_CAP_ETH(mdev, lro_cap))
1799                 netdev->vlan_features    |= NETIF_F_LRO;
1800
1801         netdev->hw_features       = netdev->vlan_features;
1802         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
1803         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
1804
1805         netdev->features          = netdev->hw_features;
1806         if (!priv->params.lro_en)
1807                 netdev->features  &= ~NETIF_F_LRO;
1808
1809         netdev->features         |= NETIF_F_HIGHDMA;
1810
1811         netdev->priv_flags       |= IFF_UNICAST_FLT;
1812
1813         mlx5e_set_netdev_dev_addr(netdev);
1814 }
1815
1816 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1817                              struct mlx5_core_mr *mr)
1818 {
1819         struct mlx5_core_dev *mdev = priv->mdev;
1820         struct mlx5_create_mkey_mbox_in *in;
1821         int err;
1822
1823         in = mlx5_vzalloc(sizeof(*in));
1824         if (!in)
1825                 return -ENOMEM;
1826
1827         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1828                         MLX5_PERM_LOCAL_READ  |
1829                         MLX5_ACCESS_MODE_PA;
1830         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1831         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1832
1833         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1834                                     NULL);
1835
1836         kvfree(in);
1837
1838         return err;
1839 }
1840
1841 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1842 {
1843         struct net_device *netdev;
1844         struct mlx5e_priv *priv;
1845         int ncv = mdev->priv.eq_table.num_comp_vectors;
1846         int err;
1847
1848         if (mlx5e_check_required_hca_cap(mdev))
1849                 return NULL;
1850
1851         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
1852         if (!netdev) {
1853                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1854                 return NULL;
1855         }
1856
1857         mlx5e_build_netdev_priv(mdev, netdev, ncv);
1858         mlx5e_build_netdev(netdev);
1859
1860         netif_carrier_off(netdev);
1861
1862         priv = netdev_priv(netdev);
1863
1864         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
1865         if (err) {
1866                 netdev_err(netdev, "%s: mlx5_alloc_map_uar failed, %d\n",
1867                            __func__, err);
1868                 goto err_free_netdev;
1869         }
1870
1871         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
1872         if (err) {
1873                 netdev_err(netdev, "%s: mlx5_core_alloc_pd failed, %d\n",
1874                            __func__, err);
1875                 goto err_unmap_free_uar;
1876         }
1877
1878         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
1879         if (err) {
1880                 netdev_err(netdev, "%s: mlx5_alloc_transport_domain failed, %d\n",
1881                            __func__, err);
1882                 goto err_dealloc_pd;
1883         }
1884
1885         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
1886         if (err) {
1887                 netdev_err(netdev, "%s: mlx5e_create_mkey failed, %d\n",
1888                            __func__, err);
1889                 goto err_dealloc_transport_domain;
1890         }
1891
1892         err = register_netdev(netdev);
1893         if (err) {
1894                 netdev_err(netdev, "%s: register_netdev failed, %d\n",
1895                            __func__, err);
1896                 goto err_destroy_mkey;
1897         }
1898
1899         mlx5e_enable_async_events(priv);
1900
1901         return priv;
1902
1903 err_destroy_mkey:
1904         mlx5_core_destroy_mkey(mdev, &priv->mr);
1905
1906 err_dealloc_transport_domain:
1907         mlx5_dealloc_transport_domain(mdev, priv->tdn);
1908
1909 err_dealloc_pd:
1910         mlx5_core_dealloc_pd(mdev, priv->pdn);
1911
1912 err_unmap_free_uar:
1913         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
1914
1915 err_free_netdev:
1916         free_netdev(netdev);
1917
1918         return NULL;
1919 }
1920
1921 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
1922 {
1923         struct mlx5e_priv *priv = vpriv;
1924         struct net_device *netdev = priv->netdev;
1925
1926         unregister_netdev(netdev);
1927         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
1928         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
1929         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
1930         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
1931         mlx5e_disable_async_events(priv);
1932         flush_scheduled_work();
1933         free_netdev(netdev);
1934 }
1935
1936 static void *mlx5e_get_netdev(void *vpriv)
1937 {
1938         struct mlx5e_priv *priv = vpriv;
1939
1940         return priv->netdev;
1941 }
1942
1943 static struct mlx5_interface mlx5e_interface = {
1944         .add       = mlx5e_create_netdev,
1945         .remove    = mlx5e_destroy_netdev,
1946         .event     = mlx5e_async_event,
1947         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
1948         .get_dev   = mlx5e_get_netdev,
1949 };
1950
1951 void mlx5e_init(void)
1952 {
1953         mlx5_register_interface(&mlx5e_interface);
1954 }
1955
1956 void mlx5e_cleanup(void)
1957 {
1958         mlx5_unregister_interface(&mlx5e_interface);
1959 }