2 * drivers/net/ethernet/micrel/ks8851_mll.c
3 * Copyright (c) 2009 Micrel Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * KS8851 16bit MLL chip from Micrel Inc.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/cache.h>
32 #include <linux/crc32.h>
33 #include <linux/mii.h>
34 #include <linux/platform_device.h>
35 #include <linux/delay.h>
36 #include <linux/slab.h>
37 #include <linux/ks8851_mll.h>
39 #define DRV_NAME "ks8851_mll"
41 static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
42 #define MAX_RECV_FRAMES 255
43 #define MAX_BUF_SIZE 2048
44 #define TX_BUF_SIZE 2000
45 #define RX_BUF_SIZE 2000
48 #define CCR_EEPROM (1 << 9)
49 #define CCR_SPI (1 << 8)
50 #define CCR_8BIT (1 << 7)
51 #define CCR_16BIT (1 << 6)
52 #define CCR_32BIT (1 << 5)
53 #define CCR_SHARED (1 << 4)
54 #define CCR_32PIN (1 << 0)
56 /* MAC address registers */
62 #define OBCR_ODS_16MA (1 << 6)
65 #define EEPCR_EESA (1 << 4)
66 #define EEPCR_EESB (1 << 3)
67 #define EEPCR_EEDO (1 << 2)
68 #define EEPCR_EESCK (1 << 1)
69 #define EEPCR_EECS (1 << 0)
72 #define MBIR_TXMBF (1 << 12)
73 #define MBIR_TXMBFA (1 << 11)
74 #define MBIR_RXMBF (1 << 4)
75 #define MBIR_RXMBFA (1 << 3)
78 #define GRR_QMU (1 << 1)
79 #define GRR_GSR (1 << 0)
82 #define WFCR_MPRXE (1 << 7)
83 #define WFCR_WF3E (1 << 3)
84 #define WFCR_WF2E (1 << 2)
85 #define WFCR_WF1E (1 << 1)
86 #define WFCR_WF0E (1 << 0)
88 #define KS_WF0CRC0 0x30
89 #define KS_WF0CRC1 0x32
90 #define KS_WF0BM0 0x34
91 #define KS_WF0BM1 0x36
92 #define KS_WF0BM2 0x38
93 #define KS_WF0BM3 0x3A
95 #define KS_WF1CRC0 0x40
96 #define KS_WF1CRC1 0x42
97 #define KS_WF1BM0 0x44
98 #define KS_WF1BM1 0x46
99 #define KS_WF1BM2 0x48
100 #define KS_WF1BM3 0x4A
102 #define KS_WF2CRC0 0x50
103 #define KS_WF2CRC1 0x52
104 #define KS_WF2BM0 0x54
105 #define KS_WF2BM1 0x56
106 #define KS_WF2BM2 0x58
107 #define KS_WF2BM3 0x5A
109 #define KS_WF3CRC0 0x60
110 #define KS_WF3CRC1 0x62
111 #define KS_WF3BM0 0x64
112 #define KS_WF3BM1 0x66
113 #define KS_WF3BM2 0x68
114 #define KS_WF3BM3 0x6A
117 #define TXCR_TCGICMP (1 << 8)
118 #define TXCR_TCGUDP (1 << 7)
119 #define TXCR_TCGTCP (1 << 6)
120 #define TXCR_TCGIP (1 << 5)
121 #define TXCR_FTXQ (1 << 4)
122 #define TXCR_TXFCE (1 << 3)
123 #define TXCR_TXPE (1 << 2)
124 #define TXCR_TXCRC (1 << 1)
125 #define TXCR_TXE (1 << 0)
128 #define TXSR_TXLC (1 << 13)
129 #define TXSR_TXMC (1 << 12)
130 #define TXSR_TXFID_MASK (0x3f << 0)
131 #define TXSR_TXFID_SHIFT (0)
132 #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
135 #define KS_RXCR1 0x74
136 #define RXCR1_FRXQ (1 << 15)
137 #define RXCR1_RXUDPFCC (1 << 14)
138 #define RXCR1_RXTCPFCC (1 << 13)
139 #define RXCR1_RXIPFCC (1 << 12)
140 #define RXCR1_RXPAFMA (1 << 11)
141 #define RXCR1_RXFCE (1 << 10)
142 #define RXCR1_RXEFE (1 << 9)
143 #define RXCR1_RXMAFMA (1 << 8)
144 #define RXCR1_RXBE (1 << 7)
145 #define RXCR1_RXME (1 << 6)
146 #define RXCR1_RXUE (1 << 5)
147 #define RXCR1_RXAE (1 << 4)
148 #define RXCR1_RXINVF (1 << 1)
149 #define RXCR1_RXE (1 << 0)
150 #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
151 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
153 #define KS_RXCR2 0x76
154 #define RXCR2_SRDBL_MASK (0x7 << 5)
155 #define RXCR2_SRDBL_SHIFT (5)
156 #define RXCR2_SRDBL_4B (0x0 << 5)
157 #define RXCR2_SRDBL_8B (0x1 << 5)
158 #define RXCR2_SRDBL_16B (0x2 << 5)
159 #define RXCR2_SRDBL_32B (0x3 << 5)
160 /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
161 #define RXCR2_IUFFP (1 << 4)
162 #define RXCR2_RXIUFCEZ (1 << 3)
163 #define RXCR2_UDPLFE (1 << 2)
164 #define RXCR2_RXICMPFCC (1 << 1)
165 #define RXCR2_RXSAF (1 << 0)
167 #define KS_TXMIR 0x78
169 #define KS_RXFHSR 0x7C
170 #define RXFSHR_RXFV (1 << 15)
171 #define RXFSHR_RXICMPFCS (1 << 13)
172 #define RXFSHR_RXIPFCS (1 << 12)
173 #define RXFSHR_RXTCPFCS (1 << 11)
174 #define RXFSHR_RXUDPFCS (1 << 10)
175 #define RXFSHR_RXBF (1 << 7)
176 #define RXFSHR_RXMF (1 << 6)
177 #define RXFSHR_RXUF (1 << 5)
178 #define RXFSHR_RXMR (1 << 4)
179 #define RXFSHR_RXFT (1 << 3)
180 #define RXFSHR_RXFTL (1 << 2)
181 #define RXFSHR_RXRF (1 << 1)
182 #define RXFSHR_RXCE (1 << 0)
183 #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
184 RXFSHR_RXFTL | RXFSHR_RXMR |\
185 RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
187 #define KS_RXFHBCR 0x7E
188 #define RXFHBCR_CNT_MASK 0x0FFF
190 #define KS_TXQCR 0x80
191 #define TXQCR_AETFE (1 << 2)
192 #define TXQCR_TXQMAM (1 << 1)
193 #define TXQCR_METFE (1 << 0)
195 #define KS_RXQCR 0x82
196 #define RXQCR_RXDTTS (1 << 12)
197 #define RXQCR_RXDBCTS (1 << 11)
198 #define RXQCR_RXFCTS (1 << 10)
199 #define RXQCR_RXIPHTOE (1 << 9)
200 #define RXQCR_RXDTTE (1 << 7)
201 #define RXQCR_RXDBCTE (1 << 6)
202 #define RXQCR_RXFCTE (1 << 5)
203 #define RXQCR_ADRFE (1 << 4)
204 #define RXQCR_SDA (1 << 3)
205 #define RXQCR_RRXEF (1 << 0)
206 #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
208 #define KS_TXFDPR 0x84
209 #define TXFDPR_TXFPAI (1 << 14)
210 #define TXFDPR_TXFP_MASK (0x7ff << 0)
211 #define TXFDPR_TXFP_SHIFT (0)
213 #define KS_RXFDPR 0x86
214 #define RXFDPR_RXFPAI (1 << 14)
216 #define KS_RXDTTR 0x8C
217 #define KS_RXDBCTR 0x8E
221 #define IRQ_LCI (1 << 15)
222 #define IRQ_TXI (1 << 14)
223 #define IRQ_RXI (1 << 13)
224 #define IRQ_RXOI (1 << 11)
225 #define IRQ_TXPSI (1 << 9)
226 #define IRQ_RXPSI (1 << 8)
227 #define IRQ_TXSAI (1 << 6)
228 #define IRQ_RXWFDI (1 << 5)
229 #define IRQ_RXMPDI (1 << 4)
230 #define IRQ_LDI (1 << 3)
231 #define IRQ_EDI (1 << 2)
232 #define IRQ_SPIBEI (1 << 1)
233 #define IRQ_DEDI (1 << 0)
235 #define KS_RXFCTR 0x9C
236 #define RXFCTR_THRESHOLD_MASK 0x00FF
239 #define RXFCTR_RXFC_MASK (0xff << 8)
240 #define RXFCTR_RXFC_SHIFT (8)
241 #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
242 #define RXFCTR_RXFCT_MASK (0xff << 0)
243 #define RXFCTR_RXFCT_SHIFT (0)
245 #define KS_TXNTFSR 0x9E
247 #define KS_MAHTR0 0xA0
248 #define KS_MAHTR1 0xA2
249 #define KS_MAHTR2 0xA4
250 #define KS_MAHTR3 0xA6
252 #define KS_FCLWR 0xB0
253 #define KS_FCHWR 0xB2
254 #define KS_FCOWR 0xB4
256 #define KS_CIDER 0xC0
257 #define CIDER_ID 0x8870
258 #define CIDER_REV_MASK (0x7 << 1)
259 #define CIDER_REV_SHIFT (1)
260 #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
264 #define IACR_RDEN (1 << 12)
265 #define IACR_TSEL_MASK (0x3 << 10)
266 #define IACR_TSEL_SHIFT (10)
267 #define IACR_TSEL_MIB (0x3 << 10)
268 #define IACR_ADDR_MASK (0x1f << 0)
269 #define IACR_ADDR_SHIFT (0)
271 #define KS_IADLR 0xD0
272 #define KS_IAHDR 0xD2
274 #define KS_PMECR 0xD4
275 #define PMECR_PME_DELAY (1 << 14)
276 #define PMECR_PME_POL (1 << 12)
277 #define PMECR_WOL_WAKEUP (1 << 11)
278 #define PMECR_WOL_MAGICPKT (1 << 10)
279 #define PMECR_WOL_LINKUP (1 << 9)
280 #define PMECR_WOL_ENERGY (1 << 8)
281 #define PMECR_AUTO_WAKE_EN (1 << 7)
282 #define PMECR_WAKEUP_NORMAL (1 << 6)
283 #define PMECR_WKEVT_MASK (0xf << 2)
284 #define PMECR_WKEVT_SHIFT (2)
285 #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
286 #define PMECR_WKEVT_ENERGY (0x1 << 2)
287 #define PMECR_WKEVT_LINK (0x2 << 2)
288 #define PMECR_WKEVT_MAGICPKT (0x4 << 2)
289 #define PMECR_WKEVT_FRAME (0x8 << 2)
290 #define PMECR_PM_MASK (0x3 << 0)
291 #define PMECR_PM_SHIFT (0)
292 #define PMECR_PM_NORMAL (0x0 << 0)
293 #define PMECR_PM_ENERGY (0x1 << 0)
294 #define PMECR_PM_SOFTDOWN (0x2 << 0)
295 #define PMECR_PM_POWERSAVE (0x3 << 0)
297 /* Standard MII PHY data */
298 #define KS_P1MBCR 0xE4
299 #define P1MBCR_FORCE_FDX (1 << 8)
301 #define KS_P1MBSR 0xE6
302 #define P1MBSR_AN_COMPLETE (1 << 5)
303 #define P1MBSR_AN_CAPABLE (1 << 3)
304 #define P1MBSR_LINK_UP (1 << 2)
306 #define KS_PHY1ILR 0xE8
307 #define KS_PHY1IHR 0xEA
308 #define KS_P1ANAR 0xEC
309 #define KS_P1ANLPR 0xEE
311 #define KS_P1SCLMD 0xF4
312 #define P1SCLMD_LEDOFF (1 << 15)
313 #define P1SCLMD_TXIDS (1 << 14)
314 #define P1SCLMD_RESTARTAN (1 << 13)
315 #define P1SCLMD_DISAUTOMDIX (1 << 10)
316 #define P1SCLMD_FORCEMDIX (1 << 9)
317 #define P1SCLMD_AUTONEGEN (1 << 7)
318 #define P1SCLMD_FORCE100 (1 << 6)
319 #define P1SCLMD_FORCEFDX (1 << 5)
320 #define P1SCLMD_ADV_FLOW (1 << 4)
321 #define P1SCLMD_ADV_100BT_FDX (1 << 3)
322 #define P1SCLMD_ADV_100BT_HDX (1 << 2)
323 #define P1SCLMD_ADV_10BT_FDX (1 << 1)
324 #define P1SCLMD_ADV_10BT_HDX (1 << 0)
327 #define P1CR_HP_MDIX (1 << 15)
328 #define P1CR_REV_POL (1 << 13)
329 #define P1CR_OP_100M (1 << 10)
330 #define P1CR_OP_FDX (1 << 9)
331 #define P1CR_OP_MDI (1 << 7)
332 #define P1CR_AN_DONE (1 << 6)
333 #define P1CR_LINK_GOOD (1 << 5)
334 #define P1CR_PNTR_FLOW (1 << 4)
335 #define P1CR_PNTR_100BT_FDX (1 << 3)
336 #define P1CR_PNTR_100BT_HDX (1 << 2)
337 #define P1CR_PNTR_10BT_FDX (1 << 1)
338 #define P1CR_PNTR_10BT_HDX (1 << 0)
340 /* TX Frame control */
342 #define TXFR_TXIC (1 << 15)
343 #define TXFR_TXFID_MASK (0x3f << 0)
344 #define TXFR_TXFID_SHIFT (0)
347 #define P1SR_HP_MDIX (1 << 15)
348 #define P1SR_REV_POL (1 << 13)
349 #define P1SR_OP_100M (1 << 10)
350 #define P1SR_OP_FDX (1 << 9)
351 #define P1SR_OP_MDI (1 << 7)
352 #define P1SR_AN_DONE (1 << 6)
353 #define P1SR_LINK_GOOD (1 << 5)
354 #define P1SR_PNTR_FLOW (1 << 4)
355 #define P1SR_PNTR_100BT_FDX (1 << 3)
356 #define P1SR_PNTR_100BT_HDX (1 << 2)
357 #define P1SR_PNTR_10BT_FDX (1 << 1)
358 #define P1SR_PNTR_10BT_HDX (1 << 0)
360 #define ENUM_BUS_NONE 0
361 #define ENUM_BUS_8BIT 1
362 #define ENUM_BUS_16BIT 2
363 #define ENUM_BUS_32BIT 3
365 #define MAX_MCAST_LST 32
366 #define HW_MCAST_SIZE 8
369 * union ks_tx_hdr - tx header data
370 * @txb: The header as bytes
371 * @txw: The header as 16bit, little-endian words
373 * A dual representation of the tx header data to allow
374 * access to individual bytes, and to allow 16bit accesses
375 * with 16bit alignment.
383 * struct ks_net - KS8851 driver private data
384 * @net_device : The network device we're bound to
385 * @hw_addr : start address of data register.
386 * @hw_addr_cmd : start address of command register.
387 * @txh : temporaly buffer to save status/length.
388 * @lock : Lock to ensure that the device is not accessed when busy.
389 * @pdev : Pointer to platform device.
390 * @mii : The MII state information for the mii calls.
391 * @frame_head_info : frame header information for multi-pkt rx.
392 * @statelock : Lock on this structure for tx list.
393 * @msg_enable : The message flags controlling driver output (see ethtool).
394 * @frame_cnt : number of frames received.
395 * @bus_width : i/o bus width.
396 * @rc_rxqcr : Cached copy of KS_RXQCR.
397 * @rc_txcr : Cached copy of KS_TXCR.
398 * @rc_ier : Cached copy of KS_IER.
399 * @sharedbus : Multipex(addr and data bus) mode indicator.
400 * @cmd_reg_cache : command register cached.
401 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
402 * @promiscuous : promiscuous mode indicator.
403 * @all_mcast : mutlicast indicator.
404 * @mcast_lst_size : size of multicast list.
405 * @mcast_lst : multicast list.
406 * @mcast_bits : multicast enabed.
407 * @mac_addr : MAC address assigned to this device.
409 * @extra_byte : number of extra byte prepended rx pkt.
410 * @enabled : indicator this device works.
412 * The @lock ensures that the chip is protected when certain operations are
413 * in progress. When the read or write packet transfer is in progress, most
414 * of the chip registers are not accessible until the transfer is finished and
415 * the DMA has been de-asserted.
417 * The @statelock is used to protect information in the structure which may
418 * need to be accessed via several sources, such as the network driver layer
419 * or one of the work queues.
423 /* Receive multiplex framer header info */
424 struct type_frame_head {
425 u16 sts; /* Frame status */
426 u16 len; /* Byte count */
430 struct net_device *netdev;
431 void __iomem *hw_addr;
432 void __iomem *hw_addr_cmd;
433 union ks_tx_hdr txh ____cacheline_aligned;
434 struct mutex lock; /* spinlock to be interrupt safe */
435 struct platform_device *pdev;
436 struct mii_if_info mii;
437 struct type_frame_head *frame_head_info;
438 spinlock_t statelock;
448 u16 cmd_reg_cache_int;
452 u8 mcast_lst[MAX_MCAST_LST][ETH_ALEN];
453 u8 mcast_bits[HW_MCAST_SIZE];
460 static int msg_enable;
462 #define BE3 0x8000 /* Byte Enable 3 */
463 #define BE2 0x4000 /* Byte Enable 2 */
464 #define BE1 0x2000 /* Byte Enable 1 */
465 #define BE0 0x1000 /* Byte Enable 0 */
467 /* register read/write calls.
469 * All these calls issue transactions to access the chip's registers. They
470 * all require that the necessary lock is held to prevent accesses when the
471 * chip is busy transferring packet data (RX/TX FIFO accesses).
475 * ks_rdreg8 - read 8 bit register from device
476 * @ks : The chip information
477 * @offset: The register address
479 * Read a 8bit register from the chip, returning the result
481 static u8 ks_rdreg8(struct ks_net *ks, int offset)
484 u8 shift_bit = offset & 0x03;
485 u8 shift_data = (offset & 1) << 3;
486 ks->cmd_reg_cache = (u16) offset | (u16)(BE0 << shift_bit);
487 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
488 data = ioread16(ks->hw_addr);
489 return (u8)(data >> shift_data);
493 * ks_rdreg16 - read 16 bit register from device
494 * @ks : The chip information
495 * @offset: The register address
497 * Read a 16bit register from the chip, returning the result
500 static u16 ks_rdreg16(struct ks_net *ks, int offset)
502 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
503 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
504 return ioread16(ks->hw_addr);
508 * ks_wrreg8 - write 8bit register value to chip
509 * @ks: The chip information
510 * @offset: The register address
511 * @value: The value to write
514 static void ks_wrreg8(struct ks_net *ks, int offset, u8 value)
516 u8 shift_bit = (offset & 0x03);
517 u16 value_write = (u16)(value << ((offset & 1) << 3));
518 ks->cmd_reg_cache = (u16)offset | (BE0 << shift_bit);
519 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
520 iowrite16(value_write, ks->hw_addr);
524 * ks_wrreg16 - write 16bit register value to chip
525 * @ks: The chip information
526 * @offset: The register address
527 * @value: The value to write
531 static void ks_wrreg16(struct ks_net *ks, int offset, u16 value)
533 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
534 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
535 iowrite16(value, ks->hw_addr);
539 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled.
540 * @ks: The chip state
541 * @wptr: buffer address to save data
542 * @len: length in byte to read
545 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
549 *wptr++ = (u16)ioread16(ks->hw_addr);
553 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
554 * @ks: The chip information
555 * @wptr: buffer address
556 * @len: length in byte to write
559 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
563 iowrite16(*wptr++, ks->hw_addr);
566 static void ks_disable_int(struct ks_net *ks)
568 ks_wrreg16(ks, KS_IER, 0x0000);
569 } /* ks_disable_int */
571 static void ks_enable_int(struct ks_net *ks)
573 ks_wrreg16(ks, KS_IER, ks->rc_ier);
574 } /* ks_enable_int */
577 * ks_tx_fifo_space - return the available hardware buffer size.
578 * @ks: The chip information
581 static inline u16 ks_tx_fifo_space(struct ks_net *ks)
583 return ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
587 * ks_save_cmd_reg - save the command register from the cache.
588 * @ks: The chip information
591 static inline void ks_save_cmd_reg(struct ks_net *ks)
593 /*ks8851 MLL has a bug to read back the command register.
594 * So rely on software to save the content of command register.
596 ks->cmd_reg_cache_int = ks->cmd_reg_cache;
600 * ks_restore_cmd_reg - restore the command register from the cache and
601 * write to hardware register.
602 * @ks: The chip information
605 static inline void ks_restore_cmd_reg(struct ks_net *ks)
607 ks->cmd_reg_cache = ks->cmd_reg_cache_int;
608 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
612 * ks_set_powermode - set power mode of the device
613 * @ks: The chip information
614 * @pwrmode: The power mode value to write to KS_PMECR.
616 * Change the power mode of the chip.
618 static void ks_set_powermode(struct ks_net *ks, unsigned pwrmode)
622 netif_dbg(ks, hw, ks->netdev, "setting power mode %d\n", pwrmode);
624 ks_rdreg16(ks, KS_GRR);
625 pmecr = ks_rdreg16(ks, KS_PMECR);
626 pmecr &= ~PMECR_PM_MASK;
629 ks_wrreg16(ks, KS_PMECR, pmecr);
633 * ks_read_config - read chip configuration of bus width.
634 * @ks: The chip information
637 static void ks_read_config(struct ks_net *ks)
641 /* Regardless of bus width, 8 bit read should always work.*/
642 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
643 reg_data |= ks_rdreg8(ks, KS_CCR+1) << 8;
645 /* addr/data bus are multiplexed */
646 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
648 /* There are garbage data when reading data from QMU,
649 depending on bus-width.
652 if (reg_data & CCR_8BIT) {
653 ks->bus_width = ENUM_BUS_8BIT;
655 } else if (reg_data & CCR_16BIT) {
656 ks->bus_width = ENUM_BUS_16BIT;
659 ks->bus_width = ENUM_BUS_32BIT;
665 * ks_soft_reset - issue one of the soft reset to the device
666 * @ks: The device state.
667 * @op: The bit(s) to set in the GRR
669 * Issue the relevant soft-reset command to the device's GRR register
672 * Note, the delays are in there as a caution to ensure that the reset
673 * has time to take effect and then complete. Since the datasheet does
674 * not currently specify the exact sequence, we have chosen something
675 * that seems to work with our device.
677 static void ks_soft_reset(struct ks_net *ks, unsigned op)
679 /* Disable interrupt first */
680 ks_wrreg16(ks, KS_IER, 0x0000);
681 ks_wrreg16(ks, KS_GRR, op);
682 mdelay(10); /* wait a short time to effect reset */
683 ks_wrreg16(ks, KS_GRR, 0);
684 mdelay(1); /* wait for condition to clear */
688 void ks_enable_qmu(struct ks_net *ks)
692 w = ks_rdreg16(ks, KS_TXCR);
693 /* Enables QMU Transmit (TXCR). */
694 ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
697 * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
701 w = ks_rdreg16(ks, KS_RXQCR);
702 ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
704 /* Enables QMU Receive (RXCR1). */
705 w = ks_rdreg16(ks, KS_RXCR1);
706 ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
708 } /* ks_enable_qmu */
710 static void ks_disable_qmu(struct ks_net *ks)
714 w = ks_rdreg16(ks, KS_TXCR);
716 /* Disables QMU Transmit (TXCR). */
718 ks_wrreg16(ks, KS_TXCR, w);
720 /* Disables QMU Receive (RXCR1). */
721 w = ks_rdreg16(ks, KS_RXCR1);
723 ks_wrreg16(ks, KS_RXCR1, w);
727 } /* ks_disable_qmu */
730 * ks_read_qmu - read 1 pkt data from the QMU.
731 * @ks: The chip information
732 * @buf: buffer address to save 1 pkt
734 * Here is the sequence to read 1 pkt:
735 * 1. set sudo DMA mode
736 * 2. read prepend data
738 * 4. reset sudo DMA Mode
740 static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
742 u32 r = ks->extra_byte & 0x1 ;
743 u32 w = ks->extra_byte - r;
745 /* 1. set sudo DMA mode */
746 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
747 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
749 /* 2. read prepend data */
751 * read 4 + extra bytes and discard them.
752 * extra bytes for dummy, 2 for status, 2 for len
755 /* use likely(r) for 8 bit access for performance */
757 ioread8(ks->hw_addr);
758 ks_inblk(ks, buf, w + 2 + 2);
760 /* 3. read pkt data */
761 ks_inblk(ks, buf, ALIGN(len, 4));
763 /* 4. reset sudo DMA Mode */
764 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
768 * ks_rcv - read multiple pkts data from the QMU.
769 * @ks: The chip information
770 * @netdev: The network device being opened.
772 * Read all of header information before reading pkt content.
773 * It is not allowed only port of pkts in QMU after issuing
776 static void ks_rcv(struct ks_net *ks, struct net_device *netdev)
779 struct type_frame_head *frame_hdr = ks->frame_head_info;
782 ks->frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8;
784 /* read all header information */
785 for (i = 0; i < ks->frame_cnt; i++) {
786 /* Checking Received packet status */
787 frame_hdr->sts = ks_rdreg16(ks, KS_RXFHSR);
788 /* Get packet len from hardware */
789 frame_hdr->len = ks_rdreg16(ks, KS_RXFHBCR);
793 frame_hdr = ks->frame_head_info;
794 while (ks->frame_cnt--) {
795 skb = netdev_alloc_skb(netdev, frame_hdr->len + 16);
796 if (likely(skb && (frame_hdr->sts & RXFSHR_RXFV) &&
797 (frame_hdr->len < RX_BUF_SIZE) && frame_hdr->len)) {
799 /* read data block including CRC 4 bytes */
800 ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len);
801 skb_put(skb, frame_hdr->len);
802 skb->protocol = eth_type_trans(skb, netdev);
805 pr_err("%s: err:skb alloc\n", __func__);
806 ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
808 dev_kfree_skb_irq(skb);
815 * ks_update_link_status - link status update.
816 * @netdev: The network device being opened.
817 * @ks: The chip information
821 static void ks_update_link_status(struct net_device *netdev, struct ks_net *ks)
823 /* check the status of the link */
825 if (ks_rdreg16(ks, KS_P1SR) & P1SR_LINK_GOOD) {
826 netif_carrier_on(netdev);
827 link_up_status = true;
829 netif_carrier_off(netdev);
830 link_up_status = false;
832 netif_dbg(ks, link, ks->netdev,
833 "%s: %s\n", __func__, link_up_status ? "UP" : "DOWN");
837 * ks_irq - device interrupt handler
838 * @irq: Interrupt number passed from the IRQ handler.
839 * @pw: The private word passed to register_irq(), our struct ks_net.
841 * This is the handler invoked to find out what happened
843 * Read the interrupt status, work out what needs to be done and then clear
844 * any of the interrupts that are not needed.
847 static irqreturn_t ks_irq(int irq, void *pw)
849 struct net_device *netdev = pw;
850 struct ks_net *ks = netdev_priv(netdev);
853 /*this should be the first in IRQ handler */
856 status = ks_rdreg16(ks, KS_ISR);
857 if (unlikely(!status)) {
858 ks_restore_cmd_reg(ks);
862 ks_wrreg16(ks, KS_ISR, status);
864 if (likely(status & IRQ_RXI))
867 if (unlikely(status & IRQ_LCI))
868 ks_update_link_status(netdev, ks);
870 if (unlikely(status & IRQ_TXI))
871 netif_wake_queue(netdev);
873 if (unlikely(status & IRQ_LDI)) {
875 u16 pmecr = ks_rdreg16(ks, KS_PMECR);
876 pmecr &= ~PMECR_WKEVT_MASK;
877 ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
880 /* this should be the last in IRQ handler*/
881 ks_restore_cmd_reg(ks);
887 * ks_net_open - open network device
888 * @netdev: The network device being opened.
890 * Called when the network device is marked active, such as a user executing
891 * 'ifconfig up' on the device.
893 static int ks_net_open(struct net_device *netdev)
895 struct ks_net *ks = netdev_priv(netdev);
898 #define KS_INT_FLAGS (IRQF_DISABLED|IRQF_TRIGGER_LOW)
899 /* lock the card, even if we may not actually do anything
900 * else at the moment.
903 netif_dbg(ks, ifup, ks->netdev, "%s - entry\n", __func__);
906 err = request_irq(netdev->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, netdev);
909 pr_err("Failed to request IRQ: %d: %d\n", netdev->irq, err);
913 /* wake up powermode to normal mode */
914 ks_set_powermode(ks, PMECR_PM_NORMAL);
915 mdelay(1); /* wait for normal mode to take effect */
917 ks_wrreg16(ks, KS_ISR, 0xffff);
920 netif_start_queue(ks->netdev);
922 netif_dbg(ks, ifup, ks->netdev, "network device up\n");
928 * ks_net_stop - close network device
929 * @netdev: The device being closed.
931 * Called to close down a network device which has been active. Cancell any
932 * work, shutdown the RX and TX process and then place the chip into a low
933 * power state whilst it is not being used.
935 static int ks_net_stop(struct net_device *netdev)
937 struct ks_net *ks = netdev_priv(netdev);
939 netif_info(ks, ifdown, netdev, "shutting down\n");
941 netif_stop_queue(netdev);
943 mutex_lock(&ks->lock);
945 /* turn off the IRQs and ack any outstanding */
946 ks_wrreg16(ks, KS_IER, 0x0000);
947 ks_wrreg16(ks, KS_ISR, 0xffff);
949 /* shutdown RX/TX QMU */
952 /* set powermode to soft power down to save power */
953 ks_set_powermode(ks, PMECR_PM_SOFTDOWN);
954 free_irq(netdev->irq, netdev);
955 mutex_unlock(&ks->lock);
961 * ks_write_qmu - write 1 pkt data to the QMU.
962 * @ks: The chip information
963 * @pdata: buffer address to save 1 pkt
964 * @len: Pkt length in byte
965 * Here is the sequence to write 1 pkt:
966 * 1. set sudo DMA mode
967 * 2. write status/length
969 * 4. reset sudo DMA Mode
970 * 5. reset sudo DMA mode
971 * 6. Wait until pkt is out
973 static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
975 /* start header at txb[0] to align txw entries */
977 ks->txh.txw[1] = cpu_to_le16(len);
979 /* 1. set sudo-DMA mode */
980 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
981 /* 2. write status/lenth info */
982 ks_outblk(ks, ks->txh.txw, 4);
983 /* 3. write pkt data */
984 ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
985 /* 4. reset sudo-DMA mode */
986 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
987 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
988 ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
989 /* 6. wait until TXQCR_METFE is auto-cleared */
990 while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE)
995 * ks_start_xmit - transmit packet
996 * @skb : The buffer to transmit
997 * @netdev : The device used to transmit the packet.
999 * Called by the network layer to transmit the @skb.
1000 * spin_lock_irqsave is required because tx and rx should be mutual exclusive.
1001 * So while tx is in-progress, prevent IRQ interrupt from happenning.
1003 static int ks_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1005 int retv = NETDEV_TX_OK;
1006 struct ks_net *ks = netdev_priv(netdev);
1008 disable_irq(netdev->irq);
1010 spin_lock(&ks->statelock);
1012 /* Extra space are required:
1013 * 4 byte for alignment, 4 for status/length, 4 for CRC
1016 if (likely(ks_tx_fifo_space(ks) >= skb->len + 12)) {
1017 ks_write_qmu(ks, skb->data, skb->len);
1020 retv = NETDEV_TX_BUSY;
1021 spin_unlock(&ks->statelock);
1023 enable_irq(netdev->irq);
1028 * ks_start_rx - ready to serve pkts
1029 * @ks : The chip information
1032 static void ks_start_rx(struct ks_net *ks)
1036 /* Enables QMU Receive (RXCR1). */
1037 cntl = ks_rdreg16(ks, KS_RXCR1);
1039 ks_wrreg16(ks, KS_RXCR1, cntl);
1043 * ks_stop_rx - stop to serve pkts
1044 * @ks : The chip information
1047 static void ks_stop_rx(struct ks_net *ks)
1051 /* Disables QMU Receive (RXCR1). */
1052 cntl = ks_rdreg16(ks, KS_RXCR1);
1053 cntl &= ~RXCR1_RXE ;
1054 ks_wrreg16(ks, KS_RXCR1, cntl);
1058 static unsigned long const ethernet_polynomial = 0x04c11db7U;
1060 static unsigned long ether_gen_crc(int length, u8 *data)
1063 while (--length >= 0) {
1064 u8 current_octet = *data++;
1067 for (bit = 0; bit < 8; bit++, current_octet >>= 1) {
1069 ((crc < 0) ^ (current_octet & 1) ?
1070 ethernet_polynomial : 0);
1073 return (unsigned long)crc;
1074 } /* ether_gen_crc */
1077 * ks_set_grpaddr - set multicast information
1078 * @ks : The chip information
1081 static void ks_set_grpaddr(struct ks_net *ks)
1084 u32 index, position, value;
1086 memset(ks->mcast_bits, 0, sizeof(u8) * HW_MCAST_SIZE);
1088 for (i = 0; i < ks->mcast_lst_size; i++) {
1089 position = (ether_gen_crc(6, ks->mcast_lst[i]) >> 26) & 0x3f;
1090 index = position >> 3;
1091 value = 1 << (position & 7);
1092 ks->mcast_bits[index] |= (u8)value;
1095 for (i = 0; i < HW_MCAST_SIZE; i++) {
1097 ks_wrreg16(ks, (u16)((KS_MAHTR0 + i) & ~1),
1098 (ks->mcast_bits[i] << 8) |
1099 ks->mcast_bits[i - 1]);
1102 } /* ks_set_grpaddr */
1105 * ks_clear_mcast - clear multicast information
1107 * @ks : The chip information
1108 * This routine removes all mcast addresses set in the hardware.
1111 static void ks_clear_mcast(struct ks_net *ks)
1114 for (i = 0; i < HW_MCAST_SIZE; i++)
1115 ks->mcast_bits[i] = 0;
1117 mcast_size = HW_MCAST_SIZE >> 2;
1118 for (i = 0; i < mcast_size; i++)
1119 ks_wrreg16(ks, KS_MAHTR0 + (2*i), 0);
1122 static void ks_set_promis(struct ks_net *ks, u16 promiscuous_mode)
1125 ks->promiscuous = promiscuous_mode;
1126 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1127 cntl = ks_rdreg16(ks, KS_RXCR1);
1129 cntl &= ~RXCR1_FILTER_MASK;
1130 if (promiscuous_mode)
1131 /* Enable Promiscuous mode */
1132 cntl |= RXCR1_RXAE | RXCR1_RXINVF;
1134 /* Disable Promiscuous mode (default normal mode) */
1135 cntl |= RXCR1_RXPAFMA;
1137 ks_wrreg16(ks, KS_RXCR1, cntl);
1142 } /* ks_set_promis */
1144 static void ks_set_mcast(struct ks_net *ks, u16 mcast)
1148 ks->all_mcast = mcast;
1149 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1150 cntl = ks_rdreg16(ks, KS_RXCR1);
1151 cntl &= ~RXCR1_FILTER_MASK;
1153 /* Enable "Perfect with Multicast address passed mode" */
1154 cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1157 * Disable "Perfect with Multicast address passed
1158 * mode" (normal mode).
1160 cntl |= RXCR1_RXPAFMA;
1162 ks_wrreg16(ks, KS_RXCR1, cntl);
1166 } /* ks_set_mcast */
1168 static void ks_set_rx_mode(struct net_device *netdev)
1170 struct ks_net *ks = netdev_priv(netdev);
1171 struct netdev_hw_addr *ha;
1173 /* Turn on/off promiscuous mode. */
1174 if ((netdev->flags & IFF_PROMISC) == IFF_PROMISC)
1176 (u16)((netdev->flags & IFF_PROMISC) == IFF_PROMISC));
1177 /* Turn on/off all mcast mode. */
1178 else if ((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI)
1180 (u16)((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI));
1182 ks_set_promis(ks, false);
1184 if ((netdev->flags & IFF_MULTICAST) && netdev_mc_count(netdev)) {
1185 if (netdev_mc_count(netdev) <= MAX_MCAST_LST) {
1188 netdev_for_each_mc_addr(ha, netdev) {
1189 if (i >= MAX_MCAST_LST)
1191 memcpy(ks->mcast_lst[i++], ha->addr, ETH_ALEN);
1193 ks->mcast_lst_size = (u8)i;
1197 * List too big to support so
1198 * turn on all mcast mode.
1200 ks->mcast_lst_size = MAX_MCAST_LST;
1201 ks_set_mcast(ks, true);
1204 ks->mcast_lst_size = 0;
1207 } /* ks_set_rx_mode */
1209 static void ks_set_mac(struct ks_net *ks, u8 *data)
1211 u16 *pw = (u16 *)data;
1214 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1217 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1218 ks_wrreg16(ks, KS_MARH, w);
1221 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1222 ks_wrreg16(ks, KS_MARM, w);
1225 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1226 ks_wrreg16(ks, KS_MARL, w);
1228 memcpy(ks->mac_addr, data, 6);
1234 static int ks_set_mac_address(struct net_device *netdev, void *paddr)
1236 struct ks_net *ks = netdev_priv(netdev);
1237 struct sockaddr *addr = paddr;
1240 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1242 da = (u8 *)netdev->dev_addr;
1248 static int ks_net_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
1250 struct ks_net *ks = netdev_priv(netdev);
1252 if (!netif_running(netdev))
1255 return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL);
1258 static const struct net_device_ops ks_netdev_ops = {
1259 .ndo_open = ks_net_open,
1260 .ndo_stop = ks_net_stop,
1261 .ndo_do_ioctl = ks_net_ioctl,
1262 .ndo_start_xmit = ks_start_xmit,
1263 .ndo_set_mac_address = ks_set_mac_address,
1264 .ndo_set_rx_mode = ks_set_rx_mode,
1265 .ndo_change_mtu = eth_change_mtu,
1266 .ndo_validate_addr = eth_validate_addr,
1269 /* ethtool support */
1271 static void ks_get_drvinfo(struct net_device *netdev,
1272 struct ethtool_drvinfo *di)
1274 strlcpy(di->driver, DRV_NAME, sizeof(di->driver));
1275 strlcpy(di->version, "1.00", sizeof(di->version));
1276 strlcpy(di->bus_info, dev_name(netdev->dev.parent),
1277 sizeof(di->bus_info));
1280 static u32 ks_get_msglevel(struct net_device *netdev)
1282 struct ks_net *ks = netdev_priv(netdev);
1283 return ks->msg_enable;
1286 static void ks_set_msglevel(struct net_device *netdev, u32 to)
1288 struct ks_net *ks = netdev_priv(netdev);
1289 ks->msg_enable = to;
1292 static int ks_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1294 struct ks_net *ks = netdev_priv(netdev);
1295 return mii_ethtool_gset(&ks->mii, cmd);
1298 static int ks_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1300 struct ks_net *ks = netdev_priv(netdev);
1301 return mii_ethtool_sset(&ks->mii, cmd);
1304 static u32 ks_get_link(struct net_device *netdev)
1306 struct ks_net *ks = netdev_priv(netdev);
1307 return mii_link_ok(&ks->mii);
1310 static int ks_nway_reset(struct net_device *netdev)
1312 struct ks_net *ks = netdev_priv(netdev);
1313 return mii_nway_restart(&ks->mii);
1316 static const struct ethtool_ops ks_ethtool_ops = {
1317 .get_drvinfo = ks_get_drvinfo,
1318 .get_msglevel = ks_get_msglevel,
1319 .set_msglevel = ks_set_msglevel,
1320 .get_settings = ks_get_settings,
1321 .set_settings = ks_set_settings,
1322 .get_link = ks_get_link,
1323 .nway_reset = ks_nway_reset,
1326 /* MII interface controls */
1329 * ks_phy_reg - convert MII register into a KS8851 register
1330 * @reg: MII register number.
1332 * Return the KS8851 register number for the corresponding MII PHY register
1333 * if possible. Return zero if the MII register has no direct mapping to the
1334 * KS8851 register set.
1336 static int ks_phy_reg(int reg)
1357 * ks_phy_read - MII interface PHY register read.
1358 * @netdev: The network device the PHY is on.
1359 * @phy_addr: Address of PHY (ignored as we only have one)
1360 * @reg: The register to read.
1362 * This call reads data from the PHY register specified in @reg. Since the
1363 * device does not support all the MII registers, the non-existent values
1364 * are always returned as zero.
1366 * We return zero for unsupported registers as the MII code does not check
1367 * the value returned for any error status, and simply returns it to the
1368 * caller. The mii-tool that the driver was tested with takes any -ve error
1369 * as real PHY capabilities, thus displaying incorrect data to the user.
1371 static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg)
1373 struct ks_net *ks = netdev_priv(netdev);
1377 ksreg = ks_phy_reg(reg);
1379 return 0x0; /* no error return allowed, so use zero */
1381 mutex_lock(&ks->lock);
1382 result = ks_rdreg16(ks, ksreg);
1383 mutex_unlock(&ks->lock);
1388 static void ks_phy_write(struct net_device *netdev,
1389 int phy, int reg, int value)
1391 struct ks_net *ks = netdev_priv(netdev);
1394 ksreg = ks_phy_reg(reg);
1396 mutex_lock(&ks->lock);
1397 ks_wrreg16(ks, ksreg, value);
1398 mutex_unlock(&ks->lock);
1403 * ks_read_selftest - read the selftest memory info.
1404 * @ks: The device state
1406 * Read and check the TX/RX memory selftest information.
1408 static int ks_read_selftest(struct ks_net *ks)
1410 unsigned both_done = MBIR_TXMBF | MBIR_RXMBF;
1414 rd = ks_rdreg16(ks, KS_MBIR);
1416 if ((rd & both_done) != both_done) {
1417 netdev_warn(ks->netdev, "Memory selftest not finished\n");
1421 if (rd & MBIR_TXMBFA) {
1422 netdev_err(ks->netdev, "TX memory selftest fails\n");
1426 if (rd & MBIR_RXMBFA) {
1427 netdev_err(ks->netdev, "RX memory selftest fails\n");
1431 netdev_info(ks->netdev, "the selftest passes\n");
1435 static void ks_setup(struct ks_net *ks)
1440 * Configure QMU Transmit
1443 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
1444 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
1446 /* Setup Receive Frame Data Pointer Auto-Increment */
1447 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
1449 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
1450 ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
1452 /* Setup RxQ Command Control (RXQCR) */
1453 ks->rc_rxqcr = RXQCR_CMD_CNTL;
1454 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
1457 * set the force mode to half duplex, default is full duplex
1458 * because if the auto-negotiation fails, most switch uses
1462 w = ks_rdreg16(ks, KS_P1MBCR);
1463 w &= ~P1MBCR_FORCE_FDX;
1464 ks_wrreg16(ks, KS_P1MBCR, w);
1466 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
1467 ks_wrreg16(ks, KS_TXCR, w);
1469 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
1471 if (ks->promiscuous) /* bPromiscuous */
1472 w |= (RXCR1_RXAE | RXCR1_RXINVF);
1473 else if (ks->all_mcast) /* Multicast address passed mode */
1474 w |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1475 else /* Normal mode */
1478 ks_wrreg16(ks, KS_RXCR1, w);
1482 static void ks_setup_int(struct ks_net *ks)
1485 /* Clear the interrupts status of the hardware. */
1486 ks_wrreg16(ks, KS_ISR, 0xffff);
1488 /* Enables the interrupts of the hardware. */
1489 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
1490 } /* ks_setup_int */
1492 static int ks_hw_init(struct ks_net *ks)
1494 #define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
1495 ks->promiscuous = 0;
1497 ks->mcast_lst_size = 0;
1499 ks->frame_head_info = kmalloc(MHEADER_SIZE, GFP_KERNEL);
1500 if (!ks->frame_head_info)
1503 ks_set_mac(ks, KS_DEFAULT_MAC_ADDRESS);
1508 static int ks8851_probe(struct platform_device *pdev)
1511 struct resource *io_d, *io_c;
1512 struct net_device *netdev;
1515 struct ks8851_mll_platform_data *pdata;
1517 io_d = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1518 io_c = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1520 if (!request_mem_region(io_d->start, resource_size(io_d), DRV_NAME))
1521 goto err_mem_region;
1523 if (!request_mem_region(io_c->start, resource_size(io_c), DRV_NAME))
1524 goto err_mem_region1;
1526 netdev = alloc_etherdev(sizeof(struct ks_net));
1528 goto err_alloc_etherdev;
1530 SET_NETDEV_DEV(netdev, &pdev->dev);
1532 ks = netdev_priv(netdev);
1533 ks->netdev = netdev;
1534 ks->hw_addr = ioremap(io_d->start, resource_size(io_d));
1539 ks->hw_addr_cmd = ioremap(io_c->start, resource_size(io_c));
1540 if (!ks->hw_addr_cmd)
1543 netdev->irq = platform_get_irq(pdev, 0);
1545 if ((int)netdev->irq < 0) {
1552 mutex_init(&ks->lock);
1553 spin_lock_init(&ks->statelock);
1555 netdev->netdev_ops = &ks_netdev_ops;
1556 netdev->ethtool_ops = &ks_ethtool_ops;
1558 /* setup mii state */
1559 ks->mii.dev = netdev;
1561 ks->mii.phy_id_mask = 1;
1562 ks->mii.reg_num_mask = 0xf;
1563 ks->mii.mdio_read = ks_phy_read;
1564 ks->mii.mdio_write = ks_phy_write;
1566 netdev_info(netdev, "message enable is %d\n", msg_enable);
1567 /* set the default message enable */
1568 ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV |
1573 /* simple check for a valid chip being connected to the bus */
1574 if ((ks_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
1575 netdev_err(netdev, "failed to read device ID\n");
1580 if (ks_read_selftest(ks)) {
1581 netdev_err(netdev, "failed to read device ID\n");
1586 err = register_netdev(netdev);
1590 platform_set_drvdata(pdev, netdev);
1592 ks_soft_reset(ks, GRR_GSR);
1598 data = ks_rdreg16(ks, KS_OBCR);
1599 ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
1601 /* overwriting the default MAC address */
1602 pdata = pdev->dev.platform_data;
1604 netdev_err(netdev, "No platform data\n");
1608 memcpy(ks->mac_addr, pdata->mac_addr, 6);
1609 if (!is_valid_ether_addr(ks->mac_addr)) {
1610 /* Use random MAC address if none passed */
1611 eth_random_addr(ks->mac_addr);
1612 netdev_info(netdev, "Using random mac address\n");
1614 netdev_info(netdev, "Mac address is: %pM\n", ks->mac_addr);
1616 memcpy(netdev->dev_addr, ks->mac_addr, 6);
1618 ks_set_mac(ks, netdev->dev_addr);
1620 id = ks_rdreg16(ks, KS_CIDER);
1622 netdev_info(netdev, "Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1623 (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7);
1627 unregister_netdev(netdev);
1630 iounmap(ks->hw_addr_cmd);
1632 iounmap(ks->hw_addr);
1634 free_netdev(netdev);
1636 release_mem_region(io_c->start, resource_size(io_c));
1638 release_mem_region(io_d->start, resource_size(io_d));
1643 static int ks8851_remove(struct platform_device *pdev)
1645 struct net_device *netdev = platform_get_drvdata(pdev);
1646 struct ks_net *ks = netdev_priv(netdev);
1647 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1649 kfree(ks->frame_head_info);
1650 unregister_netdev(netdev);
1651 iounmap(ks->hw_addr);
1652 free_netdev(netdev);
1653 release_mem_region(iomem->start, resource_size(iomem));
1654 platform_set_drvdata(pdev, NULL);
1659 static struct platform_driver ks8851_platform_driver = {
1662 .owner = THIS_MODULE,
1664 .probe = ks8851_probe,
1665 .remove = ks8851_remove,
1668 module_platform_driver(ks8851_platform_driver);
1670 MODULE_DESCRIPTION("KS8851 MLL Network driver");
1671 MODULE_AUTHOR("David Choi <david.choi@micrel.com>");
1672 MODULE_LICENSE("GPL");
1673 module_param_named(message, msg_enable, int, 0);
1674 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");