2 * Register map access API - ENCX24J600 support
4 * Copyright 2015 Gridpoint
6 * Author: Jon Ringle <jringle@gridpoint.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/regmap.h>
19 #include <linux/spi/spi.h>
21 #include "encx24j600_hw.h"
23 static inline bool is_bits_set(int value, int mask)
25 return (value & mask) == mask;
28 static int encx24j600_switch_bank(struct encx24j600_context *ctx,
33 int bank_opcode = BANK_SELECT(bank);
34 ret = spi_write(ctx->spi, &bank_opcode, 1);
41 static int encx24j600_cmdn(struct encx24j600_context *ctx, u8 opcode,
42 const void *buf, size_t len)
45 struct spi_transfer t[2] = { { .tx_buf = &opcode, .len = 1, },
46 { .tx_buf = buf, .len = len }, };
48 spi_message_add_tail(&t[0], &m);
49 spi_message_add_tail(&t[1], &m);
51 return spi_sync(ctx->spi, &m);
54 static void regmap_lock_mutex(void *context)
56 struct encx24j600_context *ctx = context;
57 mutex_lock(&ctx->mutex);
60 static void regmap_unlock_mutex(void *context)
62 struct encx24j600_context *ctx = context;
63 mutex_unlock(&ctx->mutex);
66 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val,
69 struct encx24j600_context *ctx = context;
70 u8 banked_reg = reg & ADDR_MASK;
71 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
78 cmd = RCRCODE | banked_reg;
79 if ((banked_reg < 0x16) && (ctx->bank != bank))
80 ret = encx24j600_switch_bank(ctx, bank);
84 /* Translate registers that are more effecient using
97 cmd = RUDARDPT; break;
99 cmd = RUDAWRPT; break;
112 ret = spi_write_then_read(ctx->spi, tx_buf, i, val, len);
117 static int regmap_encx24j600_sfr_update(struct encx24j600_context *ctx,
118 u8 reg, u8 *val, size_t len,
119 u8 unbanked_cmd, u8 banked_code)
121 u8 banked_reg = reg & ADDR_MASK;
122 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
123 u8 cmd = unbanked_cmd;
124 struct spi_message m;
125 struct spi_transfer t[3] = { { .tx_buf = &cmd, .len = sizeof(cmd), },
126 { .tx_buf = ®, .len = sizeof(reg), },
127 { .tx_buf = val, .len = len }, };
131 cmd = banked_code | banked_reg;
132 if ((banked_reg < 0x16) && (ctx->bank != bank))
133 ret = encx24j600_switch_bank(ctx, bank);
137 /* Translate registers that are more effecient using
138 * 3-byte SPI commands
142 cmd = WGPRDPT; break;
144 cmd = WGPWRPT; break;
146 cmd = WRXRDPT; break;
148 cmd = WRXWRPT; break;
150 cmd = WUDARDPT; break;
152 cmd = WUDAWRPT; break;
161 spi_message_init(&m);
162 spi_message_add_tail(&t[0], &m);
164 if (cmd == unbanked_cmd) {
166 spi_message_add_tail(&t[1], &m);
169 spi_message_add_tail(&t[2], &m);
170 return spi_sync(ctx->spi, &m);
173 static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val,
176 struct encx24j600_context *ctx = context;
177 return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE);
180 static int regmap_encx24j600_sfr_set_bits(struct encx24j600_context *ctx,
183 return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE);
186 static int regmap_encx24j600_sfr_clr_bits(struct encx24j600_context *ctx,
189 return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE);
192 static int regmap_encx24j600_reg_update_bits(void *context, unsigned int reg,
194 unsigned int val, bool *change,
197 struct encx24j600_context *ctx = context;
200 unsigned int set_mask = mask & val;
201 unsigned int clr_mask = mask & ~val;
206 if ((reg >= 0x40 && reg < 0x6c) || reg >= 0x80) {
207 /* Must do read/modify/write cycles for
208 * MAC/MII regs or Unbanked SFR regs
212 ret = regmap_encx24j600_sfr_read(context, reg, (u8 *)&orig,
220 if (force_write || (tmp != orig)) {
221 ret = regmap_encx24j600_sfr_write(context, reg,
233 if (set_mask & 0xff) {
234 ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);
235 if (ret == 0 && change)
238 set_mask = (set_mask & 0xff00) >> 8;
240 if ((set_mask & 0xff) && (ret == 0)) {
241 ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);
242 if (ret == 0 && change)
246 if ((clr_mask & 0xff) && (ret == 0)) {
247 ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask);
248 if (ret == 0 && change)
251 clr_mask = (clr_mask & 0xff00) >> 8;
253 if ((clr_mask & 0xff) && (ret == 0)) {
254 ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask);
255 if (ret == 0 && change)
262 int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
265 struct encx24j600_context *ctx = context;
268 return encx24j600_cmdn(ctx, reg, data, count);
270 /* SPI 1-byte command. Ignore data */
271 return spi_write(ctx->spi, ®, 1);
273 EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_write);
275 int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count)
277 struct encx24j600_context *ctx = context;
279 if (reg == RBSEL && count > 1)
282 return spi_write_then_read(ctx->spi, ®, sizeof(reg), data, count);
284 EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_read);
286 static int regmap_encx24j600_write(void *context, const void *data,
289 u8 *dout = (u8 *)data;
295 return regmap_encx24j600_spi_write(context, reg, dout, len);
300 return regmap_encx24j600_sfr_write(context, reg, dout, len);
303 static int regmap_encx24j600_read(void *context,
304 const void *reg_buf, size_t reg_size,
305 void *val, size_t val_size)
307 u8 reg = *(const u8 *)reg_buf;
310 pr_err("%s: reg=%02x reg_size=%zu\n", __func__, reg, reg_size);
315 return regmap_encx24j600_spi_read(context, reg, val, val_size);
318 pr_err("%s: reg=%02x val_size=%zu\n", __func__, reg, val_size);
322 return regmap_encx24j600_sfr_read(context, reg, val, val_size);
325 static bool encx24j600_regmap_readable(struct device *dev, unsigned int reg)
328 ((reg >= 0x40) && (reg < 0x4c)) ||
329 ((reg >= 0x52) && (reg < 0x56)) ||
330 ((reg >= 0x60) && (reg < 0x66)) ||
331 ((reg >= 0x68) && (reg < 0x80)) ||
332 ((reg >= 0x86) && (reg < 0x92)) ||
339 static bool encx24j600_regmap_writeable(struct device *dev, unsigned int reg)
342 ((reg >= 0x14) && (reg < 0x1a)) ||
343 ((reg >= 0x1c) && (reg < 0x36)) ||
344 ((reg >= 0x40) && (reg < 0x4c)) ||
345 ((reg >= 0x52) && (reg < 0x56)) ||
346 ((reg >= 0x60) && (reg < 0x68)) ||
347 ((reg >= 0x6c) && (reg < 0x80)) ||
348 ((reg >= 0x86) && (reg < 0x92)) ||
349 ((reg >= 0xc0) && (reg < 0xc8)) ||
350 ((reg >= 0xca) && (reg < 0xf0)))
356 static bool encx24j600_regmap_volatile(struct device *dev, unsigned int reg)
363 case ECON1: /* Can be modified via single byte cmds */
364 case ECON2: /* Can be modified via single byte cmds */
366 case EIR: /* Can be modified via single byte cmds */
377 static bool encx24j600_regmap_precious(struct device *dev, unsigned int reg)
379 /* single byte cmds are precious */
380 if (((reg >= 0xc0) && (reg < 0xc8)) ||
381 ((reg >= 0xca) && (reg < 0xf0)))
387 static int regmap_encx24j600_phy_reg_read(void *context, unsigned int reg,
390 struct encx24j600_context *ctx = context;
394 reg = MIREGADR_VAL | (reg & PHREG_MASK);
395 ret = regmap_write(ctx->regmap, MIREGADR, reg);
399 ret = regmap_write(ctx->regmap, MICMD, MIIRD);
403 usleep_range(26, 100);
404 while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
411 ret = regmap_write(ctx->regmap, MICMD, 0);
415 ret = regmap_read(ctx->regmap, MIRD, val);
419 pr_err("%s: error %d reading reg %02x\n", __func__, ret,
425 static int regmap_encx24j600_phy_reg_write(void *context, unsigned int reg,
428 struct encx24j600_context *ctx = context;
432 reg = MIREGADR_VAL | (reg & PHREG_MASK);
433 ret = regmap_write(ctx->regmap, MIREGADR, reg);
437 ret = regmap_write(ctx->regmap, MIWR, val);
441 usleep_range(26, 100);
442 while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
448 pr_err("%s: error %d writing reg %02x=%04x\n", __func__, ret,
449 reg & PHREG_MASK, val);
454 static bool encx24j600_phymap_readable(struct device *dev, unsigned int reg)
471 static bool encx24j600_phymap_writeable(struct device *dev, unsigned int reg)
488 static bool encx24j600_phymap_volatile(struct device *dev, unsigned int reg)
503 static struct regmap_config regcfg = {
507 .max_register = 0xee,
509 .cache_type = REGCACHE_RBTREE,
510 .val_format_endian = REGMAP_ENDIAN_LITTLE,
511 .readable_reg = encx24j600_regmap_readable,
512 .writeable_reg = encx24j600_regmap_writeable,
513 .volatile_reg = encx24j600_regmap_volatile,
514 .precious_reg = encx24j600_regmap_precious,
515 .lock = regmap_lock_mutex,
516 .unlock = regmap_unlock_mutex,
519 static struct regmap_bus regmap_encx24j600 = {
520 .write = regmap_encx24j600_write,
521 .read = regmap_encx24j600_read,
522 .reg_update_bits = regmap_encx24j600_reg_update_bits,
525 static struct regmap_config phycfg = {
529 .max_register = 0x1f,
530 .cache_type = REGCACHE_RBTREE,
531 .val_format_endian = REGMAP_ENDIAN_LITTLE,
532 .readable_reg = encx24j600_phymap_readable,
533 .writeable_reg = encx24j600_phymap_writeable,
534 .volatile_reg = encx24j600_phymap_volatile,
536 static struct regmap_bus phymap_encx24j600 = {
537 .reg_write = regmap_encx24j600_phy_reg_write,
538 .reg_read = regmap_encx24j600_phy_reg_read,
541 void devm_regmap_init_encx24j600(struct device *dev,
542 struct encx24j600_context *ctx)
544 mutex_init(&ctx->mutex);
545 regcfg.lock_arg = ctx;
546 ctx->regmap = devm_regmap_init(dev, ®map_encx24j600, ctx, ®cfg);
547 ctx->phymap = devm_regmap_init(dev, &phymap_encx24j600, ctx, &phycfg);
549 EXPORT_SYMBOL_GPL(devm_regmap_init_encx24j600);
551 MODULE_LICENSE("GPL");