drivers/net/ethernet/neterion/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2010 Exar Corp.
   4  *
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explanation of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     2(MSI_X). Default value is '2(MSI_X)'
  41  * lro_max_pkts: This parameter defines maximum number of packets can be
  42  *     aggregated as a single large packet
  43  * napi: This parameter used to enable/disable NAPI (polling Rx)
  44  *     Possible values '1' for enable and '0' for disable. Default is '1'
  45  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  46  *      Possible values '1' for enable and '0' for disable. Default is '0'
  47  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  48  *                 Possible values '1' for enable , '0' for disable.
  49  *                 Default is '2' - which means disable in promisc mode
  50  *                 and enable in non-promiscuous mode.
  51  * multiq: This parameter used to enable/disable MULTIQUEUE support.
  52  *      Possible values '1' for enable and '0' for disable. Default is '0'
  53  ************************************************************************/
  54
  55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  56
  57 #include <linux/module.h>
  58 #include <linux/types.h>
  59 #include <linux/errno.h>
  60 #include <linux/ioport.h>
  61 #include <linux/pci.h>
  62 #include <linux/dma-mapping.h>
  63 #include <linux/kernel.h>
  64 #include <linux/netdevice.h>
  65 #include <linux/etherdevice.h>
  66 #include <linux/mdio.h>
  67 #include <linux/skbuff.h>
  68 #include <linux/init.h>
  69 #include <linux/delay.h>
  70 #include <linux/stddef.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/timex.h>
  73 #include <linux/ethtool.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/if_vlan.h>
  76 #include <linux/ip.h>
  77 #include <linux/tcp.h>
  78 #include <linux/uaccess.h>
  79 #include <linux/io.h>
  80 #include <linux/slab.h>
  81 #include <linux/prefetch.h>
  82 #include <net/tcp.h>
  83 #include <net/checksum.h>
  84
  85 #include <asm/div64.h>
  86 #include <asm/irq.h>
  87
  88 /* local include */
  89 #include "s2io.h"
  90 #include "s2io-regs.h"
  91
  92 #define DRV_VERSION "2.0.26.28"
  93
  94 /* S2io Driver name & version. */
  95 static const char s2io_driver_name[] = "Neterion";
  96 static const char s2io_driver_version[] = DRV_VERSION;
  97
  98 static const int rxd_size[2] = {32, 48};
  99 static const int rxd_count[2] = {127, 85};
 100
 101 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
 102 {
 103         int ret;
 104
 105         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 106                (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 107
 108         return ret;
 109 }
 110
 111 /*
 112  * Cards with following subsystem_id have a link state indication
 113  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 114  * macro below identifies these cards given the subsystem_id.
 115  */
 116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid)              \
 117         (dev_type == XFRAME_I_DEVICE) ?                                 \
 118         ((((subid >= 0x600B) && (subid <= 0x600D)) ||                   \
 119           ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 120
 121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 122                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 123
 124 static inline int is_s2io_card_up(const struct s2io_nic *sp)
 125 {
 126         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
 127 }
 128
 129 /* Ethtool related variables and Macros. */
 130 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
 131         "Register test\t(offline)",
 132         "Eeprom test\t(offline)",
 133         "Link test\t(online)",
 134         "RLDRAM test\t(offline)",
 135         "BIST Test\t(offline)"
 136 };
 137
 138 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 139         {"tmac_frms"},
 140         {"tmac_data_octets"},
 141         {"tmac_drop_frms"},
 142         {"tmac_mcst_frms"},
 143         {"tmac_bcst_frms"},
 144         {"tmac_pause_ctrl_frms"},
 145         {"tmac_ttl_octets"},
 146         {"tmac_ucst_frms"},
 147         {"tmac_nucst_frms"},
 148         {"tmac_any_err_frms"},
 149         {"tmac_ttl_less_fb_octets"},
 150         {"tmac_vld_ip_octets"},
 151         {"tmac_vld_ip"},
 152         {"tmac_drop_ip"},
 153         {"tmac_icmp"},
 154         {"tmac_rst_tcp"},
 155         {"tmac_tcp"},
 156         {"tmac_udp"},
 157         {"rmac_vld_frms"},
 158         {"rmac_data_octets"},
 159         {"rmac_fcs_err_frms"},
 160         {"rmac_drop_frms"},
 161         {"rmac_vld_mcst_frms"},
 162         {"rmac_vld_bcst_frms"},
 163         {"rmac_in_rng_len_err_frms"},
 164         {"rmac_out_rng_len_err_frms"},
 165         {"rmac_long_frms"},
 166         {"rmac_pause_ctrl_frms"},
 167         {"rmac_unsup_ctrl_frms"},
 168         {"rmac_ttl_octets"},
 169         {"rmac_accepted_ucst_frms"},
 170         {"rmac_accepted_nucst_frms"},
 171         {"rmac_discarded_frms"},
 172         {"rmac_drop_events"},
 173         {"rmac_ttl_less_fb_octets"},
 174         {"rmac_ttl_frms"},
 175         {"rmac_usized_frms"},
 176         {"rmac_osized_frms"},
 177         {"rmac_frag_frms"},
 178         {"rmac_jabber_frms"},
 179         {"rmac_ttl_64_frms"},
 180         {"rmac_ttl_65_127_frms"},
 181         {"rmac_ttl_128_255_frms"},
 182         {"rmac_ttl_256_511_frms"},
 183         {"rmac_ttl_512_1023_frms"},
 184         {"rmac_ttl_1024_1518_frms"},
 185         {"rmac_ip"},
 186         {"rmac_ip_octets"},
 187         {"rmac_hdr_err_ip"},
 188         {"rmac_drop_ip"},
 189         {"rmac_icmp"},
 190         {"rmac_tcp"},
 191         {"rmac_udp"},
 192         {"rmac_err_drp_udp"},
 193         {"rmac_xgmii_err_sym"},
 194         {"rmac_frms_q0"},
 195         {"rmac_frms_q1"},
 196         {"rmac_frms_q2"},
 197         {"rmac_frms_q3"},
 198         {"rmac_frms_q4"},
 199         {"rmac_frms_q5"},
 200         {"rmac_frms_q6"},
 201         {"rmac_frms_q7"},
 202         {"rmac_full_q0"},
 203         {"rmac_full_q1"},
 204         {"rmac_full_q2"},
 205         {"rmac_full_q3"},
 206         {"rmac_full_q4"},
 207         {"rmac_full_q5"},
 208         {"rmac_full_q6"},
 209         {"rmac_full_q7"},
 210         {"rmac_pause_cnt"},
 211         {"rmac_xgmii_data_err_cnt"},
 212         {"rmac_xgmii_ctrl_err_cnt"},
 213         {"rmac_accepted_ip"},
 214         {"rmac_err_tcp"},
 215         {"rd_req_cnt"},
 216         {"new_rd_req_cnt"},
 217         {"new_rd_req_rtry_cnt"},
 218         {"rd_rtry_cnt"},
 219         {"wr_rtry_rd_ack_cnt"},
 220         {"wr_req_cnt"},
 221         {"new_wr_req_cnt"},
 222         {"new_wr_req_rtry_cnt"},
 223         {"wr_rtry_cnt"},
 224         {"wr_disc_cnt"},
 225         {"rd_rtry_wr_ack_cnt"},
 226         {"txp_wr_cnt"},
 227         {"txd_rd_cnt"},
 228         {"txd_wr_cnt"},
 229         {"rxd_rd_cnt"},
 230         {"rxd_wr_cnt"},
 231         {"txf_rd_cnt"},
 232         {"rxf_wr_cnt"}
 233 };
 234
 235 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 236         {"rmac_ttl_1519_4095_frms"},
 237         {"rmac_ttl_4096_8191_frms"},
 238         {"rmac_ttl_8192_max_frms"},
 239         {"rmac_ttl_gt_max_frms"},
 240         {"rmac_osized_alt_frms"},
 241         {"rmac_jabber_alt_frms"},
 242         {"rmac_gt_max_alt_frms"},
 243         {"rmac_vlan_frms"},
 244         {"rmac_len_discard"},
 245         {"rmac_fcs_discard"},
 246         {"rmac_pf_discard"},
 247         {"rmac_da_discard"},
 248         {"rmac_red_discard"},
 249         {"rmac_rts_discard"},
 250         {"rmac_ingm_full_discard"},
 251         {"link_fault_cnt"}
 252 };
 253
 254 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 255         {"\n DRIVER STATISTICS"},
 256         {"single_bit_ecc_errs"},
 257         {"double_bit_ecc_errs"},
 258         {"parity_err_cnt"},
 259         {"serious_err_cnt"},
 260         {"soft_reset_cnt"},
 261         {"fifo_full_cnt"},
 262         {"ring_0_full_cnt"},
 263         {"ring_1_full_cnt"},
 264         {"ring_2_full_cnt"},
 265         {"ring_3_full_cnt"},
 266         {"ring_4_full_cnt"},
 267         {"ring_5_full_cnt"},
 268         {"ring_6_full_cnt"},
 269         {"ring_7_full_cnt"},
 270         {"alarm_transceiver_temp_high"},
 271         {"alarm_transceiver_temp_low"},
 272         {"alarm_laser_bias_current_high"},
 273         {"alarm_laser_bias_current_low"},
 274         {"alarm_laser_output_power_high"},
 275         {"alarm_laser_output_power_low"},
 276         {"warn_transceiver_temp_high"},
 277         {"warn_transceiver_temp_low"},
 278         {"warn_laser_bias_current_high"},
 279         {"warn_laser_bias_current_low"},
 280         {"warn_laser_output_power_high"},
 281         {"warn_laser_output_power_low"},
 282         {"lro_aggregated_pkts"},
 283         {"lro_flush_both_count"},
 284         {"lro_out_of_sequence_pkts"},
 285         {"lro_flush_due_to_max_pkts"},
 286         {"lro_avg_aggr_pkts"},
 287         {"mem_alloc_fail_cnt"},
 288         {"pci_map_fail_cnt"},
 289         {"watchdog_timer_cnt"},
 290         {"mem_allocated"},
 291         {"mem_freed"},
 292         {"link_up_cnt"},
 293         {"link_down_cnt"},
 294         {"link_up_time"},
 295         {"link_down_time"},
 296         {"tx_tcode_buf_abort_cnt"},
 297         {"tx_tcode_desc_abort_cnt"},
 298         {"tx_tcode_parity_err_cnt"},
 299         {"tx_tcode_link_loss_cnt"},
 300         {"tx_tcode_list_proc_err_cnt"},
 301         {"rx_tcode_parity_err_cnt"},
 302         {"rx_tcode_abort_cnt"},
 303         {"rx_tcode_parity_abort_cnt"},
 304         {"rx_tcode_rda_fail_cnt"},
 305         {"rx_tcode_unkn_prot_cnt"},
 306         {"rx_tcode_fcs_err_cnt"},
 307         {"rx_tcode_buf_size_err_cnt"},
 308         {"rx_tcode_rxd_corrupt_cnt"},
 309         {"rx_tcode_unkn_err_cnt"},
 310         {"tda_err_cnt"},
 311         {"pfc_err_cnt"},
 312         {"pcc_err_cnt"},
 313         {"tti_err_cnt"},
 314         {"tpa_err_cnt"},
 315         {"sm_err_cnt"},
 316         {"lso_err_cnt"},
 317         {"mac_tmac_err_cnt"},
 318         {"mac_rmac_err_cnt"},
 319         {"xgxs_txgxs_err_cnt"},
 320         {"xgxs_rxgxs_err_cnt"},
 321         {"rc_err_cnt"},
 322         {"prc_pcix_err_cnt"},
 323         {"rpa_err_cnt"},
 324         {"rda_err_cnt"},
 325         {"rti_err_cnt"},
 326         {"mc_err_cnt"}
 327 };
 328
 329 #define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
 330 #define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
 331 #define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
 332
 333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
 334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
 335
 336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
 337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
 338
 339 #define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
 340 #define S2IO_STRINGS_LEN        (S2IO_TEST_LEN * ETH_GSTRING_LEN)
 341
 342 #define S2IO_TIMER_CONF(timer, handle, arg, exp)        \
 343         init_timer(&timer);                             \
 344         timer.function = handle;                        \
 345         timer.data = (unsigned long)arg;                \
 346         mod_timer(&timer, (jiffies + exp))              \
 347
 348 /* copy mac addr to def_mac_addr array */
 349 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
 350 {
 351         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
 352         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
 353         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
 354         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
 355         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
 356         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
 357 }
 358
 359 /*
 360  * Constants to be programmed into the Xena's registers, to configure
 361  * the XAUI.
 362  */
 363
 364 #define END_SIGN        0x0
 365 static const u64 herc_act_dtx_cfg[] = {
 366         /* Set address */
 367         0x8000051536750000ULL, 0x80000515367500E0ULL,
 368         /* Write data */
 369         0x8000051536750004ULL, 0x80000515367500E4ULL,
 370         /* Set address */
 371         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 372         /* Write data */
 373         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 374         /* Set address */
 375         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 376         /* Write data */
 377         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 378         /* Set address */
 379         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 380         /* Write data */
 381         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 382         /* Done */
 383         END_SIGN
 384 };
 385
 386 static const u64 xena_dtx_cfg[] = {
 387         /* Set address */
 388         0x8000051500000000ULL, 0x80000515000000E0ULL,
 389         /* Write data */
 390         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 391         /* Set address */
 392         0x8001051500000000ULL, 0x80010515000000E0ULL,
 393         /* Write data */
 394         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 395         /* Set address */
 396         0x8002051500000000ULL, 0x80020515000000E0ULL,
 397         /* Write data */
 398         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 399         END_SIGN
 400 };
 401
 402 /*
 403  * Constants for Fixing the MacAddress problem seen mostly on
 404  * Alpha machines.
 405  */
 406 static const u64 fix_mac[] = {
 407         0x0060000000000000ULL, 0x0060600000000000ULL,
 408         0x0040600000000000ULL, 0x0000600000000000ULL,
 409         0x0020600000000000ULL, 0x0060600000000000ULL,
 410         0x0020600000000000ULL, 0x0060600000000000ULL,
 411         0x0020600000000000ULL, 0x0060600000000000ULL,
 412         0x0020600000000000ULL, 0x0060600000000000ULL,
 413         0x0020600000000000ULL, 0x0060600000000000ULL,
 414         0x0020600000000000ULL, 0x0060600000000000ULL,
 415         0x0020600000000000ULL, 0x0060600000000000ULL,
 416         0x0020600000000000ULL, 0x0060600000000000ULL,
 417         0x0020600000000000ULL, 0x0060600000000000ULL,
 418         0x0020600000000000ULL, 0x0060600000000000ULL,
 419         0x0020600000000000ULL, 0x0000600000000000ULL,
 420         0x0040600000000000ULL, 0x0060600000000000ULL,
 421         END_SIGN
 422 };
 423
 424 MODULE_LICENSE("GPL");
 425 MODULE_VERSION(DRV_VERSION);
 426
 427
 428 /* Module Loadable parameters. */
 429 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
 430 S2IO_PARM_INT(rx_ring_num, 1);
 431 S2IO_PARM_INT(multiq, 0);
 432 S2IO_PARM_INT(rx_ring_mode, 1);
 433 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 434 S2IO_PARM_INT(rmac_pause_time, 0x100);
 435 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 436 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 437 S2IO_PARM_INT(shared_splits, 0);
 438 S2IO_PARM_INT(tmac_util_period, 5);
 439 S2IO_PARM_INT(rmac_util_period, 5);
 440 S2IO_PARM_INT(l3l4hdr_size, 128);
 441 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
 442 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
 443 /* Frequency of Rx desc syncs expressed as power of 2 */
 444 S2IO_PARM_INT(rxsync_frequency, 3);
 445 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
 446 S2IO_PARM_INT(intr_type, 2);
 447 /* Large receive offload feature */
 448
 449 /* Max pkts to be aggregated by LRO at one time. If not specified,
 450  * aggregation happens until we hit max IP pkt size(64K)
 451  */
 452 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 453 S2IO_PARM_INT(indicate_max_pkts, 0);
 454
 455 S2IO_PARM_INT(napi, 1);
 456 S2IO_PARM_INT(ufo, 0);
 457 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 458
 459 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 460 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 461 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 462 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 463 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 464 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 465
 466 module_param_array(tx_fifo_len, uint, NULL, 0);
 467 module_param_array(rx_ring_sz, uint, NULL, 0);
 468 module_param_array(rts_frm_len, uint, NULL, 0);
 469
 470 /*
 471  * S2IO device table.
 472  * This table lists all the devices that this driver supports.
 473  */
 474 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
 475         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 476          PCI_ANY_ID, PCI_ANY_ID},
 477         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 478          PCI_ANY_ID, PCI_ANY_ID},
 479         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 480          PCI_ANY_ID, PCI_ANY_ID},
 481         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 482          PCI_ANY_ID, PCI_ANY_ID},
 483         {0,}
 484 };
 485
 486 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 487
 488 static const struct pci_error_handlers s2io_err_handler = {
 489         .error_detected = s2io_io_error_detected,
 490         .slot_reset = s2io_io_slot_reset,
 491         .resume = s2io_io_resume,
 492 };
 493
 494 static struct pci_driver s2io_driver = {
 495         .name = "S2IO",
 496         .id_table = s2io_tbl,
 497         .probe = s2io_init_nic,
 498         .remove = s2io_rem_nic,
 499         .err_handler = &s2io_err_handler,
 500 };
 501
 502 /* A simplifier macro used both by init and free shared_mem Fns(). */
 503 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 504
 505 /* netqueue manipulation helper functions */
 506 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
 507 {
 508         if (!sp->config.multiq) {
 509                 int i;
 510
 511                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 512                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
 513         }
 514         netif_tx_stop_all_queues(sp->dev);
 515 }
 516
 517 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
 518 {
 519         if (!sp->config.multiq)
 520                 sp->mac_control.fifos[fifo_no].queue_state =
 521                         FIFO_QUEUE_STOP;
 522
 523         netif_tx_stop_all_queues(sp->dev);
 524 }
 525
 526 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
 527 {
 528         if (!sp->config.multiq) {
 529                 int i;
 530
 531                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 532                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 533         }
 534         netif_tx_start_all_queues(sp->dev);
 535 }
 536
 537 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
 538 {
 539         if (!sp->config.multiq)
 540                 sp->mac_control.fifos[fifo_no].queue_state =
 541                         FIFO_QUEUE_START;
 542
 543         netif_tx_start_all_queues(sp->dev);
 544 }
 545
 546 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
 547 {
 548         if (!sp->config.multiq) {
 549                 int i;
 550
 551                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 552                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 553         }
 554         netif_tx_wake_all_queues(sp->dev);
 555 }
 556
 557 static inline void s2io_wake_tx_queue(
 558         struct fifo_info *fifo, int cnt, u8 multiq)
 559 {
 560
 561         if (multiq) {
 562                 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
 563                         netif_wake_subqueue(fifo->dev, fifo->fifo_no);
 564         } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
 565                 if (netif_queue_stopped(fifo->dev)) {
 566                         fifo->queue_state = FIFO_QUEUE_START;
 567                         netif_wake_queue(fifo->dev);
 568                 }
 569         }
 570 }
 571
 572 /**
 573  * init_shared_mem - Allocation and Initialization of Memory
 574  * @nic: Device private variable.
 575  * Description: The function allocates all the memory areas shared
 576  * between the NIC and the driver. This includes Tx descriptors,
 577  * Rx descriptors and the statistics block.
 578  */
 579
 580 static int init_shared_mem(struct s2io_nic *nic)
 581 {
 582         u32 size;
 583         void *tmp_v_addr, *tmp_v_addr_next;
 584         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 585         struct RxD_block *pre_rxd_blk = NULL;
 586         int i, j, blk_cnt;
 587         int lst_size, lst_per_page;
 588         struct net_device *dev = nic->dev;
 589         unsigned long tmp;
 590         struct buffAdd *ba;
 591         struct config_param *config = &nic->config;
 592         struct mac_info *mac_control = &nic->mac_control;
 593         unsigned long long mem_allocated = 0;
 594
 595         /* Allocation and initialization of TXDLs in FIFOs */
 596         size = 0;
 597         for (i = 0; i < config->tx_fifo_num; i++) {
 598                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 599
 600                 size += tx_cfg->fifo_len;
 601         }
 602         if (size > MAX_AVAILABLE_TXDS) {
 603                 DBG_PRINT(ERR_DBG,
 604                           "Too many TxDs requested: %d, max supported: %d\n",
 605                           size, MAX_AVAILABLE_TXDS);
 606                 return -EINVAL;
 607         }
 608
 609         size = 0;
 610         for (i = 0; i < config->tx_fifo_num; i++) {
 611                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 612
 613                 size = tx_cfg->fifo_len;
 614                 /*
 615                  * Legal values are from 2 to 8192
 616                  */
 617                 if (size < 2) {
 618                         DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
 619                                   "Valid lengths are 2 through 8192\n",
 620                                   i, size);
 621                         return -EINVAL;
 622                 }
 623         }
 624
 625         lst_size = (sizeof(struct TxD) * config->max_txds);
 626         lst_per_page = PAGE_SIZE / lst_size;
 627
 628         for (i = 0; i < config->tx_fifo_num; i++) {
 629                 struct fifo_info *fifo = &mac_control->fifos[i];
 630                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 631                 int fifo_len = tx_cfg->fifo_len;
 632                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 633
 634                 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
 635                 if (!fifo->list_info) {
 636                         DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
 637                         return -ENOMEM;
 638                 }
 639                 mem_allocated += list_holder_size;
 640         }
 641         for (i = 0; i < config->tx_fifo_num; i++) {
 642                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 643                                                 lst_per_page);
 644                 struct fifo_info *fifo = &mac_control->fifos[i];
 645                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 646
 647                 fifo->tx_curr_put_info.offset = 0;
 648                 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
 649                 fifo->tx_curr_get_info.offset = 0;
 650                 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
 651                 fifo->fifo_no = i;
 652                 fifo->nic = nic;
 653                 fifo->max_txds = MAX_SKB_FRAGS + 2;
 654                 fifo->dev = dev;
 655
 656                 for (j = 0; j < page_num; j++) {
 657                         int k = 0;
 658                         dma_addr_t tmp_p;
 659                         void *tmp_v;
 660                         tmp_v = pci_alloc_consistent(nic->pdev,
 661                                                      PAGE_SIZE, &tmp_p);
 662                         if (!tmp_v) {
 663                                 DBG_PRINT(INFO_DBG,
 664                                           "pci_alloc_consistent failed for TxDL\n");
 665                                 return -ENOMEM;
 666                         }
 667                         /* If we got a zero DMA address(can happen on
 668                          * certain platforms like PPC), reallocate.
 669                          * Store virtual address of page we don't want,
 670                          * to be freed later.
 671                          */
 672                         if (!tmp_p) {
 673                                 mac_control->zerodma_virt_addr = tmp_v;
 674                                 DBG_PRINT(INIT_DBG,
 675                                           "%s: Zero DMA address for TxDL. "
 676                                           "Virtual address %p\n",
 677                                           dev->name, tmp_v);
 678                                 tmp_v = pci_alloc_consistent(nic->pdev,
 679                                                              PAGE_SIZE, &tmp_p);
 680                                 if (!tmp_v) {
 681                                         DBG_PRINT(INFO_DBG,
 682                                                   "pci_alloc_consistent failed for TxDL\n");
 683                                         return -ENOMEM;
 684                                 }
 685                                 mem_allocated += PAGE_SIZE;
 686                         }
 687                         while (k < lst_per_page) {
 688                                 int l = (j * lst_per_page) + k;
 689                                 if (l == tx_cfg->fifo_len)
 690                                         break;
 691                                 fifo->list_info[l].list_virt_addr =
 692                                         tmp_v + (k * lst_size);
 693                                 fifo->list_info[l].list_phy_addr =
 694                                         tmp_p + (k * lst_size);
 695                                 k++;
 696                         }
 697                 }
 698         }
 699
 700         for (i = 0; i < config->tx_fifo_num; i++) {
 701                 struct fifo_info *fifo = &mac_control->fifos[i];
 702                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 703
 704                 size = tx_cfg->fifo_len;
 705                 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 706                 if (!fifo->ufo_in_band_v)
 707                         return -ENOMEM;
 708                 mem_allocated += (size * sizeof(u64));
 709         }
 710
 711         /* Allocation and initialization of RXDs in Rings */
 712         size = 0;
 713         for (i = 0; i < config->rx_ring_num; i++) {
 714                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 715                 struct ring_info *ring = &mac_control->rings[i];
 716
 717                 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
 718                         DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
 719                                   "multiple of RxDs per Block\n",
 720                                   dev->name, i);
 721                         return FAILURE;
 722                 }
 723                 size += rx_cfg->num_rxd;
 724                 ring->block_count = rx_cfg->num_rxd /
 725                         (rxd_count[nic->rxd_mode] + 1);
 726                 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
 727         }
 728         if (nic->rxd_mode == RXD_MODE_1)
 729                 size = (size * (sizeof(struct RxD1)));
 730         else
 731                 size = (size * (sizeof(struct RxD3)));
 732
 733         for (i = 0; i < config->rx_ring_num; i++) {
 734                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 735                 struct ring_info *ring = &mac_control->rings[i];
 736
 737                 ring->rx_curr_get_info.block_index = 0;
 738                 ring->rx_curr_get_info.offset = 0;
 739                 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
 740                 ring->rx_curr_put_info.block_index = 0;
 741                 ring->rx_curr_put_info.offset = 0;
 742                 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
 743                 ring->nic = nic;
 744                 ring->ring_no = i;
 745
 746                 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
 747                 /*  Allocating all the Rx blocks */
 748                 for (j = 0; j < blk_cnt; j++) {
 749                         struct rx_block_info *rx_blocks;
 750                         int l;
 751
 752                         rx_blocks = &ring->rx_blocks[j];
 753                         size = SIZE_OF_BLOCK;   /* size is always page size */
 754                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 755                                                           &tmp_p_addr);
 756                         if (tmp_v_addr == NULL) {
 757                                 /*
 758                                  * In case of failure, free_shared_mem()
 759                                  * is called, which should free any
 760                                  * memory that was alloced till the
 761                                  * failure happened.
 762                                  */
 763                                 rx_blocks->block_virt_addr = tmp_v_addr;
 764                                 return -ENOMEM;
 765                         }
 766                         mem_allocated += size;
 767                         memset(tmp_v_addr, 0, size);
 768
 769                         size = sizeof(struct rxd_info) *
 770                                 rxd_count[nic->rxd_mode];
 771                         rx_blocks->block_virt_addr = tmp_v_addr;
 772                         rx_blocks->block_dma_addr = tmp_p_addr;
 773                         rx_blocks->rxds = kmalloc(size,  GFP_KERNEL);
 774                         if (!rx_blocks->rxds)
 775                                 return -ENOMEM;
 776                         mem_allocated += size;
 777                         for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
 778                                 rx_blocks->rxds[l].virt_addr =
 779                                         rx_blocks->block_virt_addr +
 780                                         (rxd_size[nic->rxd_mode] * l);
 781                                 rx_blocks->rxds[l].dma_addr =
 782                                         rx_blocks->block_dma_addr +
 783                                         (rxd_size[nic->rxd_mode] * l);
 784                         }
 785                 }
 786                 /* Interlinking all Rx Blocks */
 787                 for (j = 0; j < blk_cnt; j++) {
 788                         int next = (j + 1) % blk_cnt;
 789                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
 790                         tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
 791                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
 792                         tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
 793
 794                         pre_rxd_blk = tmp_v_addr;
 795                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 796                                 (unsigned long)tmp_v_addr_next;
 797                         pre_rxd_blk->pNext_RxD_Blk_physical =
 798                                 (u64)tmp_p_addr_next;
 799                 }
 800         }
 801         if (nic->rxd_mode == RXD_MODE_3B) {
 802                 /*
 803                  * Allocation of Storages for buffer addresses in 2BUFF mode
 804                  * and the buffers as well.
 805                  */
 806                 for (i = 0; i < config->rx_ring_num; i++) {
 807                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 808                         struct ring_info *ring = &mac_control->rings[i];
 809
 810                         blk_cnt = rx_cfg->num_rxd /
 811                                 (rxd_count[nic->rxd_mode] + 1);
 812                         size = sizeof(struct buffAdd *) * blk_cnt;
 813                         ring->ba = kmalloc(size, GFP_KERNEL);
 814                         if (!ring->ba)
 815                                 return -ENOMEM;
 816                         mem_allocated += size;
 817                         for (j = 0; j < blk_cnt; j++) {
 818                                 int k = 0;
 819
 820                                 size = sizeof(struct buffAdd) *
 821                                         (rxd_count[nic->rxd_mode] + 1);
 822                                 ring->ba[j] = kmalloc(size, GFP_KERNEL);
 823                                 if (!ring->ba[j])
 824                                         return -ENOMEM;
 825                                 mem_allocated += size;
 826                                 while (k != rxd_count[nic->rxd_mode]) {
 827                                         ba = &ring->ba[j][k];
 828                                         size = BUF0_LEN + ALIGN_SIZE;
 829                                         ba->ba_0_org = kmalloc(size, GFP_KERNEL);
 830                                         if (!ba->ba_0_org)
 831                                                 return -ENOMEM;
 832                                         mem_allocated += size;
 833                                         tmp = (unsigned long)ba->ba_0_org;
 834                                         tmp += ALIGN_SIZE;
 835                                         tmp &= ~((unsigned long)ALIGN_SIZE);
 836                                         ba->ba_0 = (void *)tmp;
 837
 838                                         size = BUF1_LEN + ALIGN_SIZE;
 839                                         ba->ba_1_org = kmalloc(size, GFP_KERNEL);
 840                                         if (!ba->ba_1_org)
 841                                                 return -ENOMEM;
 842                                         mem_allocated += size;
 843                                         tmp = (unsigned long)ba->ba_1_org;
 844                                         tmp += ALIGN_SIZE;
 845                                         tmp &= ~((unsigned long)ALIGN_SIZE);
 846                                         ba->ba_1 = (void *)tmp;
 847                                         k++;
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         /* Allocation and initialization of Statistics block */
 854         size = sizeof(struct stat_block);
 855         mac_control->stats_mem =
 856                 pci_alloc_consistent(nic->pdev, size,
 857                                      &mac_control->stats_mem_phy);
 858
 859         if (!mac_control->stats_mem) {
 860                 /*
 861                  * In case of failure, free_shared_mem() is called, which
 862                  * should free any memory that was alloced till the
 863                  * failure happened.
 864                  */
 865                 return -ENOMEM;
 866         }
 867         mem_allocated += size;
 868         mac_control->stats_mem_sz = size;
 869
 870         tmp_v_addr = mac_control->stats_mem;
 871         mac_control->stats_info = tmp_v_addr;
 872         memset(tmp_v_addr, 0, size);
 873         DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
 874                 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
 875         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 876         return SUCCESS;
 877 }
 878
 879 /**
 880  * free_shared_mem - Free the allocated Memory
 881  * @nic:  Device private variable.
 882  * Description: This function is to free all memory locations allocated by
 883  * the init_shared_mem() function and return it to the kernel.
 884  */
 885
 886 static void free_shared_mem(struct s2io_nic *nic)
 887 {
 888         int i, j, blk_cnt, size;
 889         void *tmp_v_addr;
 890         dma_addr_t tmp_p_addr;
 891         int lst_size, lst_per_page;
 892         struct net_device *dev;
 893         int page_num = 0;
 894         struct config_param *config;
 895         struct mac_info *mac_control;
 896         struct stat_block *stats;
 897         struct swStat *swstats;
 898
 899         if (!nic)
 900                 return;
 901
 902         dev = nic->dev;
 903
 904         config = &nic->config;
 905         mac_control = &nic->mac_control;
 906         stats = mac_control->stats_info;
 907         swstats = &stats->sw_stat;
 908
 909         lst_size = sizeof(struct TxD) * config->max_txds;
 910         lst_per_page = PAGE_SIZE / lst_size;
 911
 912         for (i = 0; i < config->tx_fifo_num; i++) {
 913                 struct fifo_info *fifo = &mac_control->fifos[i];
 914                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 915
 916                 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
 917                 for (j = 0; j < page_num; j++) {
 918                         int mem_blks = (j * lst_per_page);
 919                         struct list_info_hold *fli;
 920
 921                         if (!fifo->list_info)
 922                                 return;
 923
 924                         fli = &fifo->list_info[mem_blks];
 925                         if (!fli->list_virt_addr)
 926                                 break;
 927                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 928                                             fli->list_virt_addr,
 929                                             fli->list_phy_addr);
 930                         swstats->mem_freed += PAGE_SIZE;
 931                 }
 932                 /* If we got a zero DMA address during allocation,
 933                  * free the page now
 934                  */
 935                 if (mac_control->zerodma_virt_addr) {
 936                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 937                                             mac_control->zerodma_virt_addr,
 938                                             (dma_addr_t)0);
 939                         DBG_PRINT(INIT_DBG,
 940                                   "%s: Freeing TxDL with zero DMA address. "
 941                                   "Virtual address %p\n",
 942                                   dev->name, mac_control->zerodma_virt_addr);
 943                         swstats->mem_freed += PAGE_SIZE;
 944                 }
 945                 kfree(fifo->list_info);
 946                 swstats->mem_freed += tx_cfg->fifo_len *
 947                         sizeof(struct list_info_hold);
 948         }
 949
 950         size = SIZE_OF_BLOCK;
 951         for (i = 0; i < config->rx_ring_num; i++) {
 952                 struct ring_info *ring = &mac_control->rings[i];
 953
 954                 blk_cnt = ring->block_count;
 955                 for (j = 0; j < blk_cnt; j++) {
 956                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
 957                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
 958                         if (tmp_v_addr == NULL)
 959                                 break;
 960                         pci_free_consistent(nic->pdev, size,
 961                                             tmp_v_addr, tmp_p_addr);
 962                         swstats->mem_freed += size;
 963                         kfree(ring->rx_blocks[j].rxds);
 964                         swstats->mem_freed += sizeof(struct rxd_info) *
 965                                 rxd_count[nic->rxd_mode];
 966                 }
 967         }
 968
 969         if (nic->rxd_mode == RXD_MODE_3B) {
 970                 /* Freeing buffer storage addresses in 2BUFF mode. */
 971                 for (i = 0; i < config->rx_ring_num; i++) {
 972                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 973                         struct ring_info *ring = &mac_control->rings[i];
 974
 975                         blk_cnt = rx_cfg->num_rxd /
 976                                 (rxd_count[nic->rxd_mode] + 1);
 977                         for (j = 0; j < blk_cnt; j++) {
 978                                 int k = 0;
 979                                 if (!ring->ba[j])
 980                                         continue;
 981                                 while (k != rxd_count[nic->rxd_mode]) {
 982                                         struct buffAdd *ba = &ring->ba[j][k];
 983                                         kfree(ba->ba_0_org);
 984                                         swstats->mem_freed +=
 985                                                 BUF0_LEN + ALIGN_SIZE;
 986                                         kfree(ba->ba_1_org);
 987                                         swstats->mem_freed +=
 988                                                 BUF1_LEN + ALIGN_SIZE;
 989                                         k++;
 990                                 }
 991                                 kfree(ring->ba[j]);
 992                                 swstats->mem_freed += sizeof(struct buffAdd) *
 993                                         (rxd_count[nic->rxd_mode] + 1);
 994                         }
 995                         kfree(ring->ba);
 996                         swstats->mem_freed += sizeof(struct buffAdd *) *
 997                                 blk_cnt;
 998                 }
 999         }
1000
1001         for (i = 0; i < nic->config.tx_fifo_num; i++) {
1002                 struct fifo_info *fifo = &mac_control->fifos[i];
1003                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1004
1005                 if (fifo->ufo_in_band_v) {
1006                         swstats->mem_freed += tx_cfg->fifo_len *
1007                                 sizeof(u64);
1008                         kfree(fifo->ufo_in_band_v);
1009                 }
1010         }
1011
1012         if (mac_control->stats_mem) {
1013                 swstats->mem_freed += mac_control->stats_mem_sz;
1014                 pci_free_consistent(nic->pdev,
1015                                     mac_control->stats_mem_sz,
1016                                     mac_control->stats_mem,
1017                                     mac_control->stats_mem_phy);
1018         }
1019 }
1020
1021 /**
1022  * s2io_verify_pci_mode -
1023  */
1024
1025 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1026 {
1027         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1028         register u64 val64 = 0;
1029         int     mode;
1030
1031         val64 = readq(&bar0->pci_mode);
1032         mode = (u8)GET_PCI_MODE(val64);
1033
1034         if (val64 & PCI_MODE_UNKNOWN_MODE)
1035                 return -1;      /* Unknown PCI mode */
1036         return mode;
1037 }
1038
1039 #define NEC_VENID   0x1033
1040 #define NEC_DEVID   0x0125
1041 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1042 {
1043         struct pci_dev *tdev = NULL;
1044         for_each_pci_dev(tdev) {
1045                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1046                         if (tdev->bus == s2io_pdev->bus->parent) {
1047                                 pci_dev_put(tdev);
1048                                 return 1;
1049                         }
1050                 }
1051         }
1052         return 0;
1053 }
1054
1055 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1056 /**
1057  * s2io_print_pci_mode -
1058  */
1059 static int s2io_print_pci_mode(struct s2io_nic *nic)
1060 {
1061         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1062         register u64 val64 = 0;
1063         int     mode;
1064         struct config_param *config = &nic->config;
1065         const char *pcimode;
1066
1067         val64 = readq(&bar0->pci_mode);
1068         mode = (u8)GET_PCI_MODE(val64);
1069
1070         if (val64 & PCI_MODE_UNKNOWN_MODE)
1071                 return -1;      /* Unknown PCI mode */
1072
1073         config->bus_speed = bus_speed[mode];
1074
1075         if (s2io_on_nec_bridge(nic->pdev)) {
1076                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1077                           nic->dev->name);
1078                 return mode;
1079         }
1080
1081         switch (mode) {
1082         case PCI_MODE_PCI_33:
1083                 pcimode = "33MHz PCI bus";
1084                 break;
1085         case PCI_MODE_PCI_66:
1086                 pcimode = "66MHz PCI bus";
1087                 break;
1088         case PCI_MODE_PCIX_M1_66:
1089                 pcimode = "66MHz PCIX(M1) bus";
1090                 break;
1091         case PCI_MODE_PCIX_M1_100:
1092                 pcimode = "100MHz PCIX(M1) bus";
1093                 break;
1094         case PCI_MODE_PCIX_M1_133:
1095                 pcimode = "133MHz PCIX(M1) bus";
1096                 break;
1097         case PCI_MODE_PCIX_M2_66:
1098                 pcimode = "133MHz PCIX(M2) bus";
1099                 break;
1100         case PCI_MODE_PCIX_M2_100:
1101                 pcimode = "200MHz PCIX(M2) bus";
1102                 break;
1103         case PCI_MODE_PCIX_M2_133:
1104                 pcimode = "266MHz PCIX(M2) bus";
1105                 break;
1106         default:
1107                 pcimode = "unsupported bus!";
1108                 mode = -1;
1109         }
1110
1111         DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1112                   nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1113
1114         return mode;
1115 }
1116
1117 /**
1118  *  init_tti - Initialization transmit traffic interrupt scheme
1119  *  @nic: device private variable
1120  *  @link: link status (UP/DOWN) used to enable/disable continuous
1121  *  transmit interrupts
1122  *  Description: The function configures transmit traffic interrupts
1123  *  Return Value:  SUCCESS on success and
1124  *  '-1' on failure
1125  */
1126
1127 static int init_tti(struct s2io_nic *nic, int link)
1128 {
1129         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1130         register u64 val64 = 0;
1131         int i;
1132         struct config_param *config = &nic->config;
1133
1134         for (i = 0; i < config->tx_fifo_num; i++) {
1135                 /*
1136                  * TTI Initialization. Default Tx timer gets us about
1137                  * 250 interrupts per sec. Continuous interrupts are enabled
1138                  * by default.
1139                  */
1140                 if (nic->device_type == XFRAME_II_DEVICE) {
1141                         int count = (nic->config.bus_speed * 125)/2;
1142                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1143                 } else
1144                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1145
1146                 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1147                         TTI_DATA1_MEM_TX_URNG_B(0x10) |
1148                         TTI_DATA1_MEM_TX_URNG_C(0x30) |
1149                         TTI_DATA1_MEM_TX_TIMER_AC_EN;
1150                 if (i == 0)
1151                         if (use_continuous_tx_intrs && (link == LINK_UP))
1152                                 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1153                 writeq(val64, &bar0->tti_data1_mem);
1154
1155                 if (nic->config.intr_type == MSI_X) {
1156                         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1157                                 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1158                                 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1159                                 TTI_DATA2_MEM_TX_UFC_D(0x300);
1160                 } else {
1161                         if ((nic->config.tx_steering_type ==
1162                              TX_DEFAULT_STEERING) &&
1163                             (config->tx_fifo_num > 1) &&
1164                             (i >= nic->udp_fifo_idx) &&
1165                             (i < (nic->udp_fifo_idx +
1166                                   nic->total_udp_fifos)))
1167                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1168                                         TTI_DATA2_MEM_TX_UFC_B(0x80) |
1169                                         TTI_DATA2_MEM_TX_UFC_C(0x100) |
1170                                         TTI_DATA2_MEM_TX_UFC_D(0x120);
1171                         else
1172                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1173                                         TTI_DATA2_MEM_TX_UFC_B(0x20) |
1174                                         TTI_DATA2_MEM_TX_UFC_C(0x40) |
1175                                         TTI_DATA2_MEM_TX_UFC_D(0x80);
1176                 }
1177
1178                 writeq(val64, &bar0->tti_data2_mem);
1179
1180                 val64 = TTI_CMD_MEM_WE |
1181                         TTI_CMD_MEM_STROBE_NEW_CMD |
1182                         TTI_CMD_MEM_OFFSET(i);
1183                 writeq(val64, &bar0->tti_command_mem);
1184
1185                 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1186                                           TTI_CMD_MEM_STROBE_NEW_CMD,
1187                                           S2IO_BIT_RESET) != SUCCESS)
1188                         return FAILURE;
1189         }
1190
1191         return SUCCESS;
1192 }
1193
1194 /**
1195  *  init_nic - Initialization of hardware
1196  *  @nic: device private variable
1197  *  Description: The function sequentially configures every block
1198  *  of the H/W from their reset values.
1199  *  Return Value:  SUCCESS on success and
1200  *  '-1' on failure (endian settings incorrect).
1201  */
1202
1203 static int init_nic(struct s2io_nic *nic)
1204 {
1205         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1206         struct net_device *dev = nic->dev;
1207         register u64 val64 = 0;
1208         void __iomem *add;
1209         u32 time;
1210         int i, j;
1211         int dtx_cnt = 0;
1212         unsigned long long mem_share;
1213         int mem_size;
1214         struct config_param *config = &nic->config;
1215         struct mac_info *mac_control = &nic->mac_control;
1216
1217         /* to set the swapper controle on the card */
1218         if (s2io_set_swapper(nic)) {
1219                 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1220                 return -EIO;
1221         }
1222
1223         /*
1224          * Herc requires EOI to be removed from reset before XGXS, so..
1225          */
1226         if (nic->device_type & XFRAME_II_DEVICE) {
1227                 val64 = 0xA500000000ULL;
1228                 writeq(val64, &bar0->sw_reset);
1229                 msleep(500);
1230                 val64 = readq(&bar0->sw_reset);
1231         }
1232
1233         /* Remove XGXS from reset state */
1234         val64 = 0;
1235         writeq(val64, &bar0->sw_reset);
1236         msleep(500);
1237         val64 = readq(&bar0->sw_reset);
1238
1239         /* Ensure that it's safe to access registers by checking
1240          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1241          */
1242         if (nic->device_type == XFRAME_II_DEVICE) {
1243                 for (i = 0; i < 50; i++) {
1244                         val64 = readq(&bar0->adapter_status);
1245                         if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1246                                 break;
1247                         msleep(10);
1248                 }
1249                 if (i == 50)
1250                         return -ENODEV;
1251         }
1252
1253         /*  Enable Receiving broadcasts */
1254         add = &bar0->mac_cfg;
1255         val64 = readq(&bar0->mac_cfg);
1256         val64 |= MAC_RMAC_BCAST_ENABLE;
1257         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1258         writel((u32)val64, add);
1259         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1260         writel((u32) (val64 >> 32), (add + 4));
1261
1262         /* Read registers in all blocks */
1263         val64 = readq(&bar0->mac_int_mask);
1264         val64 = readq(&bar0->mc_int_mask);
1265         val64 = readq(&bar0->xgxs_int_mask);
1266
1267         /*  Set MTU */
1268         val64 = dev->mtu;
1269         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1270
1271         if (nic->device_type & XFRAME_II_DEVICE) {
1272                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1273                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1274                                           &bar0->dtx_control, UF);
1275                         if (dtx_cnt & 0x1)
1276                                 msleep(1); /* Necessary!! */
1277                         dtx_cnt++;
1278                 }
1279         } else {
1280                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1281                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1282                                           &bar0->dtx_control, UF);
1283                         val64 = readq(&bar0->dtx_control);
1284                         dtx_cnt++;
1285                 }
1286         }
1287
1288         /*  Tx DMA Initialization */
1289         val64 = 0;
1290         writeq(val64, &bar0->tx_fifo_partition_0);
1291         writeq(val64, &bar0->tx_fifo_partition_1);
1292         writeq(val64, &bar0->tx_fifo_partition_2);
1293         writeq(val64, &bar0->tx_fifo_partition_3);
1294
1295         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1296                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1297
1298                 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1299                         vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1300
1301                 if (i == (config->tx_fifo_num - 1)) {
1302                         if (i % 2 == 0)
1303                                 i++;
1304                 }
1305
1306                 switch (i) {
1307                 case 1:
1308                         writeq(val64, &bar0->tx_fifo_partition_0);
1309                         val64 = 0;
1310                         j = 0;
1311                         break;
1312                 case 3:
1313                         writeq(val64, &bar0->tx_fifo_partition_1);
1314                         val64 = 0;
1315                         j = 0;
1316                         break;
1317                 case 5:
1318                         writeq(val64, &bar0->tx_fifo_partition_2);
1319                         val64 = 0;
1320                         j = 0;
1321                         break;
1322                 case 7:
1323                         writeq(val64, &bar0->tx_fifo_partition_3);
1324                         val64 = 0;
1325                         j = 0;
1326                         break;
1327                 default:
1328                         j++;
1329                         break;
1330                 }
1331         }
1332
1333         /*
1334          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1335          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1336          */
1337         if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1338                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1339
1340         val64 = readq(&bar0->tx_fifo_partition_0);
1341         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1342                   &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1343
1344         /*
1345          * Initialization of Tx_PA_CONFIG register to ignore packet
1346          * integrity checking.
1347          */
1348         val64 = readq(&bar0->tx_pa_cfg);
1349         val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1350                 TX_PA_CFG_IGNORE_SNAP_OUI |
1351                 TX_PA_CFG_IGNORE_LLC_CTRL |
1352                 TX_PA_CFG_IGNORE_L2_ERR;
1353         writeq(val64, &bar0->tx_pa_cfg);
1354
1355         /* Rx DMA intialization. */
1356         val64 = 0;
1357         for (i = 0; i < config->rx_ring_num; i++) {
1358                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1359
1360                 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1361         }
1362         writeq(val64, &bar0->rx_queue_priority);
1363
1364         /*
1365          * Allocating equal share of memory to all the
1366          * configured Rings.
1367          */
1368         val64 = 0;
1369         if (nic->device_type & XFRAME_II_DEVICE)
1370                 mem_size = 32;
1371         else
1372                 mem_size = 64;
1373
1374         for (i = 0; i < config->rx_ring_num; i++) {
1375                 switch (i) {
1376                 case 0:
1377                         mem_share = (mem_size / config->rx_ring_num +
1378                                      mem_size % config->rx_ring_num);
1379                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1380                         continue;
1381                 case 1:
1382                         mem_share = (mem_size / config->rx_ring_num);
1383                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1384                         continue;
1385                 case 2:
1386                         mem_share = (mem_size / config->rx_ring_num);
1387                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1388                         continue;
1389                 case 3:
1390                         mem_share = (mem_size / config->rx_ring_num);
1391                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1392                         continue;
1393                 case 4:
1394                         mem_share = (mem_size / config->rx_ring_num);
1395                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1396                         continue;
1397                 case 5:
1398                         mem_share = (mem_size / config->rx_ring_num);
1399                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1400                         continue;
1401                 case 6:
1402                         mem_share = (mem_size / config->rx_ring_num);
1403                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1404                         continue;
1405                 case 7:
1406                         mem_share = (mem_size / config->rx_ring_num);
1407                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1408                         continue;
1409                 }
1410         }
1411         writeq(val64, &bar0->rx_queue_cfg);
1412
1413         /*
1414          * Filling Tx round robin registers
1415          * as per the number of FIFOs for equal scheduling priority
1416          */
1417         switch (config->tx_fifo_num) {
1418         case 1:
1419                 val64 = 0x0;
1420                 writeq(val64, &bar0->tx_w_round_robin_0);
1421                 writeq(val64, &bar0->tx_w_round_robin_1);
1422                 writeq(val64, &bar0->tx_w_round_robin_2);
1423                 writeq(val64, &bar0->tx_w_round_robin_3);
1424                 writeq(val64, &bar0->tx_w_round_robin_4);
1425                 break;
1426         case 2:
1427                 val64 = 0x0001000100010001ULL;
1428                 writeq(val64, &bar0->tx_w_round_robin_0);
1429                 writeq(val64, &bar0->tx_w_round_robin_1);
1430                 writeq(val64, &bar0->tx_w_round_robin_2);
1431                 writeq(val64, &bar0->tx_w_round_robin_3);
1432                 val64 = 0x0001000100000000ULL;
1433                 writeq(val64, &bar0->tx_w_round_robin_4);
1434                 break;
1435         case 3:
1436                 val64 = 0x0001020001020001ULL;
1437                 writeq(val64, &bar0->tx_w_round_robin_0);
1438                 val64 = 0x0200010200010200ULL;
1439                 writeq(val64, &bar0->tx_w_round_robin_1);
1440                 val64 = 0x0102000102000102ULL;
1441                 writeq(val64, &bar0->tx_w_round_robin_2);
1442                 val64 = 0x0001020001020001ULL;
1443                 writeq(val64, &bar0->tx_w_round_robin_3);
1444                 val64 = 0x0200010200000000ULL;
1445                 writeq(val64, &bar0->tx_w_round_robin_4);
1446                 break;
1447         case 4:
1448                 val64 = 0x0001020300010203ULL;
1449                 writeq(val64, &bar0->tx_w_round_robin_0);
1450                 writeq(val64, &bar0->tx_w_round_robin_1);
1451                 writeq(val64, &bar0->tx_w_round_robin_2);
1452                 writeq(val64, &bar0->tx_w_round_robin_3);
1453                 val64 = 0x0001020300000000ULL;
1454                 writeq(val64, &bar0->tx_w_round_robin_4);
1455                 break;
1456         case 5:
1457                 val64 = 0x0001020304000102ULL;
1458                 writeq(val64, &bar0->tx_w_round_robin_0);
1459                 val64 = 0x0304000102030400ULL;
1460                 writeq(val64, &bar0->tx_w_round_robin_1);
1461                 val64 = 0x0102030400010203ULL;
1462                 writeq(val64, &bar0->tx_w_round_robin_2);
1463                 val64 = 0x0400010203040001ULL;
1464                 writeq(val64, &bar0->tx_w_round_robin_3);
1465                 val64 = 0x0203040000000000ULL;
1466                 writeq(val64, &bar0->tx_w_round_robin_4);
1467                 break;
1468         case 6:
1469                 val64 = 0x0001020304050001ULL;
1470                 writeq(val64, &bar0->tx_w_round_robin_0);
1471                 val64 = 0x0203040500010203ULL;
1472                 writeq(val64, &bar0->tx_w_round_robin_1);
1473                 val64 = 0x0405000102030405ULL;
1474                 writeq(val64, &bar0->tx_w_round_robin_2);
1475                 val64 = 0x0001020304050001ULL;
1476                 writeq(val64, &bar0->tx_w_round_robin_3);
1477                 val64 = 0x0203040500000000ULL;
1478                 writeq(val64, &bar0->tx_w_round_robin_4);
1479                 break;
1480         case 7:
1481                 val64 = 0x0001020304050600ULL;
1482                 writeq(val64, &bar0->tx_w_round_robin_0);
1483                 val64 = 0x0102030405060001ULL;
1484                 writeq(val64, &bar0->tx_w_round_robin_1);
1485                 val64 = 0x0203040506000102ULL;
1486                 writeq(val64, &bar0->tx_w_round_robin_2);
1487                 val64 = 0x0304050600010203ULL;
1488                 writeq(val64, &bar0->tx_w_round_robin_3);
1489                 val64 = 0x0405060000000000ULL;
1490                 writeq(val64, &bar0->tx_w_round_robin_4);
1491                 break;
1492         case 8:
1493                 val64 = 0x0001020304050607ULL;
1494                 writeq(val64, &bar0->tx_w_round_robin_0);
1495                 writeq(val64, &bar0->tx_w_round_robin_1);
1496                 writeq(val64, &bar0->tx_w_round_robin_2);
1497                 writeq(val64, &bar0->tx_w_round_robin_3);
1498                 val64 = 0x0001020300000000ULL;
1499                 writeq(val64, &bar0->tx_w_round_robin_4);
1500                 break;
1501         }
1502
1503         /* Enable all configured Tx FIFO partitions */
1504         val64 = readq(&bar0->tx_fifo_partition_0);
1505         val64 |= (TX_FIFO_PARTITION_EN);
1506         writeq(val64, &bar0->tx_fifo_partition_0);
1507
1508         /* Filling the Rx round robin registers as per the
1509          * number of Rings and steering based on QoS with
1510          * equal priority.
1511          */
1512         switch (config->rx_ring_num) {
1513         case 1:
1514                 val64 = 0x0;
1515                 writeq(val64, &bar0->rx_w_round_robin_0);
1516                 writeq(val64, &bar0->rx_w_round_robin_1);
1517                 writeq(val64, &bar0->rx_w_round_robin_2);
1518                 writeq(val64, &bar0->rx_w_round_robin_3);
1519                 writeq(val64, &bar0->rx_w_round_robin_4);
1520
1521                 val64 = 0x8080808080808080ULL;
1522                 writeq(val64, &bar0->rts_qos_steering);
1523                 break;
1524         case 2:
1525                 val64 = 0x0001000100010001ULL;
1526                 writeq(val64, &bar0->rx_w_round_robin_0);
1527                 writeq(val64, &bar0->rx_w_round_robin_1);
1528                 writeq(val64, &bar0->rx_w_round_robin_2);
1529                 writeq(val64, &bar0->rx_w_round_robin_3);
1530                 val64 = 0x0001000100000000ULL;
1531                 writeq(val64, &bar0->rx_w_round_robin_4);
1532
1533                 val64 = 0x8080808040404040ULL;
1534                 writeq(val64, &bar0->rts_qos_steering);
1535                 break;
1536         case 3:
1537                 val64 = 0x0001020001020001ULL;
1538                 writeq(val64, &bar0->rx_w_round_robin_0);
1539                 val64 = 0x0200010200010200ULL;
1540                 writeq(val64, &bar0->rx_w_round_robin_1);
1541                 val64 = 0x0102000102000102ULL;
1542                 writeq(val64, &bar0->rx_w_round_robin_2);
1543                 val64 = 0x0001020001020001ULL;
1544                 writeq(val64, &bar0->rx_w_round_robin_3);
1545                 val64 = 0x0200010200000000ULL;
1546                 writeq(val64, &bar0->rx_w_round_robin_4);
1547
1548                 val64 = 0x8080804040402020ULL;
1549                 writeq(val64, &bar0->rts_qos_steering);
1550                 break;
1551         case 4:
1552                 val64 = 0x0001020300010203ULL;
1553                 writeq(val64, &bar0->rx_w_round_robin_0);
1554                 writeq(val64, &bar0->rx_w_round_robin_1);
1555                 writeq(val64, &bar0->rx_w_round_robin_2);
1556                 writeq(val64, &bar0->rx_w_round_robin_3);
1557                 val64 = 0x0001020300000000ULL;
1558                 writeq(val64, &bar0->rx_w_round_robin_4);
1559
1560                 val64 = 0x8080404020201010ULL;
1561                 writeq(val64, &bar0->rts_qos_steering);
1562                 break;
1563         case 5:
1564                 val64 = 0x0001020304000102ULL;
1565                 writeq(val64, &bar0->rx_w_round_robin_0);
1566                 val64 = 0x0304000102030400ULL;
1567                 writeq(val64, &bar0->rx_w_round_robin_1);
1568                 val64 = 0x0102030400010203ULL;
1569                 writeq(val64, &bar0->rx_w_round_robin_2);
1570                 val64 = 0x0400010203040001ULL;
1571                 writeq(val64, &bar0->rx_w_round_robin_3);
1572                 val64 = 0x0203040000000000ULL;
1573                 writeq(val64, &bar0->rx_w_round_robin_4);
1574
1575                 val64 = 0x8080404020201008ULL;
1576                 writeq(val64, &bar0->rts_qos_steering);
1577                 break;
1578         case 6:
1579                 val64 = 0x0001020304050001ULL;
1580                 writeq(val64, &bar0->rx_w_round_robin_0);
1581                 val64 = 0x0203040500010203ULL;
1582                 writeq(val64, &bar0->rx_w_round_robin_1);
1583                 val64 = 0x0405000102030405ULL;
1584                 writeq(val64, &bar0->rx_w_round_robin_2);
1585                 val64 = 0x0001020304050001ULL;
1586                 writeq(val64, &bar0->rx_w_round_robin_3);
1587                 val64 = 0x0203040500000000ULL;
1588                 writeq(val64, &bar0->rx_w_round_robin_4);
1589
1590                 val64 = 0x8080404020100804ULL;
1591                 writeq(val64, &bar0->rts_qos_steering);
1592                 break;
1593         case 7:
1594                 val64 = 0x0001020304050600ULL;
1595                 writeq(val64, &bar0->rx_w_round_robin_0);
1596                 val64 = 0x0102030405060001ULL;
1597                 writeq(val64, &bar0->rx_w_round_robin_1);
1598                 val64 = 0x0203040506000102ULL;
1599                 writeq(val64, &bar0->rx_w_round_robin_2);
1600                 val64 = 0x0304050600010203ULL;
1601                 writeq(val64, &bar0->rx_w_round_robin_3);
1602                 val64 = 0x0405060000000000ULL;
1603                 writeq(val64, &bar0->rx_w_round_robin_4);
1604
1605                 val64 = 0x8080402010080402ULL;
1606                 writeq(val64, &bar0->rts_qos_steering);
1607                 break;
1608         case 8:
1609                 val64 = 0x0001020304050607ULL;
1610                 writeq(val64, &bar0->rx_w_round_robin_0);
1611                 writeq(val64, &bar0->rx_w_round_robin_1);
1612                 writeq(val64, &bar0->rx_w_round_robin_2);
1613                 writeq(val64, &bar0->rx_w_round_robin_3);
1614                 val64 = 0x0001020300000000ULL;
1615                 writeq(val64, &bar0->rx_w_round_robin_4);
1616
1617                 val64 = 0x8040201008040201ULL;
1618                 writeq(val64, &bar0->rts_qos_steering);
1619                 break;
1620         }
1621
1622         /* UDP Fix */
1623         val64 = 0;
1624         for (i = 0; i < 8; i++)
1625                 writeq(val64, &bar0->rts_frm_len_n[i]);
1626
1627         /* Set the default rts frame length for the rings configured */
1628         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1629         for (i = 0 ; i < config->rx_ring_num ; i++)
1630                 writeq(val64, &bar0->rts_frm_len_n[i]);
1631
1632         /* Set the frame length for the configured rings
1633          * desired by the user
1634          */
1635         for (i = 0; i < config->rx_ring_num; i++) {
1636                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1637                  * specified frame length steering.
1638                  * If the user provides the frame length then program
1639                  * the rts_frm_len register for those values or else
1640                  * leave it as it is.
1641                  */
1642                 if (rts_frm_len[i] != 0) {
1643                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1644                                &bar0->rts_frm_len_n[i]);
1645                 }
1646         }
1647
1648         /* Disable differentiated services steering logic */
1649         for (i = 0; i < 64; i++) {
1650                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1651                         DBG_PRINT(ERR_DBG,
1652                                   "%s: rts_ds_steer failed on codepoint %d\n",
1653                                   dev->name, i);
1654                         return -ENODEV;
1655                 }
1656         }
1657
1658         /* Program statistics memory */
1659         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1660
1661         if (nic->device_type == XFRAME_II_DEVICE) {
1662                 val64 = STAT_BC(0x320);
1663                 writeq(val64, &bar0->stat_byte_cnt);
1664         }
1665
1666         /*
1667          * Initializing the sampling rate for the device to calculate the
1668          * bandwidth utilization.
1669          */
1670         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1671                 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1672         writeq(val64, &bar0->mac_link_util);
1673
1674         /*
1675          * Initializing the Transmit and Receive Traffic Interrupt
1676          * Scheme.
1677          */
1678
1679         /* Initialize TTI */
1680         if (SUCCESS != init_tti(nic, nic->last_link_state))
1681                 return -ENODEV;
1682
1683         /* RTI Initialization */
1684         if (nic->device_type == XFRAME_II_DEVICE) {
1685                 /*
1686                  * Programmed to generate Apprx 500 Intrs per
1687                  * second
1688                  */
1689                 int count = (nic->config.bus_speed * 125)/4;
1690                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1691         } else
1692                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1693         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1694                 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1695                 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1696                 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1697
1698         writeq(val64, &bar0->rti_data1_mem);
1699
1700         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1701                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1702         if (nic->config.intr_type == MSI_X)
1703                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1704                           RTI_DATA2_MEM_RX_UFC_D(0x40));
1705         else
1706                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1707                           RTI_DATA2_MEM_RX_UFC_D(0x80));
1708         writeq(val64, &bar0->rti_data2_mem);
1709
1710         for (i = 0; i < config->rx_ring_num; i++) {
1711                 val64 = RTI_CMD_MEM_WE |
1712                         RTI_CMD_MEM_STROBE_NEW_CMD |
1713                         RTI_CMD_MEM_OFFSET(i);
1714                 writeq(val64, &bar0->rti_command_mem);
1715
1716                 /*
1717                  * Once the operation completes, the Strobe bit of the
1718                  * command register will be reset. We poll for this
1719                  * particular condition. We wait for a maximum of 500ms
1720                  * for the operation to complete, if it's not complete
1721                  * by then we return error.
1722                  */
1723                 time = 0;
1724                 while (true) {
1725                         val64 = readq(&bar0->rti_command_mem);
1726                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1727                                 break;
1728
1729                         if (time > 10) {
1730                                 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1731                                           dev->name);
1732                                 return -ENODEV;
1733                         }
1734                         time++;
1735                         msleep(50);
1736                 }
1737         }
1738
1739         /*
1740          * Initializing proper values as Pause threshold into all
1741          * the 8 Queues on Rx side.
1742          */
1743         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1744         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1745
1746         /* Disable RMAC PAD STRIPPING */
1747         add = &bar0->mac_cfg;
1748         val64 = readq(&bar0->mac_cfg);
1749         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1750         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1751         writel((u32) (val64), add);
1752         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1753         writel((u32) (val64 >> 32), (add + 4));
1754         val64 = readq(&bar0->mac_cfg);
1755
1756         /* Enable FCS stripping by adapter */
1757         add = &bar0->mac_cfg;
1758         val64 = readq(&bar0->mac_cfg);
1759         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1760         if (nic->device_type == XFRAME_II_DEVICE)
1761                 writeq(val64, &bar0->mac_cfg);
1762         else {
1763                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1764                 writel((u32) (val64), add);
1765                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1766                 writel((u32) (val64 >> 32), (add + 4));
1767         }
1768
1769         /*
1770          * Set the time value to be inserted in the pause frame
1771          * generated by xena.
1772          */
1773         val64 = readq(&bar0->rmac_pause_cfg);
1774         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1775         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1776         writeq(val64, &bar0->rmac_pause_cfg);
1777
1778         /*
1779          * Set the Threshold Limit for Generating the pause frame
1780          * If the amount of data in any Queue exceeds ratio of
1781          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1782          * pause frame is generated
1783          */
1784         val64 = 0;
1785         for (i = 0; i < 4; i++) {
1786                 val64 |= (((u64)0xFF00 |
1787                            nic->mac_control.mc_pause_threshold_q0q3)
1788                           << (i * 2 * 8));
1789         }
1790         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1791
1792         val64 = 0;
1793         for (i = 0; i < 4; i++) {
1794                 val64 |= (((u64)0xFF00 |
1795                            nic->mac_control.mc_pause_threshold_q4q7)
1796                           << (i * 2 * 8));
1797         }
1798         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1799
1800         /*
1801          * TxDMA will stop Read request if the number of read split has
1802          * exceeded the limit pointed by shared_splits
1803          */
1804         val64 = readq(&bar0->pic_control);
1805         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1806         writeq(val64, &bar0->pic_control);
1807
1808         if (nic->config.bus_speed == 266) {
1809                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1810                 writeq(0x0, &bar0->read_retry_delay);
1811                 writeq(0x0, &bar0->write_retry_delay);
1812         }
1813
1814         /*
1815          * Programming the Herc to split every write transaction
1816          * that does not start on an ADB to reduce disconnects.
1817          */
1818         if (nic->device_type == XFRAME_II_DEVICE) {
1819                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1820                         MISC_LINK_STABILITY_PRD(3);
1821                 writeq(val64, &bar0->misc_control);
1822                 val64 = readq(&bar0->pic_control2);
1823                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1824                 writeq(val64, &bar0->pic_control2);
1825         }
1826         if (strstr(nic->product_name, "CX4")) {
1827                 val64 = TMAC_AVG_IPG(0x17);
1828                 writeq(val64, &bar0->tmac_avg_ipg);
1829         }
1830
1831         return SUCCESS;
1832 }
1833 #define LINK_UP_DOWN_INTERRUPT          1
1834 #define MAC_RMAC_ERR_TIMER              2
1835
1836 static int s2io_link_fault_indication(struct s2io_nic *nic)
1837 {
1838         if (nic->device_type == XFRAME_II_DEVICE)
1839                 return LINK_UP_DOWN_INTERRUPT;
1840         else
1841                 return MAC_RMAC_ERR_TIMER;
1842 }
1843
1844 /**
1845  *  do_s2io_write_bits -  update alarm bits in alarm register
1846  *  @value: alarm bits
1847  *  @flag: interrupt status
1848  *  @addr: address value
1849  *  Description: update alarm bits in alarm register
1850  *  Return Value:
1851  *  NONE.
1852  */
1853 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1854 {
1855         u64 temp64;
1856
1857         temp64 = readq(addr);
1858
1859         if (flag == ENABLE_INTRS)
1860                 temp64 &= ~((u64)value);
1861         else
1862                 temp64 |= ((u64)value);
1863         writeq(temp64, addr);
1864 }
1865
1866 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1867 {
1868         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1869         register u64 gen_int_mask = 0;
1870         u64 interruptible;
1871
1872         writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1873         if (mask & TX_DMA_INTR) {
1874                 gen_int_mask |= TXDMA_INT_M;
1875
1876                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1877                                    TXDMA_PCC_INT | TXDMA_TTI_INT |
1878                                    TXDMA_LSO_INT | TXDMA_TPA_INT |
1879                                    TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1880
1881                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1882                                    PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1883                                    PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1884                                    &bar0->pfc_err_mask);
1885
1886                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1887                                    TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1888                                    TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1889
1890                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1891                                    PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1892                                    PCC_N_SERR | PCC_6_COF_OV_ERR |
1893                                    PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1894                                    PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1895                                    PCC_TXB_ECC_SG_ERR,
1896                                    flag, &bar0->pcc_err_mask);
1897
1898                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1899                                    TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1900
1901                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1902                                    LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1903                                    LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1904                                    flag, &bar0->lso_err_mask);
1905
1906                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1907                                    flag, &bar0->tpa_err_mask);
1908
1909                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1910         }
1911
1912         if (mask & TX_MAC_INTR) {
1913                 gen_int_mask |= TXMAC_INT_M;
1914                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1915                                    &bar0->mac_int_mask);
1916                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1917                                    TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1918                                    TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1919                                    flag, &bar0->mac_tmac_err_mask);
1920         }
1921
1922         if (mask & TX_XGXS_INTR) {
1923                 gen_int_mask |= TXXGXS_INT_M;
1924                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1925                                    &bar0->xgxs_int_mask);
1926                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1927                                    TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1928                                    flag, &bar0->xgxs_txgxs_err_mask);
1929         }
1930
1931         if (mask & RX_DMA_INTR) {
1932                 gen_int_mask |= RXDMA_INT_M;
1933                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1934                                    RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1935                                    flag, &bar0->rxdma_int_mask);
1936                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1937                                    RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1938                                    RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1939                                    RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1940                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1941                                    PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1942                                    PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1943                                    &bar0->prc_pcix_err_mask);
1944                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1945                                    RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1946                                    &bar0->rpa_err_mask);
1947                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1948                                    RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1949                                    RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1950                                    RDA_FRM_ECC_SG_ERR |
1951                                    RDA_MISC_ERR|RDA_PCIX_ERR,
1952                                    flag, &bar0->rda_err_mask);
1953                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1954                                    RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1955                                    flag, &bar0->rti_err_mask);
1956         }
1957
1958         if (mask & RX_MAC_INTR) {
1959                 gen_int_mask |= RXMAC_INT_M;
1960                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1961                                    &bar0->mac_int_mask);
1962                 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1963                                  RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1964                                  RMAC_DOUBLE_ECC_ERR);
1965                 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
1966                         interruptible |= RMAC_LINK_STATE_CHANGE_INT;
1967                 do_s2io_write_bits(interruptible,
1968                                    flag, &bar0->mac_rmac_err_mask);
1969         }
1970
1971         if (mask & RX_XGXS_INTR) {
1972                 gen_int_mask |= RXXGXS_INT_M;
1973                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1974                                    &bar0->xgxs_int_mask);
1975                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1976                                    &bar0->xgxs_rxgxs_err_mask);
1977         }
1978
1979         if (mask & MC_INTR) {
1980                 gen_int_mask |= MC_INT_M;
1981                 do_s2io_write_bits(MC_INT_MASK_MC_INT,
1982                                    flag, &bar0->mc_int_mask);
1983                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1984                                    MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1985                                    &bar0->mc_err_mask);
1986         }
1987         nic->general_int_mask = gen_int_mask;
1988
1989         /* Remove this line when alarm interrupts are enabled */
1990         nic->general_int_mask = 0;
1991 }
1992
1993 /**
1994  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1995  *  @nic: device private variable,
1996  *  @mask: A mask indicating which Intr block must be modified and,
1997  *  @flag: A flag indicating whether to enable or disable the Intrs.
1998  *  Description: This function will either disable or enable the interrupts
1999  *  depending on the flag argument. The mask argument can be used to
2000  *  enable/disable any Intr block.
2001  *  Return Value: NONE.
2002  */
2003
2004 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2005 {
2006         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2007         register u64 temp64 = 0, intr_mask = 0;
2008
2009         intr_mask = nic->general_int_mask;
2010
2011         /*  Top level interrupt classification */
2012         /*  PIC Interrupts */
2013         if (mask & TX_PIC_INTR) {
2014                 /*  Enable PIC Intrs in the general intr mask register */
2015                 intr_mask |= TXPIC_INT_M;
2016                 if (flag == ENABLE_INTRS) {
2017                         /*
2018                          * If Hercules adapter enable GPIO otherwise
2019                          * disable all PCIX, Flash, MDIO, IIC and GPIO
2020                          * interrupts for now.
2021                          * TODO
2022                          */
2023                         if (s2io_link_fault_indication(nic) ==
2024                             LINK_UP_DOWN_INTERRUPT) {
2025                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
2026                                                    &bar0->pic_int_mask);
2027                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2028                                                    &bar0->gpio_int_mask);
2029                         } else
2030                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2031                 } else if (flag == DISABLE_INTRS) {
2032                         /*
2033                          * Disable PIC Intrs in the general
2034                          * intr mask register
2035                          */
2036                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2037                 }
2038         }
2039
2040         /*  Tx traffic interrupts */
2041         if (mask & TX_TRAFFIC_INTR) {
2042                 intr_mask |= TXTRAFFIC_INT_M;
2043                 if (flag == ENABLE_INTRS) {
2044                         /*
2045                          * Enable all the Tx side interrupts
2046                          * writing 0 Enables all 64 TX interrupt levels
2047                          */
2048                         writeq(0x0, &bar0->tx_traffic_mask);
2049                 } else if (flag == DISABLE_INTRS) {
2050                         /*
2051                          * Disable Tx Traffic Intrs in the general intr mask
2052                          * register.
2053                          */
2054                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2055                 }
2056         }
2057
2058         /*  Rx traffic interrupts */
2059         if (mask & RX_TRAFFIC_INTR) {
2060                 intr_mask |= RXTRAFFIC_INT_M;
2061                 if (flag == ENABLE_INTRS) {
2062                         /* writing 0 Enables all 8 RX interrupt levels */
2063                         writeq(0x0, &bar0->rx_traffic_mask);
2064                 } else if (flag == DISABLE_INTRS) {
2065                         /*
2066                          * Disable Rx Traffic Intrs in the general intr mask
2067                          * register.
2068                          */
2069                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2070                 }
2071         }
2072
2073         temp64 = readq(&bar0->general_int_mask);
2074         if (flag == ENABLE_INTRS)
2075                 temp64 &= ~((u64)intr_mask);
2076         else
2077                 temp64 = DISABLE_ALL_INTRS;
2078         writeq(temp64, &bar0->general_int_mask);
2079
2080         nic->general_int_mask = readq(&bar0->general_int_mask);
2081 }
2082
2083 /**
2084  *  verify_pcc_quiescent- Checks for PCC quiescent state
2085  *  Return: 1 If PCC is quiescence
2086  *          0 If PCC is not quiescence
2087  */
2088 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2089 {
2090         int ret = 0, herc;
2091         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2092         u64 val64 = readq(&bar0->adapter_status);
2093
2094         herc = (sp->device_type == XFRAME_II_DEVICE);
2095
2096         if (flag == false) {
2097                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2098                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2099                                 ret = 1;
2100                 } else {
2101                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2102                                 ret = 1;
2103                 }
2104         } else {
2105                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2106                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2107                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2108                                 ret = 1;
2109                 } else {
2110                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2111                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2112                                 ret = 1;
2113                 }
2114         }
2115
2116         return ret;
2117 }
2118 /**
2119  *  verify_xena_quiescence - Checks whether the H/W is ready
2120  *  Description: Returns whether the H/W is ready to go or not. Depending
2121  *  on whether adapter enable bit was written or not the comparison
2122  *  differs and the calling function passes the input argument flag to
2123  *  indicate this.
2124  *  Return: 1 If xena is quiescence
2125  *          0 If Xena is not quiescence
2126  */
2127
2128 static int verify_xena_quiescence(struct s2io_nic *sp)
2129 {
2130         int  mode;
2131         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2132         u64 val64 = readq(&bar0->adapter_status);
2133         mode = s2io_verify_pci_mode(sp);
2134
2135         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2136                 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2137                 return 0;
2138         }
2139         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2140                 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2141                 return 0;
2142         }
2143         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2144                 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2145                 return 0;
2146         }
2147         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2148                 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2149                 return 0;
2150         }
2151         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2152                 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2153                 return 0;
2154         }
2155         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2156                 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2157                 return 0;
2158         }
2159         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2160                 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2161                 return 0;
2162         }
2163         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2164                 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2165                 return 0;
2166         }
2167
2168         /*
2169          * In PCI 33 mode, the P_PLL is not used, and therefore,
2170          * the the P_PLL_LOCK bit in the adapter_status register will
2171          * not be asserted.
2172          */
2173         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2174             sp->device_type == XFRAME_II_DEVICE &&
2175             mode != PCI_MODE_PCI_33) {
2176                 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2177                 return 0;
2178         }
2179         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2180               ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2181                 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2182                 return 0;
2183         }
2184         return 1;
2185 }
2186
2187 /**
2188  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2189  * @sp: Pointer to device specifc structure
2190  * Description :
2191  * New procedure to clear mac address reading  problems on Alpha platforms
2192  *
2193  */
2194
2195 static void fix_mac_address(struct s2io_nic *sp)
2196 {
2197         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2198         int i = 0;
2199
2200         while (fix_mac[i] != END_SIGN) {
2201                 writeq(fix_mac[i++], &bar0->gpio_control);
2202                 udelay(10);
2203                 (void) readq(&bar0->gpio_control);
2204         }
2205 }
2206
2207 /**
2208  *  start_nic - Turns the device on
2209  *  @nic : device private variable.
2210  *  Description:
2211  *  This function actually turns the device on. Before this  function is
2212  *  called,all Registers are configured from their reset states
2213  *  and shared memory is allocated but the NIC is still quiescent. On
2214  *  calling this function, the device interrupts are cleared and the NIC is
2215  *  literally switched on by writing into the adapter control register.
2216  *  Return Value:
2217  *  SUCCESS on success and -1 on failure.
2218  */
2219
2220 static int start_nic(struct s2io_nic *nic)
2221 {
2222         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2223         struct net_device *dev = nic->dev;
2224         register u64 val64 = 0;
2225         u16 subid, i;
2226         struct config_param *config = &nic->config;
2227         struct mac_info *mac_control = &nic->mac_control;
2228
2229         /*  PRC Initialization and configuration */
2230         for (i = 0; i < config->rx_ring_num; i++) {
2231                 struct ring_info *ring = &mac_control->rings[i];
2232
2233                 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2234                        &bar0->prc_rxd0_n[i]);
2235
2236                 val64 = readq(&bar0->prc_ctrl_n[i]);
2237                 if (nic->rxd_mode == RXD_MODE_1)
2238                         val64 |= PRC_CTRL_RC_ENABLED;
2239                 else
2240                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2241                 if (nic->device_type == XFRAME_II_DEVICE)
2242                         val64 |= PRC_CTRL_GROUP_READS;
2243                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2244                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2245                 writeq(val64, &bar0->prc_ctrl_n[i]);
2246         }
2247
2248         if (nic->rxd_mode == RXD_MODE_3B) {
2249                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2250                 val64 = readq(&bar0->rx_pa_cfg);
2251                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2252                 writeq(val64, &bar0->rx_pa_cfg);
2253         }
2254
2255         if (vlan_tag_strip == 0) {
2256                 val64 = readq(&bar0->rx_pa_cfg);
2257                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2258                 writeq(val64, &bar0->rx_pa_cfg);
2259                 nic->vlan_strip_flag = 0;
2260         }
2261
2262         /*
2263          * Enabling MC-RLDRAM. After enabling the device, we timeout
2264          * for around 100ms, which is approximately the time required
2265          * for the device to be ready for operation.
2266          */
2267         val64 = readq(&bar0->mc_rldram_mrs);
2268         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2269         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2270         val64 = readq(&bar0->mc_rldram_mrs);
2271
2272         msleep(100);    /* Delay by around 100 ms. */
2273
2274         /* Enabling ECC Protection. */
2275         val64 = readq(&bar0->adapter_control);
2276         val64 &= ~ADAPTER_ECC_EN;
2277         writeq(val64, &bar0->adapter_control);
2278
2279         /*
2280          * Verify if the device is ready to be enabled, if so enable
2281          * it.
2282          */
2283         val64 = readq(&bar0->adapter_status);
2284         if (!verify_xena_quiescence(nic)) {
2285                 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2286                           "Adapter status reads: 0x%llx\n",
2287                           dev->name, (unsigned long long)val64);
2288                 return FAILURE;
2289         }
2290
2291         /*
2292          * With some switches, link might be already up at this point.
2293          * Because of this weird behavior, when we enable laser,
2294          * we may not get link. We need to handle this. We cannot
2295          * figure out which switch is misbehaving. So we are forced to
2296          * make a global change.
2297          */
2298
2299         /* Enabling Laser. */
2300         val64 = readq(&bar0->adapter_control);
2301         val64 |= ADAPTER_EOI_TX_ON;
2302         writeq(val64, &bar0->adapter_control);
2303
2304         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2305                 /*
2306                  * Dont see link state interrupts initially on some switches,
2307                  * so directly scheduling the link state task here.
2308                  */
2309                 schedule_work(&nic->set_link_task);
2310         }
2311         /* SXE-002: Initialize link and activity LED */
2312         subid = nic->pdev->subsystem_device;
2313         if (((subid & 0xFF) >= 0x07) &&
2314             (nic->device_type == XFRAME_I_DEVICE)) {
2315                 val64 = readq(&bar0->gpio_control);
2316                 val64 |= 0x0000800000000000ULL;
2317                 writeq(val64, &bar0->gpio_control);
2318                 val64 = 0x0411040400000000ULL;
2319                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2320         }
2321
2322         return SUCCESS;
2323 }
2324 /**
2325  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2326  */
2327 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2328                                         struct TxD *txdlp, int get_off)
2329 {
2330         struct s2io_nic *nic = fifo_data->nic;
2331         struct sk_buff *skb;
2332         struct TxD *txds;
2333         u16 j, frg_cnt;
2334
2335         txds = txdlp;
2336         if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2337                 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2338                                  sizeof(u64), PCI_DMA_TODEVICE);
2339                 txds++;
2340         }
2341
2342         skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2343         if (!skb) {
2344                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2345                 return NULL;
2346         }
2347         pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2348                          skb_headlen(skb), PCI_DMA_TODEVICE);
2349         frg_cnt = skb_shinfo(skb)->nr_frags;
2350         if (frg_cnt) {
2351                 txds++;
2352                 for (j = 0; j < frg_cnt; j++, txds++) {
2353                         const skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2354                         if (!txds->Buffer_Pointer)
2355                                 break;
2356                         pci_unmap_page(nic->pdev,
2357                                        (dma_addr_t)txds->Buffer_Pointer,
2358                                        skb_frag_size(frag), PCI_DMA_TODEVICE);
2359                 }
2360         }
2361         memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2362         return skb;
2363 }
2364
2365 /**
2366  *  free_tx_buffers - Free all queued Tx buffers
2367  *  @nic : device private variable.
2368  *  Description:
2369  *  Free all queued Tx buffers.
2370  *  Return Value: void
2371  */
2372
2373 static void free_tx_buffers(struct s2io_nic *nic)
2374 {
2375         struct net_device *dev = nic->dev;
2376         struct sk_buff *skb;
2377         struct TxD *txdp;
2378         int i, j;
2379         int cnt = 0;
2380         struct config_param *config = &nic->config;
2381         struct mac_info *mac_control = &nic->mac_control;
2382         struct stat_block *stats = mac_control->stats_info;
2383         struct swStat *swstats = &stats->sw_stat;
2384
2385         for (i = 0; i < config->tx_fifo_num; i++) {
2386                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2387                 struct fifo_info *fifo = &mac_control->fifos[i];
2388                 unsigned long flags;
2389
2390                 spin_lock_irqsave(&fifo->tx_lock, flags);
2391                 for (j = 0; j < tx_cfg->fifo_len; j++) {
2392                         txdp = fifo->list_info[j].list_virt_addr;
2393                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2394                         if (skb) {
2395                                 swstats->mem_freed += skb->truesize;
2396                                 dev_kfree_skb(skb);
2397                                 cnt++;
2398                         }
2399                 }
2400                 DBG_PRINT(INTR_DBG,
2401                           "%s: forcibly freeing %d skbs on FIFO%d\n",
2402                           dev->name, cnt, i);
2403                 fifo->tx_curr_get_info.offset = 0;
2404                 fifo->tx_curr_put_info.offset = 0;
2405                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2406         }
2407 }
2408
2409 /**
2410  *   stop_nic -  To stop the nic
2411  *   @nic ; device private variable.
2412  *   Description:
2413  *   This function does exactly the opposite of what the start_nic()
2414  *   function does. This function is called to stop the device.
2415  *   Return Value:
2416  *   void.
2417  */
2418
2419 static void stop_nic(struct s2io_nic *nic)
2420 {
2421         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2422         register u64 val64 = 0;
2423         u16 interruptible;
2424
2425         /*  Disable all interrupts */
2426         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2427         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2428         interruptible |= TX_PIC_INTR;
2429         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2430
2431         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2432         val64 = readq(&bar0->adapter_control);
2433         val64 &= ~(ADAPTER_CNTL_EN);
2434         writeq(val64, &bar0->adapter_control);
2435 }
2436
2437 /**
2438  *  fill_rx_buffers - Allocates the Rx side skbs
2439  *  @ring_info: per ring structure
2440  *  @from_card_up: If this is true, we will map the buffer to get
2441  *     the dma address for buf0 and buf1 to give it to the card.
2442  *     Else we will sync the already mapped buffer to give it to the card.
2443  *  Description:
2444  *  The function allocates Rx side skbs and puts the physical
2445  *  address of these buffers into the RxD buffer pointers, so that the NIC
2446  *  can DMA the received frame into these locations.
2447  *  The NIC supports 3 receive modes, viz
2448  *  1. single buffer,
2449  *  2. three buffer and
2450  *  3. Five buffer modes.
2451  *  Each mode defines how many fragments the received frame will be split
2452  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2453  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2454  *  is split into 3 fragments. As of now only single buffer mode is
2455  *  supported.
2456  *   Return Value:
2457  *  SUCCESS on success or an appropriate -ve value on failure.
2458  */
2459 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2460                            int from_card_up)
2461 {
2462         struct sk_buff *skb;
2463         struct RxD_t *rxdp;
2464         int off, size, block_no, block_no1;
2465         u32 alloc_tab = 0;
2466         u32 alloc_cnt;
2467         u64 tmp;
2468         struct buffAdd *ba;
2469         struct RxD_t *first_rxdp = NULL;
2470         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2471         int rxd_index = 0;
2472         struct RxD1 *rxdp1;
2473         struct RxD3 *rxdp3;
2474         struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2475
2476         alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2477
2478         block_no1 = ring->rx_curr_get_info.block_index;
2479         while (alloc_tab < alloc_cnt) {
2480                 block_no = ring->rx_curr_put_info.block_index;
2481
2482                 off = ring->rx_curr_put_info.offset;
2483
2484                 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2485
2486                 rxd_index = off + 1;
2487                 if (block_no)
2488                         rxd_index += (block_no * ring->rxd_count);
2489
2490                 if ((block_no == block_no1) &&
2491                     (off == ring->rx_curr_get_info.offset) &&
2492                     (rxdp->Host_Control)) {
2493                         DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2494                                   ring->dev->name);
2495                         goto end;
2496                 }
2497                 if (off && (off == ring->rxd_count)) {
2498                         ring->rx_curr_put_info.block_index++;
2499                         if (ring->rx_curr_put_info.block_index ==
2500                             ring->block_count)
2501                                 ring->rx_curr_put_info.block_index = 0;
2502                         block_no = ring->rx_curr_put_info.block_index;
2503                         off = 0;
2504                         ring->rx_curr_put_info.offset = off;
2505                         rxdp = ring->rx_blocks[block_no].block_virt_addr;
2506                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2507                                   ring->dev->name, rxdp);
2508
2509                 }
2510
2511                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2512                     ((ring->rxd_mode == RXD_MODE_3B) &&
2513                      (rxdp->Control_2 & s2BIT(0)))) {
2514                         ring->rx_curr_put_info.offset = off;
2515                         goto end;
2516                 }
2517                 /* calculate size of skb based on ring mode */
2518                 size = ring->mtu +
2519                         HEADER_ETHERNET_II_802_3_SIZE +
2520                         HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2521                 if (ring->rxd_mode == RXD_MODE_1)
2522                         size += NET_IP_ALIGN;
2523                 else
2524                         size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2525
2526                 /* allocate skb */
2527                 skb = netdev_alloc_skb(nic->dev, size);
2528                 if (!skb) {
2529                         DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2530                                   ring->dev->name);
2531                         if (first_rxdp) {
2532                                 wmb();
2533                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2534                         }
2535                         swstats->mem_alloc_fail_cnt++;
2536
2537                         return -ENOMEM ;
2538                 }
2539                 swstats->mem_allocated += skb->truesize;
2540
2541                 if (ring->rxd_mode == RXD_MODE_1) {
2542                         /* 1 buffer mode - normal operation mode */
2543                         rxdp1 = (struct RxD1 *)rxdp;
2544                         memset(rxdp, 0, sizeof(struct RxD1));
2545                         skb_reserve(skb, NET_IP_ALIGN);
2546                         rxdp1->Buffer0_ptr =
2547                                 pci_map_single(ring->pdev, skb->data,
2548                                                size - NET_IP_ALIGN,
2549                                                PCI_DMA_FROMDEVICE);
2550                         if (pci_dma_mapping_error(nic->pdev,
2551                                                   rxdp1->Buffer0_ptr))
2552                                 goto pci_map_failed;
2553
2554                         rxdp->Control_2 =
2555                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2556                         rxdp->Host_Control = (unsigned long)skb;
2557                 } else if (ring->rxd_mode == RXD_MODE_3B) {
2558                         /*
2559                          * 2 buffer mode -
2560                          * 2 buffer mode provides 128
2561                          * byte aligned receive buffers.
2562                          */
2563
2564                         rxdp3 = (struct RxD3 *)rxdp;
2565                         /* save buffer pointers to avoid frequent dma mapping */
2566                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2567                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2568                         memset(rxdp, 0, sizeof(struct RxD3));
2569                         /* restore the buffer pointers for dma sync*/
2570                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2571                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2572
2573                         ba = &ring->ba[block_no][off];
2574                         skb_reserve(skb, BUF0_LEN);
2575                         tmp = (u64)(unsigned long)skb->data;
2576                         tmp += ALIGN_SIZE;
2577                         tmp &= ~ALIGN_SIZE;
2578                         skb->data = (void *) (unsigned long)tmp;
2579                         skb_reset_tail_pointer(skb);
2580
2581                         if (from_card_up) {
2582                                 rxdp3->Buffer0_ptr =
2583                                         pci_map_single(ring->pdev, ba->ba_0,
2584                                                        BUF0_LEN,
2585                                                        PCI_DMA_FROMDEVICE);
2586                                 if (pci_dma_mapping_error(nic->pdev,
2587                                                           rxdp3->Buffer0_ptr))
2588                                         goto pci_map_failed;
2589                         } else
2590                                 pci_dma_sync_single_for_device(ring->pdev,
2591                                                                (dma_addr_t)rxdp3->Buffer0_ptr,
2592                                                                BUF0_LEN,
2593                                                                PCI_DMA_FROMDEVICE);
2594
2595                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2596                         if (ring->rxd_mode == RXD_MODE_3B) {
2597                                 /* Two buffer mode */
2598
2599                                 /*
2600                                  * Buffer2 will have L3/L4 header plus
2601                                  * L4 payload
2602                                  */
2603                                 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2604                                                                     skb->data,
2605                                                                     ring->mtu + 4,
2606                                                                     PCI_DMA_FROMDEVICE);
2607
2608                                 if (pci_dma_mapping_error(nic->pdev,
2609                                                           rxdp3->Buffer2_ptr))
2610                                         goto pci_map_failed;
2611
2612                                 if (from_card_up) {
2613                                         rxdp3->Buffer1_ptr =
2614                                                 pci_map_single(ring->pdev,
2615                                                                ba->ba_1,
2616                                                                BUF1_LEN,
2617                                                                PCI_DMA_FROMDEVICE);
2618
2619                                         if (pci_dma_mapping_error(nic->pdev,
2620                                                                   rxdp3->Buffer1_ptr)) {
2621                                                 pci_unmap_single(ring->pdev,
2622                                                                  (dma_addr_t)(unsigned long)
2623                                                                  skb->data,
2624                                                                  ring->mtu + 4,
2625                                                                  PCI_DMA_FROMDEVICE);
2626                                                 goto pci_map_failed;
2627                                         }
2628                                 }
2629                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2630                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2631                                         (ring->mtu + 4);
2632                         }
2633                         rxdp->Control_2 |= s2BIT(0);
2634                         rxdp->Host_Control = (unsigned long) (skb);
2635                 }
2636                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2637                         rxdp->Control_1 |= RXD_OWN_XENA;
2638                 off++;
2639                 if (off == (ring->rxd_count + 1))
2640                         off = 0;
2641                 ring->rx_curr_put_info.offset = off;
2642
2643                 rxdp->Control_2 |= SET_RXD_MARKER;
2644                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2645                         if (first_rxdp) {
2646                                 wmb();
2647                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2648                         }
2649                         first_rxdp = rxdp;
2650                 }
2651                 ring->rx_bufs_left += 1;
2652                 alloc_tab++;
2653         }
2654
2655 end:
2656         /* Transfer ownership of first descriptor to adapter just before
2657          * exiting. Before that, use memory barrier so that ownership
2658          * and other fields are seen by adapter correctly.
2659          */
2660         if (first_rxdp) {
2661                 wmb();
2662                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2663         }
2664
2665         return SUCCESS;
2666
2667 pci_map_failed:
2668         swstats->pci_map_fail_cnt++;
2669         swstats->mem_freed += skb->truesize;
2670         dev_kfree_skb_irq(skb);
2671         return -ENOMEM;
2672 }
2673
2674 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2675 {
2676         struct net_device *dev = sp->dev;
2677         int j;
2678         struct sk_buff *skb;
2679         struct RxD_t *rxdp;
2680         struct RxD1 *rxdp1;
2681         struct RxD3 *rxdp3;
2682         struct mac_info *mac_control = &sp->mac_control;
2683         struct stat_block *stats = mac_control->stats_info;
2684         struct swStat *swstats = &stats->sw_stat;
2685
2686         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2687                 rxdp = mac_control->rings[ring_no].
2688                         rx_blocks[blk].rxds[j].virt_addr;
2689                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2690                 if (!skb)
2691                         continue;
2692                 if (sp->rxd_mode == RXD_MODE_1) {
2693                         rxdp1 = (struct RxD1 *)rxdp;
2694                         pci_unmap_single(sp->pdev,
2695                                          (dma_addr_t)rxdp1->Buffer0_ptr,
2696                                          dev->mtu +
2697                                          HEADER_ETHERNET_II_802_3_SIZE +
2698                                          HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2699                                          PCI_DMA_FROMDEVICE);
2700                         memset(rxdp, 0, sizeof(struct RxD1));
2701                 } else if (sp->rxd_mode == RXD_MODE_3B) {
2702                         rxdp3 = (struct RxD3 *)rxdp;
2703                         pci_unmap_single(sp->pdev,
2704                                          (dma_addr_t)rxdp3->Buffer0_ptr,
2705                                          BUF0_LEN,
2706                                          PCI_DMA_FROMDEVICE);
2707                         pci_unmap_single(sp->pdev,
2708                                          (dma_addr_t)rxdp3->Buffer1_ptr,
2709                                          BUF1_LEN,
2710                                          PCI_DMA_FROMDEVICE);
2711                         pci_unmap_single(sp->pdev,
2712                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2713                                          dev->mtu + 4,
2714                                          PCI_DMA_FROMDEVICE);
2715                         memset(rxdp, 0, sizeof(struct RxD3));
2716                 }
2717                 swstats->mem_freed += skb->truesize;
2718                 dev_kfree_skb(skb);
2719                 mac_control->rings[ring_no].rx_bufs_left -= 1;
2720         }
2721 }
2722
2723 /**
2724  *  free_rx_buffers - Frees all Rx buffers
2725  *  @sp: device private variable.
2726  *  Description:
2727  *  This function will free all Rx buffers allocated by host.
2728  *  Return Value:
2729  *  NONE.
2730  */
2731
2732 static void free_rx_buffers(struct s2io_nic *sp)
2733 {
2734         struct net_device *dev = sp->dev;
2735         int i, blk = 0, buf_cnt = 0;
2736         struct config_param *config = &sp->config;
2737         struct mac_info *mac_control = &sp->mac_control;
2738
2739         for (i = 0; i < config->rx_ring_num; i++) {
2740                 struct ring_info *ring = &mac_control->rings[i];
2741
2742                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2743                         free_rxd_blk(sp, i, blk);
2744
2745                 ring->rx_curr_put_info.block_index = 0;
2746                 ring->rx_curr_get_info.block_index = 0;
2747                 ring->rx_curr_put_info.offset = 0;
2748                 ring->rx_curr_get_info.offset = 0;
2749                 ring->rx_bufs_left = 0;
2750                 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2751                           dev->name, buf_cnt, i);
2752         }
2753 }
2754
2755 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2756 {
2757         if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2758                 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2759                           ring->dev->name);
2760         }
2761         return 0;
2762 }
2763
2764 /**
2765  * s2io_poll - Rx interrupt handler for NAPI support
2766  * @napi : pointer to the napi structure.
2767  * @budget : The number of packets that were budgeted to be processed
2768  * during  one pass through the 'Poll" function.
2769  * Description:
2770  * Comes into picture only if NAPI support has been incorporated. It does
2771  * the same thing that rx_intr_handler does, but not in a interrupt context
2772  * also It will process only a given number of packets.
2773  * Return value:
2774  * 0 on success and 1 if there are No Rx packets to be processed.
2775  */
2776
2777 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2778 {
2779         struct ring_info *ring = container_of(napi, struct ring_info, napi);
2780         struct net_device *dev = ring->dev;
2781         int pkts_processed = 0;
2782         u8 __iomem *addr = NULL;
2783         u8 val8 = 0;
2784         struct s2io_nic *nic = netdev_priv(dev);
2785         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2786         int budget_org = budget;
2787
2788         if (unlikely(!is_s2io_card_up(nic)))
2789                 return 0;
2790
2791         pkts_processed = rx_intr_handler(ring, budget);
2792         s2io_chk_rx_buffers(nic, ring);
2793
2794         if (pkts_processed < budget_org) {
2795                 napi_complete(napi);
2796                 /*Re Enable MSI-Rx Vector*/
2797                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2798                 addr += 7 - ring->ring_no;
2799                 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2800                 writeb(val8, addr);
2801                 val8 = readb(addr);
2802         }
2803         return pkts_processed;
2804 }
2805
2806 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2807 {
2808         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2809         int pkts_processed = 0;
2810         int ring_pkts_processed, i;
2811         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2812         int budget_org = budget;
2813         struct config_param *config = &nic->config;
2814         struct mac_info *mac_control = &nic->mac_control;
2815
2816         if (unlikely(!is_s2io_card_up(nic)))
2817                 return 0;
2818
2819         for (i = 0; i < config->rx_ring_num; i++) {
2820                 struct ring_info *ring = &mac_control->rings[i];
2821                 ring_pkts_processed = rx_intr_handler(ring, budget);
2822                 s2io_chk_rx_buffers(nic, ring);
2823                 pkts_processed += ring_pkts_processed;
2824                 budget -= ring_pkts_processed;
2825                 if (budget <= 0)
2826                         break;
2827         }
2828         if (pkts_processed < budget_org) {
2829                 napi_complete(napi);
2830                 /* Re enable the Rx interrupts for the ring */
2831                 writeq(0, &bar0->rx_traffic_mask);
2832                 readl(&bar0->rx_traffic_mask);
2833         }
2834         return pkts_processed;
2835 }
2836
2837 #ifdef CONFIG_NET_POLL_CONTROLLER
2838 /**
2839  * s2io_netpoll - netpoll event handler entry point
2840  * @dev : pointer to the device structure.
2841  * Description:
2842  *      This function will be called by upper layer to check for events on the
2843  * interface in situations where interrupts are disabled. It is used for
2844  * specific in-kernel networking tasks, such as remote consoles and kernel
2845  * debugging over the network (example netdump in RedHat).
2846  */
2847 static void s2io_netpoll(struct net_device *dev)
2848 {
2849         struct s2io_nic *nic = netdev_priv(dev);
2850         const int irq = nic->pdev->irq;
2851         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2852         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2853         int i;
2854         struct config_param *config = &nic->config;
2855         struct mac_info *mac_control = &nic->mac_control;
2856
2857         if (pci_channel_offline(nic->pdev))
2858                 return;
2859
2860         disable_irq(irq);
2861
2862         writeq(val64, &bar0->rx_traffic_int);
2863         writeq(val64, &bar0->tx_traffic_int);
2864
2865         /* we need to free up the transmitted skbufs or else netpoll will
2866          * run out of skbs and will fail and eventually netpoll application such
2867          * as netdump will fail.
2868          */
2869         for (i = 0; i < config->tx_fifo_num; i++)
2870                 tx_intr_handler(&mac_control->fifos[i]);
2871
2872         /* check for received packet and indicate up to network */
2873         for (i = 0; i < config->rx_ring_num; i++) {
2874                 struct ring_info *ring = &mac_control->rings[i];
2875
2876                 rx_intr_handler(ring, 0);
2877         }
2878
2879         for (i = 0; i < config->rx_ring_num; i++) {
2880                 struct ring_info *ring = &mac_control->rings[i];
2881
2882                 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2883                         DBG_PRINT(INFO_DBG,
2884                                   "%s: Out of memory in Rx Netpoll!!\n",
2885                                   dev->name);
2886                         break;
2887                 }
2888         }
2889         enable_irq(irq);
2890 }
2891 #endif
2892
2893 /**
2894  *  rx_intr_handler - Rx interrupt handler
2895  *  @ring_info: per ring structure.
2896  *  @budget: budget for napi processing.
2897  *  Description:
2898  *  If the interrupt is because of a received frame or if the
2899  *  receive ring contains fresh as yet un-processed frames,this function is
2900  *  called. It picks out the RxD at which place the last Rx processing had
2901  *  stopped and sends the skb to the OSM's Rx handler and then increments
2902  *  the offset.
2903  *  Return Value:
2904  *  No. of napi packets processed.
2905  */
2906 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2907 {
2908         int get_block, put_block;
2909         struct rx_curr_get_info get_info, put_info;
2910         struct RxD_t *rxdp;
2911         struct sk_buff *skb;
2912         int pkt_cnt = 0, napi_pkts = 0;
2913         int i;
2914         struct RxD1 *rxdp1;
2915         struct RxD3 *rxdp3;
2916
2917         if (budget <= 0)
2918                 return napi_pkts;
2919
2920         get_info = ring_data->rx_curr_get_info;
2921         get_block = get_info.block_index;
2922         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2923         put_block = put_info.block_index;
2924         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2925
2926         while (RXD_IS_UP2DT(rxdp)) {
2927                 /*
2928                  * If your are next to put index then it's
2929                  * FIFO full condition
2930                  */
2931                 if ((get_block == put_block) &&
2932                     (get_info.offset + 1) == put_info.offset) {
2933                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2934                                   ring_data->dev->name);
2935                         break;
2936                 }
2937                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2938                 if (skb == NULL) {
2939                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2940                                   ring_data->dev->name);
2941                         return 0;
2942                 }
2943                 if (ring_data->rxd_mode == RXD_MODE_1) {
2944                         rxdp1 = (struct RxD1 *)rxdp;
2945                         pci_unmap_single(ring_data->pdev, (dma_addr_t)
2946                                          rxdp1->Buffer0_ptr,
2947                                          ring_data->mtu +
2948                                          HEADER_ETHERNET_II_802_3_SIZE +
2949                                          HEADER_802_2_SIZE +
2950                                          HEADER_SNAP_SIZE,
2951                                          PCI_DMA_FROMDEVICE);
2952                 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
2953                         rxdp3 = (struct RxD3 *)rxdp;
2954                         pci_dma_sync_single_for_cpu(ring_data->pdev,
2955                                                     (dma_addr_t)rxdp3->Buffer0_ptr,
2956                                                     BUF0_LEN,
2957                                                     PCI_DMA_FROMDEVICE);
2958                         pci_unmap_single(ring_data->pdev,
2959                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2960                                          ring_data->mtu + 4,
2961                                          PCI_DMA_FROMDEVICE);
2962                 }
2963                 prefetch(skb->data);
2964                 rx_osm_handler(ring_data, rxdp);
2965                 get_info.offset++;
2966                 ring_data->rx_curr_get_info.offset = get_info.offset;
2967                 rxdp = ring_data->rx_blocks[get_block].
2968                         rxds[get_info.offset].virt_addr;
2969                 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
2970                         get_info.offset = 0;
2971                         ring_data->rx_curr_get_info.offset = get_info.offset;
2972                         get_block++;
2973                         if (get_block == ring_data->block_count)
2974                                 get_block = 0;
2975                         ring_data->rx_curr_get_info.block_index = get_block;
2976                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2977                 }
2978
2979                 if (ring_data->nic->config.napi) {
2980                         budget--;
2981                         napi_pkts++;
2982                         if (!budget)
2983                                 break;
2984                 }
2985                 pkt_cnt++;
2986                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2987                         break;
2988         }
2989         if (ring_data->lro) {
2990                 /* Clear all LRO sessions before exiting */
2991                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
2992                         struct lro *lro = &ring_data->lro0_n[i];
2993                         if (lro->in_use) {
2994                                 update_L3L4_header(ring_data->nic, lro);
2995                                 queue_rx_frame(lro->parent, lro->vlan_tag);
2996                                 clear_lro_session(lro);
2997                         }
2998                 }
2999         }
3000         return napi_pkts;
3001 }
3002
3003 /**
3004  *  tx_intr_handler - Transmit interrupt handler
3005  *  @nic : device private variable
3006  *  Description:
3007  *  If an interrupt was raised to indicate DMA complete of the
3008  *  Tx packet, this function is called. It identifies the last TxD
3009  *  whose buffer was freed and frees all skbs whose data have already
3010  *  DMA'ed into the NICs internal memory.
3011  *  Return Value:
3012  *  NONE
3013  */
3014
3015 static void tx_intr_handler(struct fifo_info *fifo_data)
3016 {
3017         struct s2io_nic *nic = fifo_data->nic;
3018         struct tx_curr_get_info get_info, put_info;
3019         struct sk_buff *skb = NULL;
3020         struct TxD *txdlp;
3021         int pkt_cnt = 0;
3022         unsigned long flags = 0;
3023         u8 err_mask;
3024         struct stat_block *stats = nic->mac_control.stats_info;
3025         struct swStat *swstats = &stats->sw_stat;
3026
3027         if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3028                 return;
3029
3030         get_info = fifo_data->tx_curr_get_info;
3031         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3032         txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3033         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3034                (get_info.offset != put_info.offset) &&
3035                (txdlp->Host_Control)) {
3036                 /* Check for TxD errors */
3037                 if (txdlp->Control_1 & TXD_T_CODE) {
3038                         unsigned long long err;
3039                         err = txdlp->Control_1 & TXD_T_CODE;
3040                         if (err & 0x1) {
3041                                 swstats->parity_err_cnt++;
3042                         }
3043
3044                         /* update t_code statistics */
3045                         err_mask = err >> 48;
3046                         switch (err_mask) {
3047                         case 2:
3048                                 swstats->tx_buf_abort_cnt++;
3049                                 break;
3050
3051                         case 3:
3052                                 swstats->tx_desc_abort_cnt++;
3053                                 break;
3054
3055                         case 7:
3056                                 swstats->tx_parity_err_cnt++;
3057                                 break;
3058
3059                         case 10:
3060                                 swstats->tx_link_loss_cnt++;
3061                                 break;
3062
3063                         case 15:
3064                                 swstats->tx_list_proc_err_cnt++;
3065                                 break;
3066                         }
3067                 }
3068
3069                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3070                 if (skb == NULL) {
3071                         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3072                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3073                                   __func__);
3074                         return;
3075                 }
3076                 pkt_cnt++;
3077
3078                 /* Updating the statistics block */
3079                 swstats->mem_freed += skb->truesize;
3080                 dev_kfree_skb_irq(skb);
3081
3082                 get_info.offset++;
3083                 if (get_info.offset == get_info.fifo_len + 1)
3084                         get_info.offset = 0;
3085                 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3086                 fifo_data->tx_curr_get_info.offset = get_info.offset;
3087         }
3088
3089         s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3090
3091         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3092 }
3093
3094 /**
3095  *  s2io_mdio_write - Function to write in to MDIO registers
3096  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3097  *  @addr     : address value
3098  *  @value    : data value
3099  *  @dev      : pointer to net_device structure
3100  *  Description:
3101  *  This function is used to write values to the MDIO registers
3102  *  NONE
3103  */
3104 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3105                             struct net_device *dev)
3106 {
3107         u64 val64;
3108         struct s2io_nic *sp = netdev_priv(dev);
3109         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3110
3111         /* address transaction */
3112         val64 = MDIO_MMD_INDX_ADDR(addr) |
3113                 MDIO_MMD_DEV_ADDR(mmd_type) |
3114                 MDIO_MMS_PRT_ADDR(0x0);
3115         writeq(val64, &bar0->mdio_control);
3116         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3117         writeq(val64, &bar0->mdio_control);
3118         udelay(100);
3119
3120         /* Data transaction */
3121         val64 = MDIO_MMD_INDX_ADDR(addr) |
3122                 MDIO_MMD_DEV_ADDR(mmd_type) |
3123                 MDIO_MMS_PRT_ADDR(0x0) |
3124                 MDIO_MDIO_DATA(value) |
3125                 MDIO_OP(MDIO_OP_WRITE_TRANS);
3126         writeq(val64, &bar0->mdio_control);
3127         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3128         writeq(val64, &bar0->mdio_control);
3129         udelay(100);
3130
3131         val64 = MDIO_MMD_INDX_ADDR(addr) |
3132                 MDIO_MMD_DEV_ADDR(mmd_type) |
3133                 MDIO_MMS_PRT_ADDR(0x0) |
3134                 MDIO_OP(MDIO_OP_READ_TRANS);
3135         writeq(val64, &bar0->mdio_control);
3136         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3137         writeq(val64, &bar0->mdio_control);
3138         udelay(100);
3139 }
3140
3141 /**
3142  *  s2io_mdio_read - Function to write in to MDIO registers
3143  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3144  *  @addr     : address value
3145  *  @dev      : pointer to net_device structure
3146  *  Description:
3147  *  This function is used to read values to the MDIO registers
3148  *  NONE
3149  */
3150 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3151 {
3152         u64 val64 = 0x0;
3153         u64 rval64 = 0x0;
3154         struct s2io_nic *sp = netdev_priv(dev);
3155         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3156
3157         /* address transaction */
3158         val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3159                          | MDIO_MMD_DEV_ADDR(mmd_type)
3160                          | MDIO_MMS_PRT_ADDR(0x0));
3161         writeq(val64, &bar0->mdio_control);
3162         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3163         writeq(val64, &bar0->mdio_control);
3164         udelay(100);
3165
3166         /* Data transaction */
3167         val64 = MDIO_MMD_INDX_ADDR(addr) |
3168                 MDIO_MMD_DEV_ADDR(mmd_type) |
3169                 MDIO_MMS_PRT_ADDR(0x0) |
3170                 MDIO_OP(MDIO_OP_READ_TRANS);
3171         writeq(val64, &bar0->mdio_control);
3172         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3173         writeq(val64, &bar0->mdio_control);
3174         udelay(100);
3175
3176         /* Read the value from regs */
3177         rval64 = readq(&bar0->mdio_control);
3178         rval64 = rval64 & 0xFFFF0000;
3179         rval64 = rval64 >> 16;
3180         return rval64;
3181 }
3182
3183 /**
3184  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3185  *  @counter      : counter value to be updated
3186  *  @flag         : flag to indicate the status
3187  *  @type         : counter type
3188  *  Description:
3189  *  This function is to check the status of the xpak counters value
3190  *  NONE
3191  */
3192
3193 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3194                                   u16 flag, u16 type)
3195 {
3196         u64 mask = 0x3;
3197         u64 val64;
3198         int i;
3199         for (i = 0; i < index; i++)
3200                 mask = mask << 0x2;
3201
3202         if (flag > 0) {
3203                 *counter = *counter + 1;
3204                 val64 = *regs_stat & mask;
3205                 val64 = val64 >> (index * 0x2);
3206                 val64 = val64 + 1;
3207                 if (val64 == 3) {
3208                         switch (type) {
3209                         case 1:
3210                                 DBG_PRINT(ERR_DBG,
3211                                           "Take Xframe NIC out of service.\n");
3212                                 DBG_PRINT(ERR_DBG,
3213 "Excessive temperatures may result in premature transceiver failure.\n");
3214                                 break;
3215                         case 2:
3216                                 DBG_PRINT(ERR_DBG,
3217                                           "Take Xframe NIC out of service.\n");
3218                                 DBG_PRINT(ERR_DBG,
3219 "Excessive bias currents may indicate imminent laser diode failure.\n");
3220                                 break;
3221                         case 3:
3222                                 DBG_PRINT(ERR_DBG,
3223                                           "Take Xframe NIC out of service.\n");
3224                                 DBG_PRINT(ERR_DBG,
3225 "Excessive laser output power may saturate far-end receiver.\n");
3226                                 break;
3227                         default:
3228                                 DBG_PRINT(ERR_DBG,
3229                                           "Incorrect XPAK Alarm type\n");
3230                         }
3231                         val64 = 0x0;
3232                 }
3233                 val64 = val64 << (index * 0x2);
3234                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3235
3236         } else {
3237                 *regs_stat = *regs_stat & (~mask);
3238         }
3239 }
3240
3241 /**
3242  *  s2io_updt_xpak_counter - Function to update the xpak counters
3243  *  @dev         : pointer to net_device struct
3244  *  Description:
3245  *  This function is to upate the status of the xpak counters value
3246  *  NONE
3247  */
3248 static void s2io_updt_xpak_counter(struct net_device *dev)
3249 {
3250         u16 flag  = 0x0;
3251         u16 type  = 0x0;
3252         u16 val16 = 0x0;
3253         u64 val64 = 0x0;
3254         u64 addr  = 0x0;
3255
3256         struct s2io_nic *sp = netdev_priv(dev);
3257         struct stat_block *stats = sp->mac_control.stats_info;
3258         struct xpakStat *xstats = &stats->xpak_stat;
3259
3260         /* Check the communication with the MDIO slave */
3261         addr = MDIO_CTRL1;
3262         val64 = 0x0;
3263         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3264         if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3265                 DBG_PRINT(ERR_DBG,
3266                           "ERR: MDIO slave access failed - Returned %llx\n",
3267                           (unsigned long long)val64);
3268                 return;
3269         }
3270
3271         /* Check for the expected value of control reg 1 */
3272         if (val64 != MDIO_CTRL1_SPEED10G) {
3273                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3274                           "Returned: %llx- Expected: 0x%x\n",
3275                           (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3276                 return;
3277         }
3278
3279         /* Loading the DOM register to MDIO register */
3280         addr = 0xA100;
3281         s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3282         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3283
3284         /* Reading the Alarm flags */
3285         addr = 0xA070;
3286         val64 = 0x0;
3287         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3288
3289         flag = CHECKBIT(val64, 0x7);
3290         type = 1;
3291         s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3292                               &xstats->xpak_regs_stat,
3293                               0x0, flag, type);
3294
3295         if (CHECKBIT(val64, 0x6))
3296                 xstats->alarm_transceiver_temp_low++;
3297
3298         flag = CHECKBIT(val64, 0x3);
3299         type = 2;
3300         s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3301                               &xstats->xpak_regs_stat,
3302                               0x2, flag, type);
3303
3304         if (CHECKBIT(val64, 0x2))
3305                 xstats->alarm_laser_bias_current_low++;
3306
3307         flag = CHECKBIT(val64, 0x1);
3308         type = 3;
3309         s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3310                               &xstats->xpak_regs_stat,
3311                               0x4, flag, type);
3312
3313         if (CHECKBIT(val64, 0x0))
3314                 xstats->alarm_laser_output_power_low++;
3315
3316         /* Reading the Warning flags */
3317         addr = 0xA074;
3318         val64 = 0x0;
3319         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3320
3321         if (CHECKBIT(val64, 0x7))
3322                 xstats->warn_transceiver_temp_high++;
3323
3324         if (CHECKBIT(val64, 0x6))
3325                 xstats->warn_transceiver_temp_low++;
3326
3327         if (CHECKBIT(val64, 0x3))
3328                 xstats->warn_laser_bias_current_high++;
3329
3330         if (CHECKBIT(val64, 0x2))
3331                 xstats->warn_laser_bias_current_low++;
3332
3333         if (CHECKBIT(val64, 0x1))
3334                 xstats->warn_laser_output_power_high++;
3335
3336         if (CHECKBIT(val64, 0x0))
3337                 xstats->warn_laser_output_power_low++;
3338 }
3339
3340 /**
3341  *  wait_for_cmd_complete - waits for a command to complete.
3342  *  @sp : private member of the device structure, which is a pointer to the
3343  *  s2io_nic structure.
3344  *  Description: Function that waits for a command to Write into RMAC
3345  *  ADDR DATA registers to be completed and returns either success or
3346  *  error depending on whether the command was complete or not.
3347  *  Return value:
3348  *   SUCCESS on success and FAILURE on failure.
3349  */
3350
3351 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3352                                  int bit_state)
3353 {
3354         int ret = FAILURE, cnt = 0, delay = 1;
3355         u64 val64;
3356
3357         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3358                 return FAILURE;
3359
3360         do {
3361                 val64 = readq(addr);
3362                 if (bit_state == S2IO_BIT_RESET) {
3363                         if (!(val64 & busy_bit)) {
3364                                 ret = SUCCESS;
3365                                 break;
3366                         }
3367                 } else {
3368                         if (val64 & busy_bit) {
3369                                 ret = SUCCESS;
3370                                 break;
3371                         }
3372                 }
3373
3374                 if (in_interrupt())
3375                         mdelay(delay);
3376                 else
3377                         msleep(delay);
3378
3379                 if (++cnt >= 10)
3380                         delay = 50;
3381         } while (cnt < 20);
3382         return ret;
3383 }
3384 /**
3385  * check_pci_device_id - Checks if the device id is supported
3386  * @id : device id
3387  * Description: Function to check if the pci device id is supported by driver.
3388  * Return value: Actual device id if supported else PCI_ANY_ID
3389  */
3390 static u16 check_pci_device_id(u16 id)
3391 {
3392         switch (id) {
3393         case PCI_DEVICE_ID_HERC_WIN:
3394         case PCI_DEVICE_ID_HERC_UNI:
3395                 return XFRAME_II_DEVICE;
3396         case PCI_DEVICE_ID_S2IO_UNI:
3397         case PCI_DEVICE_ID_S2IO_WIN:
3398                 return XFRAME_I_DEVICE;
3399         default:
3400                 return PCI_ANY_ID;
3401         }
3402 }
3403
3404 /**
3405  *  s2io_reset - Resets the card.
3406  *  @sp : private member of the device structure.
3407  *  Description: Function to Reset the card. This function then also
3408  *  restores the previously saved PCI configuration space registers as
3409  *  the card reset also resets the configuration space.
3410  *  Return value:
3411  *  void.
3412  */
3413
3414 static void s2io_reset(struct s2io_nic *sp)
3415 {
3416         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3417         u64 val64;
3418         u16 subid, pci_cmd;
3419         int i;
3420         u16 val16;
3421         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3422         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3423         struct stat_block *stats;
3424         struct swStat *swstats;
3425
3426         DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3427                   __func__, pci_name(sp->pdev));
3428
3429         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3430         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3431
3432         val64 = SW_RESET_ALL;
3433         writeq(val64, &bar0->sw_reset);
3434         if (strstr(sp->product_name, "CX4"))
3435                 msleep(750);
3436         msleep(250);
3437         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3438
3439                 /* Restore the PCI state saved during initialization. */
3440                 pci_restore_state(sp->pdev);
3441                 pci_save_state(sp->pdev);
3442                 pci_read_config_word(sp->pdev, 0x2, &val16);
3443                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3444                         break;
3445                 msleep(200);
3446         }
3447
3448         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3449                 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3450
3451         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3452
3453         s2io_init_pci(sp);
3454
3455         /* Set swapper to enable I/O register access */
3456         s2io_set_swapper(sp);
3457
3458         /* restore mac_addr entries */
3459         do_s2io_restore_unicast_mc(sp);
3460
3461         /* Restore the MSIX table entries from local variables */
3462         restore_xmsi_data(sp);
3463
3464         /* Clear certain PCI/PCI-X fields after reset */
3465         if (sp->device_type == XFRAME_II_DEVICE) {
3466                 /* Clear "detected parity error" bit */
3467                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3468
3469                 /* Clearing PCIX Ecc status register */
3470                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3471
3472                 /* Clearing PCI_STATUS error reflected here */
3473                 writeq(s2BIT(62), &bar0->txpic_int_reg);
3474         }
3475
3476         /* Reset device statistics maintained by OS */
3477         memset(&sp->stats, 0, sizeof(struct net_device_stats));
3478
3479         stats = sp->mac_control.stats_info;
3480         swstats = &stats->sw_stat;
3481
3482         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3483         up_cnt = swstats->link_up_cnt;
3484         down_cnt = swstats->link_down_cnt;
3485         up_time = swstats->link_up_time;
3486         down_time = swstats->link_down_time;
3487         reset_cnt = swstats->soft_reset_cnt;
3488         mem_alloc_cnt = swstats->mem_allocated;
3489         mem_free_cnt = swstats->mem_freed;
3490         watchdog_cnt = swstats->watchdog_timer_cnt;
3491
3492         memset(stats, 0, sizeof(struct stat_block));
3493
3494         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3495         swstats->link_up_cnt = up_cnt;
3496         swstats->link_down_cnt = down_cnt;
3497         swstats->link_up_time = up_time;
3498         swstats->link_down_time = down_time;
3499         swstats->soft_reset_cnt = reset_cnt;
3500         swstats->mem_allocated = mem_alloc_cnt;
3501         swstats->mem_freed = mem_free_cnt;
3502         swstats->watchdog_timer_cnt = watchdog_cnt;
3503
3504         /* SXE-002: Configure link and activity LED to turn it off */
3505         subid = sp->pdev->subsystem_device;
3506         if (((subid & 0xFF) >= 0x07) &&
3507             (sp->device_type == XFRAME_I_DEVICE)) {
3508                 val64 = readq(&bar0->gpio_control);
3509                 val64 |= 0x0000800000000000ULL;
3510                 writeq(val64, &bar0->gpio_control);
3511                 val64 = 0x0411040400000000ULL;
3512                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3513         }
3514
3515         /*
3516          * Clear spurious ECC interrupts that would have occurred on
3517          * XFRAME II cards after reset.
3518          */
3519         if (sp->device_type == XFRAME_II_DEVICE) {
3520                 val64 = readq(&bar0->pcc_err_reg);
3521                 writeq(val64, &bar0->pcc_err_reg);
3522         }
3523
3524         sp->device_enabled_once = false;
3525 }
3526
3527 /**
3528  *  s2io_set_swapper - to set the swapper controle on the card
3529  *  @sp : private member of the device structure,
3530  *  pointer to the s2io_nic structure.
3531  *  Description: Function to set the swapper control on the card
3532  *  correctly depending on the 'endianness' of the system.
3533  *  Return value:
3534  *  SUCCESS on success and FAILURE on failure.
3535  */
3536
3537 static int s2io_set_swapper(struct s2io_nic *sp)
3538 {
3539         struct net_device *dev = sp->dev;
3540         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3541         u64 val64, valt, valr;
3542
3543         /*
3544          * Set proper endian settings and verify the same by reading
3545          * the PIF Feed-back register.
3546          */
3547
3548         val64 = readq(&bar0->pif_rd_swapper_fb);
3549         if (val64 != 0x0123456789ABCDEFULL) {
3550                 int i = 0;
3551                 static const u64 value[] = {
3552                         0xC30000C3C30000C3ULL,  /* FE=1, SE=1 */
3553                         0x8100008181000081ULL,  /* FE=1, SE=0 */
3554                         0x4200004242000042ULL,  /* FE=0, SE=1 */
3555                         0                       /* FE=0, SE=0 */
3556                 };
3557
3558                 while (i < 4) {
3559                         writeq(value[i], &bar0->swapper_ctrl);
3560                         val64 = readq(&bar0->pif_rd_swapper_fb);
3561                         if (val64 == 0x0123456789ABCDEFULL)
3562                                 break;
3563                         i++;
3564                 }
3565                 if (i == 4) {
3566                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3567                                   "feedback read %llx\n",
3568                                   dev->name, (unsigned long long)val64);
3569                         return FAILURE;
3570                 }
3571                 valr = value[i];
3572         } else {
3573                 valr = readq(&bar0->swapper_ctrl);
3574         }
3575
3576         valt = 0x0123456789ABCDEFULL;
3577         writeq(valt, &bar0->xmsi_address);
3578         val64 = readq(&bar0->xmsi_address);
3579
3580         if (val64 != valt) {
3581                 int i = 0;
3582                 static const u64 value[] = {
3583                         0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3584                         0x0081810000818100ULL,  /* FE=1, SE=0 */
3585                         0x0042420000424200ULL,  /* FE=0, SE=1 */
3586                         0                       /* FE=0, SE=0 */
3587                 };
3588
3589                 while (i < 4) {
3590                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3591                         writeq(valt, &bar0->xmsi_address);
3592                         val64 = readq(&bar0->xmsi_address);
3593                         if (val64 == valt)
3594                                 break;
3595                         i++;
3596                 }
3597                 if (i == 4) {
3598                         unsigned long long x = val64;
3599                         DBG_PRINT(ERR_DBG,
3600                                   "Write failed, Xmsi_addr reads:0x%llx\n", x);
3601                         return FAILURE;
3602                 }
3603         }
3604         val64 = readq(&bar0->swapper_ctrl);
3605         val64 &= 0xFFFF000000000000ULL;
3606
3607 #ifdef __BIG_ENDIAN
3608         /*
3609          * The device by default set to a big endian format, so a
3610          * big endian driver need not set anything.
3611          */
3612         val64 |= (SWAPPER_CTRL_TXP_FE |
3613                   SWAPPER_CTRL_TXP_SE |
3614                   SWAPPER_CTRL_TXD_R_FE |
3615                   SWAPPER_CTRL_TXD_W_FE |
3616                   SWAPPER_CTRL_TXF_R_FE |
3617                   SWAPPER_CTRL_RXD_R_FE |
3618                   SWAPPER_CTRL_RXD_W_FE |
3619                   SWAPPER_CTRL_RXF_W_FE |
3620                   SWAPPER_CTRL_XMSI_FE |
3621                   SWAPPER_CTRL_STATS_FE |
3622                   SWAPPER_CTRL_STATS_SE);
3623         if (sp->config.intr_type == INTA)
3624                 val64 |= SWAPPER_CTRL_XMSI_SE;
3625         writeq(val64, &bar0->swapper_ctrl);
3626 #else
3627         /*
3628          * Initially we enable all bits to make it accessible by the
3629          * driver, then we selectively enable only those bits that
3630          * we want to set.
3631          */
3632         val64 |= (SWAPPER_CTRL_TXP_FE |
3633                   SWAPPER_CTRL_TXP_SE |
3634                   SWAPPER_CTRL_TXD_R_FE |
3635                   SWAPPER_CTRL_TXD_R_SE |
3636                   SWAPPER_CTRL_TXD_W_FE |
3637                   SWAPPER_CTRL_TXD_W_SE |
3638                   SWAPPER_CTRL_TXF_R_FE |
3639                   SWAPPER_CTRL_RXD_R_FE |
3640                   SWAPPER_CTRL_RXD_R_SE |
3641                   SWAPPER_CTRL_RXD_W_FE |
3642                   SWAPPER_CTRL_RXD_W_SE |
3643                   SWAPPER_CTRL_RXF_W_FE |
3644                   SWAPPER_CTRL_XMSI_FE |
3645                   SWAPPER_CTRL_STATS_FE |
3646                   SWAPPER_CTRL_STATS_SE);
3647         if (sp->config.intr_type == INTA)
3648                 val64 |= SWAPPER_CTRL_XMSI_SE;
3649         writeq(val64, &bar0->swapper_ctrl);
3650 #endif
3651         val64 = readq(&bar0->swapper_ctrl);
3652
3653         /*
3654          * Verifying if endian settings are accurate by reading a
3655          * feedback register.
3656          */
3657         val64 = readq(&bar0->pif_rd_swapper_fb);
3658         if (val64 != 0x0123456789ABCDEFULL) {
3659                 /* Endian settings are incorrect, calls for another dekko. */
3660                 DBG_PRINT(ERR_DBG,
3661                           "%s: Endian settings are wrong, feedback read %llx\n",
3662                           dev->name, (unsigned long long)val64);
3663                 return FAILURE;
3664         }
3665
3666         return SUCCESS;
3667 }
3668
3669 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3670 {
3671         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3672         u64 val64;
3673         int ret = 0, cnt = 0;
3674
3675         do {
3676                 val64 = readq(&bar0->xmsi_access);
3677                 if (!(val64 & s2BIT(15)))
3678                         break;
3679                 mdelay(1);
3680                 cnt++;
3681         } while (cnt < 5);
3682         if (cnt == 5) {
3683                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3684                 ret = 1;
3685         }
3686
3687         return ret;
3688 }
3689
3690 static void restore_xmsi_data(struct s2io_nic *nic)
3691 {
3692         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3693         u64 val64;
3694         int i, msix_index;
3695
3696         if (nic->device_type == XFRAME_I_DEVICE)
3697                 return;
3698
3699         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3700                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3701                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3702                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3703                 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3704                 writeq(val64, &bar0->xmsi_access);
3705                 if (wait_for_msix_trans(nic, msix_index)) {
3706                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3707                                   __func__, msix_index);
3708                         continue;
3709                 }
3710         }
3711 }
3712
3713 static void store_xmsi_data(struct s2io_nic *nic)
3714 {
3715         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3716         u64 val64, addr, data;
3717         int i, msix_index;
3718
3719         if (nic->device_type == XFRAME_I_DEVICE)
3720                 return;
3721
3722         /* Store and display */
3723         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3724                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3725                 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3726                 writeq(val64, &bar0->xmsi_access);
3727                 if (wait_for_msix_trans(nic, msix_index)) {
3728                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3729                                   __func__, msix_index);
3730                         continue;
3731                 }
3732                 addr = readq(&bar0->xmsi_address);
3733                 data = readq(&bar0->xmsi_data);
3734                 if (addr && data) {
3735                         nic->msix_info[i].addr = addr;
3736                         nic->msix_info[i].data = data;
3737                 }
3738         }
3739 }
3740
3741 static int s2io_enable_msi_x(struct s2io_nic *nic)
3742 {
3743         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3744         u64 rx_mat;
3745         u16 msi_control; /* Temp variable */
3746         int ret, i, j, msix_indx = 1;
3747         int size;
3748         struct stat_block *stats = nic->mac_control.stats_info;
3749         struct swStat *swstats = &stats->sw_stat;
3750
3751         size = nic->num_entries * sizeof(struct msix_entry);
3752         nic->entries = kzalloc(size, GFP_KERNEL);
3753         if (!nic->entries) {
3754                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3755                           __func__);
3756                 swstats->mem_alloc_fail_cnt++;
3757                 return -ENOMEM;
3758         }
3759         swstats->mem_allocated += size;
3760
3761         size = nic->num_entries * sizeof(struct s2io_msix_entry);
3762         nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3763         if (!nic->s2io_entries) {
3764                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3765                           __func__);
3766                 swstats->mem_alloc_fail_cnt++;
3767                 kfree(nic->entries);
3768                 swstats->mem_freed
3769                         += (nic->num_entries * sizeof(struct msix_entry));
3770                 return -ENOMEM;
3771         }
3772         swstats->mem_allocated += size;
3773
3774         nic->entries[0].entry = 0;
3775         nic->s2io_entries[0].entry = 0;
3776         nic->s2io_entries[0].in_use = MSIX_FLG;
3777         nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3778         nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3779
3780         for (i = 1; i < nic->num_entries; i++) {
3781                 nic->entries[i].entry = ((i - 1) * 8) + 1;
3782                 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3783                 nic->s2io_entries[i].arg = NULL;
3784                 nic->s2io_entries[i].in_use = 0;
3785         }
3786
3787         rx_mat = readq(&bar0->rx_mat);
3788         for (j = 0; j < nic->config.rx_ring_num; j++) {
3789                 rx_mat |= RX_MAT_SET(j, msix_indx);
3790                 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3791                 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3792                 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3793                 msix_indx += 8;
3794         }
3795         writeq(rx_mat, &bar0->rx_mat);
3796         readq(&bar0->rx_mat);
3797
3798         ret = pci_enable_msix_range(nic->pdev, nic->entries,
3799                                     nic->num_entries, nic->num_entries);
3800         /* We fail init if error or we get less vectors than min required */
3801         if (ret < 0) {
3802                 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3803                 kfree(nic->entries);
3804                 swstats->mem_freed += nic->num_entries *
3805                         sizeof(struct msix_entry);
3806                 kfree(nic->s2io_entries);
3807                 swstats->mem_freed += nic->num_entries *
3808                         sizeof(struct s2io_msix_entry);
3809                 nic->entries = NULL;
3810                 nic->s2io_entries = NULL;
3811                 return -ENOMEM;
3812         }
3813
3814         /*
3815          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3816          * in the herc NIC. (Temp change, needs to be removed later)
3817          */
3818         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3819         msi_control |= 0x1; /* Enable MSI */
3820         pci_write_config_word(nic->pdev, 0x42, msi_control);
3821
3822         return 0;
3823 }
3824
3825 /* Handle software interrupt used during MSI(X) test */
3826 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3827 {
3828         struct s2io_nic *sp = dev_id;
3829
3830         sp->msi_detected = 1;
3831         wake_up(&sp->msi_wait);
3832
3833         return IRQ_HANDLED;
3834 }
3835
3836 /* Test interrupt path by forcing a a software IRQ */
3837 static int s2io_test_msi(struct s2io_nic *sp)
3838 {
3839         struct pci_dev *pdev = sp->pdev;
3840         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3841         int err;
3842         u64 val64, saved64;
3843
3844         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3845                           sp->name, sp);
3846         if (err) {
3847                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3848                           sp->dev->name, pci_name(pdev), pdev->irq);
3849                 return err;
3850         }
3851
3852         init_waitqueue_head(&sp->msi_wait);
3853         sp->msi_detected = 0;
3854
3855         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3856         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3857         val64 |= SCHED_INT_CTRL_TIMER_EN;
3858         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3859         writeq(val64, &bar0->scheduled_int_ctrl);
3860
3861         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3862
3863         if (!sp->msi_detected) {
3864                 /* MSI(X) test failed, go back to INTx mode */
3865                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3866                           "using MSI(X) during test\n",
3867                           sp->dev->name, pci_name(pdev));
3868
3869                 err = -EOPNOTSUPP;
3870         }
3871
3872         free_irq(sp->entries[1].vector, sp);
3873
3874         writeq(saved64, &bar0->scheduled_int_ctrl);
3875
3876         return err;
3877 }
3878
3879 static void remove_msix_isr(struct s2io_nic *sp)
3880 {
3881         int i;
3882         u16 msi_control;
3883
3884         for (i = 0; i < sp->num_entries; i++) {
3885                 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3886                         int vector = sp->entries[i].vector;
3887                         void *arg = sp->s2io_entries[i].arg;
3888                         free_irq(vector, arg);
3889                 }
3890         }
3891
3892         kfree(sp->entries);
3893         kfree(sp->s2io_entries);
3894         sp->entries = NULL;
3895         sp->s2io_entries = NULL;
3896
3897         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3898         msi_control &= 0xFFFE; /* Disable MSI */
3899         pci_write_config_word(sp->pdev, 0x42, msi_control);
3900
3901         pci_disable_msix(sp->pdev);
3902 }
3903
3904 static void remove_inta_isr(struct s2io_nic *sp)
3905 {
3906         free_irq(sp->pdev->irq, sp->dev);
3907 }
3908
3909 /* ********************************************************* *
3910  * Functions defined below concern the OS part of the driver *
3911  * ********************************************************* */
3912
3913 /**
3914  *  s2io_open - open entry point of the driver
3915  *  @dev : pointer to the device structure.
3916  *  Description:
3917  *  This function is the open entry point of the driver. It mainly calls a
3918  *  function to allocate Rx buffers and inserts them into the buffer
3919  *  descriptors and then enables the Rx part of the NIC.
3920  *  Return value:
3921  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3922  *   file on failure.
3923  */
3924
3925 static int s2io_open(struct net_device *dev)
3926 {
3927         struct s2io_nic *sp = netdev_priv(dev);
3928         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3929         int err = 0;
3930
3931         /*
3932          * Make sure you have link off by default every time
3933          * Nic is initialized
3934          */
3935         netif_carrier_off(dev);
3936         sp->last_link_state = 0;
3937
3938         /* Initialize H/W and enable interrupts */
3939         err = s2io_card_up(sp);
3940         if (err) {
3941                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3942                           dev->name);
3943                 goto hw_init_failed;
3944         }
3945
3946         if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3947                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3948                 s2io_card_down(sp);
3949                 err = -ENODEV;
3950                 goto hw_init_failed;
3951         }
3952         s2io_start_all_tx_queue(sp);
3953         return 0;
3954
3955 hw_init_failed:
3956         if (sp->config.intr_type == MSI_X) {
3957                 if (sp->entries) {
3958                         kfree(sp->entries);
3959                         swstats->mem_freed += sp->num_entries *
3960                                 sizeof(struct msix_entry);
3961                 }
3962                 if (sp->s2io_entries) {
3963                         kfree(sp->s2io_entries);
3964                         swstats->mem_freed += sp->num_entries *
3965                                 sizeof(struct s2io_msix_entry);
3966                 }
3967         }
3968         return err;
3969 }
3970
3971 /**
3972  *  s2io_close -close entry point of the driver
3973  *  @dev : device pointer.
3974  *  Description:
3975  *  This is the stop entry point of the driver. It needs to undo exactly
3976  *  whatever was done by the open entry point,thus it's usually referred to
3977  *  as the close function.Among other things this function mainly stops the
3978  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3979  *  Return value:
3980  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3981  *  file on failure.
3982  */
3983
3984 static int s2io_close(struct net_device *dev)
3985 {
3986         struct s2io_nic *sp = netdev_priv(dev);
3987         struct config_param *config = &sp->config;
3988         u64 tmp64;
3989         int offset;
3990
3991         /* Return if the device is already closed               *
3992          *  Can happen when s2io_card_up failed in change_mtu    *
3993          */
3994         if (!is_s2io_card_up(sp))
3995                 return 0;
3996
3997         s2io_stop_all_tx_queue(sp);
3998         /* delete all populated mac entries */
3999         for (offset = 1; offset < config->max_mc_addr; offset++) {
4000                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4001                 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4002                         do_s2io_delete_unicast_mc(sp, tmp64);
4003         }
4004
4005         s2io_card_down(sp);
4006
4007         return 0;
4008 }
4009
4010 /**
4011  *  s2io_xmit - Tx entry point of te driver
4012  *  @skb : the socket buffer containing the Tx data.
4013  *  @dev : device pointer.
4014  *  Description :
4015  *  This function is the Tx entry point of the driver. S2IO NIC supports
4016  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4017  *  NOTE: when device can't queue the pkt,just the trans_start variable will
4018  *  not be upadted.
4019  *  Return value:
4020  *  0 on success & 1 on failure.
4021  */
4022
4023 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4024 {
4025         struct s2io_nic *sp = netdev_priv(dev);
4026         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4027         register u64 val64;
4028         struct TxD *txdp;
4029         struct TxFIFO_element __iomem *tx_fifo;
4030         unsigned long flags = 0;
4031         u16 vlan_tag = 0;
4032         struct fifo_info *fifo = NULL;
4033         int do_spin_lock = 1;
4034         int offload_type;
4035         int enable_per_list_interrupt = 0;
4036         struct config_param *config = &sp->config;
4037         struct mac_info *mac_control = &sp->mac_control;
4038         struct stat_block *stats = mac_control->stats_info;
4039         struct swStat *swstats = &stats->sw_stat;
4040
4041         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4042
4043         if (unlikely(skb->len <= 0)) {
4044                 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4045                 dev_kfree_skb_any(skb);
4046                 return NETDEV_TX_OK;
4047         }
4048
4049         if (!is_s2io_card_up(sp)) {
4050                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4051                           dev->name);
4052                 dev_kfree_skb_any(skb);
4053                 return NETDEV_TX_OK;
4054         }
4055
4056         queue = 0;
4057         if (vlan_tx_tag_present(skb))
4058                 vlan_tag = vlan_tx_tag_get(skb);
4059         if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4060                 if (skb->protocol == htons(ETH_P_IP)) {
4061                         struct iphdr *ip;
4062                         struct tcphdr *th;
4063                         ip = ip_hdr(skb);
4064
4065                         if (!ip_is_fragment(ip)) {
4066                                 th = (struct tcphdr *)(((unsigned char *)ip) +
4067                                                        ip->ihl*4);
4068
4069                                 if (ip->protocol == IPPROTO_TCP) {
4070                                         queue_len = sp->total_tcp_fifos;
4071                                         queue = (ntohs(th->source) +
4072                                                  ntohs(th->dest)) &
4073                                                 sp->fifo_selector[queue_len - 1];
4074                                         if (queue >= queue_len)
4075                                                 queue = queue_len - 1;
4076                                 } else if (ip->protocol == IPPROTO_UDP) {
4077                                         queue_len = sp->total_udp_fifos;
4078                                         queue = (ntohs(th->source) +
4079                                                  ntohs(th->dest)) &
4080                                                 sp->fifo_selector[queue_len - 1];
4081                                         if (queue >= queue_len)
4082                                                 queue = queue_len - 1;
4083                                         queue += sp->udp_fifo_idx;
4084                                         if (skb->len > 1024)
4085                                                 enable_per_list_interrupt = 1;
4086                                         do_spin_lock = 0;
4087                                 }
4088                         }
4089                 }
4090         } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4091                 /* get fifo number based on skb->priority value */
4092                 queue = config->fifo_mapping
4093                         [skb->priority & (MAX_TX_FIFOS - 1)];
4094         fifo = &mac_control->fifos[queue];
4095
4096         if (do_spin_lock)
4097                 spin_lock_irqsave(&fifo->tx_lock, flags);
4098         else {
4099                 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4100                         return NETDEV_TX_LOCKED;
4101         }
4102
4103         if (sp->config.multiq) {
4104                 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4105                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4106                         return NETDEV_TX_BUSY;
4107                 }
4108         } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4109                 if (netif_queue_stopped(dev)) {
4110                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4111                         return NETDEV_TX_BUSY;
4112                 }
4113         }
4114
4115         put_off = (u16)fifo->tx_curr_put_info.offset;
4116         get_off = (u16)fifo->tx_curr_get_info.offset;
4117         txdp = fifo->list_info[put_off].list_virt_addr;
4118
4119         queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4120         /* Avoid "put" pointer going beyond "get" pointer */
4121         if (txdp->Host_Control ||
4122             ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4123                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4124                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4125                 dev_kfree_skb_any(skb);
4126                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4127                 return NETDEV_TX_OK;
4128         }
4129
4130         offload_type = s2io_offload_type(skb);
4131         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4132                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4133                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4134         }
4135         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4136                 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4137                                     TXD_TX_CKO_TCP_EN |
4138                                     TXD_TX_CKO_UDP_EN);
4139         }
4140         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4141         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4142         txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4143         if (enable_per_list_interrupt)
4144                 if (put_off & (queue_len >> 5))
4145                         txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4146         if (vlan_tag) {
4147                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4148                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4149         }
4150
4151         frg_len = skb_headlen(skb);
4152         if (offload_type == SKB_GSO_UDP) {
4153                 int ufo_size;
4154
4155                 ufo_size = s2io_udp_mss(skb);
4156                 ufo_size &= ~7;
4157                 txdp->Control_1 |= TXD_UFO_EN;
4158                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4159                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4160 #ifdef __BIG_ENDIAN
4161                 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4162                 fifo->ufo_in_band_v[put_off] =
4163                         (__force u64)skb_shinfo(skb)->ip6_frag_id;
4164 #else
4165                 fifo->ufo_in_band_v[put_off] =
4166                         (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4167 #endif
4168                 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4169                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4170                                                       fifo->ufo_in_band_v,
4171                                                       sizeof(u64),
4172                                                       PCI_DMA_TODEVICE);
4173                 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4174                         goto pci_map_failed;
4175                 txdp++;
4176         }
4177
4178         txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4179                                               frg_len, PCI_DMA_TODEVICE);
4180         if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4181                 goto pci_map_failed;
4182
4183         txdp->Host_Control = (unsigned long)skb;
4184         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4185         if (offload_type == SKB_GSO_UDP)
4186                 txdp->Control_1 |= TXD_UFO_EN;
4187
4188         frg_cnt = skb_shinfo(skb)->nr_frags;
4189         /* For fragmented SKB. */
4190         for (i = 0; i < frg_cnt; i++) {
4191                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4192                 /* A '0' length fragment will be ignored */
4193                 if (!skb_frag_size(frag))
4194                         continue;
4195                 txdp++;
4196                 txdp->Buffer_Pointer = (u64)skb_frag_dma_map(&sp->pdev->dev,
4197                                                              frag, 0,
4198                                                              skb_frag_size(frag),
4199                                                              DMA_TO_DEVICE);
4200                 txdp->Control_1 = TXD_BUFFER0_SIZE(skb_frag_size(frag));
4201                 if (offload_type == SKB_GSO_UDP)
4202                         txdp->Control_1 |= TXD_UFO_EN;
4203         }
4204         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4205
4206         if (offload_type == SKB_GSO_UDP)
4207                 frg_cnt++; /* as Txd0 was used for inband header */
4208
4209         tx_fifo = mac_control->tx_FIFO_start[queue];
4210         val64 = fifo->list_info[put_off].list_phy_addr;
4211         writeq(val64, &tx_fifo->TxDL_Pointer);
4212
4213         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4214                  TX_FIFO_LAST_LIST);
4215         if (offload_type)
4216                 val64 |= TX_FIFO_SPECIAL_FUNC;
4217
4218         writeq(val64, &tx_fifo->List_Control);
4219
4220         mmiowb();
4221
4222         put_off++;
4223         if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4224                 put_off = 0;
4225         fifo->tx_curr_put_info.offset = put_off;
4226
4227         /* Avoid "put" pointer going beyond "get" pointer */
4228         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4229                 swstats->fifo_full_cnt++;
4230                 DBG_PRINT(TX_DBG,
4231                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4232                           put_off, get_off);
4233                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4234         }
4235         swstats->mem_allocated += skb->truesize;
4236         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4237
4238         if (sp->config.intr_type == MSI_X)
4239                 tx_intr_handler(fifo);
4240
4241         return NETDEV_TX_OK;
4242
4243 pci_map_failed:
4244         swstats->pci_map_fail_cnt++;
4245         s2io_stop_tx_queue(sp, fifo->fifo_no);
4246         swstats->mem_freed += skb->truesize;
4247         dev_kfree_skb_any(skb);
4248         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4249         return NETDEV_TX_OK;
4250 }
4251
4252 static void
4253 s2io_alarm_handle(unsigned long data)
4254 {
4255         struct s2io_nic *sp = (struct s2io_nic *)data;
4256         struct net_device *dev = sp->dev;
4257
4258         s2io_handle_errors(dev);
4259         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4260 }
4261
4262 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4263 {
4264         struct ring_info *ring = (struct ring_info *)dev_id;
4265         struct s2io_nic *sp = ring->nic;
4266         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4267
4268         if (unlikely(!is_s2io_card_up(sp)))
4269                 return IRQ_HANDLED;
4270
4271         if (sp->config.napi) {
4272                 u8 __iomem *addr = NULL;
4273                 u8 val8 = 0;
4274
4275                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4276                 addr += (7 - ring->ring_no);
4277                 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4278                 writeb(val8, addr);
4279                 val8 = readb(addr);
4280                 napi_schedule(&ring->napi);
4281         } else {
4282                 rx_intr_handler(ring, 0);
4283                 s2io_chk_rx_buffers(sp, ring);
4284         }
4285
4286         return IRQ_HANDLED;
4287 }
4288
4289 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4290 {
4291         int i;
4292         struct fifo_info *fifos = (struct fifo_info *)dev_id;
4293         struct s2io_nic *sp = fifos->nic;
4294         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4295         struct config_param *config  = &sp->config;
4296         u64 reason;
4297
4298         if (unlikely(!is_s2io_card_up(sp)))
4299                 return IRQ_NONE;
4300
4301         reason = readq(&bar0->general_int_status);
4302         if (unlikely(reason == S2IO_MINUS_ONE))
4303                 /* Nothing much can be done. Get out */
4304                 return IRQ_HANDLED;
4305
4306         if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4307                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4308
4309                 if (reason & GEN_INTR_TXPIC)
4310                         s2io_txpic_intr_handle(sp);
4311
4312                 if (reason & GEN_INTR_TXTRAFFIC)
4313                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4314
4315                 for (i = 0; i < config->tx_fifo_num; i++)
4316                         tx_intr_handler(&fifos[i]);
4317
4318                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4319                 readl(&bar0->general_int_status);
4320                 return IRQ_HANDLED;
4321         }
4322         /* The interrupt was not raised by us */
4323         return IRQ_NONE;
4324 }
4325
4326 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4327 {
4328         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4329         u64 val64;
4330
4331         val64 = readq(&bar0->pic_int_status);
4332         if (val64 & PIC_INT_GPIO) {
4333                 val64 = readq(&bar0->gpio_int_reg);
4334                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4335                     (val64 & GPIO_INT_REG_LINK_UP)) {
4336                         /*
4337                          * This is unstable state so clear both up/down
4338                          * interrupt and adapter to re-evaluate the link state.
4339                          */
4340                         val64 |= GPIO_INT_REG_LINK_DOWN;
4341                         val64 |= GPIO_INT_REG_LINK_UP;
4342                         writeq(val64, &bar0->gpio_int_reg);
4343                         val64 = readq(&bar0->gpio_int_mask);
4344                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4345                                    GPIO_INT_MASK_LINK_DOWN);
4346                         writeq(val64, &bar0->gpio_int_mask);
4347                 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4348                         val64 = readq(&bar0->adapter_status);
4349                         /* Enable Adapter */
4350                         val64 = readq(&bar0->adapter_control);
4351                         val64 |= ADAPTER_CNTL_EN;
4352                         writeq(val64, &bar0->adapter_control);
4353                         val64 |= ADAPTER_LED_ON;
4354                         writeq(val64, &bar0->adapter_control);
4355                         if (!sp->device_enabled_once)
4356                                 sp->device_enabled_once = 1;
4357
4358                         s2io_link(sp, LINK_UP);
4359                         /*
4360                          * unmask link down interrupt and mask link-up
4361                          * intr
4362                          */
4363                         val64 = readq(&bar0->gpio_int_mask);
4364                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4365                         val64 |= GPIO_INT_MASK_LINK_UP;
4366                         writeq(val64, &bar0->gpio_int_mask);
4367
4368                 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4369                         val64 = readq(&bar0->adapter_status);
4370                         s2io_link(sp, LINK_DOWN);
4371                         /* Link is down so unmaks link up interrupt */
4372                         val64 = readq(&bar0->gpio_int_mask);
4373                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4374                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4375                         writeq(val64, &bar0->gpio_int_mask);
4376
4377                         /* turn off LED */
4378                         val64 = readq(&bar0->adapter_control);
4379                         val64 = val64 & (~ADAPTER_LED_ON);
4380                         writeq(val64, &bar0->adapter_control);
4381                 }
4382         }
4383         val64 = readq(&bar0->gpio_int_mask);
4384 }
4385
4386 /**
4387  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4388  *  @value: alarm bits
4389  *  @addr: address value
4390  *  @cnt: counter variable
4391  *  Description: Check for alarm and increment the counter
4392  *  Return Value:
4393  *  1 - if alarm bit set
4394  *  0 - if alarm bit is not set
4395  */
4396 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4397                                  unsigned long long *cnt)
4398 {
4399         u64 val64;
4400         val64 = readq(addr);
4401         if (val64 & value) {
4402                 writeq(val64, addr);
4403                 (*cnt)++;
4404                 return 1;
4405         }
4406         return 0;
4407
4408 }
4409
4410 /**
4411  *  s2io_handle_errors - Xframe error indication handler
4412  *  @nic: device private variable
4413  *  Description: Handle alarms such as loss of link, single or
4414  *  double ECC errors, critical and serious errors.
4415  *  Return Value:
4416  *  NONE
4417  */
4418 static void s2io_handle_errors(void *dev_id)
4419 {
4420         struct net_device *dev = (struct net_device *)dev_id;
4421         struct s2io_nic *sp = netdev_priv(dev);
4422         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4423         u64 temp64 = 0, val64 = 0;
4424         int i = 0;
4425
4426         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4427         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4428
4429         if (!is_s2io_card_up(sp))
4430                 return;
4431
4432         if (pci_channel_offline(sp->pdev))
4433                 return;
4434
4435         memset(&sw_stat->ring_full_cnt, 0,
4436                sizeof(sw_stat->ring_full_cnt));
4437
4438         /* Handling the XPAK counters update */
4439         if (stats->xpak_timer_count < 72000) {
4440                 /* waiting for an hour */
4441                 stats->xpak_timer_count++;
4442         } else {
4443                 s2io_updt_xpak_counter(dev);
4444                 /* reset the count to zero */
4445                 stats->xpak_timer_count = 0;
4446         }
4447
4448         /* Handling link status change error Intr */
4449         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4450                 val64 = readq(&bar0->mac_rmac_err_reg);
4451                 writeq(val64, &bar0->mac_rmac_err_reg);
4452                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4453                         schedule_work(&sp->set_link_task);
4454         }
4455
4456         /* In case of a serious error, the device will be Reset. */
4457         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4458                                   &sw_stat->serious_err_cnt))
4459                 goto reset;
4460
4461         /* Check for data parity error */
4462         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4463                                   &sw_stat->parity_err_cnt))
4464                 goto reset;
4465
4466         /* Check for ring full counter */
4467         if (sp->device_type == XFRAME_II_DEVICE) {
4468                 val64 = readq(&bar0->ring_bump_counter1);
4469                 for (i = 0; i < 4; i++) {
4470                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4471                         temp64 >>= 64 - ((i+1)*16);
4472                         sw_stat->ring_full_cnt[i] += temp64;
4473                 }
4474
4475                 val64 = readq(&bar0->ring_bump_counter2);
4476                 for (i = 0; i < 4; i++) {
4477                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4478                         temp64 >>= 64 - ((i+1)*16);
4479                         sw_stat->ring_full_cnt[i+4] += temp64;
4480                 }
4481         }
4482
4483         val64 = readq(&bar0->txdma_int_status);
4484         /*check for pfc_err*/
4485         if (val64 & TXDMA_PFC_INT) {
4486                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4487                                           PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4488                                           PFC_PCIX_ERR,
4489                                           &bar0->pfc_err_reg,
4490                                           &sw_stat->pfc_err_cnt))
4491                         goto reset;
4492                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4493                                       &bar0->pfc_err_reg,
4494                                       &sw_stat->pfc_err_cnt);
4495         }
4496
4497         /*check for tda_err*/
4498         if (val64 & TXDMA_TDA_INT) {
4499                 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4500                                           TDA_SM0_ERR_ALARM |
4501                                           TDA_SM1_ERR_ALARM,
4502                                           &bar0->tda_err_reg,
4503                                           &sw_stat->tda_err_cnt))
4504                         goto reset;
4505                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4506                                       &bar0->tda_err_reg,
4507                                       &sw_stat->tda_err_cnt);
4508         }
4509         /*check for pcc_err*/
4510         if (val64 & TXDMA_PCC_INT) {
4511                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4512                                           PCC_N_SERR | PCC_6_COF_OV_ERR |
4513                                           PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4514                                           PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4515                                           PCC_TXB_ECC_DB_ERR,
4516                                           &bar0->pcc_err_reg,
4517                                           &sw_stat->pcc_err_cnt))
4518                         goto reset;
4519                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4520                                       &bar0->pcc_err_reg,
4521                                       &sw_stat->pcc_err_cnt);
4522         }
4523
4524         /*check for tti_err*/
4525         if (val64 & TXDMA_TTI_INT) {
4526                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4527                                           &bar0->tti_err_reg,
4528                                           &sw_stat->tti_err_cnt))
4529                         goto reset;
4530                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4531                                       &bar0->tti_err_reg,
4532                                       &sw_stat->tti_err_cnt);
4533         }
4534
4535         /*check for lso_err*/
4536         if (val64 & TXDMA_LSO_INT) {
4537                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4538                                           LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4539                                           &bar0->lso_err_reg,
4540                                           &sw_stat->lso_err_cnt))
4541                         goto reset;
4542                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4543                                       &bar0->lso_err_reg,
4544                                       &sw_stat->lso_err_cnt);
4545         }
4546
4547         /*check for tpa_err*/
4548         if (val64 & TXDMA_TPA_INT) {
4549                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4550                                           &bar0->tpa_err_reg,
4551                                           &sw_stat->tpa_err_cnt))
4552                         goto reset;
4553                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4554                                       &bar0->tpa_err_reg,
4555                                       &sw_stat->tpa_err_cnt);
4556         }
4557
4558         /*check for sm_err*/
4559         if (val64 & TXDMA_SM_INT) {
4560                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4561                                           &bar0->sm_err_reg,
4562                                           &sw_stat->sm_err_cnt))
4563                         goto reset;
4564         }
4565
4566         val64 = readq(&bar0->mac_int_status);
4567         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4568                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4569                                           &bar0->mac_tmac_err_reg,
4570                                           &sw_stat->mac_tmac_err_cnt))
4571                         goto reset;
4572                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4573                                       TMAC_DESC_ECC_SG_ERR |
4574                                       TMAC_DESC_ECC_DB_ERR,
4575                                       &bar0->mac_tmac_err_reg,
4576                                       &sw_stat->mac_tmac_err_cnt);
4577         }
4578
4579         val64 = readq(&bar0->xgxs_int_status);
4580         if (val64 & XGXS_INT_STATUS_TXGXS) {
4581                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4582                                           &bar0->xgxs_txgxs_err_reg,
4583                                           &sw_stat->xgxs_txgxs_err_cnt))
4584                         goto reset;
4585                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4586                                       &bar0->xgxs_txgxs_err_reg,
4587                                       &sw_stat->xgxs_txgxs_err_cnt);
4588         }
4589
4590         val64 = readq(&bar0->rxdma_int_status);
4591         if (val64 & RXDMA_INT_RC_INT_M) {
4592                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4593                                           RC_FTC_ECC_DB_ERR |
4594                                           RC_PRCn_SM_ERR_ALARM |
4595                                           RC_FTC_SM_ERR_ALARM,
4596                                           &bar0->rc_err_reg,
4597                                           &sw_stat->rc_err_cnt))
4598                         goto reset;
4599                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4600                                       RC_FTC_ECC_SG_ERR |
4601                                       RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4602                                       &sw_stat->rc_err_cnt);
4603                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4604                                           PRC_PCI_AB_WR_Rn |
4605                                           PRC_PCI_AB_F_WR_Rn,
4606                                           &bar0->prc_pcix_err_reg,
4607                                           &sw_stat->prc_pcix_err_cnt))
4608                         goto reset;
4609                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4610                                       PRC_PCI_DP_WR_Rn |
4611                                       PRC_PCI_DP_F_WR_Rn,
4612                                       &bar0->prc_pcix_err_reg,
4613                                       &sw_stat->prc_pcix_err_cnt);
4614         }
4615
4616         if (val64 & RXDMA_INT_RPA_INT_M) {
4617                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4618                                           &bar0->rpa_err_reg,
4619                                           &sw_stat->rpa_err_cnt))
4620                         goto reset;
4621                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4622                                       &bar0->rpa_err_reg,
4623                                       &sw_stat->rpa_err_cnt);
4624         }
4625
4626         if (val64 & RXDMA_INT_RDA_INT_M) {
4627                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4628                                           RDA_FRM_ECC_DB_N_AERR |
4629                                           RDA_SM1_ERR_ALARM |
4630                                           RDA_SM0_ERR_ALARM |
4631                                           RDA_RXD_ECC_DB_SERR,
4632                                           &bar0->rda_err_reg,
4633                                           &sw_stat->rda_err_cnt))
4634                         goto reset;
4635                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4636                                       RDA_FRM_ECC_SG_ERR |
4637                                       RDA_MISC_ERR |
4638                                       RDA_PCIX_ERR,
4639                                       &bar0->rda_err_reg,
4640                                       &sw_stat->rda_err_cnt);
4641         }
4642
4643         if (val64 & RXDMA_INT_RTI_INT_M) {
4644                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4645                                           &bar0->rti_err_reg,
4646                                           &sw_stat->rti_err_cnt))
4647                         goto reset;
4648                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4649                                       &bar0->rti_err_reg,
4650                                       &sw_stat->rti_err_cnt);
4651         }
4652
4653         val64 = readq(&bar0->mac_int_status);
4654         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4655                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4656                                           &bar0->mac_rmac_err_reg,
4657                                           &sw_stat->mac_rmac_err_cnt))
4658                         goto reset;
4659                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4660                                       RMAC_SINGLE_ECC_ERR |
4661                                       RMAC_DOUBLE_ECC_ERR,
4662                                       &bar0->mac_rmac_err_reg,
4663                                       &sw_stat->mac_rmac_err_cnt);
4664         }
4665
4666         val64 = readq(&bar0->xgxs_int_status);
4667         if (val64 & XGXS_INT_STATUS_RXGXS) {
4668                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4669                                           &bar0->xgxs_rxgxs_err_reg,
4670                                           &sw_stat->xgxs_rxgxs_err_cnt))
4671                         goto reset;
4672         }
4673
4674         val64 = readq(&bar0->mc_int_status);
4675         if (val64 & MC_INT_STATUS_MC_INT) {
4676                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4677                                           &bar0->mc_err_reg,
4678                                           &sw_stat->mc_err_cnt))
4679                         goto reset;
4680
4681                 /* Handling Ecc errors */
4682                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4683                         writeq(val64, &bar0->mc_err_reg);
4684                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4685                                 sw_stat->double_ecc_errs++;
4686                                 if (sp->device_type != XFRAME_II_DEVICE) {
4687                                         /*
4688                                          * Reset XframeI only if critical error
4689                                          */
4690                                         if (val64 &
4691                                             (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4692                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4693                                                 goto reset;
4694                                 }
4695                         } else
4696                                 sw_stat->single_ecc_errs++;
4697                 }
4698         }
4699         return;
4700
4701 reset:
4702         s2io_stop_all_tx_queue(sp);
4703         schedule_work(&sp->rst_timer_task);
4704         sw_stat->soft_reset_cnt++;
4705 }
4706
4707 /**
4708  *  s2io_isr - ISR handler of the device .
4709  *  @irq: the irq of the device.
4710  *  @dev_id: a void pointer to the dev structure of the NIC.
4711  *  Description:  This function is the ISR handler of the device. It
4712  *  identifies the reason for the interrupt and calls the relevant
4713  *  service routines. As a contongency measure, this ISR allocates the
4714  *  recv buffers, if their numbers are below the panic value which is
4715  *  presently set to 25% of the original number of rcv buffers allocated.
4716  *  Return value:
4717  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4718  *   IRQ_NONE: will be returned if interrupt is not from our device
4719  */
4720 static irqreturn_t s2io_isr(int irq, void *dev_id)
4721 {
4722         struct net_device *dev = (struct net_device *)dev_id;
4723         struct s2io_nic *sp = netdev_priv(dev);
4724         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4725         int i;
4726         u64 reason = 0;
4727         struct mac_info *mac_control;
4728         struct config_param *config;
4729
4730         /* Pretend we handled any irq's from a disconnected card */
4731         if (pci_channel_offline(sp->pdev))
4732                 return IRQ_NONE;
4733
4734         if (!is_s2io_card_up(sp))
4735                 return IRQ_NONE;
4736
4737         config = &sp->config;
4738         mac_control = &sp->mac_control;
4739
4740         /*
4741          * Identify the cause for interrupt and call the appropriate
4742          * interrupt handler. Causes for the interrupt could be;
4743          * 1. Rx of packet.
4744          * 2. Tx complete.
4745          * 3. Link down.
4746          */
4747         reason = readq(&bar0->general_int_status);
4748
4749         if (unlikely(reason == S2IO_MINUS_ONE))
4750                 return IRQ_HANDLED;     /* Nothing much can be done. Get out */
4751
4752         if (reason &
4753             (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4754                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4755
4756                 if (config->napi) {
4757                         if (reason & GEN_INTR_RXTRAFFIC) {
4758                                 napi_schedule(&sp->napi);
4759                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4760                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4761                                 readl(&bar0->rx_traffic_int);
4762                         }
4763                 } else {
4764                         /*
4765                          * rx_traffic_int reg is an R1 register, writing all 1's
4766                          * will ensure that the actual interrupt causing bit
4767                          * get's cleared and hence a read can be avoided.
4768                          */
4769                         if (reason & GEN_INTR_RXTRAFFIC)
4770                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4771
4772                         for (i = 0; i < config->rx_ring_num; i++) {
4773                                 struct ring_info *ring = &mac_control->rings[i];
4774
4775                                 rx_intr_handler(ring, 0);
4776                         }
4777                 }
4778
4779                 /*
4780                  * tx_traffic_int reg is an R1 register, writing all 1's
4781                  * will ensure that the actual interrupt causing bit get's
4782                  * cleared and hence a read can be avoided.
4783                  */
4784                 if (reason & GEN_INTR_TXTRAFFIC)
4785                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4786
4787                 for (i = 0; i < config->tx_fifo_num; i++)
4788                         tx_intr_handler(&mac_control->fifos[i]);
4789
4790                 if (reason & GEN_INTR_TXPIC)
4791                         s2io_txpic_intr_handle(sp);
4792
4793                 /*
4794                  * Reallocate the buffers from the interrupt handler itself.
4795                  */
4796                 if (!config->napi) {
4797                         for (i = 0; i < config->rx_ring_num; i++) {
4798                                 struct ring_info *ring = &mac_control->rings[i];
4799
4800                                 s2io_chk_rx_buffers(sp, ring);
4801                         }
4802                 }
4803                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4804                 readl(&bar0->general_int_status);
4805
4806                 return IRQ_HANDLED;
4807
4808         } else if (!reason) {
4809                 /* The interrupt was not raised by us */
4810                 return IRQ_NONE;
4811         }
4812
4813         return IRQ_HANDLED;
4814 }
4815
4816 /**
4817  * s2io_updt_stats -
4818  */
4819 static void s2io_updt_stats(struct s2io_nic *sp)
4820 {
4821         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4822         u64 val64;
4823         int cnt = 0;
4824
4825         if (is_s2io_card_up(sp)) {
4826                 /* Apprx 30us on a 133 MHz bus */
4827                 val64 = SET_UPDT_CLICKS(10) |
4828                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4829                 writeq(val64, &bar0->stat_cfg);
4830                 do {
4831                         udelay(100);
4832                         val64 = readq(&bar0->stat_cfg);
4833                         if (!(val64 & s2BIT(0)))
4834                                 break;
4835                         cnt++;
4836                         if (cnt == 5)
4837                                 break; /* Updt failed */
4838                 } while (1);
4839         }
4840 }
4841
4842 /**
4843  *  s2io_get_stats - Updates the device statistics structure.
4844  *  @dev : pointer to the device structure.
4845  *  Description:
4846  *  This function updates the device statistics structure in the s2io_nic
4847  *  structure and returns a pointer to the same.
4848  *  Return value:
4849  *  pointer to the updated net_device_stats structure.
4850  */
4851 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4852 {
4853         struct s2io_nic *sp = netdev_priv(dev);
4854         struct mac_info *mac_control = &sp->mac_control;
4855         struct stat_block *stats = mac_control->stats_info;
4856         u64 delta;
4857
4858         /* Configure Stats for immediate updt */
4859         s2io_updt_stats(sp);
4860
4861         /* A device reset will cause the on-adapter statistics to be zero'ed.
4862          * This can be done while running by changing the MTU.  To prevent the
4863          * system from having the stats zero'ed, the driver keeps a copy of the
4864          * last update to the system (which is also zero'ed on reset).  This
4865          * enables the driver to accurately know the delta between the last
4866          * update and the current update.
4867          */
4868         delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4869                 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4870         sp->stats.rx_packets += delta;
4871         dev->stats.rx_packets += delta;
4872
4873         delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4874                 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4875         sp->stats.tx_packets += delta;
4876         dev->stats.tx_packets += delta;
4877
4878         delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4879                 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4880         sp->stats.rx_bytes += delta;
4881         dev->stats.rx_bytes += delta;
4882
4883         delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4884                 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4885         sp->stats.tx_bytes += delta;
4886         dev->stats.tx_bytes += delta;
4887
4888         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4889         sp->stats.rx_errors += delta;
4890         dev->stats.rx_errors += delta;
4891
4892         delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4893                 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4894         sp->stats.tx_errors += delta;
4895         dev->stats.tx_errors += delta;
4896
4897         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4898         sp->stats.rx_dropped += delta;
4899         dev->stats.rx_dropped += delta;
4900
4901         delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4902         sp->stats.tx_dropped += delta;
4903         dev->stats.tx_dropped += delta;
4904
4905         /* The adapter MAC interprets pause frames as multicast packets, but
4906          * does not pass them up.  This erroneously increases the multicast
4907          * packet count and needs to be deducted when the multicast frame count
4908          * is queried.
4909          */
4910         delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4911                 le32_to_cpu(stats->rmac_vld_mcst_frms);
4912         delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4913         delta -= sp->stats.multicast;
4914         sp->stats.multicast += delta;
4915         dev->stats.multicast += delta;
4916
4917         delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4918                 le32_to_cpu(stats->rmac_usized_frms)) +
4919                 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4920         sp->stats.rx_length_errors += delta;
4921         dev->stats.rx_length_errors += delta;
4922
4923         delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4924         sp->stats.rx_crc_errors += delta;
4925         dev->stats.rx_crc_errors += delta;
4926
4927         return &dev->stats;
4928 }
4929
4930 /**
4931  *  s2io_set_multicast - entry point for multicast address enable/disable.
4932  *  @dev : pointer to the device structure
4933  *  Description:
4934  *  This function is a driver entry point which gets called by the kernel
4935  *  whenever multicast addresses must be enabled/disabled. This also gets
4936  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4937  *  determine, if multicast address must be enabled or if promiscuous mode
4938  *  is to be disabled etc.
4939  *  Return value:
4940  *  void.
4941  */
4942
4943 static void s2io_set_multicast(struct net_device *dev)
4944 {
4945         int i, j, prev_cnt;
4946         struct netdev_hw_addr *ha;
4947         struct s2io_nic *sp = netdev_priv(dev);
4948         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4949         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4950                 0xfeffffffffffULL;
4951         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4952         void __iomem *add;
4953         struct config_param *config = &sp->config;
4954
4955         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4956                 /*  Enable all Multicast addresses */
4957                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4958                        &bar0->rmac_addr_data0_mem);
4959                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4960                        &bar0->rmac_addr_data1_mem);
4961                 val64 = RMAC_ADDR_CMD_MEM_WE |
4962                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4963                         RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4964                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4965                 /* Wait till command completes */
4966                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4967                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4968                                       S2IO_BIT_RESET);
4969
4970                 sp->m_cast_flg = 1;
4971                 sp->all_multi_pos = config->max_mc_addr - 1;
4972         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4973                 /*  Disable all Multicast addresses */
4974                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4975                        &bar0->rmac_addr_data0_mem);
4976                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4977                        &bar0->rmac_addr_data1_mem);
4978                 val64 = RMAC_ADDR_CMD_MEM_WE |
4979                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4980                         RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4981                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4982                 /* Wait till command completes */
4983                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4984                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4985                                       S2IO_BIT_RESET);
4986
4987                 sp->m_cast_flg = 0;
4988                 sp->all_multi_pos = 0;
4989         }
4990
4991         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4992                 /*  Put the NIC into promiscuous mode */
4993                 add = &bar0->mac_cfg;
4994                 val64 = readq(&bar0->mac_cfg);
4995                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4996
4997                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4998                 writel((u32)val64, add);
4999                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5000                 writel((u32) (val64 >> 32), (add + 4));
5001
5002                 if (vlan_tag_strip != 1) {
5003                         val64 = readq(&bar0->rx_pa_cfg);
5004                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5005                         writeq(val64, &bar0->rx_pa_cfg);
5006                         sp->vlan_strip_flag = 0;
5007                 }
5008
5009                 val64 = readq(&bar0->mac_cfg);
5010                 sp->promisc_flg = 1;
5011                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5012                           dev->name);
5013         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5014                 /*  Remove the NIC from promiscuous mode */
5015                 add = &bar0->mac_cfg;
5016                 val64 = readq(&bar0->mac_cfg);
5017                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5018
5019                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5020                 writel((u32)val64, add);
5021                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5022                 writel((u32) (val64 >> 32), (add + 4));
5023
5024                 if (vlan_tag_strip != 0) {
5025                         val64 = readq(&bar0->rx_pa_cfg);
5026                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5027                         writeq(val64, &bar0->rx_pa_cfg);
5028                         sp->vlan_strip_flag = 1;
5029                 }
5030
5031                 val64 = readq(&bar0->mac_cfg);
5032                 sp->promisc_flg = 0;
5033                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5034         }
5035
5036         /*  Update individual M_CAST address list */
5037         if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5038                 if (netdev_mc_count(dev) >
5039                     (config->max_mc_addr - config->max_mac_addr)) {
5040                         DBG_PRINT(ERR_DBG,
5041                                   "%s: No more Rx filters can be added - "
5042                                   "please enable ALL_MULTI instead\n",
5043                                   dev->name);
5044                         return;
5045                 }
5046
5047                 prev_cnt = sp->mc_addr_count;
5048                 sp->mc_addr_count = netdev_mc_count(dev);
5049
5050                 /* Clear out the previous list of Mc in the H/W. */
5051                 for (i = 0; i < prev_cnt; i++) {
5052                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5053                                &bar0->rmac_addr_data0_mem);
5054                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5055                                &bar0->rmac_addr_data1_mem);
5056                         val64 = RMAC_ADDR_CMD_MEM_WE |
5057                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5058                                 RMAC_ADDR_CMD_MEM_OFFSET
5059                                 (config->mc_start_offset + i);
5060                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5061
5062                         /* Wait for command completes */
5063                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5064                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5065                                                   S2IO_BIT_RESET)) {
5066                                 DBG_PRINT(ERR_DBG,
5067                                           "%s: Adding Multicasts failed\n",
5068                                           dev->name);
5069                                 return;
5070                         }
5071                 }
5072
5073                 /* Create the new Rx filter list and update the same in H/W. */
5074                 i = 0;
5075                 netdev_for_each_mc_addr(ha, dev) {
5076                         mac_addr = 0;
5077                         for (j = 0; j < ETH_ALEN; j++) {
5078                                 mac_addr |= ha->addr[j];
5079                                 mac_addr <<= 8;
5080                         }
5081                         mac_addr >>= 8;
5082                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5083                                &bar0->rmac_addr_data0_mem);
5084                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5085                                &bar0->rmac_addr_data1_mem);
5086                         val64 = RMAC_ADDR_CMD_MEM_WE |
5087                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5088                                 RMAC_ADDR_CMD_MEM_OFFSET
5089                                 (i + config->mc_start_offset);
5090                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5091
5092                         /* Wait for command completes */
5093                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5094                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5095                                                   S2IO_BIT_RESET)) {
5096                                 DBG_PRINT(ERR_DBG,
5097                                           "%s: Adding Multicasts failed\n",
5098                                           dev->name);
5099                                 return;
5100                         }
5101                         i++;
5102                 }
5103         }
5104 }
5105
5106 /* read from CAM unicast & multicast addresses and store it in
5107  * def_mac_addr structure
5108  */
5109 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5110 {
5111         int offset;
5112         u64 mac_addr = 0x0;
5113         struct config_param *config = &sp->config;
5114
5115         /* store unicast & multicast mac addresses */
5116         for (offset = 0; offset < config->max_mc_addr; offset++) {
5117                 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5118                 /* if read fails disable the entry */
5119                 if (mac_addr == FAILURE)
5120                         mac_addr = S2IO_DISABLE_MAC_ENTRY;
5121                 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5122         }
5123 }
5124
5125 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5126 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5127 {
5128         int offset;
5129         struct config_param *config = &sp->config;
5130         /* restore unicast mac address */
5131         for (offset = 0; offset < config->max_mac_addr; offset++)
5132                 do_s2io_prog_unicast(sp->dev,
5133                                      sp->def_mac_addr[offset].mac_addr);
5134
5135         /* restore multicast mac address */
5136         for (offset = config->mc_start_offset;
5137              offset < config->max_mc_addr; offset++)
5138                 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5139 }
5140
5141 /* add a multicast MAC address to CAM */
5142 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5143 {
5144         int i;
5145         u64 mac_addr = 0;
5146         struct config_param *config = &sp->config;
5147
5148         for (i = 0; i < ETH_ALEN; i++) {
5149                 mac_addr <<= 8;
5150                 mac_addr |= addr[i];
5151         }
5152         if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5153                 return SUCCESS;
5154
5155         /* check if the multicast mac already preset in CAM */
5156         for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5157                 u64 tmp64;
5158                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5159                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5160                         break;
5161
5162                 if (tmp64 == mac_addr)
5163                         return SUCCESS;
5164         }
5165         if (i == config->max_mc_addr) {
5166                 DBG_PRINT(ERR_DBG,
5167                           "CAM full no space left for multicast MAC\n");
5168                 return FAILURE;
5169         }
5170         /* Update the internal structure with this new mac address */
5171         do_s2io_copy_mac_addr(sp, i, mac_addr);
5172
5173         return do_s2io_add_mac(sp, mac_addr, i);
5174 }
5175
5176 /* add MAC address to CAM */
5177 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5178 {
5179         u64 val64;
5180         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5181
5182         writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5183                &bar0->rmac_addr_data0_mem);
5184
5185         val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5186                 RMAC_ADDR_CMD_MEM_OFFSET(off);
5187         writeq(val64, &bar0->rmac_addr_cmd_mem);
5188
5189         /* Wait till command completes */
5190         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5191                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5192                                   S2IO_BIT_RESET)) {
5193                 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5194                 return FAILURE;
5195         }
5196         return SUCCESS;
5197 }
5198 /* deletes a specified unicast/multicast mac entry from CAM */
5199 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5200 {
5201         int offset;
5202         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5203         struct config_param *config = &sp->config;
5204
5205         for (offset = 1;
5206              offset < config->max_mc_addr; offset++) {
5207                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5208                 if (tmp64 == addr) {
5209                         /* disable the entry by writing  0xffffffffffffULL */
5210                         if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5211                                 return FAILURE;
5212                         /* store the new mac list from CAM */
5213                         do_s2io_store_unicast_mc(sp);
5214                         return SUCCESS;
5215                 }
5216         }
5217         DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5218                   (unsigned long long)addr);
5219         return FAILURE;
5220 }
5221
5222 /* read mac entries from CAM */
5223 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5224 {
5225         u64 tmp64 = 0xffffffffffff0000ULL, val64;
5226         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5227
5228         /* read mac addr */
5229         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5230                 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5231         writeq(val64, &bar0->rmac_addr_cmd_mem);
5232
5233         /* Wait till command completes */
5234         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5235                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5236                                   S2IO_BIT_RESET)) {
5237                 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5238                 return FAILURE;
5239         }
5240         tmp64 = readq(&bar0->rmac_addr_data0_mem);
5241
5242         return tmp64 >> 16;
5243 }
5244
5245 /**
5246  * s2io_set_mac_addr - driver entry point
5247  */
5248
5249 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5250 {
5251         struct sockaddr *addr = p;
5252
5253         if (!is_valid_ether_addr(addr->sa_data))
5254                 return -EADDRNOTAVAIL;
5255
5256         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5257
5258         /* store the MAC address in CAM */
5259         return do_s2io_prog_unicast(dev, dev->dev_addr);
5260 }
5261 /**
5262  *  do_s2io_prog_unicast - Programs the Xframe mac address
5263  *  @dev : pointer to the device structure.
5264  *  @addr: a uchar pointer to the new mac address which is to be set.
5265  *  Description : This procedure will program the Xframe to receive
5266  *  frames with new Mac Address
5267  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5268  *  as defined in errno.h file on failure.
5269  */
5270
5271 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5272 {
5273         struct s2io_nic *sp = netdev_priv(dev);
5274         register u64 mac_addr = 0, perm_addr = 0;
5275         int i;
5276         u64 tmp64;
5277         struct config_param *config = &sp->config;
5278
5279         /*
5280          * Set the new MAC address as the new unicast filter and reflect this
5281          * change on the device address registered with the OS. It will be
5282          * at offset 0.
5283          */
5284         for (i = 0; i < ETH_ALEN; i++) {
5285                 mac_addr <<= 8;
5286                 mac_addr |= addr[i];
5287                 perm_addr <<= 8;
5288                 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5289         }
5290
5291         /* check if the dev_addr is different than perm_addr */
5292         if (mac_addr == perm_addr)
5293                 return SUCCESS;
5294
5295         /* check if the mac already preset in CAM */
5296         for (i = 1; i < config->max_mac_addr; i++) {
5297                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5298                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5299                         break;
5300
5301                 if (tmp64 == mac_addr) {
5302                         DBG_PRINT(INFO_DBG,
5303                                   "MAC addr:0x%llx already present in CAM\n",
5304                                   (unsigned long long)mac_addr);
5305                         return SUCCESS;
5306                 }
5307         }
5308         if (i == config->max_mac_addr) {
5309                 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5310                 return FAILURE;
5311         }
5312         /* Update the internal structure with this new mac address */
5313         do_s2io_copy_mac_addr(sp, i, mac_addr);
5314
5315         return do_s2io_add_mac(sp, mac_addr, i);
5316 }
5317
5318 /**
5319  * s2io_ethtool_sset - Sets different link parameters.
5320  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
5321  * @info: pointer to the structure with parameters given by ethtool to set
5322  * link information.
5323  * Description:
5324  * The function sets different link parameters provided by the user onto
5325  * the NIC.
5326  * Return value:
5327  * 0 on success.
5328  */
5329
5330 static int s2io_ethtool_sset(struct net_device *dev,
5331                              struct ethtool_cmd *info)
5332 {
5333         struct s2io_nic *sp = netdev_priv(dev);
5334         if ((info->autoneg == AUTONEG_ENABLE) ||
5335             (ethtool_cmd_speed(info) != SPEED_10000) ||
5336             (info->duplex != DUPLEX_FULL))
5337                 return -EINVAL;
5338         else {
5339                 s2io_close(sp->dev);
5340                 s2io_open(sp->dev);
5341         }
5342
5343         return 0;
5344 }
5345
5346 /**
5347  * s2io_ethtol_gset - Return link specific information.
5348  * @sp : private member of the device structure, pointer to the
5349  *      s2io_nic structure.
5350  * @info : pointer to the structure with parameters given by ethtool
5351  * to return link information.
5352  * Description:
5353  * Returns link specific information like speed, duplex etc.. to ethtool.
5354  * Return value :
5355  * return 0 on success.
5356  */
5357
5358 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5359 {
5360         struct s2io_nic *sp = netdev_priv(dev);
5361         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5362         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5363         info->port = PORT_FIBRE;
5364
5365         /* info->transceiver */
5366         info->transceiver = XCVR_EXTERNAL;
5367
5368         if (netif_carrier_ok(sp->dev)) {
5369                 ethtool_cmd_speed_set(info, SPEED_10000);
5370                 info->duplex = DUPLEX_FULL;
5371         } else {
5372                 ethtool_cmd_speed_set(info, -1);
5373                 info->duplex = -1;
5374         }
5375
5376         info->autoneg = AUTONEG_DISABLE;
5377         return 0;
5378 }
5379
5380 /**
5381  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5382  * @sp : private member of the device structure, which is a pointer to the
5383  * s2io_nic structure.
5384  * @info : pointer to the structure with parameters given by ethtool to
5385  * return driver information.
5386  * Description:
5387  * Returns driver specefic information like name, version etc.. to ethtool.
5388  * Return value:
5389  *  void
5390  */
5391
5392 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5393                                   struct ethtool_drvinfo *info)
5394 {
5395         struct s2io_nic *sp = netdev_priv(dev);
5396
5397         strlcpy(info->driver, s2io_driver_name, sizeof(info->driver));
5398         strlcpy(info->version, s2io_driver_version, sizeof(info->version));
5399         strlcpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5400         info->regdump_len = XENA_REG_SPACE;
5401         info->eedump_len = XENA_EEPROM_SPACE;
5402 }
5403
5404 /**
5405  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5406  *  @sp: private member of the device structure, which is a pointer to the
5407  *  s2io_nic structure.
5408  *  @regs : pointer to the structure with parameters given by ethtool for
5409  *  dumping the registers.
5410  *  @reg_space: The input argumnet into which all the registers are dumped.
5411  *  Description:
5412  *  Dumps the entire register space of xFrame NIC into the user given
5413  *  buffer area.
5414  * Return value :
5415  * void .
5416  */
5417
5418 static void s2io_ethtool_gregs(struct net_device *dev,
5419                                struct ethtool_regs *regs, void *space)
5420 {
5421         int i;
5422         u64 reg;
5423         u8 *reg_space = (u8 *)space;
5424         struct s2io_nic *sp = netdev_priv(dev);
5425
5426         regs->len = XENA_REG_SPACE;
5427         regs->version = sp->pdev->subsystem_device;
5428
5429         for (i = 0; i < regs->len; i += 8) {
5430                 reg = readq(sp->bar0 + i);
5431                 memcpy((reg_space + i), &reg, 8);
5432         }
5433 }
5434
5435 /*
5436  *  s2io_set_led - control NIC led
5437  */
5438 static void s2io_set_led(struct s2io_nic *sp, bool on)
5439 {
5440         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5441         u16 subid = sp->pdev->subsystem_device;
5442         u64 val64;
5443
5444         if ((sp->device_type == XFRAME_II_DEVICE) ||
5445             ((subid & 0xFF) >= 0x07)) {
5446                 val64 = readq(&bar0->gpio_control);
5447                 if (on)
5448                         val64 |= GPIO_CTRL_GPIO_0;
5449                 else
5450                         val64 &= ~GPIO_CTRL_GPIO_0;
5451
5452                 writeq(val64, &bar0->gpio_control);
5453         } else {
5454                 val64 = readq(&bar0->adapter_control);
5455                 if (on)
5456                         val64 |= ADAPTER_LED_ON;
5457                 else
5458                         val64 &= ~ADAPTER_LED_ON;
5459
5460                 writeq(val64, &bar0->adapter_control);
5461         }
5462
5463 }
5464
5465 /**
5466  * s2io_ethtool_set_led - To physically identify the nic on the system.
5467  * @dev : network device
5468  * @state: led setting
5469  *
5470  * Description: Used to physically identify the NIC on the system.
5471  * The Link LED will blink for a time specified by the user for
5472  * identification.
5473  * NOTE: The Link has to be Up to be able to blink the LED. Hence
5474  * identification is possible only if it's link is up.
5475  */
5476
5477 static int s2io_ethtool_set_led(struct net_device *dev,
5478                                 enum ethtool_phys_id_state state)
5479 {
5480         struct s2io_nic *sp = netdev_priv(dev);
5481         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5482         u16 subid = sp->pdev->subsystem_device;
5483
5484         if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5485                 u64 val64 = readq(&bar0->adapter_control);
5486                 if (!(val64 & ADAPTER_CNTL_EN)) {
5487                         pr_err("Adapter Link down, cannot blink LED\n");
5488                         return -EAGAIN;
5489                 }
5490         }
5491
5492         switch (state) {
5493         case ETHTOOL_ID_ACTIVE:
5494                 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5495                 return 1;       /* cycle on/off once per second */
5496
5497         case ETHTOOL_ID_ON:
5498                 s2io_set_led(sp, true);
5499                 break;
5500
5501         case ETHTOOL_ID_OFF:
5502                 s2io_set_led(sp, false);
5503                 break;
5504
5505         case ETHTOOL_ID_INACTIVE:
5506                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5507                         writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5508         }
5509
5510         return 0;
5511 }
5512
5513 static void s2io_ethtool_gringparam(struct net_device *dev,
5514                                     struct ethtool_ringparam *ering)
5515 {
5516         struct s2io_nic *sp = netdev_priv(dev);
5517         int i, tx_desc_count = 0, rx_desc_count = 0;
5518
5519         if (sp->rxd_mode == RXD_MODE_1) {
5520                 ering->rx_max_pending = MAX_RX_DESC_1;
5521                 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5522         } else {
5523                 ering->rx_max_pending = MAX_RX_DESC_2;
5524                 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5525         }
5526
5527         ering->tx_max_pending = MAX_TX_DESC;
5528
5529         for (i = 0; i < sp->config.rx_ring_num; i++)
5530                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5531         ering->rx_pending = rx_desc_count;
5532         ering->rx_jumbo_pending = rx_desc_count;
5533
5534         for (i = 0; i < sp->config.tx_fifo_num; i++)
5535                 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5536         ering->tx_pending = tx_desc_count;
5537         DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5538 }
5539
5540 /**
5541  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5542  * @sp : private member of the device structure, which is a pointer to the
5543  *      s2io_nic structure.
5544  * @ep : pointer to the structure with pause parameters given by ethtool.
5545  * Description:
5546  * Returns the Pause frame generation and reception capability of the NIC.
5547  * Return value:
5548  *  void
5549  */
5550 static void s2io_ethtool_getpause_data(struct net_device *dev,
5551                                        struct ethtool_pauseparam *ep)
5552 {
5553         u64 val64;
5554         struct s2io_nic *sp = netdev_priv(dev);
5555         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5556
5557         val64 = readq(&bar0->rmac_pause_cfg);
5558         if (val64 & RMAC_PAUSE_GEN_ENABLE)
5559                 ep->tx_pause = true;
5560         if (val64 & RMAC_PAUSE_RX_ENABLE)
5561                 ep->rx_pause = true;
5562         ep->autoneg = false;
5563 }
5564
5565 /**
5566  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
5567  * @sp : private member of the device structure, which is a pointer to the
5568  *      s2io_nic structure.
5569  * @ep : pointer to the structure with pause parameters given by ethtool.
5570  * Description:
5571  * It can be used to set or reset Pause frame generation or reception
5572  * support of the NIC.
5573  * Return value:
5574  * int, returns 0 on Success
5575  */
5576
5577 static int s2io_ethtool_setpause_data(struct net_device *dev,
5578                                       struct ethtool_pauseparam *ep)
5579 {
5580         u64 val64;
5581         struct s2io_nic *sp = netdev_priv(dev);
5582         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5583
5584         val64 = readq(&bar0->rmac_pause_cfg);
5585         if (ep->tx_pause)
5586                 val64 |= RMAC_PAUSE_GEN_ENABLE;
5587         else
5588                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5589         if (ep->rx_pause)
5590                 val64 |= RMAC_PAUSE_RX_ENABLE;
5591         else
5592                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5593         writeq(val64, &bar0->rmac_pause_cfg);
5594         return 0;
5595 }
5596
5597 /**
5598  * read_eeprom - reads 4 bytes of data from user given offset.
5599  * @sp : private member of the device structure, which is a pointer to the
5600  *      s2io_nic structure.
5601  * @off : offset at which the data must be written
5602  * @data : Its an output parameter where the data read at the given
5603  *      offset is stored.
5604  * Description:
5605  * Will read 4 bytes of data from the user given offset and return the
5606  * read data.
5607  * NOTE: Will allow to read only part of the EEPROM visible through the
5608  *   I2C bus.
5609  * Return value:
5610  *  -1 on failure and 0 on success.
5611  */
5612
5613 #define S2IO_DEV_ID             5
5614 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5615 {
5616         int ret = -1;
5617         u32 exit_cnt = 0;
5618         u64 val64;
5619         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5620
5621         if (sp->device_type == XFRAME_I_DEVICE) {
5622                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5623                         I2C_CONTROL_ADDR(off) |
5624                         I2C_CONTROL_BYTE_CNT(0x3) |
5625                         I2C_CONTROL_READ |
5626                         I2C_CONTROL_CNTL_START;
5627                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5628
5629                 while (exit_cnt < 5) {
5630                         val64 = readq(&bar0->i2c_control);
5631                         if (I2C_CONTROL_CNTL_END(val64)) {
5632                                 *data = I2C_CONTROL_GET_DATA(val64);
5633                                 ret = 0;
5634                                 break;
5635                         }
5636                         msleep(50);
5637                         exit_cnt++;
5638                 }
5639         }
5640
5641         if (sp->device_type == XFRAME_II_DEVICE) {
5642                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5643                         SPI_CONTROL_BYTECNT(0x3) |
5644                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5645                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5646                 val64 |= SPI_CONTROL_REQ;
5647                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5648                 while (exit_cnt < 5) {
5649                         val64 = readq(&bar0->spi_control);
5650                         if (val64 & SPI_CONTROL_NACK) {
5651                                 ret = 1;
5652                                 break;
5653                         } else if (val64 & SPI_CONTROL_DONE) {
5654                                 *data = readq(&bar0->spi_data);
5655                                 *data &= 0xffffff;
5656                                 ret = 0;
5657                                 break;
5658                         }
5659                         msleep(50);
5660                         exit_cnt++;
5661                 }
5662         }
5663         return ret;
5664 }
5665
5666 /**
5667  *  write_eeprom - actually writes the relevant part of the data value.
5668  *  @sp : private member of the device structure, which is a pointer to the
5669  *       s2io_nic structure.
5670  *  @off : offset at which the data must be written
5671  *  @data : The data that is to be written
5672  *  @cnt : Number of bytes of the data that are actually to be written into
5673  *  the Eeprom. (max of 3)
5674  * Description:
5675  *  Actually writes the relevant part of the data value into the Eeprom
5676  *  through the I2C bus.
5677  * Return value:
5678  *  0 on success, -1 on failure.
5679  */
5680
5681 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5682 {
5683         int exit_cnt = 0, ret = -1;
5684         u64 val64;
5685         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5686
5687         if (sp->device_type == XFRAME_I_DEVICE) {
5688                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5689                         I2C_CONTROL_ADDR(off) |
5690                         I2C_CONTROL_BYTE_CNT(cnt) |
5691                         I2C_CONTROL_SET_DATA((u32)data) |
5692                         I2C_CONTROL_CNTL_START;
5693                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5694
5695                 while (exit_cnt < 5) {
5696                         val64 = readq(&bar0->i2c_control);
5697                         if (I2C_CONTROL_CNTL_END(val64)) {
5698                                 if (!(val64 & I2C_CONTROL_NACK))
5699                                         ret = 0;
5700                                 break;
5701                         }
5702                         msleep(50);
5703                         exit_cnt++;
5704                 }
5705         }
5706
5707         if (sp->device_type == XFRAME_II_DEVICE) {
5708                 int write_cnt = (cnt == 8) ? 0 : cnt;
5709                 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5710
5711                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5712                         SPI_CONTROL_BYTECNT(write_cnt) |
5713                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5714                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5715                 val64 |= SPI_CONTROL_REQ;
5716                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5717                 while (exit_cnt < 5) {
5718                         val64 = readq(&bar0->spi_control);
5719                         if (val64 & SPI_CONTROL_NACK) {
5720                                 ret = 1;
5721                                 break;
5722                         } else if (val64 & SPI_CONTROL_DONE) {
5723                                 ret = 0;
5724                                 break;
5725                         }
5726                         msleep(50);
5727                         exit_cnt++;
5728                 }
5729         }
5730         return ret;
5731 }
5732 static void s2io_vpd_read(struct s2io_nic *nic)
5733 {
5734         u8 *vpd_data;
5735         u8 data;
5736         int i = 0, cnt, len, fail = 0;
5737         int vpd_addr = 0x80;
5738         struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5739
5740         if (nic->device_type == XFRAME_II_DEVICE) {
5741                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5742                 vpd_addr = 0x80;
5743         } else {
5744                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5745                 vpd_addr = 0x50;
5746         }
5747         strcpy(nic->serial_num, "NOT AVAILABLE");
5748
5749         vpd_data = kmalloc(256, GFP_KERNEL);
5750         if (!vpd_data) {
5751                 swstats->mem_alloc_fail_cnt++;
5752                 return;
5753         }
5754         swstats->mem_allocated += 256;
5755
5756         for (i = 0; i < 256; i += 4) {
5757                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5758                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5759                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5760                 for (cnt = 0; cnt < 5; cnt++) {
5761                         msleep(2);
5762                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5763                         if (data == 0x80)
5764                                 break;
5765                 }
5766                 if (cnt >= 5) {
5767                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5768                         fail = 1;
5769                         break;
5770                 }
5771                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5772                                       (u32 *)&vpd_data[i]);
5773         }
5774
5775         if (!fail) {
5776                 /* read serial number of adapter */
5777                 for (cnt = 0; cnt < 252; cnt++) {
5778                         if ((vpd_data[cnt] == 'S') &&
5779                             (vpd_data[cnt+1] == 'N')) {
5780                                 len = vpd_data[cnt+2];
5781                                 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5782                                         memcpy(nic->serial_num,
5783                                                &vpd_data[cnt + 3],
5784                                                len);
5785                                         memset(nic->serial_num+len,
5786                                                0,
5787                                                VPD_STRING_LEN-len);
5788                                         break;
5789                                 }
5790                         }
5791                 }
5792         }
5793
5794         if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5795                 len = vpd_data[1];
5796                 memcpy(nic->product_name, &vpd_data[3], len);
5797                 nic->product_name[len] = 0;
5798         }
5799         kfree(vpd_data);
5800         swstats->mem_freed += 256;
5801 }
5802
5803 /**
5804  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5805  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
5806  *  @eeprom : pointer to the user level structure provided by ethtool,
5807  *  containing all relevant information.
5808  *  @data_buf : user defined value to be written into Eeprom.
5809  *  Description: Reads the values stored in the Eeprom at given offset
5810  *  for a given length. Stores these values int the input argument data
5811  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5812  *  Return value:
5813  *  int  0 on success
5814  */
5815
5816 static int s2io_ethtool_geeprom(struct net_device *dev,
5817                                 struct ethtool_eeprom *eeprom, u8 * data_buf)
5818 {
5819         u32 i, valid;
5820         u64 data;
5821         struct s2io_nic *sp = netdev_priv(dev);
5822
5823         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5824
5825         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5826                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5827
5828         for (i = 0; i < eeprom->len; i += 4) {
5829                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5830                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5831                         return -EFAULT;
5832                 }
5833                 valid = INV(data);
5834                 memcpy((data_buf + i), &valid, 4);
5835         }
5836         return 0;
5837 }
5838
5839 /**
5840  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5841  *  @sp : private member of the device structure, which is a pointer to the
5842  *  s2io_nic structure.
5843  *  @eeprom : pointer to the user level structure provided by ethtool,
5844  *  containing all relevant information.
5845  *  @data_buf ; user defined value to be written into Eeprom.
5846  *  Description:
5847  *  Tries to write the user provided value in the Eeprom, at the offset
5848  *  given by the user.
5849  *  Return value:
5850  *  0 on success, -EFAULT on failure.
5851  */
5852
5853 static int s2io_ethtool_seeprom(struct net_device *dev,
5854                                 struct ethtool_eeprom *eeprom,
5855                                 u8 *data_buf)
5856 {
5857         int len = eeprom->len, cnt = 0;
5858         u64 valid = 0, data;
5859         struct s2io_nic *sp = netdev_priv(dev);
5860
5861         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5862                 DBG_PRINT(ERR_DBG,
5863                           "ETHTOOL_WRITE_EEPROM Err: "
5864                           "Magic value is wrong, it is 0x%x should be 0x%x\n",
5865                           (sp->pdev->vendor | (sp->pdev->device << 16)),
5866                           eeprom->magic);
5867                 return -EFAULT;
5868         }
5869
5870         while (len) {
5871                 data = (u32)data_buf[cnt] & 0x000000FF;
5872                 if (data)
5873                         valid = (u32)(data << 24);
5874                 else
5875                         valid = data;
5876
5877                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5878                         DBG_PRINT(ERR_DBG,
5879                                   "ETHTOOL_WRITE_EEPROM Err: "
5880                                   "Cannot write into the specified offset\n");
5881                         return -EFAULT;
5882                 }
5883                 cnt++;
5884                 len--;
5885         }
5886
5887         return 0;
5888 }
5889
5890 /**
5891  * s2io_register_test - reads and writes into all clock domains.
5892  * @sp : private member of the device structure, which is a pointer to the
5893  * s2io_nic structure.
5894  * @data : variable that returns the result of each of the test conducted b
5895  * by the driver.
5896  * Description:
5897  * Read and write into all clock domains. The NIC has 3 clock domains,
5898  * see that registers in all the three regions are accessible.
5899  * Return value:
5900  * 0 on success.
5901  */
5902
5903 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5904 {
5905         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5906         u64 val64 = 0, exp_val;
5907         int fail = 0;
5908
5909         val64 = readq(&bar0->pif_rd_swapper_fb);
5910         if (val64 != 0x123456789abcdefULL) {
5911                 fail = 1;
5912                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5913         }
5914
5915         val64 = readq(&bar0->rmac_pause_cfg);
5916         if (val64 != 0xc000ffff00000000ULL) {
5917                 fail = 1;
5918                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5919         }
5920
5921         val64 = readq(&bar0->rx_queue_cfg);
5922         if (sp->device_type == XFRAME_II_DEVICE)
5923                 exp_val = 0x0404040404040404ULL;
5924         else
5925                 exp_val = 0x0808080808080808ULL;
5926         if (val64 != exp_val) {
5927                 fail = 1;
5928                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5929         }
5930
5931         val64 = readq(&bar0->xgxs_efifo_cfg);
5932         if (val64 != 0x000000001923141EULL) {
5933                 fail = 1;
5934                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5935         }
5936
5937         val64 = 0x5A5A5A5A5A5A5A5AULL;
5938         writeq(val64, &bar0->xmsi_data);
5939         val64 = readq(&bar0->xmsi_data);
5940         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5941                 fail = 1;
5942                 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5943         }
5944
5945         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5946         writeq(val64, &bar0->xmsi_data);
5947         val64 = readq(&bar0->xmsi_data);
5948         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5949                 fail = 1;
5950                 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5951         }
5952
5953         *data = fail;
5954         return fail;
5955 }
5956
5957 /**
5958  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5959  * @sp : private member of the device structure, which is a pointer to the
5960  * s2io_nic structure.
5961  * @data:variable that returns the result of each of the test conducted by
5962  * the driver.
5963  * Description:
5964  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5965  * register.
5966  * Return value:
5967  * 0 on success.
5968  */
5969
5970 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5971 {
5972         int fail = 0;
5973         u64 ret_data, org_4F0, org_7F0;
5974         u8 saved_4F0 = 0, saved_7F0 = 0;
5975         struct net_device *dev = sp->dev;
5976
5977         /* Test Write Error at offset 0 */
5978         /* Note that SPI interface allows write access to all areas
5979          * of EEPROM. Hence doing all negative testing only for Xframe I.
5980          */
5981         if (sp->device_type == XFRAME_I_DEVICE)
5982                 if (!write_eeprom(sp, 0, 0, 3))
5983                         fail = 1;
5984
5985         /* Save current values at offsets 0x4F0 and 0x7F0 */
5986         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5987                 saved_4F0 = 1;
5988         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5989                 saved_7F0 = 1;
5990
5991         /* Test Write at offset 4f0 */
5992         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5993                 fail = 1;
5994         if (read_eeprom(sp, 0x4F0, &ret_data))
5995                 fail = 1;
5996
5997         if (ret_data != 0x012345) {
5998                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5999                           "Data written %llx Data read %llx\n",
6000                           dev->name, (unsigned long long)0x12345,
6001                           (unsigned long long)ret_data);
6002                 fail = 1;
6003         }
6004
6005         /* Reset the EEPROM data go FFFF */
6006         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6007
6008         /* Test Write Request Error at offset 0x7c */
6009         if (sp->device_type == XFRAME_I_DEVICE)
6010                 if (!write_eeprom(sp, 0x07C, 0, 3))
6011                         fail = 1;
6012
6013         /* Test Write Request at offset 0x7f0 */
6014         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6015                 fail = 1;
6016         if (read_eeprom(sp, 0x7F0, &ret_data))
6017                 fail = 1;
6018
6019         if (ret_data != 0x012345) {
6020                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6021                           "Data written %llx Data read %llx\n",
6022                           dev->name, (unsigned long long)0x12345,
6023                           (unsigned long long)ret_data);
6024                 fail = 1;
6025         }
6026
6027         /* Reset the EEPROM data go FFFF */
6028         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6029
6030         if (sp->device_type == XFRAME_I_DEVICE) {
6031                 /* Test Write Error at offset 0x80 */
6032                 if (!write_eeprom(sp, 0x080, 0, 3))
6033                         fail = 1;
6034
6035                 /* Test Write Error at offset 0xfc */
6036                 if (!write_eeprom(sp, 0x0FC, 0, 3))
6037                         fail = 1;
6038
6039                 /* Test Write Error at offset 0x100 */
6040                 if (!write_eeprom(sp, 0x100, 0, 3))
6041                         fail = 1;
6042
6043                 /* Test Write Error at offset 4ec */
6044                 if (!write_eeprom(sp, 0x4EC, 0, 3))
6045                         fail = 1;
6046         }
6047
6048         /* Restore values at offsets 0x4F0 and 0x7F0 */
6049         if (saved_4F0)
6050                 write_eeprom(sp, 0x4F0, org_4F0, 3);
6051         if (saved_7F0)
6052                 write_eeprom(sp, 0x7F0, org_7F0, 3);
6053
6054         *data = fail;
6055         return fail;
6056 }
6057
6058 /**
6059  * s2io_bist_test - invokes the MemBist test of the card .
6060  * @sp : private member of the device structure, which is a pointer to the
6061  * s2io_nic structure.
6062  * @data:variable that returns the result of each of the test conducted by
6063  * the driver.
6064  * Description:
6065  * This invokes the MemBist test of the card. We give around
6066  * 2 secs time for the Test to complete. If it's still not complete
6067  * within this peiod, we consider that the test failed.
6068  * Return value:
6069  * 0 on success and -1 on failure.
6070  */
6071
6072 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6073 {
6074         u8 bist = 0;
6075         int cnt = 0, ret = -1;
6076
6077         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6078         bist |= PCI_BIST_START;
6079         pci_write_config_word(sp->pdev, PCI_BIST, bist);
6080
6081         while (cnt < 20) {
6082                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6083                 if (!(bist & PCI_BIST_START)) {
6084                         *data = (bist & PCI_BIST_CODE_MASK);
6085                         ret = 0;
6086                         break;
6087                 }
6088                 msleep(100);
6089                 cnt++;
6090         }
6091
6092         return ret;
6093 }
6094
6095 /**
6096  * s2io_link_test - verifies the link state of the nic
6097  * @sp ; private member of the device structure, which is a pointer to the
6098  * s2io_nic structure.
6099  * @data: variable that returns the result of each of the test conducted by
6100  * the driver.
6101  * Description:
6102  * The function verifies the link state of the NIC and updates the input
6103  * argument 'data' appropriately.
6104  * Return value:
6105  * 0 on success.
6106  */
6107
6108 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6109 {
6110         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6111         u64 val64;
6112
6113         val64 = readq(&bar0->adapter_status);
6114         if (!(LINK_IS_UP(val64)))
6115                 *data = 1;
6116         else
6117                 *data = 0;
6118
6119         return *data;
6120 }
6121
6122 /**
6123  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6124  * @sp: private member of the device structure, which is a pointer to the
6125  * s2io_nic structure.
6126  * @data: variable that returns the result of each of the test
6127  * conducted by the driver.
6128  * Description:
6129  *  This is one of the offline test that tests the read and write
6130  *  access to the RldRam chip on the NIC.
6131  * Return value:
6132  *  0 on success.
6133  */
6134
6135 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6136 {
6137         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6138         u64 val64;
6139         int cnt, iteration = 0, test_fail = 0;
6140
6141         val64 = readq(&bar0->adapter_control);
6142         val64 &= ~ADAPTER_ECC_EN;
6143         writeq(val64, &bar0->adapter_control);
6144
6145         val64 = readq(&bar0->mc_rldram_test_ctrl);
6146         val64 |= MC_RLDRAM_TEST_MODE;
6147         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6148
6149         val64 = readq(&bar0->mc_rldram_mrs);
6150         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6151         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6152
6153         val64 |= MC_RLDRAM_MRS_ENABLE;
6154         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6155
6156         while (iteration < 2) {
6157                 val64 = 0x55555555aaaa0000ULL;
6158                 if (iteration == 1)
6159                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6160                 writeq(val64, &bar0->mc_rldram_test_d0);
6161
6162                 val64 = 0xaaaa5a5555550000ULL;
6163                 if (iteration == 1)
6164                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6165                 writeq(val64, &bar0->mc_rldram_test_d1);
6166
6167                 val64 = 0x55aaaaaaaa5a0000ULL;
6168                 if (iteration == 1)
6169                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6170                 writeq(val64, &bar0->mc_rldram_test_d2);
6171
6172                 val64 = (u64) (0x0000003ffffe0100ULL);
6173                 writeq(val64, &bar0->mc_rldram_test_add);
6174
6175                 val64 = MC_RLDRAM_TEST_MODE |
6176                         MC_RLDRAM_TEST_WRITE |
6177                         MC_RLDRAM_TEST_GO;
6178                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6179
6180                 for (cnt = 0; cnt < 5; cnt++) {
6181                         val64 = readq(&bar0->mc_rldram_test_ctrl);
6182                         if (val64 & MC_RLDRAM_TEST_DONE)
6183                                 break;
6184                         msleep(200);
6185                 }
6186
6187                 if (cnt == 5)
6188                         break;
6189
6190                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6191                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6192
6193                 for (cnt = 0; cnt < 5; cnt++) {
6194                         val64 = readq(&bar0->mc_rldram_test_ctrl);
6195                         if (val64 & MC_RLDRAM_TEST_DONE)
6196                                 break;
6197                         msleep(500);
6198                 }
6199
6200                 if (cnt == 5)
6201                         break;
6202
6203                 val64 = readq(&bar0->mc_rldram_test_ctrl);
6204                 if (!(val64 & MC_RLDRAM_TEST_PASS))
6205                         test_fail = 1;
6206
6207                 iteration++;
6208         }
6209
6210         *data = test_fail;
6211
6212         /* Bring the adapter out of test mode */
6213         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6214
6215         return test_fail;
6216 }
6217
6218 /**
6219  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6220  *  @sp : private member of the device structure, which is a pointer to the
6221  *  s2io_nic structure.
6222  *  @ethtest : pointer to a ethtool command specific structure that will be
6223  *  returned to the user.
6224  *  @data : variable that returns the result of each of the test
6225  * conducted by the driver.
6226  * Description:
6227  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
6228  *  the health of the card.
6229  * Return value:
6230  *  void
6231  */
6232
6233 static void s2io_ethtool_test(struct net_device *dev,
6234                               struct ethtool_test *ethtest,
6235                               uint64_t *data)
6236 {
6237         struct s2io_nic *sp = netdev_priv(dev);
6238         int orig_state = netif_running(sp->dev);
6239
6240         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6241                 /* Offline Tests. */
6242                 if (orig_state)
6243                         s2io_close(sp->dev);
6244
6245                 if (s2io_register_test(sp, &data[0]))
6246                         ethtest->flags |= ETH_TEST_FL_FAILED;
6247
6248                 s2io_reset(sp);
6249
6250                 if (s2io_rldram_test(sp, &data[3]))
6251                         ethtest->flags |= ETH_TEST_FL_FAILED;
6252
6253                 s2io_reset(sp);
6254
6255                 if (s2io_eeprom_test(sp, &data[1]))
6256                         ethtest->flags |= ETH_TEST_FL_FAILED;
6257
6258                 if (s2io_bist_test(sp, &data[4]))
6259                         ethtest->flags |= ETH_TEST_FL_FAILED;
6260
6261                 if (orig_state)
6262                         s2io_open(sp->dev);
6263
6264                 data[2] = 0;
6265         } else {
6266                 /* Online Tests. */
6267                 if (!orig_state) {
6268                         DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6269                                   dev->name);
6270                         data[0] = -1;
6271                         data[1] = -1;
6272                         data[2] = -1;
6273                         data[3] = -1;
6274                         data[4] = -1;
6275                 }
6276
6277                 if (s2io_link_test(sp, &data[2]))
6278                         ethtest->flags |= ETH_TEST_FL_FAILED;
6279
6280                 data[0] = 0;
6281                 data[1] = 0;
6282                 data[3] = 0;
6283                 data[4] = 0;
6284         }
6285 }
6286
6287 static void s2io_get_ethtool_stats(struct net_device *dev,
6288                                    struct ethtool_stats *estats,
6289                                    u64 *tmp_stats)
6290 {
6291         int i = 0, k;
6292         struct s2io_nic *sp = netdev_priv(dev);
6293         struct stat_block *stats = sp->mac_control.stats_info;
6294         struct swStat *swstats = &stats->sw_stat;
6295         struct xpakStat *xstats = &stats->xpak_stat;
6296
6297         s2io_updt_stats(sp);
6298         tmp_stats[i++] =
6299                 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32  |
6300                 le32_to_cpu(stats->tmac_frms);
6301         tmp_stats[i++] =
6302                 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6303                 le32_to_cpu(stats->tmac_data_octets);
6304         tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6305         tmp_stats[i++] =
6306                 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6307                 le32_to_cpu(stats->tmac_mcst_frms);
6308         tmp_stats[i++] =
6309                 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6310                 le32_to_cpu(stats->tmac_bcst_frms);
6311         tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6312         tmp_stats[i++] =
6313                 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6314                 le32_to_cpu(stats->tmac_ttl_octets);
6315         tmp_stats[i++] =
6316                 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6317                 le32_to_cpu(stats->tmac_ucst_frms);
6318         tmp_stats[i++] =
6319                 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6320                 le32_to_cpu(stats->tmac_nucst_frms);
6321         tmp_stats[i++] =
6322                 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6323                 le32_to_cpu(stats->tmac_any_err_frms);
6324         tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6325         tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6326         tmp_stats[i++] =
6327                 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6328                 le32_to_cpu(stats->tmac_vld_ip);
6329         tmp_stats[i++] =
6330                 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6331                 le32_to_cpu(stats->tmac_drop_ip);
6332         tmp_stats[i++] =
6333                 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6334                 le32_to_cpu(stats->tmac_icmp);
6335         tmp_stats[i++] =
6336                 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6337                 le32_to_cpu(stats->tmac_rst_tcp);
6338         tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6339         tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6340                 le32_to_cpu(stats->tmac_udp);
6341         tmp_stats[i++] =
6342                 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6343                 le32_to_cpu(stats->rmac_vld_frms);
6344         tmp_stats[i++] =
6345                 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6346                 le32_to_cpu(stats->rmac_data_octets);
6347         tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6348         tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6349         tmp_stats[i++] =
6350                 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6351                 le32_to_cpu(stats->rmac_vld_mcst_frms);
6352         tmp_stats[i++] =
6353                 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6354                 le32_to_cpu(stats->rmac_vld_bcst_frms);
6355         tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6356         tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6357         tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6358         tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6359         tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6360         tmp_stats[i++] =
6361                 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6362                 le32_to_cpu(stats->rmac_ttl_octets);
6363         tmp_stats[i++] =
6364                 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6365                 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6366         tmp_stats[i++] =
6367                 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6368                 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6369         tmp_stats[i++] =
6370                 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6371                 le32_to_cpu(stats->rmac_discarded_frms);
6372         tmp_stats[i++] =
6373                 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6374                 << 32 | le32_to_cpu(stats->rmac_drop_events);
6375         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6376         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6377         tmp_stats[i++] =
6378                 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6379                 le32_to_cpu(stats->rmac_usized_frms);
6380         tmp_stats[i++] =
6381                 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6382                 le32_to_cpu(stats->rmac_osized_frms);
6383         tmp_stats[i++] =
6384                 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6385                 le32_to_cpu(stats->rmac_frag_frms);
6386         tmp_stats[i++] =
6387                 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6388                 le32_to_cpu(stats->rmac_jabber_frms);
6389         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6390         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6391         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6392         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6393         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6394         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6395         tmp_stats[i++] =
6396                 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6397                 le32_to_cpu(stats->rmac_ip);
6398         tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6399         tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6400         tmp_stats[i++] =
6401                 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6402                 le32_to_cpu(stats->rmac_drop_ip);
6403         tmp_stats[i++] =
6404                 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6405                 le32_to_cpu(stats->rmac_icmp);
6406         tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6407         tmp_stats[i++] =
6408                 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6409                 le32_to_cpu(stats->rmac_udp);
6410         tmp_stats[i++] =
6411                 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6412                 le32_to_cpu(stats->rmac_err_drp_udp);
6413         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6414         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6415         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6416         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6417         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6418         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6419         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6420         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6421         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6422         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6423         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6424         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6425         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6426         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6427         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6428         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6429         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6430         tmp_stats[i++] =
6431                 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6432                 le32_to_cpu(stats->rmac_pause_cnt);
6433         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6434         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6435         tmp_stats[i++] =
6436                 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6437                 le32_to_cpu(stats->rmac_accepted_ip);
6438         tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6439         tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6440         tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6441         tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6442         tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6443         tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6444         tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6445         tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6446         tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6447         tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6448         tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6449         tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6450         tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6451         tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6452         tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6453         tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6454         tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6455         tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6456         tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6457
6458         /* Enhanced statistics exist only for Hercules */
6459         if (sp->device_type == XFRAME_II_DEVICE) {
6460                 tmp_stats[i++] =
6461                         le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6462                 tmp_stats[i++] =
6463                         le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6464                 tmp_stats[i++] =
6465                         le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6466                 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6467                 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6468                 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6469                 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6470                 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6471                 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6472                 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6473                 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6474                 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6475                 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6476                 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6477                 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6478                 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6479         }
6480
6481         tmp_stats[i++] = 0;
6482         tmp_stats[i++] = swstats->single_ecc_errs;
6483         tmp_stats[i++] = swstats->double_ecc_errs;
6484         tmp_stats[i++] = swstats->parity_err_cnt;
6485         tmp_stats[i++] = swstats->serious_err_cnt;
6486         tmp_stats[i++] = swstats->soft_reset_cnt;
6487         tmp_stats[i++] = swstats->fifo_full_cnt;
6488         for (k = 0; k < MAX_RX_RINGS; k++)
6489                 tmp_stats[i++] = swstats->ring_full_cnt[k];
6490         tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6491         tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6492         tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6493         tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6494         tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6495         tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6496         tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6497         tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6498         tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6499         tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6500         tmp_stats[i++] = xstats->warn_laser_output_power_high;
6501         tmp_stats[i++] = xstats->warn_laser_output_power_low;
6502         tmp_stats[i++] = swstats->clubbed_frms_cnt;
6503         tmp_stats[i++] = swstats->sending_both;
6504         tmp_stats[i++] = swstats->outof_sequence_pkts;
6505         tmp_stats[i++] = swstats->flush_max_pkts;
6506         if (swstats->num_aggregations) {
6507                 u64 tmp = swstats->sum_avg_pkts_aggregated;
6508                 int count = 0;
6509                 /*
6510                  * Since 64-bit divide does not work on all platforms,
6511                  * do repeated subtraction.
6512                  */
6513                 while (tmp >= swstats->num_aggregations) {
6514                         tmp -= swstats->num_aggregations;
6515                         count++;
6516                 }
6517                 tmp_stats[i++] = count;
6518         } else
6519                 tmp_stats[i++] = 0;
6520         tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6521         tmp_stats[i++] = swstats->pci_map_fail_cnt;
6522         tmp_stats[i++] = swstats->watchdog_timer_cnt;
6523         tmp_stats[i++] = swstats->mem_allocated;
6524         tmp_stats[i++] = swstats->mem_freed;
6525         tmp_stats[i++] = swstats->link_up_cnt;
6526         tmp_stats[i++] = swstats->link_down_cnt;
6527         tmp_stats[i++] = swstats->link_up_time;
6528         tmp_stats[i++] = swstats->link_down_time;
6529
6530         tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6531         tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6532         tmp_stats[i++] = swstats->tx_parity_err_cnt;
6533         tmp_stats[i++] = swstats->tx_link_loss_cnt;
6534         tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6535
6536         tmp_stats[i++] = swstats->rx_parity_err_cnt;
6537         tmp_stats[i++] = swstats->rx_abort_cnt;
6538         tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6539         tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6540         tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6541         tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6542         tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6543         tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6544         tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6545         tmp_stats[i++] = swstats->tda_err_cnt;
6546         tmp_stats[i++] = swstats->pfc_err_cnt;
6547         tmp_stats[i++] = swstats->pcc_err_cnt;
6548         tmp_stats[i++] = swstats->tti_err_cnt;
6549         tmp_stats[i++] = swstats->tpa_err_cnt;
6550         tmp_stats[i++] = swstats->sm_err_cnt;
6551         tmp_stats[i++] = swstats->lso_err_cnt;
6552         tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6553         tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6554         tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6555         tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6556         tmp_stats[i++] = swstats->rc_err_cnt;
6557         tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6558         tmp_stats[i++] = swstats->rpa_err_cnt;
6559         tmp_stats[i++] = swstats->rda_err_cnt;
6560         tmp_stats[i++] = swstats->rti_err_cnt;
6561         tmp_stats[i++] = swstats->mc_err_cnt;
6562 }
6563
6564 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6565 {
6566         return XENA_REG_SPACE;
6567 }
6568
6569
6570 static int s2io_get_eeprom_len(struct net_device *dev)
6571 {
6572         return XENA_EEPROM_SPACE;
6573 }
6574
6575 static int s2io_get_sset_count(struct net_device *dev, int sset)
6576 {
6577         struct s2io_nic *sp = netdev_priv(dev);
6578
6579         switch (sset) {
6580         case ETH_SS_TEST:
6581                 return S2IO_TEST_LEN;
6582         case ETH_SS_STATS:
6583                 switch (sp->device_type) {
6584                 case XFRAME_I_DEVICE:
6585                         return XFRAME_I_STAT_LEN;
6586                 case XFRAME_II_DEVICE:
6587                         return XFRAME_II_STAT_LEN;
6588                 default:
6589                         return 0;
6590                 }
6591         default:
6592                 return -EOPNOTSUPP;
6593         }
6594 }
6595
6596 static void s2io_ethtool_get_strings(struct net_device *dev,
6597                                      u32 stringset, u8 *data)
6598 {
6599         int stat_size = 0;
6600         struct s2io_nic *sp = netdev_priv(dev);
6601
6602         switch (stringset) {
6603         case ETH_SS_TEST:
6604                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6605                 break;
6606         case ETH_SS_STATS:
6607                 stat_size = sizeof(ethtool_xena_stats_keys);
6608                 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6609                 if (sp->device_type == XFRAME_II_DEVICE) {
6610                         memcpy(data + stat_size,
6611                                &ethtool_enhanced_stats_keys,
6612                                sizeof(ethtool_enhanced_stats_keys));
6613                         stat_size += sizeof(ethtool_enhanced_stats_keys);
6614                 }
6615
6616                 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6617                        sizeof(ethtool_driver_stats_keys));
6618         }
6619 }
6620
6621 static int s2io_set_features(struct net_device *dev, netdev_features_t features)
6622 {
6623         struct s2io_nic *sp = netdev_priv(dev);
6624         netdev_features_t changed = (features ^ dev->features) & NETIF_F_LRO;
6625
6626         if (changed && netif_running(dev)) {
6627                 int rc;
6628
6629                 s2io_stop_all_tx_queue(sp);
6630                 s2io_card_down(sp);
6631                 dev->features = features;
6632                 rc = s2io_card_up(sp);
6633                 if (rc)
6634                         s2io_reset(sp);
6635                 else
6636                         s2io_start_all_tx_queue(sp);
6637
6638                 return rc ? rc : 1;
6639         }
6640
6641         return 0;
6642 }
6643
6644 static const struct ethtool_ops netdev_ethtool_ops = {
6645         .get_settings = s2io_ethtool_gset,
6646         .set_settings = s2io_ethtool_sset,
6647         .get_drvinfo = s2io_ethtool_gdrvinfo,
6648         .get_regs_len = s2io_ethtool_get_regs_len,
6649         .get_regs = s2io_ethtool_gregs,
6650         .get_link = ethtool_op_get_link,
6651         .get_eeprom_len = s2io_get_eeprom_len,
6652         .get_eeprom = s2io_ethtool_geeprom,
6653         .set_eeprom = s2io_ethtool_seeprom,
6654         .get_ringparam = s2io_ethtool_gringparam,
6655         .get_pauseparam = s2io_ethtool_getpause_data,
6656         .set_pauseparam = s2io_ethtool_setpause_data,
6657         .self_test = s2io_ethtool_test,
6658         .get_strings = s2io_ethtool_get_strings,
6659         .set_phys_id = s2io_ethtool_set_led,
6660         .get_ethtool_stats = s2io_get_ethtool_stats,
6661         .get_sset_count = s2io_get_sset_count,
6662 };
6663
6664 /**
6665  *  s2io_ioctl - Entry point for the Ioctl
6666  *  @dev :  Device pointer.
6667  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
6668  *  a proprietary structure used to pass information to the driver.
6669  *  @cmd :  This is used to distinguish between the different commands that
6670  *  can be passed to the IOCTL functions.
6671  *  Description:
6672  *  Currently there are no special functionality supported in IOCTL, hence
6673  *  function always return EOPNOTSUPPORTED
6674  */
6675
6676 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6677 {
6678         return -EOPNOTSUPP;
6679 }
6680
6681 /**
6682  *  s2io_change_mtu - entry point to change MTU size for the device.
6683  *   @dev : device pointer.
6684  *   @new_mtu : the new MTU size for the device.
6685  *   Description: A driver entry point to change MTU size for the device.
6686  *   Before changing the MTU the device must be stopped.
6687  *  Return value:
6688  *   0 on success and an appropriate (-)ve integer as defined in errno.h
6689  *   file on failure.
6690  */
6691
6692 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6693 {
6694         struct s2io_nic *sp = netdev_priv(dev);
6695         int ret = 0;
6696
6697         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6698                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6699                 return -EPERM;
6700         }
6701
6702         dev->mtu = new_mtu;
6703         if (netif_running(dev)) {
6704                 s2io_stop_all_tx_queue(sp);
6705                 s2io_card_down(sp);
6706                 ret = s2io_card_up(sp);
6707                 if (ret) {
6708                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6709                                   __func__);
6710                         return ret;
6711                 }
6712                 s2io_wake_all_tx_queue(sp);
6713         } else { /* Device is down */
6714                 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6715                 u64 val64 = new_mtu;
6716
6717                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6718         }
6719
6720         return ret;
6721 }
6722
6723 /**
6724  * s2io_set_link - Set the LInk status
6725  * @data: long pointer to device private structue
6726  * Description: Sets the link status for the adapter
6727  */
6728
6729 static void s2io_set_link(struct work_struct *work)
6730 {
6731         struct s2io_nic *nic = container_of(work, struct s2io_nic,
6732                                             set_link_task);
6733         struct net_device *dev = nic->dev;
6734         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6735         register u64 val64;
6736         u16 subid;
6737
6738         rtnl_lock();
6739
6740         if (!netif_running(dev))
6741                 goto out_unlock;
6742
6743         if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6744                 /* The card is being reset, no point doing anything */
6745                 goto out_unlock;
6746         }
6747
6748         subid = nic->pdev->subsystem_device;
6749         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6750                 /*
6751                  * Allow a small delay for the NICs self initiated
6752                  * cleanup to complete.
6753                  */
6754                 msleep(100);
6755         }
6756
6757         val64 = readq(&bar0->adapter_status);
6758         if (LINK_IS_UP(val64)) {
6759                 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6760                         if (verify_xena_quiescence(nic)) {
6761                                 val64 = readq(&bar0->adapter_control);
6762                                 val64 |= ADAPTER_CNTL_EN;
6763                                 writeq(val64, &bar0->adapter_control);
6764                                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6765                                             nic->device_type, subid)) {
6766                                         val64 = readq(&bar0->gpio_control);
6767                                         val64 |= GPIO_CTRL_GPIO_0;
6768                                         writeq(val64, &bar0->gpio_control);
6769                                         val64 = readq(&bar0->gpio_control);
6770                                 } else {
6771                                         val64 |= ADAPTER_LED_ON;
6772                                         writeq(val64, &bar0->adapter_control);
6773                                 }
6774                                 nic->device_enabled_once = true;
6775                         } else {
6776                                 DBG_PRINT(ERR_DBG,
6777                                           "%s: Error: device is not Quiescent\n",
6778                                           dev->name);
6779                                 s2io_stop_all_tx_queue(nic);
6780                         }
6781                 }
6782                 val64 = readq(&bar0->adapter_control);
6783                 val64 |= ADAPTER_LED_ON;
6784                 writeq(val64, &bar0->adapter_control);
6785                 s2io_link(nic, LINK_UP);
6786         } else {
6787                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6788                                                       subid)) {
6789                         val64 = readq(&bar0->gpio_control);
6790                         val64 &= ~GPIO_CTRL_GPIO_0;
6791                         writeq(val64, &bar0->gpio_control);
6792                         val64 = readq(&bar0->gpio_control);
6793                 }
6794                 /* turn off LED */
6795                 val64 = readq(&bar0->adapter_control);
6796                 val64 = val64 & (~ADAPTER_LED_ON);
6797                 writeq(val64, &bar0->adapter_control);
6798                 s2io_link(nic, LINK_DOWN);
6799         }
6800         clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6801
6802 out_unlock:
6803         rtnl_unlock();
6804 }
6805
6806 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6807                                   struct buffAdd *ba,
6808                                   struct sk_buff **skb, u64 *temp0, u64 *temp1,
6809                                   u64 *temp2, int size)
6810 {
6811         struct net_device *dev = sp->dev;
6812         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6813
6814         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6815                 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6816                 /* allocate skb */
6817                 if (*skb) {
6818                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6819                         /*
6820                          * As Rx frame are not going to be processed,
6821                          * using same mapped address for the Rxd
6822                          * buffer pointer
6823                          */
6824                         rxdp1->Buffer0_ptr = *temp0;
6825                 } else {
6826                         *skb = netdev_alloc_skb(dev, size);
6827                         if (!(*skb)) {
6828                                 DBG_PRINT(INFO_DBG,
6829                                           "%s: Out of memory to allocate %s\n",
6830                                           dev->name, "1 buf mode SKBs");
6831                                 stats->mem_alloc_fail_cnt++;
6832                                 return -ENOMEM ;
6833                         }
6834                         stats->mem_allocated += (*skb)->truesize;
6835                         /* storing the mapped addr in a temp variable
6836                          * such it will be used for next rxd whose
6837                          * Host Control is NULL
6838                          */
6839                         rxdp1->Buffer0_ptr = *temp0 =
6840                                 pci_map_single(sp->pdev, (*skb)->data,
6841                                                size - NET_IP_ALIGN,
6842                                                PCI_DMA_FROMDEVICE);
6843                         if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6844                                 goto memalloc_failed;
6845                         rxdp->Host_Control = (unsigned long) (*skb);
6846                 }
6847         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6848                 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6849                 /* Two buffer Mode */
6850                 if (*skb) {
6851                         rxdp3->Buffer2_ptr = *temp2;
6852                         rxdp3->Buffer0_ptr = *temp0;
6853                         rxdp3->Buffer1_ptr = *temp1;
6854                 } else {
6855                         *skb = netdev_alloc_skb(dev, size);
6856                         if (!(*skb)) {
6857                                 DBG_PRINT(INFO_DBG,
6858                                           "%s: Out of memory to allocate %s\n",
6859                                           dev->name,
6860                                           "2 buf mode SKBs");
6861                                 stats->mem_alloc_fail_cnt++;
6862                                 return -ENOMEM;
6863                         }
6864                         stats->mem_allocated += (*skb)->truesize;
6865                         rxdp3->Buffer2_ptr = *temp2 =
6866                                 pci_map_single(sp->pdev, (*skb)->data,
6867                                                dev->mtu + 4,
6868                                                PCI_DMA_FROMDEVICE);
6869                         if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6870                                 goto memalloc_failed;
6871                         rxdp3->Buffer0_ptr = *temp0 =
6872                                 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6873                                                PCI_DMA_FROMDEVICE);
6874                         if (pci_dma_mapping_error(sp->pdev,
6875                                                   rxdp3->Buffer0_ptr)) {
6876                                 pci_unmap_single(sp->pdev,
6877                                                  (dma_addr_t)rxdp3->Buffer2_ptr,
6878                                                  dev->mtu + 4,
6879                                                  PCI_DMA_FROMDEVICE);
6880                                 goto memalloc_failed;
6881                         }
6882                         rxdp->Host_Control = (unsigned long) (*skb);
6883
6884                         /* Buffer-1 will be dummy buffer not used */
6885                         rxdp3->Buffer1_ptr = *temp1 =
6886                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6887                                                PCI_DMA_FROMDEVICE);
6888                         if (pci_dma_mapping_error(sp->pdev,
6889                                                   rxdp3->Buffer1_ptr)) {
6890                                 pci_unmap_single(sp->pdev,
6891                                                  (dma_addr_t)rxdp3->Buffer0_ptr,
6892                                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
6893                                 pci_unmap_single(sp->pdev,
6894                                                  (dma_addr_t)rxdp3->Buffer2_ptr,
6895                                                  dev->mtu + 4,
6896                                                  PCI_DMA_FROMDEVICE);
6897                                 goto memalloc_failed;
6898                         }
6899                 }
6900         }
6901         return 0;
6902
6903 memalloc_failed:
6904         stats->pci_map_fail_cnt++;
6905         stats->mem_freed += (*skb)->truesize;
6906         dev_kfree_skb(*skb);
6907         return -ENOMEM;
6908 }
6909
6910 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6911                                 int size)
6912 {
6913         struct net_device *dev = sp->dev;
6914         if (sp->rxd_mode == RXD_MODE_1) {
6915                 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6916         } else if (sp->rxd_mode == RXD_MODE_3B) {
6917                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6918                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6919                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6920         }
6921 }
6922
6923 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
6924 {
6925         int i, j, k, blk_cnt = 0, size;
6926         struct config_param *config = &sp->config;
6927         struct mac_info *mac_control = &sp->mac_control;
6928         struct net_device *dev = sp->dev;
6929         struct RxD_t *rxdp = NULL;
6930         struct sk_buff *skb = NULL;
6931         struct buffAdd *ba = NULL;
6932         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6933
6934         /* Calculate the size based on ring mode */
6935         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6936                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6937         if (sp->rxd_mode == RXD_MODE_1)
6938                 size += NET_IP_ALIGN;
6939         else if (sp->rxd_mode == RXD_MODE_3B)
6940                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6941
6942         for (i = 0; i < config->rx_ring_num; i++) {
6943                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6944                 struct ring_info *ring = &mac_control->rings[i];
6945
6946                 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6947
6948                 for (j = 0; j < blk_cnt; j++) {
6949                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6950                                 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
6951                                 if (sp->rxd_mode == RXD_MODE_3B)
6952                                         ba = &ring->ba[j][k];
6953                                 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
6954                                                            &temp0_64,
6955                                                            &temp1_64,
6956                                                            &temp2_64,
6957                                                            size) == -ENOMEM) {
6958                                         return 0;
6959                                 }
6960
6961                                 set_rxd_buffer_size(sp, rxdp, size);
6962                                 wmb();
6963                                 /* flip the Ownership bit to Hardware */
6964                                 rxdp->Control_1 |= RXD_OWN_XENA;
6965                         }
6966                 }
6967         }
6968         return 0;
6969
6970 }
6971
6972 static int s2io_add_isr(struct s2io_nic *sp)
6973 {
6974         int ret = 0;
6975         struct net_device *dev = sp->dev;
6976         int err = 0;
6977
6978         if (sp->config.intr_type == MSI_X)
6979                 ret = s2io_enable_msi_x(sp);
6980         if (ret) {
6981                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6982                 sp->config.intr_type = INTA;
6983         }
6984
6985         /*
6986          * Store the values of the MSIX table in
6987          * the struct s2io_nic structure
6988          */
6989         store_xmsi_data(sp);
6990
6991         /* After proper initialization of H/W, register ISR */
6992         if (sp->config.intr_type == MSI_X) {
6993                 int i, msix_rx_cnt = 0;
6994
6995                 for (i = 0; i < sp->num_entries; i++) {
6996                         if (sp->s2io_entries[i].in_use == MSIX_FLG) {
6997                                 if (sp->s2io_entries[i].type ==
6998                                     MSIX_RING_TYPE) {
6999                                         sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7000                                                 dev->name, i);
7001                                         err = request_irq(sp->entries[i].vector,
7002                                                           s2io_msix_ring_handle,
7003                                                           0,
7004                                                           sp->desc[i],
7005                                                           sp->s2io_entries[i].arg);
7006                                 } else if (sp->s2io_entries[i].type ==
7007                                            MSIX_ALARM_TYPE) {
7008                                         sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7009                                                 dev->name, i);
7010                                         err = request_irq(sp->entries[i].vector,
7011                                                           s2io_msix_fifo_handle,
7012                                                           0,
7013                                                           sp->desc[i],
7014                                                           sp->s2io_entries[i].arg);
7015
7016                                 }
7017                                 /* if either data or addr is zero print it. */
7018                                 if (!(sp->msix_info[i].addr &&
7019                                       sp->msix_info[i].data)) {
7020                                         DBG_PRINT(ERR_DBG,
7021                                                   "%s @Addr:0x%llx Data:0x%llx\n",
7022                                                   sp->desc[i],
7023                                                   (unsigned long long)
7024                                                   sp->msix_info[i].addr,
7025                                                   (unsigned long long)
7026                                                   ntohl(sp->msix_info[i].data));
7027                                 } else
7028                                         msix_rx_cnt++;
7029                                 if (err) {
7030                                         remove_msix_isr(sp);
7031
7032                                         DBG_PRINT(ERR_DBG,
7033                                                   "%s:MSI-X-%d registration "
7034                                                   "failed\n", dev->name, i);
7035
7036                                         DBG_PRINT(ERR_DBG,
7037                                                   "%s: Defaulting to INTA\n",
7038                                                   dev->name);
7039                                         sp->config.intr_type = INTA;
7040                                         break;
7041                                 }
7042                                 sp->s2io_entries[i].in_use =
7043                                         MSIX_REGISTERED_SUCCESS;
7044                         }
7045                 }
7046                 if (!err) {
7047                         pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7048                         DBG_PRINT(INFO_DBG,
7049                                   "MSI-X-TX entries enabled through alarm vector\n");
7050                 }
7051         }
7052         if (sp->config.intr_type == INTA) {
7053                 err = request_irq(sp->pdev->irq, s2io_isr, IRQF_SHARED,
7054                                   sp->name, dev);
7055                 if (err) {
7056                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7057                                   dev->name);
7058                         return -1;
7059                 }
7060         }
7061         return 0;
7062 }
7063
7064 static void s2io_rem_isr(struct s2io_nic *sp)
7065 {
7066         if (sp->config.intr_type == MSI_X)
7067                 remove_msix_isr(sp);
7068         else
7069                 remove_inta_isr(sp);
7070 }
7071
7072 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7073 {
7074         int cnt = 0;
7075         struct XENA_dev_config __iomem *bar0 = sp->bar0;
7076         register u64 val64 = 0;
7077         struct config_param *config;
7078         config = &sp->config;
7079
7080         if (!is_s2io_card_up(sp))
7081                 return;
7082
7083         del_timer_sync(&sp->alarm_timer);
7084         /* If s2io_set_link task is executing, wait till it completes. */
7085         while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7086                 msleep(50);
7087         clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7088
7089         /* Disable napi */
7090         if (sp->config.napi) {
7091                 int off = 0;
7092                 if (config->intr_type ==  MSI_X) {
7093                         for (; off < sp->config.rx_ring_num; off++)
7094                                 napi_disable(&sp->mac_control.rings[off].napi);
7095                 }
7096                 else
7097                         napi_disable(&sp->napi);
7098         }
7099
7100         /* disable Tx and Rx traffic on the NIC */
7101         if (do_io)
7102                 stop_nic(sp);
7103
7104         s2io_rem_isr(sp);
7105
7106         /* stop the tx queue, indicate link down */
7107         s2io_link(sp, LINK_DOWN);
7108
7109         /* Check if the device is Quiescent and then Reset the NIC */
7110         while (do_io) {
7111                 /* As per the HW requirement we need to replenish the
7112                  * receive buffer to avoid the ring bump. Since there is
7113                  * no intention of processing the Rx frame at this pointwe are
7114                  * just setting the ownership bit of rxd in Each Rx
7115                  * ring to HW and set the appropriate buffer size
7116                  * based on the ring mode
7117                  */
7118                 rxd_owner_bit_reset(sp);
7119
7120                 val64 = readq(&bar0->adapter_status);
7121                 if (verify_xena_quiescence(sp)) {
7122                         if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7123                                 break;
7124                 }
7125
7126                 msleep(50);
7127                 cnt++;
7128                 if (cnt == 10) {
7129                         DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7130                                   "adapter status reads 0x%llx\n",
7131                                   (unsigned long long)val64);
7132                         break;
7133                 }
7134         }
7135         if (do_io)
7136                 s2io_reset(sp);
7137
7138         /* Free all Tx buffers */
7139         free_tx_buffers(sp);
7140
7141         /* Free all Rx buffers */
7142         free_rx_buffers(sp);
7143
7144         clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7145 }
7146
7147 static void s2io_card_down(struct s2io_nic *sp)
7148 {
7149         do_s2io_card_down(sp, 1);
7150 }
7151
7152 static int s2io_card_up(struct s2io_nic *sp)
7153 {
7154         int i, ret = 0;
7155         struct config_param *config;
7156         struct mac_info *mac_control;
7157         struct net_device *dev = sp->dev;
7158         u16 interruptible;
7159
7160         /* Initialize the H/W I/O registers */
7161         ret = init_nic(sp);
7162         if (ret != 0) {
7163                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7164                           dev->name);
7165                 if (ret != -EIO)
7166                         s2io_reset(sp);
7167                 return ret;
7168         }
7169
7170         /*
7171          * Initializing the Rx buffers. For now we are considering only 1
7172          * Rx ring and initializing buffers into 30 Rx blocks
7173          */
7174         config = &sp->config;
7175         mac_control = &sp->mac_control;
7176
7177         for (i = 0; i < config->rx_ring_num; i++) {
7178                 struct ring_info *ring = &mac_control->rings[i];
7179
7180                 ring->mtu = dev->mtu;
7181                 ring->lro = !!(dev->features & NETIF_F_LRO);
7182                 ret = fill_rx_buffers(sp, ring, 1);
7183                 if (ret) {
7184                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7185                                   dev->name);
7186                         s2io_reset(sp);
7187                         free_rx_buffers(sp);
7188                         return -ENOMEM;
7189                 }
7190                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7191                           ring->rx_bufs_left);
7192         }
7193
7194         /* Initialise napi */
7195         if (config->napi) {
7196                 if (config->intr_type ==  MSI_X) {
7197                         for (i = 0; i < sp->config.rx_ring_num; i++)
7198                                 napi_enable(&sp->mac_control.rings[i].napi);
7199                 } else {
7200                         napi_enable(&sp->napi);
7201                 }
7202         }
7203
7204         /* Maintain the state prior to the open */
7205         if (sp->promisc_flg)
7206                 sp->promisc_flg = 0;
7207         if (sp->m_cast_flg) {
7208                 sp->m_cast_flg = 0;
7209                 sp->all_multi_pos = 0;
7210         }
7211
7212         /* Setting its receive mode */
7213         s2io_set_multicast(dev);
7214
7215         if (dev->features & NETIF_F_LRO) {
7216                 /* Initialize max aggregatable pkts per session based on MTU */
7217                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7218                 /* Check if we can use (if specified) user provided value */
7219                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7220                         sp->lro_max_aggr_per_sess = lro_max_pkts;
7221         }
7222
7223         /* Enable Rx Traffic and interrupts on the NIC */
7224         if (start_nic(sp)) {
7225                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7226                 s2io_reset(sp);
7227                 free_rx_buffers(sp);
7228                 return -ENODEV;
7229         }
7230
7231         /* Add interrupt service routine */
7232         if (s2io_add_isr(sp) != 0) {
7233                 if (sp->config.intr_type == MSI_X)
7234                         s2io_rem_isr(sp);
7235                 s2io_reset(sp);
7236                 free_rx_buffers(sp);
7237                 return -ENODEV;
7238         }
7239
7240         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7241
7242         set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7243
7244         /*  Enable select interrupts */
7245         en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7246         if (sp->config.intr_type != INTA) {
7247                 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7248                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7249         } else {
7250                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7251                 interruptible |= TX_PIC_INTR;
7252                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7253         }
7254
7255         return 0;
7256 }
7257
7258 /**
7259  * s2io_restart_nic - Resets the NIC.
7260  * @data : long pointer to the device private structure
7261  * Description:
7262  * This function is scheduled to be run by the s2io_tx_watchdog
7263  * function after 0.5 secs to reset the NIC. The idea is to reduce
7264  * the run time of the watch dog routine which is run holding a
7265  * spin lock.
7266  */
7267
7268 static void s2io_restart_nic(struct work_struct *work)
7269 {
7270         struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7271         struct net_device *dev = sp->dev;
7272
7273         rtnl_lock();
7274
7275         if (!netif_running(dev))
7276                 goto out_unlock;
7277
7278         s2io_card_down(sp);
7279         if (s2io_card_up(sp)) {
7280                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7281         }
7282         s2io_wake_all_tx_queue(sp);
7283         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7284 out_unlock:
7285         rtnl_unlock();
7286 }
7287
7288 /**
7289  *  s2io_tx_watchdog - Watchdog for transmit side.
7290  *  @dev : Pointer to net device structure
7291  *  Description:
7292  *  This function is triggered if the Tx Queue is stopped
7293  *  for a pre-defined amount of time when the Interface is still up.
7294  *  If the Interface is jammed in such a situation, the hardware is
7295  *  reset (by s2io_close) and restarted again (by s2io_open) to
7296  *  overcome any problem that might have been caused in the hardware.
7297  *  Return value:
7298  *  void
7299  */
7300
7301 static void s2io_tx_watchdog(struct net_device *dev)
7302 {
7303         struct s2io_nic *sp = netdev_priv(dev);
7304         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7305
7306         if (netif_carrier_ok(dev)) {
7307                 swstats->watchdog_timer_cnt++;
7308                 schedule_work(&sp->rst_timer_task);
7309                 swstats->soft_reset_cnt++;
7310         }
7311 }
7312
7313 /**
7314  *   rx_osm_handler - To perform some OS related operations on SKB.
7315  *   @sp: private member of the device structure,pointer to s2io_nic structure.
7316  *   @skb : the socket buffer pointer.
7317  *   @len : length of the packet
7318  *   @cksum : FCS checksum of the frame.
7319  *   @ring_no : the ring from which this RxD was extracted.
7320  *   Description:
7321  *   This function is called by the Rx interrupt serivce routine to perform
7322  *   some OS related operations on the SKB before passing it to the upper
7323  *   layers. It mainly checks if the checksum is OK, if so adds it to the
7324  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
7325  *   to the upper layer. If the checksum is wrong, it increments the Rx
7326  *   packet error count, frees the SKB and returns error.
7327  *   Return value:
7328  *   SUCCESS on success and -1 on failure.
7329  */
7330 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7331 {
7332         struct s2io_nic *sp = ring_data->nic;
7333         struct net_device *dev = ring_data->dev;
7334         struct sk_buff *skb = (struct sk_buff *)
7335                 ((unsigned long)rxdp->Host_Control);
7336         int ring_no = ring_data->ring_no;
7337         u16 l3_csum, l4_csum;
7338         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7339         struct lro *uninitialized_var(lro);
7340         u8 err_mask;
7341         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7342
7343         skb->dev = dev;
7344
7345         if (err) {
7346                 /* Check for parity error */
7347                 if (err & 0x1)
7348                         swstats->parity_err_cnt++;
7349
7350                 err_mask = err >> 48;
7351                 switch (err_mask) {
7352                 case 1:
7353                         swstats->rx_parity_err_cnt++;
7354                         break;
7355
7356                 case 2:
7357                         swstats->rx_abort_cnt++;
7358                         break;
7359
7360                 case 3:
7361                         swstats->rx_parity_abort_cnt++;
7362                         break;
7363
7364                 case 4:
7365                         swstats->rx_rda_fail_cnt++;
7366                         break;
7367
7368                 case 5:
7369                         swstats->rx_unkn_prot_cnt++;
7370                         break;
7371
7372                 case 6:
7373                         swstats->rx_fcs_err_cnt++;
7374                         break;
7375
7376                 case 7:
7377                         swstats->rx_buf_size_err_cnt++;
7378                         break;
7379
7380                 case 8:
7381                         swstats->rx_rxd_corrupt_cnt++;
7382                         break;
7383
7384                 case 15:
7385                         swstats->rx_unkn_err_cnt++;
7386                         break;
7387                 }
7388                 /*
7389                  * Drop the packet if bad transfer code. Exception being
7390                  * 0x5, which could be due to unsupported IPv6 extension header.
7391                  * In this case, we let stack handle the packet.
7392                  * Note that in this case, since checksum will be incorrect,
7393                  * stack will validate the same.
7394                  */
7395                 if (err_mask != 0x5) {
7396                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7397                                   dev->name, err_mask);
7398                         dev->stats.rx_crc_errors++;
7399                         swstats->mem_freed
7400                                 += skb->truesize;
7401                         dev_kfree_skb(skb);
7402                         ring_data->rx_bufs_left -= 1;
7403                         rxdp->Host_Control = 0;
7404                         return 0;
7405                 }
7406         }
7407
7408         rxdp->Host_Control = 0;
7409         if (sp->rxd_mode == RXD_MODE_1) {
7410                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7411
7412                 skb_put(skb, len);
7413         } else if (sp->rxd_mode == RXD_MODE_3B) {
7414                 int get_block = ring_data->rx_curr_get_info.block_index;
7415                 int get_off = ring_data->rx_curr_get_info.offset;
7416                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7417                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7418                 unsigned char *buff = skb_push(skb, buf0_len);
7419
7420                 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7421                 memcpy(buff, ba->ba_0, buf0_len);
7422                 skb_put(skb, buf2_len);
7423         }
7424
7425         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7426             ((!ring_data->lro) ||
7427              (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7428             (dev->features & NETIF_F_RXCSUM)) {
7429                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7430                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7431                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7432                         /*
7433                          * NIC verifies if the Checksum of the received
7434                          * frame is Ok or not and accordingly returns
7435                          * a flag in the RxD.
7436                          */
7437                         skb->ip_summed = CHECKSUM_UNNECESSARY;
7438                         if (ring_data->lro) {
7439                                 u32 tcp_len = 0;
7440                                 u8 *tcp;
7441                                 int ret = 0;
7442
7443                                 ret = s2io_club_tcp_session(ring_data,
7444                                                             skb->data, &tcp,
7445                                                             &tcp_len, &lro,
7446                                                             rxdp, sp);
7447                                 switch (ret) {
7448                                 case 3: /* Begin anew */
7449                                         lro->parent = skb;
7450                                         goto aggregate;
7451                                 case 1: /* Aggregate */
7452                                         lro_append_pkt(sp, lro, skb, tcp_len);
7453                                         goto aggregate;
7454                                 case 4: /* Flush session */
7455                                         lro_append_pkt(sp, lro, skb, tcp_len);
7456                                         queue_rx_frame(lro->parent,
7457                                                        lro->vlan_tag);
7458                                         clear_lro_session(lro);
7459                                         swstats->flush_max_pkts++;
7460                                         goto aggregate;
7461                                 case 2: /* Flush both */
7462                                         lro->parent->data_len = lro->frags_len;
7463                                         swstats->sending_both++;
7464                                         queue_rx_frame(lro->parent,
7465                                                        lro->vlan_tag);
7466                                         clear_lro_session(lro);
7467                                         goto send_up;
7468                                 case 0: /* sessions exceeded */
7469                                 case -1: /* non-TCP or not L2 aggregatable */
7470                                 case 5: /*
7471                                          * First pkt in session not
7472                                          * L3/L4 aggregatable
7473                                          */
7474                                         break;
7475                                 default:
7476                                         DBG_PRINT(ERR_DBG,
7477                                                   "%s: Samadhana!!\n",
7478                                                   __func__);
7479                                         BUG();
7480                                 }
7481                         }
7482                 } else {
7483                         /*
7484                          * Packet with erroneous checksum, let the
7485                          * upper layers deal with it.
7486                          */
7487                         skb_checksum_none_assert(skb);
7488                 }
7489         } else
7490                 skb_checksum_none_assert(skb);
7491
7492         swstats->mem_freed += skb->truesize;
7493 send_up:
7494         skb_record_rx_queue(skb, ring_no);
7495         queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7496 aggregate:
7497         sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7498         return SUCCESS;
7499 }
7500
7501 /**
7502  *  s2io_link - stops/starts the Tx queue.
7503  *  @sp : private member of the device structure, which is a pointer to the
7504  *  s2io_nic structure.
7505  *  @link : inidicates whether link is UP/DOWN.
7506  *  Description:
7507  *  This function stops/starts the Tx queue depending on whether the link
7508  *  status of the NIC is is down or up. This is called by the Alarm
7509  *  interrupt handler whenever a link change interrupt comes up.
7510  *  Return value:
7511  *  void.
7512  */
7513
7514 static void s2io_link(struct s2io_nic *sp, int link)
7515 {
7516         struct net_device *dev = sp->dev;
7517         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7518
7519         if (link != sp->last_link_state) {
7520                 init_tti(sp, link);
7521                 if (link == LINK_DOWN) {
7522                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7523                         s2io_stop_all_tx_queue(sp);
7524                         netif_carrier_off(dev);
7525                         if (swstats->link_up_cnt)
7526                                 swstats->link_up_time =
7527                                         jiffies - sp->start_time;
7528                         swstats->link_down_cnt++;
7529                 } else {
7530                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7531                         if (swstats->link_down_cnt)
7532                                 swstats->link_down_time =
7533                                         jiffies - sp->start_time;
7534                         swstats->link_up_cnt++;
7535                         netif_carrier_on(dev);
7536                         s2io_wake_all_tx_queue(sp);
7537                 }
7538         }
7539         sp->last_link_state = link;
7540         sp->start_time = jiffies;
7541 }
7542
7543 /**
7544  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7545  *  @sp : private member of the device structure, which is a pointer to the
7546  *  s2io_nic structure.
7547  *  Description:
7548  *  This function initializes a few of the PCI and PCI-X configuration registers
7549  *  with recommended values.
7550  *  Return value:
7551  *  void
7552  */
7553
7554 static void s2io_init_pci(struct s2io_nic *sp)
7555 {
7556         u16 pci_cmd = 0, pcix_cmd = 0;
7557
7558         /* Enable Data Parity Error Recovery in PCI-X command register. */
7559         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7560                              &(pcix_cmd));
7561         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7562                               (pcix_cmd | 1));
7563         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7564                              &(pcix_cmd));
7565
7566         /* Set the PErr Response bit in PCI command register. */
7567         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7568         pci_write_config_word(sp->pdev, PCI_COMMAND,
7569                               (pci_cmd | PCI_COMMAND_PARITY));
7570         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7571 }
7572
7573 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7574                             u8 *dev_multiq)
7575 {
7576         int i;
7577
7578         if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7579                 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7580                           "(%d) not supported\n", tx_fifo_num);
7581
7582                 if (tx_fifo_num < 1)
7583                         tx_fifo_num = 1;
7584                 else
7585                         tx_fifo_num = MAX_TX_FIFOS;
7586
7587                 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7588         }
7589
7590         if (multiq)
7591                 *dev_multiq = multiq;
7592
7593         if (tx_steering_type && (1 == tx_fifo_num)) {
7594                 if (tx_steering_type != TX_DEFAULT_STEERING)
7595                         DBG_PRINT(ERR_DBG,
7596                                   "Tx steering is not supported with "
7597                                   "one fifo. Disabling Tx steering.\n");
7598                 tx_steering_type = NO_STEERING;
7599         }
7600
7601         if ((tx_steering_type < NO_STEERING) ||
7602             (tx_steering_type > TX_DEFAULT_STEERING)) {
7603                 DBG_PRINT(ERR_DBG,
7604                           "Requested transmit steering not supported\n");
7605                 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7606                 tx_steering_type = NO_STEERING;
7607         }
7608
7609         if (rx_ring_num > MAX_RX_RINGS) {
7610                 DBG_PRINT(ERR_DBG,
7611                           "Requested number of rx rings not supported\n");
7612                 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7613                           MAX_RX_RINGS);
7614                 rx_ring_num = MAX_RX_RINGS;
7615         }
7616
7617         if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7618                 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7619                           "Defaulting to INTA\n");
7620                 *dev_intr_type = INTA;
7621         }
7622
7623         if ((*dev_intr_type == MSI_X) &&
7624             ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7625              (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7626                 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7627                           "Defaulting to INTA\n");
7628                 *dev_intr_type = INTA;
7629         }
7630
7631         if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7632                 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7633                 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7634                 rx_ring_mode = 1;
7635         }
7636
7637         for (i = 0; i < MAX_RX_RINGS; i++)
7638                 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7639                         DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7640                                   "supported\nDefaulting to %d\n",
7641                                   MAX_RX_BLOCKS_PER_RING);
7642                         rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7643                 }
7644
7645         return SUCCESS;
7646 }
7647
7648 /**
7649  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7650  * or Traffic class respectively.
7651  * @nic: device private variable
7652  * Description: The function configures the receive steering to
7653  * desired receive ring.
7654  * Return Value:  SUCCESS on success and
7655  * '-1' on failure (endian settings incorrect).
7656  */
7657 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7658 {
7659         struct XENA_dev_config __iomem *bar0 = nic->bar0;
7660         register u64 val64 = 0;
7661
7662         if (ds_codepoint > 63)
7663                 return FAILURE;
7664
7665         val64 = RTS_DS_MEM_DATA(ring);
7666         writeq(val64, &bar0->rts_ds_mem_data);
7667
7668         val64 = RTS_DS_MEM_CTRL_WE |
7669                 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7670                 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7671
7672         writeq(val64, &bar0->rts_ds_mem_ctrl);
7673
7674         return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7675                                      RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7676                                      S2IO_BIT_RESET);
7677 }
7678
7679 static const struct net_device_ops s2io_netdev_ops = {
7680         .ndo_open               = s2io_open,
7681         .ndo_stop               = s2io_close,
7682         .ndo_get_stats          = s2io_get_stats,
7683         .ndo_start_xmit         = s2io_xmit,
7684         .ndo_validate_addr      = eth_validate_addr,
7685         .ndo_set_rx_mode        = s2io_set_multicast,
7686         .ndo_do_ioctl           = s2io_ioctl,
7687         .ndo_set_mac_address    = s2io_set_mac_addr,
7688         .ndo_change_mtu         = s2io_change_mtu,
7689         .ndo_set_features       = s2io_set_features,
7690         .ndo_tx_timeout         = s2io_tx_watchdog,
7691 #ifdef CONFIG_NET_POLL_CONTROLLER
7692         .ndo_poll_controller    = s2io_netpoll,
7693 #endif
7694 };
7695
7696 /**
7697  *  s2io_init_nic - Initialization of the adapter .
7698  *  @pdev : structure containing the PCI related information of the device.
7699  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7700  *  Description:
7701  *  The function initializes an adapter identified by the pci_dec structure.
7702  *  All OS related initialization including memory and device structure and
7703  *  initlaization of the device private variable is done. Also the swapper
7704  *  control register is initialized to enable read and write into the I/O
7705  *  registers of the device.
7706  *  Return value:
7707  *  returns 0 on success and negative on failure.
7708  */
7709
7710 static int
7711 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7712 {
7713         struct s2io_nic *sp;
7714         struct net_device *dev;
7715         int i, j, ret;
7716         int dma_flag = false;
7717         u32 mac_up, mac_down;
7718         u64 val64 = 0, tmp64 = 0;
7719         struct XENA_dev_config __iomem *bar0 = NULL;
7720         u16 subid;
7721         struct config_param *config;
7722         struct mac_info *mac_control;
7723         int mode;
7724         u8 dev_intr_type = intr_type;
7725         u8 dev_multiq = 0;
7726
7727         ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7728         if (ret)
7729                 return ret;
7730
7731         ret = pci_enable_device(pdev);
7732         if (ret) {
7733                 DBG_PRINT(ERR_DBG,
7734                           "%s: pci_enable_device failed\n", __func__);
7735                 return ret;
7736         }
7737
7738         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7739                 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7740                 dma_flag = true;
7741                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7742                         DBG_PRINT(ERR_DBG,
7743                                   "Unable to obtain 64bit DMA "
7744                                   "for consistent allocations\n");
7745                         pci_disable_device(pdev);
7746                         return -ENOMEM;
7747                 }
7748         } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7749                 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7750         } else {
7751                 pci_disable_device(pdev);
7752                 return -ENOMEM;
7753         }
7754         ret = pci_request_regions(pdev, s2io_driver_name);
7755         if (ret) {
7756                 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7757                           __func__, ret);
7758                 pci_disable_device(pdev);
7759                 return -ENODEV;
7760         }
7761         if (dev_multiq)
7762                 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7763         else
7764                 dev = alloc_etherdev(sizeof(struct s2io_nic));
7765         if (dev == NULL) {
7766                 pci_disable_device(pdev);
7767                 pci_release_regions(pdev);
7768                 return -ENODEV;
7769         }
7770
7771         pci_set_master(pdev);
7772         pci_set_drvdata(pdev, dev);
7773         SET_NETDEV_DEV(dev, &pdev->dev);
7774
7775         /*  Private member variable initialized to s2io NIC structure */
7776         sp = netdev_priv(dev);
7777         sp->dev = dev;
7778         sp->pdev = pdev;
7779         sp->high_dma_flag = dma_flag;
7780         sp->device_enabled_once = false;
7781         if (rx_ring_mode == 1)
7782                 sp->rxd_mode = RXD_MODE_1;
7783         if (rx_ring_mode == 2)
7784                 sp->rxd_mode = RXD_MODE_3B;
7785
7786         sp->config.intr_type = dev_intr_type;
7787
7788         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7789             (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7790                 sp->device_type = XFRAME_II_DEVICE;
7791         else
7792                 sp->device_type = XFRAME_I_DEVICE;
7793
7794
7795         /* Initialize some PCI/PCI-X fields of the NIC. */
7796         s2io_init_pci(sp);
7797
7798         /*
7799          * Setting the device configuration parameters.
7800          * Most of these parameters can be specified by the user during
7801          * module insertion as they are module loadable parameters. If
7802          * these parameters are not not specified during load time, they
7803          * are initialized with default values.
7804          */
7805         config = &sp->config;
7806         mac_control = &sp->mac_control;
7807
7808         config->napi = napi;
7809         config->tx_steering_type = tx_steering_type;
7810
7811         /* Tx side parameters. */
7812         if (config->tx_steering_type == TX_PRIORITY_STEERING)
7813                 config->tx_fifo_num = MAX_TX_FIFOS;
7814         else
7815                 config->tx_fifo_num = tx_fifo_num;
7816
7817         /* Initialize the fifos used for tx steering */
7818         if (config->tx_fifo_num < 5) {
7819                 if (config->tx_fifo_num  == 1)
7820                         sp->total_tcp_fifos = 1;
7821                 else
7822                         sp->total_tcp_fifos = config->tx_fifo_num - 1;
7823                 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7824                 sp->total_udp_fifos = 1;
7825                 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7826         } else {
7827                 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7828                                        FIFO_OTHER_MAX_NUM);
7829                 sp->udp_fifo_idx = sp->total_tcp_fifos;
7830                 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7831                 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7832         }
7833
7834         config->multiq = dev_multiq;
7835         for (i = 0; i < config->tx_fifo_num; i++) {
7836                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7837
7838                 tx_cfg->fifo_len = tx_fifo_len[i];
7839                 tx_cfg->fifo_priority = i;
7840         }
7841
7842         /* mapping the QoS priority to the configured fifos */
7843         for (i = 0; i < MAX_TX_FIFOS; i++)
7844                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7845
7846         /* map the hashing selector table to the configured fifos */
7847         for (i = 0; i < config->tx_fifo_num; i++)
7848                 sp->fifo_selector[i] = fifo_selector[i];
7849
7850
7851         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7852         for (i = 0; i < config->tx_fifo_num; i++) {
7853                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7854
7855                 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7856                 if (tx_cfg->fifo_len < 65) {
7857                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7858                         break;
7859                 }
7860         }
7861         /* + 2 because one Txd for skb->data and one Txd for UFO */
7862         config->max_txds = MAX_SKB_FRAGS + 2;
7863
7864         /* Rx side parameters. */
7865         config->rx_ring_num = rx_ring_num;
7866         for (i = 0; i < config->rx_ring_num; i++) {
7867                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7868                 struct ring_info *ring = &mac_control->rings[i];
7869
7870                 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7871                 rx_cfg->ring_priority = i;
7872                 ring->rx_bufs_left = 0;
7873                 ring->rxd_mode = sp->rxd_mode;
7874                 ring->rxd_count = rxd_count[sp->rxd_mode];
7875                 ring->pdev = sp->pdev;
7876                 ring->dev = sp->dev;
7877         }
7878
7879         for (i = 0; i < rx_ring_num; i++) {
7880                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7881
7882                 rx_cfg->ring_org = RING_ORG_BUFF1;
7883                 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7884         }
7885
7886         /*  Setting Mac Control parameters */
7887         mac_control->rmac_pause_time = rmac_pause_time;
7888         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7889         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7890
7891
7892         /*  initialize the shared memory used by the NIC and the host */
7893         if (init_shared_mem(sp)) {
7894                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7895                 ret = -ENOMEM;
7896                 goto mem_alloc_failed;
7897         }
7898
7899         sp->bar0 = pci_ioremap_bar(pdev, 0);
7900         if (!sp->bar0) {
7901                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7902                           dev->name);
7903                 ret = -ENOMEM;
7904                 goto bar0_remap_failed;
7905         }
7906
7907         sp->bar1 = pci_ioremap_bar(pdev, 2);
7908         if (!sp->bar1) {
7909                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7910                           dev->name);
7911                 ret = -ENOMEM;
7912                 goto bar1_remap_failed;
7913         }
7914
7915         /* Initializing the BAR1 address as the start of the FIFO pointer. */
7916         for (j = 0; j < MAX_TX_FIFOS; j++) {
7917                 mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000);
7918         }
7919
7920         /*  Driver entry points */
7921         dev->netdev_ops = &s2io_netdev_ops;
7922         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7923         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7924                 NETIF_F_TSO | NETIF_F_TSO6 |
7925                 NETIF_F_RXCSUM | NETIF_F_LRO;
7926         dev->features |= dev->hw_features |
7927                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7928         if (sp->device_type & XFRAME_II_DEVICE) {
7929                 dev->hw_features |= NETIF_F_UFO;
7930                 if (ufo)
7931                         dev->features |= NETIF_F_UFO;
7932         }
7933         if (sp->high_dma_flag == true)
7934                 dev->features |= NETIF_F_HIGHDMA;
7935         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7936         INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7937         INIT_WORK(&sp->set_link_task, s2io_set_link);
7938
7939         pci_save_state(sp->pdev);
7940
7941         /* Setting swapper control on the NIC, for proper reset operation */
7942         if (s2io_set_swapper(sp)) {
7943                 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7944                           dev->name);
7945                 ret = -EAGAIN;
7946                 goto set_swap_failed;
7947         }
7948
7949         /* Verify if the Herc works on the slot its placed into */
7950         if (sp->device_type & XFRAME_II_DEVICE) {
7951                 mode = s2io_verify_pci_mode(sp);
7952                 if (mode < 0) {
7953                         DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
7954                                   __func__);
7955                         ret = -EBADSLT;
7956                         goto set_swap_failed;
7957                 }
7958         }
7959
7960         if (sp->config.intr_type == MSI_X) {
7961                 sp->num_entries = config->rx_ring_num + 1;
7962                 ret = s2io_enable_msi_x(sp);
7963
7964                 if (!ret) {
7965                         ret = s2io_test_msi(sp);
7966                         /* rollback MSI-X, will re-enable during add_isr() */
7967                         remove_msix_isr(sp);
7968                 }
7969                 if (ret) {
7970
7971                         DBG_PRINT(ERR_DBG,
7972                                   "MSI-X requested but failed to enable\n");
7973                         sp->config.intr_type = INTA;
7974                 }
7975         }
7976
7977         if (config->intr_type ==  MSI_X) {
7978                 for (i = 0; i < config->rx_ring_num ; i++) {
7979                         struct ring_info *ring = &mac_control->rings[i];
7980
7981                         netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
7982                 }
7983         } else {
7984                 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
7985         }
7986
7987         /* Not needed for Herc */
7988         if (sp->device_type & XFRAME_I_DEVICE) {
7989                 /*
7990                  * Fix for all "FFs" MAC address problems observed on
7991                  * Alpha platforms
7992                  */
7993                 fix_mac_address(sp);
7994                 s2io_reset(sp);
7995         }
7996
7997         /*
7998          * MAC address initialization.
7999          * For now only one mac address will be read and used.
8000          */
8001         bar0 = sp->bar0;
8002         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8003                 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8004         writeq(val64, &bar0->rmac_addr_cmd_mem);
8005         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8006                               RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8007                               S2IO_BIT_RESET);
8008         tmp64 = readq(&bar0->rmac_addr_data0_mem);
8009         mac_down = (u32)tmp64;
8010         mac_up = (u32) (tmp64 >> 32);
8011
8012         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8013         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8014         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8015         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8016         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8017         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8018
8019         /*  Set the factory defined MAC address initially   */
8020         dev->addr_len = ETH_ALEN;
8021         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8022
8023         /* initialize number of multicast & unicast MAC entries variables */
8024         if (sp->device_type == XFRAME_I_DEVICE) {
8025                 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8026                 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8027                 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8028         } else if (sp->device_type == XFRAME_II_DEVICE) {
8029                 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8030                 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8031                 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8032         }
8033
8034         /* store mac addresses from CAM to s2io_nic structure */
8035         do_s2io_store_unicast_mc(sp);
8036
8037         /* Configure MSIX vector for number of rings configured plus one */
8038         if ((sp->device_type == XFRAME_II_DEVICE) &&
8039             (config->intr_type == MSI_X))
8040                 sp->num_entries = config->rx_ring_num + 1;
8041
8042         /* Store the values of the MSIX table in the s2io_nic structure */
8043         store_xmsi_data(sp);
8044         /* reset Nic and bring it to known state */
8045         s2io_reset(sp);
8046
8047         /*
8048          * Initialize link state flags
8049          * and the card state parameter
8050          */
8051         sp->state = 0;
8052
8053         /* Initialize spinlocks */
8054         for (i = 0; i < sp->config.tx_fifo_num; i++) {
8055                 struct fifo_info *fifo = &mac_control->fifos[i];
8056
8057                 spin_lock_init(&fifo->tx_lock);
8058         }
8059
8060         /*
8061          * SXE-002: Configure link and activity LED to init state
8062          * on driver load.
8063          */
8064         subid = sp->pdev->subsystem_device;
8065         if ((subid & 0xFF) >= 0x07) {
8066                 val64 = readq(&bar0->gpio_control);
8067                 val64 |= 0x0000800000000000ULL;
8068                 writeq(val64, &bar0->gpio_control);
8069                 val64 = 0x0411040400000000ULL;
8070                 writeq(val64, (void __iomem *)bar0 + 0x2700);
8071                 val64 = readq(&bar0->gpio_control);
8072         }
8073
8074         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
8075
8076         if (register_netdev(dev)) {
8077                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8078                 ret = -ENODEV;
8079                 goto register_failed;
8080         }
8081         s2io_vpd_read(sp);
8082         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8083         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8084                   sp->product_name, pdev->revision);
8085         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8086                   s2io_driver_version);
8087         DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8088         DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8089         if (sp->device_type & XFRAME_II_DEVICE) {
8090                 mode = s2io_print_pci_mode(sp);
8091                 if (mode < 0) {
8092                         ret = -EBADSLT;
8093                         unregister_netdev(dev);
8094                         goto set_swap_failed;
8095                 }
8096         }
8097         switch (sp->rxd_mode) {
8098         case RXD_MODE_1:
8099                 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8100                           dev->name);
8101                 break;
8102         case RXD_MODE_3B:
8103                 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8104                           dev->name);
8105                 break;
8106         }
8107
8108         switch (sp->config.napi) {
8109         case 0:
8110                 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8111                 break;
8112         case 1:
8113                 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8114                 break;
8115         }
8116
8117         DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8118                   sp->config.tx_fifo_num);
8119
8120         DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8121                   sp->config.rx_ring_num);
8122
8123         switch (sp->config.intr_type) {
8124         case INTA:
8125                 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8126                 break;
8127         case MSI_X:
8128                 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8129                 break;
8130         }
8131         if (sp->config.multiq) {
8132                 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8133                         struct fifo_info *fifo = &mac_control->fifos[i];
8134
8135                         fifo->multiq = config->multiq;
8136                 }
8137                 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8138                           dev->name);
8139         } else
8140                 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8141                           dev->name);
8142
8143         switch (sp->config.tx_steering_type) {
8144         case NO_STEERING:
8145                 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8146                           dev->name);
8147                 break;
8148         case TX_PRIORITY_STEERING:
8149                 DBG_PRINT(ERR_DBG,
8150                           "%s: Priority steering enabled for transmit\n",
8151                           dev->name);
8152                 break;
8153         case TX_DEFAULT_STEERING:
8154                 DBG_PRINT(ERR_DBG,
8155                           "%s: Default steering enabled for transmit\n",
8156                           dev->name);
8157         }
8158
8159         DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8160                   dev->name);
8161         if (ufo)
8162                 DBG_PRINT(ERR_DBG,
8163                           "%s: UDP Fragmentation Offload(UFO) enabled\n",
8164                           dev->name);
8165         /* Initialize device name */
8166         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8167
8168         if (vlan_tag_strip)
8169                 sp->vlan_strip_flag = 1;
8170         else
8171                 sp->vlan_strip_flag = 0;
8172
8173         /*
8174          * Make Link state as off at this point, when the Link change
8175          * interrupt comes the state will be automatically changed to
8176          * the right state.
8177          */
8178         netif_carrier_off(dev);
8179
8180         return 0;
8181
8182 register_failed:
8183 set_swap_failed:
8184         iounmap(sp->bar1);
8185 bar1_remap_failed:
8186         iounmap(sp->bar0);
8187 bar0_remap_failed:
8188 mem_alloc_failed:
8189         free_shared_mem(sp);
8190         pci_disable_device(pdev);
8191         pci_release_regions(pdev);
8192         free_netdev(dev);
8193
8194         return ret;
8195 }
8196
8197 /**
8198  * s2io_rem_nic - Free the PCI device
8199  * @pdev: structure containing the PCI related information of the device.
8200  * Description: This function is called by the Pci subsystem to release a
8201  * PCI device and free up all resource held up by the device. This could
8202  * be in response to a Hot plug event or when the driver is to be removed
8203  * from memory.
8204  */
8205
8206 static void s2io_rem_nic(struct pci_dev *pdev)
8207 {
8208         struct net_device *dev = pci_get_drvdata(pdev);
8209         struct s2io_nic *sp;
8210
8211         if (dev == NULL) {
8212                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8213                 return;
8214         }
8215
8216         sp = netdev_priv(dev);
8217
8218         cancel_work_sync(&sp->rst_timer_task);
8219         cancel_work_sync(&sp->set_link_task);
8220
8221         unregister_netdev(dev);
8222
8223         free_shared_mem(sp);
8224         iounmap(sp->bar0);
8225         iounmap(sp->bar1);
8226         pci_release_regions(pdev);
8227         free_netdev(dev);
8228         pci_disable_device(pdev);
8229 }
8230
8231 /**
8232  * s2io_starter - Entry point for the driver
8233  * Description: This function is the entry point for the driver. It verifies
8234  * the module loadable parameters and initializes PCI configuration space.
8235  */
8236
8237 static int __init s2io_starter(void)
8238 {
8239         return pci_register_driver(&s2io_driver);
8240 }
8241
8242 /**
8243  * s2io_closer - Cleanup routine for the driver
8244  * Description: This function is the cleanup routine for the driver. It
8245  * unregisters the driver.
8246  */
8247
8248 static __exit void s2io_closer(void)
8249 {
8250         pci_unregister_driver(&s2io_driver);
8251         DBG_PRINT(INIT_DBG, "cleanup done\n");
8252 }
8253
8254 module_init(s2io_starter);
8255 module_exit(s2io_closer);
8256
8257 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8258                                 struct tcphdr **tcp, struct RxD_t *rxdp,
8259                                 struct s2io_nic *sp)
8260 {
8261         int ip_off;
8262         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8263
8264         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8265                 DBG_PRINT(INIT_DBG,
8266                           "%s: Non-TCP frames not supported for LRO\n",
8267                           __func__);
8268                 return -1;
8269         }
8270
8271         /* Checking for DIX type or DIX type with VLAN */
8272         if ((l2_type == 0) || (l2_type == 4)) {
8273                 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8274                 /*
8275                  * If vlan stripping is disabled and the frame is VLAN tagged,
8276                  * shift the offset by the VLAN header size bytes.
8277                  */
8278                 if ((!sp->vlan_strip_flag) &&
8279                     (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8280                         ip_off += HEADER_VLAN_SIZE;
8281         } else {
8282                 /* LLC, SNAP etc are considered non-mergeable */
8283                 return -1;
8284         }
8285
8286         *ip = (struct iphdr *)(buffer + ip_off);
8287         ip_len = (u8)((*ip)->ihl);
8288         ip_len <<= 2;
8289         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8290
8291         return 0;
8292 }
8293
8294 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8295                                   struct tcphdr *tcp)
8296 {
8297         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8298         if ((lro->iph->saddr != ip->saddr) ||
8299             (lro->iph->daddr != ip->daddr) ||
8300             (lro->tcph->source != tcp->source) ||
8301             (lro->tcph->dest != tcp->dest))
8302                 return -1;
8303         return 0;
8304 }
8305
8306 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8307 {
8308         return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8309 }
8310
8311 static void initiate_new_session(struct lro *lro, u8 *l2h,
8312                                  struct iphdr *ip, struct tcphdr *tcp,
8313                                  u32 tcp_pyld_len, u16 vlan_tag)
8314 {
8315         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8316         lro->l2h = l2h;
8317         lro->iph = ip;
8318         lro->tcph = tcp;
8319         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8320         lro->tcp_ack = tcp->ack_seq;
8321         lro->sg_num = 1;
8322         lro->total_len = ntohs(ip->tot_len);
8323         lro->frags_len = 0;
8324         lro->vlan_tag = vlan_tag;
8325         /*
8326          * Check if we saw TCP timestamp.
8327          * Other consistency checks have already been done.
8328          */
8329         if (tcp->doff == 8) {
8330                 __be32 *ptr;
8331                 ptr = (__be32 *)(tcp+1);
8332                 lro->saw_ts = 1;
8333                 lro->cur_tsval = ntohl(*(ptr+1));
8334                 lro->cur_tsecr = *(ptr+2);
8335         }
8336         lro->in_use = 1;
8337 }
8338
8339 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8340 {
8341         struct iphdr *ip = lro->iph;
8342         struct tcphdr *tcp = lro->tcph;
8343         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8344
8345         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8346
8347         /* Update L3 header */
8348         csum_replace2(&ip->check, ip->tot_len, htons(lro->total_len));
8349         ip->tot_len = htons(lro->total_len);
8350
8351         /* Update L4 header */
8352         tcp->ack_seq = lro->tcp_ack;
8353         tcp->window = lro->window;
8354
8355         /* Update tsecr field if this session has timestamps enabled */
8356         if (lro->saw_ts) {
8357                 __be32 *ptr = (__be32 *)(tcp + 1);
8358                 *(ptr+2) = lro->cur_tsecr;
8359         }
8360
8361         /* Update counters required for calculation of
8362          * average no. of packets aggregated.
8363          */
8364         swstats->sum_avg_pkts_aggregated += lro->sg_num;
8365         swstats->num_aggregations++;
8366 }
8367
8368 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8369                              struct tcphdr *tcp, u32 l4_pyld)
8370 {
8371         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8372         lro->total_len += l4_pyld;
8373         lro->frags_len += l4_pyld;
8374         lro->tcp_next_seq += l4_pyld;
8375         lro->sg_num++;
8376
8377         /* Update ack seq no. and window ad(from this pkt) in LRO object */
8378         lro->tcp_ack = tcp->ack_seq;
8379         lro->window = tcp->window;
8380
8381         if (lro->saw_ts) {
8382                 __be32 *ptr;
8383                 /* Update tsecr and tsval from this packet */
8384                 ptr = (__be32 *)(tcp+1);
8385                 lro->cur_tsval = ntohl(*(ptr+1));
8386                 lro->cur_tsecr = *(ptr + 2);
8387         }
8388 }
8389
8390 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8391                                     struct tcphdr *tcp, u32 tcp_pyld_len)
8392 {
8393         u8 *ptr;
8394
8395         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8396
8397         if (!tcp_pyld_len) {
8398                 /* Runt frame or a pure ack */
8399                 return -1;
8400         }
8401
8402         if (ip->ihl != 5) /* IP has options */
8403                 return -1;
8404
8405         /* If we see CE codepoint in IP header, packet is not mergeable */
8406         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8407                 return -1;
8408
8409         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8410         if (tcp->urg || tcp->psh || tcp->rst ||
8411             tcp->syn || tcp->fin ||
8412             tcp->ece || tcp->cwr || !tcp->ack) {
8413                 /*
8414                  * Currently recognize only the ack control word and
8415                  * any other control field being set would result in
8416                  * flushing the LRO session
8417                  */
8418                 return -1;
8419         }
8420
8421         /*
8422          * Allow only one TCP timestamp option. Don't aggregate if
8423          * any other options are detected.
8424          */
8425         if (tcp->doff != 5 && tcp->doff != 8)
8426                 return -1;
8427
8428         if (tcp->doff == 8) {
8429                 ptr = (u8 *)(tcp + 1);
8430                 while (*ptr == TCPOPT_NOP)
8431                         ptr++;
8432                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8433                         return -1;
8434
8435                 /* Ensure timestamp value increases monotonically */
8436                 if (l_lro)
8437                         if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8438                                 return -1;
8439
8440                 /* timestamp echo reply should be non-zero */
8441                 if (*((__be32 *)(ptr+6)) == 0)
8442                         return -1;
8443         }
8444
8445         return 0;
8446 }
8447
8448 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8449                                  u8 **tcp, u32 *tcp_len, struct lro **lro,
8450                                  struct RxD_t *rxdp, struct s2io_nic *sp)
8451 {
8452         struct iphdr *ip;
8453         struct tcphdr *tcph;
8454         int ret = 0, i;
8455         u16 vlan_tag = 0;
8456         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8457
8458         ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8459                                    rxdp, sp);
8460         if (ret)
8461                 return ret;
8462
8463         DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8464
8465         vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8466         tcph = (struct tcphdr *)*tcp;
8467         *tcp_len = get_l4_pyld_length(ip, tcph);
8468         for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8469                 struct lro *l_lro = &ring_data->lro0_n[i];
8470                 if (l_lro->in_use) {
8471                         if (check_for_socket_match(l_lro, ip, tcph))
8472                                 continue;
8473                         /* Sock pair matched */
8474                         *lro = l_lro;
8475
8476                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8477                                 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8478                                           "expected 0x%x, actual 0x%x\n",
8479                                           __func__,
8480                                           (*lro)->tcp_next_seq,
8481                                           ntohl(tcph->seq));
8482
8483                                 swstats->outof_sequence_pkts++;
8484                                 ret = 2;
8485                                 break;
8486                         }
8487
8488                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8489                                                       *tcp_len))
8490                                 ret = 1; /* Aggregate */
8491                         else
8492                                 ret = 2; /* Flush both */
8493                         break;
8494                 }
8495         }
8496
8497         if (ret == 0) {
8498                 /* Before searching for available LRO objects,
8499                  * check if the pkt is L3/L4 aggregatable. If not
8500                  * don't create new LRO session. Just send this
8501                  * packet up.
8502                  */
8503                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8504                         return 5;
8505
8506                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8507                         struct lro *l_lro = &ring_data->lro0_n[i];
8508                         if (!(l_lro->in_use)) {
8509                                 *lro = l_lro;
8510                                 ret = 3; /* Begin anew */
8511                                 break;
8512                         }
8513                 }
8514         }
8515
8516         if (ret == 0) { /* sessions exceeded */
8517                 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8518                           __func__);
8519                 *lro = NULL;
8520                 return ret;
8521         }
8522
8523         switch (ret) {
8524         case 3:
8525                 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8526                                      vlan_tag);
8527                 break;
8528         case 2:
8529                 update_L3L4_header(sp, *lro);
8530                 break;
8531         case 1:
8532                 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8533                 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8534                         update_L3L4_header(sp, *lro);
8535                         ret = 4; /* Flush the LRO */
8536                 }
8537                 break;
8538         default:
8539                 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8540                 break;
8541         }
8542
8543         return ret;
8544 }
8545
8546 static void clear_lro_session(struct lro *lro)
8547 {
8548         static u16 lro_struct_size = sizeof(struct lro);
8549
8550         memset(lro, 0, lro_struct_size);
8551 }
8552
8553 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8554 {
8555         struct net_device *dev = skb->dev;
8556         struct s2io_nic *sp = netdev_priv(dev);
8557
8558         skb->protocol = eth_type_trans(skb, dev);
8559         if (vlan_tag && sp->vlan_strip_flag)
8560                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
8561         if (sp->config.napi)
8562                 netif_receive_skb(skb);
8563         else
8564                 netif_rx(skb);
8565 }
8566
8567 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8568                            struct sk_buff *skb, u32 tcp_len)
8569 {
8570         struct sk_buff *first = lro->parent;
8571         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8572
8573         first->len += tcp_len;
8574         first->data_len = lro->frags_len;
8575         skb_pull(skb, (skb->len - tcp_len));
8576         if (skb_shinfo(first)->frag_list)
8577                 lro->last_frag->next = skb;
8578         else
8579                 skb_shinfo(first)->frag_list = skb;
8580         first->truesize += skb->truesize;
8581         lro->last_frag = skb;
8582         swstats->clubbed_frms_cnt++;
8583 }
8584
8585 /**
8586  * s2io_io_error_detected - called when PCI error is detected
8587  * @pdev: Pointer to PCI device
8588  * @state: The current pci connection state
8589  *
8590  * This function is called after a PCI bus error affecting
8591  * this device has been detected.
8592  */
8593 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8594                                                pci_channel_state_t state)
8595 {
8596         struct net_device *netdev = pci_get_drvdata(pdev);
8597         struct s2io_nic *sp = netdev_priv(netdev);
8598
8599         netif_device_detach(netdev);
8600
8601         if (state == pci_channel_io_perm_failure)
8602                 return PCI_ERS_RESULT_DISCONNECT;
8603
8604         if (netif_running(netdev)) {
8605                 /* Bring down the card, while avoiding PCI I/O */
8606                 do_s2io_card_down(sp, 0);
8607         }
8608         pci_disable_device(pdev);
8609
8610         return PCI_ERS_RESULT_NEED_RESET;
8611 }
8612
8613 /**
8614  * s2io_io_slot_reset - called after the pci bus has been reset.
8615  * @pdev: Pointer to PCI device
8616  *
8617  * Restart the card from scratch, as if from a cold-boot.
8618  * At this point, the card has exprienced a hard reset,
8619  * followed by fixups by BIOS, and has its config space
8620  * set up identically to what it was at cold boot.
8621  */
8622 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8623 {
8624         struct net_device *netdev = pci_get_drvdata(pdev);
8625         struct s2io_nic *sp = netdev_priv(netdev);
8626
8627         if (pci_enable_device(pdev)) {
8628                 pr_err("Cannot re-enable PCI device after reset.\n");
8629                 return PCI_ERS_RESULT_DISCONNECT;
8630         }
8631
8632         pci_set_master(pdev);
8633         s2io_reset(sp);
8634
8635         return PCI_ERS_RESULT_RECOVERED;
8636 }
8637
8638 /**
8639  * s2io_io_resume - called when traffic can start flowing again.
8640  * @pdev: Pointer to PCI device
8641  *
8642  * This callback is called when the error recovery driver tells
8643  * us that its OK to resume normal operation.
8644  */
8645 static void s2io_io_resume(struct pci_dev *pdev)
8646 {
8647         struct net_device *netdev = pci_get_drvdata(pdev);
8648         struct s2io_nic *sp = netdev_priv(netdev);
8649
8650         if (netif_running(netdev)) {
8651                 if (s2io_card_up(sp)) {
8652                         pr_err("Can't bring device back up after reset.\n");
8653                         return;
8654                 }
8655
8656                 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8657                         s2io_card_down(sp);
8658                         pr_err("Can't restore mac addr after reset.\n");
8659                         return;
8660                 }
8661         }
8662
8663         netif_device_attach(netdev);
8664         netif_tx_wake_all_queues(netdev);
8665 }