1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2010 Exar Corp.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_max_pkts: This parameter defines maximum number of packets can be
42 * aggregated as a single large packet
43 * napi: This parameter used to enable/disable NAPI (polling Rx)
44 * Possible values '1' for enable and '0' for disable. Default is '1'
45 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46 * Possible values '1' for enable and '0' for disable. Default is '0'
47 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48 * Possible values '1' for enable , '0' for disable.
49 * Default is '2' - which means disable in promisc mode
50 * and enable in non-promiscuous mode.
51 * multiq: This parameter used to enable/disable MULTIQUEUE support.
52 * Possible values '1' for enable and '0' for disable. Default is '0'
53 ************************************************************************/
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
77 #include <linux/tcp.h>
78 #include <linux/uaccess.h>
80 #include <linux/slab.h>
81 #include <linux/prefetch.h>
83 #include <net/checksum.h>
85 #include <asm/div64.h>
90 #include "s2io-regs.h"
92 #define DRV_VERSION "2.0.26.28"
94 /* S2io Driver name & version. */
95 static const char s2io_driver_name[] = "Neterion";
96 static const char s2io_driver_version[] = DRV_VERSION;
98 static const int rxd_size[2] = {32, 48};
99 static const int rxd_count[2] = {127, 85};
101 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
105 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
106 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
112 * Cards with following subsystem_id have a link state indication
113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114 * macro below identifies these cards given the subsystem_id.
116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
117 (dev_type == XFRAME_I_DEVICE) ? \
118 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
119 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
124 static inline int is_s2io_card_up(const struct s2io_nic *sp)
126 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
129 /* Ethtool related variables and Macros. */
130 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
131 "Register test\t(offline)",
132 "Eeprom test\t(offline)",
133 "Link test\t(online)",
134 "RLDRAM test\t(offline)",
135 "BIST Test\t(offline)"
138 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
140 {"tmac_data_octets"},
144 {"tmac_pause_ctrl_frms"},
148 {"tmac_any_err_frms"},
149 {"tmac_ttl_less_fb_octets"},
150 {"tmac_vld_ip_octets"},
158 {"rmac_data_octets"},
159 {"rmac_fcs_err_frms"},
161 {"rmac_vld_mcst_frms"},
162 {"rmac_vld_bcst_frms"},
163 {"rmac_in_rng_len_err_frms"},
164 {"rmac_out_rng_len_err_frms"},
166 {"rmac_pause_ctrl_frms"},
167 {"rmac_unsup_ctrl_frms"},
169 {"rmac_accepted_ucst_frms"},
170 {"rmac_accepted_nucst_frms"},
171 {"rmac_discarded_frms"},
172 {"rmac_drop_events"},
173 {"rmac_ttl_less_fb_octets"},
175 {"rmac_usized_frms"},
176 {"rmac_osized_frms"},
178 {"rmac_jabber_frms"},
179 {"rmac_ttl_64_frms"},
180 {"rmac_ttl_65_127_frms"},
181 {"rmac_ttl_128_255_frms"},
182 {"rmac_ttl_256_511_frms"},
183 {"rmac_ttl_512_1023_frms"},
184 {"rmac_ttl_1024_1518_frms"},
192 {"rmac_err_drp_udp"},
193 {"rmac_xgmii_err_sym"},
211 {"rmac_xgmii_data_err_cnt"},
212 {"rmac_xgmii_ctrl_err_cnt"},
213 {"rmac_accepted_ip"},
217 {"new_rd_req_rtry_cnt"},
219 {"wr_rtry_rd_ack_cnt"},
222 {"new_wr_req_rtry_cnt"},
225 {"rd_rtry_wr_ack_cnt"},
235 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
236 {"rmac_ttl_1519_4095_frms"},
237 {"rmac_ttl_4096_8191_frms"},
238 {"rmac_ttl_8192_max_frms"},
239 {"rmac_ttl_gt_max_frms"},
240 {"rmac_osized_alt_frms"},
241 {"rmac_jabber_alt_frms"},
242 {"rmac_gt_max_alt_frms"},
244 {"rmac_len_discard"},
245 {"rmac_fcs_discard"},
248 {"rmac_red_discard"},
249 {"rmac_rts_discard"},
250 {"rmac_ingm_full_discard"},
254 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
255 {"\n DRIVER STATISTICS"},
256 {"single_bit_ecc_errs"},
257 {"double_bit_ecc_errs"},
270 {"alarm_transceiver_temp_high"},
271 {"alarm_transceiver_temp_low"},
272 {"alarm_laser_bias_current_high"},
273 {"alarm_laser_bias_current_low"},
274 {"alarm_laser_output_power_high"},
275 {"alarm_laser_output_power_low"},
276 {"warn_transceiver_temp_high"},
277 {"warn_transceiver_temp_low"},
278 {"warn_laser_bias_current_high"},
279 {"warn_laser_bias_current_low"},
280 {"warn_laser_output_power_high"},
281 {"warn_laser_output_power_low"},
282 {"lro_aggregated_pkts"},
283 {"lro_flush_both_count"},
284 {"lro_out_of_sequence_pkts"},
285 {"lro_flush_due_to_max_pkts"},
286 {"lro_avg_aggr_pkts"},
287 {"mem_alloc_fail_cnt"},
288 {"pci_map_fail_cnt"},
289 {"watchdog_timer_cnt"},
296 {"tx_tcode_buf_abort_cnt"},
297 {"tx_tcode_desc_abort_cnt"},
298 {"tx_tcode_parity_err_cnt"},
299 {"tx_tcode_link_loss_cnt"},
300 {"tx_tcode_list_proc_err_cnt"},
301 {"rx_tcode_parity_err_cnt"},
302 {"rx_tcode_abort_cnt"},
303 {"rx_tcode_parity_abort_cnt"},
304 {"rx_tcode_rda_fail_cnt"},
305 {"rx_tcode_unkn_prot_cnt"},
306 {"rx_tcode_fcs_err_cnt"},
307 {"rx_tcode_buf_size_err_cnt"},
308 {"rx_tcode_rxd_corrupt_cnt"},
309 {"rx_tcode_unkn_err_cnt"},
317 {"mac_tmac_err_cnt"},
318 {"mac_rmac_err_cnt"},
319 {"xgxs_txgxs_err_cnt"},
320 {"xgxs_rxgxs_err_cnt"},
322 {"prc_pcix_err_cnt"},
329 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
330 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
331 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
339 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
340 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
342 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
343 init_timer(&timer); \
344 timer.function = handle; \
345 timer.data = (unsigned long)arg; \
346 mod_timer(&timer, (jiffies + exp)) \
348 /* copy mac addr to def_mac_addr array */
349 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
351 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
360 * Constants to be programmed into the Xena's registers, to configure
365 static const u64 herc_act_dtx_cfg[] = {
367 0x8000051536750000ULL, 0x80000515367500E0ULL,
369 0x8000051536750004ULL, 0x80000515367500E4ULL,
371 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
373 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
375 0x801205150D440000ULL, 0x801205150D4400E0ULL,
377 0x801205150D440004ULL, 0x801205150D4400E4ULL,
379 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
381 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
386 static const u64 xena_dtx_cfg[] = {
388 0x8000051500000000ULL, 0x80000515000000E0ULL,
390 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
392 0x8001051500000000ULL, 0x80010515000000E0ULL,
394 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
396 0x8002051500000000ULL, 0x80020515000000E0ULL,
398 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
403 * Constants for Fixing the MacAddress problem seen mostly on
406 static const u64 fix_mac[] = {
407 0x0060000000000000ULL, 0x0060600000000000ULL,
408 0x0040600000000000ULL, 0x0000600000000000ULL,
409 0x0020600000000000ULL, 0x0060600000000000ULL,
410 0x0020600000000000ULL, 0x0060600000000000ULL,
411 0x0020600000000000ULL, 0x0060600000000000ULL,
412 0x0020600000000000ULL, 0x0060600000000000ULL,
413 0x0020600000000000ULL, 0x0060600000000000ULL,
414 0x0020600000000000ULL, 0x0060600000000000ULL,
415 0x0020600000000000ULL, 0x0060600000000000ULL,
416 0x0020600000000000ULL, 0x0060600000000000ULL,
417 0x0020600000000000ULL, 0x0060600000000000ULL,
418 0x0020600000000000ULL, 0x0060600000000000ULL,
419 0x0020600000000000ULL, 0x0000600000000000ULL,
420 0x0040600000000000ULL, 0x0060600000000000ULL,
424 MODULE_LICENSE("GPL");
425 MODULE_VERSION(DRV_VERSION);
428 /* Module Loadable parameters. */
429 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
430 S2IO_PARM_INT(rx_ring_num, 1);
431 S2IO_PARM_INT(multiq, 0);
432 S2IO_PARM_INT(rx_ring_mode, 1);
433 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
434 S2IO_PARM_INT(rmac_pause_time, 0x100);
435 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
436 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
437 S2IO_PARM_INT(shared_splits, 0);
438 S2IO_PARM_INT(tmac_util_period, 5);
439 S2IO_PARM_INT(rmac_util_period, 5);
440 S2IO_PARM_INT(l3l4hdr_size, 128);
441 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
442 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
443 /* Frequency of Rx desc syncs expressed as power of 2 */
444 S2IO_PARM_INT(rxsync_frequency, 3);
445 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
446 S2IO_PARM_INT(intr_type, 2);
447 /* Large receive offload feature */
449 /* Max pkts to be aggregated by LRO at one time. If not specified,
450 * aggregation happens until we hit max IP pkt size(64K)
452 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
453 S2IO_PARM_INT(indicate_max_pkts, 0);
455 S2IO_PARM_INT(napi, 1);
456 S2IO_PARM_INT(ufo, 0);
457 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
459 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
460 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
461 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
462 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
463 static unsigned int rts_frm_len[MAX_RX_RINGS] =
464 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
466 module_param_array(tx_fifo_len, uint, NULL, 0);
467 module_param_array(rx_ring_sz, uint, NULL, 0);
468 module_param_array(rts_frm_len, uint, NULL, 0);
472 * This table lists all the devices that this driver supports.
474 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
475 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
476 PCI_ANY_ID, PCI_ANY_ID},
477 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
478 PCI_ANY_ID, PCI_ANY_ID},
479 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
480 PCI_ANY_ID, PCI_ANY_ID},
481 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
482 PCI_ANY_ID, PCI_ANY_ID},
486 MODULE_DEVICE_TABLE(pci, s2io_tbl);
488 static const struct pci_error_handlers s2io_err_handler = {
489 .error_detected = s2io_io_error_detected,
490 .slot_reset = s2io_io_slot_reset,
491 .resume = s2io_io_resume,
494 static struct pci_driver s2io_driver = {
496 .id_table = s2io_tbl,
497 .probe = s2io_init_nic,
498 .remove = s2io_rem_nic,
499 .err_handler = &s2io_err_handler,
502 /* A simplifier macro used both by init and free shared_mem Fns(). */
503 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
505 /* netqueue manipulation helper functions */
506 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
508 if (!sp->config.multiq) {
511 for (i = 0; i < sp->config.tx_fifo_num; i++)
512 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
514 netif_tx_stop_all_queues(sp->dev);
517 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
519 if (!sp->config.multiq)
520 sp->mac_control.fifos[fifo_no].queue_state =
523 netif_tx_stop_all_queues(sp->dev);
526 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
528 if (!sp->config.multiq) {
531 for (i = 0; i < sp->config.tx_fifo_num; i++)
532 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
534 netif_tx_start_all_queues(sp->dev);
537 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
539 if (!sp->config.multiq)
540 sp->mac_control.fifos[fifo_no].queue_state =
543 netif_tx_start_all_queues(sp->dev);
546 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
548 if (!sp->config.multiq) {
551 for (i = 0; i < sp->config.tx_fifo_num; i++)
552 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
554 netif_tx_wake_all_queues(sp->dev);
557 static inline void s2io_wake_tx_queue(
558 struct fifo_info *fifo, int cnt, u8 multiq)
562 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
563 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
564 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
565 if (netif_queue_stopped(fifo->dev)) {
566 fifo->queue_state = FIFO_QUEUE_START;
567 netif_wake_queue(fifo->dev);
573 * init_shared_mem - Allocation and Initialization of Memory
574 * @nic: Device private variable.
575 * Description: The function allocates all the memory areas shared
576 * between the NIC and the driver. This includes Tx descriptors,
577 * Rx descriptors and the statistics block.
580 static int init_shared_mem(struct s2io_nic *nic)
583 void *tmp_v_addr, *tmp_v_addr_next;
584 dma_addr_t tmp_p_addr, tmp_p_addr_next;
585 struct RxD_block *pre_rxd_blk = NULL;
587 int lst_size, lst_per_page;
588 struct net_device *dev = nic->dev;
591 struct config_param *config = &nic->config;
592 struct mac_info *mac_control = &nic->mac_control;
593 unsigned long long mem_allocated = 0;
595 /* Allocation and initialization of TXDLs in FIFOs */
597 for (i = 0; i < config->tx_fifo_num; i++) {
598 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
600 size += tx_cfg->fifo_len;
602 if (size > MAX_AVAILABLE_TXDS) {
604 "Too many TxDs requested: %d, max supported: %d\n",
605 size, MAX_AVAILABLE_TXDS);
610 for (i = 0; i < config->tx_fifo_num; i++) {
611 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
613 size = tx_cfg->fifo_len;
615 * Legal values are from 2 to 8192
618 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
619 "Valid lengths are 2 through 8192\n",
625 lst_size = (sizeof(struct TxD) * config->max_txds);
626 lst_per_page = PAGE_SIZE / lst_size;
628 for (i = 0; i < config->tx_fifo_num; i++) {
629 struct fifo_info *fifo = &mac_control->fifos[i];
630 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
631 int fifo_len = tx_cfg->fifo_len;
632 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
634 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
635 if (!fifo->list_info) {
636 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
639 mem_allocated += list_holder_size;
641 for (i = 0; i < config->tx_fifo_num; i++) {
642 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
644 struct fifo_info *fifo = &mac_control->fifos[i];
645 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
647 fifo->tx_curr_put_info.offset = 0;
648 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
649 fifo->tx_curr_get_info.offset = 0;
650 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
653 fifo->max_txds = MAX_SKB_FRAGS + 2;
656 for (j = 0; j < page_num; j++) {
660 tmp_v = pci_alloc_consistent(nic->pdev,
664 "pci_alloc_consistent failed for TxDL\n");
667 /* If we got a zero DMA address(can happen on
668 * certain platforms like PPC), reallocate.
669 * Store virtual address of page we don't want,
673 mac_control->zerodma_virt_addr = tmp_v;
675 "%s: Zero DMA address for TxDL. "
676 "Virtual address %p\n",
678 tmp_v = pci_alloc_consistent(nic->pdev,
682 "pci_alloc_consistent failed for TxDL\n");
685 mem_allocated += PAGE_SIZE;
687 while (k < lst_per_page) {
688 int l = (j * lst_per_page) + k;
689 if (l == tx_cfg->fifo_len)
691 fifo->list_info[l].list_virt_addr =
692 tmp_v + (k * lst_size);
693 fifo->list_info[l].list_phy_addr =
694 tmp_p + (k * lst_size);
700 for (i = 0; i < config->tx_fifo_num; i++) {
701 struct fifo_info *fifo = &mac_control->fifos[i];
702 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
704 size = tx_cfg->fifo_len;
705 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
706 if (!fifo->ufo_in_band_v)
708 mem_allocated += (size * sizeof(u64));
711 /* Allocation and initialization of RXDs in Rings */
713 for (i = 0; i < config->rx_ring_num; i++) {
714 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
715 struct ring_info *ring = &mac_control->rings[i];
717 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
718 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
719 "multiple of RxDs per Block\n",
723 size += rx_cfg->num_rxd;
724 ring->block_count = rx_cfg->num_rxd /
725 (rxd_count[nic->rxd_mode] + 1);
726 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
728 if (nic->rxd_mode == RXD_MODE_1)
729 size = (size * (sizeof(struct RxD1)));
731 size = (size * (sizeof(struct RxD3)));
733 for (i = 0; i < config->rx_ring_num; i++) {
734 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
735 struct ring_info *ring = &mac_control->rings[i];
737 ring->rx_curr_get_info.block_index = 0;
738 ring->rx_curr_get_info.offset = 0;
739 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
740 ring->rx_curr_put_info.block_index = 0;
741 ring->rx_curr_put_info.offset = 0;
742 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
746 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
747 /* Allocating all the Rx blocks */
748 for (j = 0; j < blk_cnt; j++) {
749 struct rx_block_info *rx_blocks;
752 rx_blocks = &ring->rx_blocks[j];
753 size = SIZE_OF_BLOCK; /* size is always page size */
754 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
756 if (tmp_v_addr == NULL) {
758 * In case of failure, free_shared_mem()
759 * is called, which should free any
760 * memory that was alloced till the
763 rx_blocks->block_virt_addr = tmp_v_addr;
766 mem_allocated += size;
767 memset(tmp_v_addr, 0, size);
769 size = sizeof(struct rxd_info) *
770 rxd_count[nic->rxd_mode];
771 rx_blocks->block_virt_addr = tmp_v_addr;
772 rx_blocks->block_dma_addr = tmp_p_addr;
773 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
774 if (!rx_blocks->rxds)
776 mem_allocated += size;
777 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
778 rx_blocks->rxds[l].virt_addr =
779 rx_blocks->block_virt_addr +
780 (rxd_size[nic->rxd_mode] * l);
781 rx_blocks->rxds[l].dma_addr =
782 rx_blocks->block_dma_addr +
783 (rxd_size[nic->rxd_mode] * l);
786 /* Interlinking all Rx Blocks */
787 for (j = 0; j < blk_cnt; j++) {
788 int next = (j + 1) % blk_cnt;
789 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
790 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
791 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
792 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
794 pre_rxd_blk = tmp_v_addr;
795 pre_rxd_blk->reserved_2_pNext_RxD_block =
796 (unsigned long)tmp_v_addr_next;
797 pre_rxd_blk->pNext_RxD_Blk_physical =
798 (u64)tmp_p_addr_next;
801 if (nic->rxd_mode == RXD_MODE_3B) {
803 * Allocation of Storages for buffer addresses in 2BUFF mode
804 * and the buffers as well.
806 for (i = 0; i < config->rx_ring_num; i++) {
807 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
808 struct ring_info *ring = &mac_control->rings[i];
810 blk_cnt = rx_cfg->num_rxd /
811 (rxd_count[nic->rxd_mode] + 1);
812 size = sizeof(struct buffAdd *) * blk_cnt;
813 ring->ba = kmalloc(size, GFP_KERNEL);
816 mem_allocated += size;
817 for (j = 0; j < blk_cnt; j++) {
820 size = sizeof(struct buffAdd) *
821 (rxd_count[nic->rxd_mode] + 1);
822 ring->ba[j] = kmalloc(size, GFP_KERNEL);
825 mem_allocated += size;
826 while (k != rxd_count[nic->rxd_mode]) {
827 ba = &ring->ba[j][k];
828 size = BUF0_LEN + ALIGN_SIZE;
829 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
832 mem_allocated += size;
833 tmp = (unsigned long)ba->ba_0_org;
835 tmp &= ~((unsigned long)ALIGN_SIZE);
836 ba->ba_0 = (void *)tmp;
838 size = BUF1_LEN + ALIGN_SIZE;
839 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
842 mem_allocated += size;
843 tmp = (unsigned long)ba->ba_1_org;
845 tmp &= ~((unsigned long)ALIGN_SIZE);
846 ba->ba_1 = (void *)tmp;
853 /* Allocation and initialization of Statistics block */
854 size = sizeof(struct stat_block);
855 mac_control->stats_mem =
856 pci_alloc_consistent(nic->pdev, size,
857 &mac_control->stats_mem_phy);
859 if (!mac_control->stats_mem) {
861 * In case of failure, free_shared_mem() is called, which
862 * should free any memory that was alloced till the
867 mem_allocated += size;
868 mac_control->stats_mem_sz = size;
870 tmp_v_addr = mac_control->stats_mem;
871 mac_control->stats_info = tmp_v_addr;
872 memset(tmp_v_addr, 0, size);
873 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
874 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
875 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
880 * free_shared_mem - Free the allocated Memory
881 * @nic: Device private variable.
882 * Description: This function is to free all memory locations allocated by
883 * the init_shared_mem() function and return it to the kernel.
886 static void free_shared_mem(struct s2io_nic *nic)
888 int i, j, blk_cnt, size;
890 dma_addr_t tmp_p_addr;
891 int lst_size, lst_per_page;
892 struct net_device *dev;
894 struct config_param *config;
895 struct mac_info *mac_control;
896 struct stat_block *stats;
897 struct swStat *swstats;
904 config = &nic->config;
905 mac_control = &nic->mac_control;
906 stats = mac_control->stats_info;
907 swstats = &stats->sw_stat;
909 lst_size = sizeof(struct TxD) * config->max_txds;
910 lst_per_page = PAGE_SIZE / lst_size;
912 for (i = 0; i < config->tx_fifo_num; i++) {
913 struct fifo_info *fifo = &mac_control->fifos[i];
914 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
916 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
917 for (j = 0; j < page_num; j++) {
918 int mem_blks = (j * lst_per_page);
919 struct list_info_hold *fli;
921 if (!fifo->list_info)
924 fli = &fifo->list_info[mem_blks];
925 if (!fli->list_virt_addr)
927 pci_free_consistent(nic->pdev, PAGE_SIZE,
930 swstats->mem_freed += PAGE_SIZE;
932 /* If we got a zero DMA address during allocation,
935 if (mac_control->zerodma_virt_addr) {
936 pci_free_consistent(nic->pdev, PAGE_SIZE,
937 mac_control->zerodma_virt_addr,
940 "%s: Freeing TxDL with zero DMA address. "
941 "Virtual address %p\n",
942 dev->name, mac_control->zerodma_virt_addr);
943 swstats->mem_freed += PAGE_SIZE;
945 kfree(fifo->list_info);
946 swstats->mem_freed += tx_cfg->fifo_len *
947 sizeof(struct list_info_hold);
950 size = SIZE_OF_BLOCK;
951 for (i = 0; i < config->rx_ring_num; i++) {
952 struct ring_info *ring = &mac_control->rings[i];
954 blk_cnt = ring->block_count;
955 for (j = 0; j < blk_cnt; j++) {
956 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
957 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
958 if (tmp_v_addr == NULL)
960 pci_free_consistent(nic->pdev, size,
961 tmp_v_addr, tmp_p_addr);
962 swstats->mem_freed += size;
963 kfree(ring->rx_blocks[j].rxds);
964 swstats->mem_freed += sizeof(struct rxd_info) *
965 rxd_count[nic->rxd_mode];
969 if (nic->rxd_mode == RXD_MODE_3B) {
970 /* Freeing buffer storage addresses in 2BUFF mode. */
971 for (i = 0; i < config->rx_ring_num; i++) {
972 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
973 struct ring_info *ring = &mac_control->rings[i];
975 blk_cnt = rx_cfg->num_rxd /
976 (rxd_count[nic->rxd_mode] + 1);
977 for (j = 0; j < blk_cnt; j++) {
981 while (k != rxd_count[nic->rxd_mode]) {
982 struct buffAdd *ba = &ring->ba[j][k];
984 swstats->mem_freed +=
985 BUF0_LEN + ALIGN_SIZE;
987 swstats->mem_freed +=
988 BUF1_LEN + ALIGN_SIZE;
992 swstats->mem_freed += sizeof(struct buffAdd) *
993 (rxd_count[nic->rxd_mode] + 1);
996 swstats->mem_freed += sizeof(struct buffAdd *) *
1001 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1002 struct fifo_info *fifo = &mac_control->fifos[i];
1003 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1005 if (fifo->ufo_in_band_v) {
1006 swstats->mem_freed += tx_cfg->fifo_len *
1008 kfree(fifo->ufo_in_band_v);
1012 if (mac_control->stats_mem) {
1013 swstats->mem_freed += mac_control->stats_mem_sz;
1014 pci_free_consistent(nic->pdev,
1015 mac_control->stats_mem_sz,
1016 mac_control->stats_mem,
1017 mac_control->stats_mem_phy);
1022 * s2io_verify_pci_mode -
1025 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1027 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1028 register u64 val64 = 0;
1031 val64 = readq(&bar0->pci_mode);
1032 mode = (u8)GET_PCI_MODE(val64);
1034 if (val64 & PCI_MODE_UNKNOWN_MODE)
1035 return -1; /* Unknown PCI mode */
1039 #define NEC_VENID 0x1033
1040 #define NEC_DEVID 0x0125
1041 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1043 struct pci_dev *tdev = NULL;
1044 for_each_pci_dev(tdev) {
1045 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1046 if (tdev->bus == s2io_pdev->bus->parent) {
1055 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1057 * s2io_print_pci_mode -
1059 static int s2io_print_pci_mode(struct s2io_nic *nic)
1061 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1062 register u64 val64 = 0;
1064 struct config_param *config = &nic->config;
1065 const char *pcimode;
1067 val64 = readq(&bar0->pci_mode);
1068 mode = (u8)GET_PCI_MODE(val64);
1070 if (val64 & PCI_MODE_UNKNOWN_MODE)
1071 return -1; /* Unknown PCI mode */
1073 config->bus_speed = bus_speed[mode];
1075 if (s2io_on_nec_bridge(nic->pdev)) {
1076 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1082 case PCI_MODE_PCI_33:
1083 pcimode = "33MHz PCI bus";
1085 case PCI_MODE_PCI_66:
1086 pcimode = "66MHz PCI bus";
1088 case PCI_MODE_PCIX_M1_66:
1089 pcimode = "66MHz PCIX(M1) bus";
1091 case PCI_MODE_PCIX_M1_100:
1092 pcimode = "100MHz PCIX(M1) bus";
1094 case PCI_MODE_PCIX_M1_133:
1095 pcimode = "133MHz PCIX(M1) bus";
1097 case PCI_MODE_PCIX_M2_66:
1098 pcimode = "133MHz PCIX(M2) bus";
1100 case PCI_MODE_PCIX_M2_100:
1101 pcimode = "200MHz PCIX(M2) bus";
1103 case PCI_MODE_PCIX_M2_133:
1104 pcimode = "266MHz PCIX(M2) bus";
1107 pcimode = "unsupported bus!";
1111 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1112 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1118 * init_tti - Initialization transmit traffic interrupt scheme
1119 * @nic: device private variable
1120 * @link: link status (UP/DOWN) used to enable/disable continuous
1121 * transmit interrupts
1122 * Description: The function configures transmit traffic interrupts
1123 * Return Value: SUCCESS on success and
1127 static int init_tti(struct s2io_nic *nic, int link)
1129 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1130 register u64 val64 = 0;
1132 struct config_param *config = &nic->config;
1134 for (i = 0; i < config->tx_fifo_num; i++) {
1136 * TTI Initialization. Default Tx timer gets us about
1137 * 250 interrupts per sec. Continuous interrupts are enabled
1140 if (nic->device_type == XFRAME_II_DEVICE) {
1141 int count = (nic->config.bus_speed * 125)/2;
1142 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1144 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1146 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1147 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1148 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1149 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1151 if (use_continuous_tx_intrs && (link == LINK_UP))
1152 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1153 writeq(val64, &bar0->tti_data1_mem);
1155 if (nic->config.intr_type == MSI_X) {
1156 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1157 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1158 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1159 TTI_DATA2_MEM_TX_UFC_D(0x300);
1161 if ((nic->config.tx_steering_type ==
1162 TX_DEFAULT_STEERING) &&
1163 (config->tx_fifo_num > 1) &&
1164 (i >= nic->udp_fifo_idx) &&
1165 (i < (nic->udp_fifo_idx +
1166 nic->total_udp_fifos)))
1167 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1168 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1169 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1170 TTI_DATA2_MEM_TX_UFC_D(0x120);
1172 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1173 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1174 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1175 TTI_DATA2_MEM_TX_UFC_D(0x80);
1178 writeq(val64, &bar0->tti_data2_mem);
1180 val64 = TTI_CMD_MEM_WE |
1181 TTI_CMD_MEM_STROBE_NEW_CMD |
1182 TTI_CMD_MEM_OFFSET(i);
1183 writeq(val64, &bar0->tti_command_mem);
1185 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1186 TTI_CMD_MEM_STROBE_NEW_CMD,
1187 S2IO_BIT_RESET) != SUCCESS)
1195 * init_nic - Initialization of hardware
1196 * @nic: device private variable
1197 * Description: The function sequentially configures every block
1198 * of the H/W from their reset values.
1199 * Return Value: SUCCESS on success and
1200 * '-1' on failure (endian settings incorrect).
1203 static int init_nic(struct s2io_nic *nic)
1205 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1206 struct net_device *dev = nic->dev;
1207 register u64 val64 = 0;
1212 unsigned long long mem_share;
1214 struct config_param *config = &nic->config;
1215 struct mac_info *mac_control = &nic->mac_control;
1217 /* to set the swapper controle on the card */
1218 if (s2io_set_swapper(nic)) {
1219 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1224 * Herc requires EOI to be removed from reset before XGXS, so..
1226 if (nic->device_type & XFRAME_II_DEVICE) {
1227 val64 = 0xA500000000ULL;
1228 writeq(val64, &bar0->sw_reset);
1230 val64 = readq(&bar0->sw_reset);
1233 /* Remove XGXS from reset state */
1235 writeq(val64, &bar0->sw_reset);
1237 val64 = readq(&bar0->sw_reset);
1239 /* Ensure that it's safe to access registers by checking
1240 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1242 if (nic->device_type == XFRAME_II_DEVICE) {
1243 for (i = 0; i < 50; i++) {
1244 val64 = readq(&bar0->adapter_status);
1245 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1253 /* Enable Receiving broadcasts */
1254 add = &bar0->mac_cfg;
1255 val64 = readq(&bar0->mac_cfg);
1256 val64 |= MAC_RMAC_BCAST_ENABLE;
1257 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1258 writel((u32)val64, add);
1259 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1260 writel((u32) (val64 >> 32), (add + 4));
1262 /* Read registers in all blocks */
1263 val64 = readq(&bar0->mac_int_mask);
1264 val64 = readq(&bar0->mc_int_mask);
1265 val64 = readq(&bar0->xgxs_int_mask);
1269 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1271 if (nic->device_type & XFRAME_II_DEVICE) {
1272 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1273 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1274 &bar0->dtx_control, UF);
1276 msleep(1); /* Necessary!! */
1280 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1281 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1282 &bar0->dtx_control, UF);
1283 val64 = readq(&bar0->dtx_control);
1288 /* Tx DMA Initialization */
1290 writeq(val64, &bar0->tx_fifo_partition_0);
1291 writeq(val64, &bar0->tx_fifo_partition_1);
1292 writeq(val64, &bar0->tx_fifo_partition_2);
1293 writeq(val64, &bar0->tx_fifo_partition_3);
1295 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1296 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1298 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1299 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1301 if (i == (config->tx_fifo_num - 1)) {
1308 writeq(val64, &bar0->tx_fifo_partition_0);
1313 writeq(val64, &bar0->tx_fifo_partition_1);
1318 writeq(val64, &bar0->tx_fifo_partition_2);
1323 writeq(val64, &bar0->tx_fifo_partition_3);
1334 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1335 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1337 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1338 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1340 val64 = readq(&bar0->tx_fifo_partition_0);
1341 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1342 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1345 * Initialization of Tx_PA_CONFIG register to ignore packet
1346 * integrity checking.
1348 val64 = readq(&bar0->tx_pa_cfg);
1349 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1350 TX_PA_CFG_IGNORE_SNAP_OUI |
1351 TX_PA_CFG_IGNORE_LLC_CTRL |
1352 TX_PA_CFG_IGNORE_L2_ERR;
1353 writeq(val64, &bar0->tx_pa_cfg);
1355 /* Rx DMA intialization. */
1357 for (i = 0; i < config->rx_ring_num; i++) {
1358 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1360 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1362 writeq(val64, &bar0->rx_queue_priority);
1365 * Allocating equal share of memory to all the
1369 if (nic->device_type & XFRAME_II_DEVICE)
1374 for (i = 0; i < config->rx_ring_num; i++) {
1377 mem_share = (mem_size / config->rx_ring_num +
1378 mem_size % config->rx_ring_num);
1379 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1382 mem_share = (mem_size / config->rx_ring_num);
1383 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1386 mem_share = (mem_size / config->rx_ring_num);
1387 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1390 mem_share = (mem_size / config->rx_ring_num);
1391 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1394 mem_share = (mem_size / config->rx_ring_num);
1395 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1398 mem_share = (mem_size / config->rx_ring_num);
1399 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1402 mem_share = (mem_size / config->rx_ring_num);
1403 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1406 mem_share = (mem_size / config->rx_ring_num);
1407 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1411 writeq(val64, &bar0->rx_queue_cfg);
1414 * Filling Tx round robin registers
1415 * as per the number of FIFOs for equal scheduling priority
1417 switch (config->tx_fifo_num) {
1420 writeq(val64, &bar0->tx_w_round_robin_0);
1421 writeq(val64, &bar0->tx_w_round_robin_1);
1422 writeq(val64, &bar0->tx_w_round_robin_2);
1423 writeq(val64, &bar0->tx_w_round_robin_3);
1424 writeq(val64, &bar0->tx_w_round_robin_4);
1427 val64 = 0x0001000100010001ULL;
1428 writeq(val64, &bar0->tx_w_round_robin_0);
1429 writeq(val64, &bar0->tx_w_round_robin_1);
1430 writeq(val64, &bar0->tx_w_round_robin_2);
1431 writeq(val64, &bar0->tx_w_round_robin_3);
1432 val64 = 0x0001000100000000ULL;
1433 writeq(val64, &bar0->tx_w_round_robin_4);
1436 val64 = 0x0001020001020001ULL;
1437 writeq(val64, &bar0->tx_w_round_robin_0);
1438 val64 = 0x0200010200010200ULL;
1439 writeq(val64, &bar0->tx_w_round_robin_1);
1440 val64 = 0x0102000102000102ULL;
1441 writeq(val64, &bar0->tx_w_round_robin_2);
1442 val64 = 0x0001020001020001ULL;
1443 writeq(val64, &bar0->tx_w_round_robin_3);
1444 val64 = 0x0200010200000000ULL;
1445 writeq(val64, &bar0->tx_w_round_robin_4);
1448 val64 = 0x0001020300010203ULL;
1449 writeq(val64, &bar0->tx_w_round_robin_0);
1450 writeq(val64, &bar0->tx_w_round_robin_1);
1451 writeq(val64, &bar0->tx_w_round_robin_2);
1452 writeq(val64, &bar0->tx_w_round_robin_3);
1453 val64 = 0x0001020300000000ULL;
1454 writeq(val64, &bar0->tx_w_round_robin_4);
1457 val64 = 0x0001020304000102ULL;
1458 writeq(val64, &bar0->tx_w_round_robin_0);
1459 val64 = 0x0304000102030400ULL;
1460 writeq(val64, &bar0->tx_w_round_robin_1);
1461 val64 = 0x0102030400010203ULL;
1462 writeq(val64, &bar0->tx_w_round_robin_2);
1463 val64 = 0x0400010203040001ULL;
1464 writeq(val64, &bar0->tx_w_round_robin_3);
1465 val64 = 0x0203040000000000ULL;
1466 writeq(val64, &bar0->tx_w_round_robin_4);
1469 val64 = 0x0001020304050001ULL;
1470 writeq(val64, &bar0->tx_w_round_robin_0);
1471 val64 = 0x0203040500010203ULL;
1472 writeq(val64, &bar0->tx_w_round_robin_1);
1473 val64 = 0x0405000102030405ULL;
1474 writeq(val64, &bar0->tx_w_round_robin_2);
1475 val64 = 0x0001020304050001ULL;
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 val64 = 0x0203040500000000ULL;
1478 writeq(val64, &bar0->tx_w_round_robin_4);
1481 val64 = 0x0001020304050600ULL;
1482 writeq(val64, &bar0->tx_w_round_robin_0);
1483 val64 = 0x0102030405060001ULL;
1484 writeq(val64, &bar0->tx_w_round_robin_1);
1485 val64 = 0x0203040506000102ULL;
1486 writeq(val64, &bar0->tx_w_round_robin_2);
1487 val64 = 0x0304050600010203ULL;
1488 writeq(val64, &bar0->tx_w_round_robin_3);
1489 val64 = 0x0405060000000000ULL;
1490 writeq(val64, &bar0->tx_w_round_robin_4);
1493 val64 = 0x0001020304050607ULL;
1494 writeq(val64, &bar0->tx_w_round_robin_0);
1495 writeq(val64, &bar0->tx_w_round_robin_1);
1496 writeq(val64, &bar0->tx_w_round_robin_2);
1497 writeq(val64, &bar0->tx_w_round_robin_3);
1498 val64 = 0x0001020300000000ULL;
1499 writeq(val64, &bar0->tx_w_round_robin_4);
1503 /* Enable all configured Tx FIFO partitions */
1504 val64 = readq(&bar0->tx_fifo_partition_0);
1505 val64 |= (TX_FIFO_PARTITION_EN);
1506 writeq(val64, &bar0->tx_fifo_partition_0);
1508 /* Filling the Rx round robin registers as per the
1509 * number of Rings and steering based on QoS with
1512 switch (config->rx_ring_num) {
1515 writeq(val64, &bar0->rx_w_round_robin_0);
1516 writeq(val64, &bar0->rx_w_round_robin_1);
1517 writeq(val64, &bar0->rx_w_round_robin_2);
1518 writeq(val64, &bar0->rx_w_round_robin_3);
1519 writeq(val64, &bar0->rx_w_round_robin_4);
1521 val64 = 0x8080808080808080ULL;
1522 writeq(val64, &bar0->rts_qos_steering);
1525 val64 = 0x0001000100010001ULL;
1526 writeq(val64, &bar0->rx_w_round_robin_0);
1527 writeq(val64, &bar0->rx_w_round_robin_1);
1528 writeq(val64, &bar0->rx_w_round_robin_2);
1529 writeq(val64, &bar0->rx_w_round_robin_3);
1530 val64 = 0x0001000100000000ULL;
1531 writeq(val64, &bar0->rx_w_round_robin_4);
1533 val64 = 0x8080808040404040ULL;
1534 writeq(val64, &bar0->rts_qos_steering);
1537 val64 = 0x0001020001020001ULL;
1538 writeq(val64, &bar0->rx_w_round_robin_0);
1539 val64 = 0x0200010200010200ULL;
1540 writeq(val64, &bar0->rx_w_round_robin_1);
1541 val64 = 0x0102000102000102ULL;
1542 writeq(val64, &bar0->rx_w_round_robin_2);
1543 val64 = 0x0001020001020001ULL;
1544 writeq(val64, &bar0->rx_w_round_robin_3);
1545 val64 = 0x0200010200000000ULL;
1546 writeq(val64, &bar0->rx_w_round_robin_4);
1548 val64 = 0x8080804040402020ULL;
1549 writeq(val64, &bar0->rts_qos_steering);
1552 val64 = 0x0001020300010203ULL;
1553 writeq(val64, &bar0->rx_w_round_robin_0);
1554 writeq(val64, &bar0->rx_w_round_robin_1);
1555 writeq(val64, &bar0->rx_w_round_robin_2);
1556 writeq(val64, &bar0->rx_w_round_robin_3);
1557 val64 = 0x0001020300000000ULL;
1558 writeq(val64, &bar0->rx_w_round_robin_4);
1560 val64 = 0x8080404020201010ULL;
1561 writeq(val64, &bar0->rts_qos_steering);
1564 val64 = 0x0001020304000102ULL;
1565 writeq(val64, &bar0->rx_w_round_robin_0);
1566 val64 = 0x0304000102030400ULL;
1567 writeq(val64, &bar0->rx_w_round_robin_1);
1568 val64 = 0x0102030400010203ULL;
1569 writeq(val64, &bar0->rx_w_round_robin_2);
1570 val64 = 0x0400010203040001ULL;
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 val64 = 0x0203040000000000ULL;
1573 writeq(val64, &bar0->rx_w_round_robin_4);
1575 val64 = 0x8080404020201008ULL;
1576 writeq(val64, &bar0->rts_qos_steering);
1579 val64 = 0x0001020304050001ULL;
1580 writeq(val64, &bar0->rx_w_round_robin_0);
1581 val64 = 0x0203040500010203ULL;
1582 writeq(val64, &bar0->rx_w_round_robin_1);
1583 val64 = 0x0405000102030405ULL;
1584 writeq(val64, &bar0->rx_w_round_robin_2);
1585 val64 = 0x0001020304050001ULL;
1586 writeq(val64, &bar0->rx_w_round_robin_3);
1587 val64 = 0x0203040500000000ULL;
1588 writeq(val64, &bar0->rx_w_round_robin_4);
1590 val64 = 0x8080404020100804ULL;
1591 writeq(val64, &bar0->rts_qos_steering);
1594 val64 = 0x0001020304050600ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_0);
1596 val64 = 0x0102030405060001ULL;
1597 writeq(val64, &bar0->rx_w_round_robin_1);
1598 val64 = 0x0203040506000102ULL;
1599 writeq(val64, &bar0->rx_w_round_robin_2);
1600 val64 = 0x0304050600010203ULL;
1601 writeq(val64, &bar0->rx_w_round_robin_3);
1602 val64 = 0x0405060000000000ULL;
1603 writeq(val64, &bar0->rx_w_round_robin_4);
1605 val64 = 0x8080402010080402ULL;
1606 writeq(val64, &bar0->rts_qos_steering);
1609 val64 = 0x0001020304050607ULL;
1610 writeq(val64, &bar0->rx_w_round_robin_0);
1611 writeq(val64, &bar0->rx_w_round_robin_1);
1612 writeq(val64, &bar0->rx_w_round_robin_2);
1613 writeq(val64, &bar0->rx_w_round_robin_3);
1614 val64 = 0x0001020300000000ULL;
1615 writeq(val64, &bar0->rx_w_round_robin_4);
1617 val64 = 0x8040201008040201ULL;
1618 writeq(val64, &bar0->rts_qos_steering);
1624 for (i = 0; i < 8; i++)
1625 writeq(val64, &bar0->rts_frm_len_n[i]);
1627 /* Set the default rts frame length for the rings configured */
1628 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1629 for (i = 0 ; i < config->rx_ring_num ; i++)
1630 writeq(val64, &bar0->rts_frm_len_n[i]);
1632 /* Set the frame length for the configured rings
1633 * desired by the user
1635 for (i = 0; i < config->rx_ring_num; i++) {
1636 /* If rts_frm_len[i] == 0 then it is assumed that user not
1637 * specified frame length steering.
1638 * If the user provides the frame length then program
1639 * the rts_frm_len register for those values or else
1640 * leave it as it is.
1642 if (rts_frm_len[i] != 0) {
1643 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1644 &bar0->rts_frm_len_n[i]);
1648 /* Disable differentiated services steering logic */
1649 for (i = 0; i < 64; i++) {
1650 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1652 "%s: rts_ds_steer failed on codepoint %d\n",
1658 /* Program statistics memory */
1659 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1661 if (nic->device_type == XFRAME_II_DEVICE) {
1662 val64 = STAT_BC(0x320);
1663 writeq(val64, &bar0->stat_byte_cnt);
1667 * Initializing the sampling rate for the device to calculate the
1668 * bandwidth utilization.
1670 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1671 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1672 writeq(val64, &bar0->mac_link_util);
1675 * Initializing the Transmit and Receive Traffic Interrupt
1679 /* Initialize TTI */
1680 if (SUCCESS != init_tti(nic, nic->last_link_state))
1683 /* RTI Initialization */
1684 if (nic->device_type == XFRAME_II_DEVICE) {
1686 * Programmed to generate Apprx 500 Intrs per
1689 int count = (nic->config.bus_speed * 125)/4;
1690 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1692 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1693 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1694 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1695 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1696 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1698 writeq(val64, &bar0->rti_data1_mem);
1700 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1701 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1702 if (nic->config.intr_type == MSI_X)
1703 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1704 RTI_DATA2_MEM_RX_UFC_D(0x40));
1706 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1707 RTI_DATA2_MEM_RX_UFC_D(0x80));
1708 writeq(val64, &bar0->rti_data2_mem);
1710 for (i = 0; i < config->rx_ring_num; i++) {
1711 val64 = RTI_CMD_MEM_WE |
1712 RTI_CMD_MEM_STROBE_NEW_CMD |
1713 RTI_CMD_MEM_OFFSET(i);
1714 writeq(val64, &bar0->rti_command_mem);
1717 * Once the operation completes, the Strobe bit of the
1718 * command register will be reset. We poll for this
1719 * particular condition. We wait for a maximum of 500ms
1720 * for the operation to complete, if it's not complete
1721 * by then we return error.
1725 val64 = readq(&bar0->rti_command_mem);
1726 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1730 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1740 * Initializing proper values as Pause threshold into all
1741 * the 8 Queues on Rx side.
1743 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1744 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1746 /* Disable RMAC PAD STRIPPING */
1747 add = &bar0->mac_cfg;
1748 val64 = readq(&bar0->mac_cfg);
1749 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1750 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1751 writel((u32) (val64), add);
1752 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1753 writel((u32) (val64 >> 32), (add + 4));
1754 val64 = readq(&bar0->mac_cfg);
1756 /* Enable FCS stripping by adapter */
1757 add = &bar0->mac_cfg;
1758 val64 = readq(&bar0->mac_cfg);
1759 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1760 if (nic->device_type == XFRAME_II_DEVICE)
1761 writeq(val64, &bar0->mac_cfg);
1763 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1764 writel((u32) (val64), add);
1765 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1766 writel((u32) (val64 >> 32), (add + 4));
1770 * Set the time value to be inserted in the pause frame
1771 * generated by xena.
1773 val64 = readq(&bar0->rmac_pause_cfg);
1774 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1775 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1776 writeq(val64, &bar0->rmac_pause_cfg);
1779 * Set the Threshold Limit for Generating the pause frame
1780 * If the amount of data in any Queue exceeds ratio of
1781 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1782 * pause frame is generated
1785 for (i = 0; i < 4; i++) {
1786 val64 |= (((u64)0xFF00 |
1787 nic->mac_control.mc_pause_threshold_q0q3)
1790 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1793 for (i = 0; i < 4; i++) {
1794 val64 |= (((u64)0xFF00 |
1795 nic->mac_control.mc_pause_threshold_q4q7)
1798 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1801 * TxDMA will stop Read request if the number of read split has
1802 * exceeded the limit pointed by shared_splits
1804 val64 = readq(&bar0->pic_control);
1805 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1806 writeq(val64, &bar0->pic_control);
1808 if (nic->config.bus_speed == 266) {
1809 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1810 writeq(0x0, &bar0->read_retry_delay);
1811 writeq(0x0, &bar0->write_retry_delay);
1815 * Programming the Herc to split every write transaction
1816 * that does not start on an ADB to reduce disconnects.
1818 if (nic->device_type == XFRAME_II_DEVICE) {
1819 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1820 MISC_LINK_STABILITY_PRD(3);
1821 writeq(val64, &bar0->misc_control);
1822 val64 = readq(&bar0->pic_control2);
1823 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1824 writeq(val64, &bar0->pic_control2);
1826 if (strstr(nic->product_name, "CX4")) {
1827 val64 = TMAC_AVG_IPG(0x17);
1828 writeq(val64, &bar0->tmac_avg_ipg);
1833 #define LINK_UP_DOWN_INTERRUPT 1
1834 #define MAC_RMAC_ERR_TIMER 2
1836 static int s2io_link_fault_indication(struct s2io_nic *nic)
1838 if (nic->device_type == XFRAME_II_DEVICE)
1839 return LINK_UP_DOWN_INTERRUPT;
1841 return MAC_RMAC_ERR_TIMER;
1845 * do_s2io_write_bits - update alarm bits in alarm register
1846 * @value: alarm bits
1847 * @flag: interrupt status
1848 * @addr: address value
1849 * Description: update alarm bits in alarm register
1853 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1857 temp64 = readq(addr);
1859 if (flag == ENABLE_INTRS)
1860 temp64 &= ~((u64)value);
1862 temp64 |= ((u64)value);
1863 writeq(temp64, addr);
1866 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1868 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1869 register u64 gen_int_mask = 0;
1872 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1873 if (mask & TX_DMA_INTR) {
1874 gen_int_mask |= TXDMA_INT_M;
1876 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1877 TXDMA_PCC_INT | TXDMA_TTI_INT |
1878 TXDMA_LSO_INT | TXDMA_TPA_INT |
1879 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1881 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1882 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1883 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1884 &bar0->pfc_err_mask);
1886 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1887 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1888 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1890 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1891 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1892 PCC_N_SERR | PCC_6_COF_OV_ERR |
1893 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1894 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1896 flag, &bar0->pcc_err_mask);
1898 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1899 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1901 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1902 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1903 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1904 flag, &bar0->lso_err_mask);
1906 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1907 flag, &bar0->tpa_err_mask);
1909 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1912 if (mask & TX_MAC_INTR) {
1913 gen_int_mask |= TXMAC_INT_M;
1914 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1915 &bar0->mac_int_mask);
1916 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1917 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1918 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1919 flag, &bar0->mac_tmac_err_mask);
1922 if (mask & TX_XGXS_INTR) {
1923 gen_int_mask |= TXXGXS_INT_M;
1924 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1925 &bar0->xgxs_int_mask);
1926 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1927 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1928 flag, &bar0->xgxs_txgxs_err_mask);
1931 if (mask & RX_DMA_INTR) {
1932 gen_int_mask |= RXDMA_INT_M;
1933 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1934 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1935 flag, &bar0->rxdma_int_mask);
1936 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1937 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1938 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1939 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1940 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1941 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1942 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1943 &bar0->prc_pcix_err_mask);
1944 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1945 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1946 &bar0->rpa_err_mask);
1947 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1948 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1949 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1950 RDA_FRM_ECC_SG_ERR |
1951 RDA_MISC_ERR|RDA_PCIX_ERR,
1952 flag, &bar0->rda_err_mask);
1953 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1954 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1955 flag, &bar0->rti_err_mask);
1958 if (mask & RX_MAC_INTR) {
1959 gen_int_mask |= RXMAC_INT_M;
1960 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1961 &bar0->mac_int_mask);
1962 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1963 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1964 RMAC_DOUBLE_ECC_ERR);
1965 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
1966 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
1967 do_s2io_write_bits(interruptible,
1968 flag, &bar0->mac_rmac_err_mask);
1971 if (mask & RX_XGXS_INTR) {
1972 gen_int_mask |= RXXGXS_INT_M;
1973 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1974 &bar0->xgxs_int_mask);
1975 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1976 &bar0->xgxs_rxgxs_err_mask);
1979 if (mask & MC_INTR) {
1980 gen_int_mask |= MC_INT_M;
1981 do_s2io_write_bits(MC_INT_MASK_MC_INT,
1982 flag, &bar0->mc_int_mask);
1983 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1984 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1985 &bar0->mc_err_mask);
1987 nic->general_int_mask = gen_int_mask;
1989 /* Remove this line when alarm interrupts are enabled */
1990 nic->general_int_mask = 0;
1994 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1995 * @nic: device private variable,
1996 * @mask: A mask indicating which Intr block must be modified and,
1997 * @flag: A flag indicating whether to enable or disable the Intrs.
1998 * Description: This function will either disable or enable the interrupts
1999 * depending on the flag argument. The mask argument can be used to
2000 * enable/disable any Intr block.
2001 * Return Value: NONE.
2004 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2006 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2007 register u64 temp64 = 0, intr_mask = 0;
2009 intr_mask = nic->general_int_mask;
2011 /* Top level interrupt classification */
2012 /* PIC Interrupts */
2013 if (mask & TX_PIC_INTR) {
2014 /* Enable PIC Intrs in the general intr mask register */
2015 intr_mask |= TXPIC_INT_M;
2016 if (flag == ENABLE_INTRS) {
2018 * If Hercules adapter enable GPIO otherwise
2019 * disable all PCIX, Flash, MDIO, IIC and GPIO
2020 * interrupts for now.
2023 if (s2io_link_fault_indication(nic) ==
2024 LINK_UP_DOWN_INTERRUPT) {
2025 do_s2io_write_bits(PIC_INT_GPIO, flag,
2026 &bar0->pic_int_mask);
2027 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2028 &bar0->gpio_int_mask);
2030 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2031 } else if (flag == DISABLE_INTRS) {
2033 * Disable PIC Intrs in the general
2034 * intr mask register
2036 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2040 /* Tx traffic interrupts */
2041 if (mask & TX_TRAFFIC_INTR) {
2042 intr_mask |= TXTRAFFIC_INT_M;
2043 if (flag == ENABLE_INTRS) {
2045 * Enable all the Tx side interrupts
2046 * writing 0 Enables all 64 TX interrupt levels
2048 writeq(0x0, &bar0->tx_traffic_mask);
2049 } else if (flag == DISABLE_INTRS) {
2051 * Disable Tx Traffic Intrs in the general intr mask
2054 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2058 /* Rx traffic interrupts */
2059 if (mask & RX_TRAFFIC_INTR) {
2060 intr_mask |= RXTRAFFIC_INT_M;
2061 if (flag == ENABLE_INTRS) {
2062 /* writing 0 Enables all 8 RX interrupt levels */
2063 writeq(0x0, &bar0->rx_traffic_mask);
2064 } else if (flag == DISABLE_INTRS) {
2066 * Disable Rx Traffic Intrs in the general intr mask
2069 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2073 temp64 = readq(&bar0->general_int_mask);
2074 if (flag == ENABLE_INTRS)
2075 temp64 &= ~((u64)intr_mask);
2077 temp64 = DISABLE_ALL_INTRS;
2078 writeq(temp64, &bar0->general_int_mask);
2080 nic->general_int_mask = readq(&bar0->general_int_mask);
2084 * verify_pcc_quiescent- Checks for PCC quiescent state
2085 * Return: 1 If PCC is quiescence
2086 * 0 If PCC is not quiescence
2088 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2091 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2092 u64 val64 = readq(&bar0->adapter_status);
2094 herc = (sp->device_type == XFRAME_II_DEVICE);
2096 if (flag == false) {
2097 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2098 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2101 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2105 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2106 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2107 ADAPTER_STATUS_RMAC_PCC_IDLE))
2110 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2111 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2119 * verify_xena_quiescence - Checks whether the H/W is ready
2120 * Description: Returns whether the H/W is ready to go or not. Depending
2121 * on whether adapter enable bit was written or not the comparison
2122 * differs and the calling function passes the input argument flag to
2124 * Return: 1 If xena is quiescence
2125 * 0 If Xena is not quiescence
2128 static int verify_xena_quiescence(struct s2io_nic *sp)
2131 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2132 u64 val64 = readq(&bar0->adapter_status);
2133 mode = s2io_verify_pci_mode(sp);
2135 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2136 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2139 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2140 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2143 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2144 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2147 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2148 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2151 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2152 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2155 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2156 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2159 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2160 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2163 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2164 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2169 * In PCI 33 mode, the P_PLL is not used, and therefore,
2170 * the the P_PLL_LOCK bit in the adapter_status register will
2173 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2174 sp->device_type == XFRAME_II_DEVICE &&
2175 mode != PCI_MODE_PCI_33) {
2176 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2179 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2180 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2181 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2188 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2189 * @sp: Pointer to device specifc structure
2191 * New procedure to clear mac address reading problems on Alpha platforms
2195 static void fix_mac_address(struct s2io_nic *sp)
2197 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2200 while (fix_mac[i] != END_SIGN) {
2201 writeq(fix_mac[i++], &bar0->gpio_control);
2203 (void) readq(&bar0->gpio_control);
2208 * start_nic - Turns the device on
2209 * @nic : device private variable.
2211 * This function actually turns the device on. Before this function is
2212 * called,all Registers are configured from their reset states
2213 * and shared memory is allocated but the NIC is still quiescent. On
2214 * calling this function, the device interrupts are cleared and the NIC is
2215 * literally switched on by writing into the adapter control register.
2217 * SUCCESS on success and -1 on failure.
2220 static int start_nic(struct s2io_nic *nic)
2222 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2223 struct net_device *dev = nic->dev;
2224 register u64 val64 = 0;
2226 struct config_param *config = &nic->config;
2227 struct mac_info *mac_control = &nic->mac_control;
2229 /* PRC Initialization and configuration */
2230 for (i = 0; i < config->rx_ring_num; i++) {
2231 struct ring_info *ring = &mac_control->rings[i];
2233 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2234 &bar0->prc_rxd0_n[i]);
2236 val64 = readq(&bar0->prc_ctrl_n[i]);
2237 if (nic->rxd_mode == RXD_MODE_1)
2238 val64 |= PRC_CTRL_RC_ENABLED;
2240 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2241 if (nic->device_type == XFRAME_II_DEVICE)
2242 val64 |= PRC_CTRL_GROUP_READS;
2243 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2244 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2245 writeq(val64, &bar0->prc_ctrl_n[i]);
2248 if (nic->rxd_mode == RXD_MODE_3B) {
2249 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2250 val64 = readq(&bar0->rx_pa_cfg);
2251 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2252 writeq(val64, &bar0->rx_pa_cfg);
2255 if (vlan_tag_strip == 0) {
2256 val64 = readq(&bar0->rx_pa_cfg);
2257 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2258 writeq(val64, &bar0->rx_pa_cfg);
2259 nic->vlan_strip_flag = 0;
2263 * Enabling MC-RLDRAM. After enabling the device, we timeout
2264 * for around 100ms, which is approximately the time required
2265 * for the device to be ready for operation.
2267 val64 = readq(&bar0->mc_rldram_mrs);
2268 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2269 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2270 val64 = readq(&bar0->mc_rldram_mrs);
2272 msleep(100); /* Delay by around 100 ms. */
2274 /* Enabling ECC Protection. */
2275 val64 = readq(&bar0->adapter_control);
2276 val64 &= ~ADAPTER_ECC_EN;
2277 writeq(val64, &bar0->adapter_control);
2280 * Verify if the device is ready to be enabled, if so enable
2283 val64 = readq(&bar0->adapter_status);
2284 if (!verify_xena_quiescence(nic)) {
2285 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2286 "Adapter status reads: 0x%llx\n",
2287 dev->name, (unsigned long long)val64);
2292 * With some switches, link might be already up at this point.
2293 * Because of this weird behavior, when we enable laser,
2294 * we may not get link. We need to handle this. We cannot
2295 * figure out which switch is misbehaving. So we are forced to
2296 * make a global change.
2299 /* Enabling Laser. */
2300 val64 = readq(&bar0->adapter_control);
2301 val64 |= ADAPTER_EOI_TX_ON;
2302 writeq(val64, &bar0->adapter_control);
2304 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2306 * Dont see link state interrupts initially on some switches,
2307 * so directly scheduling the link state task here.
2309 schedule_work(&nic->set_link_task);
2311 /* SXE-002: Initialize link and activity LED */
2312 subid = nic->pdev->subsystem_device;
2313 if (((subid & 0xFF) >= 0x07) &&
2314 (nic->device_type == XFRAME_I_DEVICE)) {
2315 val64 = readq(&bar0->gpio_control);
2316 val64 |= 0x0000800000000000ULL;
2317 writeq(val64, &bar0->gpio_control);
2318 val64 = 0x0411040400000000ULL;
2319 writeq(val64, (void __iomem *)bar0 + 0x2700);
2325 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2327 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2328 struct TxD *txdlp, int get_off)
2330 struct s2io_nic *nic = fifo_data->nic;
2331 struct sk_buff *skb;
2336 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2337 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2338 sizeof(u64), PCI_DMA_TODEVICE);
2342 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2344 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2347 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2348 skb_headlen(skb), PCI_DMA_TODEVICE);
2349 frg_cnt = skb_shinfo(skb)->nr_frags;
2352 for (j = 0; j < frg_cnt; j++, txds++) {
2353 const skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2354 if (!txds->Buffer_Pointer)
2356 pci_unmap_page(nic->pdev,
2357 (dma_addr_t)txds->Buffer_Pointer,
2358 skb_frag_size(frag), PCI_DMA_TODEVICE);
2361 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2366 * free_tx_buffers - Free all queued Tx buffers
2367 * @nic : device private variable.
2369 * Free all queued Tx buffers.
2370 * Return Value: void
2373 static void free_tx_buffers(struct s2io_nic *nic)
2375 struct net_device *dev = nic->dev;
2376 struct sk_buff *skb;
2380 struct config_param *config = &nic->config;
2381 struct mac_info *mac_control = &nic->mac_control;
2382 struct stat_block *stats = mac_control->stats_info;
2383 struct swStat *swstats = &stats->sw_stat;
2385 for (i = 0; i < config->tx_fifo_num; i++) {
2386 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2387 struct fifo_info *fifo = &mac_control->fifos[i];
2388 unsigned long flags;
2390 spin_lock_irqsave(&fifo->tx_lock, flags);
2391 for (j = 0; j < tx_cfg->fifo_len; j++) {
2392 txdp = fifo->list_info[j].list_virt_addr;
2393 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2395 swstats->mem_freed += skb->truesize;
2401 "%s: forcibly freeing %d skbs on FIFO%d\n",
2403 fifo->tx_curr_get_info.offset = 0;
2404 fifo->tx_curr_put_info.offset = 0;
2405 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2410 * stop_nic - To stop the nic
2411 * @nic ; device private variable.
2413 * This function does exactly the opposite of what the start_nic()
2414 * function does. This function is called to stop the device.
2419 static void stop_nic(struct s2io_nic *nic)
2421 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2422 register u64 val64 = 0;
2425 /* Disable all interrupts */
2426 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2427 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2428 interruptible |= TX_PIC_INTR;
2429 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2431 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2432 val64 = readq(&bar0->adapter_control);
2433 val64 &= ~(ADAPTER_CNTL_EN);
2434 writeq(val64, &bar0->adapter_control);
2438 * fill_rx_buffers - Allocates the Rx side skbs
2439 * @ring_info: per ring structure
2440 * @from_card_up: If this is true, we will map the buffer to get
2441 * the dma address for buf0 and buf1 to give it to the card.
2442 * Else we will sync the already mapped buffer to give it to the card.
2444 * The function allocates Rx side skbs and puts the physical
2445 * address of these buffers into the RxD buffer pointers, so that the NIC
2446 * can DMA the received frame into these locations.
2447 * The NIC supports 3 receive modes, viz
2449 * 2. three buffer and
2450 * 3. Five buffer modes.
2451 * Each mode defines how many fragments the received frame will be split
2452 * up into by the NIC. The frame is split into L3 header, L4 Header,
2453 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2454 * is split into 3 fragments. As of now only single buffer mode is
2457 * SUCCESS on success or an appropriate -ve value on failure.
2459 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2462 struct sk_buff *skb;
2464 int off, size, block_no, block_no1;
2469 struct RxD_t *first_rxdp = NULL;
2470 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2474 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2476 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2478 block_no1 = ring->rx_curr_get_info.block_index;
2479 while (alloc_tab < alloc_cnt) {
2480 block_no = ring->rx_curr_put_info.block_index;
2482 off = ring->rx_curr_put_info.offset;
2484 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2486 rxd_index = off + 1;
2488 rxd_index += (block_no * ring->rxd_count);
2490 if ((block_no == block_no1) &&
2491 (off == ring->rx_curr_get_info.offset) &&
2492 (rxdp->Host_Control)) {
2493 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2497 if (off && (off == ring->rxd_count)) {
2498 ring->rx_curr_put_info.block_index++;
2499 if (ring->rx_curr_put_info.block_index ==
2501 ring->rx_curr_put_info.block_index = 0;
2502 block_no = ring->rx_curr_put_info.block_index;
2504 ring->rx_curr_put_info.offset = off;
2505 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2506 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2507 ring->dev->name, rxdp);
2511 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2512 ((ring->rxd_mode == RXD_MODE_3B) &&
2513 (rxdp->Control_2 & s2BIT(0)))) {
2514 ring->rx_curr_put_info.offset = off;
2517 /* calculate size of skb based on ring mode */
2519 HEADER_ETHERNET_II_802_3_SIZE +
2520 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2521 if (ring->rxd_mode == RXD_MODE_1)
2522 size += NET_IP_ALIGN;
2524 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2527 skb = netdev_alloc_skb(nic->dev, size);
2529 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2533 first_rxdp->Control_1 |= RXD_OWN_XENA;
2535 swstats->mem_alloc_fail_cnt++;
2539 swstats->mem_allocated += skb->truesize;
2541 if (ring->rxd_mode == RXD_MODE_1) {
2542 /* 1 buffer mode - normal operation mode */
2543 rxdp1 = (struct RxD1 *)rxdp;
2544 memset(rxdp, 0, sizeof(struct RxD1));
2545 skb_reserve(skb, NET_IP_ALIGN);
2546 rxdp1->Buffer0_ptr =
2547 pci_map_single(ring->pdev, skb->data,
2548 size - NET_IP_ALIGN,
2549 PCI_DMA_FROMDEVICE);
2550 if (pci_dma_mapping_error(nic->pdev,
2551 rxdp1->Buffer0_ptr))
2552 goto pci_map_failed;
2555 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2556 rxdp->Host_Control = (unsigned long)skb;
2557 } else if (ring->rxd_mode == RXD_MODE_3B) {
2560 * 2 buffer mode provides 128
2561 * byte aligned receive buffers.
2564 rxdp3 = (struct RxD3 *)rxdp;
2565 /* save buffer pointers to avoid frequent dma mapping */
2566 Buffer0_ptr = rxdp3->Buffer0_ptr;
2567 Buffer1_ptr = rxdp3->Buffer1_ptr;
2568 memset(rxdp, 0, sizeof(struct RxD3));
2569 /* restore the buffer pointers for dma sync*/
2570 rxdp3->Buffer0_ptr = Buffer0_ptr;
2571 rxdp3->Buffer1_ptr = Buffer1_ptr;
2573 ba = &ring->ba[block_no][off];
2574 skb_reserve(skb, BUF0_LEN);
2575 tmp = (u64)(unsigned long)skb->data;
2578 skb->data = (void *) (unsigned long)tmp;
2579 skb_reset_tail_pointer(skb);
2582 rxdp3->Buffer0_ptr =
2583 pci_map_single(ring->pdev, ba->ba_0,
2585 PCI_DMA_FROMDEVICE);
2586 if (pci_dma_mapping_error(nic->pdev,
2587 rxdp3->Buffer0_ptr))
2588 goto pci_map_failed;
2590 pci_dma_sync_single_for_device(ring->pdev,
2591 (dma_addr_t)rxdp3->Buffer0_ptr,
2593 PCI_DMA_FROMDEVICE);
2595 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2596 if (ring->rxd_mode == RXD_MODE_3B) {
2597 /* Two buffer mode */
2600 * Buffer2 will have L3/L4 header plus
2603 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2606 PCI_DMA_FROMDEVICE);
2608 if (pci_dma_mapping_error(nic->pdev,
2609 rxdp3->Buffer2_ptr))
2610 goto pci_map_failed;
2613 rxdp3->Buffer1_ptr =
2614 pci_map_single(ring->pdev,
2617 PCI_DMA_FROMDEVICE);
2619 if (pci_dma_mapping_error(nic->pdev,
2620 rxdp3->Buffer1_ptr)) {
2621 pci_unmap_single(ring->pdev,
2622 (dma_addr_t)(unsigned long)
2625 PCI_DMA_FROMDEVICE);
2626 goto pci_map_failed;
2629 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2630 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2633 rxdp->Control_2 |= s2BIT(0);
2634 rxdp->Host_Control = (unsigned long) (skb);
2636 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2637 rxdp->Control_1 |= RXD_OWN_XENA;
2639 if (off == (ring->rxd_count + 1))
2641 ring->rx_curr_put_info.offset = off;
2643 rxdp->Control_2 |= SET_RXD_MARKER;
2644 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2647 first_rxdp->Control_1 |= RXD_OWN_XENA;
2651 ring->rx_bufs_left += 1;
2656 /* Transfer ownership of first descriptor to adapter just before
2657 * exiting. Before that, use memory barrier so that ownership
2658 * and other fields are seen by adapter correctly.
2662 first_rxdp->Control_1 |= RXD_OWN_XENA;
2668 swstats->pci_map_fail_cnt++;
2669 swstats->mem_freed += skb->truesize;
2670 dev_kfree_skb_irq(skb);
2674 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2676 struct net_device *dev = sp->dev;
2678 struct sk_buff *skb;
2682 struct mac_info *mac_control = &sp->mac_control;
2683 struct stat_block *stats = mac_control->stats_info;
2684 struct swStat *swstats = &stats->sw_stat;
2686 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2687 rxdp = mac_control->rings[ring_no].
2688 rx_blocks[blk].rxds[j].virt_addr;
2689 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2692 if (sp->rxd_mode == RXD_MODE_1) {
2693 rxdp1 = (struct RxD1 *)rxdp;
2694 pci_unmap_single(sp->pdev,
2695 (dma_addr_t)rxdp1->Buffer0_ptr,
2697 HEADER_ETHERNET_II_802_3_SIZE +
2698 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2699 PCI_DMA_FROMDEVICE);
2700 memset(rxdp, 0, sizeof(struct RxD1));
2701 } else if (sp->rxd_mode == RXD_MODE_3B) {
2702 rxdp3 = (struct RxD3 *)rxdp;
2703 pci_unmap_single(sp->pdev,
2704 (dma_addr_t)rxdp3->Buffer0_ptr,
2706 PCI_DMA_FROMDEVICE);
2707 pci_unmap_single(sp->pdev,
2708 (dma_addr_t)rxdp3->Buffer1_ptr,
2710 PCI_DMA_FROMDEVICE);
2711 pci_unmap_single(sp->pdev,
2712 (dma_addr_t)rxdp3->Buffer2_ptr,
2714 PCI_DMA_FROMDEVICE);
2715 memset(rxdp, 0, sizeof(struct RxD3));
2717 swstats->mem_freed += skb->truesize;
2719 mac_control->rings[ring_no].rx_bufs_left -= 1;
2724 * free_rx_buffers - Frees all Rx buffers
2725 * @sp: device private variable.
2727 * This function will free all Rx buffers allocated by host.
2732 static void free_rx_buffers(struct s2io_nic *sp)
2734 struct net_device *dev = sp->dev;
2735 int i, blk = 0, buf_cnt = 0;
2736 struct config_param *config = &sp->config;
2737 struct mac_info *mac_control = &sp->mac_control;
2739 for (i = 0; i < config->rx_ring_num; i++) {
2740 struct ring_info *ring = &mac_control->rings[i];
2742 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2743 free_rxd_blk(sp, i, blk);
2745 ring->rx_curr_put_info.block_index = 0;
2746 ring->rx_curr_get_info.block_index = 0;
2747 ring->rx_curr_put_info.offset = 0;
2748 ring->rx_curr_get_info.offset = 0;
2749 ring->rx_bufs_left = 0;
2750 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2751 dev->name, buf_cnt, i);
2755 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2757 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2758 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2765 * s2io_poll - Rx interrupt handler for NAPI support
2766 * @napi : pointer to the napi structure.
2767 * @budget : The number of packets that were budgeted to be processed
2768 * during one pass through the 'Poll" function.
2770 * Comes into picture only if NAPI support has been incorporated. It does
2771 * the same thing that rx_intr_handler does, but not in a interrupt context
2772 * also It will process only a given number of packets.
2774 * 0 on success and 1 if there are No Rx packets to be processed.
2777 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2779 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2780 struct net_device *dev = ring->dev;
2781 int pkts_processed = 0;
2782 u8 __iomem *addr = NULL;
2784 struct s2io_nic *nic = netdev_priv(dev);
2785 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2786 int budget_org = budget;
2788 if (unlikely(!is_s2io_card_up(nic)))
2791 pkts_processed = rx_intr_handler(ring, budget);
2792 s2io_chk_rx_buffers(nic, ring);
2794 if (pkts_processed < budget_org) {
2795 napi_complete(napi);
2796 /*Re Enable MSI-Rx Vector*/
2797 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2798 addr += 7 - ring->ring_no;
2799 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2803 return pkts_processed;
2806 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2808 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2809 int pkts_processed = 0;
2810 int ring_pkts_processed, i;
2811 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2812 int budget_org = budget;
2813 struct config_param *config = &nic->config;
2814 struct mac_info *mac_control = &nic->mac_control;
2816 if (unlikely(!is_s2io_card_up(nic)))
2819 for (i = 0; i < config->rx_ring_num; i++) {
2820 struct ring_info *ring = &mac_control->rings[i];
2821 ring_pkts_processed = rx_intr_handler(ring, budget);
2822 s2io_chk_rx_buffers(nic, ring);
2823 pkts_processed += ring_pkts_processed;
2824 budget -= ring_pkts_processed;
2828 if (pkts_processed < budget_org) {
2829 napi_complete(napi);
2830 /* Re enable the Rx interrupts for the ring */
2831 writeq(0, &bar0->rx_traffic_mask);
2832 readl(&bar0->rx_traffic_mask);
2834 return pkts_processed;
2837 #ifdef CONFIG_NET_POLL_CONTROLLER
2839 * s2io_netpoll - netpoll event handler entry point
2840 * @dev : pointer to the device structure.
2842 * This function will be called by upper layer to check for events on the
2843 * interface in situations where interrupts are disabled. It is used for
2844 * specific in-kernel networking tasks, such as remote consoles and kernel
2845 * debugging over the network (example netdump in RedHat).
2847 static void s2io_netpoll(struct net_device *dev)
2849 struct s2io_nic *nic = netdev_priv(dev);
2850 const int irq = nic->pdev->irq;
2851 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2852 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2854 struct config_param *config = &nic->config;
2855 struct mac_info *mac_control = &nic->mac_control;
2857 if (pci_channel_offline(nic->pdev))
2862 writeq(val64, &bar0->rx_traffic_int);
2863 writeq(val64, &bar0->tx_traffic_int);
2865 /* we need to free up the transmitted skbufs or else netpoll will
2866 * run out of skbs and will fail and eventually netpoll application such
2867 * as netdump will fail.
2869 for (i = 0; i < config->tx_fifo_num; i++)
2870 tx_intr_handler(&mac_control->fifos[i]);
2872 /* check for received packet and indicate up to network */
2873 for (i = 0; i < config->rx_ring_num; i++) {
2874 struct ring_info *ring = &mac_control->rings[i];
2876 rx_intr_handler(ring, 0);
2879 for (i = 0; i < config->rx_ring_num; i++) {
2880 struct ring_info *ring = &mac_control->rings[i];
2882 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2884 "%s: Out of memory in Rx Netpoll!!\n",
2894 * rx_intr_handler - Rx interrupt handler
2895 * @ring_info: per ring structure.
2896 * @budget: budget for napi processing.
2898 * If the interrupt is because of a received frame or if the
2899 * receive ring contains fresh as yet un-processed frames,this function is
2900 * called. It picks out the RxD at which place the last Rx processing had
2901 * stopped and sends the skb to the OSM's Rx handler and then increments
2904 * No. of napi packets processed.
2906 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2908 int get_block, put_block;
2909 struct rx_curr_get_info get_info, put_info;
2911 struct sk_buff *skb;
2912 int pkt_cnt = 0, napi_pkts = 0;
2917 get_info = ring_data->rx_curr_get_info;
2918 get_block = get_info.block_index;
2919 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2920 put_block = put_info.block_index;
2921 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2923 while (RXD_IS_UP2DT(rxdp)) {
2925 * If your are next to put index then it's
2926 * FIFO full condition
2928 if ((get_block == put_block) &&
2929 (get_info.offset + 1) == put_info.offset) {
2930 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2931 ring_data->dev->name);
2934 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2936 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2937 ring_data->dev->name);
2940 if (ring_data->rxd_mode == RXD_MODE_1) {
2941 rxdp1 = (struct RxD1 *)rxdp;
2942 pci_unmap_single(ring_data->pdev, (dma_addr_t)
2945 HEADER_ETHERNET_II_802_3_SIZE +
2948 PCI_DMA_FROMDEVICE);
2949 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
2950 rxdp3 = (struct RxD3 *)rxdp;
2951 pci_dma_sync_single_for_cpu(ring_data->pdev,
2952 (dma_addr_t)rxdp3->Buffer0_ptr,
2954 PCI_DMA_FROMDEVICE);
2955 pci_unmap_single(ring_data->pdev,
2956 (dma_addr_t)rxdp3->Buffer2_ptr,
2958 PCI_DMA_FROMDEVICE);
2960 prefetch(skb->data);
2961 rx_osm_handler(ring_data, rxdp);
2963 ring_data->rx_curr_get_info.offset = get_info.offset;
2964 rxdp = ring_data->rx_blocks[get_block].
2965 rxds[get_info.offset].virt_addr;
2966 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
2967 get_info.offset = 0;
2968 ring_data->rx_curr_get_info.offset = get_info.offset;
2970 if (get_block == ring_data->block_count)
2972 ring_data->rx_curr_get_info.block_index = get_block;
2973 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2976 if (ring_data->nic->config.napi) {
2983 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2986 if (ring_data->lro) {
2987 /* Clear all LRO sessions before exiting */
2988 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
2989 struct lro *lro = &ring_data->lro0_n[i];
2991 update_L3L4_header(ring_data->nic, lro);
2992 queue_rx_frame(lro->parent, lro->vlan_tag);
2993 clear_lro_session(lro);
3001 * tx_intr_handler - Transmit interrupt handler
3002 * @nic : device private variable
3004 * If an interrupt was raised to indicate DMA complete of the
3005 * Tx packet, this function is called. It identifies the last TxD
3006 * whose buffer was freed and frees all skbs whose data have already
3007 * DMA'ed into the NICs internal memory.
3012 static void tx_intr_handler(struct fifo_info *fifo_data)
3014 struct s2io_nic *nic = fifo_data->nic;
3015 struct tx_curr_get_info get_info, put_info;
3016 struct sk_buff *skb = NULL;
3019 unsigned long flags = 0;
3021 struct stat_block *stats = nic->mac_control.stats_info;
3022 struct swStat *swstats = &stats->sw_stat;
3024 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3027 get_info = fifo_data->tx_curr_get_info;
3028 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3029 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3030 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3031 (get_info.offset != put_info.offset) &&
3032 (txdlp->Host_Control)) {
3033 /* Check for TxD errors */
3034 if (txdlp->Control_1 & TXD_T_CODE) {
3035 unsigned long long err;
3036 err = txdlp->Control_1 & TXD_T_CODE;
3038 swstats->parity_err_cnt++;
3041 /* update t_code statistics */
3042 err_mask = err >> 48;
3045 swstats->tx_buf_abort_cnt++;
3049 swstats->tx_desc_abort_cnt++;
3053 swstats->tx_parity_err_cnt++;
3057 swstats->tx_link_loss_cnt++;
3061 swstats->tx_list_proc_err_cnt++;
3066 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3068 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3069 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3075 /* Updating the statistics block */
3076 swstats->mem_freed += skb->truesize;
3077 dev_kfree_skb_irq(skb);
3080 if (get_info.offset == get_info.fifo_len + 1)
3081 get_info.offset = 0;
3082 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3083 fifo_data->tx_curr_get_info.offset = get_info.offset;
3086 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3088 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3092 * s2io_mdio_write - Function to write in to MDIO registers
3093 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3094 * @addr : address value
3095 * @value : data value
3096 * @dev : pointer to net_device structure
3098 * This function is used to write values to the MDIO registers
3101 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3102 struct net_device *dev)
3105 struct s2io_nic *sp = netdev_priv(dev);
3106 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3108 /* address transaction */
3109 val64 = MDIO_MMD_INDX_ADDR(addr) |
3110 MDIO_MMD_DEV_ADDR(mmd_type) |
3111 MDIO_MMS_PRT_ADDR(0x0);
3112 writeq(val64, &bar0->mdio_control);
3113 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3114 writeq(val64, &bar0->mdio_control);
3117 /* Data transaction */
3118 val64 = MDIO_MMD_INDX_ADDR(addr) |
3119 MDIO_MMD_DEV_ADDR(mmd_type) |
3120 MDIO_MMS_PRT_ADDR(0x0) |
3121 MDIO_MDIO_DATA(value) |
3122 MDIO_OP(MDIO_OP_WRITE_TRANS);
3123 writeq(val64, &bar0->mdio_control);
3124 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3125 writeq(val64, &bar0->mdio_control);
3128 val64 = MDIO_MMD_INDX_ADDR(addr) |
3129 MDIO_MMD_DEV_ADDR(mmd_type) |
3130 MDIO_MMS_PRT_ADDR(0x0) |
3131 MDIO_OP(MDIO_OP_READ_TRANS);
3132 writeq(val64, &bar0->mdio_control);
3133 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3134 writeq(val64, &bar0->mdio_control);
3139 * s2io_mdio_read - Function to write in to MDIO registers
3140 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3141 * @addr : address value
3142 * @dev : pointer to net_device structure
3144 * This function is used to read values to the MDIO registers
3147 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3151 struct s2io_nic *sp = netdev_priv(dev);
3152 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3154 /* address transaction */
3155 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3156 | MDIO_MMD_DEV_ADDR(mmd_type)
3157 | MDIO_MMS_PRT_ADDR(0x0));
3158 writeq(val64, &bar0->mdio_control);
3159 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3160 writeq(val64, &bar0->mdio_control);
3163 /* Data transaction */
3164 val64 = MDIO_MMD_INDX_ADDR(addr) |
3165 MDIO_MMD_DEV_ADDR(mmd_type) |
3166 MDIO_MMS_PRT_ADDR(0x0) |
3167 MDIO_OP(MDIO_OP_READ_TRANS);
3168 writeq(val64, &bar0->mdio_control);
3169 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3170 writeq(val64, &bar0->mdio_control);
3173 /* Read the value from regs */
3174 rval64 = readq(&bar0->mdio_control);
3175 rval64 = rval64 & 0xFFFF0000;
3176 rval64 = rval64 >> 16;
3181 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3182 * @counter : counter value to be updated
3183 * @flag : flag to indicate the status
3184 * @type : counter type
3186 * This function is to check the status of the xpak counters value
3190 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3196 for (i = 0; i < index; i++)
3200 *counter = *counter + 1;
3201 val64 = *regs_stat & mask;
3202 val64 = val64 >> (index * 0x2);
3208 "Take Xframe NIC out of service.\n");
3210 "Excessive temperatures may result in premature transceiver failure.\n");
3214 "Take Xframe NIC out of service.\n");
3216 "Excessive bias currents may indicate imminent laser diode failure.\n");
3220 "Take Xframe NIC out of service.\n");
3222 "Excessive laser output power may saturate far-end receiver.\n");
3226 "Incorrect XPAK Alarm type\n");
3230 val64 = val64 << (index * 0x2);
3231 *regs_stat = (*regs_stat & (~mask)) | (val64);
3234 *regs_stat = *regs_stat & (~mask);
3239 * s2io_updt_xpak_counter - Function to update the xpak counters
3240 * @dev : pointer to net_device struct
3242 * This function is to upate the status of the xpak counters value
3245 static void s2io_updt_xpak_counter(struct net_device *dev)
3253 struct s2io_nic *sp = netdev_priv(dev);
3254 struct stat_block *stats = sp->mac_control.stats_info;
3255 struct xpakStat *xstats = &stats->xpak_stat;
3257 /* Check the communication with the MDIO slave */
3260 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3261 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3263 "ERR: MDIO slave access failed - Returned %llx\n",
3264 (unsigned long long)val64);
3268 /* Check for the expected value of control reg 1 */
3269 if (val64 != MDIO_CTRL1_SPEED10G) {
3270 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3271 "Returned: %llx- Expected: 0x%x\n",
3272 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3276 /* Loading the DOM register to MDIO register */
3278 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3279 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3281 /* Reading the Alarm flags */
3284 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3286 flag = CHECKBIT(val64, 0x7);
3288 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3289 &xstats->xpak_regs_stat,
3292 if (CHECKBIT(val64, 0x6))
3293 xstats->alarm_transceiver_temp_low++;
3295 flag = CHECKBIT(val64, 0x3);
3297 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3298 &xstats->xpak_regs_stat,
3301 if (CHECKBIT(val64, 0x2))
3302 xstats->alarm_laser_bias_current_low++;
3304 flag = CHECKBIT(val64, 0x1);
3306 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3307 &xstats->xpak_regs_stat,
3310 if (CHECKBIT(val64, 0x0))
3311 xstats->alarm_laser_output_power_low++;
3313 /* Reading the Warning flags */
3316 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3318 if (CHECKBIT(val64, 0x7))
3319 xstats->warn_transceiver_temp_high++;
3321 if (CHECKBIT(val64, 0x6))
3322 xstats->warn_transceiver_temp_low++;
3324 if (CHECKBIT(val64, 0x3))
3325 xstats->warn_laser_bias_current_high++;
3327 if (CHECKBIT(val64, 0x2))
3328 xstats->warn_laser_bias_current_low++;
3330 if (CHECKBIT(val64, 0x1))
3331 xstats->warn_laser_output_power_high++;
3333 if (CHECKBIT(val64, 0x0))
3334 xstats->warn_laser_output_power_low++;
3338 * wait_for_cmd_complete - waits for a command to complete.
3339 * @sp : private member of the device structure, which is a pointer to the
3340 * s2io_nic structure.
3341 * Description: Function that waits for a command to Write into RMAC
3342 * ADDR DATA registers to be completed and returns either success or
3343 * error depending on whether the command was complete or not.
3345 * SUCCESS on success and FAILURE on failure.
3348 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3351 int ret = FAILURE, cnt = 0, delay = 1;
3354 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3358 val64 = readq(addr);
3359 if (bit_state == S2IO_BIT_RESET) {
3360 if (!(val64 & busy_bit)) {
3365 if (val64 & busy_bit) {
3382 * check_pci_device_id - Checks if the device id is supported
3384 * Description: Function to check if the pci device id is supported by driver.
3385 * Return value: Actual device id if supported else PCI_ANY_ID
3387 static u16 check_pci_device_id(u16 id)
3390 case PCI_DEVICE_ID_HERC_WIN:
3391 case PCI_DEVICE_ID_HERC_UNI:
3392 return XFRAME_II_DEVICE;
3393 case PCI_DEVICE_ID_S2IO_UNI:
3394 case PCI_DEVICE_ID_S2IO_WIN:
3395 return XFRAME_I_DEVICE;
3402 * s2io_reset - Resets the card.
3403 * @sp : private member of the device structure.
3404 * Description: Function to Reset the card. This function then also
3405 * restores the previously saved PCI configuration space registers as
3406 * the card reset also resets the configuration space.
3411 static void s2io_reset(struct s2io_nic *sp)
3413 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3418 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3419 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3420 struct stat_block *stats;
3421 struct swStat *swstats;
3423 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3424 __func__, pci_name(sp->pdev));
3426 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3427 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3429 val64 = SW_RESET_ALL;
3430 writeq(val64, &bar0->sw_reset);
3431 if (strstr(sp->product_name, "CX4"))
3434 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3436 /* Restore the PCI state saved during initialization. */
3437 pci_restore_state(sp->pdev);
3438 pci_save_state(sp->pdev);
3439 pci_read_config_word(sp->pdev, 0x2, &val16);
3440 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3445 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3446 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3448 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3452 /* Set swapper to enable I/O register access */
3453 s2io_set_swapper(sp);
3455 /* restore mac_addr entries */
3456 do_s2io_restore_unicast_mc(sp);
3458 /* Restore the MSIX table entries from local variables */
3459 restore_xmsi_data(sp);
3461 /* Clear certain PCI/PCI-X fields after reset */
3462 if (sp->device_type == XFRAME_II_DEVICE) {
3463 /* Clear "detected parity error" bit */
3464 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3466 /* Clearing PCIX Ecc status register */
3467 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3469 /* Clearing PCI_STATUS error reflected here */
3470 writeq(s2BIT(62), &bar0->txpic_int_reg);
3473 /* Reset device statistics maintained by OS */
3474 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3476 stats = sp->mac_control.stats_info;
3477 swstats = &stats->sw_stat;
3479 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3480 up_cnt = swstats->link_up_cnt;
3481 down_cnt = swstats->link_down_cnt;
3482 up_time = swstats->link_up_time;
3483 down_time = swstats->link_down_time;
3484 reset_cnt = swstats->soft_reset_cnt;
3485 mem_alloc_cnt = swstats->mem_allocated;
3486 mem_free_cnt = swstats->mem_freed;
3487 watchdog_cnt = swstats->watchdog_timer_cnt;
3489 memset(stats, 0, sizeof(struct stat_block));
3491 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3492 swstats->link_up_cnt = up_cnt;
3493 swstats->link_down_cnt = down_cnt;
3494 swstats->link_up_time = up_time;
3495 swstats->link_down_time = down_time;
3496 swstats->soft_reset_cnt = reset_cnt;
3497 swstats->mem_allocated = mem_alloc_cnt;
3498 swstats->mem_freed = mem_free_cnt;
3499 swstats->watchdog_timer_cnt = watchdog_cnt;
3501 /* SXE-002: Configure link and activity LED to turn it off */
3502 subid = sp->pdev->subsystem_device;
3503 if (((subid & 0xFF) >= 0x07) &&
3504 (sp->device_type == XFRAME_I_DEVICE)) {
3505 val64 = readq(&bar0->gpio_control);
3506 val64 |= 0x0000800000000000ULL;
3507 writeq(val64, &bar0->gpio_control);
3508 val64 = 0x0411040400000000ULL;
3509 writeq(val64, (void __iomem *)bar0 + 0x2700);
3513 * Clear spurious ECC interrupts that would have occurred on
3514 * XFRAME II cards after reset.
3516 if (sp->device_type == XFRAME_II_DEVICE) {
3517 val64 = readq(&bar0->pcc_err_reg);
3518 writeq(val64, &bar0->pcc_err_reg);
3521 sp->device_enabled_once = false;
3525 * s2io_set_swapper - to set the swapper controle on the card
3526 * @sp : private member of the device structure,
3527 * pointer to the s2io_nic structure.
3528 * Description: Function to set the swapper control on the card
3529 * correctly depending on the 'endianness' of the system.
3531 * SUCCESS on success and FAILURE on failure.
3534 static int s2io_set_swapper(struct s2io_nic *sp)
3536 struct net_device *dev = sp->dev;
3537 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3538 u64 val64, valt, valr;
3541 * Set proper endian settings and verify the same by reading
3542 * the PIF Feed-back register.
3545 val64 = readq(&bar0->pif_rd_swapper_fb);
3546 if (val64 != 0x0123456789ABCDEFULL) {
3548 static const u64 value[] = {
3549 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3550 0x8100008181000081ULL, /* FE=1, SE=0 */
3551 0x4200004242000042ULL, /* FE=0, SE=1 */
3556 writeq(value[i], &bar0->swapper_ctrl);
3557 val64 = readq(&bar0->pif_rd_swapper_fb);
3558 if (val64 == 0x0123456789ABCDEFULL)
3563 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3564 "feedback read %llx\n",
3565 dev->name, (unsigned long long)val64);
3570 valr = readq(&bar0->swapper_ctrl);
3573 valt = 0x0123456789ABCDEFULL;
3574 writeq(valt, &bar0->xmsi_address);
3575 val64 = readq(&bar0->xmsi_address);
3577 if (val64 != valt) {
3579 static const u64 value[] = {
3580 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3581 0x0081810000818100ULL, /* FE=1, SE=0 */
3582 0x0042420000424200ULL, /* FE=0, SE=1 */
3587 writeq((value[i] | valr), &bar0->swapper_ctrl);
3588 writeq(valt, &bar0->xmsi_address);
3589 val64 = readq(&bar0->xmsi_address);
3595 unsigned long long x = val64;
3597 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3601 val64 = readq(&bar0->swapper_ctrl);
3602 val64 &= 0xFFFF000000000000ULL;
3606 * The device by default set to a big endian format, so a
3607 * big endian driver need not set anything.
3609 val64 |= (SWAPPER_CTRL_TXP_FE |
3610 SWAPPER_CTRL_TXP_SE |
3611 SWAPPER_CTRL_TXD_R_FE |
3612 SWAPPER_CTRL_TXD_W_FE |
3613 SWAPPER_CTRL_TXF_R_FE |
3614 SWAPPER_CTRL_RXD_R_FE |
3615 SWAPPER_CTRL_RXD_W_FE |
3616 SWAPPER_CTRL_RXF_W_FE |
3617 SWAPPER_CTRL_XMSI_FE |
3618 SWAPPER_CTRL_STATS_FE |
3619 SWAPPER_CTRL_STATS_SE);
3620 if (sp->config.intr_type == INTA)
3621 val64 |= SWAPPER_CTRL_XMSI_SE;
3622 writeq(val64, &bar0->swapper_ctrl);
3625 * Initially we enable all bits to make it accessible by the
3626 * driver, then we selectively enable only those bits that
3629 val64 |= (SWAPPER_CTRL_TXP_FE |
3630 SWAPPER_CTRL_TXP_SE |
3631 SWAPPER_CTRL_TXD_R_FE |
3632 SWAPPER_CTRL_TXD_R_SE |
3633 SWAPPER_CTRL_TXD_W_FE |
3634 SWAPPER_CTRL_TXD_W_SE |
3635 SWAPPER_CTRL_TXF_R_FE |
3636 SWAPPER_CTRL_RXD_R_FE |
3637 SWAPPER_CTRL_RXD_R_SE |
3638 SWAPPER_CTRL_RXD_W_FE |
3639 SWAPPER_CTRL_RXD_W_SE |
3640 SWAPPER_CTRL_RXF_W_FE |
3641 SWAPPER_CTRL_XMSI_FE |
3642 SWAPPER_CTRL_STATS_FE |
3643 SWAPPER_CTRL_STATS_SE);
3644 if (sp->config.intr_type == INTA)
3645 val64 |= SWAPPER_CTRL_XMSI_SE;
3646 writeq(val64, &bar0->swapper_ctrl);
3648 val64 = readq(&bar0->swapper_ctrl);
3651 * Verifying if endian settings are accurate by reading a
3652 * feedback register.
3654 val64 = readq(&bar0->pif_rd_swapper_fb);
3655 if (val64 != 0x0123456789ABCDEFULL) {
3656 /* Endian settings are incorrect, calls for another dekko. */
3658 "%s: Endian settings are wrong, feedback read %llx\n",
3659 dev->name, (unsigned long long)val64);
3666 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3668 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3670 int ret = 0, cnt = 0;
3673 val64 = readq(&bar0->xmsi_access);
3674 if (!(val64 & s2BIT(15)))
3680 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3687 static void restore_xmsi_data(struct s2io_nic *nic)
3689 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3693 if (nic->device_type == XFRAME_I_DEVICE)
3696 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3697 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3698 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3699 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3700 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3701 writeq(val64, &bar0->xmsi_access);
3702 if (wait_for_msix_trans(nic, msix_index)) {
3703 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3704 __func__, msix_index);
3710 static void store_xmsi_data(struct s2io_nic *nic)
3712 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3713 u64 val64, addr, data;
3716 if (nic->device_type == XFRAME_I_DEVICE)
3719 /* Store and display */
3720 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3721 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3722 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3723 writeq(val64, &bar0->xmsi_access);
3724 if (wait_for_msix_trans(nic, msix_index)) {
3725 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3726 __func__, msix_index);
3729 addr = readq(&bar0->xmsi_address);
3730 data = readq(&bar0->xmsi_data);
3732 nic->msix_info[i].addr = addr;
3733 nic->msix_info[i].data = data;
3738 static int s2io_enable_msi_x(struct s2io_nic *nic)
3740 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3742 u16 msi_control; /* Temp variable */
3743 int ret, i, j, msix_indx = 1;
3745 struct stat_block *stats = nic->mac_control.stats_info;
3746 struct swStat *swstats = &stats->sw_stat;
3748 size = nic->num_entries * sizeof(struct msix_entry);
3749 nic->entries = kzalloc(size, GFP_KERNEL);
3750 if (!nic->entries) {
3751 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3753 swstats->mem_alloc_fail_cnt++;
3756 swstats->mem_allocated += size;
3758 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3759 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3760 if (!nic->s2io_entries) {
3761 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3763 swstats->mem_alloc_fail_cnt++;
3764 kfree(nic->entries);
3766 += (nic->num_entries * sizeof(struct msix_entry));
3769 swstats->mem_allocated += size;
3771 nic->entries[0].entry = 0;
3772 nic->s2io_entries[0].entry = 0;
3773 nic->s2io_entries[0].in_use = MSIX_FLG;
3774 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3775 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3777 for (i = 1; i < nic->num_entries; i++) {
3778 nic->entries[i].entry = ((i - 1) * 8) + 1;
3779 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3780 nic->s2io_entries[i].arg = NULL;
3781 nic->s2io_entries[i].in_use = 0;
3784 rx_mat = readq(&bar0->rx_mat);
3785 for (j = 0; j < nic->config.rx_ring_num; j++) {
3786 rx_mat |= RX_MAT_SET(j, msix_indx);
3787 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3788 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3789 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3792 writeq(rx_mat, &bar0->rx_mat);
3793 readq(&bar0->rx_mat);
3795 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3796 /* We fail init if error or we get less vectors than min required */
3798 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3799 kfree(nic->entries);
3800 swstats->mem_freed += nic->num_entries *
3801 sizeof(struct msix_entry);
3802 kfree(nic->s2io_entries);
3803 swstats->mem_freed += nic->num_entries *
3804 sizeof(struct s2io_msix_entry);
3805 nic->entries = NULL;
3806 nic->s2io_entries = NULL;
3811 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3812 * in the herc NIC. (Temp change, needs to be removed later)
3814 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3815 msi_control |= 0x1; /* Enable MSI */
3816 pci_write_config_word(nic->pdev, 0x42, msi_control);
3821 /* Handle software interrupt used during MSI(X) test */
3822 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3824 struct s2io_nic *sp = dev_id;
3826 sp->msi_detected = 1;
3827 wake_up(&sp->msi_wait);
3832 /* Test interrupt path by forcing a a software IRQ */
3833 static int s2io_test_msi(struct s2io_nic *sp)
3835 struct pci_dev *pdev = sp->pdev;
3836 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3840 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3843 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3844 sp->dev->name, pci_name(pdev), pdev->irq);
3848 init_waitqueue_head(&sp->msi_wait);
3849 sp->msi_detected = 0;
3851 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3852 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3853 val64 |= SCHED_INT_CTRL_TIMER_EN;
3854 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3855 writeq(val64, &bar0->scheduled_int_ctrl);
3857 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3859 if (!sp->msi_detected) {
3860 /* MSI(X) test failed, go back to INTx mode */
3861 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3862 "using MSI(X) during test\n",
3863 sp->dev->name, pci_name(pdev));
3868 free_irq(sp->entries[1].vector, sp);
3870 writeq(saved64, &bar0->scheduled_int_ctrl);
3875 static void remove_msix_isr(struct s2io_nic *sp)
3880 for (i = 0; i < sp->num_entries; i++) {
3881 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3882 int vector = sp->entries[i].vector;
3883 void *arg = sp->s2io_entries[i].arg;
3884 free_irq(vector, arg);
3889 kfree(sp->s2io_entries);
3891 sp->s2io_entries = NULL;
3893 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3894 msi_control &= 0xFFFE; /* Disable MSI */
3895 pci_write_config_word(sp->pdev, 0x42, msi_control);
3897 pci_disable_msix(sp->pdev);
3900 static void remove_inta_isr(struct s2io_nic *sp)
3902 free_irq(sp->pdev->irq, sp->dev);
3905 /* ********************************************************* *
3906 * Functions defined below concern the OS part of the driver *
3907 * ********************************************************* */
3910 * s2io_open - open entry point of the driver
3911 * @dev : pointer to the device structure.
3913 * This function is the open entry point of the driver. It mainly calls a
3914 * function to allocate Rx buffers and inserts them into the buffer
3915 * descriptors and then enables the Rx part of the NIC.
3917 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3921 static int s2io_open(struct net_device *dev)
3923 struct s2io_nic *sp = netdev_priv(dev);
3924 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3928 * Make sure you have link off by default every time
3929 * Nic is initialized
3931 netif_carrier_off(dev);
3932 sp->last_link_state = 0;
3934 /* Initialize H/W and enable interrupts */
3935 err = s2io_card_up(sp);
3937 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3939 goto hw_init_failed;
3942 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3943 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3946 goto hw_init_failed;
3948 s2io_start_all_tx_queue(sp);
3952 if (sp->config.intr_type == MSI_X) {
3955 swstats->mem_freed += sp->num_entries *
3956 sizeof(struct msix_entry);
3958 if (sp->s2io_entries) {
3959 kfree(sp->s2io_entries);
3960 swstats->mem_freed += sp->num_entries *
3961 sizeof(struct s2io_msix_entry);
3968 * s2io_close -close entry point of the driver
3969 * @dev : device pointer.
3971 * This is the stop entry point of the driver. It needs to undo exactly
3972 * whatever was done by the open entry point,thus it's usually referred to
3973 * as the close function.Among other things this function mainly stops the
3974 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3976 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3980 static int s2io_close(struct net_device *dev)
3982 struct s2io_nic *sp = netdev_priv(dev);
3983 struct config_param *config = &sp->config;
3987 /* Return if the device is already closed *
3988 * Can happen when s2io_card_up failed in change_mtu *
3990 if (!is_s2io_card_up(sp))
3993 s2io_stop_all_tx_queue(sp);
3994 /* delete all populated mac entries */
3995 for (offset = 1; offset < config->max_mc_addr; offset++) {
3996 tmp64 = do_s2io_read_unicast_mc(sp, offset);
3997 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3998 do_s2io_delete_unicast_mc(sp, tmp64);
4007 * s2io_xmit - Tx entry point of te driver
4008 * @skb : the socket buffer containing the Tx data.
4009 * @dev : device pointer.
4011 * This function is the Tx entry point of the driver. S2IO NIC supports
4012 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4013 * NOTE: when device can't queue the pkt,just the trans_start variable will
4016 * 0 on success & 1 on failure.
4019 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4021 struct s2io_nic *sp = netdev_priv(dev);
4022 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4025 struct TxFIFO_element __iomem *tx_fifo;
4026 unsigned long flags = 0;
4028 struct fifo_info *fifo = NULL;
4029 int do_spin_lock = 1;
4031 int enable_per_list_interrupt = 0;
4032 struct config_param *config = &sp->config;
4033 struct mac_info *mac_control = &sp->mac_control;
4034 struct stat_block *stats = mac_control->stats_info;
4035 struct swStat *swstats = &stats->sw_stat;
4037 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4039 if (unlikely(skb->len <= 0)) {
4040 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4041 dev_kfree_skb_any(skb);
4042 return NETDEV_TX_OK;
4045 if (!is_s2io_card_up(sp)) {
4046 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4049 return NETDEV_TX_OK;
4053 if (vlan_tx_tag_present(skb))
4054 vlan_tag = vlan_tx_tag_get(skb);
4055 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4056 if (skb->protocol == htons(ETH_P_IP)) {
4061 if (!ip_is_fragment(ip)) {
4062 th = (struct tcphdr *)(((unsigned char *)ip) +
4065 if (ip->protocol == IPPROTO_TCP) {
4066 queue_len = sp->total_tcp_fifos;
4067 queue = (ntohs(th->source) +
4069 sp->fifo_selector[queue_len - 1];
4070 if (queue >= queue_len)
4071 queue = queue_len - 1;
4072 } else if (ip->protocol == IPPROTO_UDP) {
4073 queue_len = sp->total_udp_fifos;
4074 queue = (ntohs(th->source) +
4076 sp->fifo_selector[queue_len - 1];
4077 if (queue >= queue_len)
4078 queue = queue_len - 1;
4079 queue += sp->udp_fifo_idx;
4080 if (skb->len > 1024)
4081 enable_per_list_interrupt = 1;
4086 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4087 /* get fifo number based on skb->priority value */
4088 queue = config->fifo_mapping
4089 [skb->priority & (MAX_TX_FIFOS - 1)];
4090 fifo = &mac_control->fifos[queue];
4093 spin_lock_irqsave(&fifo->tx_lock, flags);
4095 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4096 return NETDEV_TX_LOCKED;
4099 if (sp->config.multiq) {
4100 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4101 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4102 return NETDEV_TX_BUSY;
4104 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4105 if (netif_queue_stopped(dev)) {
4106 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4107 return NETDEV_TX_BUSY;
4111 put_off = (u16)fifo->tx_curr_put_info.offset;
4112 get_off = (u16)fifo->tx_curr_get_info.offset;
4113 txdp = fifo->list_info[put_off].list_virt_addr;
4115 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4116 /* Avoid "put" pointer going beyond "get" pointer */
4117 if (txdp->Host_Control ||
4118 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4119 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4120 s2io_stop_tx_queue(sp, fifo->fifo_no);
4122 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4123 return NETDEV_TX_OK;
4126 offload_type = s2io_offload_type(skb);
4127 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4128 txdp->Control_1 |= TXD_TCP_LSO_EN;
4129 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4131 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4132 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4136 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4137 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4138 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4139 if (enable_per_list_interrupt)
4140 if (put_off & (queue_len >> 5))
4141 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4143 txdp->Control_2 |= TXD_VLAN_ENABLE;
4144 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4147 frg_len = skb_headlen(skb);
4148 if (offload_type == SKB_GSO_UDP) {
4151 ufo_size = s2io_udp_mss(skb);
4153 txdp->Control_1 |= TXD_UFO_EN;
4154 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4155 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4157 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4158 fifo->ufo_in_band_v[put_off] =
4159 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4161 fifo->ufo_in_band_v[put_off] =
4162 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4164 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4165 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4166 fifo->ufo_in_band_v,
4169 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4170 goto pci_map_failed;
4174 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4175 frg_len, PCI_DMA_TODEVICE);
4176 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4177 goto pci_map_failed;
4179 txdp->Host_Control = (unsigned long)skb;
4180 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4181 if (offload_type == SKB_GSO_UDP)
4182 txdp->Control_1 |= TXD_UFO_EN;
4184 frg_cnt = skb_shinfo(skb)->nr_frags;
4185 /* For fragmented SKB. */
4186 for (i = 0; i < frg_cnt; i++) {
4187 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4188 /* A '0' length fragment will be ignored */
4189 if (!skb_frag_size(frag))
4192 txdp->Buffer_Pointer = (u64)skb_frag_dma_map(&sp->pdev->dev,
4194 skb_frag_size(frag),
4196 txdp->Control_1 = TXD_BUFFER0_SIZE(skb_frag_size(frag));
4197 if (offload_type == SKB_GSO_UDP)
4198 txdp->Control_1 |= TXD_UFO_EN;
4200 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4202 if (offload_type == SKB_GSO_UDP)
4203 frg_cnt++; /* as Txd0 was used for inband header */
4205 tx_fifo = mac_control->tx_FIFO_start[queue];
4206 val64 = fifo->list_info[put_off].list_phy_addr;
4207 writeq(val64, &tx_fifo->TxDL_Pointer);
4209 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4212 val64 |= TX_FIFO_SPECIAL_FUNC;
4214 writeq(val64, &tx_fifo->List_Control);
4219 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4221 fifo->tx_curr_put_info.offset = put_off;
4223 /* Avoid "put" pointer going beyond "get" pointer */
4224 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4225 swstats->fifo_full_cnt++;
4227 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4229 s2io_stop_tx_queue(sp, fifo->fifo_no);
4231 swstats->mem_allocated += skb->truesize;
4232 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4234 if (sp->config.intr_type == MSI_X)
4235 tx_intr_handler(fifo);
4237 return NETDEV_TX_OK;
4240 swstats->pci_map_fail_cnt++;
4241 s2io_stop_tx_queue(sp, fifo->fifo_no);
4242 swstats->mem_freed += skb->truesize;
4244 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4245 return NETDEV_TX_OK;
4249 s2io_alarm_handle(unsigned long data)
4251 struct s2io_nic *sp = (struct s2io_nic *)data;
4252 struct net_device *dev = sp->dev;
4254 s2io_handle_errors(dev);
4255 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4258 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4260 struct ring_info *ring = (struct ring_info *)dev_id;
4261 struct s2io_nic *sp = ring->nic;
4262 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4264 if (unlikely(!is_s2io_card_up(sp)))
4267 if (sp->config.napi) {
4268 u8 __iomem *addr = NULL;
4271 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4272 addr += (7 - ring->ring_no);
4273 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4276 napi_schedule(&ring->napi);
4278 rx_intr_handler(ring, 0);
4279 s2io_chk_rx_buffers(sp, ring);
4285 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4288 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4289 struct s2io_nic *sp = fifos->nic;
4290 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4291 struct config_param *config = &sp->config;
4294 if (unlikely(!is_s2io_card_up(sp)))
4297 reason = readq(&bar0->general_int_status);
4298 if (unlikely(reason == S2IO_MINUS_ONE))
4299 /* Nothing much can be done. Get out */
4302 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4303 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4305 if (reason & GEN_INTR_TXPIC)
4306 s2io_txpic_intr_handle(sp);
4308 if (reason & GEN_INTR_TXTRAFFIC)
4309 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4311 for (i = 0; i < config->tx_fifo_num; i++)
4312 tx_intr_handler(&fifos[i]);
4314 writeq(sp->general_int_mask, &bar0->general_int_mask);
4315 readl(&bar0->general_int_status);
4318 /* The interrupt was not raised by us */
4322 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4324 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4327 val64 = readq(&bar0->pic_int_status);
4328 if (val64 & PIC_INT_GPIO) {
4329 val64 = readq(&bar0->gpio_int_reg);
4330 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4331 (val64 & GPIO_INT_REG_LINK_UP)) {
4333 * This is unstable state so clear both up/down
4334 * interrupt and adapter to re-evaluate the link state.
4336 val64 |= GPIO_INT_REG_LINK_DOWN;
4337 val64 |= GPIO_INT_REG_LINK_UP;
4338 writeq(val64, &bar0->gpio_int_reg);
4339 val64 = readq(&bar0->gpio_int_mask);
4340 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4341 GPIO_INT_MASK_LINK_DOWN);
4342 writeq(val64, &bar0->gpio_int_mask);
4343 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4344 val64 = readq(&bar0->adapter_status);
4345 /* Enable Adapter */
4346 val64 = readq(&bar0->adapter_control);
4347 val64 |= ADAPTER_CNTL_EN;
4348 writeq(val64, &bar0->adapter_control);
4349 val64 |= ADAPTER_LED_ON;
4350 writeq(val64, &bar0->adapter_control);
4351 if (!sp->device_enabled_once)
4352 sp->device_enabled_once = 1;
4354 s2io_link(sp, LINK_UP);
4356 * unmask link down interrupt and mask link-up
4359 val64 = readq(&bar0->gpio_int_mask);
4360 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4361 val64 |= GPIO_INT_MASK_LINK_UP;
4362 writeq(val64, &bar0->gpio_int_mask);
4364 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4365 val64 = readq(&bar0->adapter_status);
4366 s2io_link(sp, LINK_DOWN);
4367 /* Link is down so unmaks link up interrupt */
4368 val64 = readq(&bar0->gpio_int_mask);
4369 val64 &= ~GPIO_INT_MASK_LINK_UP;
4370 val64 |= GPIO_INT_MASK_LINK_DOWN;
4371 writeq(val64, &bar0->gpio_int_mask);
4374 val64 = readq(&bar0->adapter_control);
4375 val64 = val64 & (~ADAPTER_LED_ON);
4376 writeq(val64, &bar0->adapter_control);
4379 val64 = readq(&bar0->gpio_int_mask);
4383 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4384 * @value: alarm bits
4385 * @addr: address value
4386 * @cnt: counter variable
4387 * Description: Check for alarm and increment the counter
4389 * 1 - if alarm bit set
4390 * 0 - if alarm bit is not set
4392 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4393 unsigned long long *cnt)
4396 val64 = readq(addr);
4397 if (val64 & value) {
4398 writeq(val64, addr);
4407 * s2io_handle_errors - Xframe error indication handler
4408 * @nic: device private variable
4409 * Description: Handle alarms such as loss of link, single or
4410 * double ECC errors, critical and serious errors.
4414 static void s2io_handle_errors(void *dev_id)
4416 struct net_device *dev = (struct net_device *)dev_id;
4417 struct s2io_nic *sp = netdev_priv(dev);
4418 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4419 u64 temp64 = 0, val64 = 0;
4422 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4423 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4425 if (!is_s2io_card_up(sp))
4428 if (pci_channel_offline(sp->pdev))
4431 memset(&sw_stat->ring_full_cnt, 0,
4432 sizeof(sw_stat->ring_full_cnt));
4434 /* Handling the XPAK counters update */
4435 if (stats->xpak_timer_count < 72000) {
4436 /* waiting for an hour */
4437 stats->xpak_timer_count++;
4439 s2io_updt_xpak_counter(dev);
4440 /* reset the count to zero */
4441 stats->xpak_timer_count = 0;
4444 /* Handling link status change error Intr */
4445 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4446 val64 = readq(&bar0->mac_rmac_err_reg);
4447 writeq(val64, &bar0->mac_rmac_err_reg);
4448 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4449 schedule_work(&sp->set_link_task);
4452 /* In case of a serious error, the device will be Reset. */
4453 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4454 &sw_stat->serious_err_cnt))
4457 /* Check for data parity error */
4458 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4459 &sw_stat->parity_err_cnt))
4462 /* Check for ring full counter */
4463 if (sp->device_type == XFRAME_II_DEVICE) {
4464 val64 = readq(&bar0->ring_bump_counter1);
4465 for (i = 0; i < 4; i++) {
4466 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4467 temp64 >>= 64 - ((i+1)*16);
4468 sw_stat->ring_full_cnt[i] += temp64;
4471 val64 = readq(&bar0->ring_bump_counter2);
4472 for (i = 0; i < 4; i++) {
4473 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4474 temp64 >>= 64 - ((i+1)*16);
4475 sw_stat->ring_full_cnt[i+4] += temp64;
4479 val64 = readq(&bar0->txdma_int_status);
4480 /*check for pfc_err*/
4481 if (val64 & TXDMA_PFC_INT) {
4482 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4483 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4486 &sw_stat->pfc_err_cnt))
4488 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4490 &sw_stat->pfc_err_cnt);
4493 /*check for tda_err*/
4494 if (val64 & TXDMA_TDA_INT) {
4495 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4499 &sw_stat->tda_err_cnt))
4501 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4503 &sw_stat->tda_err_cnt);
4505 /*check for pcc_err*/
4506 if (val64 & TXDMA_PCC_INT) {
4507 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4508 PCC_N_SERR | PCC_6_COF_OV_ERR |
4509 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4510 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4513 &sw_stat->pcc_err_cnt))
4515 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4517 &sw_stat->pcc_err_cnt);
4520 /*check for tti_err*/
4521 if (val64 & TXDMA_TTI_INT) {
4522 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4524 &sw_stat->tti_err_cnt))
4526 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4528 &sw_stat->tti_err_cnt);
4531 /*check for lso_err*/
4532 if (val64 & TXDMA_LSO_INT) {
4533 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4534 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4536 &sw_stat->lso_err_cnt))
4538 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4540 &sw_stat->lso_err_cnt);
4543 /*check for tpa_err*/
4544 if (val64 & TXDMA_TPA_INT) {
4545 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4547 &sw_stat->tpa_err_cnt))
4549 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4551 &sw_stat->tpa_err_cnt);
4554 /*check for sm_err*/
4555 if (val64 & TXDMA_SM_INT) {
4556 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4558 &sw_stat->sm_err_cnt))
4562 val64 = readq(&bar0->mac_int_status);
4563 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4564 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4565 &bar0->mac_tmac_err_reg,
4566 &sw_stat->mac_tmac_err_cnt))
4568 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4569 TMAC_DESC_ECC_SG_ERR |
4570 TMAC_DESC_ECC_DB_ERR,
4571 &bar0->mac_tmac_err_reg,
4572 &sw_stat->mac_tmac_err_cnt);
4575 val64 = readq(&bar0->xgxs_int_status);
4576 if (val64 & XGXS_INT_STATUS_TXGXS) {
4577 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4578 &bar0->xgxs_txgxs_err_reg,
4579 &sw_stat->xgxs_txgxs_err_cnt))
4581 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4582 &bar0->xgxs_txgxs_err_reg,
4583 &sw_stat->xgxs_txgxs_err_cnt);
4586 val64 = readq(&bar0->rxdma_int_status);
4587 if (val64 & RXDMA_INT_RC_INT_M) {
4588 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4590 RC_PRCn_SM_ERR_ALARM |
4591 RC_FTC_SM_ERR_ALARM,
4593 &sw_stat->rc_err_cnt))
4595 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4597 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4598 &sw_stat->rc_err_cnt);
4599 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4602 &bar0->prc_pcix_err_reg,
4603 &sw_stat->prc_pcix_err_cnt))
4605 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4608 &bar0->prc_pcix_err_reg,
4609 &sw_stat->prc_pcix_err_cnt);
4612 if (val64 & RXDMA_INT_RPA_INT_M) {
4613 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4615 &sw_stat->rpa_err_cnt))
4617 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4619 &sw_stat->rpa_err_cnt);
4622 if (val64 & RXDMA_INT_RDA_INT_M) {
4623 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4624 RDA_FRM_ECC_DB_N_AERR |
4627 RDA_RXD_ECC_DB_SERR,
4629 &sw_stat->rda_err_cnt))
4631 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4632 RDA_FRM_ECC_SG_ERR |
4636 &sw_stat->rda_err_cnt);
4639 if (val64 & RXDMA_INT_RTI_INT_M) {
4640 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4642 &sw_stat->rti_err_cnt))
4644 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4646 &sw_stat->rti_err_cnt);
4649 val64 = readq(&bar0->mac_int_status);
4650 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4651 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4652 &bar0->mac_rmac_err_reg,
4653 &sw_stat->mac_rmac_err_cnt))
4655 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4656 RMAC_SINGLE_ECC_ERR |
4657 RMAC_DOUBLE_ECC_ERR,
4658 &bar0->mac_rmac_err_reg,
4659 &sw_stat->mac_rmac_err_cnt);
4662 val64 = readq(&bar0->xgxs_int_status);
4663 if (val64 & XGXS_INT_STATUS_RXGXS) {
4664 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4665 &bar0->xgxs_rxgxs_err_reg,
4666 &sw_stat->xgxs_rxgxs_err_cnt))
4670 val64 = readq(&bar0->mc_int_status);
4671 if (val64 & MC_INT_STATUS_MC_INT) {
4672 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4674 &sw_stat->mc_err_cnt))
4677 /* Handling Ecc errors */
4678 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4679 writeq(val64, &bar0->mc_err_reg);
4680 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4681 sw_stat->double_ecc_errs++;
4682 if (sp->device_type != XFRAME_II_DEVICE) {
4684 * Reset XframeI only if critical error
4687 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4688 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4692 sw_stat->single_ecc_errs++;
4698 s2io_stop_all_tx_queue(sp);
4699 schedule_work(&sp->rst_timer_task);
4700 sw_stat->soft_reset_cnt++;
4704 * s2io_isr - ISR handler of the device .
4705 * @irq: the irq of the device.
4706 * @dev_id: a void pointer to the dev structure of the NIC.
4707 * Description: This function is the ISR handler of the device. It
4708 * identifies the reason for the interrupt and calls the relevant
4709 * service routines. As a contongency measure, this ISR allocates the
4710 * recv buffers, if their numbers are below the panic value which is
4711 * presently set to 25% of the original number of rcv buffers allocated.
4713 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4714 * IRQ_NONE: will be returned if interrupt is not from our device
4716 static irqreturn_t s2io_isr(int irq, void *dev_id)
4718 struct net_device *dev = (struct net_device *)dev_id;
4719 struct s2io_nic *sp = netdev_priv(dev);
4720 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4723 struct mac_info *mac_control;
4724 struct config_param *config;
4726 /* Pretend we handled any irq's from a disconnected card */
4727 if (pci_channel_offline(sp->pdev))
4730 if (!is_s2io_card_up(sp))
4733 config = &sp->config;
4734 mac_control = &sp->mac_control;
4737 * Identify the cause for interrupt and call the appropriate
4738 * interrupt handler. Causes for the interrupt could be;
4743 reason = readq(&bar0->general_int_status);
4745 if (unlikely(reason == S2IO_MINUS_ONE))
4746 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4749 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4750 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4753 if (reason & GEN_INTR_RXTRAFFIC) {
4754 napi_schedule(&sp->napi);
4755 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4756 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4757 readl(&bar0->rx_traffic_int);
4761 * rx_traffic_int reg is an R1 register, writing all 1's
4762 * will ensure that the actual interrupt causing bit
4763 * get's cleared and hence a read can be avoided.
4765 if (reason & GEN_INTR_RXTRAFFIC)
4766 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4768 for (i = 0; i < config->rx_ring_num; i++) {
4769 struct ring_info *ring = &mac_control->rings[i];
4771 rx_intr_handler(ring, 0);
4776 * tx_traffic_int reg is an R1 register, writing all 1's
4777 * will ensure that the actual interrupt causing bit get's
4778 * cleared and hence a read can be avoided.
4780 if (reason & GEN_INTR_TXTRAFFIC)
4781 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4783 for (i = 0; i < config->tx_fifo_num; i++)
4784 tx_intr_handler(&mac_control->fifos[i]);
4786 if (reason & GEN_INTR_TXPIC)
4787 s2io_txpic_intr_handle(sp);
4790 * Reallocate the buffers from the interrupt handler itself.
4792 if (!config->napi) {
4793 for (i = 0; i < config->rx_ring_num; i++) {
4794 struct ring_info *ring = &mac_control->rings[i];
4796 s2io_chk_rx_buffers(sp, ring);
4799 writeq(sp->general_int_mask, &bar0->general_int_mask);
4800 readl(&bar0->general_int_status);
4804 } else if (!reason) {
4805 /* The interrupt was not raised by us */
4815 static void s2io_updt_stats(struct s2io_nic *sp)
4817 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4821 if (is_s2io_card_up(sp)) {
4822 /* Apprx 30us on a 133 MHz bus */
4823 val64 = SET_UPDT_CLICKS(10) |
4824 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4825 writeq(val64, &bar0->stat_cfg);
4828 val64 = readq(&bar0->stat_cfg);
4829 if (!(val64 & s2BIT(0)))
4833 break; /* Updt failed */
4839 * s2io_get_stats - Updates the device statistics structure.
4840 * @dev : pointer to the device structure.
4842 * This function updates the device statistics structure in the s2io_nic
4843 * structure and returns a pointer to the same.
4845 * pointer to the updated net_device_stats structure.
4847 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4849 struct s2io_nic *sp = netdev_priv(dev);
4850 struct mac_info *mac_control = &sp->mac_control;
4851 struct stat_block *stats = mac_control->stats_info;
4854 /* Configure Stats for immediate updt */
4855 s2io_updt_stats(sp);
4857 /* A device reset will cause the on-adapter statistics to be zero'ed.
4858 * This can be done while running by changing the MTU. To prevent the
4859 * system from having the stats zero'ed, the driver keeps a copy of the
4860 * last update to the system (which is also zero'ed on reset). This
4861 * enables the driver to accurately know the delta between the last
4862 * update and the current update.
4864 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4865 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4866 sp->stats.rx_packets += delta;
4867 dev->stats.rx_packets += delta;
4869 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4870 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4871 sp->stats.tx_packets += delta;
4872 dev->stats.tx_packets += delta;
4874 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4875 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4876 sp->stats.rx_bytes += delta;
4877 dev->stats.rx_bytes += delta;
4879 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4880 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4881 sp->stats.tx_bytes += delta;
4882 dev->stats.tx_bytes += delta;
4884 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4885 sp->stats.rx_errors += delta;
4886 dev->stats.rx_errors += delta;
4888 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4889 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4890 sp->stats.tx_errors += delta;
4891 dev->stats.tx_errors += delta;
4893 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4894 sp->stats.rx_dropped += delta;
4895 dev->stats.rx_dropped += delta;
4897 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4898 sp->stats.tx_dropped += delta;
4899 dev->stats.tx_dropped += delta;
4901 /* The adapter MAC interprets pause frames as multicast packets, but
4902 * does not pass them up. This erroneously increases the multicast
4903 * packet count and needs to be deducted when the multicast frame count
4906 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4907 le32_to_cpu(stats->rmac_vld_mcst_frms);
4908 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4909 delta -= sp->stats.multicast;
4910 sp->stats.multicast += delta;
4911 dev->stats.multicast += delta;
4913 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4914 le32_to_cpu(stats->rmac_usized_frms)) +
4915 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4916 sp->stats.rx_length_errors += delta;
4917 dev->stats.rx_length_errors += delta;
4919 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4920 sp->stats.rx_crc_errors += delta;
4921 dev->stats.rx_crc_errors += delta;
4927 * s2io_set_multicast - entry point for multicast address enable/disable.
4928 * @dev : pointer to the device structure
4930 * This function is a driver entry point which gets called by the kernel
4931 * whenever multicast addresses must be enabled/disabled. This also gets
4932 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4933 * determine, if multicast address must be enabled or if promiscuous mode
4934 * is to be disabled etc.
4939 static void s2io_set_multicast(struct net_device *dev)
4942 struct netdev_hw_addr *ha;
4943 struct s2io_nic *sp = netdev_priv(dev);
4944 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4945 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4947 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4949 struct config_param *config = &sp->config;
4951 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4952 /* Enable all Multicast addresses */
4953 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4954 &bar0->rmac_addr_data0_mem);
4955 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4956 &bar0->rmac_addr_data1_mem);
4957 val64 = RMAC_ADDR_CMD_MEM_WE |
4958 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4959 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4960 writeq(val64, &bar0->rmac_addr_cmd_mem);
4961 /* Wait till command completes */
4962 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4963 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4967 sp->all_multi_pos = config->max_mc_addr - 1;
4968 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4969 /* Disable all Multicast addresses */
4970 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4971 &bar0->rmac_addr_data0_mem);
4972 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4973 &bar0->rmac_addr_data1_mem);
4974 val64 = RMAC_ADDR_CMD_MEM_WE |
4975 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4976 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4977 writeq(val64, &bar0->rmac_addr_cmd_mem);
4978 /* Wait till command completes */
4979 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4980 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4984 sp->all_multi_pos = 0;
4987 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4988 /* Put the NIC into promiscuous mode */
4989 add = &bar0->mac_cfg;
4990 val64 = readq(&bar0->mac_cfg);
4991 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4993 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4994 writel((u32)val64, add);
4995 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4996 writel((u32) (val64 >> 32), (add + 4));
4998 if (vlan_tag_strip != 1) {
4999 val64 = readq(&bar0->rx_pa_cfg);
5000 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5001 writeq(val64, &bar0->rx_pa_cfg);
5002 sp->vlan_strip_flag = 0;
5005 val64 = readq(&bar0->mac_cfg);
5006 sp->promisc_flg = 1;
5007 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5009 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5010 /* Remove the NIC from promiscuous mode */
5011 add = &bar0->mac_cfg;
5012 val64 = readq(&bar0->mac_cfg);
5013 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5015 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5016 writel((u32)val64, add);
5017 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5018 writel((u32) (val64 >> 32), (add + 4));
5020 if (vlan_tag_strip != 0) {
5021 val64 = readq(&bar0->rx_pa_cfg);
5022 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5023 writeq(val64, &bar0->rx_pa_cfg);
5024 sp->vlan_strip_flag = 1;
5027 val64 = readq(&bar0->mac_cfg);
5028 sp->promisc_flg = 0;
5029 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5032 /* Update individual M_CAST address list */
5033 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5034 if (netdev_mc_count(dev) >
5035 (config->max_mc_addr - config->max_mac_addr)) {
5037 "%s: No more Rx filters can be added - "
5038 "please enable ALL_MULTI instead\n",
5043 prev_cnt = sp->mc_addr_count;
5044 sp->mc_addr_count = netdev_mc_count(dev);
5046 /* Clear out the previous list of Mc in the H/W. */
5047 for (i = 0; i < prev_cnt; i++) {
5048 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5049 &bar0->rmac_addr_data0_mem);
5050 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5051 &bar0->rmac_addr_data1_mem);
5052 val64 = RMAC_ADDR_CMD_MEM_WE |
5053 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5054 RMAC_ADDR_CMD_MEM_OFFSET
5055 (config->mc_start_offset + i);
5056 writeq(val64, &bar0->rmac_addr_cmd_mem);
5058 /* Wait for command completes */
5059 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5060 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5063 "%s: Adding Multicasts failed\n",
5069 /* Create the new Rx filter list and update the same in H/W. */
5071 netdev_for_each_mc_addr(ha, dev) {
5073 for (j = 0; j < ETH_ALEN; j++) {
5074 mac_addr |= ha->addr[j];
5078 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5079 &bar0->rmac_addr_data0_mem);
5080 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5081 &bar0->rmac_addr_data1_mem);
5082 val64 = RMAC_ADDR_CMD_MEM_WE |
5083 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5084 RMAC_ADDR_CMD_MEM_OFFSET
5085 (i + config->mc_start_offset);
5086 writeq(val64, &bar0->rmac_addr_cmd_mem);
5088 /* Wait for command completes */
5089 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5090 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5093 "%s: Adding Multicasts failed\n",
5102 /* read from CAM unicast & multicast addresses and store it in
5103 * def_mac_addr structure
5105 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5109 struct config_param *config = &sp->config;
5111 /* store unicast & multicast mac addresses */
5112 for (offset = 0; offset < config->max_mc_addr; offset++) {
5113 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5114 /* if read fails disable the entry */
5115 if (mac_addr == FAILURE)
5116 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5117 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5121 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5122 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5125 struct config_param *config = &sp->config;
5126 /* restore unicast mac address */
5127 for (offset = 0; offset < config->max_mac_addr; offset++)
5128 do_s2io_prog_unicast(sp->dev,
5129 sp->def_mac_addr[offset].mac_addr);
5131 /* restore multicast mac address */
5132 for (offset = config->mc_start_offset;
5133 offset < config->max_mc_addr; offset++)
5134 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5137 /* add a multicast MAC address to CAM */
5138 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5142 struct config_param *config = &sp->config;
5144 for (i = 0; i < ETH_ALEN; i++) {
5146 mac_addr |= addr[i];
5148 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5151 /* check if the multicast mac already preset in CAM */
5152 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5154 tmp64 = do_s2io_read_unicast_mc(sp, i);
5155 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5158 if (tmp64 == mac_addr)
5161 if (i == config->max_mc_addr) {
5163 "CAM full no space left for multicast MAC\n");
5166 /* Update the internal structure with this new mac address */
5167 do_s2io_copy_mac_addr(sp, i, mac_addr);
5169 return do_s2io_add_mac(sp, mac_addr, i);
5172 /* add MAC address to CAM */
5173 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5176 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5178 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5179 &bar0->rmac_addr_data0_mem);
5181 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5182 RMAC_ADDR_CMD_MEM_OFFSET(off);
5183 writeq(val64, &bar0->rmac_addr_cmd_mem);
5185 /* Wait till command completes */
5186 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5187 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5189 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5194 /* deletes a specified unicast/multicast mac entry from CAM */
5195 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5198 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5199 struct config_param *config = &sp->config;
5202 offset < config->max_mc_addr; offset++) {
5203 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5204 if (tmp64 == addr) {
5205 /* disable the entry by writing 0xffffffffffffULL */
5206 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5208 /* store the new mac list from CAM */
5209 do_s2io_store_unicast_mc(sp);
5213 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5214 (unsigned long long)addr);
5218 /* read mac entries from CAM */
5219 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5221 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5222 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5225 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5226 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5227 writeq(val64, &bar0->rmac_addr_cmd_mem);
5229 /* Wait till command completes */
5230 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5231 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5233 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5236 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5242 * s2io_set_mac_addr - driver entry point
5245 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5247 struct sockaddr *addr = p;
5249 if (!is_valid_ether_addr(addr->sa_data))
5250 return -EADDRNOTAVAIL;
5252 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5254 /* store the MAC address in CAM */
5255 return do_s2io_prog_unicast(dev, dev->dev_addr);
5258 * do_s2io_prog_unicast - Programs the Xframe mac address
5259 * @dev : pointer to the device structure.
5260 * @addr: a uchar pointer to the new mac address which is to be set.
5261 * Description : This procedure will program the Xframe to receive
5262 * frames with new Mac Address
5263 * Return value: SUCCESS on success and an appropriate (-)ve integer
5264 * as defined in errno.h file on failure.
5267 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5269 struct s2io_nic *sp = netdev_priv(dev);
5270 register u64 mac_addr = 0, perm_addr = 0;
5273 struct config_param *config = &sp->config;
5276 * Set the new MAC address as the new unicast filter and reflect this
5277 * change on the device address registered with the OS. It will be
5280 for (i = 0; i < ETH_ALEN; i++) {
5282 mac_addr |= addr[i];
5284 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5287 /* check if the dev_addr is different than perm_addr */
5288 if (mac_addr == perm_addr)
5291 /* check if the mac already preset in CAM */
5292 for (i = 1; i < config->max_mac_addr; i++) {
5293 tmp64 = do_s2io_read_unicast_mc(sp, i);
5294 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5297 if (tmp64 == mac_addr) {
5299 "MAC addr:0x%llx already present in CAM\n",
5300 (unsigned long long)mac_addr);
5304 if (i == config->max_mac_addr) {
5305 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5308 /* Update the internal structure with this new mac address */
5309 do_s2io_copy_mac_addr(sp, i, mac_addr);
5311 return do_s2io_add_mac(sp, mac_addr, i);
5315 * s2io_ethtool_sset - Sets different link parameters.
5316 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5317 * @info: pointer to the structure with parameters given by ethtool to set
5320 * The function sets different link parameters provided by the user onto
5326 static int s2io_ethtool_sset(struct net_device *dev,
5327 struct ethtool_cmd *info)
5329 struct s2io_nic *sp = netdev_priv(dev);
5330 if ((info->autoneg == AUTONEG_ENABLE) ||
5331 (ethtool_cmd_speed(info) != SPEED_10000) ||
5332 (info->duplex != DUPLEX_FULL))
5335 s2io_close(sp->dev);
5343 * s2io_ethtol_gset - Return link specific information.
5344 * @sp : private member of the device structure, pointer to the
5345 * s2io_nic structure.
5346 * @info : pointer to the structure with parameters given by ethtool
5347 * to return link information.
5349 * Returns link specific information like speed, duplex etc.. to ethtool.
5351 * return 0 on success.
5354 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5356 struct s2io_nic *sp = netdev_priv(dev);
5357 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5358 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5359 info->port = PORT_FIBRE;
5361 /* info->transceiver */
5362 info->transceiver = XCVR_EXTERNAL;
5364 if (netif_carrier_ok(sp->dev)) {
5365 ethtool_cmd_speed_set(info, SPEED_10000);
5366 info->duplex = DUPLEX_FULL;
5368 ethtool_cmd_speed_set(info, -1);
5372 info->autoneg = AUTONEG_DISABLE;
5377 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5378 * @sp : private member of the device structure, which is a pointer to the
5379 * s2io_nic structure.
5380 * @info : pointer to the structure with parameters given by ethtool to
5381 * return driver information.
5383 * Returns driver specefic information like name, version etc.. to ethtool.
5388 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5389 struct ethtool_drvinfo *info)
5391 struct s2io_nic *sp = netdev_priv(dev);
5393 strlcpy(info->driver, s2io_driver_name, sizeof(info->driver));
5394 strlcpy(info->version, s2io_driver_version, sizeof(info->version));
5395 strlcpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5396 info->regdump_len = XENA_REG_SPACE;
5397 info->eedump_len = XENA_EEPROM_SPACE;
5401 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5402 * @sp: private member of the device structure, which is a pointer to the
5403 * s2io_nic structure.
5404 * @regs : pointer to the structure with parameters given by ethtool for
5405 * dumping the registers.
5406 * @reg_space: The input argumnet into which all the registers are dumped.
5408 * Dumps the entire register space of xFrame NIC into the user given
5414 static void s2io_ethtool_gregs(struct net_device *dev,
5415 struct ethtool_regs *regs, void *space)
5419 u8 *reg_space = (u8 *)space;
5420 struct s2io_nic *sp = netdev_priv(dev);
5422 regs->len = XENA_REG_SPACE;
5423 regs->version = sp->pdev->subsystem_device;
5425 for (i = 0; i < regs->len; i += 8) {
5426 reg = readq(sp->bar0 + i);
5427 memcpy((reg_space + i), ®, 8);
5432 * s2io_set_led - control NIC led
5434 static void s2io_set_led(struct s2io_nic *sp, bool on)
5436 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5437 u16 subid = sp->pdev->subsystem_device;
5440 if ((sp->device_type == XFRAME_II_DEVICE) ||
5441 ((subid & 0xFF) >= 0x07)) {
5442 val64 = readq(&bar0->gpio_control);
5444 val64 |= GPIO_CTRL_GPIO_0;
5446 val64 &= ~GPIO_CTRL_GPIO_0;
5448 writeq(val64, &bar0->gpio_control);
5450 val64 = readq(&bar0->adapter_control);
5452 val64 |= ADAPTER_LED_ON;
5454 val64 &= ~ADAPTER_LED_ON;
5456 writeq(val64, &bar0->adapter_control);
5462 * s2io_ethtool_set_led - To physically identify the nic on the system.
5463 * @dev : network device
5464 * @state: led setting
5466 * Description: Used to physically identify the NIC on the system.
5467 * The Link LED will blink for a time specified by the user for
5469 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5470 * identification is possible only if it's link is up.
5473 static int s2io_ethtool_set_led(struct net_device *dev,
5474 enum ethtool_phys_id_state state)
5476 struct s2io_nic *sp = netdev_priv(dev);
5477 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5478 u16 subid = sp->pdev->subsystem_device;
5480 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5481 u64 val64 = readq(&bar0->adapter_control);
5482 if (!(val64 & ADAPTER_CNTL_EN)) {
5483 pr_err("Adapter Link down, cannot blink LED\n");
5489 case ETHTOOL_ID_ACTIVE:
5490 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5491 return 1; /* cycle on/off once per second */
5494 s2io_set_led(sp, true);
5497 case ETHTOOL_ID_OFF:
5498 s2io_set_led(sp, false);
5501 case ETHTOOL_ID_INACTIVE:
5502 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5503 writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5509 static void s2io_ethtool_gringparam(struct net_device *dev,
5510 struct ethtool_ringparam *ering)
5512 struct s2io_nic *sp = netdev_priv(dev);
5513 int i, tx_desc_count = 0, rx_desc_count = 0;
5515 if (sp->rxd_mode == RXD_MODE_1) {
5516 ering->rx_max_pending = MAX_RX_DESC_1;
5517 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5519 ering->rx_max_pending = MAX_RX_DESC_2;
5520 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5523 ering->tx_max_pending = MAX_TX_DESC;
5525 for (i = 0; i < sp->config.rx_ring_num; i++)
5526 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5527 ering->rx_pending = rx_desc_count;
5528 ering->rx_jumbo_pending = rx_desc_count;
5530 for (i = 0; i < sp->config.tx_fifo_num; i++)
5531 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5532 ering->tx_pending = tx_desc_count;
5533 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5537 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5538 * @sp : private member of the device structure, which is a pointer to the
5539 * s2io_nic structure.
5540 * @ep : pointer to the structure with pause parameters given by ethtool.
5542 * Returns the Pause frame generation and reception capability of the NIC.
5546 static void s2io_ethtool_getpause_data(struct net_device *dev,
5547 struct ethtool_pauseparam *ep)
5550 struct s2io_nic *sp = netdev_priv(dev);
5551 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5553 val64 = readq(&bar0->rmac_pause_cfg);
5554 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5555 ep->tx_pause = true;
5556 if (val64 & RMAC_PAUSE_RX_ENABLE)
5557 ep->rx_pause = true;
5558 ep->autoneg = false;
5562 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5563 * @sp : private member of the device structure, which is a pointer to the
5564 * s2io_nic structure.
5565 * @ep : pointer to the structure with pause parameters given by ethtool.
5567 * It can be used to set or reset Pause frame generation or reception
5568 * support of the NIC.
5570 * int, returns 0 on Success
5573 static int s2io_ethtool_setpause_data(struct net_device *dev,
5574 struct ethtool_pauseparam *ep)
5577 struct s2io_nic *sp = netdev_priv(dev);
5578 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5580 val64 = readq(&bar0->rmac_pause_cfg);
5582 val64 |= RMAC_PAUSE_GEN_ENABLE;
5584 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5586 val64 |= RMAC_PAUSE_RX_ENABLE;
5588 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5589 writeq(val64, &bar0->rmac_pause_cfg);
5594 * read_eeprom - reads 4 bytes of data from user given offset.
5595 * @sp : private member of the device structure, which is a pointer to the
5596 * s2io_nic structure.
5597 * @off : offset at which the data must be written
5598 * @data : Its an output parameter where the data read at the given
5601 * Will read 4 bytes of data from the user given offset and return the
5603 * NOTE: Will allow to read only part of the EEPROM visible through the
5606 * -1 on failure and 0 on success.
5609 #define S2IO_DEV_ID 5
5610 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5615 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5617 if (sp->device_type == XFRAME_I_DEVICE) {
5618 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5619 I2C_CONTROL_ADDR(off) |
5620 I2C_CONTROL_BYTE_CNT(0x3) |
5622 I2C_CONTROL_CNTL_START;
5623 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5625 while (exit_cnt < 5) {
5626 val64 = readq(&bar0->i2c_control);
5627 if (I2C_CONTROL_CNTL_END(val64)) {
5628 *data = I2C_CONTROL_GET_DATA(val64);
5637 if (sp->device_type == XFRAME_II_DEVICE) {
5638 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5639 SPI_CONTROL_BYTECNT(0x3) |
5640 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5641 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5642 val64 |= SPI_CONTROL_REQ;
5643 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5644 while (exit_cnt < 5) {
5645 val64 = readq(&bar0->spi_control);
5646 if (val64 & SPI_CONTROL_NACK) {
5649 } else if (val64 & SPI_CONTROL_DONE) {
5650 *data = readq(&bar0->spi_data);
5663 * write_eeprom - actually writes the relevant part of the data value.
5664 * @sp : private member of the device structure, which is a pointer to the
5665 * s2io_nic structure.
5666 * @off : offset at which the data must be written
5667 * @data : The data that is to be written
5668 * @cnt : Number of bytes of the data that are actually to be written into
5669 * the Eeprom. (max of 3)
5671 * Actually writes the relevant part of the data value into the Eeprom
5672 * through the I2C bus.
5674 * 0 on success, -1 on failure.
5677 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5679 int exit_cnt = 0, ret = -1;
5681 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5683 if (sp->device_type == XFRAME_I_DEVICE) {
5684 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5685 I2C_CONTROL_ADDR(off) |
5686 I2C_CONTROL_BYTE_CNT(cnt) |
5687 I2C_CONTROL_SET_DATA((u32)data) |
5688 I2C_CONTROL_CNTL_START;
5689 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5691 while (exit_cnt < 5) {
5692 val64 = readq(&bar0->i2c_control);
5693 if (I2C_CONTROL_CNTL_END(val64)) {
5694 if (!(val64 & I2C_CONTROL_NACK))
5703 if (sp->device_type == XFRAME_II_DEVICE) {
5704 int write_cnt = (cnt == 8) ? 0 : cnt;
5705 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5707 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5708 SPI_CONTROL_BYTECNT(write_cnt) |
5709 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5710 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5711 val64 |= SPI_CONTROL_REQ;
5712 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5713 while (exit_cnt < 5) {
5714 val64 = readq(&bar0->spi_control);
5715 if (val64 & SPI_CONTROL_NACK) {
5718 } else if (val64 & SPI_CONTROL_DONE) {
5728 static void s2io_vpd_read(struct s2io_nic *nic)
5732 int i = 0, cnt, len, fail = 0;
5733 int vpd_addr = 0x80;
5734 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5736 if (nic->device_type == XFRAME_II_DEVICE) {
5737 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5740 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5743 strcpy(nic->serial_num, "NOT AVAILABLE");
5745 vpd_data = kmalloc(256, GFP_KERNEL);
5747 swstats->mem_alloc_fail_cnt++;
5750 swstats->mem_allocated += 256;
5752 for (i = 0; i < 256; i += 4) {
5753 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5754 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5755 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5756 for (cnt = 0; cnt < 5; cnt++) {
5758 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5763 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5767 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5768 (u32 *)&vpd_data[i]);
5772 /* read serial number of adapter */
5773 for (cnt = 0; cnt < 252; cnt++) {
5774 if ((vpd_data[cnt] == 'S') &&
5775 (vpd_data[cnt+1] == 'N')) {
5776 len = vpd_data[cnt+2];
5777 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5778 memcpy(nic->serial_num,
5781 memset(nic->serial_num+len,
5783 VPD_STRING_LEN-len);
5790 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5792 memcpy(nic->product_name, &vpd_data[3], len);
5793 nic->product_name[len] = 0;
5796 swstats->mem_freed += 256;
5800 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5801 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5802 * @eeprom : pointer to the user level structure provided by ethtool,
5803 * containing all relevant information.
5804 * @data_buf : user defined value to be written into Eeprom.
5805 * Description: Reads the values stored in the Eeprom at given offset
5806 * for a given length. Stores these values int the input argument data
5807 * buffer 'data_buf' and returns these to the caller (ethtool.)
5812 static int s2io_ethtool_geeprom(struct net_device *dev,
5813 struct ethtool_eeprom *eeprom, u8 * data_buf)
5817 struct s2io_nic *sp = netdev_priv(dev);
5819 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5821 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5822 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5824 for (i = 0; i < eeprom->len; i += 4) {
5825 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5826 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5830 memcpy((data_buf + i), &valid, 4);
5836 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5837 * @sp : private member of the device structure, which is a pointer to the
5838 * s2io_nic structure.
5839 * @eeprom : pointer to the user level structure provided by ethtool,
5840 * containing all relevant information.
5841 * @data_buf ; user defined value to be written into Eeprom.
5843 * Tries to write the user provided value in the Eeprom, at the offset
5844 * given by the user.
5846 * 0 on success, -EFAULT on failure.
5849 static int s2io_ethtool_seeprom(struct net_device *dev,
5850 struct ethtool_eeprom *eeprom,
5853 int len = eeprom->len, cnt = 0;
5854 u64 valid = 0, data;
5855 struct s2io_nic *sp = netdev_priv(dev);
5857 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5859 "ETHTOOL_WRITE_EEPROM Err: "
5860 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5861 (sp->pdev->vendor | (sp->pdev->device << 16)),
5867 data = (u32)data_buf[cnt] & 0x000000FF;
5869 valid = (u32)(data << 24);
5873 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5875 "ETHTOOL_WRITE_EEPROM Err: "
5876 "Cannot write into the specified offset\n");
5887 * s2io_register_test - reads and writes into all clock domains.
5888 * @sp : private member of the device structure, which is a pointer to the
5889 * s2io_nic structure.
5890 * @data : variable that returns the result of each of the test conducted b
5893 * Read and write into all clock domains. The NIC has 3 clock domains,
5894 * see that registers in all the three regions are accessible.
5899 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5901 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5902 u64 val64 = 0, exp_val;
5905 val64 = readq(&bar0->pif_rd_swapper_fb);
5906 if (val64 != 0x123456789abcdefULL) {
5908 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5911 val64 = readq(&bar0->rmac_pause_cfg);
5912 if (val64 != 0xc000ffff00000000ULL) {
5914 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5917 val64 = readq(&bar0->rx_queue_cfg);
5918 if (sp->device_type == XFRAME_II_DEVICE)
5919 exp_val = 0x0404040404040404ULL;
5921 exp_val = 0x0808080808080808ULL;
5922 if (val64 != exp_val) {
5924 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5927 val64 = readq(&bar0->xgxs_efifo_cfg);
5928 if (val64 != 0x000000001923141EULL) {
5930 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5933 val64 = 0x5A5A5A5A5A5A5A5AULL;
5934 writeq(val64, &bar0->xmsi_data);
5935 val64 = readq(&bar0->xmsi_data);
5936 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5938 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5941 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5942 writeq(val64, &bar0->xmsi_data);
5943 val64 = readq(&bar0->xmsi_data);
5944 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5946 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5954 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5955 * @sp : private member of the device structure, which is a pointer to the
5956 * s2io_nic structure.
5957 * @data:variable that returns the result of each of the test conducted by
5960 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5966 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5969 u64 ret_data, org_4F0, org_7F0;
5970 u8 saved_4F0 = 0, saved_7F0 = 0;
5971 struct net_device *dev = sp->dev;
5973 /* Test Write Error at offset 0 */
5974 /* Note that SPI interface allows write access to all areas
5975 * of EEPROM. Hence doing all negative testing only for Xframe I.
5977 if (sp->device_type == XFRAME_I_DEVICE)
5978 if (!write_eeprom(sp, 0, 0, 3))
5981 /* Save current values at offsets 0x4F0 and 0x7F0 */
5982 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5984 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5987 /* Test Write at offset 4f0 */
5988 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5990 if (read_eeprom(sp, 0x4F0, &ret_data))
5993 if (ret_data != 0x012345) {
5994 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5995 "Data written %llx Data read %llx\n",
5996 dev->name, (unsigned long long)0x12345,
5997 (unsigned long long)ret_data);
6001 /* Reset the EEPROM data go FFFF */
6002 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6004 /* Test Write Request Error at offset 0x7c */
6005 if (sp->device_type == XFRAME_I_DEVICE)
6006 if (!write_eeprom(sp, 0x07C, 0, 3))
6009 /* Test Write Request at offset 0x7f0 */
6010 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6012 if (read_eeprom(sp, 0x7F0, &ret_data))
6015 if (ret_data != 0x012345) {
6016 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6017 "Data written %llx Data read %llx\n",
6018 dev->name, (unsigned long long)0x12345,
6019 (unsigned long long)ret_data);
6023 /* Reset the EEPROM data go FFFF */
6024 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6026 if (sp->device_type == XFRAME_I_DEVICE) {
6027 /* Test Write Error at offset 0x80 */
6028 if (!write_eeprom(sp, 0x080, 0, 3))
6031 /* Test Write Error at offset 0xfc */
6032 if (!write_eeprom(sp, 0x0FC, 0, 3))
6035 /* Test Write Error at offset 0x100 */
6036 if (!write_eeprom(sp, 0x100, 0, 3))
6039 /* Test Write Error at offset 4ec */
6040 if (!write_eeprom(sp, 0x4EC, 0, 3))
6044 /* Restore values at offsets 0x4F0 and 0x7F0 */
6046 write_eeprom(sp, 0x4F0, org_4F0, 3);
6048 write_eeprom(sp, 0x7F0, org_7F0, 3);
6055 * s2io_bist_test - invokes the MemBist test of the card .
6056 * @sp : private member of the device structure, which is a pointer to the
6057 * s2io_nic structure.
6058 * @data:variable that returns the result of each of the test conducted by
6061 * This invokes the MemBist test of the card. We give around
6062 * 2 secs time for the Test to complete. If it's still not complete
6063 * within this peiod, we consider that the test failed.
6065 * 0 on success and -1 on failure.
6068 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6071 int cnt = 0, ret = -1;
6073 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6074 bist |= PCI_BIST_START;
6075 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6078 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6079 if (!(bist & PCI_BIST_START)) {
6080 *data = (bist & PCI_BIST_CODE_MASK);
6092 * s2io_link_test - verifies the link state of the nic
6093 * @sp ; private member of the device structure, which is a pointer to the
6094 * s2io_nic structure.
6095 * @data: variable that returns the result of each of the test conducted by
6098 * The function verifies the link state of the NIC and updates the input
6099 * argument 'data' appropriately.
6104 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6106 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6109 val64 = readq(&bar0->adapter_status);
6110 if (!(LINK_IS_UP(val64)))
6119 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6120 * @sp: private member of the device structure, which is a pointer to the
6121 * s2io_nic structure.
6122 * @data: variable that returns the result of each of the test
6123 * conducted by the driver.
6125 * This is one of the offline test that tests the read and write
6126 * access to the RldRam chip on the NIC.
6131 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6133 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6135 int cnt, iteration = 0, test_fail = 0;
6137 val64 = readq(&bar0->adapter_control);
6138 val64 &= ~ADAPTER_ECC_EN;
6139 writeq(val64, &bar0->adapter_control);
6141 val64 = readq(&bar0->mc_rldram_test_ctrl);
6142 val64 |= MC_RLDRAM_TEST_MODE;
6143 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6145 val64 = readq(&bar0->mc_rldram_mrs);
6146 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6147 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6149 val64 |= MC_RLDRAM_MRS_ENABLE;
6150 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6152 while (iteration < 2) {
6153 val64 = 0x55555555aaaa0000ULL;
6155 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6156 writeq(val64, &bar0->mc_rldram_test_d0);
6158 val64 = 0xaaaa5a5555550000ULL;
6160 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6161 writeq(val64, &bar0->mc_rldram_test_d1);
6163 val64 = 0x55aaaaaaaa5a0000ULL;
6165 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6166 writeq(val64, &bar0->mc_rldram_test_d2);
6168 val64 = (u64) (0x0000003ffffe0100ULL);
6169 writeq(val64, &bar0->mc_rldram_test_add);
6171 val64 = MC_RLDRAM_TEST_MODE |
6172 MC_RLDRAM_TEST_WRITE |
6174 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6176 for (cnt = 0; cnt < 5; cnt++) {
6177 val64 = readq(&bar0->mc_rldram_test_ctrl);
6178 if (val64 & MC_RLDRAM_TEST_DONE)
6186 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6187 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6189 for (cnt = 0; cnt < 5; cnt++) {
6190 val64 = readq(&bar0->mc_rldram_test_ctrl);
6191 if (val64 & MC_RLDRAM_TEST_DONE)
6199 val64 = readq(&bar0->mc_rldram_test_ctrl);
6200 if (!(val64 & MC_RLDRAM_TEST_PASS))
6208 /* Bring the adapter out of test mode */
6209 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6215 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6216 * @sp : private member of the device structure, which is a pointer to the
6217 * s2io_nic structure.
6218 * @ethtest : pointer to a ethtool command specific structure that will be
6219 * returned to the user.
6220 * @data : variable that returns the result of each of the test
6221 * conducted by the driver.
6223 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6224 * the health of the card.
6229 static void s2io_ethtool_test(struct net_device *dev,
6230 struct ethtool_test *ethtest,
6233 struct s2io_nic *sp = netdev_priv(dev);
6234 int orig_state = netif_running(sp->dev);
6236 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6237 /* Offline Tests. */
6239 s2io_close(sp->dev);
6241 if (s2io_register_test(sp, &data[0]))
6242 ethtest->flags |= ETH_TEST_FL_FAILED;
6246 if (s2io_rldram_test(sp, &data[3]))
6247 ethtest->flags |= ETH_TEST_FL_FAILED;
6251 if (s2io_eeprom_test(sp, &data[1]))
6252 ethtest->flags |= ETH_TEST_FL_FAILED;
6254 if (s2io_bist_test(sp, &data[4]))
6255 ethtest->flags |= ETH_TEST_FL_FAILED;
6264 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6273 if (s2io_link_test(sp, &data[2]))
6274 ethtest->flags |= ETH_TEST_FL_FAILED;
6283 static void s2io_get_ethtool_stats(struct net_device *dev,
6284 struct ethtool_stats *estats,
6288 struct s2io_nic *sp = netdev_priv(dev);
6289 struct stat_block *stats = sp->mac_control.stats_info;
6290 struct swStat *swstats = &stats->sw_stat;
6291 struct xpakStat *xstats = &stats->xpak_stat;
6293 s2io_updt_stats(sp);
6295 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6296 le32_to_cpu(stats->tmac_frms);
6298 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6299 le32_to_cpu(stats->tmac_data_octets);
6300 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6302 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6303 le32_to_cpu(stats->tmac_mcst_frms);
6305 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6306 le32_to_cpu(stats->tmac_bcst_frms);
6307 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6309 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6310 le32_to_cpu(stats->tmac_ttl_octets);
6312 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6313 le32_to_cpu(stats->tmac_ucst_frms);
6315 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6316 le32_to_cpu(stats->tmac_nucst_frms);
6318 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6319 le32_to_cpu(stats->tmac_any_err_frms);
6320 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6321 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6323 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6324 le32_to_cpu(stats->tmac_vld_ip);
6326 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6327 le32_to_cpu(stats->tmac_drop_ip);
6329 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6330 le32_to_cpu(stats->tmac_icmp);
6332 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6333 le32_to_cpu(stats->tmac_rst_tcp);
6334 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6335 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6336 le32_to_cpu(stats->tmac_udp);
6338 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6339 le32_to_cpu(stats->rmac_vld_frms);
6341 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6342 le32_to_cpu(stats->rmac_data_octets);
6343 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6344 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6346 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6347 le32_to_cpu(stats->rmac_vld_mcst_frms);
6349 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6350 le32_to_cpu(stats->rmac_vld_bcst_frms);
6351 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6352 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6353 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6354 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6355 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6357 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6358 le32_to_cpu(stats->rmac_ttl_octets);
6360 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6361 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6363 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6364 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6366 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6367 le32_to_cpu(stats->rmac_discarded_frms);
6369 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6370 << 32 | le32_to_cpu(stats->rmac_drop_events);
6371 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6372 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6374 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6375 le32_to_cpu(stats->rmac_usized_frms);
6377 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6378 le32_to_cpu(stats->rmac_osized_frms);
6380 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6381 le32_to_cpu(stats->rmac_frag_frms);
6383 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6384 le32_to_cpu(stats->rmac_jabber_frms);
6385 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6386 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6387 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6388 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6389 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6390 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6392 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6393 le32_to_cpu(stats->rmac_ip);
6394 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6395 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6397 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6398 le32_to_cpu(stats->rmac_drop_ip);
6400 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6401 le32_to_cpu(stats->rmac_icmp);
6402 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6404 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6405 le32_to_cpu(stats->rmac_udp);
6407 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6408 le32_to_cpu(stats->rmac_err_drp_udp);
6409 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6410 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6411 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6412 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6413 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6418 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6419 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6420 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6421 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6422 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6423 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6424 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6425 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6427 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6428 le32_to_cpu(stats->rmac_pause_cnt);
6429 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6430 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6432 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6433 le32_to_cpu(stats->rmac_accepted_ip);
6434 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6435 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6436 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6437 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6438 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6439 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6440 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6441 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6442 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6443 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6444 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6445 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6446 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6447 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6448 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6449 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6450 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6451 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6452 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6454 /* Enhanced statistics exist only for Hercules */
6455 if (sp->device_type == XFRAME_II_DEVICE) {
6457 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6459 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6461 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6462 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6463 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6464 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6465 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6466 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6467 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6468 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6469 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6470 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6471 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6472 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6473 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6474 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6478 tmp_stats[i++] = swstats->single_ecc_errs;
6479 tmp_stats[i++] = swstats->double_ecc_errs;
6480 tmp_stats[i++] = swstats->parity_err_cnt;
6481 tmp_stats[i++] = swstats->serious_err_cnt;
6482 tmp_stats[i++] = swstats->soft_reset_cnt;
6483 tmp_stats[i++] = swstats->fifo_full_cnt;
6484 for (k = 0; k < MAX_RX_RINGS; k++)
6485 tmp_stats[i++] = swstats->ring_full_cnt[k];
6486 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6487 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6488 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6489 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6490 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6491 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6492 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6493 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6494 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6495 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6496 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6497 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6498 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6499 tmp_stats[i++] = swstats->sending_both;
6500 tmp_stats[i++] = swstats->outof_sequence_pkts;
6501 tmp_stats[i++] = swstats->flush_max_pkts;
6502 if (swstats->num_aggregations) {
6503 u64 tmp = swstats->sum_avg_pkts_aggregated;
6506 * Since 64-bit divide does not work on all platforms,
6507 * do repeated subtraction.
6509 while (tmp >= swstats->num_aggregations) {
6510 tmp -= swstats->num_aggregations;
6513 tmp_stats[i++] = count;
6516 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6517 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6518 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6519 tmp_stats[i++] = swstats->mem_allocated;
6520 tmp_stats[i++] = swstats->mem_freed;
6521 tmp_stats[i++] = swstats->link_up_cnt;
6522 tmp_stats[i++] = swstats->link_down_cnt;
6523 tmp_stats[i++] = swstats->link_up_time;
6524 tmp_stats[i++] = swstats->link_down_time;
6526 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6527 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6528 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6529 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6530 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6532 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6533 tmp_stats[i++] = swstats->rx_abort_cnt;
6534 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6535 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6536 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6537 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6538 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6539 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6540 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6541 tmp_stats[i++] = swstats->tda_err_cnt;
6542 tmp_stats[i++] = swstats->pfc_err_cnt;
6543 tmp_stats[i++] = swstats->pcc_err_cnt;
6544 tmp_stats[i++] = swstats->tti_err_cnt;
6545 tmp_stats[i++] = swstats->tpa_err_cnt;
6546 tmp_stats[i++] = swstats->sm_err_cnt;
6547 tmp_stats[i++] = swstats->lso_err_cnt;
6548 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6549 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6550 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6551 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6552 tmp_stats[i++] = swstats->rc_err_cnt;
6553 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6554 tmp_stats[i++] = swstats->rpa_err_cnt;
6555 tmp_stats[i++] = swstats->rda_err_cnt;
6556 tmp_stats[i++] = swstats->rti_err_cnt;
6557 tmp_stats[i++] = swstats->mc_err_cnt;
6560 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6562 return XENA_REG_SPACE;
6566 static int s2io_get_eeprom_len(struct net_device *dev)
6568 return XENA_EEPROM_SPACE;
6571 static int s2io_get_sset_count(struct net_device *dev, int sset)
6573 struct s2io_nic *sp = netdev_priv(dev);
6577 return S2IO_TEST_LEN;
6579 switch (sp->device_type) {
6580 case XFRAME_I_DEVICE:
6581 return XFRAME_I_STAT_LEN;
6582 case XFRAME_II_DEVICE:
6583 return XFRAME_II_STAT_LEN;
6592 static void s2io_ethtool_get_strings(struct net_device *dev,
6593 u32 stringset, u8 *data)
6596 struct s2io_nic *sp = netdev_priv(dev);
6598 switch (stringset) {
6600 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6603 stat_size = sizeof(ethtool_xena_stats_keys);
6604 memcpy(data, ðtool_xena_stats_keys, stat_size);
6605 if (sp->device_type == XFRAME_II_DEVICE) {
6606 memcpy(data + stat_size,
6607 ðtool_enhanced_stats_keys,
6608 sizeof(ethtool_enhanced_stats_keys));
6609 stat_size += sizeof(ethtool_enhanced_stats_keys);
6612 memcpy(data + stat_size, ðtool_driver_stats_keys,
6613 sizeof(ethtool_driver_stats_keys));
6617 static int s2io_set_features(struct net_device *dev, netdev_features_t features)
6619 struct s2io_nic *sp = netdev_priv(dev);
6620 netdev_features_t changed = (features ^ dev->features) & NETIF_F_LRO;
6622 if (changed && netif_running(dev)) {
6625 s2io_stop_all_tx_queue(sp);
6627 dev->features = features;
6628 rc = s2io_card_up(sp);
6632 s2io_start_all_tx_queue(sp);
6640 static const struct ethtool_ops netdev_ethtool_ops = {
6641 .get_settings = s2io_ethtool_gset,
6642 .set_settings = s2io_ethtool_sset,
6643 .get_drvinfo = s2io_ethtool_gdrvinfo,
6644 .get_regs_len = s2io_ethtool_get_regs_len,
6645 .get_regs = s2io_ethtool_gregs,
6646 .get_link = ethtool_op_get_link,
6647 .get_eeprom_len = s2io_get_eeprom_len,
6648 .get_eeprom = s2io_ethtool_geeprom,
6649 .set_eeprom = s2io_ethtool_seeprom,
6650 .get_ringparam = s2io_ethtool_gringparam,
6651 .get_pauseparam = s2io_ethtool_getpause_data,
6652 .set_pauseparam = s2io_ethtool_setpause_data,
6653 .self_test = s2io_ethtool_test,
6654 .get_strings = s2io_ethtool_get_strings,
6655 .set_phys_id = s2io_ethtool_set_led,
6656 .get_ethtool_stats = s2io_get_ethtool_stats,
6657 .get_sset_count = s2io_get_sset_count,
6661 * s2io_ioctl - Entry point for the Ioctl
6662 * @dev : Device pointer.
6663 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6664 * a proprietary structure used to pass information to the driver.
6665 * @cmd : This is used to distinguish between the different commands that
6666 * can be passed to the IOCTL functions.
6668 * Currently there are no special functionality supported in IOCTL, hence
6669 * function always return EOPNOTSUPPORTED
6672 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6678 * s2io_change_mtu - entry point to change MTU size for the device.
6679 * @dev : device pointer.
6680 * @new_mtu : the new MTU size for the device.
6681 * Description: A driver entry point to change MTU size for the device.
6682 * Before changing the MTU the device must be stopped.
6684 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6688 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6690 struct s2io_nic *sp = netdev_priv(dev);
6693 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6694 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6699 if (netif_running(dev)) {
6700 s2io_stop_all_tx_queue(sp);
6702 ret = s2io_card_up(sp);
6704 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6708 s2io_wake_all_tx_queue(sp);
6709 } else { /* Device is down */
6710 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6711 u64 val64 = new_mtu;
6713 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6720 * s2io_set_link - Set the LInk status
6721 * @data: long pointer to device private structue
6722 * Description: Sets the link status for the adapter
6725 static void s2io_set_link(struct work_struct *work)
6727 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6729 struct net_device *dev = nic->dev;
6730 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6736 if (!netif_running(dev))
6739 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6740 /* The card is being reset, no point doing anything */
6744 subid = nic->pdev->subsystem_device;
6745 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6747 * Allow a small delay for the NICs self initiated
6748 * cleanup to complete.
6753 val64 = readq(&bar0->adapter_status);
6754 if (LINK_IS_UP(val64)) {
6755 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6756 if (verify_xena_quiescence(nic)) {
6757 val64 = readq(&bar0->adapter_control);
6758 val64 |= ADAPTER_CNTL_EN;
6759 writeq(val64, &bar0->adapter_control);
6760 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6761 nic->device_type, subid)) {
6762 val64 = readq(&bar0->gpio_control);
6763 val64 |= GPIO_CTRL_GPIO_0;
6764 writeq(val64, &bar0->gpio_control);
6765 val64 = readq(&bar0->gpio_control);
6767 val64 |= ADAPTER_LED_ON;
6768 writeq(val64, &bar0->adapter_control);
6770 nic->device_enabled_once = true;
6773 "%s: Error: device is not Quiescent\n",
6775 s2io_stop_all_tx_queue(nic);
6778 val64 = readq(&bar0->adapter_control);
6779 val64 |= ADAPTER_LED_ON;
6780 writeq(val64, &bar0->adapter_control);
6781 s2io_link(nic, LINK_UP);
6783 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6785 val64 = readq(&bar0->gpio_control);
6786 val64 &= ~GPIO_CTRL_GPIO_0;
6787 writeq(val64, &bar0->gpio_control);
6788 val64 = readq(&bar0->gpio_control);
6791 val64 = readq(&bar0->adapter_control);
6792 val64 = val64 & (~ADAPTER_LED_ON);
6793 writeq(val64, &bar0->adapter_control);
6794 s2io_link(nic, LINK_DOWN);
6796 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6802 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6804 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6805 u64 *temp2, int size)
6807 struct net_device *dev = sp->dev;
6808 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6810 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6811 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6814 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6816 * As Rx frame are not going to be processed,
6817 * using same mapped address for the Rxd
6820 rxdp1->Buffer0_ptr = *temp0;
6822 *skb = netdev_alloc_skb(dev, size);
6825 "%s: Out of memory to allocate %s\n",
6826 dev->name, "1 buf mode SKBs");
6827 stats->mem_alloc_fail_cnt++;
6830 stats->mem_allocated += (*skb)->truesize;
6831 /* storing the mapped addr in a temp variable
6832 * such it will be used for next rxd whose
6833 * Host Control is NULL
6835 rxdp1->Buffer0_ptr = *temp0 =
6836 pci_map_single(sp->pdev, (*skb)->data,
6837 size - NET_IP_ALIGN,
6838 PCI_DMA_FROMDEVICE);
6839 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6840 goto memalloc_failed;
6841 rxdp->Host_Control = (unsigned long) (*skb);
6843 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6844 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6845 /* Two buffer Mode */
6847 rxdp3->Buffer2_ptr = *temp2;
6848 rxdp3->Buffer0_ptr = *temp0;
6849 rxdp3->Buffer1_ptr = *temp1;
6851 *skb = netdev_alloc_skb(dev, size);
6854 "%s: Out of memory to allocate %s\n",
6857 stats->mem_alloc_fail_cnt++;
6860 stats->mem_allocated += (*skb)->truesize;
6861 rxdp3->Buffer2_ptr = *temp2 =
6862 pci_map_single(sp->pdev, (*skb)->data,
6864 PCI_DMA_FROMDEVICE);
6865 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6866 goto memalloc_failed;
6867 rxdp3->Buffer0_ptr = *temp0 =
6868 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6869 PCI_DMA_FROMDEVICE);
6870 if (pci_dma_mapping_error(sp->pdev,
6871 rxdp3->Buffer0_ptr)) {
6872 pci_unmap_single(sp->pdev,
6873 (dma_addr_t)rxdp3->Buffer2_ptr,
6875 PCI_DMA_FROMDEVICE);
6876 goto memalloc_failed;
6878 rxdp->Host_Control = (unsigned long) (*skb);
6880 /* Buffer-1 will be dummy buffer not used */
6881 rxdp3->Buffer1_ptr = *temp1 =
6882 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6883 PCI_DMA_FROMDEVICE);
6884 if (pci_dma_mapping_error(sp->pdev,
6885 rxdp3->Buffer1_ptr)) {
6886 pci_unmap_single(sp->pdev,
6887 (dma_addr_t)rxdp3->Buffer0_ptr,
6888 BUF0_LEN, PCI_DMA_FROMDEVICE);
6889 pci_unmap_single(sp->pdev,
6890 (dma_addr_t)rxdp3->Buffer2_ptr,
6892 PCI_DMA_FROMDEVICE);
6893 goto memalloc_failed;
6900 stats->pci_map_fail_cnt++;
6901 stats->mem_freed += (*skb)->truesize;
6902 dev_kfree_skb(*skb);
6906 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6909 struct net_device *dev = sp->dev;
6910 if (sp->rxd_mode == RXD_MODE_1) {
6911 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6912 } else if (sp->rxd_mode == RXD_MODE_3B) {
6913 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6914 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6915 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6919 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6921 int i, j, k, blk_cnt = 0, size;
6922 struct config_param *config = &sp->config;
6923 struct mac_info *mac_control = &sp->mac_control;
6924 struct net_device *dev = sp->dev;
6925 struct RxD_t *rxdp = NULL;
6926 struct sk_buff *skb = NULL;
6927 struct buffAdd *ba = NULL;
6928 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6930 /* Calculate the size based on ring mode */
6931 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6932 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6933 if (sp->rxd_mode == RXD_MODE_1)
6934 size += NET_IP_ALIGN;
6935 else if (sp->rxd_mode == RXD_MODE_3B)
6936 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6938 for (i = 0; i < config->rx_ring_num; i++) {
6939 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6940 struct ring_info *ring = &mac_control->rings[i];
6942 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6944 for (j = 0; j < blk_cnt; j++) {
6945 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6946 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
6947 if (sp->rxd_mode == RXD_MODE_3B)
6948 ba = &ring->ba[j][k];
6949 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
6957 set_rxd_buffer_size(sp, rxdp, size);
6959 /* flip the Ownership bit to Hardware */
6960 rxdp->Control_1 |= RXD_OWN_XENA;
6968 static int s2io_add_isr(struct s2io_nic *sp)
6971 struct net_device *dev = sp->dev;
6974 if (sp->config.intr_type == MSI_X)
6975 ret = s2io_enable_msi_x(sp);
6977 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6978 sp->config.intr_type = INTA;
6982 * Store the values of the MSIX table in
6983 * the struct s2io_nic structure
6985 store_xmsi_data(sp);
6987 /* After proper initialization of H/W, register ISR */
6988 if (sp->config.intr_type == MSI_X) {
6989 int i, msix_rx_cnt = 0;
6991 for (i = 0; i < sp->num_entries; i++) {
6992 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
6993 if (sp->s2io_entries[i].type ==
6995 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6997 err = request_irq(sp->entries[i].vector,
6998 s2io_msix_ring_handle,
7001 sp->s2io_entries[i].arg);
7002 } else if (sp->s2io_entries[i].type ==
7004 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7006 err = request_irq(sp->entries[i].vector,
7007 s2io_msix_fifo_handle,
7010 sp->s2io_entries[i].arg);
7013 /* if either data or addr is zero print it. */
7014 if (!(sp->msix_info[i].addr &&
7015 sp->msix_info[i].data)) {
7017 "%s @Addr:0x%llx Data:0x%llx\n",
7019 (unsigned long long)
7020 sp->msix_info[i].addr,
7021 (unsigned long long)
7022 ntohl(sp->msix_info[i].data));
7026 remove_msix_isr(sp);
7029 "%s:MSI-X-%d registration "
7030 "failed\n", dev->name, i);
7033 "%s: Defaulting to INTA\n",
7035 sp->config.intr_type = INTA;
7038 sp->s2io_entries[i].in_use =
7039 MSIX_REGISTERED_SUCCESS;
7043 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7045 "MSI-X-TX entries enabled through alarm vector\n");
7048 if (sp->config.intr_type == INTA) {
7049 err = request_irq(sp->pdev->irq, s2io_isr, IRQF_SHARED,
7052 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7060 static void s2io_rem_isr(struct s2io_nic *sp)
7062 if (sp->config.intr_type == MSI_X)
7063 remove_msix_isr(sp);
7065 remove_inta_isr(sp);
7068 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7071 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7072 register u64 val64 = 0;
7073 struct config_param *config;
7074 config = &sp->config;
7076 if (!is_s2io_card_up(sp))
7079 del_timer_sync(&sp->alarm_timer);
7080 /* If s2io_set_link task is executing, wait till it completes. */
7081 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7083 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7086 if (sp->config.napi) {
7088 if (config->intr_type == MSI_X) {
7089 for (; off < sp->config.rx_ring_num; off++)
7090 napi_disable(&sp->mac_control.rings[off].napi);
7093 napi_disable(&sp->napi);
7096 /* disable Tx and Rx traffic on the NIC */
7102 /* stop the tx queue, indicate link down */
7103 s2io_link(sp, LINK_DOWN);
7105 /* Check if the device is Quiescent and then Reset the NIC */
7107 /* As per the HW requirement we need to replenish the
7108 * receive buffer to avoid the ring bump. Since there is
7109 * no intention of processing the Rx frame at this pointwe are
7110 * just setting the ownership bit of rxd in Each Rx
7111 * ring to HW and set the appropriate buffer size
7112 * based on the ring mode
7114 rxd_owner_bit_reset(sp);
7116 val64 = readq(&bar0->adapter_status);
7117 if (verify_xena_quiescence(sp)) {
7118 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7125 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7126 "adapter status reads 0x%llx\n",
7127 (unsigned long long)val64);
7134 /* Free all Tx buffers */
7135 free_tx_buffers(sp);
7137 /* Free all Rx buffers */
7138 free_rx_buffers(sp);
7140 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7143 static void s2io_card_down(struct s2io_nic *sp)
7145 do_s2io_card_down(sp, 1);
7148 static int s2io_card_up(struct s2io_nic *sp)
7151 struct config_param *config;
7152 struct mac_info *mac_control;
7153 struct net_device *dev = sp->dev;
7156 /* Initialize the H/W I/O registers */
7159 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7167 * Initializing the Rx buffers. For now we are considering only 1
7168 * Rx ring and initializing buffers into 30 Rx blocks
7170 config = &sp->config;
7171 mac_control = &sp->mac_control;
7173 for (i = 0; i < config->rx_ring_num; i++) {
7174 struct ring_info *ring = &mac_control->rings[i];
7176 ring->mtu = dev->mtu;
7177 ring->lro = !!(dev->features & NETIF_F_LRO);
7178 ret = fill_rx_buffers(sp, ring, 1);
7180 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7183 free_rx_buffers(sp);
7186 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7187 ring->rx_bufs_left);
7190 /* Initialise napi */
7192 if (config->intr_type == MSI_X) {
7193 for (i = 0; i < sp->config.rx_ring_num; i++)
7194 napi_enable(&sp->mac_control.rings[i].napi);
7196 napi_enable(&sp->napi);
7200 /* Maintain the state prior to the open */
7201 if (sp->promisc_flg)
7202 sp->promisc_flg = 0;
7203 if (sp->m_cast_flg) {
7205 sp->all_multi_pos = 0;
7208 /* Setting its receive mode */
7209 s2io_set_multicast(dev);
7211 if (dev->features & NETIF_F_LRO) {
7212 /* Initialize max aggregatable pkts per session based on MTU */
7213 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7214 /* Check if we can use (if specified) user provided value */
7215 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7216 sp->lro_max_aggr_per_sess = lro_max_pkts;
7219 /* Enable Rx Traffic and interrupts on the NIC */
7220 if (start_nic(sp)) {
7221 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7223 free_rx_buffers(sp);
7227 /* Add interrupt service routine */
7228 if (s2io_add_isr(sp) != 0) {
7229 if (sp->config.intr_type == MSI_X)
7232 free_rx_buffers(sp);
7236 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7238 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7240 /* Enable select interrupts */
7241 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7242 if (sp->config.intr_type != INTA) {
7243 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7244 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7246 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7247 interruptible |= TX_PIC_INTR;
7248 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7255 * s2io_restart_nic - Resets the NIC.
7256 * @data : long pointer to the device private structure
7258 * This function is scheduled to be run by the s2io_tx_watchdog
7259 * function after 0.5 secs to reset the NIC. The idea is to reduce
7260 * the run time of the watch dog routine which is run holding a
7264 static void s2io_restart_nic(struct work_struct *work)
7266 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7267 struct net_device *dev = sp->dev;
7271 if (!netif_running(dev))
7275 if (s2io_card_up(sp)) {
7276 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7278 s2io_wake_all_tx_queue(sp);
7279 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7285 * s2io_tx_watchdog - Watchdog for transmit side.
7286 * @dev : Pointer to net device structure
7288 * This function is triggered if the Tx Queue is stopped
7289 * for a pre-defined amount of time when the Interface is still up.
7290 * If the Interface is jammed in such a situation, the hardware is
7291 * reset (by s2io_close) and restarted again (by s2io_open) to
7292 * overcome any problem that might have been caused in the hardware.
7297 static void s2io_tx_watchdog(struct net_device *dev)
7299 struct s2io_nic *sp = netdev_priv(dev);
7300 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7302 if (netif_carrier_ok(dev)) {
7303 swstats->watchdog_timer_cnt++;
7304 schedule_work(&sp->rst_timer_task);
7305 swstats->soft_reset_cnt++;
7310 * rx_osm_handler - To perform some OS related operations on SKB.
7311 * @sp: private member of the device structure,pointer to s2io_nic structure.
7312 * @skb : the socket buffer pointer.
7313 * @len : length of the packet
7314 * @cksum : FCS checksum of the frame.
7315 * @ring_no : the ring from which this RxD was extracted.
7317 * This function is called by the Rx interrupt serivce routine to perform
7318 * some OS related operations on the SKB before passing it to the upper
7319 * layers. It mainly checks if the checksum is OK, if so adds it to the
7320 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7321 * to the upper layer. If the checksum is wrong, it increments the Rx
7322 * packet error count, frees the SKB and returns error.
7324 * SUCCESS on success and -1 on failure.
7326 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7328 struct s2io_nic *sp = ring_data->nic;
7329 struct net_device *dev = ring_data->dev;
7330 struct sk_buff *skb = (struct sk_buff *)
7331 ((unsigned long)rxdp->Host_Control);
7332 int ring_no = ring_data->ring_no;
7333 u16 l3_csum, l4_csum;
7334 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7335 struct lro *uninitialized_var(lro);
7337 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7342 /* Check for parity error */
7344 swstats->parity_err_cnt++;
7346 err_mask = err >> 48;
7349 swstats->rx_parity_err_cnt++;
7353 swstats->rx_abort_cnt++;
7357 swstats->rx_parity_abort_cnt++;
7361 swstats->rx_rda_fail_cnt++;
7365 swstats->rx_unkn_prot_cnt++;
7369 swstats->rx_fcs_err_cnt++;
7373 swstats->rx_buf_size_err_cnt++;
7377 swstats->rx_rxd_corrupt_cnt++;
7381 swstats->rx_unkn_err_cnt++;
7385 * Drop the packet if bad transfer code. Exception being
7386 * 0x5, which could be due to unsupported IPv6 extension header.
7387 * In this case, we let stack handle the packet.
7388 * Note that in this case, since checksum will be incorrect,
7389 * stack will validate the same.
7391 if (err_mask != 0x5) {
7392 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7393 dev->name, err_mask);
7394 dev->stats.rx_crc_errors++;
7398 ring_data->rx_bufs_left -= 1;
7399 rxdp->Host_Control = 0;
7404 rxdp->Host_Control = 0;
7405 if (sp->rxd_mode == RXD_MODE_1) {
7406 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7409 } else if (sp->rxd_mode == RXD_MODE_3B) {
7410 int get_block = ring_data->rx_curr_get_info.block_index;
7411 int get_off = ring_data->rx_curr_get_info.offset;
7412 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7413 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7414 unsigned char *buff = skb_push(skb, buf0_len);
7416 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7417 memcpy(buff, ba->ba_0, buf0_len);
7418 skb_put(skb, buf2_len);
7421 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7422 ((!ring_data->lro) ||
7423 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7424 (dev->features & NETIF_F_RXCSUM)) {
7425 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7426 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7427 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7429 * NIC verifies if the Checksum of the received
7430 * frame is Ok or not and accordingly returns
7431 * a flag in the RxD.
7433 skb->ip_summed = CHECKSUM_UNNECESSARY;
7434 if (ring_data->lro) {
7439 ret = s2io_club_tcp_session(ring_data,
7444 case 3: /* Begin anew */
7447 case 1: /* Aggregate */
7448 lro_append_pkt(sp, lro, skb, tcp_len);
7450 case 4: /* Flush session */
7451 lro_append_pkt(sp, lro, skb, tcp_len);
7452 queue_rx_frame(lro->parent,
7454 clear_lro_session(lro);
7455 swstats->flush_max_pkts++;
7457 case 2: /* Flush both */
7458 lro->parent->data_len = lro->frags_len;
7459 swstats->sending_both++;
7460 queue_rx_frame(lro->parent,
7462 clear_lro_session(lro);
7464 case 0: /* sessions exceeded */
7465 case -1: /* non-TCP or not L2 aggregatable */
7467 * First pkt in session not
7468 * L3/L4 aggregatable
7473 "%s: Samadhana!!\n",
7480 * Packet with erroneous checksum, let the
7481 * upper layers deal with it.
7483 skb_checksum_none_assert(skb);
7486 skb_checksum_none_assert(skb);
7488 swstats->mem_freed += skb->truesize;
7490 skb_record_rx_queue(skb, ring_no);
7491 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7493 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7498 * s2io_link - stops/starts the Tx queue.
7499 * @sp : private member of the device structure, which is a pointer to the
7500 * s2io_nic structure.
7501 * @link : inidicates whether link is UP/DOWN.
7503 * This function stops/starts the Tx queue depending on whether the link
7504 * status of the NIC is is down or up. This is called by the Alarm
7505 * interrupt handler whenever a link change interrupt comes up.
7510 static void s2io_link(struct s2io_nic *sp, int link)
7512 struct net_device *dev = sp->dev;
7513 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7515 if (link != sp->last_link_state) {
7517 if (link == LINK_DOWN) {
7518 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7519 s2io_stop_all_tx_queue(sp);
7520 netif_carrier_off(dev);
7521 if (swstats->link_up_cnt)
7522 swstats->link_up_time =
7523 jiffies - sp->start_time;
7524 swstats->link_down_cnt++;
7526 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7527 if (swstats->link_down_cnt)
7528 swstats->link_down_time =
7529 jiffies - sp->start_time;
7530 swstats->link_up_cnt++;
7531 netif_carrier_on(dev);
7532 s2io_wake_all_tx_queue(sp);
7535 sp->last_link_state = link;
7536 sp->start_time = jiffies;
7540 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7541 * @sp : private member of the device structure, which is a pointer to the
7542 * s2io_nic structure.
7544 * This function initializes a few of the PCI and PCI-X configuration registers
7545 * with recommended values.
7550 static void s2io_init_pci(struct s2io_nic *sp)
7552 u16 pci_cmd = 0, pcix_cmd = 0;
7554 /* Enable Data Parity Error Recovery in PCI-X command register. */
7555 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7557 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7559 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7562 /* Set the PErr Response bit in PCI command register. */
7563 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7564 pci_write_config_word(sp->pdev, PCI_COMMAND,
7565 (pci_cmd | PCI_COMMAND_PARITY));
7566 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7569 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7574 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7575 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7576 "(%d) not supported\n", tx_fifo_num);
7578 if (tx_fifo_num < 1)
7581 tx_fifo_num = MAX_TX_FIFOS;
7583 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7587 *dev_multiq = multiq;
7589 if (tx_steering_type && (1 == tx_fifo_num)) {
7590 if (tx_steering_type != TX_DEFAULT_STEERING)
7592 "Tx steering is not supported with "
7593 "one fifo. Disabling Tx steering.\n");
7594 tx_steering_type = NO_STEERING;
7597 if ((tx_steering_type < NO_STEERING) ||
7598 (tx_steering_type > TX_DEFAULT_STEERING)) {
7600 "Requested transmit steering not supported\n");
7601 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7602 tx_steering_type = NO_STEERING;
7605 if (rx_ring_num > MAX_RX_RINGS) {
7607 "Requested number of rx rings not supported\n");
7608 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7610 rx_ring_num = MAX_RX_RINGS;
7613 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7614 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7615 "Defaulting to INTA\n");
7616 *dev_intr_type = INTA;
7619 if ((*dev_intr_type == MSI_X) &&
7620 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7621 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7622 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7623 "Defaulting to INTA\n");
7624 *dev_intr_type = INTA;
7627 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7628 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7629 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7633 for (i = 0; i < MAX_RX_RINGS; i++)
7634 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7635 DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7636 "supported\nDefaulting to %d\n",
7637 MAX_RX_BLOCKS_PER_RING);
7638 rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7645 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7646 * or Traffic class respectively.
7647 * @nic: device private variable
7648 * Description: The function configures the receive steering to
7649 * desired receive ring.
7650 * Return Value: SUCCESS on success and
7651 * '-1' on failure (endian settings incorrect).
7653 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7655 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7656 register u64 val64 = 0;
7658 if (ds_codepoint > 63)
7661 val64 = RTS_DS_MEM_DATA(ring);
7662 writeq(val64, &bar0->rts_ds_mem_data);
7664 val64 = RTS_DS_MEM_CTRL_WE |
7665 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7666 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7668 writeq(val64, &bar0->rts_ds_mem_ctrl);
7670 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7671 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7675 static const struct net_device_ops s2io_netdev_ops = {
7676 .ndo_open = s2io_open,
7677 .ndo_stop = s2io_close,
7678 .ndo_get_stats = s2io_get_stats,
7679 .ndo_start_xmit = s2io_xmit,
7680 .ndo_validate_addr = eth_validate_addr,
7681 .ndo_set_rx_mode = s2io_set_multicast,
7682 .ndo_do_ioctl = s2io_ioctl,
7683 .ndo_set_mac_address = s2io_set_mac_addr,
7684 .ndo_change_mtu = s2io_change_mtu,
7685 .ndo_set_features = s2io_set_features,
7686 .ndo_tx_timeout = s2io_tx_watchdog,
7687 #ifdef CONFIG_NET_POLL_CONTROLLER
7688 .ndo_poll_controller = s2io_netpoll,
7693 * s2io_init_nic - Initialization of the adapter .
7694 * @pdev : structure containing the PCI related information of the device.
7695 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7697 * The function initializes an adapter identified by the pci_dec structure.
7698 * All OS related initialization including memory and device structure and
7699 * initlaization of the device private variable is done. Also the swapper
7700 * control register is initialized to enable read and write into the I/O
7701 * registers of the device.
7703 * returns 0 on success and negative on failure.
7707 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7709 struct s2io_nic *sp;
7710 struct net_device *dev;
7712 int dma_flag = false;
7713 u32 mac_up, mac_down;
7714 u64 val64 = 0, tmp64 = 0;
7715 struct XENA_dev_config __iomem *bar0 = NULL;
7717 struct config_param *config;
7718 struct mac_info *mac_control;
7720 u8 dev_intr_type = intr_type;
7723 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7727 ret = pci_enable_device(pdev);
7730 "%s: pci_enable_device failed\n", __func__);
7734 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7735 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7737 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7739 "Unable to obtain 64bit DMA "
7740 "for consistent allocations\n");
7741 pci_disable_device(pdev);
7744 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7745 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7747 pci_disable_device(pdev);
7750 ret = pci_request_regions(pdev, s2io_driver_name);
7752 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7754 pci_disable_device(pdev);
7758 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7760 dev = alloc_etherdev(sizeof(struct s2io_nic));
7762 pci_disable_device(pdev);
7763 pci_release_regions(pdev);
7767 pci_set_master(pdev);
7768 pci_set_drvdata(pdev, dev);
7769 SET_NETDEV_DEV(dev, &pdev->dev);
7771 /* Private member variable initialized to s2io NIC structure */
7772 sp = netdev_priv(dev);
7775 sp->high_dma_flag = dma_flag;
7776 sp->device_enabled_once = false;
7777 if (rx_ring_mode == 1)
7778 sp->rxd_mode = RXD_MODE_1;
7779 if (rx_ring_mode == 2)
7780 sp->rxd_mode = RXD_MODE_3B;
7782 sp->config.intr_type = dev_intr_type;
7784 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7785 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7786 sp->device_type = XFRAME_II_DEVICE;
7788 sp->device_type = XFRAME_I_DEVICE;
7791 /* Initialize some PCI/PCI-X fields of the NIC. */
7795 * Setting the device configuration parameters.
7796 * Most of these parameters can be specified by the user during
7797 * module insertion as they are module loadable parameters. If
7798 * these parameters are not not specified during load time, they
7799 * are initialized with default values.
7801 config = &sp->config;
7802 mac_control = &sp->mac_control;
7804 config->napi = napi;
7805 config->tx_steering_type = tx_steering_type;
7807 /* Tx side parameters. */
7808 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7809 config->tx_fifo_num = MAX_TX_FIFOS;
7811 config->tx_fifo_num = tx_fifo_num;
7813 /* Initialize the fifos used for tx steering */
7814 if (config->tx_fifo_num < 5) {
7815 if (config->tx_fifo_num == 1)
7816 sp->total_tcp_fifos = 1;
7818 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7819 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7820 sp->total_udp_fifos = 1;
7821 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7823 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7824 FIFO_OTHER_MAX_NUM);
7825 sp->udp_fifo_idx = sp->total_tcp_fifos;
7826 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7827 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7830 config->multiq = dev_multiq;
7831 for (i = 0; i < config->tx_fifo_num; i++) {
7832 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7834 tx_cfg->fifo_len = tx_fifo_len[i];
7835 tx_cfg->fifo_priority = i;
7838 /* mapping the QoS priority to the configured fifos */
7839 for (i = 0; i < MAX_TX_FIFOS; i++)
7840 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7842 /* map the hashing selector table to the configured fifos */
7843 for (i = 0; i < config->tx_fifo_num; i++)
7844 sp->fifo_selector[i] = fifo_selector[i];
7847 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7848 for (i = 0; i < config->tx_fifo_num; i++) {
7849 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7851 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7852 if (tx_cfg->fifo_len < 65) {
7853 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7857 /* + 2 because one Txd for skb->data and one Txd for UFO */
7858 config->max_txds = MAX_SKB_FRAGS + 2;
7860 /* Rx side parameters. */
7861 config->rx_ring_num = rx_ring_num;
7862 for (i = 0; i < config->rx_ring_num; i++) {
7863 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7864 struct ring_info *ring = &mac_control->rings[i];
7866 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7867 rx_cfg->ring_priority = i;
7868 ring->rx_bufs_left = 0;
7869 ring->rxd_mode = sp->rxd_mode;
7870 ring->rxd_count = rxd_count[sp->rxd_mode];
7871 ring->pdev = sp->pdev;
7872 ring->dev = sp->dev;
7875 for (i = 0; i < rx_ring_num; i++) {
7876 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7878 rx_cfg->ring_org = RING_ORG_BUFF1;
7879 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7882 /* Setting Mac Control parameters */
7883 mac_control->rmac_pause_time = rmac_pause_time;
7884 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7885 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7888 /* initialize the shared memory used by the NIC and the host */
7889 if (init_shared_mem(sp)) {
7890 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7892 goto mem_alloc_failed;
7895 sp->bar0 = pci_ioremap_bar(pdev, 0);
7897 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7900 goto bar0_remap_failed;
7903 sp->bar1 = pci_ioremap_bar(pdev, 2);
7905 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7908 goto bar1_remap_failed;
7911 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7912 for (j = 0; j < MAX_TX_FIFOS; j++) {
7913 mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000);
7916 /* Driver entry points */
7917 dev->netdev_ops = &s2io_netdev_ops;
7918 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7919 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7920 NETIF_F_TSO | NETIF_F_TSO6 |
7921 NETIF_F_RXCSUM | NETIF_F_LRO;
7922 dev->features |= dev->hw_features |
7923 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7924 if (sp->device_type & XFRAME_II_DEVICE) {
7925 dev->hw_features |= NETIF_F_UFO;
7927 dev->features |= NETIF_F_UFO;
7929 if (sp->high_dma_flag == true)
7930 dev->features |= NETIF_F_HIGHDMA;
7931 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7932 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7933 INIT_WORK(&sp->set_link_task, s2io_set_link);
7935 pci_save_state(sp->pdev);
7937 /* Setting swapper control on the NIC, for proper reset operation */
7938 if (s2io_set_swapper(sp)) {
7939 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7942 goto set_swap_failed;
7945 /* Verify if the Herc works on the slot its placed into */
7946 if (sp->device_type & XFRAME_II_DEVICE) {
7947 mode = s2io_verify_pci_mode(sp);
7949 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
7952 goto set_swap_failed;
7956 if (sp->config.intr_type == MSI_X) {
7957 sp->num_entries = config->rx_ring_num + 1;
7958 ret = s2io_enable_msi_x(sp);
7961 ret = s2io_test_msi(sp);
7962 /* rollback MSI-X, will re-enable during add_isr() */
7963 remove_msix_isr(sp);
7968 "MSI-X requested but failed to enable\n");
7969 sp->config.intr_type = INTA;
7973 if (config->intr_type == MSI_X) {
7974 for (i = 0; i < config->rx_ring_num ; i++) {
7975 struct ring_info *ring = &mac_control->rings[i];
7977 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
7980 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
7983 /* Not needed for Herc */
7984 if (sp->device_type & XFRAME_I_DEVICE) {
7986 * Fix for all "FFs" MAC address problems observed on
7989 fix_mac_address(sp);
7994 * MAC address initialization.
7995 * For now only one mac address will be read and used.
7998 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7999 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8000 writeq(val64, &bar0->rmac_addr_cmd_mem);
8001 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8002 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8004 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8005 mac_down = (u32)tmp64;
8006 mac_up = (u32) (tmp64 >> 32);
8008 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8009 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8010 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8011 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8012 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8013 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8015 /* Set the factory defined MAC address initially */
8016 dev->addr_len = ETH_ALEN;
8017 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8019 /* initialize number of multicast & unicast MAC entries variables */
8020 if (sp->device_type == XFRAME_I_DEVICE) {
8021 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8022 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8023 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8024 } else if (sp->device_type == XFRAME_II_DEVICE) {
8025 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8026 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8027 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8030 /* store mac addresses from CAM to s2io_nic structure */
8031 do_s2io_store_unicast_mc(sp);
8033 /* Configure MSIX vector for number of rings configured plus one */
8034 if ((sp->device_type == XFRAME_II_DEVICE) &&
8035 (config->intr_type == MSI_X))
8036 sp->num_entries = config->rx_ring_num + 1;
8038 /* Store the values of the MSIX table in the s2io_nic structure */
8039 store_xmsi_data(sp);
8040 /* reset Nic and bring it to known state */
8044 * Initialize link state flags
8045 * and the card state parameter
8049 /* Initialize spinlocks */
8050 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8051 struct fifo_info *fifo = &mac_control->fifos[i];
8053 spin_lock_init(&fifo->tx_lock);
8057 * SXE-002: Configure link and activity LED to init state
8060 subid = sp->pdev->subsystem_device;
8061 if ((subid & 0xFF) >= 0x07) {
8062 val64 = readq(&bar0->gpio_control);
8063 val64 |= 0x0000800000000000ULL;
8064 writeq(val64, &bar0->gpio_control);
8065 val64 = 0x0411040400000000ULL;
8066 writeq(val64, (void __iomem *)bar0 + 0x2700);
8067 val64 = readq(&bar0->gpio_control);
8070 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8072 if (register_netdev(dev)) {
8073 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8075 goto register_failed;
8078 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8079 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8080 sp->product_name, pdev->revision);
8081 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8082 s2io_driver_version);
8083 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8084 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8085 if (sp->device_type & XFRAME_II_DEVICE) {
8086 mode = s2io_print_pci_mode(sp);
8089 unregister_netdev(dev);
8090 goto set_swap_failed;
8093 switch (sp->rxd_mode) {
8095 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8099 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8104 switch (sp->config.napi) {
8106 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8109 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8113 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8114 sp->config.tx_fifo_num);
8116 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8117 sp->config.rx_ring_num);
8119 switch (sp->config.intr_type) {
8121 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8124 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8127 if (sp->config.multiq) {
8128 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8129 struct fifo_info *fifo = &mac_control->fifos[i];
8131 fifo->multiq = config->multiq;
8133 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8136 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8139 switch (sp->config.tx_steering_type) {
8141 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8144 case TX_PRIORITY_STEERING:
8146 "%s: Priority steering enabled for transmit\n",
8149 case TX_DEFAULT_STEERING:
8151 "%s: Default steering enabled for transmit\n",
8155 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8159 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8161 /* Initialize device name */
8162 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8165 sp->vlan_strip_flag = 1;
8167 sp->vlan_strip_flag = 0;
8170 * Make Link state as off at this point, when the Link change
8171 * interrupt comes the state will be automatically changed to
8174 netif_carrier_off(dev);
8185 free_shared_mem(sp);
8186 pci_disable_device(pdev);
8187 pci_release_regions(pdev);
8194 * s2io_rem_nic - Free the PCI device
8195 * @pdev: structure containing the PCI related information of the device.
8196 * Description: This function is called by the Pci subsystem to release a
8197 * PCI device and free up all resource held up by the device. This could
8198 * be in response to a Hot plug event or when the driver is to be removed
8202 static void s2io_rem_nic(struct pci_dev *pdev)
8204 struct net_device *dev = pci_get_drvdata(pdev);
8205 struct s2io_nic *sp;
8208 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8212 sp = netdev_priv(dev);
8214 cancel_work_sync(&sp->rst_timer_task);
8215 cancel_work_sync(&sp->set_link_task);
8217 unregister_netdev(dev);
8219 free_shared_mem(sp);
8222 pci_release_regions(pdev);
8224 pci_disable_device(pdev);
8228 * s2io_starter - Entry point for the driver
8229 * Description: This function is the entry point for the driver. It verifies
8230 * the module loadable parameters and initializes PCI configuration space.
8233 static int __init s2io_starter(void)
8235 return pci_register_driver(&s2io_driver);
8239 * s2io_closer - Cleanup routine for the driver
8240 * Description: This function is the cleanup routine for the driver. It
8241 * unregisters the driver.
8244 static __exit void s2io_closer(void)
8246 pci_unregister_driver(&s2io_driver);
8247 DBG_PRINT(INIT_DBG, "cleanup done\n");
8250 module_init(s2io_starter);
8251 module_exit(s2io_closer);
8253 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8254 struct tcphdr **tcp, struct RxD_t *rxdp,
8255 struct s2io_nic *sp)
8258 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8260 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8262 "%s: Non-TCP frames not supported for LRO\n",
8267 /* Checking for DIX type or DIX type with VLAN */
8268 if ((l2_type == 0) || (l2_type == 4)) {
8269 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8271 * If vlan stripping is disabled and the frame is VLAN tagged,
8272 * shift the offset by the VLAN header size bytes.
8274 if ((!sp->vlan_strip_flag) &&
8275 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8276 ip_off += HEADER_VLAN_SIZE;
8278 /* LLC, SNAP etc are considered non-mergeable */
8282 *ip = (struct iphdr *)(buffer + ip_off);
8283 ip_len = (u8)((*ip)->ihl);
8285 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8290 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8293 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8294 if ((lro->iph->saddr != ip->saddr) ||
8295 (lro->iph->daddr != ip->daddr) ||
8296 (lro->tcph->source != tcp->source) ||
8297 (lro->tcph->dest != tcp->dest))
8302 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8304 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8307 static void initiate_new_session(struct lro *lro, u8 *l2h,
8308 struct iphdr *ip, struct tcphdr *tcp,
8309 u32 tcp_pyld_len, u16 vlan_tag)
8311 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8315 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8316 lro->tcp_ack = tcp->ack_seq;
8318 lro->total_len = ntohs(ip->tot_len);
8320 lro->vlan_tag = vlan_tag;
8322 * Check if we saw TCP timestamp.
8323 * Other consistency checks have already been done.
8325 if (tcp->doff == 8) {
8327 ptr = (__be32 *)(tcp+1);
8329 lro->cur_tsval = ntohl(*(ptr+1));
8330 lro->cur_tsecr = *(ptr+2);
8335 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8337 struct iphdr *ip = lro->iph;
8338 struct tcphdr *tcp = lro->tcph;
8339 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8341 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8343 /* Update L3 header */
8344 csum_replace2(&ip->check, ip->tot_len, htons(lro->total_len));
8345 ip->tot_len = htons(lro->total_len);
8347 /* Update L4 header */
8348 tcp->ack_seq = lro->tcp_ack;
8349 tcp->window = lro->window;
8351 /* Update tsecr field if this session has timestamps enabled */
8353 __be32 *ptr = (__be32 *)(tcp + 1);
8354 *(ptr+2) = lro->cur_tsecr;
8357 /* Update counters required for calculation of
8358 * average no. of packets aggregated.
8360 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8361 swstats->num_aggregations++;
8364 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8365 struct tcphdr *tcp, u32 l4_pyld)
8367 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8368 lro->total_len += l4_pyld;
8369 lro->frags_len += l4_pyld;
8370 lro->tcp_next_seq += l4_pyld;
8373 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8374 lro->tcp_ack = tcp->ack_seq;
8375 lro->window = tcp->window;
8379 /* Update tsecr and tsval from this packet */
8380 ptr = (__be32 *)(tcp+1);
8381 lro->cur_tsval = ntohl(*(ptr+1));
8382 lro->cur_tsecr = *(ptr + 2);
8386 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8387 struct tcphdr *tcp, u32 tcp_pyld_len)
8391 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8393 if (!tcp_pyld_len) {
8394 /* Runt frame or a pure ack */
8398 if (ip->ihl != 5) /* IP has options */
8401 /* If we see CE codepoint in IP header, packet is not mergeable */
8402 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8405 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8406 if (tcp->urg || tcp->psh || tcp->rst ||
8407 tcp->syn || tcp->fin ||
8408 tcp->ece || tcp->cwr || !tcp->ack) {
8410 * Currently recognize only the ack control word and
8411 * any other control field being set would result in
8412 * flushing the LRO session
8418 * Allow only one TCP timestamp option. Don't aggregate if
8419 * any other options are detected.
8421 if (tcp->doff != 5 && tcp->doff != 8)
8424 if (tcp->doff == 8) {
8425 ptr = (u8 *)(tcp + 1);
8426 while (*ptr == TCPOPT_NOP)
8428 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8431 /* Ensure timestamp value increases monotonically */
8433 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8436 /* timestamp echo reply should be non-zero */
8437 if (*((__be32 *)(ptr+6)) == 0)
8444 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8445 u8 **tcp, u32 *tcp_len, struct lro **lro,
8446 struct RxD_t *rxdp, struct s2io_nic *sp)
8449 struct tcphdr *tcph;
8452 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8454 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8459 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8461 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8462 tcph = (struct tcphdr *)*tcp;
8463 *tcp_len = get_l4_pyld_length(ip, tcph);
8464 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8465 struct lro *l_lro = &ring_data->lro0_n[i];
8466 if (l_lro->in_use) {
8467 if (check_for_socket_match(l_lro, ip, tcph))
8469 /* Sock pair matched */
8472 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8473 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8474 "expected 0x%x, actual 0x%x\n",
8476 (*lro)->tcp_next_seq,
8479 swstats->outof_sequence_pkts++;
8484 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8486 ret = 1; /* Aggregate */
8488 ret = 2; /* Flush both */
8494 /* Before searching for available LRO objects,
8495 * check if the pkt is L3/L4 aggregatable. If not
8496 * don't create new LRO session. Just send this
8499 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8502 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8503 struct lro *l_lro = &ring_data->lro0_n[i];
8504 if (!(l_lro->in_use)) {
8506 ret = 3; /* Begin anew */
8512 if (ret == 0) { /* sessions exceeded */
8513 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8521 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8525 update_L3L4_header(sp, *lro);
8528 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8529 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8530 update_L3L4_header(sp, *lro);
8531 ret = 4; /* Flush the LRO */
8535 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8542 static void clear_lro_session(struct lro *lro)
8544 static u16 lro_struct_size = sizeof(struct lro);
8546 memset(lro, 0, lro_struct_size);
8549 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8551 struct net_device *dev = skb->dev;
8552 struct s2io_nic *sp = netdev_priv(dev);
8554 skb->protocol = eth_type_trans(skb, dev);
8555 if (vlan_tag && sp->vlan_strip_flag)
8556 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
8557 if (sp->config.napi)
8558 netif_receive_skb(skb);
8563 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8564 struct sk_buff *skb, u32 tcp_len)
8566 struct sk_buff *first = lro->parent;
8567 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8569 first->len += tcp_len;
8570 first->data_len = lro->frags_len;
8571 skb_pull(skb, (skb->len - tcp_len));
8572 if (skb_shinfo(first)->frag_list)
8573 lro->last_frag->next = skb;
8575 skb_shinfo(first)->frag_list = skb;
8576 first->truesize += skb->truesize;
8577 lro->last_frag = skb;
8578 swstats->clubbed_frms_cnt++;
8582 * s2io_io_error_detected - called when PCI error is detected
8583 * @pdev: Pointer to PCI device
8584 * @state: The current pci connection state
8586 * This function is called after a PCI bus error affecting
8587 * this device has been detected.
8589 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8590 pci_channel_state_t state)
8592 struct net_device *netdev = pci_get_drvdata(pdev);
8593 struct s2io_nic *sp = netdev_priv(netdev);
8595 netif_device_detach(netdev);
8597 if (state == pci_channel_io_perm_failure)
8598 return PCI_ERS_RESULT_DISCONNECT;
8600 if (netif_running(netdev)) {
8601 /* Bring down the card, while avoiding PCI I/O */
8602 do_s2io_card_down(sp, 0);
8604 pci_disable_device(pdev);
8606 return PCI_ERS_RESULT_NEED_RESET;
8610 * s2io_io_slot_reset - called after the pci bus has been reset.
8611 * @pdev: Pointer to PCI device
8613 * Restart the card from scratch, as if from a cold-boot.
8614 * At this point, the card has exprienced a hard reset,
8615 * followed by fixups by BIOS, and has its config space
8616 * set up identically to what it was at cold boot.
8618 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8620 struct net_device *netdev = pci_get_drvdata(pdev);
8621 struct s2io_nic *sp = netdev_priv(netdev);
8623 if (pci_enable_device(pdev)) {
8624 pr_err("Cannot re-enable PCI device after reset.\n");
8625 return PCI_ERS_RESULT_DISCONNECT;
8628 pci_set_master(pdev);
8631 return PCI_ERS_RESULT_RECOVERED;
8635 * s2io_io_resume - called when traffic can start flowing again.
8636 * @pdev: Pointer to PCI device
8638 * This callback is called when the error recovery driver tells
8639 * us that its OK to resume normal operation.
8641 static void s2io_io_resume(struct pci_dev *pdev)
8643 struct net_device *netdev = pci_get_drvdata(pdev);
8644 struct s2io_nic *sp = netdev_priv(netdev);
8646 if (netif_running(netdev)) {
8647 if (s2io_card_up(sp)) {
8648 pr_err("Can't bring device back up after reset.\n");
8652 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8654 pr_err("Can't restore mac addr after reset.\n");
8659 netif_device_attach(netdev);
8660 netif_tx_wake_all_queues(netdev);