drivers/net/ethernet/nvidia/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42
  43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  44
  45 #define FORCEDETH_VERSION               "0.64"
  46 #define DRV_NAME                        "forcedeth"
  47
  48 #include <linux/module.h>
  49 #include <linux/types.h>
  50 #include <linux/pci.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/etherdevice.h>
  54 #include <linux/delay.h>
  55 #include <linux/sched.h>
  56 #include <linux/spinlock.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/timer.h>
  59 #include <linux/skbuff.h>
  60 #include <linux/mii.h>
  61 #include <linux/random.h>
  62 #include <linux/init.h>
  63 #include <linux/if_vlan.h>
  64 #include <linux/dma-mapping.h>
  65 #include <linux/slab.h>
  66 #include <linux/uaccess.h>
  67 #include <linux/prefetch.h>
  68 #include <linux/u64_stats_sync.h>
  69 #include <linux/io.h>
  70
  71 #include <asm/irq.h>
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  92 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  93 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  94 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  95 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  96 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  97 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  98 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  99 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
 100 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 101 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 102 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 103 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 104 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 105 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 106 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 107
 108 enum {
 109         NvRegIrqStatus = 0x000,
 110 #define NVREG_IRQSTAT_MIIEVENT  0x040
 111 #define NVREG_IRQSTAT_MASK              0x83ff
 112         NvRegIrqMask = 0x004,
 113 #define NVREG_IRQ_RX_ERROR              0x0001
 114 #define NVREG_IRQ_RX                    0x0002
 115 #define NVREG_IRQ_RX_NOBUF              0x0004
 116 #define NVREG_IRQ_TX_ERR                0x0008
 117 #define NVREG_IRQ_TX_OK                 0x0010
 118 #define NVREG_IRQ_TIMER                 0x0020
 119 #define NVREG_IRQ_LINK                  0x0040
 120 #define NVREG_IRQ_RX_FORCED             0x0080
 121 #define NVREG_IRQ_TX_FORCED             0x0100
 122 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 123 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 124 #define NVREG_IRQMASK_CPU               0x0060
 125 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 126 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 127 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 128
 129         NvRegUnknownSetupReg6 = 0x008,
 130 #define NVREG_UNKSETUP6_VAL             3
 131
 132 /*
 133  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 134  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 135  */
 136         NvRegPollingInterval = 0x00c,
 137 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 138 #define NVREG_POLL_DEFAULT_CPU  13
 139         NvRegMSIMap0 = 0x020,
 140         NvRegMSIMap1 = 0x024,
 141         NvRegMSIIrqMask = 0x030,
 142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 143         NvRegMisc1 = 0x080,
 144 #define NVREG_MISC1_PAUSE_TX    0x01
 145 #define NVREG_MISC1_HD          0x02
 146 #define NVREG_MISC1_FORCE       0x3b0f3c
 147
 148         NvRegMacReset = 0x34,
 149 #define NVREG_MAC_RESET_ASSERT  0x0F3
 150         NvRegTransmitterControl = 0x084,
 151 #define NVREG_XMITCTL_START     0x01
 152 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 153 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 154 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 155 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 156 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 157 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 158 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 159 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 160 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 161 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 162 #define NVREG_XMITCTL_DATA_START        0x00100000
 163 #define NVREG_XMITCTL_DATA_READY        0x00010000
 164 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 165         NvRegTransmitterStatus = 0x088,
 166 #define NVREG_XMITSTAT_BUSY     0x01
 167
 168         NvRegPacketFilterFlags = 0x8c,
 169 #define NVREG_PFF_PAUSE_RX      0x08
 170 #define NVREG_PFF_ALWAYS        0x7F0000
 171 #define NVREG_PFF_PROMISC       0x80
 172 #define NVREG_PFF_MYADDR        0x20
 173 #define NVREG_PFF_LOOPBACK      0x10
 174
 175         NvRegOffloadConfig = 0x90,
 176 #define NVREG_OFFLOAD_HOMEPHY   0x601
 177 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 178         NvRegReceiverControl = 0x094,
 179 #define NVREG_RCVCTL_START      0x01
 180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 181         NvRegReceiverStatus = 0x98,
 182 #define NVREG_RCVSTAT_BUSY      0x01
 183
 184         NvRegSlotTime = 0x9c,
 185 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 186 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 187 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 188 #define NVREG_SLOTTIME_HALF             0x0000ff00
 189 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 190 #define NVREG_SLOTTIME_MASK             0x000000ff
 191
 192         NvRegTxDeferral = 0xA0,
 193 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 194 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 195 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 198 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 199         NvRegRxDeferral = 0xA4,
 200 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 201         NvRegMacAddrA = 0xA8,
 202         NvRegMacAddrB = 0xAC,
 203         NvRegMulticastAddrA = 0xB0,
 204 #define NVREG_MCASTADDRA_FORCE  0x01
 205         NvRegMulticastAddrB = 0xB4,
 206         NvRegMulticastMaskA = 0xB8,
 207 #define NVREG_MCASTMASKA_NONE           0xffffffff
 208         NvRegMulticastMaskB = 0xBC,
 209 #define NVREG_MCASTMASKB_NONE           0xffff
 210
 211         NvRegPhyInterface = 0xC0,
 212 #define PHY_RGMII               0x10000000
 213         NvRegBackOffControl = 0xC4,
 214 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 215 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 216 #define NVREG_BKOFFCTRL_SELECT                  24
 217 #define NVREG_BKOFFCTRL_GEAR                    12
 218
 219         NvRegTxRingPhysAddr = 0x100,
 220         NvRegRxRingPhysAddr = 0x104,
 221         NvRegRingSizes = 0x108,
 222 #define NVREG_RINGSZ_TXSHIFT 0
 223 #define NVREG_RINGSZ_RXSHIFT 16
 224         NvRegTransmitPoll = 0x10c,
 225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 226         NvRegLinkSpeed = 0x110,
 227 #define NVREG_LINKSPEED_FORCE 0x10000
 228 #define NVREG_LINKSPEED_10      1000
 229 #define NVREG_LINKSPEED_100     100
 230 #define NVREG_LINKSPEED_1000    50
 231 #define NVREG_LINKSPEED_MASK    (0xFFF)
 232         NvRegUnknownSetupReg5 = 0x130,
 233 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 234         NvRegTxWatermark = 0x13c,
 235 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 236 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 237 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 238         NvRegTxRxControl = 0x144,
 239 #define NVREG_TXRXCTL_KICK      0x0001
 240 #define NVREG_TXRXCTL_BIT1      0x0002
 241 #define NVREG_TXRXCTL_BIT2      0x0004
 242 #define NVREG_TXRXCTL_IDLE      0x0008
 243 #define NVREG_TXRXCTL_RESET     0x0010
 244 #define NVREG_TXRXCTL_RXCHECK   0x0400
 245 #define NVREG_TXRXCTL_DESC_1    0
 246 #define NVREG_TXRXCTL_DESC_2    0x002100
 247 #define NVREG_TXRXCTL_DESC_3    0xc02200
 248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 249 #define NVREG_TXRXCTL_VLANINS   0x00080
 250         NvRegTxRingPhysAddrHigh = 0x148,
 251         NvRegRxRingPhysAddrHigh = 0x14C,
 252         NvRegTxPauseFrame = 0x170,
 253 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 257         NvRegTxPauseFrameLimit = 0x174,
 258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 259         NvRegMIIStatus = 0x180,
 260 #define NVREG_MIISTAT_ERROR             0x0001
 261 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 262 #define NVREG_MIISTAT_MASK_RW           0x0007
 263 #define NVREG_MIISTAT_MASK_ALL          0x000f
 264         NvRegMIIMask = 0x184,
 265 #define NVREG_MII_LINKCHANGE            0x0008
 266
 267         NvRegAdapterControl = 0x188,
 268 #define NVREG_ADAPTCTL_START    0x02
 269 #define NVREG_ADAPTCTL_LINKUP   0x04
 270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 271 #define NVREG_ADAPTCTL_RUNNING  0x100000
 272 #define NVREG_ADAPTCTL_PHYSHIFT 24
 273         NvRegMIISpeed = 0x18c,
 274 #define NVREG_MIISPEED_BIT8     (1<<8)
 275 #define NVREG_MIIDELAY  5
 276         NvRegMIIControl = 0x190,
 277 #define NVREG_MIICTL_INUSE      0x08000
 278 #define NVREG_MIICTL_WRITE      0x00400
 279 #define NVREG_MIICTL_ADDRSHIFT  5
 280         NvRegMIIData = 0x194,
 281         NvRegTxUnicast = 0x1a0,
 282         NvRegTxMulticast = 0x1a4,
 283         NvRegTxBroadcast = 0x1a8,
 284         NvRegWakeUpFlags = 0x200,
 285 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 288 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 289 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 290 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 291 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 295 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 296
 297         NvRegMgmtUnitGetVersion = 0x204,
 298 #define NVREG_MGMTUNITGETVERSION        0x01
 299         NvRegMgmtUnitVersion = 0x208,
 300 #define NVREG_MGMTUNITVERSION           0x08
 301         NvRegPowerCap = 0x268,
 302 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 303 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 304 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 305         NvRegPowerState = 0x26c,
 306 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 307 #define NVREG_POWERSTATE_VALID          0x0100
 308 #define NVREG_POWERSTATE_MASK           0x0003
 309 #define NVREG_POWERSTATE_D0             0x0000
 310 #define NVREG_POWERSTATE_D1             0x0001
 311 #define NVREG_POWERSTATE_D2             0x0002
 312 #define NVREG_POWERSTATE_D3             0x0003
 313         NvRegMgmtUnitControl = 0x278,
 314 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 315         NvRegTxCnt = 0x280,
 316         NvRegTxZeroReXmt = 0x284,
 317         NvRegTxOneReXmt = 0x288,
 318         NvRegTxManyReXmt = 0x28c,
 319         NvRegTxLateCol = 0x290,
 320         NvRegTxUnderflow = 0x294,
 321         NvRegTxLossCarrier = 0x298,
 322         NvRegTxExcessDef = 0x29c,
 323         NvRegTxRetryErr = 0x2a0,
 324         NvRegRxFrameErr = 0x2a4,
 325         NvRegRxExtraByte = 0x2a8,
 326         NvRegRxLateCol = 0x2ac,
 327         NvRegRxRunt = 0x2b0,
 328         NvRegRxFrameTooLong = 0x2b4,
 329         NvRegRxOverflow = 0x2b8,
 330         NvRegRxFCSErr = 0x2bc,
 331         NvRegRxFrameAlignErr = 0x2c0,
 332         NvRegRxLenErr = 0x2c4,
 333         NvRegRxUnicast = 0x2c8,
 334         NvRegRxMulticast = 0x2cc,
 335         NvRegRxBroadcast = 0x2d0,
 336         NvRegTxDef = 0x2d4,
 337         NvRegTxFrame = 0x2d8,
 338         NvRegRxCnt = 0x2dc,
 339         NvRegTxPause = 0x2e0,
 340         NvRegRxPause = 0x2e4,
 341         NvRegRxDropFrame = 0x2e8,
 342         NvRegVlanControl = 0x300,
 343 #define NVREG_VLANCONTROL_ENABLE        0x2000
 344         NvRegMSIXMap0 = 0x3e0,
 345         NvRegMSIXMap1 = 0x3e4,
 346         NvRegMSIXIrqStatus = 0x3f0,
 347
 348         NvRegPowerState2 = 0x600,
 349 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 350 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 351 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 352 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 353 };
 354
 355 /* Big endian: should work, but is untested */
 356 struct ring_desc {
 357         __le32 buf;
 358         __le32 flaglen;
 359 };
 360
 361 struct ring_desc_ex {
 362         __le32 bufhigh;
 363         __le32 buflow;
 364         __le32 txvlan;
 365         __le32 flaglen;
 366 };
 367
 368 union ring_type {
 369         struct ring_desc *orig;
 370         struct ring_desc_ex *ex;
 371 };
 372
 373 #define FLAG_MASK_V1 0xffff0000
 374 #define FLAG_MASK_V2 0xffffc000
 375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 377
 378 #define NV_TX_LASTPACKET        (1<<16)
 379 #define NV_TX_RETRYERROR        (1<<19)
 380 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 381 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 382 #define NV_TX_DEFERRED          (1<<26)
 383 #define NV_TX_CARRIERLOST       (1<<27)
 384 #define NV_TX_LATECOLLISION     (1<<28)
 385 #define NV_TX_UNDERFLOW         (1<<29)
 386 #define NV_TX_ERROR             (1<<30)
 387 #define NV_TX_VALID             (1<<31)
 388
 389 #define NV_TX2_LASTPACKET       (1<<29)
 390 #define NV_TX2_RETRYERROR       (1<<18)
 391 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 393 #define NV_TX2_DEFERRED         (1<<25)
 394 #define NV_TX2_CARRIERLOST      (1<<26)
 395 #define NV_TX2_LATECOLLISION    (1<<27)
 396 #define NV_TX2_UNDERFLOW        (1<<28)
 397 /* error and valid are the same for both */
 398 #define NV_TX2_ERROR            (1<<30)
 399 #define NV_TX2_VALID            (1<<31)
 400 #define NV_TX2_TSO              (1<<28)
 401 #define NV_TX2_TSO_SHIFT        14
 402 #define NV_TX2_TSO_MAX_SHIFT    14
 403 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 404 #define NV_TX2_CHECKSUM_L3      (1<<27)
 405 #define NV_TX2_CHECKSUM_L4      (1<<26)
 406
 407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 408
 409 #define NV_RX_DESCRIPTORVALID   (1<<16)
 410 #define NV_RX_MISSEDFRAME       (1<<17)
 411 #define NV_RX_SUBSTRACT1        (1<<18)
 412 #define NV_RX_ERROR1            (1<<23)
 413 #define NV_RX_ERROR2            (1<<24)
 414 #define NV_RX_ERROR3            (1<<25)
 415 #define NV_RX_ERROR4            (1<<26)
 416 #define NV_RX_CRCERR            (1<<27)
 417 #define NV_RX_OVERFLOW          (1<<28)
 418 #define NV_RX_FRAMINGERR        (1<<29)
 419 #define NV_RX_ERROR             (1<<30)
 420 #define NV_RX_AVAIL             (1<<31)
 421 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 422
 423 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 424 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 425 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 426 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 427 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 428 #define NV_RX2_SUBSTRACT1       (1<<25)
 429 #define NV_RX2_ERROR1           (1<<18)
 430 #define NV_RX2_ERROR2           (1<<19)
 431 #define NV_RX2_ERROR3           (1<<20)
 432 #define NV_RX2_ERROR4           (1<<21)
 433 #define NV_RX2_CRCERR           (1<<22)
 434 #define NV_RX2_OVERFLOW         (1<<23)
 435 #define NV_RX2_FRAMINGERR       (1<<24)
 436 /* error and avail are the same for both */
 437 #define NV_RX2_ERROR            (1<<30)
 438 #define NV_RX2_AVAIL            (1<<31)
 439 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 440
 441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 442 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 443
 444 /* Miscellaneous hardware related defines: */
 445 #define NV_PCI_REGSZ_VER1       0x270
 446 #define NV_PCI_REGSZ_VER2       0x2d4
 447 #define NV_PCI_REGSZ_VER3       0x604
 448 #define NV_PCI_REGSZ_MAX        0x604
 449
 450 /* various timeout delays: all in usec */
 451 #define NV_TXRX_RESET_DELAY     4
 452 #define NV_TXSTOP_DELAY1        10
 453 #define NV_TXSTOP_DELAY1MAX     500000
 454 #define NV_TXSTOP_DELAY2        100
 455 #define NV_RXSTOP_DELAY1        10
 456 #define NV_RXSTOP_DELAY1MAX     500000
 457 #define NV_RXSTOP_DELAY2        100
 458 #define NV_SETUP5_DELAY         5
 459 #define NV_SETUP5_DELAYMAX      50000
 460 #define NV_POWERUP_DELAY        5
 461 #define NV_POWERUP_DELAYMAX     5000
 462 #define NV_MIIBUSY_DELAY        50
 463 #define NV_MIIPHY_DELAY 10
 464 #define NV_MIIPHY_DELAYMAX      10000
 465 #define NV_MAC_RESET_DELAY      64
 466
 467 #define NV_WAKEUPPATTERNS       5
 468 #define NV_WAKEUPMASKENTRIES    4
 469
 470 /* General driver defaults */
 471 #define NV_WATCHDOG_TIMEO       (5*HZ)
 472
 473 #define RX_RING_DEFAULT         512
 474 #define TX_RING_DEFAULT         256
 475 #define RX_RING_MIN             128
 476 #define TX_RING_MIN             64
 477 #define RING_MAX_DESC_VER_1     1024
 478 #define RING_MAX_DESC_VER_2_3   16384
 479
 480 /* rx/tx mac addr + type + vlan + align + slack*/
 481 #define NV_RX_HEADERS           (64)
 482 /* even more slack. */
 483 #define NV_RX_ALLOC_PAD         (64)
 484
 485 /* maximum mtu size */
 486 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 487 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 488
 489 #define OOM_REFILL      (1+HZ/20)
 490 #define POLL_WAIT       (1+HZ/100)
 491 #define LINK_TIMEOUT    (3*HZ)
 492 #define STATS_INTERVAL  (10*HZ)
 493
 494 /*
 495  * desc_ver values:
 496  * The nic supports three different descriptor types:
 497  * - DESC_VER_1: Original
 498  * - DESC_VER_2: support for jumbo frames.
 499  * - DESC_VER_3: 64-bit format.
 500  */
 501 #define DESC_VER_1      1
 502 #define DESC_VER_2      2
 503 #define DESC_VER_3      3
 504
 505 /* PHY defines */
 506 #define PHY_OUI_MARVELL         0x5043
 507 #define PHY_OUI_CICADA          0x03f1
 508 #define PHY_OUI_VITESSE         0x01c1
 509 #define PHY_OUI_REALTEK         0x0732
 510 #define PHY_OUI_REALTEK2        0x0020
 511 #define PHYID1_OUI_MASK 0x03ff
 512 #define PHYID1_OUI_SHFT 6
 513 #define PHYID2_OUI_MASK 0xfc00
 514 #define PHYID2_OUI_SHFT 10
 515 #define PHYID2_MODEL_MASK               0x03f0
 516 #define PHY_MODEL_REALTEK_8211          0x0110
 517 #define PHY_REV_MASK                    0x0001
 518 #define PHY_REV_REALTEK_8211B           0x0000
 519 #define PHY_REV_REALTEK_8211C           0x0001
 520 #define PHY_MODEL_REALTEK_8201          0x0200
 521 #define PHY_MODEL_MARVELL_E3016         0x0220
 522 #define PHY_MARVELL_E3016_INITMASK      0x0300
 523 #define PHY_CICADA_INIT1        0x0f000
 524 #define PHY_CICADA_INIT2        0x0e00
 525 #define PHY_CICADA_INIT3        0x01000
 526 #define PHY_CICADA_INIT4        0x0200
 527 #define PHY_CICADA_INIT5        0x0004
 528 #define PHY_CICADA_INIT6        0x02000
 529 #define PHY_VITESSE_INIT_REG1   0x1f
 530 #define PHY_VITESSE_INIT_REG2   0x10
 531 #define PHY_VITESSE_INIT_REG3   0x11
 532 #define PHY_VITESSE_INIT_REG4   0x12
 533 #define PHY_VITESSE_INIT_MSK1   0xc
 534 #define PHY_VITESSE_INIT_MSK2   0x0180
 535 #define PHY_VITESSE_INIT1       0x52b5
 536 #define PHY_VITESSE_INIT2       0xaf8a
 537 #define PHY_VITESSE_INIT3       0x8
 538 #define PHY_VITESSE_INIT4       0x8f8a
 539 #define PHY_VITESSE_INIT5       0xaf86
 540 #define PHY_VITESSE_INIT6       0x8f86
 541 #define PHY_VITESSE_INIT7       0xaf82
 542 #define PHY_VITESSE_INIT8       0x0100
 543 #define PHY_VITESSE_INIT9       0x8f82
 544 #define PHY_VITESSE_INIT10      0x0
 545 #define PHY_REALTEK_INIT_REG1   0x1f
 546 #define PHY_REALTEK_INIT_REG2   0x19
 547 #define PHY_REALTEK_INIT_REG3   0x13
 548 #define PHY_REALTEK_INIT_REG4   0x14
 549 #define PHY_REALTEK_INIT_REG5   0x18
 550 #define PHY_REALTEK_INIT_REG6   0x11
 551 #define PHY_REALTEK_INIT_REG7   0x01
 552 #define PHY_REALTEK_INIT1       0x0000
 553 #define PHY_REALTEK_INIT2       0x8e00
 554 #define PHY_REALTEK_INIT3       0x0001
 555 #define PHY_REALTEK_INIT4       0xad17
 556 #define PHY_REALTEK_INIT5       0xfb54
 557 #define PHY_REALTEK_INIT6       0xf5c7
 558 #define PHY_REALTEK_INIT7       0x1000
 559 #define PHY_REALTEK_INIT8       0x0003
 560 #define PHY_REALTEK_INIT9       0x0008
 561 #define PHY_REALTEK_INIT10      0x0005
 562 #define PHY_REALTEK_INIT11      0x0200
 563 #define PHY_REALTEK_INIT_MSK1   0x0003
 564
 565 #define PHY_GIGABIT     0x0100
 566
 567 #define PHY_TIMEOUT     0x1
 568 #define PHY_ERROR       0x2
 569
 570 #define PHY_100 0x1
 571 #define PHY_1000        0x2
 572 #define PHY_HALF        0x100
 573
 574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 576 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 577 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 578 #define NV_PAUSEFRAME_RX_REQ     0x0010
 579 #define NV_PAUSEFRAME_TX_REQ     0x0020
 580 #define NV_PAUSEFRAME_AUTONEG    0x0040
 581
 582 /* MSI/MSI-X defines */
 583 #define NV_MSI_X_MAX_VECTORS  8
 584 #define NV_MSI_X_VECTORS_MASK 0x000f
 585 #define NV_MSI_CAPABLE        0x0010
 586 #define NV_MSI_X_CAPABLE      0x0020
 587 #define NV_MSI_ENABLED        0x0040
 588 #define NV_MSI_X_ENABLED      0x0080
 589
 590 #define NV_MSI_X_VECTOR_ALL   0x0
 591 #define NV_MSI_X_VECTOR_RX    0x0
 592 #define NV_MSI_X_VECTOR_TX    0x1
 593 #define NV_MSI_X_VECTOR_OTHER 0x2
 594
 595 #define NV_MSI_PRIV_OFFSET 0x68
 596 #define NV_MSI_PRIV_VALUE  0xffffffff
 597
 598 #define NV_RESTART_TX         0x1
 599 #define NV_RESTART_RX         0x2
 600
 601 #define NV_TX_LIMIT_COUNT     16
 602
 603 #define NV_DYNAMIC_THRESHOLD        4
 604 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 605
 606 /* statistics */
 607 struct nv_ethtool_str {
 608         char name[ETH_GSTRING_LEN];
 609 };
 610
 611 static const struct nv_ethtool_str nv_estats_str[] = {
 612         { "tx_bytes" }, /* includes Ethernet FCS CRC */
 613         { "tx_zero_rexmt" },
 614         { "tx_one_rexmt" },
 615         { "tx_many_rexmt" },
 616         { "tx_late_collision" },
 617         { "tx_fifo_errors" },
 618         { "tx_carrier_errors" },
 619         { "tx_excess_deferral" },
 620         { "tx_retry_error" },
 621         { "rx_frame_error" },
 622         { "rx_extra_byte" },
 623         { "rx_late_collision" },
 624         { "rx_runt" },
 625         { "rx_frame_too_long" },
 626         { "rx_over_errors" },
 627         { "rx_crc_errors" },
 628         { "rx_frame_align_error" },
 629         { "rx_length_error" },
 630         { "rx_unicast" },
 631         { "rx_multicast" },
 632         { "rx_broadcast" },
 633         { "rx_packets" },
 634         { "rx_errors_total" },
 635         { "tx_errors_total" },
 636
 637         /* version 2 stats */
 638         { "tx_deferral" },
 639         { "tx_packets" },
 640         { "rx_bytes" }, /* includes Ethernet FCS CRC */
 641         { "tx_pause" },
 642         { "rx_pause" },
 643         { "rx_drop_frame" },
 644
 645         /* version 3 stats */
 646         { "tx_unicast" },
 647         { "tx_multicast" },
 648         { "tx_broadcast" }
 649 };
 650
 651 struct nv_ethtool_stats {
 652         u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
 653         u64 tx_zero_rexmt;
 654         u64 tx_one_rexmt;
 655         u64 tx_many_rexmt;
 656         u64 tx_late_collision;
 657         u64 tx_fifo_errors;
 658         u64 tx_carrier_errors;
 659         u64 tx_excess_deferral;
 660         u64 tx_retry_error;
 661         u64 rx_frame_error;
 662         u64 rx_extra_byte;
 663         u64 rx_late_collision;
 664         u64 rx_runt;
 665         u64 rx_frame_too_long;
 666         u64 rx_over_errors;
 667         u64 rx_crc_errors;
 668         u64 rx_frame_align_error;
 669         u64 rx_length_error;
 670         u64 rx_unicast;
 671         u64 rx_multicast;
 672         u64 rx_broadcast;
 673         u64 rx_packets; /* should be ifconfig->rx_packets */
 674         u64 rx_errors_total;
 675         u64 tx_errors_total;
 676
 677         /* version 2 stats */
 678         u64 tx_deferral;
 679         u64 tx_packets; /* should be ifconfig->tx_packets */
 680         u64 rx_bytes;   /* should be ifconfig->rx_bytes + 4*rx_packets */
 681         u64 tx_pause;
 682         u64 rx_pause;
 683         u64 rx_drop_frame;
 684
 685         /* version 3 stats */
 686         u64 tx_unicast;
 687         u64 tx_multicast;
 688         u64 tx_broadcast;
 689 };
 690
 691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 694
 695 /* diagnostics */
 696 #define NV_TEST_COUNT_BASE 3
 697 #define NV_TEST_COUNT_EXTENDED 4
 698
 699 static const struct nv_ethtool_str nv_etests_str[] = {
 700         { "link      (online/offline)" },
 701         { "register  (offline)       " },
 702         { "interrupt (offline)       " },
 703         { "loopback  (offline)       " }
 704 };
 705
 706 struct register_test {
 707         __u32 reg;
 708         __u32 mask;
 709 };
 710
 711 static const struct register_test nv_registers_test[] = {
 712         { NvRegUnknownSetupReg6, 0x01 },
 713         { NvRegMisc1, 0x03c },
 714         { NvRegOffloadConfig, 0x03ff },
 715         { NvRegMulticastAddrA, 0xffffffff },
 716         { NvRegTxWatermark, 0x0ff },
 717         { NvRegWakeUpFlags, 0x07777 },
 718         { 0, 0 }
 719 };
 720
 721 struct nv_skb_map {
 722         struct sk_buff *skb;
 723         dma_addr_t dma;
 724         unsigned int dma_len:31;
 725         unsigned int dma_single:1;
 726         struct ring_desc_ex *first_tx_desc;
 727         struct nv_skb_map *next_tx_ctx;
 728 };
 729
 730 /*
 731  * SMP locking:
 732  * All hardware access under netdev_priv(dev)->lock, except the performance
 733  * critical parts:
 734  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 735  *      by the arch code for interrupts.
 736  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 737  *      needs netdev_priv(dev)->lock :-(
 738  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 739  *
 740  * Hardware stats updates are protected by hwstats_lock:
 741  * - updated by nv_do_stats_poll (timer). This is meant to avoid
 742  *   integer wraparound in the NIC stats registers, at low frequency
 743  *   (0.1 Hz)
 744  * - updated by nv_get_ethtool_stats + nv_get_stats64
 745  *
 746  * Software stats are accessed only through 64b synchronization points
 747  * and are not subject to other synchronization techniques (single
 748  * update thread on the TX or RX paths).
 749  */
 750
 751 /* in dev: base, irq */
 752 struct fe_priv {
 753         spinlock_t lock;
 754
 755         struct net_device *dev;
 756         struct napi_struct napi;
 757
 758         /* hardware stats are updated in syscall and timer */
 759         spinlock_t hwstats_lock;
 760         struct nv_ethtool_stats estats;
 761
 762         int in_shutdown;
 763         u32 linkspeed;
 764         int duplex;
 765         int autoneg;
 766         int fixed_mode;
 767         int phyaddr;
 768         int wolenabled;
 769         unsigned int phy_oui;
 770         unsigned int phy_model;
 771         unsigned int phy_rev;
 772         u16 gigabit;
 773         int intr_test;
 774         int recover_error;
 775         int quiet_count;
 776
 777         /* General data: RO fields */
 778         dma_addr_t ring_addr;
 779         struct pci_dev *pci_dev;
 780         u32 orig_mac[2];
 781         u32 events;
 782         u32 irqmask;
 783         u32 desc_ver;
 784         u32 txrxctl_bits;
 785         u32 vlanctl_bits;
 786         u32 driver_data;
 787         u32 device_id;
 788         u32 register_size;
 789         u32 mac_in_use;
 790         int mgmt_version;
 791         int mgmt_sema;
 792
 793         void __iomem *base;
 794
 795         /* rx specific fields.
 796          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 797          */
 798         union ring_type get_rx, put_rx, first_rx, last_rx;
 799         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 800         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 801         struct nv_skb_map *rx_skb;
 802
 803         union ring_type rx_ring;
 804         unsigned int rx_buf_sz;
 805         unsigned int pkt_limit;
 806         struct timer_list oom_kick;
 807         struct timer_list nic_poll;
 808         struct timer_list stats_poll;
 809         u32 nic_poll_irq;
 810         int rx_ring_size;
 811
 812         /* RX software stats */
 813         struct u64_stats_sync swstats_rx_syncp;
 814         u64 stat_rx_packets;
 815         u64 stat_rx_bytes; /* not always available in HW */
 816         u64 stat_rx_missed_errors;
 817         u64 stat_rx_dropped;
 818
 819         /* media detection workaround.
 820          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 821          */
 822         int need_linktimer;
 823         unsigned long link_timeout;
 824         /*
 825          * tx specific fields.
 826          */
 827         union ring_type get_tx, put_tx, first_tx, last_tx;
 828         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 829         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 830         struct nv_skb_map *tx_skb;
 831
 832         union ring_type tx_ring;
 833         u32 tx_flags;
 834         int tx_ring_size;
 835         int tx_limit;
 836         u32 tx_pkts_in_progress;
 837         struct nv_skb_map *tx_change_owner;
 838         struct nv_skb_map *tx_end_flip;
 839         int tx_stop;
 840
 841         /* TX software stats */
 842         struct u64_stats_sync swstats_tx_syncp;
 843         u64 stat_tx_packets; /* not always available in HW */
 844         u64 stat_tx_bytes;
 845         u64 stat_tx_dropped;
 846
 847         /* msi/msi-x fields */
 848         u32 msi_flags;
 849         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 850
 851         /* flow control */
 852         u32 pause_flags;
 853
 854         /* power saved state */
 855         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 856
 857         /* for different msi-x irq type */
 858         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 859         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 860         char name_other[IFNAMSIZ + 6];    /* -other */
 861 };
 862
 863 /*
 864  * Maximum number of loops until we assume that a bit in the irq mask
 865  * is stuck. Overridable with module param.
 866  */
 867 static int max_interrupt_work = 4;
 868
 869 /*
 870  * Optimization can be either throuput mode or cpu mode
 871  *
 872  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 873  * CPU Mode: Interrupts are controlled by a timer.
 874  */
 875 enum {
 876         NV_OPTIMIZATION_MODE_THROUGHPUT,
 877         NV_OPTIMIZATION_MODE_CPU,
 878         NV_OPTIMIZATION_MODE_DYNAMIC
 879 };
 880 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 881
 882 /*
 883  * Poll interval for timer irq
 884  *
 885  * This interval determines how frequent an interrupt is generated.
 886  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 887  * Min = 0, and Max = 65535
 888  */
 889 static int poll_interval = -1;
 890
 891 /*
 892  * MSI interrupts
 893  */
 894 enum {
 895         NV_MSI_INT_DISABLED,
 896         NV_MSI_INT_ENABLED
 897 };
 898 static int msi = NV_MSI_INT_ENABLED;
 899
 900 /*
 901  * MSIX interrupts
 902  */
 903 enum {
 904         NV_MSIX_INT_DISABLED,
 905         NV_MSIX_INT_ENABLED
 906 };
 907 static int msix = NV_MSIX_INT_ENABLED;
 908
 909 /*
 910  * DMA 64bit
 911  */
 912 enum {
 913         NV_DMA_64BIT_DISABLED,
 914         NV_DMA_64BIT_ENABLED
 915 };
 916 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 917
 918 /*
 919  * Debug output control for tx_timeout
 920  */
 921 static bool debug_tx_timeout = false;
 922
 923 /*
 924  * Crossover Detection
 925  * Realtek 8201 phy + some OEM boards do not work properly.
 926  */
 927 enum {
 928         NV_CROSSOVER_DETECTION_DISABLED,
 929         NV_CROSSOVER_DETECTION_ENABLED
 930 };
 931 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 932
 933 /*
 934  * Power down phy when interface is down (persists through reboot;
 935  * older Linux and other OSes may not power it up again)
 936  */
 937 static int phy_power_down;
 938
 939 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 940 {
 941         return netdev_priv(dev);
 942 }
 943
 944 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 945 {
 946         return ((struct fe_priv *)netdev_priv(dev))->base;
 947 }
 948
 949 static inline void pci_push(u8 __iomem *base)
 950 {
 951         /* force out pending posted writes */
 952         readl(base);
 953 }
 954
 955 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 956 {
 957         return le32_to_cpu(prd->flaglen)
 958                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 959 }
 960
 961 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 962 {
 963         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 964 }
 965
 966 static bool nv_optimized(struct fe_priv *np)
 967 {
 968         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 969                 return false;
 970         return true;
 971 }
 972
 973 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 974                      int delay, int delaymax)
 975 {
 976         u8 __iomem *base = get_hwbase(dev);
 977
 978         pci_push(base);
 979         do {
 980                 udelay(delay);
 981                 delaymax -= delay;
 982                 if (delaymax < 0)
 983                         return 1;
 984         } while ((readl(base + offset) & mask) != target);
 985         return 0;
 986 }
 987
 988 #define NV_SETUP_RX_RING 0x01
 989 #define NV_SETUP_TX_RING 0x02
 990
 991 static inline u32 dma_low(dma_addr_t addr)
 992 {
 993         return addr;
 994 }
 995
 996 static inline u32 dma_high(dma_addr_t addr)
 997 {
 998         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 999 }
1000
1001 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1002 {
1003         struct fe_priv *np = get_nvpriv(dev);
1004         u8 __iomem *base = get_hwbase(dev);
1005
1006         if (!nv_optimized(np)) {
1007                 if (rxtx_flags & NV_SETUP_RX_RING)
1008                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1009                 if (rxtx_flags & NV_SETUP_TX_RING)
1010                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1011         } else {
1012                 if (rxtx_flags & NV_SETUP_RX_RING) {
1013                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1014                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1015                 }
1016                 if (rxtx_flags & NV_SETUP_TX_RING) {
1017                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1018                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1019                 }
1020         }
1021 }
1022
1023 static void free_rings(struct net_device *dev)
1024 {
1025         struct fe_priv *np = get_nvpriv(dev);
1026
1027         if (!nv_optimized(np)) {
1028                 if (np->rx_ring.orig)
1029                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1030                                             np->rx_ring.orig, np->ring_addr);
1031         } else {
1032                 if (np->rx_ring.ex)
1033                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1034                                             np->rx_ring.ex, np->ring_addr);
1035         }
1036         kfree(np->rx_skb);
1037         kfree(np->tx_skb);
1038 }
1039
1040 static int using_multi_irqs(struct net_device *dev)
1041 {
1042         struct fe_priv *np = get_nvpriv(dev);
1043
1044         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1045             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1046              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1047                 return 0;
1048         else
1049                 return 1;
1050 }
1051
1052 static void nv_txrx_gate(struct net_device *dev, bool gate)
1053 {
1054         struct fe_priv *np = get_nvpriv(dev);
1055         u8 __iomem *base = get_hwbase(dev);
1056         u32 powerstate;
1057
1058         if (!np->mac_in_use &&
1059             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1060                 powerstate = readl(base + NvRegPowerState2);
1061                 if (gate)
1062                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1063                 else
1064                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1065                 writel(powerstate, base + NvRegPowerState2);
1066         }
1067 }
1068
1069 static void nv_enable_irq(struct net_device *dev)
1070 {
1071         struct fe_priv *np = get_nvpriv(dev);
1072
1073         if (!using_multi_irqs(dev)) {
1074                 if (np->msi_flags & NV_MSI_X_ENABLED)
1075                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1076                 else
1077                         enable_irq(np->pci_dev->irq);
1078         } else {
1079                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1080                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1081                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1082         }
1083 }
1084
1085 static void nv_disable_irq(struct net_device *dev)
1086 {
1087         struct fe_priv *np = get_nvpriv(dev);
1088
1089         if (!using_multi_irqs(dev)) {
1090                 if (np->msi_flags & NV_MSI_X_ENABLED)
1091                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1092                 else
1093                         disable_irq(np->pci_dev->irq);
1094         } else {
1095                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1096                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1097                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1098         }
1099 }
1100
1101 /* In MSIX mode, a write to irqmask behaves as XOR */
1102 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1103 {
1104         u8 __iomem *base = get_hwbase(dev);
1105
1106         writel(mask, base + NvRegIrqMask);
1107 }
1108
1109 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1110 {
1111         struct fe_priv *np = get_nvpriv(dev);
1112         u8 __iomem *base = get_hwbase(dev);
1113
1114         if (np->msi_flags & NV_MSI_X_ENABLED) {
1115                 writel(mask, base + NvRegIrqMask);
1116         } else {
1117                 if (np->msi_flags & NV_MSI_ENABLED)
1118                         writel(0, base + NvRegMSIIrqMask);
1119                 writel(0, base + NvRegIrqMask);
1120         }
1121 }
1122
1123 static void nv_napi_enable(struct net_device *dev)
1124 {
1125         struct fe_priv *np = get_nvpriv(dev);
1126
1127         napi_enable(&np->napi);
1128 }
1129
1130 static void nv_napi_disable(struct net_device *dev)
1131 {
1132         struct fe_priv *np = get_nvpriv(dev);
1133
1134         napi_disable(&np->napi);
1135 }
1136
1137 #define MII_READ        (-1)
1138 /* mii_rw: read/write a register on the PHY.
1139  *
1140  * Caller must guarantee serialization
1141  */
1142 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1143 {
1144         u8 __iomem *base = get_hwbase(dev);
1145         u32 reg;
1146         int retval;
1147
1148         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1149
1150         reg = readl(base + NvRegMIIControl);
1151         if (reg & NVREG_MIICTL_INUSE) {
1152                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1153                 udelay(NV_MIIBUSY_DELAY);
1154         }
1155
1156         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1157         if (value != MII_READ) {
1158                 writel(value, base + NvRegMIIData);
1159                 reg |= NVREG_MIICTL_WRITE;
1160         }
1161         writel(reg, base + NvRegMIIControl);
1162
1163         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1164                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1165                 retval = -1;
1166         } else if (value != MII_READ) {
1167                 /* it was a write operation - fewer failures are detectable */
1168                 retval = 0;
1169         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1170                 retval = -1;
1171         } else {
1172                 retval = readl(base + NvRegMIIData);
1173         }
1174
1175         return retval;
1176 }
1177
1178 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1179 {
1180         struct fe_priv *np = netdev_priv(dev);
1181         u32 miicontrol;
1182         unsigned int tries = 0;
1183
1184         miicontrol = BMCR_RESET | bmcr_setup;
1185         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1186                 return -1;
1187
1188         /* wait for 500ms */
1189         msleep(500);
1190
1191         /* must wait till reset is deasserted */
1192         while (miicontrol & BMCR_RESET) {
1193                 usleep_range(10000, 20000);
1194                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1195                 /* FIXME: 100 tries seem excessive */
1196                 if (tries++ > 100)
1197                         return -1;
1198         }
1199         return 0;
1200 }
1201
1202 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1203 {
1204         static const struct {
1205                 int reg;
1206                 int init;
1207         } ri[] = {
1208                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1209                 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1210                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1211                 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1212                 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1213                 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1214                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1215         };
1216         int i;
1217
1218         for (i = 0; i < ARRAY_SIZE(ri); i++) {
1219                 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1220                         return PHY_ERROR;
1221         }
1222
1223         return 0;
1224 }
1225
1226 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1227 {
1228         u32 reg;
1229         u8 __iomem *base = get_hwbase(dev);
1230         u32 powerstate = readl(base + NvRegPowerState2);
1231
1232         /* need to perform hw phy reset */
1233         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1234         writel(powerstate, base + NvRegPowerState2);
1235         msleep(25);
1236
1237         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1238         writel(powerstate, base + NvRegPowerState2);
1239         msleep(25);
1240
1241         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1242         reg |= PHY_REALTEK_INIT9;
1243         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1244                 return PHY_ERROR;
1245         if (mii_rw(dev, np->phyaddr,
1246                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1247                 return PHY_ERROR;
1248         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1249         if (!(reg & PHY_REALTEK_INIT11)) {
1250                 reg |= PHY_REALTEK_INIT11;
1251                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1252                         return PHY_ERROR;
1253         }
1254         if (mii_rw(dev, np->phyaddr,
1255                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1256                 return PHY_ERROR;
1257
1258         return 0;
1259 }
1260
1261 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1262 {
1263         u32 phy_reserved;
1264
1265         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1266                 phy_reserved = mii_rw(dev, np->phyaddr,
1267                                       PHY_REALTEK_INIT_REG6, MII_READ);
1268                 phy_reserved |= PHY_REALTEK_INIT7;
1269                 if (mii_rw(dev, np->phyaddr,
1270                            PHY_REALTEK_INIT_REG6, phy_reserved))
1271                         return PHY_ERROR;
1272         }
1273
1274         return 0;
1275 }
1276
1277 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1278 {
1279         u32 phy_reserved;
1280
1281         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1282                 if (mii_rw(dev, np->phyaddr,
1283                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1284                         return PHY_ERROR;
1285                 phy_reserved = mii_rw(dev, np->phyaddr,
1286                                       PHY_REALTEK_INIT_REG2, MII_READ);
1287                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1288                 phy_reserved |= PHY_REALTEK_INIT3;
1289                 if (mii_rw(dev, np->phyaddr,
1290                            PHY_REALTEK_INIT_REG2, phy_reserved))
1291                         return PHY_ERROR;
1292                 if (mii_rw(dev, np->phyaddr,
1293                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1294                         return PHY_ERROR;
1295         }
1296
1297         return 0;
1298 }
1299
1300 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1301                        u32 phyinterface)
1302 {
1303         u32 phy_reserved;
1304
1305         if (phyinterface & PHY_RGMII) {
1306                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1307                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1308                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1309                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1310                         return PHY_ERROR;
1311                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1312                 phy_reserved |= PHY_CICADA_INIT5;
1313                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1314                         return PHY_ERROR;
1315         }
1316         phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1317         phy_reserved |= PHY_CICADA_INIT6;
1318         if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1319                 return PHY_ERROR;
1320
1321         return 0;
1322 }
1323
1324 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1325 {
1326         u32 phy_reserved;
1327
1328         if (mii_rw(dev, np->phyaddr,
1329                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1330                 return PHY_ERROR;
1331         if (mii_rw(dev, np->phyaddr,
1332                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1333                 return PHY_ERROR;
1334         phy_reserved = mii_rw(dev, np->phyaddr,
1335                               PHY_VITESSE_INIT_REG4, MII_READ);
1336         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1337                 return PHY_ERROR;
1338         phy_reserved = mii_rw(dev, np->phyaddr,
1339                               PHY_VITESSE_INIT_REG3, MII_READ);
1340         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1341         phy_reserved |= PHY_VITESSE_INIT3;
1342         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1343                 return PHY_ERROR;
1344         if (mii_rw(dev, np->phyaddr,
1345                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1346                 return PHY_ERROR;
1347         if (mii_rw(dev, np->phyaddr,
1348                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1349                 return PHY_ERROR;
1350         phy_reserved = mii_rw(dev, np->phyaddr,
1351                               PHY_VITESSE_INIT_REG4, MII_READ);
1352         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1353         phy_reserved |= PHY_VITESSE_INIT3;
1354         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1355                 return PHY_ERROR;
1356         phy_reserved = mii_rw(dev, np->phyaddr,
1357                               PHY_VITESSE_INIT_REG3, MII_READ);
1358         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1359                 return PHY_ERROR;
1360         if (mii_rw(dev, np->phyaddr,
1361                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1362                 return PHY_ERROR;
1363         if (mii_rw(dev, np->phyaddr,
1364                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1365                 return PHY_ERROR;
1366         phy_reserved = mii_rw(dev, np->phyaddr,
1367                               PHY_VITESSE_INIT_REG4, MII_READ);
1368         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1369                 return PHY_ERROR;
1370         phy_reserved = mii_rw(dev, np->phyaddr,
1371                               PHY_VITESSE_INIT_REG3, MII_READ);
1372         phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1373         phy_reserved |= PHY_VITESSE_INIT8;
1374         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1375                 return PHY_ERROR;
1376         if (mii_rw(dev, np->phyaddr,
1377                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1378                 return PHY_ERROR;
1379         if (mii_rw(dev, np->phyaddr,
1380                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1381                 return PHY_ERROR;
1382
1383         return 0;
1384 }
1385
1386 static int phy_init(struct net_device *dev)
1387 {
1388         struct fe_priv *np = get_nvpriv(dev);
1389         u8 __iomem *base = get_hwbase(dev);
1390         u32 phyinterface;
1391         u32 mii_status, mii_control, mii_control_1000, reg;
1392
1393         /* phy errata for E3016 phy */
1394         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1395                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1396                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1397                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1398                         netdev_info(dev, "%s: phy write to errata reg failed\n",
1399                                     pci_name(np->pci_dev));
1400                         return PHY_ERROR;
1401                 }
1402         }
1403         if (np->phy_oui == PHY_OUI_REALTEK) {
1404                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1405                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1406                         if (init_realtek_8211b(dev, np)) {
1407                                 netdev_info(dev, "%s: phy init failed\n",
1408                                             pci_name(np->pci_dev));
1409                                 return PHY_ERROR;
1410                         }
1411                 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1412                            np->phy_rev == PHY_REV_REALTEK_8211C) {
1413                         if (init_realtek_8211c(dev, np)) {
1414                                 netdev_info(dev, "%s: phy init failed\n",
1415                                             pci_name(np->pci_dev));
1416                                 return PHY_ERROR;
1417                         }
1418                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1419                         if (init_realtek_8201(dev, np)) {
1420                                 netdev_info(dev, "%s: phy init failed\n",
1421                                             pci_name(np->pci_dev));
1422                                 return PHY_ERROR;
1423                         }
1424                 }
1425         }
1426
1427         /* set advertise register */
1428         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1429         reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1430                 ADVERTISE_100HALF | ADVERTISE_100FULL |
1431                 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1432         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1433                 netdev_info(dev, "%s: phy write to advertise failed\n",
1434                             pci_name(np->pci_dev));
1435                 return PHY_ERROR;
1436         }
1437
1438         /* get phy interface type */
1439         phyinterface = readl(base + NvRegPhyInterface);
1440
1441         /* see if gigabit phy */
1442         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1443         if (mii_status & PHY_GIGABIT) {
1444                 np->gigabit = PHY_GIGABIT;
1445                 mii_control_1000 = mii_rw(dev, np->phyaddr,
1446                                           MII_CTRL1000, MII_READ);
1447                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1448                 if (phyinterface & PHY_RGMII)
1449                         mii_control_1000 |= ADVERTISE_1000FULL;
1450                 else
1451                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1452
1453                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1454                         netdev_info(dev, "%s: phy init failed\n",
1455                                     pci_name(np->pci_dev));
1456                         return PHY_ERROR;
1457                 }
1458         } else
1459                 np->gigabit = 0;
1460
1461         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1462         mii_control |= BMCR_ANENABLE;
1463
1464         if (np->phy_oui == PHY_OUI_REALTEK &&
1465             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1466             np->phy_rev == PHY_REV_REALTEK_8211C) {
1467                 /* start autoneg since we already performed hw reset above */
1468                 mii_control |= BMCR_ANRESTART;
1469                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1470                         netdev_info(dev, "%s: phy init failed\n",
1471                                     pci_name(np->pci_dev));
1472                         return PHY_ERROR;
1473                 }
1474         } else {
1475                 /* reset the phy
1476                  * (certain phys need bmcr to be setup with reset)
1477                  */
1478                 if (phy_reset(dev, mii_control)) {
1479                         netdev_info(dev, "%s: phy reset failed\n",
1480                                     pci_name(np->pci_dev));
1481                         return PHY_ERROR;
1482                 }
1483         }
1484
1485         /* phy vendor specific configuration */
1486         if ((np->phy_oui == PHY_OUI_CICADA)) {
1487                 if (init_cicada(dev, np, phyinterface)) {
1488                         netdev_info(dev, "%s: phy init failed\n",
1489                                     pci_name(np->pci_dev));
1490                         return PHY_ERROR;
1491                 }
1492         } else if (np->phy_oui == PHY_OUI_VITESSE) {
1493                 if (init_vitesse(dev, np)) {
1494                         netdev_info(dev, "%s: phy init failed\n",
1495                                     pci_name(np->pci_dev));
1496                         return PHY_ERROR;
1497                 }
1498         } else if (np->phy_oui == PHY_OUI_REALTEK) {
1499                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1500                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1501                         /* reset could have cleared these out, set them back */
1502                         if (init_realtek_8211b(dev, np)) {
1503                                 netdev_info(dev, "%s: phy init failed\n",
1504                                             pci_name(np->pci_dev));
1505                                 return PHY_ERROR;
1506                         }
1507                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1508                         if (init_realtek_8201(dev, np) ||
1509                             init_realtek_8201_cross(dev, np)) {
1510                                 netdev_info(dev, "%s: phy init failed\n",
1511                                             pci_name(np->pci_dev));
1512                                 return PHY_ERROR;
1513                         }
1514                 }
1515         }
1516
1517         /* some phys clear out pause advertisement on reset, set it back */
1518         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1519
1520         /* restart auto negotiation, power down phy */
1521         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1522         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1523         if (phy_power_down)
1524                 mii_control |= BMCR_PDOWN;
1525         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1526                 return PHY_ERROR;
1527
1528         return 0;
1529 }
1530
1531 static void nv_start_rx(struct net_device *dev)
1532 {
1533         struct fe_priv *np = netdev_priv(dev);
1534         u8 __iomem *base = get_hwbase(dev);
1535         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1536
1537         /* Already running? Stop it. */
1538         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1539                 rx_ctrl &= ~NVREG_RCVCTL_START;
1540                 writel(rx_ctrl, base + NvRegReceiverControl);
1541                 pci_push(base);
1542         }
1543         writel(np->linkspeed, base + NvRegLinkSpeed);
1544         pci_push(base);
1545         rx_ctrl |= NVREG_RCVCTL_START;
1546         if (np->mac_in_use)
1547                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1548         writel(rx_ctrl, base + NvRegReceiverControl);
1549         pci_push(base);
1550 }
1551
1552 static void nv_stop_rx(struct net_device *dev)
1553 {
1554         struct fe_priv *np = netdev_priv(dev);
1555         u8 __iomem *base = get_hwbase(dev);
1556         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1557
1558         if (!np->mac_in_use)
1559                 rx_ctrl &= ~NVREG_RCVCTL_START;
1560         else
1561                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1562         writel(rx_ctrl, base + NvRegReceiverControl);
1563         if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1564                       NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1565                 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1566                             __func__);
1567
1568         udelay(NV_RXSTOP_DELAY2);
1569         if (!np->mac_in_use)
1570                 writel(0, base + NvRegLinkSpeed);
1571 }
1572
1573 static void nv_start_tx(struct net_device *dev)
1574 {
1575         struct fe_priv *np = netdev_priv(dev);
1576         u8 __iomem *base = get_hwbase(dev);
1577         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1578
1579         tx_ctrl |= NVREG_XMITCTL_START;
1580         if (np->mac_in_use)
1581                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1582         writel(tx_ctrl, base + NvRegTransmitterControl);
1583         pci_push(base);
1584 }
1585
1586 static void nv_stop_tx(struct net_device *dev)
1587 {
1588         struct fe_priv *np = netdev_priv(dev);
1589         u8 __iomem *base = get_hwbase(dev);
1590         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1591
1592         if (!np->mac_in_use)
1593                 tx_ctrl &= ~NVREG_XMITCTL_START;
1594         else
1595                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1596         writel(tx_ctrl, base + NvRegTransmitterControl);
1597         if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1598                       NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1599                 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1600                             __func__);
1601
1602         udelay(NV_TXSTOP_DELAY2);
1603         if (!np->mac_in_use)
1604                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1605                        base + NvRegTransmitPoll);
1606 }
1607
1608 static void nv_start_rxtx(struct net_device *dev)
1609 {
1610         nv_start_rx(dev);
1611         nv_start_tx(dev);
1612 }
1613
1614 static void nv_stop_rxtx(struct net_device *dev)
1615 {
1616         nv_stop_rx(dev);
1617         nv_stop_tx(dev);
1618 }
1619
1620 static void nv_txrx_reset(struct net_device *dev)
1621 {
1622         struct fe_priv *np = netdev_priv(dev);
1623         u8 __iomem *base = get_hwbase(dev);
1624
1625         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1626         pci_push(base);
1627         udelay(NV_TXRX_RESET_DELAY);
1628         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1629         pci_push(base);
1630 }
1631
1632 static void nv_mac_reset(struct net_device *dev)
1633 {
1634         struct fe_priv *np = netdev_priv(dev);
1635         u8 __iomem *base = get_hwbase(dev);
1636         u32 temp1, temp2, temp3;
1637
1638         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1639         pci_push(base);
1640
1641         /* save registers since they will be cleared on reset */
1642         temp1 = readl(base + NvRegMacAddrA);
1643         temp2 = readl(base + NvRegMacAddrB);
1644         temp3 = readl(base + NvRegTransmitPoll);
1645
1646         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1647         pci_push(base);
1648         udelay(NV_MAC_RESET_DELAY);
1649         writel(0, base + NvRegMacReset);
1650         pci_push(base);
1651         udelay(NV_MAC_RESET_DELAY);
1652
1653         /* restore saved registers */
1654         writel(temp1, base + NvRegMacAddrA);
1655         writel(temp2, base + NvRegMacAddrB);
1656         writel(temp3, base + NvRegTransmitPoll);
1657
1658         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1659         pci_push(base);
1660 }
1661
1662 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1663 static void nv_update_stats(struct net_device *dev)
1664 {
1665         struct fe_priv *np = netdev_priv(dev);
1666         u8 __iomem *base = get_hwbase(dev);
1667
1668         /* If it happens that this is run in top-half context, then
1669          * replace the spin_lock of hwstats_lock with
1670          * spin_lock_irqsave() in calling functions. */
1671         WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1672         assert_spin_locked(&np->hwstats_lock);
1673
1674         /* query hardware */
1675         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1676         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1677         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1678         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1679         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1680         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1681         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1682         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1683         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1684         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1685         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1686         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1687         np->estats.rx_runt += readl(base + NvRegRxRunt);
1688         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1689         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1690         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1691         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1692         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1693         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1694         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1695         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1696         np->estats.rx_packets =
1697                 np->estats.rx_unicast +
1698                 np->estats.rx_multicast +
1699                 np->estats.rx_broadcast;
1700         np->estats.rx_errors_total =
1701                 np->estats.rx_crc_errors +
1702                 np->estats.rx_over_errors +
1703                 np->estats.rx_frame_error +
1704                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1705                 np->estats.rx_late_collision +
1706                 np->estats.rx_runt +
1707                 np->estats.rx_frame_too_long;
1708         np->estats.tx_errors_total =
1709                 np->estats.tx_late_collision +
1710                 np->estats.tx_fifo_errors +
1711                 np->estats.tx_carrier_errors +
1712                 np->estats.tx_excess_deferral +
1713                 np->estats.tx_retry_error;
1714
1715         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1716                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1717                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1718                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1719                 np->estats.tx_pause += readl(base + NvRegTxPause);
1720                 np->estats.rx_pause += readl(base + NvRegRxPause);
1721                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1722                 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1723         }
1724
1725         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1726                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1727                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1728                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1729         }
1730 }
1731
1732 /*
1733  * nv_get_stats64: dev->ndo_get_stats64 function
1734  * Get latest stats value from the nic.
1735  * Called with read_lock(&dev_base_lock) held for read -
1736  * only synchronized against unregister_netdevice.
1737  */
1738 static struct rtnl_link_stats64*
1739 nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1740         __acquires(&netdev_priv(dev)->hwstats_lock)
1741         __releases(&netdev_priv(dev)->hwstats_lock)
1742 {
1743         struct fe_priv *np = netdev_priv(dev);
1744         unsigned int syncp_start;
1745
1746         /*
1747          * Note: because HW stats are not always available and for
1748          * consistency reasons, the following ifconfig stats are
1749          * managed by software: rx_bytes, tx_bytes, rx_packets and
1750          * tx_packets. The related hardware stats reported by ethtool
1751          * should be equivalent to these ifconfig stats, with 4
1752          * additional bytes per packet (Ethernet FCS CRC), except for
1753          * tx_packets when TSO kicks in.
1754          */
1755
1756         /* software stats */
1757         do {
1758                 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_rx_syncp);
1759                 storage->rx_packets       = np->stat_rx_packets;
1760                 storage->rx_bytes         = np->stat_rx_bytes;
1761                 storage->rx_dropped       = np->stat_rx_dropped;
1762                 storage->rx_missed_errors = np->stat_rx_missed_errors;
1763         } while (u64_stats_fetch_retry_bh(&np->swstats_rx_syncp, syncp_start));
1764
1765         do {
1766                 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_tx_syncp);
1767                 storage->tx_packets = np->stat_tx_packets;
1768                 storage->tx_bytes   = np->stat_tx_bytes;
1769                 storage->tx_dropped = np->stat_tx_dropped;
1770         } while (u64_stats_fetch_retry_bh(&np->swstats_tx_syncp, syncp_start));
1771
1772         /* If the nic supports hw counters then retrieve latest values */
1773         if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1774                 spin_lock_bh(&np->hwstats_lock);
1775
1776                 nv_update_stats(dev);
1777
1778                 /* generic stats */
1779                 storage->rx_errors = np->estats.rx_errors_total;
1780                 storage->tx_errors = np->estats.tx_errors_total;
1781
1782                 /* meaningful only when NIC supports stats v3 */
1783                 storage->multicast = np->estats.rx_multicast;
1784
1785                 /* detailed rx_errors */
1786                 storage->rx_length_errors = np->estats.rx_length_error;
1787                 storage->rx_over_errors   = np->estats.rx_over_errors;
1788                 storage->rx_crc_errors    = np->estats.rx_crc_errors;
1789                 storage->rx_frame_errors  = np->estats.rx_frame_align_error;
1790                 storage->rx_fifo_errors   = np->estats.rx_drop_frame;
1791
1792                 /* detailed tx_errors */
1793                 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1794                 storage->tx_fifo_errors    = np->estats.tx_fifo_errors;
1795
1796                 spin_unlock_bh(&np->hwstats_lock);
1797         }
1798
1799         return storage;
1800 }
1801
1802 /*
1803  * nv_alloc_rx: fill rx ring entries.
1804  * Return 1 if the allocations for the skbs failed and the
1805  * rx engine is without Available descriptors
1806  */
1807 static int nv_alloc_rx(struct net_device *dev)
1808 {
1809         struct fe_priv *np = netdev_priv(dev);
1810         struct ring_desc *less_rx;
1811
1812         less_rx = np->get_rx.orig;
1813         if (less_rx-- == np->first_rx.orig)
1814                 less_rx = np->last_rx.orig;
1815
1816         while (np->put_rx.orig != less_rx) {
1817                 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1818                 if (skb) {
1819                         np->put_rx_ctx->skb = skb;
1820                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1821                                                              skb->data,
1822                                                              skb_tailroom(skb),
1823                                                              PCI_DMA_FROMDEVICE);
1824                         if (pci_dma_mapping_error(np->pci_dev,
1825                                                   np->put_rx_ctx->dma)) {
1826                                 kfree_skb(skb);
1827                                 goto packet_dropped;
1828                         }
1829                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1830                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1831                         wmb();
1832                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1833                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1834                                 np->put_rx.orig = np->first_rx.orig;
1835                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1836                                 np->put_rx_ctx = np->first_rx_ctx;
1837                 } else {
1838 packet_dropped:
1839                         u64_stats_update_begin(&np->swstats_rx_syncp);
1840                         np->stat_rx_dropped++;
1841                         u64_stats_update_end(&np->swstats_rx_syncp);
1842                         return 1;
1843                 }
1844         }
1845         return 0;
1846 }
1847
1848 static int nv_alloc_rx_optimized(struct net_device *dev)
1849 {
1850         struct fe_priv *np = netdev_priv(dev);
1851         struct ring_desc_ex *less_rx;
1852
1853         less_rx = np->get_rx.ex;
1854         if (less_rx-- == np->first_rx.ex)
1855                 less_rx = np->last_rx.ex;
1856
1857         while (np->put_rx.ex != less_rx) {
1858                 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1859                 if (skb) {
1860                         np->put_rx_ctx->skb = skb;
1861                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1862                                                              skb->data,
1863                                                              skb_tailroom(skb),
1864                                                              PCI_DMA_FROMDEVICE);
1865                         if (pci_dma_mapping_error(np->pci_dev,
1866                                                   np->put_rx_ctx->dma)) {
1867                                 kfree_skb(skb);
1868                                 goto packet_dropped;
1869                         }
1870                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1871                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1872                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1873                         wmb();
1874                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1875                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1876                                 np->put_rx.ex = np->first_rx.ex;
1877                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1878                                 np->put_rx_ctx = np->first_rx_ctx;
1879                 } else {
1880 packet_dropped:
1881                         u64_stats_update_begin(&np->swstats_rx_syncp);
1882                         np->stat_rx_dropped++;
1883                         u64_stats_update_end(&np->swstats_rx_syncp);
1884                         return 1;
1885                 }
1886         }
1887         return 0;
1888 }
1889
1890 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1891 static void nv_do_rx_refill(unsigned long data)
1892 {
1893         struct net_device *dev = (struct net_device *) data;
1894         struct fe_priv *np = netdev_priv(dev);
1895
1896         /* Just reschedule NAPI rx processing */
1897         napi_schedule(&np->napi);
1898 }
1899
1900 static void nv_init_rx(struct net_device *dev)
1901 {
1902         struct fe_priv *np = netdev_priv(dev);
1903         int i;
1904
1905         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1906
1907         if (!nv_optimized(np))
1908                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1909         else
1910                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1911         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1912         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1913
1914         for (i = 0; i < np->rx_ring_size; i++) {
1915                 if (!nv_optimized(np)) {
1916                         np->rx_ring.orig[i].flaglen = 0;
1917                         np->rx_ring.orig[i].buf = 0;
1918                 } else {
1919                         np->rx_ring.ex[i].flaglen = 0;
1920                         np->rx_ring.ex[i].txvlan = 0;
1921                         np->rx_ring.ex[i].bufhigh = 0;
1922                         np->rx_ring.ex[i].buflow = 0;
1923                 }
1924                 np->rx_skb[i].skb = NULL;
1925                 np->rx_skb[i].dma = 0;
1926         }
1927 }
1928
1929 static void nv_init_tx(struct net_device *dev)
1930 {
1931         struct fe_priv *np = netdev_priv(dev);
1932         int i;
1933
1934         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1935
1936         if (!nv_optimized(np))
1937                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1938         else
1939                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1940         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1941         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1942         netdev_reset_queue(np->dev);
1943         np->tx_pkts_in_progress = 0;
1944         np->tx_change_owner = NULL;
1945         np->tx_end_flip = NULL;
1946         np->tx_stop = 0;
1947
1948         for (i = 0; i < np->tx_ring_size; i++) {
1949                 if (!nv_optimized(np)) {
1950                         np->tx_ring.orig[i].flaglen = 0;
1951                         np->tx_ring.orig[i].buf = 0;
1952                 } else {
1953                         np->tx_ring.ex[i].flaglen = 0;
1954                         np->tx_ring.ex[i].txvlan = 0;
1955                         np->tx_ring.ex[i].bufhigh = 0;
1956                         np->tx_ring.ex[i].buflow = 0;
1957                 }
1958                 np->tx_skb[i].skb = NULL;
1959                 np->tx_skb[i].dma = 0;
1960                 np->tx_skb[i].dma_len = 0;
1961                 np->tx_skb[i].dma_single = 0;
1962                 np->tx_skb[i].first_tx_desc = NULL;
1963                 np->tx_skb[i].next_tx_ctx = NULL;
1964         }
1965 }
1966
1967 static int nv_init_ring(struct net_device *dev)
1968 {
1969         struct fe_priv *np = netdev_priv(dev);
1970
1971         nv_init_tx(dev);
1972         nv_init_rx(dev);
1973
1974         if (!nv_optimized(np))
1975                 return nv_alloc_rx(dev);
1976         else
1977                 return nv_alloc_rx_optimized(dev);
1978 }
1979
1980 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1981 {
1982         if (tx_skb->dma) {
1983                 if (tx_skb->dma_single)
1984                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1985                                          tx_skb->dma_len,
1986                                          PCI_DMA_TODEVICE);
1987                 else
1988                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1989                                        tx_skb->dma_len,
1990                                        PCI_DMA_TODEVICE);
1991                 tx_skb->dma = 0;
1992         }
1993 }
1994
1995 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1996 {
1997         nv_unmap_txskb(np, tx_skb);
1998         if (tx_skb->skb) {
1999                 dev_kfree_skb_any(tx_skb->skb);
2000                 tx_skb->skb = NULL;
2001                 return 1;
2002         }
2003         return 0;
2004 }
2005
2006 static void nv_drain_tx(struct net_device *dev)
2007 {
2008         struct fe_priv *np = netdev_priv(dev);
2009         unsigned int i;
2010
2011         for (i = 0; i < np->tx_ring_size; i++) {
2012                 if (!nv_optimized(np)) {
2013                         np->tx_ring.orig[i].flaglen = 0;
2014                         np->tx_ring.orig[i].buf = 0;
2015                 } else {
2016                         np->tx_ring.ex[i].flaglen = 0;
2017                         np->tx_ring.ex[i].txvlan = 0;
2018                         np->tx_ring.ex[i].bufhigh = 0;
2019                         np->tx_ring.ex[i].buflow = 0;
2020                 }
2021                 if (nv_release_txskb(np, &np->tx_skb[i])) {
2022                         u64_stats_update_begin(&np->swstats_tx_syncp);
2023                         np->stat_tx_dropped++;
2024                         u64_stats_update_end(&np->swstats_tx_syncp);
2025                 }
2026                 np->tx_skb[i].dma = 0;
2027                 np->tx_skb[i].dma_len = 0;
2028                 np->tx_skb[i].dma_single = 0;
2029                 np->tx_skb[i].first_tx_desc = NULL;
2030                 np->tx_skb[i].next_tx_ctx = NULL;
2031         }
2032         np->tx_pkts_in_progress = 0;
2033         np->tx_change_owner = NULL;
2034         np->tx_end_flip = NULL;
2035 }
2036
2037 static void nv_drain_rx(struct net_device *dev)
2038 {
2039         struct fe_priv *np = netdev_priv(dev);
2040         int i;
2041
2042         for (i = 0; i < np->rx_ring_size; i++) {
2043                 if (!nv_optimized(np)) {
2044                         np->rx_ring.orig[i].flaglen = 0;
2045                         np->rx_ring.orig[i].buf = 0;
2046                 } else {
2047                         np->rx_ring.ex[i].flaglen = 0;
2048                         np->rx_ring.ex[i].txvlan = 0;
2049                         np->rx_ring.ex[i].bufhigh = 0;
2050                         np->rx_ring.ex[i].buflow = 0;
2051                 }
2052                 wmb();
2053                 if (np->rx_skb[i].skb) {
2054                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2055                                          (skb_end_pointer(np->rx_skb[i].skb) -
2056                                           np->rx_skb[i].skb->data),
2057                                          PCI_DMA_FROMDEVICE);
2058                         dev_kfree_skb(np->rx_skb[i].skb);
2059                         np->rx_skb[i].skb = NULL;
2060                 }
2061         }
2062 }
2063
2064 static void nv_drain_rxtx(struct net_device *dev)
2065 {
2066         nv_drain_tx(dev);
2067         nv_drain_rx(dev);
2068 }
2069
2070 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2071 {
2072         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2073 }
2074
2075 static void nv_legacybackoff_reseed(struct net_device *dev)
2076 {
2077         u8 __iomem *base = get_hwbase(dev);
2078         u32 reg;
2079         u32 low;
2080         int tx_status = 0;
2081
2082         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2083         get_random_bytes(&low, sizeof(low));
2084         reg |= low & NVREG_SLOTTIME_MASK;
2085
2086         /* Need to stop tx before change takes effect.
2087          * Caller has already gained np->lock.
2088          */
2089         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2090         if (tx_status)
2091                 nv_stop_tx(dev);
2092         nv_stop_rx(dev);
2093         writel(reg, base + NvRegSlotTime);
2094         if (tx_status)
2095                 nv_start_tx(dev);
2096         nv_start_rx(dev);
2097 }
2098
2099 /* Gear Backoff Seeds */
2100 #define BACKOFF_SEEDSET_ROWS    8
2101 #define BACKOFF_SEEDSET_LFSRS   15
2102
2103 /* Known Good seed sets */
2104 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2105         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2106         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2107         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2108         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2109         {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2110         {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2111         {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2112         {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2113
2114 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2115         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2116         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2117         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2118         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2119         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2120         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2121         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2122         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2123
2124 static void nv_gear_backoff_reseed(struct net_device *dev)
2125 {
2126         u8 __iomem *base = get_hwbase(dev);
2127         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2128         u32 temp, seedset, combinedSeed;
2129         int i;
2130
2131         /* Setup seed for free running LFSR */
2132         /* We are going to read the time stamp counter 3 times
2133            and swizzle bits around to increase randomness */
2134         get_random_bytes(&miniseed1, sizeof(miniseed1));
2135         miniseed1 &= 0x0fff;
2136         if (miniseed1 == 0)
2137                 miniseed1 = 0xabc;
2138
2139         get_random_bytes(&miniseed2, sizeof(miniseed2));
2140         miniseed2 &= 0x0fff;
2141         if (miniseed2 == 0)
2142                 miniseed2 = 0xabc;
2143         miniseed2_reversed =
2144                 ((miniseed2 & 0xF00) >> 8) |
2145                  (miniseed2 & 0x0F0) |
2146                  ((miniseed2 & 0x00F) << 8);
2147
2148         get_random_bytes(&miniseed3, sizeof(miniseed3));
2149         miniseed3 &= 0x0fff;
2150         if (miniseed3 == 0)
2151                 miniseed3 = 0xabc;
2152         miniseed3_reversed =
2153                 ((miniseed3 & 0xF00) >> 8) |
2154                  (miniseed3 & 0x0F0) |
2155                  ((miniseed3 & 0x00F) << 8);
2156
2157         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2158                        (miniseed2 ^ miniseed3_reversed);
2159
2160         /* Seeds can not be zero */
2161         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2162                 combinedSeed |= 0x08;
2163         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2164                 combinedSeed |= 0x8000;
2165
2166         /* No need to disable tx here */
2167         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2168         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2169         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2170         writel(temp, base + NvRegBackOffControl);
2171
2172         /* Setup seeds for all gear LFSRs. */
2173         get_random_bytes(&seedset, sizeof(seedset));
2174         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2175         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2176                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2177                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2178                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2179                 writel(temp, base + NvRegBackOffControl);
2180         }
2181 }
2182
2183 /*
2184  * nv_start_xmit: dev->hard_start_xmit function
2185  * Called with netif_tx_lock held.
2186  */
2187 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2188 {
2189         struct fe_priv *np = netdev_priv(dev);
2190         u32 tx_flags = 0;
2191         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2192         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2193         unsigned int i;
2194         u32 offset = 0;
2195         u32 bcnt;
2196         u32 size = skb_headlen(skb);
2197         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2198         u32 empty_slots;
2199         struct ring_desc *put_tx;
2200         struct ring_desc *start_tx;
2201         struct ring_desc *prev_tx;
2202         struct nv_skb_map *prev_tx_ctx;
2203         struct nv_skb_map *tmp_tx_ctx = NULL, *start_tx_ctx = NULL;
2204         unsigned long flags;
2205
2206         /* add fragments to entries count */
2207         for (i = 0; i < fragments; i++) {
2208                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2209
2210                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2211                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2212         }
2213
2214         spin_lock_irqsave(&np->lock, flags);
2215         empty_slots = nv_get_empty_tx_slots(np);
2216         if (unlikely(empty_slots <= entries)) {
2217                 netif_stop_queue(dev);
2218                 np->tx_stop = 1;
2219                 spin_unlock_irqrestore(&np->lock, flags);
2220                 return NETDEV_TX_BUSY;
2221         }
2222         spin_unlock_irqrestore(&np->lock, flags);
2223
2224         start_tx = put_tx = np->put_tx.orig;
2225
2226         /* setup the header buffer */
2227         do {
2228                 prev_tx = put_tx;
2229                 prev_tx_ctx = np->put_tx_ctx;
2230                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2231                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2232                                                 PCI_DMA_TODEVICE);
2233                 if (pci_dma_mapping_error(np->pci_dev,
2234                                           np->put_tx_ctx->dma)) {
2235                         /* on DMA mapping error - drop the packet */
2236                         kfree_skb(skb);
2237                         u64_stats_update_begin(&np->swstats_tx_syncp);
2238                         np->stat_tx_dropped++;
2239                         u64_stats_update_end(&np->swstats_tx_syncp);
2240                         return NETDEV_TX_OK;
2241                 }
2242                 np->put_tx_ctx->dma_len = bcnt;
2243                 np->put_tx_ctx->dma_single = 1;
2244                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2245                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2246
2247                 tx_flags = np->tx_flags;
2248                 offset += bcnt;
2249                 size -= bcnt;
2250                 if (unlikely(put_tx++ == np->last_tx.orig))
2251                         put_tx = np->first_tx.orig;
2252                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2253                         np->put_tx_ctx = np->first_tx_ctx;
2254         } while (size);
2255
2256         /* setup the fragments */
2257         for (i = 0; i < fragments; i++) {
2258                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2259                 u32 frag_size = skb_frag_size(frag);
2260                 offset = 0;
2261
2262                 do {
2263                         prev_tx = put_tx;
2264                         prev_tx_ctx = np->put_tx_ctx;
2265                         if (!start_tx_ctx)
2266                                 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2267
2268                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2269                         np->put_tx_ctx->dma = skb_frag_dma_map(
2270                                                         &np->pci_dev->dev,
2271                                                         frag, offset,
2272                                                         bcnt,
2273                                                         DMA_TO_DEVICE);
2274                         if (dma_mapping_error(&np->pci_dev->dev, np->put_tx_ctx->dma)) {
2275
2276                                 /* Unwind the mapped fragments */
2277                                 do {
2278                                         nv_unmap_txskb(np, start_tx_ctx);
2279                                         if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2280                                                 tmp_tx_ctx = np->first_tx_ctx;
2281                                 } while (tmp_tx_ctx != np->put_tx_ctx);
2282                                 kfree_skb(skb);
2283                                 np->put_tx_ctx = start_tx_ctx;
2284                                 u64_stats_update_begin(&np->swstats_tx_syncp);
2285                                 np->stat_tx_dropped++;
2286                                 u64_stats_update_end(&np->swstats_tx_syncp);
2287                                 return NETDEV_TX_OK;
2288                         }
2289
2290                         np->put_tx_ctx->dma_len = bcnt;
2291                         np->put_tx_ctx->dma_single = 0;
2292                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2293                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2294
2295                         offset += bcnt;
2296                         frag_size -= bcnt;
2297                         if (unlikely(put_tx++ == np->last_tx.orig))
2298                                 put_tx = np->first_tx.orig;
2299                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2300                                 np->put_tx_ctx = np->first_tx_ctx;
2301                 } while (frag_size);
2302         }
2303
2304         /* set last fragment flag  */
2305         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2306
2307         /* save skb in this slot's context area */
2308         prev_tx_ctx->skb = skb;
2309
2310         if (skb_is_gso(skb))
2311                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2312         else
2313                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2314                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2315
2316         spin_lock_irqsave(&np->lock, flags);
2317
2318         /* set tx flags */
2319         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2320
2321         netdev_sent_queue(np->dev, skb->len);
2322
2323         skb_tx_timestamp(skb);
2324
2325         np->put_tx.orig = put_tx;
2326
2327         spin_unlock_irqrestore(&np->lock, flags);
2328
2329         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2330         return NETDEV_TX_OK;
2331 }
2332
2333 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2334                                            struct net_device *dev)
2335 {
2336         struct fe_priv *np = netdev_priv(dev);
2337         u32 tx_flags = 0;
2338         u32 tx_flags_extra;
2339         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2340         unsigned int i;
2341         u32 offset = 0;
2342         u32 bcnt;
2343         u32 size = skb_headlen(skb);
2344         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2345         u32 empty_slots;
2346         struct ring_desc_ex *put_tx;
2347         struct ring_desc_ex *start_tx;
2348         struct ring_desc_ex *prev_tx;
2349         struct nv_skb_map *prev_tx_ctx;
2350         struct nv_skb_map *start_tx_ctx = NULL;
2351         struct nv_skb_map *tmp_tx_ctx = NULL;
2352         unsigned long flags;
2353
2354         /* add fragments to entries count */
2355         for (i = 0; i < fragments; i++) {
2356                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2357
2358                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2359                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2360         }
2361
2362         spin_lock_irqsave(&np->lock, flags);
2363         empty_slots = nv_get_empty_tx_slots(np);
2364         if (unlikely(empty_slots <= entries)) {
2365                 netif_stop_queue(dev);
2366                 np->tx_stop = 1;
2367                 spin_unlock_irqrestore(&np->lock, flags);
2368                 return NETDEV_TX_BUSY;
2369         }
2370         spin_unlock_irqrestore(&np->lock, flags);
2371
2372         start_tx = put_tx = np->put_tx.ex;
2373         start_tx_ctx = np->put_tx_ctx;
2374
2375         /* setup the header buffer */
2376         do {
2377                 prev_tx = put_tx;
2378                 prev_tx_ctx = np->put_tx_ctx;
2379                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2380                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2381                                                 PCI_DMA_TODEVICE);
2382                 if (pci_dma_mapping_error(np->pci_dev,
2383                                           np->put_tx_ctx->dma)) {
2384                         /* on DMA mapping error - drop the packet */
2385                         kfree_skb(skb);
2386                         u64_stats_update_begin(&np->swstats_tx_syncp);
2387                         np->stat_tx_dropped++;
2388                         u64_stats_update_end(&np->swstats_tx_syncp);
2389                         return NETDEV_TX_OK;
2390                 }
2391                 np->put_tx_ctx->dma_len = bcnt;
2392                 np->put_tx_ctx->dma_single = 1;
2393                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2394                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2395                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2396
2397                 tx_flags = NV_TX2_VALID;
2398                 offset += bcnt;
2399                 size -= bcnt;
2400                 if (unlikely(put_tx++ == np->last_tx.ex))
2401                         put_tx = np->first_tx.ex;
2402                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2403                         np->put_tx_ctx = np->first_tx_ctx;
2404         } while (size);
2405
2406         /* setup the fragments */
2407         for (i = 0; i < fragments; i++) {
2408                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2409                 u32 frag_size = skb_frag_size(frag);
2410                 offset = 0;
2411
2412                 do {
2413                         prev_tx = put_tx;
2414                         prev_tx_ctx = np->put_tx_ctx;
2415                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2416                         if (!start_tx_ctx)
2417                                 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2418                         np->put_tx_ctx->dma = skb_frag_dma_map(
2419                                                         &np->pci_dev->dev,
2420                                                         frag, offset,
2421                                                         bcnt,
2422                                                         DMA_TO_DEVICE);
2423
2424                         if (dma_mapping_error(&np->pci_dev->dev, np->put_tx_ctx->dma)) {
2425
2426                                 /* Unwind the mapped fragments */
2427                                 do {
2428                                         nv_unmap_txskb(np, start_tx_ctx);
2429                                         if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2430                                                 tmp_tx_ctx = np->first_tx_ctx;
2431                                 } while (tmp_tx_ctx != np->put_tx_ctx);
2432                                 kfree_skb(skb);
2433                                 np->put_tx_ctx = start_tx_ctx;
2434                                 u64_stats_update_begin(&np->swstats_tx_syncp);
2435                                 np->stat_tx_dropped++;
2436                                 u64_stats_update_end(&np->swstats_tx_syncp);
2437                                 return NETDEV_TX_OK;
2438                         }
2439                         np->put_tx_ctx->dma_len = bcnt;
2440                         np->put_tx_ctx->dma_single = 0;
2441                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2442                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2443                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2444
2445                         offset += bcnt;
2446                         frag_size -= bcnt;
2447                         if (unlikely(put_tx++ == np->last_tx.ex))
2448                                 put_tx = np->first_tx.ex;
2449                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2450                                 np->put_tx_ctx = np->first_tx_ctx;
2451                 } while (frag_size);
2452         }
2453
2454         /* set last fragment flag  */
2455         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2456
2457         /* save skb in this slot's context area */
2458         prev_tx_ctx->skb = skb;
2459
2460         if (skb_is_gso(skb))
2461                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2462         else
2463                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2464                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2465
2466         /* vlan tag */
2467         if (vlan_tx_tag_present(skb))
2468                 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2469                                         vlan_tx_tag_get(skb));
2470         else
2471                 start_tx->txvlan = 0;
2472
2473         spin_lock_irqsave(&np->lock, flags);
2474
2475         if (np->tx_limit) {
2476                 /* Limit the number of outstanding tx. Setup all fragments, but
2477                  * do not set the VALID bit on the first descriptor. Save a pointer
2478                  * to that descriptor and also for next skb_map element.
2479                  */
2480
2481                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2482                         if (!np->tx_change_owner)
2483                                 np->tx_change_owner = start_tx_ctx;
2484
2485                         /* remove VALID bit */
2486                         tx_flags &= ~NV_TX2_VALID;
2487                         start_tx_ctx->first_tx_desc = start_tx;
2488                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2489                         np->tx_end_flip = np->put_tx_ctx;
2490                 } else {
2491                         np->tx_pkts_in_progress++;
2492                 }
2493         }
2494
2495         /* set tx flags */
2496         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2497
2498         netdev_sent_queue(np->dev, skb->len);
2499
2500         skb_tx_timestamp(skb);
2501
2502         np->put_tx.ex = put_tx;
2503
2504         spin_unlock_irqrestore(&np->lock, flags);
2505
2506         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2507         return NETDEV_TX_OK;
2508 }
2509
2510 static inline void nv_tx_flip_ownership(struct net_device *dev)
2511 {
2512         struct fe_priv *np = netdev_priv(dev);
2513
2514         np->tx_pkts_in_progress--;
2515         if (np->tx_change_owner) {
2516                 np->tx_change_owner->first_tx_desc->flaglen |=
2517                         cpu_to_le32(NV_TX2_VALID);
2518                 np->tx_pkts_in_progress++;
2519
2520                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2521                 if (np->tx_change_owner == np->tx_end_flip)
2522                         np->tx_change_owner = NULL;
2523
2524                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2525         }
2526 }
2527
2528 /*
2529  * nv_tx_done: check for completed packets, release the skbs.
2530  *
2531  * Caller must own np->lock.
2532  */
2533 static int nv_tx_done(struct net_device *dev, int limit)
2534 {
2535         struct fe_priv *np = netdev_priv(dev);
2536         u32 flags;
2537         int tx_work = 0;
2538         struct ring_desc *orig_get_tx = np->get_tx.orig;
2539         unsigned int bytes_compl = 0;
2540
2541         while ((np->get_tx.orig != np->put_tx.orig) &&
2542                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2543                (tx_work < limit)) {
2544
2545                 nv_unmap_txskb(np, np->get_tx_ctx);
2546
2547                 if (np->desc_ver == DESC_VER_1) {
2548                         if (flags & NV_TX_LASTPACKET) {
2549                                 if (flags & NV_TX_ERROR) {
2550                                         if ((flags & NV_TX_RETRYERROR)
2551                                             && !(flags & NV_TX_RETRYCOUNT_MASK))
2552                                                 nv_legacybackoff_reseed(dev);
2553                                 } else {
2554                                         u64_stats_update_begin(&np->swstats_tx_syncp);
2555                                         np->stat_tx_packets++;
2556                                         np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2557                                         u64_stats_update_end(&np->swstats_tx_syncp);
2558                                 }
2559                                 bytes_compl += np->get_tx_ctx->skb->len;
2560                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2561                                 np->get_tx_ctx->skb = NULL;
2562                                 tx_work++;
2563                         }
2564                 } else {
2565                         if (flags & NV_TX2_LASTPACKET) {
2566                                 if (flags & NV_TX2_ERROR) {
2567                                         if ((flags & NV_TX2_RETRYERROR)
2568                                             && !(flags & NV_TX2_RETRYCOUNT_MASK))
2569                                                 nv_legacybackoff_reseed(dev);
2570                                 } else {
2571                                         u64_stats_update_begin(&np->swstats_tx_syncp);
2572                                         np->stat_tx_packets++;
2573                                         np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2574                                         u64_stats_update_end(&np->swstats_tx_syncp);
2575                                 }
2576                                 bytes_compl += np->get_tx_ctx->skb->len;
2577                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2578                                 np->get_tx_ctx->skb = NULL;
2579                                 tx_work++;
2580                         }
2581                 }
2582                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2583                         np->get_tx.orig = np->first_tx.orig;
2584                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2585                         np->get_tx_ctx = np->first_tx_ctx;
2586         }
2587
2588         netdev_completed_queue(np->dev, tx_work, bytes_compl);
2589
2590         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2591                 np->tx_stop = 0;
2592                 netif_wake_queue(dev);
2593         }
2594         return tx_work;
2595 }
2596
2597 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2598 {
2599         struct fe_priv *np = netdev_priv(dev);
2600         u32 flags;
2601         int tx_work = 0;
2602         struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2603         unsigned long bytes_cleaned = 0;
2604
2605         while ((np->get_tx.ex != np->put_tx.ex) &&
2606                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2607                (tx_work < limit)) {
2608
2609                 nv_unmap_txskb(np, np->get_tx_ctx);
2610
2611                 if (flags & NV_TX2_LASTPACKET) {
2612                         if (flags & NV_TX2_ERROR) {
2613                                 if ((flags & NV_TX2_RETRYERROR)
2614                                     && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2615                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2616                                                 nv_gear_backoff_reseed(dev);
2617                                         else
2618                                                 nv_legacybackoff_reseed(dev);
2619                                 }
2620                         } else {
2621                                 u64_stats_update_begin(&np->swstats_tx_syncp);
2622                                 np->stat_tx_packets++;
2623                                 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2624                                 u64_stats_update_end(&np->swstats_tx_syncp);
2625                         }
2626
2627                         bytes_cleaned += np->get_tx_ctx->skb->len;
2628                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2629                         np->get_tx_ctx->skb = NULL;
2630                         tx_work++;
2631
2632                         if (np->tx_limit)
2633                                 nv_tx_flip_ownership(dev);
2634                 }
2635
2636                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2637                         np->get_tx.ex = np->first_tx.ex;
2638                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2639                         np->get_tx_ctx = np->first_tx_ctx;
2640         }
2641
2642         netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2643
2644         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2645                 np->tx_stop = 0;
2646                 netif_wake_queue(dev);
2647         }
2648         return tx_work;
2649 }
2650
2651 /*
2652  * nv_tx_timeout: dev->tx_timeout function
2653  * Called with netif_tx_lock held.
2654  */
2655 static void nv_tx_timeout(struct net_device *dev)
2656 {
2657         struct fe_priv *np = netdev_priv(dev);
2658         u8 __iomem *base = get_hwbase(dev);
2659         u32 status;
2660         union ring_type put_tx;
2661         int saved_tx_limit;
2662
2663         if (np->msi_flags & NV_MSI_X_ENABLED)
2664                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2665         else
2666                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2667
2668         netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2669
2670         if (unlikely(debug_tx_timeout)) {
2671                 int i;
2672
2673                 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2674                 netdev_info(dev, "Dumping tx registers\n");
2675                 for (i = 0; i <= np->register_size; i += 32) {
2676                         netdev_info(dev,
2677                                     "%3x: %08x %08x %08x %08x "
2678                                     "%08x %08x %08x %08x\n",
2679                                     i,
2680                                     readl(base + i + 0), readl(base + i + 4),
2681                                     readl(base + i + 8), readl(base + i + 12),
2682                                     readl(base + i + 16), readl(base + i + 20),
2683                                     readl(base + i + 24), readl(base + i + 28));
2684                 }
2685                 netdev_info(dev, "Dumping tx ring\n");
2686                 for (i = 0; i < np->tx_ring_size; i += 4) {
2687                         if (!nv_optimized(np)) {
2688                                 netdev_info(dev,
2689                                             "%03x: %08x %08x // %08x %08x "
2690                                             "// %08x %08x // %08x %08x\n",
2691                                             i,
2692                                             le32_to_cpu(np->tx_ring.orig[i].buf),
2693                                             le32_to_cpu(np->tx_ring.orig[i].flaglen),
2694                                             le32_to_cpu(np->tx_ring.orig[i+1].buf),
2695                                             le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2696                                             le32_to_cpu(np->tx_ring.orig[i+2].buf),
2697                                             le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2698                                             le32_to_cpu(np->tx_ring.orig[i+3].buf),
2699                                             le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2700                         } else {
2701                                 netdev_info(dev,
2702                                             "%03x: %08x %08x %08x "
2703                                             "// %08x %08x %08x "
2704                                             "// %08x %08x %08x "
2705                                             "// %08x %08x %08x\n",
2706                                             i,
2707                                             le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2708                                             le32_to_cpu(np->tx_ring.ex[i].buflow),
2709                                             le32_to_cpu(np->tx_ring.ex[i].flaglen),
2710                                             le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2711                                             le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2712                                             le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2713                                             le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2714                                             le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2715                                             le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2716                                             le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2717                                             le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2718                                             le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2719                         }
2720                 }
2721         }
2722
2723         spin_lock_irq(&np->lock);
2724
2725         /* 1) stop tx engine */
2726         nv_stop_tx(dev);
2727
2728         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2729         saved_tx_limit = np->tx_limit;
2730         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2731         np->tx_stop = 0;  /* prevent waking tx queue */
2732         if (!nv_optimized(np))
2733                 nv_tx_done(dev, np->tx_ring_size);
2734         else
2735                 nv_tx_done_optimized(dev, np->tx_ring_size);
2736
2737         /* save current HW position */
2738         if (np->tx_change_owner)
2739                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2740         else
2741                 put_tx = np->put_tx;
2742
2743         /* 3) clear all tx state */
2744         nv_drain_tx(dev);
2745         nv_init_tx(dev);
2746
2747         /* 4) restore state to current HW position */
2748         np->get_tx = np->put_tx = put_tx;
2749         np->tx_limit = saved_tx_limit;
2750
2751         /* 5) restart tx engine */
2752         nv_start_tx(dev);
2753         netif_wake_queue(dev);
2754         spin_unlock_irq(&np->lock);
2755 }
2756
2757 /*
2758  * Called when the nic notices a mismatch between the actual data len on the
2759  * wire and the len indicated in the 802 header
2760  */
2761 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2762 {
2763         int hdrlen;     /* length of the 802 header */
2764         int protolen;   /* length as stored in the proto field */
2765
2766         /* 1) calculate len according to header */
2767         if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2768                 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2769                 hdrlen = VLAN_HLEN;
2770         } else {
2771                 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2772                 hdrlen = ETH_HLEN;
2773         }
2774         if (protolen > ETH_DATA_LEN)
2775                 return datalen; /* Value in proto field not a len, no checks possible */
2776
2777         protolen += hdrlen;
2778         /* consistency checks: */
2779         if (datalen > ETH_ZLEN) {
2780                 if (datalen >= protolen) {
2781                         /* more data on wire than in 802 header, trim of
2782                          * additional data.
2783                          */
2784                         return protolen;
2785                 } else {
2786                         /* less data on wire than mentioned in header.
2787                          * Discard the packet.
2788                          */
2789                         return -1;
2790                 }
2791         } else {
2792                 /* short packet. Accept only if 802 values are also short */
2793                 if (protolen > ETH_ZLEN) {
2794                         return -1;
2795                 }
2796                 return datalen;
2797         }
2798 }
2799
2800 static int nv_rx_process(struct net_device *dev, int limit)
2801 {
2802         struct fe_priv *np = netdev_priv(dev);
2803         u32 flags;
2804         int rx_work = 0;
2805         struct sk_buff *skb;
2806         int len;
2807
2808         while ((np->get_rx.orig != np->put_rx.orig) &&
2809               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2810                 (rx_work < limit)) {
2811
2812                 /*
2813                  * the packet is for us - immediately tear down the pci mapping.
2814                  * TODO: check if a prefetch of the first cacheline improves
2815                  * the performance.
2816                  */
2817                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2818                                 np->get_rx_ctx->dma_len,
2819                                 PCI_DMA_FROMDEVICE);
2820                 skb = np->get_rx_ctx->skb;
2821                 np->get_rx_ctx->skb = NULL;
2822
2823                 /* look at what we actually got: */
2824                 if (np->desc_ver == DESC_VER_1) {
2825                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2826                                 len = flags & LEN_MASK_V1;
2827                                 if (unlikely(flags & NV_RX_ERROR)) {
2828                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2829                                                 len = nv_getlen(dev, skb->data, len);
2830                                                 if (len < 0) {
2831                                                         dev_kfree_skb(skb);
2832                                                         goto next_pkt;
2833                                                 }
2834                                         }
2835                                         /* framing errors are soft errors */
2836                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2837                                                 if (flags & NV_RX_SUBSTRACT1)
2838                                                         len--;
2839                                         }
2840                                         /* the rest are hard errors */
2841                                         else {
2842                                                 if (flags & NV_RX_MISSEDFRAME) {
2843                                                         u64_stats_update_begin(&np->swstats_rx_syncp);
2844                                                         np->stat_rx_missed_errors++;
2845                                                         u64_stats_update_end(&np->swstats_rx_syncp);
2846                                                 }
2847                                                 dev_kfree_skb(skb);
2848                                                 goto next_pkt;
2849                                         }
2850                                 }
2851                         } else {
2852                                 dev_kfree_skb(skb);
2853                                 goto next_pkt;
2854                         }
2855                 } else {
2856                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2857                                 len = flags & LEN_MASK_V2;
2858                                 if (unlikely(flags & NV_RX2_ERROR)) {
2859                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2860                                                 len = nv_getlen(dev, skb->data, len);
2861                                                 if (len < 0) {
2862                                                         dev_kfree_skb(skb);
2863                                                         goto next_pkt;
2864                                                 }
2865                                         }
2866                                         /* framing errors are soft errors */
2867                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2868                                                 if (flags & NV_RX2_SUBSTRACT1)
2869                                                         len--;
2870                                         }
2871                                         /* the rest are hard errors */
2872                                         else {
2873                                                 dev_kfree_skb(skb);
2874                                                 goto next_pkt;
2875                                         }
2876                                 }
2877                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2878                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2879                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2880                         } else {
2881                                 dev_kfree_skb(skb);
2882                                 goto next_pkt;
2883                         }
2884                 }
2885                 /* got a valid packet - forward it to the network core */
2886                 skb_put(skb, len);
2887                 skb->protocol = eth_type_trans(skb, dev);
2888                 napi_gro_receive(&np->napi, skb);
2889                 u64_stats_update_begin(&np->swstats_rx_syncp);
2890                 np->stat_rx_packets++;
2891                 np->stat_rx_bytes += len;
2892                 u64_stats_update_end(&np->swstats_rx_syncp);
2893 next_pkt:
2894                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2895                         np->get_rx.orig = np->first_rx.orig;
2896                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2897                         np->get_rx_ctx = np->first_rx_ctx;
2898
2899                 rx_work++;
2900         }
2901
2902         return rx_work;
2903 }
2904
2905 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2906 {
2907         struct fe_priv *np = netdev_priv(dev);
2908         u32 flags;
2909         u32 vlanflags = 0;
2910         int rx_work = 0;
2911         struct sk_buff *skb;
2912         int len;
2913
2914         while ((np->get_rx.ex != np->put_rx.ex) &&
2915               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2916               (rx_work < limit)) {
2917
2918                 /*
2919                  * the packet is for us - immediately tear down the pci mapping.
2920                  * TODO: check if a prefetch of the first cacheline improves
2921                  * the performance.
2922                  */
2923                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2924                                 np->get_rx_ctx->dma_len,
2925                                 PCI_DMA_FROMDEVICE);
2926                 skb = np->get_rx_ctx->skb;
2927                 np->get_rx_ctx->skb = NULL;
2928
2929                 /* look at what we actually got: */
2930                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2931                         len = flags & LEN_MASK_V2;
2932                         if (unlikely(flags & NV_RX2_ERROR)) {
2933                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2934                                         len = nv_getlen(dev, skb->data, len);
2935                                         if (len < 0) {
2936                                                 dev_kfree_skb(skb);
2937                                                 goto next_pkt;
2938                                         }
2939                                 }
2940                                 /* framing errors are soft errors */
2941                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2942                                         if (flags & NV_RX2_SUBSTRACT1)
2943                                                 len--;
2944                                 }
2945                                 /* the rest are hard errors */
2946                                 else {
2947                                         dev_kfree_skb(skb);
2948                                         goto next_pkt;
2949                                 }
2950                         }
2951
2952                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2953                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2954                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2955
2956                         /* got a valid packet - forward it to the network core */
2957                         skb_put(skb, len);
2958                         skb->protocol = eth_type_trans(skb, dev);
2959                         prefetch(skb->data);
2960
2961                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2962
2963                         /*
2964                          * There's need to check for NETIF_F_HW_VLAN_CTAG_RX
2965                          * here. Even if vlan rx accel is disabled,
2966                          * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2967                          */
2968                         if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2969                             vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2970                                 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2971
2972                                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
2973                         }
2974                         napi_gro_receive(&np->napi, skb);
2975                         u64_stats_update_begin(&np->swstats_rx_syncp);
2976                         np->stat_rx_packets++;
2977                         np->stat_rx_bytes += len;
2978                         u64_stats_update_end(&np->swstats_rx_syncp);
2979                 } else {
2980                         dev_kfree_skb(skb);
2981                 }
2982 next_pkt:
2983                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2984                         np->get_rx.ex = np->first_rx.ex;
2985                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2986                         np->get_rx_ctx = np->first_rx_ctx;
2987
2988                 rx_work++;
2989         }
2990
2991         return rx_work;
2992 }
2993
2994 static void set_bufsize(struct net_device *dev)
2995 {
2996         struct fe_priv *np = netdev_priv(dev);
2997
2998         if (dev->mtu <= ETH_DATA_LEN)
2999                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
3000         else
3001                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
3002 }
3003
3004 /*
3005  * nv_change_mtu: dev->change_mtu function
3006  * Called with dev_base_lock held for read.
3007  */
3008 static int nv_change_mtu(struct net_device *dev, int new_mtu)
3009 {
3010         struct fe_priv *np = netdev_priv(dev);
3011         int old_mtu;
3012
3013         if (new_mtu < 64 || new_mtu > np->pkt_limit)
3014                 return -EINVAL;
3015
3016         old_mtu = dev->mtu;
3017         dev->mtu = new_mtu;
3018
3019         /* return early if the buffer sizes will not change */
3020         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
3021                 return 0;
3022         if (old_mtu == new_mtu)
3023                 return 0;
3024
3025         /* synchronized against open : rtnl_lock() held by caller */
3026         if (netif_running(dev)) {
3027                 u8 __iomem *base = get_hwbase(dev);
3028                 /*
3029                  * It seems that the nic preloads valid ring entries into an
3030                  * internal buffer. The procedure for flushing everything is
3031                  * guessed, there is probably a simpler approach.
3032                  * Changing the MTU is a rare event, it shouldn't matter.
3033                  */
3034                 nv_disable_irq(dev);
3035                 nv_napi_disable(dev);
3036                 netif_tx_lock_bh(dev);
3037                 netif_addr_lock(dev);
3038                 spin_lock(&np->lock);
3039                 /* stop engines */
3040                 nv_stop_rxtx(dev);
3041                 nv_txrx_reset(dev);
3042                 /* drain rx queue */
3043                 nv_drain_rxtx(dev);
3044                 /* reinit driver view of the rx queue */
3045                 set_bufsize(dev);
3046                 if (nv_init_ring(dev)) {
3047                         if (!np->in_shutdown)
3048                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3049                 }
3050                 /* reinit nic view of the rx queue */
3051                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3052                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3053                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3054                         base + NvRegRingSizes);
3055                 pci_push(base);
3056                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3057                 pci_push(base);
3058
3059                 /* restart rx engine */
3060                 nv_start_rxtx(dev);
3061                 spin_unlock(&np->lock);
3062                 netif_addr_unlock(dev);
3063                 netif_tx_unlock_bh(dev);
3064                 nv_napi_enable(dev);
3065                 nv_enable_irq(dev);
3066         }
3067         return 0;
3068 }
3069
3070 static void nv_copy_mac_to_hw(struct net_device *dev)
3071 {
3072         u8 __iomem *base = get_hwbase(dev);
3073         u32 mac[2];
3074
3075         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3076                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3077         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3078
3079         writel(mac[0], base + NvRegMacAddrA);
3080         writel(mac[1], base + NvRegMacAddrB);
3081 }
3082
3083 /*
3084  * nv_set_mac_address: dev->set_mac_address function
3085  * Called with rtnl_lock() held.
3086  */
3087 static int nv_set_mac_address(struct net_device *dev, void *addr)
3088 {
3089         struct fe_priv *np = netdev_priv(dev);
3090         struct sockaddr *macaddr = (struct sockaddr *)addr;
3091
3092         if (!is_valid_ether_addr(macaddr->sa_data))
3093                 return -EADDRNOTAVAIL;
3094
3095         /* synchronized against open : rtnl_lock() held by caller */
3096         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3097
3098         if (netif_running(dev)) {
3099                 netif_tx_lock_bh(dev);
3100                 netif_addr_lock(dev);
3101                 spin_lock_irq(&np->lock);
3102
3103                 /* stop rx engine */
3104                 nv_stop_rx(dev);
3105
3106                 /* set mac address */
3107                 nv_copy_mac_to_hw(dev);
3108
3109                 /* restart rx engine */
3110                 nv_start_rx(dev);
3111                 spin_unlock_irq(&np->lock);
3112                 netif_addr_unlock(dev);
3113                 netif_tx_unlock_bh(dev);
3114         } else {
3115                 nv_copy_mac_to_hw(dev);
3116         }
3117         return 0;
3118 }
3119
3120 /*
3121  * nv_set_multicast: dev->set_multicast function
3122  * Called with netif_tx_lock held.
3123  */
3124 static void nv_set_multicast(struct net_device *dev)
3125 {
3126         struct fe_priv *np = netdev_priv(dev);
3127         u8 __iomem *base = get_hwbase(dev);
3128         u32 addr[2];
3129         u32 mask[2];
3130         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3131
3132         memset(addr, 0, sizeof(addr));
3133         memset(mask, 0, sizeof(mask));
3134
3135         if (dev->flags & IFF_PROMISC) {
3136                 pff |= NVREG_PFF_PROMISC;
3137         } else {
3138                 pff |= NVREG_PFF_MYADDR;
3139
3140                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3141                         u32 alwaysOff[2];
3142                         u32 alwaysOn[2];
3143
3144                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3145                         if (dev->flags & IFF_ALLMULTI) {
3146                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3147                         } else {
3148                                 struct netdev_hw_addr *ha;
3149
3150                                 netdev_for_each_mc_addr(ha, dev) {
3151                                         unsigned char *hw_addr = ha->addr;
3152                                         u32 a, b;
3153
3154                                         a = le32_to_cpu(*(__le32 *) hw_addr);
3155                                         b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3156                                         alwaysOn[0] &= a;
3157                                         alwaysOff[0] &= ~a;
3158                                         alwaysOn[1] &= b;
3159                                         alwaysOff[1] &= ~b;
3160                                 }
3161                         }
3162                         addr[0] = alwaysOn[0];
3163                         addr[1] = alwaysOn[1];
3164                         mask[0] = alwaysOn[0] | alwaysOff[0];
3165                         mask[1] = alwaysOn[1] | alwaysOff[1];
3166                 } else {
3167                         mask[0] = NVREG_MCASTMASKA_NONE;
3168                         mask[1] = NVREG_MCASTMASKB_NONE;
3169                 }
3170         }
3171         addr[0] |= NVREG_MCASTADDRA_FORCE;
3172         pff |= NVREG_PFF_ALWAYS;
3173         spin_lock_irq(&np->lock);
3174         nv_stop_rx(dev);
3175         writel(addr[0], base + NvRegMulticastAddrA);
3176         writel(addr[1], base + NvRegMulticastAddrB);
3177         writel(mask[0], base + NvRegMulticastMaskA);
3178         writel(mask[1], base + NvRegMulticastMaskB);
3179         writel(pff, base + NvRegPacketFilterFlags);
3180         nv_start_rx(dev);
3181         spin_unlock_irq(&np->lock);
3182 }
3183
3184 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3185 {
3186         struct fe_priv *np = netdev_priv(dev);
3187         u8 __iomem *base = get_hwbase(dev);
3188
3189         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3190
3191         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3192                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3193                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3194                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3195                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3196                 } else {
3197                         writel(pff, base + NvRegPacketFilterFlags);
3198                 }
3199         }
3200         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3201                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3202                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3203                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3204                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3205                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3206                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3207                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3208                                 /* limit the number of tx pause frames to a default of 8 */
3209                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3210                         }
3211                         writel(pause_enable,  base + NvRegTxPauseFrame);
3212                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3213                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3214                 } else {
3215                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3216                         writel(regmisc, base + NvRegMisc1);
3217                 }
3218         }
3219 }
3220
3221 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3222 {
3223         struct fe_priv *np = netdev_priv(dev);
3224         u8 __iomem *base = get_hwbase(dev);
3225         u32 phyreg, txreg;
3226         int mii_status;
3227
3228         np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3229         np->duplex = duplex;
3230
3231         /* see if gigabit phy */
3232         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3233         if (mii_status & PHY_GIGABIT) {
3234                 np->gigabit = PHY_GIGABIT;
3235                 phyreg = readl(base + NvRegSlotTime);
3236                 phyreg &= ~(0x3FF00);
3237                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3238                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3239                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3240                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3241                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3242                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3243                 writel(phyreg, base + NvRegSlotTime);
3244         }
3245
3246         phyreg = readl(base + NvRegPhyInterface);
3247         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3248         if (np->duplex == 0)
3249                 phyreg |= PHY_HALF;
3250         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3251                 phyreg |= PHY_100;
3252         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3253                                                         NVREG_LINKSPEED_1000)
3254                 phyreg |= PHY_1000;
3255         writel(phyreg, base + NvRegPhyInterface);
3256
3257         if (phyreg & PHY_RGMII) {
3258                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3259                                                         NVREG_LINKSPEED_1000)
3260                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3261                 else
3262                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3263         } else {
3264                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3265         }
3266         writel(txreg, base + NvRegTxDeferral);
3267
3268         if (np->desc_ver == DESC_VER_1) {
3269                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3270         } else {
3271                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3272                                          NVREG_LINKSPEED_1000)
3273                         txreg = NVREG_TX_WM_DESC2_3_1000;
3274                 else
3275                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3276         }
3277         writel(txreg, base + NvRegTxWatermark);
3278
3279         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3280                         base + NvRegMisc1);
3281         pci_push(base);
3282         writel(np->linkspeed, base + NvRegLinkSpeed);
3283         pci_push(base);
3284
3285         return;
3286 }
3287
3288 /**
3289  * nv_update_linkspeed - Setup the MAC according to the link partner
3290  * @dev: Network device to be configured
3291  *
3292  * The function queries the PHY and checks if there is a link partner.
3293  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3294  * set to 10 MBit HD.
3295  *
3296  * The function returns 0 if there is no link partner and 1 if there is
3297  * a good link partner.
3298  */
3299 static int nv_update_linkspeed(struct net_device *dev)
3300 {
3301         struct fe_priv *np = netdev_priv(dev);
3302         u8 __iomem *base = get_hwbase(dev);
3303         int adv = 0;
3304         int lpa = 0;
3305         int adv_lpa, adv_pause, lpa_pause;
3306         int newls = np->linkspeed;
3307         int newdup = np->duplex;
3308         int mii_status;
3309         u32 bmcr;
3310         int retval = 0;
3311         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3312         u32 txrxFlags = 0;
3313         u32 phy_exp;
3314
3315         /* If device loopback is enabled, set carrier on and enable max link
3316          * speed.
3317          */
3318         bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3319         if (bmcr & BMCR_LOOPBACK) {
3320                 if (netif_running(dev)) {
3321                         nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3322                         if (!netif_carrier_ok(dev))
3323                                 netif_carrier_on(dev);
3324                 }
3325                 return 1;
3326         }
3327
3328         /* BMSR_LSTATUS is latched, read it twice:
3329          * we want the current value.
3330          */
3331         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3332         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3333
3334         if (!(mii_status & BMSR_LSTATUS)) {
3335                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3336                 newdup = 0;
3337                 retval = 0;
3338                 goto set_speed;
3339         }
3340
3341         if (np->autoneg == 0) {
3342                 if (np->fixed_mode & LPA_100FULL) {
3343                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3344                         newdup = 1;
3345                 } else if (np->fixed_mode & LPA_100HALF) {
3346                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3347                         newdup = 0;
3348                 } else if (np->fixed_mode & LPA_10FULL) {
3349                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3350                         newdup = 1;
3351                 } else {
3352                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3353                         newdup = 0;
3354                 }
3355                 retval = 1;
3356                 goto set_speed;
3357         }
3358         /* check auto negotiation is complete */
3359         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3360                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3361                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3362                 newdup = 0;
3363                 retval = 0;
3364                 goto set_speed;
3365         }
3366
3367         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3368         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3369
3370         retval = 1;
3371         if (np->gigabit == PHY_GIGABIT) {
3372                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3373                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3374
3375                 if ((control_1000 & ADVERTISE_1000FULL) &&
3376                         (status_1000 & LPA_1000FULL)) {
3377                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3378                         newdup = 1;
3379                         goto set_speed;
3380                 }
3381         }
3382
3383         /* FIXME: handle parallel detection properly */
3384         adv_lpa = lpa & adv;
3385         if (adv_lpa & LPA_100FULL) {
3386                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3387                 newdup = 1;
3388         } else if (adv_lpa & LPA_100HALF) {
3389                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3390                 newdup = 0;
3391         } else if (adv_lpa & LPA_10FULL) {
3392                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3393                 newdup = 1;
3394         } else if (adv_lpa & LPA_10HALF) {
3395                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3396                 newdup = 0;
3397         } else {
3398                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3399                 newdup = 0;
3400         }
3401
3402 set_speed:
3403         if (np->duplex == newdup && np->linkspeed == newls)
3404                 return retval;
3405
3406         np->duplex = newdup;
3407         np->linkspeed = newls;
3408
3409         /* The transmitter and receiver must be restarted for safe update */
3410         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3411                 txrxFlags |= NV_RESTART_TX;
3412                 nv_stop_tx(dev);
3413         }
3414         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3415                 txrxFlags |= NV_RESTART_RX;
3416                 nv_stop_rx(dev);
3417         }
3418
3419         if (np->gigabit == PHY_GIGABIT) {
3420                 phyreg = readl(base + NvRegSlotTime);
3421                 phyreg &= ~(0x3FF00);
3422                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3423                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3424                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3425                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3426                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3427                 writel(phyreg, base + NvRegSlotTime);
3428         }
3429
3430         phyreg = readl(base + NvRegPhyInterface);
3431         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3432         if (np->duplex == 0)
3433                 phyreg |= PHY_HALF;
3434         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3435                 phyreg |= PHY_100;
3436         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3437                 phyreg |= PHY_1000;
3438         writel(phyreg, base + NvRegPhyInterface);
3439
3440         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3441         if (phyreg & PHY_RGMII) {
3442                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3443                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3444                 } else {
3445                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3446                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3447                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3448                                 else
3449                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3450                         } else {
3451                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3452                         }
3453                 }
3454         } else {
3455                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3456                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3457                 else
3458                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3459         }
3460         writel(txreg, base + NvRegTxDeferral);
3461
3462         if (np->desc_ver == DESC_VER_1) {
3463                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3464         } else {
3465                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3466                         txreg = NVREG_TX_WM_DESC2_3_1000;
3467                 else
3468                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3469         }
3470         writel(txreg, base + NvRegTxWatermark);
3471
3472         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3473                 base + NvRegMisc1);
3474         pci_push(base);
3475         writel(np->linkspeed, base + NvRegLinkSpeed);
3476         pci_push(base);
3477
3478         pause_flags = 0;
3479         /* setup pause frame */
3480         if (netif_running(dev) && (np->duplex != 0)) {
3481                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3482                         adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3483                         lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3484
3485                         switch (adv_pause) {
3486                         case ADVERTISE_PAUSE_CAP:
3487                                 if (lpa_pause & LPA_PAUSE_CAP) {
3488                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3489                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3490                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3491                                 }
3492                                 break;
3493                         case ADVERTISE_PAUSE_ASYM:
3494                                 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3495                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3496                                 break;
3497                         case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3498                                 if (lpa_pause & LPA_PAUSE_CAP) {
3499                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3500                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3501                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3502                                 }
3503                                 if (lpa_pause == LPA_PAUSE_ASYM)
3504                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3505                                 break;
3506                         }
3507                 } else {
3508                         pause_flags = np->pause_flags;
3509                 }
3510         }
3511         nv_update_pause(dev, pause_flags);
3512
3513         if (txrxFlags & NV_RESTART_TX)
3514                 nv_start_tx(dev);
3515         if (txrxFlags & NV_RESTART_RX)
3516                 nv_start_rx(dev);
3517
3518         return retval;
3519 }
3520
3521 static void nv_linkchange(struct net_device *dev)
3522 {
3523         if (nv_update_linkspeed(dev)) {
3524                 if (!netif_carrier_ok(dev)) {
3525                         netif_carrier_on(dev);
3526                         netdev_info(dev, "link up\n");
3527                         nv_txrx_gate(dev, false);
3528                         nv_start_rx(dev);
3529                 }
3530         } else {
3531                 if (netif_carrier_ok(dev)) {
3532                         netif_carrier_off(dev);
3533                         netdev_info(dev, "link down\n");
3534                         nv_txrx_gate(dev, true);
3535                         nv_stop_rx(dev);
3536                 }
3537         }
3538 }
3539
3540 static void nv_link_irq(struct net_device *dev)
3541 {
3542         u8 __iomem *base = get_hwbase(dev);
3543         u32 miistat;
3544
3545         miistat = readl(base + NvRegMIIStatus);
3546         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3547
3548         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3549                 nv_linkchange(dev);
3550 }
3551
3552 static void nv_msi_workaround(struct fe_priv *np)
3553 {
3554
3555         /* Need to toggle the msi irq mask within the ethernet device,
3556          * otherwise, future interrupts will not be detected.
3557          */
3558         if (np->msi_flags & NV_MSI_ENABLED) {
3559                 u8 __iomem *base = np->base;
3560
3561                 writel(0, base + NvRegMSIIrqMask);
3562                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3563         }
3564 }
3565
3566 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3567 {
3568         struct fe_priv *np = netdev_priv(dev);
3569
3570         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3571                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3572                         /* transition to poll based interrupts */
3573                         np->quiet_count = 0;
3574                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3575                                 np->irqmask = NVREG_IRQMASK_CPU;
3576                                 return 1;
3577                         }
3578                 } else {
3579                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3580                                 np->quiet_count++;
3581                         } else {
3582                                 /* reached a period of low activity, switch
3583                                    to per tx/rx packet interrupts */
3584                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3585                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3586                                         return 1;
3587                                 }
3588                         }
3589                 }
3590         }
3591         return 0;
3592 }
3593
3594 static irqreturn_t nv_nic_irq(int foo, void *data)
3595 {
3596         struct net_device *dev = (struct net_device *) data;
3597         struct fe_priv *np = netdev_priv(dev);
3598         u8 __iomem *base = get_hwbase(dev);
3599
3600         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3601                 np->events = readl(base + NvRegIrqStatus);
3602                 writel(np->events, base + NvRegIrqStatus);
3603         } else {
3604                 np->events = readl(base + NvRegMSIXIrqStatus);
3605                 writel(np->events, base + NvRegMSIXIrqStatus);
3606         }
3607         if (!(np->events & np->irqmask))
3608                 return IRQ_NONE;
3609
3610         nv_msi_workaround(np);
3611
3612         if (napi_schedule_prep(&np->napi)) {
3613                 /*
3614                  * Disable further irq's (msix not enabled with napi)
3615                  */
3616                 writel(0, base + NvRegIrqMask);
3617                 __napi_schedule(&np->napi);
3618         }
3619
3620         return IRQ_HANDLED;
3621 }
3622
3623 /* All _optimized functions are used to help increase performance
3624  * (reduce CPU and increase throughput). They use descripter version 3,
3625  * compiler directives, and reduce memory accesses.
3626  */
3627 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3628 {
3629         struct net_device *dev = (struct net_device *) data;
3630         struct fe_priv *np = netdev_priv(dev);
3631         u8 __iomem *base = get_hwbase(dev);
3632
3633         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3634                 np->events = readl(base + NvRegIrqStatus);
3635                 writel(np->events, base + NvRegIrqStatus);
3636         } else {
3637                 np->events = readl(base + NvRegMSIXIrqStatus);
3638                 writel(np->events, base + NvRegMSIXIrqStatus);
3639         }
3640         if (!(np->events & np->irqmask))
3641                 return IRQ_NONE;
3642
3643         nv_msi_workaround(np);
3644
3645         if (napi_schedule_prep(&np->napi)) {
3646                 /*
3647                  * Disable further irq's (msix not enabled with napi)
3648                  */
3649                 writel(0, base + NvRegIrqMask);
3650                 __napi_schedule(&np->napi);
3651         }
3652
3653         return IRQ_HANDLED;
3654 }
3655
3656 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3657 {
3658         struct net_device *dev = (struct net_device *) data;
3659         struct fe_priv *np = netdev_priv(dev);
3660         u8 __iomem *base = get_hwbase(dev);
3661         u32 events;
3662         int i;
3663         unsigned long flags;
3664
3665         for (i = 0;; i++) {
3666                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3667                 writel(events, base + NvRegMSIXIrqStatus);
3668                 netdev_dbg(dev, "tx irq events: %08x\n", events);
3669                 if (!(events & np->irqmask))
3670                         break;
3671
3672                 spin_lock_irqsave(&np->lock, flags);
3673                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3674                 spin_unlock_irqrestore(&np->lock, flags);
3675
3676                 if (unlikely(i > max_interrupt_work)) {
3677                         spin_lock_irqsave(&np->lock, flags);
3678                         /* disable interrupts on the nic */
3679                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3680                         pci_push(base);
3681
3682                         if (!np->in_shutdown) {
3683                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3684                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3685                         }
3686                         spin_unlock_irqrestore(&np->lock, flags);
3687                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3688                                    __func__, i);
3689                         break;
3690                 }
3691
3692         }
3693
3694         return IRQ_RETVAL(i);
3695 }
3696
3697 static int nv_napi_poll(struct napi_struct *napi, int budget)
3698 {
3699         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3700         struct net_device *dev = np->dev;
3701         u8 __iomem *base = get_hwbase(dev);
3702         unsigned long flags;
3703         int retcode;
3704         int rx_count, tx_work = 0, rx_work = 0;
3705
3706         do {
3707                 if (!nv_optimized(np)) {
3708                         spin_lock_irqsave(&np->lock, flags);
3709                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3710                         spin_unlock_irqrestore(&np->lock, flags);
3711
3712                         rx_count = nv_rx_process(dev, budget - rx_work);
3713                         retcode = nv_alloc_rx(dev);
3714                 } else {
3715                         spin_lock_irqsave(&np->lock, flags);
3716                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3717                         spin_unlock_irqrestore(&np->lock, flags);
3718
3719                         rx_count = nv_rx_process_optimized(dev,
3720                             budget - rx_work);
3721                         retcode = nv_alloc_rx_optimized(dev);
3722                 }
3723         } while (retcode == 0 &&
3724                  rx_count > 0 && (rx_work += rx_count) < budget);
3725
3726         if (retcode) {
3727                 spin_lock_irqsave(&np->lock, flags);
3728                 if (!np->in_shutdown)
3729                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3730                 spin_unlock_irqrestore(&np->lock, flags);
3731         }
3732
3733         nv_change_interrupt_mode(dev, tx_work + rx_work);
3734
3735         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3736                 spin_lock_irqsave(&np->lock, flags);
3737                 nv_link_irq(dev);
3738                 spin_unlock_irqrestore(&np->lock, flags);
3739         }
3740         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3741                 spin_lock_irqsave(&np->lock, flags);
3742                 nv_linkchange(dev);
3743                 spin_unlock_irqrestore(&np->lock, flags);
3744                 np->link_timeout = jiffies + LINK_TIMEOUT;
3745         }
3746         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3747                 spin_lock_irqsave(&np->lock, flags);
3748                 if (!np->in_shutdown) {
3749                         np->nic_poll_irq = np->irqmask;
3750                         np->recover_error = 1;
3751                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3752                 }
3753                 spin_unlock_irqrestore(&np->lock, flags);
3754                 napi_complete(napi);
3755                 return rx_work;
3756         }
3757
3758         if (rx_work < budget) {
3759                 /* re-enable interrupts
3760                    (msix not enabled in napi) */
3761                 napi_complete(napi);
3762
3763                 writel(np->irqmask, base + NvRegIrqMask);
3764         }
3765         return rx_work;
3766 }
3767
3768 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3769 {
3770         struct net_device *dev = (struct net_device *) data;
3771         struct fe_priv *np = netdev_priv(dev);
3772         u8 __iomem *base = get_hwbase(dev);
3773         u32 events;
3774         int i;
3775         unsigned long flags;
3776
3777         for (i = 0;; i++) {
3778                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3779                 writel(events, base + NvRegMSIXIrqStatus);
3780                 netdev_dbg(dev, "rx irq events: %08x\n", events);
3781                 if (!(events & np->irqmask))
3782                         break;
3783
3784                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3785                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3786                                 spin_lock_irqsave(&np->lock, flags);
3787                                 if (!np->in_shutdown)
3788                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3789                                 spin_unlock_irqrestore(&np->lock, flags);
3790                         }
3791                 }
3792
3793                 if (unlikely(i > max_interrupt_work)) {
3794                         spin_lock_irqsave(&np->lock, flags);
3795                         /* disable interrupts on the nic */
3796                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3797                         pci_push(base);
3798
3799                         if (!np->in_shutdown) {
3800                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3801                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3802                         }
3803                         spin_unlock_irqrestore(&np->lock, flags);
3804                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3805                                    __func__, i);
3806                         break;
3807                 }
3808         }
3809
3810         return IRQ_RETVAL(i);
3811 }
3812
3813 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3814 {
3815         struct net_device *dev = (struct net_device *) data;
3816         struct fe_priv *np = netdev_priv(dev);
3817         u8 __iomem *base = get_hwbase(dev);
3818         u32 events;
3819         int i;
3820         unsigned long flags;
3821
3822         for (i = 0;; i++) {
3823                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3824                 writel(events, base + NvRegMSIXIrqStatus);
3825                 netdev_dbg(dev, "irq events: %08x\n", events);
3826                 if (!(events & np->irqmask))
3827                         break;
3828
3829                 /* check tx in case we reached max loop limit in tx isr */
3830                 spin_lock_irqsave(&np->lock, flags);
3831                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3832                 spin_unlock_irqrestore(&np->lock, flags);
3833
3834                 if (events & NVREG_IRQ_LINK) {
3835                         spin_lock_irqsave(&np->lock, flags);
3836                         nv_link_irq(dev);
3837                         spin_unlock_irqrestore(&np->lock, flags);
3838                 }
3839                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3840                         spin_lock_irqsave(&np->lock, flags);
3841                         nv_linkchange(dev);
3842                         spin_unlock_irqrestore(&np->lock, flags);
3843                         np->link_timeout = jiffies + LINK_TIMEOUT;
3844                 }
3845                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3846                         spin_lock_irqsave(&np->lock, flags);
3847                         /* disable interrupts on the nic */
3848                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3849                         pci_push(base);
3850
3851                         if (!np->in_shutdown) {
3852                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3853                                 np->recover_error = 1;
3854                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3855                         }
3856                         spin_unlock_irqrestore(&np->lock, flags);
3857                         break;
3858                 }
3859                 if (unlikely(i > max_interrupt_work)) {
3860                         spin_lock_irqsave(&np->lock, flags);
3861                         /* disable interrupts on the nic */
3862                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3863                         pci_push(base);
3864
3865                         if (!np->in_shutdown) {
3866                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3867                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3868                         }
3869                         spin_unlock_irqrestore(&np->lock, flags);
3870                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3871                                    __func__, i);
3872                         break;
3873                 }
3874
3875         }
3876
3877         return IRQ_RETVAL(i);
3878 }
3879
3880 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3881 {
3882         struct net_device *dev = (struct net_device *) data;
3883         struct fe_priv *np = netdev_priv(dev);
3884         u8 __iomem *base = get_hwbase(dev);
3885         u32 events;
3886
3887         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3888                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3889                 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3890         } else {
3891                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3892                 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3893         }
3894         pci_push(base);
3895         if (!(events & NVREG_IRQ_TIMER))
3896                 return IRQ_RETVAL(0);
3897
3898         nv_msi_workaround(np);
3899
3900         spin_lock(&np->lock);
3901         np->intr_test = 1;
3902         spin_unlock(&np->lock);
3903
3904         return IRQ_RETVAL(1);
3905 }
3906
3907 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3908 {
3909         u8 __iomem *base = get_hwbase(dev);
3910         int i;
3911         u32 msixmap = 0;
3912
3913         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3914          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3915          * the remaining 8 interrupts.
3916          */
3917         for (i = 0; i < 8; i++) {
3918                 if ((irqmask >> i) & 0x1)
3919                         msixmap |= vector << (i << 2);
3920         }
3921         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3922
3923         msixmap = 0;
3924         for (i = 0; i < 8; i++) {
3925                 if ((irqmask >> (i + 8)) & 0x1)
3926                         msixmap |= vector << (i << 2);
3927         }
3928         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3929 }
3930
3931 static int nv_request_irq(struct net_device *dev, int intr_test)
3932 {
3933         struct fe_priv *np = get_nvpriv(dev);
3934         u8 __iomem *base = get_hwbase(dev);
3935         int ret = 1;
3936         int i;
3937         irqreturn_t (*handler)(int foo, void *data);
3938
3939         if (intr_test) {
3940                 handler = nv_nic_irq_test;
3941         } else {
3942                 if (nv_optimized(np))
3943                         handler = nv_nic_irq_optimized;
3944                 else
3945                         handler = nv_nic_irq;
3946         }
3947
3948         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3949                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3950                         np->msi_x_entry[i].entry = i;
3951                 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3952                 if (ret == 0) {
3953                         np->msi_flags |= NV_MSI_X_ENABLED;
3954                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3955                                 /* Request irq for rx handling */
3956                                 sprintf(np->name_rx, "%s-rx", dev->name);
3957                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3958                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3959                                         netdev_info(dev,
3960                                                     "request_irq failed for rx %d\n",
3961                                                     ret);
3962                                         pci_disable_msix(np->pci_dev);
3963                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3964                                         goto out_err;
3965                                 }
3966                                 /* Request irq for tx handling */
3967                                 sprintf(np->name_tx, "%s-tx", dev->name);
3968                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3969                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3970                                         netdev_info(dev,
3971                                                     "request_irq failed for tx %d\n",
3972                                                     ret);
3973                                         pci_disable_msix(np->pci_dev);
3974                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3975                                         goto out_free_rx;
3976                                 }
3977                                 /* Request irq for link and timer handling */
3978                                 sprintf(np->name_other, "%s-other", dev->name);
3979                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3980                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3981                                         netdev_info(dev,
3982                                                     "request_irq failed for link %d\n",
3983                                                     ret);
3984                                         pci_disable_msix(np->pci_dev);
3985                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3986                                         goto out_free_tx;
3987                                 }
3988                                 /* map interrupts to their respective vector */
3989                                 writel(0, base + NvRegMSIXMap0);
3990                                 writel(0, base + NvRegMSIXMap1);
3991                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3992                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3993                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3994                         } else {
3995                                 /* Request irq for all interrupts */
3996                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3997                                         netdev_info(dev,
3998                                                     "request_irq failed %d\n",
3999                                                     ret);
4000                                         pci_disable_msix(np->pci_dev);
4001                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4002                                         goto out_err;
4003                                 }
4004
4005                                 /* map interrupts to vector 0 */
4006                                 writel(0, base + NvRegMSIXMap0);
4007                                 writel(0, base + NvRegMSIXMap1);
4008                         }
4009                         netdev_info(dev, "MSI-X enabled\n");
4010                 }
4011         }
4012         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4013                 ret = pci_enable_msi(np->pci_dev);
4014                 if (ret == 0) {
4015                         np->msi_flags |= NV_MSI_ENABLED;
4016                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4017                                 netdev_info(dev, "request_irq failed %d\n",
4018                                             ret);
4019                                 pci_disable_msi(np->pci_dev);
4020                                 np->msi_flags &= ~NV_MSI_ENABLED;
4021                                 goto out_err;
4022                         }
4023
4024                         /* map interrupts to vector 0 */
4025                         writel(0, base + NvRegMSIMap0);
4026                         writel(0, base + NvRegMSIMap1);
4027                         /* enable msi vector 0 */
4028                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4029                         netdev_info(dev, "MSI enabled\n");
4030                 }
4031         }
4032         if (ret != 0) {
4033                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4034                         goto out_err;
4035
4036         }
4037
4038         return 0;
4039 out_free_tx:
4040         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4041 out_free_rx:
4042         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4043 out_err:
4044         return 1;
4045 }
4046
4047 static void nv_free_irq(struct net_device *dev)
4048 {
4049         struct fe_priv *np = get_nvpriv(dev);
4050         int i;
4051
4052         if (np->msi_flags & NV_MSI_X_ENABLED) {
4053                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
4054                         free_irq(np->msi_x_entry[i].vector, dev);
4055                 pci_disable_msix(np->pci_dev);
4056                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4057         } else {
4058                 free_irq(np->pci_dev->irq, dev);
4059                 if (np->msi_flags & NV_MSI_ENABLED) {
4060                         pci_disable_msi(np->pci_dev);
4061                         np->msi_flags &= ~NV_MSI_ENABLED;
4062                 }
4063         }
4064 }
4065
4066 static void nv_do_nic_poll(unsigned long data)
4067 {
4068         struct net_device *dev = (struct net_device *) data;
4069         struct fe_priv *np = netdev_priv(dev);
4070         u8 __iomem *base = get_hwbase(dev);
4071         u32 mask = 0;
4072
4073         /*
4074          * First disable irq(s) and then
4075          * reenable interrupts on the nic, we have to do this before calling
4076          * nv_nic_irq because that may decide to do otherwise
4077          */
4078
4079         if (!using_multi_irqs(dev)) {
4080                 if (np->msi_flags & NV_MSI_X_ENABLED)
4081                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4082                 else
4083                         disable_irq_lockdep(np->pci_dev->irq);
4084                 mask = np->irqmask;
4085         } else {
4086                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4087                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4088                         mask |= NVREG_IRQ_RX_ALL;
4089                 }
4090                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4091                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4092                         mask |= NVREG_IRQ_TX_ALL;
4093                 }
4094                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4095                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4096                         mask |= NVREG_IRQ_OTHER;
4097                 }
4098         }
4099         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4100
4101         if (np->recover_error) {
4102                 np->recover_error = 0;
4103                 netdev_info(dev, "MAC in recoverable error state\n");
4104                 if (netif_running(dev)) {
4105                         netif_tx_lock_bh(dev);
4106                         netif_addr_lock(dev);
4107                         spin_lock(&np->lock);
4108                         /* stop engines */
4109                         nv_stop_rxtx(dev);
4110                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4111                                 nv_mac_reset(dev);
4112                         nv_txrx_reset(dev);
4113                         /* drain rx queue */
4114                         nv_drain_rxtx(dev);
4115                         /* reinit driver view of the rx queue */
4116                         set_bufsize(dev);
4117                         if (nv_init_ring(dev)) {
4118                                 if (!np->in_shutdown)
4119                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4120                         }
4121                         /* reinit nic view of the rx queue */
4122                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4123                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4124                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4125                                 base + NvRegRingSizes);
4126                         pci_push(base);
4127                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4128                         pci_push(base);
4129                         /* clear interrupts */
4130                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4131                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4132                         else
4133                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4134
4135                         /* restart rx engine */
4136                         nv_start_rxtx(dev);
4137                         spin_unlock(&np->lock);
4138                         netif_addr_unlock(dev);
4139                         netif_tx_unlock_bh(dev);
4140                 }
4141         }
4142
4143         writel(mask, base + NvRegIrqMask);
4144         pci_push(base);
4145
4146         if (!using_multi_irqs(dev)) {
4147                 np->nic_poll_irq = 0;
4148                 if (nv_optimized(np))
4149                         nv_nic_irq_optimized(0, dev);
4150                 else
4151                         nv_nic_irq(0, dev);
4152                 if (np->msi_flags & NV_MSI_X_ENABLED)
4153                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4154                 else
4155                         enable_irq_lockdep(np->pci_dev->irq);
4156         } else {
4157                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4158                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4159                         nv_nic_irq_rx(0, dev);
4160                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4161                 }
4162                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4163                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4164                         nv_nic_irq_tx(0, dev);
4165                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4166                 }
4167                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4168                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4169                         nv_nic_irq_other(0, dev);
4170                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4171                 }
4172         }
4173
4174 }
4175
4176 #ifdef CONFIG_NET_POLL_CONTROLLER
4177 static void nv_poll_controller(struct net_device *dev)
4178 {
4179         nv_do_nic_poll((unsigned long) dev);
4180 }
4181 #endif
4182
4183 static void nv_do_stats_poll(unsigned long data)
4184         __acquires(&netdev_priv(dev)->hwstats_lock)
4185         __releases(&netdev_priv(dev)->hwstats_lock)
4186 {
4187         struct net_device *dev = (struct net_device *) data;
4188         struct fe_priv *np = netdev_priv(dev);
4189
4190         /* If lock is currently taken, the stats are being refreshed
4191          * and hence fresh enough */
4192         if (spin_trylock(&np->hwstats_lock)) {
4193                 nv_update_stats(dev);
4194                 spin_unlock(&np->hwstats_lock);
4195         }
4196
4197         if (!np->in_shutdown)
4198                 mod_timer(&np->stats_poll,
4199                         round_jiffies(jiffies + STATS_INTERVAL));
4200 }
4201
4202 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4203 {
4204         struct fe_priv *np = netdev_priv(dev);
4205         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4206         strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4207         strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4208 }
4209
4210 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4211 {
4212         struct fe_priv *np = netdev_priv(dev);
4213         wolinfo->supported = WAKE_MAGIC;
4214
4215         spin_lock_irq(&np->lock);
4216         if (np->wolenabled)
4217                 wolinfo->wolopts = WAKE_MAGIC;
4218         spin_unlock_irq(&np->lock);
4219 }
4220
4221 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4222 {
4223         struct fe_priv *np = netdev_priv(dev);
4224         u8 __iomem *base = get_hwbase(dev);
4225         u32 flags = 0;
4226
4227         if (wolinfo->wolopts == 0) {
4228                 np->wolenabled = 0;
4229         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4230                 np->wolenabled = 1;
4231                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4232         }
4233         if (netif_running(dev)) {
4234                 spin_lock_irq(&np->lock);
4235                 writel(flags, base + NvRegWakeUpFlags);
4236                 spin_unlock_irq(&np->lock);
4237         }
4238         device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4239         return 0;
4240 }
4241
4242 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4243 {
4244         struct fe_priv *np = netdev_priv(dev);
4245         u32 speed;
4246         int adv;
4247
4248         spin_lock_irq(&np->lock);
4249         ecmd->port = PORT_MII;
4250         if (!netif_running(dev)) {
4251                 /* We do not track link speed / duplex setting if the
4252                  * interface is disabled. Force a link check */
4253                 if (nv_update_linkspeed(dev)) {
4254                         if (!netif_carrier_ok(dev))
4255                                 netif_carrier_on(dev);
4256                 } else {
4257                         if (netif_carrier_ok(dev))
4258                                 netif_carrier_off(dev);
4259                 }
4260         }
4261
4262         if (netif_carrier_ok(dev)) {
4263                 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4264                 case NVREG_LINKSPEED_10:
4265                         speed = SPEED_10;
4266                         break;
4267                 case NVREG_LINKSPEED_100:
4268                         speed = SPEED_100;
4269                         break;
4270                 case NVREG_LINKSPEED_1000:
4271                         speed = SPEED_1000;
4272                         break;
4273                 default:
4274                         speed = -1;
4275                         break;
4276                 }
4277                 ecmd->duplex = DUPLEX_HALF;
4278                 if (np->duplex)
4279                         ecmd->duplex = DUPLEX_FULL;
4280         } else {
4281                 speed = -1;
4282                 ecmd->duplex = -1;
4283         }
4284         ethtool_cmd_speed_set(ecmd, speed);
4285         ecmd->autoneg = np->autoneg;
4286
4287         ecmd->advertising = ADVERTISED_MII;
4288         if (np->autoneg) {
4289                 ecmd->advertising |= ADVERTISED_Autoneg;
4290                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4291                 if (adv & ADVERTISE_10HALF)
4292                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4293                 if (adv & ADVERTISE_10FULL)
4294                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4295                 if (adv & ADVERTISE_100HALF)
4296                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4297                 if (adv & ADVERTISE_100FULL)
4298                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4299                 if (np->gigabit == PHY_GIGABIT) {
4300                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4301                         if (adv & ADVERTISE_1000FULL)
4302                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4303                 }
4304         }
4305         ecmd->supported = (SUPPORTED_Autoneg |
4306                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4307                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4308                 SUPPORTED_MII);
4309         if (np->gigabit == PHY_GIGABIT)
4310                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4311
4312         ecmd->phy_address = np->phyaddr;
4313         ecmd->transceiver = XCVR_EXTERNAL;
4314
4315         /* ignore maxtxpkt, maxrxpkt for now */
4316         spin_unlock_irq(&np->lock);
4317         return 0;
4318 }
4319
4320 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4321 {
4322         struct fe_priv *np = netdev_priv(dev);
4323         u32 speed = ethtool_cmd_speed(ecmd);
4324
4325         if (ecmd->port != PORT_MII)
4326                 return -EINVAL;
4327         if (ecmd->transceiver != XCVR_EXTERNAL)
4328                 return -EINVAL;
4329         if (ecmd->phy_address != np->phyaddr) {
4330                 /* TODO: support switching between multiple phys. Should be
4331                  * trivial, but not enabled due to lack of test hardware. */
4332                 return -EINVAL;
4333         }
4334         if (ecmd->autoneg == AUTONEG_ENABLE) {
4335                 u32 mask;
4336
4337                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4338                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4339                 if (np->gigabit == PHY_GIGABIT)
4340                         mask |= ADVERTISED_1000baseT_Full;
4341
4342                 if ((ecmd->advertising & mask) == 0)
4343                         return -EINVAL;
4344
4345         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4346                 /* Note: autonegotiation disable, speed 1000 intentionally
4347                  * forbidden - no one should need that. */
4348
4349                 if (speed != SPEED_10 && speed != SPEED_100)
4350                         return -EINVAL;
4351                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4352                         return -EINVAL;
4353         } else {
4354                 return -EINVAL;
4355         }
4356
4357         netif_carrier_off(dev);
4358         if (netif_running(dev)) {
4359                 unsigned long flags;
4360
4361                 nv_disable_irq(dev);
4362                 netif_tx_lock_bh(dev);
4363                 netif_addr_lock(dev);
4364                 /* with plain spinlock lockdep complains */
4365                 spin_lock_irqsave(&np->lock, flags);
4366                 /* stop engines */
4367                 /* FIXME:
4368                  * this can take some time, and interrupts are disabled
4369                  * due to spin_lock_irqsave, but let's hope no daemon
4370                  * is going to change the settings very often...
4371                  * Worst case:
4372                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4373                  * + some minor delays, which is up to a second approximately
4374                  */
4375                 nv_stop_rxtx(dev);
4376                 spin_unlock_irqrestore(&np->lock, flags);
4377                 netif_addr_unlock(dev);
4378                 netif_tx_unlock_bh(dev);
4379         }
4380
4381         if (ecmd->autoneg == AUTONEG_ENABLE) {
4382                 int adv, bmcr;
4383
4384                 np->autoneg = 1;
4385
4386                 /* advertise only what has been requested */
4387                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4388                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4389                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4390                         adv |= ADVERTISE_10HALF;
4391                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4392                         adv |= ADVERTISE_10FULL;
4393                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4394                         adv |= ADVERTISE_100HALF;
4395                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4396                         adv |= ADVERTISE_100FULL;
4397                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisements but disable tx pause */
4398                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4399                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4400                         adv |=  ADVERTISE_PAUSE_ASYM;
4401                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4402
4403                 if (np->gigabit == PHY_GIGABIT) {
4404                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4405                         adv &= ~ADVERTISE_1000FULL;
4406                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4407                                 adv |= ADVERTISE_1000FULL;
4408                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4409                 }
4410
4411                 if (netif_running(dev))
4412                         netdev_info(dev, "link down\n");
4413                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4414                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4415                         bmcr |= BMCR_ANENABLE;
4416                         /* reset the phy in order for settings to stick,
4417                          * and cause autoneg to start */
4418                         if (phy_reset(dev, bmcr)) {
4419                                 netdev_info(dev, "phy reset failed\n");
4420                                 return -EINVAL;
4421                         }
4422                 } else {
4423                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4424                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4425                 }
4426         } else {
4427                 int adv, bmcr;
4428
4429                 np->autoneg = 0;
4430
4431                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4432                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4433                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4434                         adv |= ADVERTISE_10HALF;
4435                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4436                         adv |= ADVERTISE_10FULL;
4437                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4438                         adv |= ADVERTISE_100HALF;
4439                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4440                         adv |= ADVERTISE_100FULL;
4441                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4442                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4443                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4444                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4445                 }
4446                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4447                         adv |=  ADVERTISE_PAUSE_ASYM;
4448                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4449                 }
4450                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4451                 np->fixed_mode = adv;
4452
4453                 if (np->gigabit == PHY_GIGABIT) {
4454                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4455                         adv &= ~ADVERTISE_1000FULL;
4456                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4457                 }
4458
4459                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4460                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4461                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4462                         bmcr |= BMCR_FULLDPLX;
4463                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4464                         bmcr |= BMCR_SPEED100;
4465                 if (np->phy_oui == PHY_OUI_MARVELL) {
4466                         /* reset the phy in order for forced mode settings to stick */
4467                         if (phy_reset(dev, bmcr)) {
4468                                 netdev_info(dev, "phy reset failed\n");
4469                                 return -EINVAL;
4470                         }
4471                 } else {
4472                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4473                         if (netif_running(dev)) {
4474                                 /* Wait a bit and then reconfigure the nic. */
4475                                 udelay(10);
4476                                 nv_linkchange(dev);
4477                         }
4478                 }
4479         }
4480
4481         if (netif_running(dev)) {
4482                 nv_start_rxtx(dev);
4483                 nv_enable_irq(dev);
4484         }
4485
4486         return 0;
4487 }
4488
4489 #define FORCEDETH_REGS_VER      1
4490
4491 static int nv_get_regs_len(struct net_device *dev)
4492 {
4493         struct fe_priv *np = netdev_priv(dev);
4494         return np->register_size;
4495 }
4496
4497 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4498 {
4499         struct fe_priv *np = netdev_priv(dev);
4500         u8 __iomem *base = get_hwbase(dev);
4501         u32 *rbuf = buf;
4502         int i;
4503
4504         regs->version = FORCEDETH_REGS_VER;
4505         spin_lock_irq(&np->lock);
4506         for (i = 0; i < np->register_size/sizeof(u32); i++)
4507                 rbuf[i] = readl(base + i*sizeof(u32));
4508         spin_unlock_irq(&np->lock);
4509 }
4510
4511 static int nv_nway_reset(struct net_device *dev)
4512 {
4513         struct fe_priv *np = netdev_priv(dev);
4514         int ret;
4515
4516         if (np->autoneg) {
4517                 int bmcr;
4518
4519                 netif_carrier_off(dev);
4520                 if (netif_running(dev)) {
4521                         nv_disable_irq(dev);
4522                         netif_tx_lock_bh(dev);
4523                         netif_addr_lock(dev);
4524                         spin_lock(&np->lock);
4525                         /* stop engines */
4526                         nv_stop_rxtx(dev);
4527                         spin_unlock(&np->lock);
4528                         netif_addr_unlock(dev);
4529                         netif_tx_unlock_bh(dev);
4530                         netdev_info(dev, "link down\n");
4531                 }
4532
4533                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4534                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4535                         bmcr |= BMCR_ANENABLE;
4536                         /* reset the phy in order for settings to stick*/
4537                         if (phy_reset(dev, bmcr)) {
4538                                 netdev_info(dev, "phy reset failed\n");
4539                                 return -EINVAL;
4540                         }
4541                 } else {
4542                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4543                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4544                 }
4545
4546                 if (netif_running(dev)) {
4547                         nv_start_rxtx(dev);
4548                         nv_enable_irq(dev);
4549                 }
4550                 ret = 0;
4551         } else {
4552                 ret = -EINVAL;
4553         }
4554
4555         return ret;
4556 }
4557
4558 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4559 {
4560         struct fe_priv *np = netdev_priv(dev);
4561
4562         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4563         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4564
4565         ring->rx_pending = np->rx_ring_size;
4566         ring->tx_pending = np->tx_ring_size;
4567 }
4568
4569 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4570 {
4571         struct fe_priv *np = netdev_priv(dev);
4572         u8 __iomem *base = get_hwbase(dev);
4573         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4574         dma_addr_t ring_addr;
4575
4576         if (ring->rx_pending < RX_RING_MIN ||
4577             ring->tx_pending < TX_RING_MIN ||
4578             ring->rx_mini_pending != 0 ||
4579             ring->rx_jumbo_pending != 0 ||
4580             (np->desc_ver == DESC_VER_1 &&
4581              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4582               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4583             (np->desc_ver != DESC_VER_1 &&
4584              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4585               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4586                 return -EINVAL;
4587         }
4588
4589         /* allocate new rings */
4590         if (!nv_optimized(np)) {
4591                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4592                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4593                                             &ring_addr);
4594         } else {
4595                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4596                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4597                                             &ring_addr);
4598         }
4599         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4600         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4601         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4602                 /* fall back to old rings */
4603                 if (!nv_optimized(np)) {
4604                         if (rxtx_ring)
4605                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4606                                                     rxtx_ring, ring_addr);
4607                 } else {
4608                         if (rxtx_ring)
4609                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4610                                                     rxtx_ring, ring_addr);
4611                 }
4612
4613                 kfree(rx_skbuff);
4614                 kfree(tx_skbuff);
4615                 goto exit;
4616         }
4617
4618         if (netif_running(dev)) {
4619                 nv_disable_irq(dev);
4620                 nv_napi_disable(dev);
4621                 netif_tx_lock_bh(dev);
4622                 netif_addr_lock(dev);
4623                 spin_lock(&np->lock);
4624                 /* stop engines */
4625                 nv_stop_rxtx(dev);
4626                 nv_txrx_reset(dev);
4627                 /* drain queues */
4628                 nv_drain_rxtx(dev);
4629                 /* delete queues */
4630                 free_rings(dev);
4631         }
4632
4633         /* set new values */
4634         np->rx_ring_size = ring->rx_pending;
4635         np->tx_ring_size = ring->tx_pending;
4636
4637         if (!nv_optimized(np)) {
4638                 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4639                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4640         } else {
4641                 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4642                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4643         }
4644         np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4645         np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4646         np->ring_addr = ring_addr;
4647
4648         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4649         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4650
4651         if (netif_running(dev)) {
4652                 /* reinit driver view of the queues */
4653                 set_bufsize(dev);
4654                 if (nv_init_ring(dev)) {
4655                         if (!np->in_shutdown)
4656                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4657                 }
4658
4659                 /* reinit nic view of the queues */
4660                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4661                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4662                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4663                         base + NvRegRingSizes);
4664                 pci_push(base);
4665                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4666                 pci_push(base);
4667
4668                 /* restart engines */
4669                 nv_start_rxtx(dev);
4670                 spin_unlock(&np->lock);
4671                 netif_addr_unlock(dev);
4672                 netif_tx_unlock_bh(dev);
4673                 nv_napi_enable(dev);
4674                 nv_enable_irq(dev);
4675         }
4676         return 0;
4677 exit:
4678         return -ENOMEM;
4679 }
4680
4681 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4682 {
4683         struct fe_priv *np = netdev_priv(dev);
4684
4685         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4686         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4687         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4688 }
4689
4690 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4691 {
4692         struct fe_priv *np = netdev_priv(dev);
4693         int adv, bmcr;
4694
4695         if ((!np->autoneg && np->duplex == 0) ||
4696             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4697                 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4698                 return -EINVAL;
4699         }
4700         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4701                 netdev_info(dev, "hardware does not support tx pause frames\n");
4702                 return -EINVAL;
4703         }
4704
4705         netif_carrier_off(dev);
4706         if (netif_running(dev)) {
4707                 nv_disable_irq(dev);
4708                 netif_tx_lock_bh(dev);
4709                 netif_addr_lock(dev);
4710                 spin_lock(&np->lock);
4711                 /* stop engines */
4712                 nv_stop_rxtx(dev);
4713                 spin_unlock(&np->lock);
4714                 netif_addr_unlock(dev);
4715                 netif_tx_unlock_bh(dev);
4716         }
4717
4718         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4719         if (pause->rx_pause)
4720                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4721         if (pause->tx_pause)
4722                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4723
4724         if (np->autoneg && pause->autoneg) {
4725                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4726
4727                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4728                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4729                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4730                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4731                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4732                         adv |=  ADVERTISE_PAUSE_ASYM;
4733                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4734
4735                 if (netif_running(dev))
4736                         netdev_info(dev, "link down\n");
4737                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4738                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4739                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4740         } else {
4741                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4742                 if (pause->rx_pause)
4743                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4744                 if (pause->tx_pause)
4745                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4746
4747                 if (!netif_running(dev))
4748                         nv_update_linkspeed(dev);
4749                 else
4750                         nv_update_pause(dev, np->pause_flags);
4751         }
4752
4753         if (netif_running(dev)) {
4754                 nv_start_rxtx(dev);
4755                 nv_enable_irq(dev);
4756         }
4757         return 0;
4758 }
4759
4760 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4761 {
4762         struct fe_priv *np = netdev_priv(dev);
4763         unsigned long flags;
4764         u32 miicontrol;
4765         int err, retval = 0;
4766
4767         spin_lock_irqsave(&np->lock, flags);
4768         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4769         if (features & NETIF_F_LOOPBACK) {
4770                 if (miicontrol & BMCR_LOOPBACK) {
4771                         spin_unlock_irqrestore(&np->lock, flags);
4772                         netdev_info(dev, "Loopback already enabled\n");
4773                         return 0;
4774                 }
4775                 nv_disable_irq(dev);
4776                 /* Turn on loopback mode */
4777                 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4778                 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4779                 if (err) {
4780                         retval = PHY_ERROR;
4781                         spin_unlock_irqrestore(&np->lock, flags);
4782                         phy_init(dev);
4783                 } else {
4784                         if (netif_running(dev)) {
4785                                 /* Force 1000 Mbps full-duplex */
4786                                 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4787                                                                          1);
4788                                 /* Force link up */
4789                                 netif_carrier_on(dev);
4790                         }
4791                         spin_unlock_irqrestore(&np->lock, flags);
4792                         netdev_info(dev,
4793                                 "Internal PHY loopback mode enabled.\n");
4794                 }
4795         } else {
4796                 if (!(miicontrol & BMCR_LOOPBACK)) {
4797                         spin_unlock_irqrestore(&np->lock, flags);
4798                         netdev_info(dev, "Loopback already disabled\n");
4799                         return 0;
4800                 }
4801                 nv_disable_irq(dev);
4802                 /* Turn off loopback */
4803                 spin_unlock_irqrestore(&np->lock, flags);
4804                 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4805                 phy_init(dev);
4806         }
4807         msleep(500);
4808         spin_lock_irqsave(&np->lock, flags);
4809         nv_enable_irq(dev);
4810         spin_unlock_irqrestore(&np->lock, flags);
4811
4812         return retval;
4813 }
4814
4815 static netdev_features_t nv_fix_features(struct net_device *dev,
4816         netdev_features_t features)
4817 {
4818         /* vlan is dependent on rx checksum offload */
4819         if (features & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4820                 features |= NETIF_F_RXCSUM;
4821
4822         return features;
4823 }
4824
4825 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4826 {
4827         struct fe_priv *np = get_nvpriv(dev);
4828
4829         spin_lock_irq(&np->lock);
4830
4831         if (features & NETIF_F_HW_VLAN_CTAG_RX)
4832                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4833         else
4834                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4835
4836         if (features & NETIF_F_HW_VLAN_CTAG_TX)
4837                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4838         else
4839                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4840
4841         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4842
4843         spin_unlock_irq(&np->lock);
4844 }
4845
4846 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4847 {
4848         struct fe_priv *np = netdev_priv(dev);
4849         u8 __iomem *base = get_hwbase(dev);
4850         netdev_features_t changed = dev->features ^ features;
4851         int retval;
4852
4853         if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4854                 retval = nv_set_loopback(dev, features);
4855                 if (retval != 0)
4856                         return retval;
4857         }
4858
4859         if (changed & NETIF_F_RXCSUM) {
4860                 spin_lock_irq(&np->lock);
4861
4862                 if (features & NETIF_F_RXCSUM)
4863                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4864                 else
4865                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4866
4867                 if (netif_running(dev))
4868                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4869
4870                 spin_unlock_irq(&np->lock);
4871         }
4872
4873         if (changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX))
4874                 nv_vlan_mode(dev, features);
4875
4876         return 0;
4877 }
4878
4879 static int nv_get_sset_count(struct net_device *dev, int sset)
4880 {
4881         struct fe_priv *np = netdev_priv(dev);
4882
4883         switch (sset) {
4884         case ETH_SS_TEST:
4885                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4886                         return NV_TEST_COUNT_EXTENDED;
4887                 else
4888                         return NV_TEST_COUNT_BASE;
4889         case ETH_SS_STATS:
4890                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4891                         return NV_DEV_STATISTICS_V3_COUNT;
4892                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4893                         return NV_DEV_STATISTICS_V2_COUNT;
4894                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4895                         return NV_DEV_STATISTICS_V1_COUNT;
4896                 else
4897                         return 0;
4898         default:
4899                 return -EOPNOTSUPP;
4900         }
4901 }
4902
4903 static void nv_get_ethtool_stats(struct net_device *dev,
4904                                  struct ethtool_stats *estats, u64 *buffer)
4905         __acquires(&netdev_priv(dev)->hwstats_lock)
4906         __releases(&netdev_priv(dev)->hwstats_lock)
4907 {
4908         struct fe_priv *np = netdev_priv(dev);
4909
4910         spin_lock_bh(&np->hwstats_lock);
4911         nv_update_stats(dev);
4912         memcpy(buffer, &np->estats,
4913                nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4914         spin_unlock_bh(&np->hwstats_lock);
4915 }
4916
4917 static int nv_link_test(struct net_device *dev)
4918 {
4919         struct fe_priv *np = netdev_priv(dev);
4920         int mii_status;
4921
4922         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4923         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4924
4925         /* check phy link status */
4926         if (!(mii_status & BMSR_LSTATUS))
4927                 return 0;
4928         else
4929                 return 1;
4930 }
4931
4932 static int nv_register_test(struct net_device *dev)
4933 {
4934         u8 __iomem *base = get_hwbase(dev);
4935         int i = 0;
4936         u32 orig_read, new_read;
4937
4938         do {
4939                 orig_read = readl(base + nv_registers_test[i].reg);
4940
4941                 /* xor with mask to toggle bits */
4942                 orig_read ^= nv_registers_test[i].mask;
4943
4944                 writel(orig_read, base + nv_registers_test[i].reg);
4945
4946                 new_read = readl(base + nv_registers_test[i].reg);
4947
4948                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4949                         return 0;
4950
4951                 /* restore original value */
4952                 orig_read ^= nv_registers_test[i].mask;
4953                 writel(orig_read, base + nv_registers_test[i].reg);
4954
4955         } while (nv_registers_test[++i].reg != 0);
4956
4957         return 1;
4958 }
4959
4960 static int nv_interrupt_test(struct net_device *dev)
4961 {
4962         struct fe_priv *np = netdev_priv(dev);
4963         u8 __iomem *base = get_hwbase(dev);
4964         int ret = 1;
4965         int testcnt;
4966         u32 save_msi_flags, save_poll_interval = 0;
4967
4968         if (netif_running(dev)) {
4969                 /* free current irq */
4970                 nv_free_irq(dev);
4971                 save_poll_interval = readl(base+NvRegPollingInterval);
4972         }
4973
4974         /* flag to test interrupt handler */
4975         np->intr_test = 0;
4976
4977         /* setup test irq */
4978         save_msi_flags = np->msi_flags;
4979         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4980         np->msi_flags |= 0x001; /* setup 1 vector */
4981         if (nv_request_irq(dev, 1))
4982                 return 0;
4983
4984         /* setup timer interrupt */
4985         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4986         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4987
4988         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4989
4990         /* wait for at least one interrupt */
4991         msleep(100);
4992
4993         spin_lock_irq(&np->lock);
4994
4995         /* flag should be set within ISR */
4996         testcnt = np->intr_test;
4997         if (!testcnt)
4998                 ret = 2;
4999
5000         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
5001         if (!(np->msi_flags & NV_MSI_X_ENABLED))
5002                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5003         else
5004                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5005
5006         spin_unlock_irq(&np->lock);
5007
5008         nv_free_irq(dev);
5009
5010         np->msi_flags = save_msi_flags;
5011
5012         if (netif_running(dev)) {
5013                 writel(save_poll_interval, base + NvRegPollingInterval);
5014                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5015                 /* restore original irq */
5016                 if (nv_request_irq(dev, 0))
5017                         return 0;
5018         }
5019
5020         return ret;
5021 }
5022
5023 static int nv_loopback_test(struct net_device *dev)
5024 {
5025         struct fe_priv *np = netdev_priv(dev);
5026         u8 __iomem *base = get_hwbase(dev);
5027         struct sk_buff *tx_skb, *rx_skb;
5028         dma_addr_t test_dma_addr;
5029         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
5030         u32 flags;
5031         int len, i, pkt_len;
5032         u8 *pkt_data;
5033         u32 filter_flags = 0;
5034         u32 misc1_flags = 0;
5035         int ret = 1;
5036
5037         if (netif_running(dev)) {
5038                 nv_disable_irq(dev);
5039                 filter_flags = readl(base + NvRegPacketFilterFlags);
5040                 misc1_flags = readl(base + NvRegMisc1);
5041         } else {
5042                 nv_txrx_reset(dev);
5043         }
5044
5045         /* reinit driver view of the rx queue */
5046         set_bufsize(dev);
5047         nv_init_ring(dev);
5048
5049         /* setup hardware for loopback */
5050         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5051         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5052
5053         /* reinit nic view of the rx queue */
5054         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5055         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5056         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5057                 base + NvRegRingSizes);
5058         pci_push(base);
5059
5060         /* restart rx engine */
5061         nv_start_rxtx(dev);
5062
5063         /* setup packet for tx */
5064         pkt_len = ETH_DATA_LEN;
5065         tx_skb = netdev_alloc_skb(dev, pkt_len);
5066         if (!tx_skb) {
5067                 ret = 0;
5068                 goto out;
5069         }
5070         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5071                                        skb_tailroom(tx_skb),
5072                                        PCI_DMA_FROMDEVICE);
5073         if (pci_dma_mapping_error(np->pci_dev,
5074                                   test_dma_addr)) {
5075                 dev_kfree_skb_any(tx_skb);
5076                 goto out;
5077         }
5078         pkt_data = skb_put(tx_skb, pkt_len);
5079         for (i = 0; i < pkt_len; i++)
5080                 pkt_data[i] = (u8)(i & 0xff);
5081
5082         if (!nv_optimized(np)) {
5083                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5084                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5085         } else {
5086                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5087                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5088                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5089         }
5090         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5091         pci_push(get_hwbase(dev));
5092
5093         msleep(500);
5094
5095         /* check for rx of the packet */
5096         if (!nv_optimized(np)) {
5097                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5098                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5099
5100         } else {
5101                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5102                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5103         }
5104
5105         if (flags & NV_RX_AVAIL) {
5106                 ret = 0;
5107         } else if (np->desc_ver == DESC_VER_1) {
5108                 if (flags & NV_RX_ERROR)
5109                         ret = 0;
5110         } else {
5111                 if (flags & NV_RX2_ERROR)
5112                         ret = 0;
5113         }
5114
5115         if (ret) {
5116                 if (len != pkt_len) {
5117                         ret = 0;
5118                 } else {
5119                         rx_skb = np->rx_skb[0].skb;
5120                         for (i = 0; i < pkt_len; i++) {
5121                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5122                                         ret = 0;
5123                                         break;
5124                                 }
5125                         }
5126                 }
5127         }
5128
5129         pci_unmap_single(np->pci_dev, test_dma_addr,
5130                        (skb_end_pointer(tx_skb) - tx_skb->data),
5131                        PCI_DMA_TODEVICE);
5132         dev_kfree_skb_any(tx_skb);
5133  out:
5134         /* stop engines */
5135         nv_stop_rxtx(dev);
5136         nv_txrx_reset(dev);
5137         /* drain rx queue */
5138         nv_drain_rxtx(dev);
5139
5140         if (netif_running(dev)) {
5141                 writel(misc1_flags, base + NvRegMisc1);
5142                 writel(filter_flags, base + NvRegPacketFilterFlags);
5143                 nv_enable_irq(dev);
5144         }
5145
5146         return ret;
5147 }
5148
5149 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5150 {
5151         struct fe_priv *np = netdev_priv(dev);
5152         u8 __iomem *base = get_hwbase(dev);
5153         int result, count;
5154
5155         count = nv_get_sset_count(dev, ETH_SS_TEST);
5156         memset(buffer, 0, count * sizeof(u64));
5157
5158         if (!nv_link_test(dev)) {
5159                 test->flags |= ETH_TEST_FL_FAILED;
5160                 buffer[0] = 1;
5161         }
5162
5163         if (test->flags & ETH_TEST_FL_OFFLINE) {
5164                 if (netif_running(dev)) {
5165                         netif_stop_queue(dev);
5166                         nv_napi_disable(dev);
5167                         netif_tx_lock_bh(dev);
5168                         netif_addr_lock(dev);
5169                         spin_lock_irq(&np->lock);
5170                         nv_disable_hw_interrupts(dev, np->irqmask);
5171                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
5172                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5173                         else
5174                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5175                         /* stop engines */
5176                         nv_stop_rxtx(dev);
5177                         nv_txrx_reset(dev);
5178                         /* drain rx queue */
5179                         nv_drain_rxtx(dev);
5180                         spin_unlock_irq(&np->lock);
5181                         netif_addr_unlock(dev);
5182                         netif_tx_unlock_bh(dev);
5183                 }
5184
5185                 if (!nv_register_test(dev)) {
5186                         test->flags |= ETH_TEST_FL_FAILED;
5187                         buffer[1] = 1;
5188                 }
5189
5190                 result = nv_interrupt_test(dev);
5191                 if (result != 1) {
5192                         test->flags |= ETH_TEST_FL_FAILED;
5193                         buffer[2] = 1;
5194                 }
5195                 if (result == 0) {
5196                         /* bail out */
5197                         return;
5198                 }
5199
5200                 if (count > NV_TEST_COUNT_BASE && !nv_loopback_test(dev)) {
5201                         test->flags |= ETH_TEST_FL_FAILED;
5202                         buffer[3] = 1;
5203                 }
5204
5205                 if (netif_running(dev)) {
5206                         /* reinit driver view of the rx queue */
5207                         set_bufsize(dev);
5208                         if (nv_init_ring(dev)) {
5209                                 if (!np->in_shutdown)
5210                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5211                         }
5212                         /* reinit nic view of the rx queue */
5213                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5214                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5215                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5216                                 base + NvRegRingSizes);
5217                         pci_push(base);
5218                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5219                         pci_push(base);
5220                         /* restart rx engine */
5221                         nv_start_rxtx(dev);
5222                         netif_start_queue(dev);
5223                         nv_napi_enable(dev);
5224                         nv_enable_hw_interrupts(dev, np->irqmask);
5225                 }
5226         }
5227 }
5228
5229 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5230 {
5231         switch (stringset) {
5232         case ETH_SS_STATS:
5233                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5234                 break;
5235         case ETH_SS_TEST:
5236                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5237                 break;
5238         }
5239 }
5240
5241 static const struct ethtool_ops ops = {
5242         .get_drvinfo = nv_get_drvinfo,
5243         .get_link = ethtool_op_get_link,
5244         .get_wol = nv_get_wol,
5245         .set_wol = nv_set_wol,
5246         .get_settings = nv_get_settings,
5247         .set_settings = nv_set_settings,
5248         .get_regs_len = nv_get_regs_len,
5249         .get_regs = nv_get_regs,
5250         .nway_reset = nv_nway_reset,
5251         .get_ringparam = nv_get_ringparam,
5252         .set_ringparam = nv_set_ringparam,
5253         .get_pauseparam = nv_get_pauseparam,
5254         .set_pauseparam = nv_set_pauseparam,
5255         .get_strings = nv_get_strings,
5256         .get_ethtool_stats = nv_get_ethtool_stats,
5257         .get_sset_count = nv_get_sset_count,
5258         .self_test = nv_self_test,
5259         .get_ts_info = ethtool_op_get_ts_info,
5260 };
5261
5262 /* The mgmt unit and driver use a semaphore to access the phy during init */
5263 static int nv_mgmt_acquire_sema(struct net_device *dev)
5264 {
5265         struct fe_priv *np = netdev_priv(dev);
5266         u8 __iomem *base = get_hwbase(dev);
5267         int i;
5268         u32 tx_ctrl, mgmt_sema;
5269
5270         for (i = 0; i < 10; i++) {
5271                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5272                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5273                         break;
5274                 msleep(500);
5275         }
5276
5277         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5278                 return 0;
5279
5280         for (i = 0; i < 2; i++) {
5281                 tx_ctrl = readl(base + NvRegTransmitterControl);
5282                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5283                 writel(tx_ctrl, base + NvRegTransmitterControl);
5284
5285                 /* verify that semaphore was acquired */
5286                 tx_ctrl = readl(base + NvRegTransmitterControl);
5287                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5288                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5289                         np->mgmt_sema = 1;
5290                         return 1;
5291                 } else
5292                         udelay(50);
5293         }
5294
5295         return 0;
5296 }
5297
5298 static void nv_mgmt_release_sema(struct net_device *dev)
5299 {
5300         struct fe_priv *np = netdev_priv(dev);
5301         u8 __iomem *base = get_hwbase(dev);
5302         u32 tx_ctrl;
5303
5304         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5305                 if (np->mgmt_sema) {
5306                         tx_ctrl = readl(base + NvRegTransmitterControl);
5307                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5308                         writel(tx_ctrl, base + NvRegTransmitterControl);
5309                 }
5310         }
5311 }
5312
5313
5314 static int nv_mgmt_get_version(struct net_device *dev)
5315 {
5316         struct fe_priv *np = netdev_priv(dev);
5317         u8 __iomem *base = get_hwbase(dev);
5318         u32 data_ready = readl(base + NvRegTransmitterControl);
5319         u32 data_ready2 = 0;
5320         unsigned long start;
5321         int ready = 0;
5322
5323         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5324         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5325         start = jiffies;
5326         while (time_before(jiffies, start + 5*HZ)) {
5327                 data_ready2 = readl(base + NvRegTransmitterControl);
5328                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5329                         ready = 1;
5330                         break;
5331                 }
5332                 schedule_timeout_uninterruptible(1);
5333         }
5334
5335         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5336                 return 0;
5337
5338         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5339
5340         return 1;
5341 }
5342
5343 static int nv_open(struct net_device *dev)
5344 {
5345         struct fe_priv *np = netdev_priv(dev);
5346         u8 __iomem *base = get_hwbase(dev);
5347         int ret = 1;
5348         int oom, i;
5349         u32 low;
5350
5351         /* power up phy */
5352         mii_rw(dev, np->phyaddr, MII_BMCR,
5353                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5354
5355         nv_txrx_gate(dev, false);
5356         /* erase previous misconfiguration */
5357         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5358                 nv_mac_reset(dev);
5359         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5360         writel(0, base + NvRegMulticastAddrB);
5361         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5362         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5363         writel(0, base + NvRegPacketFilterFlags);
5364
5365         writel(0, base + NvRegTransmitterControl);
5366         writel(0, base + NvRegReceiverControl);
5367
5368         writel(0, base + NvRegAdapterControl);
5369
5370         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5371                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5372
5373         /* initialize descriptor rings */
5374         set_bufsize(dev);
5375         oom = nv_init_ring(dev);
5376
5377         writel(0, base + NvRegLinkSpeed);
5378         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5379         nv_txrx_reset(dev);
5380         writel(0, base + NvRegUnknownSetupReg6);
5381
5382         np->in_shutdown = 0;
5383
5384         /* give hw rings */
5385         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5386         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5387                 base + NvRegRingSizes);
5388
5389         writel(np->linkspeed, base + NvRegLinkSpeed);
5390         if (np->desc_ver == DESC_VER_1)
5391                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5392         else
5393                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5394         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5395         writel(np->vlanctl_bits, base + NvRegVlanControl);
5396         pci_push(base);
5397         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5398         if (reg_delay(dev, NvRegUnknownSetupReg5,
5399                       NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5400                       NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5401                 netdev_info(dev,
5402                             "%s: SetupReg5, Bit 31 remained off\n", __func__);
5403
5404         writel(0, base + NvRegMIIMask);
5405         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5406         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5407
5408         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5409         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5410         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5411         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5412
5413         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5414
5415         get_random_bytes(&low, sizeof(low));
5416         low &= NVREG_SLOTTIME_MASK;
5417         if (np->desc_ver == DESC_VER_1) {
5418                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5419         } else {
5420                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5421                         /* setup legacy backoff */
5422                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5423                 } else {
5424                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5425                         nv_gear_backoff_reseed(dev);
5426                 }
5427         }
5428         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5429         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5430         if (poll_interval == -1) {
5431                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5432                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5433                 else
5434                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5435         } else
5436                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5437         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5438         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5439                         base + NvRegAdapterControl);
5440         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5441         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5442         if (np->wolenabled)
5443                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5444
5445         i = readl(base + NvRegPowerState);
5446         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5447                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5448
5449         pci_push(base);
5450         udelay(10);
5451         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5452
5453         nv_disable_hw_interrupts(dev, np->irqmask);
5454         pci_push(base);
5455         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5456         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5457         pci_push(base);
5458
5459         if (nv_request_irq(dev, 0))
5460                 goto out_drain;
5461
5462         /* ask for interrupts */
5463         nv_enable_hw_interrupts(dev, np->irqmask);
5464
5465         spin_lock_irq(&np->lock);
5466         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5467         writel(0, base + NvRegMulticastAddrB);
5468         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5469         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5470         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5471         /* One manual link speed update: Interrupts are enabled, future link
5472          * speed changes cause interrupts and are handled by nv_link_irq().
5473          */
5474         {
5475                 u32 miistat;
5476                 miistat = readl(base + NvRegMIIStatus);
5477                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5478         }
5479         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5480          * to init hw */
5481         np->linkspeed = 0;
5482         ret = nv_update_linkspeed(dev);
5483         nv_start_rxtx(dev);
5484         netif_start_queue(dev);
5485         nv_napi_enable(dev);
5486
5487         if (ret) {
5488                 netif_carrier_on(dev);
5489         } else {
5490                 netdev_info(dev, "no link during initialization\n");
5491                 netif_carrier_off(dev);
5492         }
5493         if (oom)
5494                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5495
5496         /* start statistics timer */
5497         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5498                 mod_timer(&np->stats_poll,
5499                         round_jiffies(jiffies + STATS_INTERVAL));
5500
5501         spin_unlock_irq(&np->lock);
5502
5503         /* If the loopback feature was set while the device was down, make sure
5504          * that it's set correctly now.
5505          */
5506         if (dev->features & NETIF_F_LOOPBACK)
5507                 nv_set_loopback(dev, dev->features);
5508
5509         return 0;
5510 out_drain:
5511         nv_drain_rxtx(dev);
5512         return ret;
5513 }
5514
5515 static int nv_close(struct net_device *dev)
5516 {
5517         struct fe_priv *np = netdev_priv(dev);
5518         u8 __iomem *base;
5519
5520         spin_lock_irq(&np->lock);
5521         np->in_shutdown = 1;
5522         spin_unlock_irq(&np->lock);
5523         nv_napi_disable(dev);
5524         synchronize_irq(np->pci_dev->irq);
5525
5526         del_timer_sync(&np->oom_kick);
5527         del_timer_sync(&np->nic_poll);
5528         del_timer_sync(&np->stats_poll);
5529
5530         netif_stop_queue(dev);
5531         spin_lock_irq(&np->lock);
5532         nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */
5533         nv_stop_rxtx(dev);
5534         nv_txrx_reset(dev);
5535
5536         /* disable interrupts on the nic or we will lock up */
5537         base = get_hwbase(dev);
5538         nv_disable_hw_interrupts(dev, np->irqmask);
5539         pci_push(base);
5540
5541         spin_unlock_irq(&np->lock);
5542
5543         nv_free_irq(dev);
5544
5545         nv_drain_rxtx(dev);
5546
5547         if (np->wolenabled || !phy_power_down) {
5548                 nv_txrx_gate(dev, false);
5549                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5550                 nv_start_rx(dev);
5551         } else {
5552                 /* power down phy */
5553                 mii_rw(dev, np->phyaddr, MII_BMCR,
5554                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5555                 nv_txrx_gate(dev, true);
5556         }
5557
5558         /* FIXME: power down nic */
5559
5560         return 0;
5561 }
5562
5563 static const struct net_device_ops nv_netdev_ops = {
5564         .ndo_open               = nv_open,
5565         .ndo_stop               = nv_close,
5566         .ndo_get_stats64        = nv_get_stats64,
5567         .ndo_start_xmit         = nv_start_xmit,
5568         .ndo_tx_timeout         = nv_tx_timeout,
5569         .ndo_change_mtu         = nv_change_mtu,
5570         .ndo_fix_features       = nv_fix_features,
5571         .ndo_set_features       = nv_set_features,
5572         .ndo_validate_addr      = eth_validate_addr,
5573         .ndo_set_mac_address    = nv_set_mac_address,
5574         .ndo_set_rx_mode        = nv_set_multicast,
5575 #ifdef CONFIG_NET_POLL_CONTROLLER
5576         .ndo_poll_controller    = nv_poll_controller,
5577 #endif
5578 };
5579
5580 static const struct net_device_ops nv_netdev_ops_optimized = {
5581         .ndo_open               = nv_open,
5582         .ndo_stop               = nv_close,
5583         .ndo_get_stats64        = nv_get_stats64,
5584         .ndo_start_xmit         = nv_start_xmit_optimized,
5585         .ndo_tx_timeout         = nv_tx_timeout,
5586         .ndo_change_mtu         = nv_change_mtu,
5587         .ndo_fix_features       = nv_fix_features,
5588         .ndo_set_features       = nv_set_features,
5589         .ndo_validate_addr      = eth_validate_addr,
5590         .ndo_set_mac_address    = nv_set_mac_address,
5591         .ndo_set_rx_mode        = nv_set_multicast,
5592 #ifdef CONFIG_NET_POLL_CONTROLLER
5593         .ndo_poll_controller    = nv_poll_controller,
5594 #endif
5595 };
5596
5597 static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5598 {
5599         struct net_device *dev;
5600         struct fe_priv *np;
5601         unsigned long addr;
5602         u8 __iomem *base;
5603         int err, i;
5604         u32 powerstate, txreg;
5605         u32 phystate_orig = 0, phystate;
5606         int phyinitialized = 0;
5607         static int printed_version;
5608
5609         if (!printed_version++)
5610                 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5611                         FORCEDETH_VERSION);
5612
5613         dev = alloc_etherdev(sizeof(struct fe_priv));
5614         err = -ENOMEM;
5615         if (!dev)
5616                 goto out;
5617
5618         np = netdev_priv(dev);
5619         np->dev = dev;
5620         np->pci_dev = pci_dev;
5621         spin_lock_init(&np->lock);
5622         spin_lock_init(&np->hwstats_lock);
5623         SET_NETDEV_DEV(dev, &pci_dev->dev);
5624         u64_stats_init(&np->swstats_rx_syncp);
5625         u64_stats_init(&np->swstats_tx_syncp);
5626
5627         init_timer(&np->oom_kick);
5628         np->oom_kick.data = (unsigned long) dev;
5629         np->oom_kick.function = nv_do_rx_refill;        /* timer handler */
5630         init_timer(&np->nic_poll);
5631         np->nic_poll.data = (unsigned long) dev;
5632         np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5633         init_timer_deferrable(&np->stats_poll);
5634         np->stats_poll.data = (unsigned long) dev;
5635         np->stats_poll.function = nv_do_stats_poll;     /* timer handler */
5636
5637         err = pci_enable_device(pci_dev);
5638         if (err)
5639                 goto out_free;
5640
5641         pci_set_master(pci_dev);
5642
5643         err = pci_request_regions(pci_dev, DRV_NAME);
5644         if (err < 0)
5645                 goto out_disable;
5646
5647         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5648                 np->register_size = NV_PCI_REGSZ_VER3;
5649         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5650                 np->register_size = NV_PCI_REGSZ_VER2;
5651         else
5652                 np->register_size = NV_PCI_REGSZ_VER1;
5653
5654         err = -EINVAL;
5655         addr = 0;
5656         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5657                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5658                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5659                         addr = pci_resource_start(pci_dev, i);
5660                         break;
5661                 }
5662         }
5663         if (i == DEVICE_COUNT_RESOURCE) {
5664                 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5665                 goto out_relreg;
5666         }
5667
5668         /* copy of driver data */
5669         np->driver_data = id->driver_data;
5670         /* copy of device id */
5671         np->device_id = id->device;
5672
5673         /* handle different descriptor versions */
5674         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5675                 /* packet format 3: supports 40-bit addressing */
5676                 np->desc_ver = DESC_VER_3;
5677                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5678                 if (dma_64bit) {
5679                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5680                                 dev_info(&pci_dev->dev,
5681                                          "64-bit DMA failed, using 32-bit addressing\n");
5682                         else
5683                                 dev->features |= NETIF_F_HIGHDMA;
5684                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5685                                 dev_info(&pci_dev->dev,
5686                                          "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5687                         }
5688                 }
5689         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5690                 /* packet format 2: supports jumbo frames */
5691                 np->desc_ver = DESC_VER_2;
5692                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5693         } else {
5694                 /* original packet format */
5695                 np->desc_ver = DESC_VER_1;
5696                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5697         }
5698
5699         np->pkt_limit = NV_PKTLIMIT_1;
5700         if (id->driver_data & DEV_HAS_LARGEDESC)
5701                 np->pkt_limit = NV_PKTLIMIT_2;
5702
5703         if (id->driver_data & DEV_HAS_CHECKSUM) {
5704                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5705                 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5706                         NETIF_F_TSO | NETIF_F_RXCSUM;
5707         }
5708
5709         np->vlanctl_bits = 0;
5710         if (id->driver_data & DEV_HAS_VLAN) {
5711                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5712                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
5713                                     NETIF_F_HW_VLAN_CTAG_TX;
5714         }
5715
5716         dev->features |= dev->hw_features;
5717
5718         /* Add loopback capability to the device. */
5719         dev->hw_features |= NETIF_F_LOOPBACK;
5720
5721         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5722         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5723             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5724             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5725                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5726         }
5727
5728         err = -ENOMEM;
5729         np->base = ioremap(addr, np->register_size);
5730         if (!np->base)
5731                 goto out_relreg;
5732
5733         np->rx_ring_size = RX_RING_DEFAULT;
5734         np->tx_ring_size = TX_RING_DEFAULT;
5735
5736         if (!nv_optimized(np)) {
5737                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5738                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5739                                         &np->ring_addr);
5740                 if (!np->rx_ring.orig)
5741                         goto out_unmap;
5742                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5743         } else {
5744                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5745                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5746                                         &np->ring_addr);
5747                 if (!np->rx_ring.ex)
5748                         goto out_unmap;
5749                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5750         }
5751         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5752         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5753         if (!np->rx_skb || !np->tx_skb)
5754                 goto out_freering;
5755
5756         if (!nv_optimized(np))
5757                 dev->netdev_ops = &nv_netdev_ops;
5758         else
5759                 dev->netdev_ops = &nv_netdev_ops_optimized;
5760
5761         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5762         SET_ETHTOOL_OPS(dev, &ops);
5763         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5764
5765         pci_set_drvdata(pci_dev, dev);
5766
5767         /* read the mac address */
5768         base = get_hwbase(dev);
5769         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5770         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5771
5772         /* check the workaround bit for correct mac address order */
5773         txreg = readl(base + NvRegTransmitPoll);
5774         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5775                 /* mac address is already in correct order */
5776                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5777                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5778                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5779                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5780                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5781                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5782         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5783                 /* mac address is already in correct order */
5784                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5785                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5786                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5787                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5788                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5789                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5790                 /*
5791                  * Set orig mac address back to the reversed version.
5792                  * This flag will be cleared during low power transition.
5793                  * Therefore, we should always put back the reversed address.
5794                  */
5795                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5796                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5797                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5798         } else {
5799                 /* need to reverse mac address to correct order */
5800                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5801                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5802                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5803                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5804                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5805                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5806                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5807                 dev_dbg(&pci_dev->dev,
5808                         "%s: set workaround bit for reversed mac addr\n",
5809                         __func__);
5810         }
5811
5812         if (!is_valid_ether_addr(dev->dev_addr)) {
5813                 /*
5814                  * Bad mac address. At least one bios sets the mac address
5815                  * to 01:23:45:67:89:ab
5816                  */
5817                 dev_err(&pci_dev->dev,
5818                         "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5819                         dev->dev_addr);
5820                 eth_hw_addr_random(dev);
5821                 dev_err(&pci_dev->dev,
5822                         "Using random MAC address: %pM\n", dev->dev_addr);
5823         }
5824
5825         /* set mac address */
5826         nv_copy_mac_to_hw(dev);
5827
5828         /* disable WOL */
5829         writel(0, base + NvRegWakeUpFlags);
5830         np->wolenabled = 0;
5831         device_set_wakeup_enable(&pci_dev->dev, false);
5832
5833         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5834
5835                 /* take phy and nic out of low power mode */
5836                 powerstate = readl(base + NvRegPowerState2);
5837                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5838                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5839                     pci_dev->revision >= 0xA3)
5840                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5841                 writel(powerstate, base + NvRegPowerState2);
5842         }
5843
5844         if (np->desc_ver == DESC_VER_1)
5845                 np->tx_flags = NV_TX_VALID;
5846         else
5847                 np->tx_flags = NV_TX2_VALID;
5848
5849         np->msi_flags = 0;
5850         if ((id->driver_data & DEV_HAS_MSI) && msi)
5851                 np->msi_flags |= NV_MSI_CAPABLE;
5852
5853         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5854                 /* msix has had reported issues when modifying irqmask
5855                    as in the case of napi, therefore, disable for now
5856                 */
5857 #if 0
5858                 np->msi_flags |= NV_MSI_X_CAPABLE;
5859 #endif
5860         }
5861
5862         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5863                 np->irqmask = NVREG_IRQMASK_CPU;
5864                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5865                         np->msi_flags |= 0x0001;
5866         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5867                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5868                 /* start off in throughput mode */
5869                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5870                 /* remove support for msix mode */
5871                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5872         } else {
5873                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5874                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5875                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5876                         np->msi_flags |= 0x0003;
5877         }
5878
5879         if (id->driver_data & DEV_NEED_TIMERIRQ)
5880                 np->irqmask |= NVREG_IRQ_TIMER;
5881         if (id->driver_data & DEV_NEED_LINKTIMER) {
5882                 np->need_linktimer = 1;
5883                 np->link_timeout = jiffies + LINK_TIMEOUT;
5884         } else {
5885                 np->need_linktimer = 0;
5886         }
5887
5888         /* Limit the number of tx's outstanding for hw bug */
5889         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5890                 np->tx_limit = 1;
5891                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5892                     pci_dev->revision >= 0xA2)
5893                         np->tx_limit = 0;
5894         }
5895
5896         /* clear phy state and temporarily halt phy interrupts */
5897         writel(0, base + NvRegMIIMask);
5898         phystate = readl(base + NvRegAdapterControl);
5899         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5900                 phystate_orig = 1;
5901                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5902                 writel(phystate, base + NvRegAdapterControl);
5903         }
5904         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5905
5906         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5907                 /* management unit running on the mac? */
5908                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5909                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5910                     nv_mgmt_acquire_sema(dev) &&
5911                     nv_mgmt_get_version(dev)) {
5912                         np->mac_in_use = 1;
5913                         if (np->mgmt_version > 0)
5914                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5915                         /* management unit setup the phy already? */
5916                         if (np->mac_in_use &&
5917                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5918                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5919                                 /* phy is inited by mgmt unit */
5920                                 phyinitialized = 1;
5921                         } else {
5922                                 /* we need to init the phy */
5923                         }
5924                 }
5925         }
5926
5927         /* find a suitable phy */
5928         for (i = 1; i <= 32; i++) {
5929                 int id1, id2;
5930                 int phyaddr = i & 0x1F;
5931
5932                 spin_lock_irq(&np->lock);
5933                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5934                 spin_unlock_irq(&np->lock);
5935                 if (id1 < 0 || id1 == 0xffff)
5936                         continue;
5937                 spin_lock_irq(&np->lock);
5938                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5939                 spin_unlock_irq(&np->lock);
5940                 if (id2 < 0 || id2 == 0xffff)
5941                         continue;
5942
5943                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5944                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5945                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5946                 np->phyaddr = phyaddr;
5947                 np->phy_oui = id1 | id2;
5948
5949                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5950                 if (np->phy_oui == PHY_OUI_REALTEK2)
5951                         np->phy_oui = PHY_OUI_REALTEK;
5952                 /* Setup phy revision for Realtek */
5953                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5954                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5955
5956                 break;
5957         }
5958         if (i == 33) {
5959                 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5960                 goto out_error;
5961         }
5962
5963         if (!phyinitialized) {
5964                 /* reset it */
5965                 phy_init(dev);
5966         } else {
5967                 /* see if it is a gigabit phy */
5968                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5969                 if (mii_status & PHY_GIGABIT)
5970                         np->gigabit = PHY_GIGABIT;
5971         }
5972
5973         /* set default link speed settings */
5974         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5975         np->duplex = 0;
5976         np->autoneg = 1;
5977
5978         err = register_netdev(dev);
5979         if (err) {
5980                 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5981                 goto out_error;
5982         }
5983
5984         netif_carrier_off(dev);
5985
5986         /* Some NICs freeze when TX pause is enabled while NIC is
5987          * down, and this stays across warm reboots. The sequence
5988          * below should be enough to recover from that state.
5989          */
5990         nv_update_pause(dev, 0);
5991         nv_start_tx(dev);
5992         nv_stop_tx(dev);
5993
5994         if (id->driver_data & DEV_HAS_VLAN)
5995                 nv_vlan_mode(dev, dev->features);
5996
5997         dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5998                  dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5999
6000         dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6001                  dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6002                  dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6003                         "csum " : "",
6004                  dev->features & (NETIF_F_HW_VLAN_CTAG_RX |
6005                                   NETIF_F_HW_VLAN_CTAG_TX) ?
6006                         "vlan " : "",
6007                  dev->features & (NETIF_F_LOOPBACK) ?
6008                         "loopback " : "",
6009                  id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6010                  id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6011                  id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6012                  np->gigabit == PHY_GIGABIT ? "gbit " : "",
6013                  np->need_linktimer ? "lnktim " : "",
6014                  np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6015                  np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6016                  np->desc_ver);
6017
6018         return 0;
6019
6020 out_error:
6021         if (phystate_orig)
6022                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6023         pci_set_drvdata(pci_dev, NULL);
6024 out_freering:
6025         free_rings(dev);
6026 out_unmap:
6027         iounmap(get_hwbase(dev));
6028 out_relreg:
6029         pci_release_regions(pci_dev);
6030 out_disable:
6031         pci_disable_device(pci_dev);
6032 out_free:
6033         free_netdev(dev);
6034 out:
6035         return err;
6036 }
6037
6038 static void nv_restore_phy(struct net_device *dev)
6039 {
6040         struct fe_priv *np = netdev_priv(dev);
6041         u16 phy_reserved, mii_control;
6042
6043         if (np->phy_oui == PHY_OUI_REALTEK &&
6044             np->phy_model == PHY_MODEL_REALTEK_8201 &&
6045             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6046                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6047                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6048                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6049                 phy_reserved |= PHY_REALTEK_INIT8;
6050                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6051                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6052
6053                 /* restart auto negotiation */
6054                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6055                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6056                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6057         }
6058 }
6059
6060 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6061 {
6062         struct net_device *dev = pci_get_drvdata(pci_dev);
6063         struct fe_priv *np = netdev_priv(dev);
6064         u8 __iomem *base = get_hwbase(dev);
6065
6066         /* special op: write back the misordered MAC address - otherwise
6067          * the next nv_probe would see a wrong address.
6068          */
6069         writel(np->orig_mac[0], base + NvRegMacAddrA);
6070         writel(np->orig_mac[1], base + NvRegMacAddrB);
6071         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6072                base + NvRegTransmitPoll);
6073 }
6074
6075 static void nv_remove(struct pci_dev *pci_dev)
6076 {
6077         struct net_device *dev = pci_get_drvdata(pci_dev);
6078
6079         unregister_netdev(dev);
6080
6081         nv_restore_mac_addr(pci_dev);
6082
6083         /* restore any phy related changes */
6084         nv_restore_phy(dev);
6085
6086         nv_mgmt_release_sema(dev);
6087
6088         /* free all structures */
6089         free_rings(dev);
6090         iounmap(get_hwbase(dev));
6091         pci_release_regions(pci_dev);
6092         pci_disable_device(pci_dev);
6093         free_netdev(dev);
6094         pci_set_drvdata(pci_dev, NULL);
6095 }
6096
6097 #ifdef CONFIG_PM_SLEEP
6098 static int nv_suspend(struct device *device)
6099 {
6100         struct pci_dev *pdev = to_pci_dev(device);
6101         struct net_device *dev = pci_get_drvdata(pdev);
6102         struct fe_priv *np = netdev_priv(dev);
6103         u8 __iomem *base = get_hwbase(dev);
6104         int i;
6105
6106         if (netif_running(dev)) {
6107                 /* Gross. */
6108                 nv_close(dev);
6109         }
6110         netif_device_detach(dev);
6111
6112         /* save non-pci configuration space */
6113         for (i = 0; i <= np->register_size/sizeof(u32); i++)
6114                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6115
6116         return 0;
6117 }
6118
6119 static int nv_resume(struct device *device)
6120 {
6121         struct pci_dev *pdev = to_pci_dev(device);
6122         struct net_device *dev = pci_get_drvdata(pdev);
6123         struct fe_priv *np = netdev_priv(dev);
6124         u8 __iomem *base = get_hwbase(dev);
6125         int i, rc = 0;
6126
6127         /* restore non-pci configuration space */
6128         for (i = 0; i <= np->register_size/sizeof(u32); i++)
6129                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6130
6131         if (np->driver_data & DEV_NEED_MSI_FIX)
6132                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6133
6134         /* restore phy state, including autoneg */
6135         phy_init(dev);
6136
6137         netif_device_attach(dev);
6138         if (netif_running(dev)) {
6139                 rc = nv_open(dev);
6140                 nv_set_multicast(dev);
6141         }
6142         return rc;
6143 }
6144
6145 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6146 #define NV_PM_OPS (&nv_pm_ops)
6147
6148 #else
6149 #define NV_PM_OPS NULL
6150 #endif /* CONFIG_PM_SLEEP */
6151
6152 #ifdef CONFIG_PM
6153 static void nv_shutdown(struct pci_dev *pdev)
6154 {
6155         struct net_device *dev = pci_get_drvdata(pdev);
6156         struct fe_priv *np = netdev_priv(dev);
6157
6158         if (netif_running(dev))
6159                 nv_close(dev);
6160
6161         /*
6162          * Restore the MAC so a kernel started by kexec won't get confused.
6163          * If we really go for poweroff, we must not restore the MAC,
6164          * otherwise the MAC for WOL will be reversed at least on some boards.
6165          */
6166         if (system_state != SYSTEM_POWER_OFF)
6167                 nv_restore_mac_addr(pdev);
6168
6169         pci_disable_device(pdev);
6170         /*
6171          * Apparently it is not possible to reinitialise from D3 hot,
6172          * only put the device into D3 if we really go for poweroff.
6173          */
6174         if (system_state == SYSTEM_POWER_OFF) {
6175                 pci_wake_from_d3(pdev, np->wolenabled);
6176                 pci_set_power_state(pdev, PCI_D3hot);
6177         }
6178 }
6179 #else
6180 #define nv_shutdown NULL
6181 #endif /* CONFIG_PM */
6182
6183 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6184         {       /* nForce Ethernet Controller */
6185                 PCI_DEVICE(0x10DE, 0x01C3),
6186                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6187         },
6188         {       /* nForce2 Ethernet Controller */
6189                 PCI_DEVICE(0x10DE, 0x0066),
6190                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6191         },
6192         {       /* nForce3 Ethernet Controller */
6193                 PCI_DEVICE(0x10DE, 0x00D6),
6194                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6195         },
6196         {       /* nForce3 Ethernet Controller */
6197                 PCI_DEVICE(0x10DE, 0x0086),
6198                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6199         },
6200         {       /* nForce3 Ethernet Controller */
6201                 PCI_DEVICE(0x10DE, 0x008C),
6202                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6203         },
6204         {       /* nForce3 Ethernet Controller */
6205                 PCI_DEVICE(0x10DE, 0x00E6),
6206                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6207         },
6208         {       /* nForce3 Ethernet Controller */
6209                 PCI_DEVICE(0x10DE, 0x00DF),
6210                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6211         },
6212         {       /* CK804 Ethernet Controller */
6213                 PCI_DEVICE(0x10DE, 0x0056),
6214                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6215         },
6216         {       /* CK804 Ethernet Controller */
6217                 PCI_DEVICE(0x10DE, 0x0057),
6218                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6219         },
6220         {       /* MCP04 Ethernet Controller */
6221                 PCI_DEVICE(0x10DE, 0x0037),
6222                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6223         },
6224         {       /* MCP04 Ethernet Controller */
6225                 PCI_DEVICE(0x10DE, 0x0038),
6226                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6227         },
6228         {       /* MCP51 Ethernet Controller */
6229                 PCI_DEVICE(0x10DE, 0x0268),
6230                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6231         },
6232         {       /* MCP51 Ethernet Controller */
6233                 PCI_DEVICE(0x10DE, 0x0269),
6234                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6235         },
6236         {       /* MCP55 Ethernet Controller */
6237                 PCI_DEVICE(0x10DE, 0x0372),
6238                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6239         },
6240         {       /* MCP55 Ethernet Controller */
6241                 PCI_DEVICE(0x10DE, 0x0373),
6242                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6243         },
6244         {       /* MCP61 Ethernet Controller */
6245                 PCI_DEVICE(0x10DE, 0x03E5),
6246                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6247         },
6248         {       /* MCP61 Ethernet Controller */
6249                 PCI_DEVICE(0x10DE, 0x03E6),
6250                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6251         },
6252         {       /* MCP61 Ethernet Controller */
6253                 PCI_DEVICE(0x10DE, 0x03EE),
6254                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6255         },
6256         {       /* MCP61 Ethernet Controller */
6257                 PCI_DEVICE(0x10DE, 0x03EF),
6258                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6259         },
6260         {       /* MCP65 Ethernet Controller */
6261                 PCI_DEVICE(0x10DE, 0x0450),
6262                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6263         },
6264         {       /* MCP65 Ethernet Controller */
6265                 PCI_DEVICE(0x10DE, 0x0451),
6266                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6267         },
6268         {       /* MCP65 Ethernet Controller */
6269                 PCI_DEVICE(0x10DE, 0x0452),
6270                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6271         },
6272         {       /* MCP65 Ethernet Controller */
6273                 PCI_DEVICE(0x10DE, 0x0453),
6274                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6275         },
6276         {       /* MCP67 Ethernet Controller */
6277                 PCI_DEVICE(0x10DE, 0x054C),
6278                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6279         },
6280         {       /* MCP67 Ethernet Controller */
6281                 PCI_DEVICE(0x10DE, 0x054D),
6282                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6283         },
6284         {       /* MCP67 Ethernet Controller */
6285                 PCI_DEVICE(0x10DE, 0x054E),
6286                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6287         },
6288         {       /* MCP67 Ethernet Controller */
6289                 PCI_DEVICE(0x10DE, 0x054F),
6290                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6291         },
6292         {       /* MCP73 Ethernet Controller */
6293                 PCI_DEVICE(0x10DE, 0x07DC),
6294                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6295         },
6296         {       /* MCP73 Ethernet Controller */
6297                 PCI_DEVICE(0x10DE, 0x07DD),
6298                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6299         },
6300         {       /* MCP73 Ethernet Controller */
6301                 PCI_DEVICE(0x10DE, 0x07DE),
6302                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6303         },
6304         {       /* MCP73 Ethernet Controller */
6305                 PCI_DEVICE(0x10DE, 0x07DF),
6306                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6307         },
6308         {       /* MCP77 Ethernet Controller */
6309                 PCI_DEVICE(0x10DE, 0x0760),
6310                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6311         },
6312         {       /* MCP77 Ethernet Controller */
6313                 PCI_DEVICE(0x10DE, 0x0761),
6314                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6315         },
6316         {       /* MCP77 Ethernet Controller */
6317                 PCI_DEVICE(0x10DE, 0x0762),
6318                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6319         },
6320         {       /* MCP77 Ethernet Controller */
6321                 PCI_DEVICE(0x10DE, 0x0763),
6322                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6323         },
6324         {       /* MCP79 Ethernet Controller */
6325                 PCI_DEVICE(0x10DE, 0x0AB0),
6326                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6327         },
6328         {       /* MCP79 Ethernet Controller */
6329                 PCI_DEVICE(0x10DE, 0x0AB1),
6330                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6331         },
6332         {       /* MCP79 Ethernet Controller */
6333                 PCI_DEVICE(0x10DE, 0x0AB2),
6334                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6335         },
6336         {       /* MCP79 Ethernet Controller */
6337                 PCI_DEVICE(0x10DE, 0x0AB3),
6338                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6339         },
6340         {       /* MCP89 Ethernet Controller */
6341                 PCI_DEVICE(0x10DE, 0x0D7D),
6342                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6343         },
6344         {0,},
6345 };
6346
6347 static struct pci_driver forcedeth_pci_driver = {
6348         .name           = DRV_NAME,
6349         .id_table       = pci_tbl,
6350         .probe          = nv_probe,
6351         .remove         = nv_remove,
6352         .shutdown       = nv_shutdown,
6353         .driver.pm      = NV_PM_OPS,
6354 };
6355
6356 module_param(max_interrupt_work, int, 0);
6357 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6358 module_param(optimization_mode, int, 0);
6359 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6360 module_param(poll_interval, int, 0);
6361 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6362 module_param(msi, int, 0);
6363 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6364 module_param(msix, int, 0);
6365 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6366 module_param(dma_64bit, int, 0);
6367 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6368 module_param(phy_cross, int, 0);
6369 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6370 module_param(phy_power_down, int, 0);
6371 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6372 module_param(debug_tx_timeout, bool, 0);
6373 MODULE_PARM_DESC(debug_tx_timeout,
6374                  "Dump tx related registers and ring when tx_timeout happens");
6375
6376 module_pci_driver(forcedeth_pci_driver);
6377 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6378 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6379 MODULE_LICENSE("GPL");
6380 MODULE_DEVICE_TABLE(pci, pci_tbl);