2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/prefetch.h>
68 #include <linux/u64_stats_sync.h>
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
80 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
92 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
93 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
94 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
95 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
96 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
97 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
98 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
99 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
100 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
101 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
102 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
103 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
104 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
105 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
106 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
109 NvRegIrqStatus = 0x000,
110 #define NVREG_IRQSTAT_MIIEVENT 0x040
111 #define NVREG_IRQSTAT_MASK 0x83ff
112 NvRegIrqMask = 0x004,
113 #define NVREG_IRQ_RX_ERROR 0x0001
114 #define NVREG_IRQ_RX 0x0002
115 #define NVREG_IRQ_RX_NOBUF 0x0004
116 #define NVREG_IRQ_TX_ERR 0x0008
117 #define NVREG_IRQ_TX_OK 0x0010
118 #define NVREG_IRQ_TIMER 0x0020
119 #define NVREG_IRQ_LINK 0x0040
120 #define NVREG_IRQ_RX_FORCED 0x0080
121 #define NVREG_IRQ_TX_FORCED 0x0100
122 #define NVREG_IRQ_RECOVER_ERROR 0x8200
123 #define NVREG_IRQMASK_THROUGHPUT 0x00df
124 #define NVREG_IRQMASK_CPU 0x0060
125 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
126 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
127 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
129 NvRegUnknownSetupReg6 = 0x008,
130 #define NVREG_UNKSETUP6_VAL 3
133 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
134 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
136 NvRegPollingInterval = 0x00c,
137 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
138 #define NVREG_POLL_DEFAULT_CPU 13
139 NvRegMSIMap0 = 0x020,
140 NvRegMSIMap1 = 0x024,
141 NvRegMSIIrqMask = 0x030,
142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
144 #define NVREG_MISC1_PAUSE_TX 0x01
145 #define NVREG_MISC1_HD 0x02
146 #define NVREG_MISC1_FORCE 0x3b0f3c
148 NvRegMacReset = 0x34,
149 #define NVREG_MAC_RESET_ASSERT 0x0F3
150 NvRegTransmitterControl = 0x084,
151 #define NVREG_XMITCTL_START 0x01
152 #define NVREG_XMITCTL_MGMT_ST 0x40000000
153 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
154 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
155 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
156 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
157 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
158 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
159 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
160 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
161 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
162 #define NVREG_XMITCTL_DATA_START 0x00100000
163 #define NVREG_XMITCTL_DATA_READY 0x00010000
164 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
165 NvRegTransmitterStatus = 0x088,
166 #define NVREG_XMITSTAT_BUSY 0x01
168 NvRegPacketFilterFlags = 0x8c,
169 #define NVREG_PFF_PAUSE_RX 0x08
170 #define NVREG_PFF_ALWAYS 0x7F0000
171 #define NVREG_PFF_PROMISC 0x80
172 #define NVREG_PFF_MYADDR 0x20
173 #define NVREG_PFF_LOOPBACK 0x10
175 NvRegOffloadConfig = 0x90,
176 #define NVREG_OFFLOAD_HOMEPHY 0x601
177 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
178 NvRegReceiverControl = 0x094,
179 #define NVREG_RCVCTL_START 0x01
180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
181 NvRegReceiverStatus = 0x98,
182 #define NVREG_RCVSTAT_BUSY 0x01
184 NvRegSlotTime = 0x9c,
185 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
186 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
187 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
188 #define NVREG_SLOTTIME_HALF 0x0000ff00
189 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
190 #define NVREG_SLOTTIME_MASK 0x000000ff
192 NvRegTxDeferral = 0xA0,
193 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
194 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
195 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
198 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
199 NvRegRxDeferral = 0xA4,
200 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
201 NvRegMacAddrA = 0xA8,
202 NvRegMacAddrB = 0xAC,
203 NvRegMulticastAddrA = 0xB0,
204 #define NVREG_MCASTADDRA_FORCE 0x01
205 NvRegMulticastAddrB = 0xB4,
206 NvRegMulticastMaskA = 0xB8,
207 #define NVREG_MCASTMASKA_NONE 0xffffffff
208 NvRegMulticastMaskB = 0xBC,
209 #define NVREG_MCASTMASKB_NONE 0xffff
211 NvRegPhyInterface = 0xC0,
212 #define PHY_RGMII 0x10000000
213 NvRegBackOffControl = 0xC4,
214 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
215 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
216 #define NVREG_BKOFFCTRL_SELECT 24
217 #define NVREG_BKOFFCTRL_GEAR 12
219 NvRegTxRingPhysAddr = 0x100,
220 NvRegRxRingPhysAddr = 0x104,
221 NvRegRingSizes = 0x108,
222 #define NVREG_RINGSZ_TXSHIFT 0
223 #define NVREG_RINGSZ_RXSHIFT 16
224 NvRegTransmitPoll = 0x10c,
225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
226 NvRegLinkSpeed = 0x110,
227 #define NVREG_LINKSPEED_FORCE 0x10000
228 #define NVREG_LINKSPEED_10 1000
229 #define NVREG_LINKSPEED_100 100
230 #define NVREG_LINKSPEED_1000 50
231 #define NVREG_LINKSPEED_MASK (0xFFF)
232 NvRegUnknownSetupReg5 = 0x130,
233 #define NVREG_UNKSETUP5_BIT31 (1<<31)
234 NvRegTxWatermark = 0x13c,
235 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
236 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
237 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
238 NvRegTxRxControl = 0x144,
239 #define NVREG_TXRXCTL_KICK 0x0001
240 #define NVREG_TXRXCTL_BIT1 0x0002
241 #define NVREG_TXRXCTL_BIT2 0x0004
242 #define NVREG_TXRXCTL_IDLE 0x0008
243 #define NVREG_TXRXCTL_RESET 0x0010
244 #define NVREG_TXRXCTL_RXCHECK 0x0400
245 #define NVREG_TXRXCTL_DESC_1 0
246 #define NVREG_TXRXCTL_DESC_2 0x002100
247 #define NVREG_TXRXCTL_DESC_3 0xc02200
248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
249 #define NVREG_TXRXCTL_VLANINS 0x00080
250 NvRegTxRingPhysAddrHigh = 0x148,
251 NvRegRxRingPhysAddrHigh = 0x14C,
252 NvRegTxPauseFrame = 0x170,
253 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
257 NvRegTxPauseFrameLimit = 0x174,
258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
259 NvRegMIIStatus = 0x180,
260 #define NVREG_MIISTAT_ERROR 0x0001
261 #define NVREG_MIISTAT_LINKCHANGE 0x0008
262 #define NVREG_MIISTAT_MASK_RW 0x0007
263 #define NVREG_MIISTAT_MASK_ALL 0x000f
264 NvRegMIIMask = 0x184,
265 #define NVREG_MII_LINKCHANGE 0x0008
267 NvRegAdapterControl = 0x188,
268 #define NVREG_ADAPTCTL_START 0x02
269 #define NVREG_ADAPTCTL_LINKUP 0x04
270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
271 #define NVREG_ADAPTCTL_RUNNING 0x100000
272 #define NVREG_ADAPTCTL_PHYSHIFT 24
273 NvRegMIISpeed = 0x18c,
274 #define NVREG_MIISPEED_BIT8 (1<<8)
275 #define NVREG_MIIDELAY 5
276 NvRegMIIControl = 0x190,
277 #define NVREG_MIICTL_INUSE 0x08000
278 #define NVREG_MIICTL_WRITE 0x00400
279 #define NVREG_MIICTL_ADDRSHIFT 5
280 NvRegMIIData = 0x194,
281 NvRegTxUnicast = 0x1a0,
282 NvRegTxMulticast = 0x1a4,
283 NvRegTxBroadcast = 0x1a8,
284 NvRegWakeUpFlags = 0x200,
285 #define NVREG_WAKEUPFLAGS_VAL 0x7770
286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
288 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
289 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
290 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
291 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
295 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
297 NvRegMgmtUnitGetVersion = 0x204,
298 #define NVREG_MGMTUNITGETVERSION 0x01
299 NvRegMgmtUnitVersion = 0x208,
300 #define NVREG_MGMTUNITVERSION 0x08
301 NvRegPowerCap = 0x268,
302 #define NVREG_POWERCAP_D3SUPP (1<<30)
303 #define NVREG_POWERCAP_D2SUPP (1<<26)
304 #define NVREG_POWERCAP_D1SUPP (1<<25)
305 NvRegPowerState = 0x26c,
306 #define NVREG_POWERSTATE_POWEREDUP 0x8000
307 #define NVREG_POWERSTATE_VALID 0x0100
308 #define NVREG_POWERSTATE_MASK 0x0003
309 #define NVREG_POWERSTATE_D0 0x0000
310 #define NVREG_POWERSTATE_D1 0x0001
311 #define NVREG_POWERSTATE_D2 0x0002
312 #define NVREG_POWERSTATE_D3 0x0003
313 NvRegMgmtUnitControl = 0x278,
314 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
316 NvRegTxZeroReXmt = 0x284,
317 NvRegTxOneReXmt = 0x288,
318 NvRegTxManyReXmt = 0x28c,
319 NvRegTxLateCol = 0x290,
320 NvRegTxUnderflow = 0x294,
321 NvRegTxLossCarrier = 0x298,
322 NvRegTxExcessDef = 0x29c,
323 NvRegTxRetryErr = 0x2a0,
324 NvRegRxFrameErr = 0x2a4,
325 NvRegRxExtraByte = 0x2a8,
326 NvRegRxLateCol = 0x2ac,
328 NvRegRxFrameTooLong = 0x2b4,
329 NvRegRxOverflow = 0x2b8,
330 NvRegRxFCSErr = 0x2bc,
331 NvRegRxFrameAlignErr = 0x2c0,
332 NvRegRxLenErr = 0x2c4,
333 NvRegRxUnicast = 0x2c8,
334 NvRegRxMulticast = 0x2cc,
335 NvRegRxBroadcast = 0x2d0,
337 NvRegTxFrame = 0x2d8,
339 NvRegTxPause = 0x2e0,
340 NvRegRxPause = 0x2e4,
341 NvRegRxDropFrame = 0x2e8,
342 NvRegVlanControl = 0x300,
343 #define NVREG_VLANCONTROL_ENABLE 0x2000
344 NvRegMSIXMap0 = 0x3e0,
345 NvRegMSIXMap1 = 0x3e4,
346 NvRegMSIXIrqStatus = 0x3f0,
348 NvRegPowerState2 = 0x600,
349 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
350 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
351 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
352 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
355 /* Big endian: should work, but is untested */
361 struct ring_desc_ex {
369 struct ring_desc *orig;
370 struct ring_desc_ex *ex;
373 #define FLAG_MASK_V1 0xffff0000
374 #define FLAG_MASK_V2 0xffffc000
375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
378 #define NV_TX_LASTPACKET (1<<16)
379 #define NV_TX_RETRYERROR (1<<19)
380 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
381 #define NV_TX_FORCED_INTERRUPT (1<<24)
382 #define NV_TX_DEFERRED (1<<26)
383 #define NV_TX_CARRIERLOST (1<<27)
384 #define NV_TX_LATECOLLISION (1<<28)
385 #define NV_TX_UNDERFLOW (1<<29)
386 #define NV_TX_ERROR (1<<30)
387 #define NV_TX_VALID (1<<31)
389 #define NV_TX2_LASTPACKET (1<<29)
390 #define NV_TX2_RETRYERROR (1<<18)
391 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
393 #define NV_TX2_DEFERRED (1<<25)
394 #define NV_TX2_CARRIERLOST (1<<26)
395 #define NV_TX2_LATECOLLISION (1<<27)
396 #define NV_TX2_UNDERFLOW (1<<28)
397 /* error and valid are the same for both */
398 #define NV_TX2_ERROR (1<<30)
399 #define NV_TX2_VALID (1<<31)
400 #define NV_TX2_TSO (1<<28)
401 #define NV_TX2_TSO_SHIFT 14
402 #define NV_TX2_TSO_MAX_SHIFT 14
403 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
404 #define NV_TX2_CHECKSUM_L3 (1<<27)
405 #define NV_TX2_CHECKSUM_L4 (1<<26)
407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
409 #define NV_RX_DESCRIPTORVALID (1<<16)
410 #define NV_RX_MISSEDFRAME (1<<17)
411 #define NV_RX_SUBSTRACT1 (1<<18)
412 #define NV_RX_ERROR1 (1<<23)
413 #define NV_RX_ERROR2 (1<<24)
414 #define NV_RX_ERROR3 (1<<25)
415 #define NV_RX_ERROR4 (1<<26)
416 #define NV_RX_CRCERR (1<<27)
417 #define NV_RX_OVERFLOW (1<<28)
418 #define NV_RX_FRAMINGERR (1<<29)
419 #define NV_RX_ERROR (1<<30)
420 #define NV_RX_AVAIL (1<<31)
421 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
423 #define NV_RX2_CHECKSUMMASK (0x1C000000)
424 #define NV_RX2_CHECKSUM_IP (0x10000000)
425 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
426 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
427 #define NV_RX2_DESCRIPTORVALID (1<<29)
428 #define NV_RX2_SUBSTRACT1 (1<<25)
429 #define NV_RX2_ERROR1 (1<<18)
430 #define NV_RX2_ERROR2 (1<<19)
431 #define NV_RX2_ERROR3 (1<<20)
432 #define NV_RX2_ERROR4 (1<<21)
433 #define NV_RX2_CRCERR (1<<22)
434 #define NV_RX2_OVERFLOW (1<<23)
435 #define NV_RX2_FRAMINGERR (1<<24)
436 /* error and avail are the same for both */
437 #define NV_RX2_ERROR (1<<30)
438 #define NV_RX2_AVAIL (1<<31)
439 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
442 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
444 /* Miscellaneous hardware related defines: */
445 #define NV_PCI_REGSZ_VER1 0x270
446 #define NV_PCI_REGSZ_VER2 0x2d4
447 #define NV_PCI_REGSZ_VER3 0x604
448 #define NV_PCI_REGSZ_MAX 0x604
450 /* various timeout delays: all in usec */
451 #define NV_TXRX_RESET_DELAY 4
452 #define NV_TXSTOP_DELAY1 10
453 #define NV_TXSTOP_DELAY1MAX 500000
454 #define NV_TXSTOP_DELAY2 100
455 #define NV_RXSTOP_DELAY1 10
456 #define NV_RXSTOP_DELAY1MAX 500000
457 #define NV_RXSTOP_DELAY2 100
458 #define NV_SETUP5_DELAY 5
459 #define NV_SETUP5_DELAYMAX 50000
460 #define NV_POWERUP_DELAY 5
461 #define NV_POWERUP_DELAYMAX 5000
462 #define NV_MIIBUSY_DELAY 50
463 #define NV_MIIPHY_DELAY 10
464 #define NV_MIIPHY_DELAYMAX 10000
465 #define NV_MAC_RESET_DELAY 64
467 #define NV_WAKEUPPATTERNS 5
468 #define NV_WAKEUPMASKENTRIES 4
470 /* General driver defaults */
471 #define NV_WATCHDOG_TIMEO (5*HZ)
473 #define RX_RING_DEFAULT 512
474 #define TX_RING_DEFAULT 256
475 #define RX_RING_MIN 128
476 #define TX_RING_MIN 64
477 #define RING_MAX_DESC_VER_1 1024
478 #define RING_MAX_DESC_VER_2_3 16384
480 /* rx/tx mac addr + type + vlan + align + slack*/
481 #define NV_RX_HEADERS (64)
482 /* even more slack. */
483 #define NV_RX_ALLOC_PAD (64)
485 /* maximum mtu size */
486 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
487 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
489 #define OOM_REFILL (1+HZ/20)
490 #define POLL_WAIT (1+HZ/100)
491 #define LINK_TIMEOUT (3*HZ)
492 #define STATS_INTERVAL (10*HZ)
496 * The nic supports three different descriptor types:
497 * - DESC_VER_1: Original
498 * - DESC_VER_2: support for jumbo frames.
499 * - DESC_VER_3: 64-bit format.
506 #define PHY_OUI_MARVELL 0x5043
507 #define PHY_OUI_CICADA 0x03f1
508 #define PHY_OUI_VITESSE 0x01c1
509 #define PHY_OUI_REALTEK 0x0732
510 #define PHY_OUI_REALTEK2 0x0020
511 #define PHYID1_OUI_MASK 0x03ff
512 #define PHYID1_OUI_SHFT 6
513 #define PHYID2_OUI_MASK 0xfc00
514 #define PHYID2_OUI_SHFT 10
515 #define PHYID2_MODEL_MASK 0x03f0
516 #define PHY_MODEL_REALTEK_8211 0x0110
517 #define PHY_REV_MASK 0x0001
518 #define PHY_REV_REALTEK_8211B 0x0000
519 #define PHY_REV_REALTEK_8211C 0x0001
520 #define PHY_MODEL_REALTEK_8201 0x0200
521 #define PHY_MODEL_MARVELL_E3016 0x0220
522 #define PHY_MARVELL_E3016_INITMASK 0x0300
523 #define PHY_CICADA_INIT1 0x0f000
524 #define PHY_CICADA_INIT2 0x0e00
525 #define PHY_CICADA_INIT3 0x01000
526 #define PHY_CICADA_INIT4 0x0200
527 #define PHY_CICADA_INIT5 0x0004
528 #define PHY_CICADA_INIT6 0x02000
529 #define PHY_VITESSE_INIT_REG1 0x1f
530 #define PHY_VITESSE_INIT_REG2 0x10
531 #define PHY_VITESSE_INIT_REG3 0x11
532 #define PHY_VITESSE_INIT_REG4 0x12
533 #define PHY_VITESSE_INIT_MSK1 0xc
534 #define PHY_VITESSE_INIT_MSK2 0x0180
535 #define PHY_VITESSE_INIT1 0x52b5
536 #define PHY_VITESSE_INIT2 0xaf8a
537 #define PHY_VITESSE_INIT3 0x8
538 #define PHY_VITESSE_INIT4 0x8f8a
539 #define PHY_VITESSE_INIT5 0xaf86
540 #define PHY_VITESSE_INIT6 0x8f86
541 #define PHY_VITESSE_INIT7 0xaf82
542 #define PHY_VITESSE_INIT8 0x0100
543 #define PHY_VITESSE_INIT9 0x8f82
544 #define PHY_VITESSE_INIT10 0x0
545 #define PHY_REALTEK_INIT_REG1 0x1f
546 #define PHY_REALTEK_INIT_REG2 0x19
547 #define PHY_REALTEK_INIT_REG3 0x13
548 #define PHY_REALTEK_INIT_REG4 0x14
549 #define PHY_REALTEK_INIT_REG5 0x18
550 #define PHY_REALTEK_INIT_REG6 0x11
551 #define PHY_REALTEK_INIT_REG7 0x01
552 #define PHY_REALTEK_INIT1 0x0000
553 #define PHY_REALTEK_INIT2 0x8e00
554 #define PHY_REALTEK_INIT3 0x0001
555 #define PHY_REALTEK_INIT4 0xad17
556 #define PHY_REALTEK_INIT5 0xfb54
557 #define PHY_REALTEK_INIT6 0xf5c7
558 #define PHY_REALTEK_INIT7 0x1000
559 #define PHY_REALTEK_INIT8 0x0003
560 #define PHY_REALTEK_INIT9 0x0008
561 #define PHY_REALTEK_INIT10 0x0005
562 #define PHY_REALTEK_INIT11 0x0200
563 #define PHY_REALTEK_INIT_MSK1 0x0003
565 #define PHY_GIGABIT 0x0100
567 #define PHY_TIMEOUT 0x1
568 #define PHY_ERROR 0x2
572 #define PHY_HALF 0x100
574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
576 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
577 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
578 #define NV_PAUSEFRAME_RX_REQ 0x0010
579 #define NV_PAUSEFRAME_TX_REQ 0x0020
580 #define NV_PAUSEFRAME_AUTONEG 0x0040
582 /* MSI/MSI-X defines */
583 #define NV_MSI_X_MAX_VECTORS 8
584 #define NV_MSI_X_VECTORS_MASK 0x000f
585 #define NV_MSI_CAPABLE 0x0010
586 #define NV_MSI_X_CAPABLE 0x0020
587 #define NV_MSI_ENABLED 0x0040
588 #define NV_MSI_X_ENABLED 0x0080
590 #define NV_MSI_X_VECTOR_ALL 0x0
591 #define NV_MSI_X_VECTOR_RX 0x0
592 #define NV_MSI_X_VECTOR_TX 0x1
593 #define NV_MSI_X_VECTOR_OTHER 0x2
595 #define NV_MSI_PRIV_OFFSET 0x68
596 #define NV_MSI_PRIV_VALUE 0xffffffff
598 #define NV_RESTART_TX 0x1
599 #define NV_RESTART_RX 0x2
601 #define NV_TX_LIMIT_COUNT 16
603 #define NV_DYNAMIC_THRESHOLD 4
604 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
607 struct nv_ethtool_str {
608 char name[ETH_GSTRING_LEN];
611 static const struct nv_ethtool_str nv_estats_str[] = {
612 { "tx_bytes" }, /* includes Ethernet FCS CRC */
616 { "tx_late_collision" },
617 { "tx_fifo_errors" },
618 { "tx_carrier_errors" },
619 { "tx_excess_deferral" },
620 { "tx_retry_error" },
621 { "rx_frame_error" },
623 { "rx_late_collision" },
625 { "rx_frame_too_long" },
626 { "rx_over_errors" },
628 { "rx_frame_align_error" },
629 { "rx_length_error" },
634 { "rx_errors_total" },
635 { "tx_errors_total" },
637 /* version 2 stats */
640 { "rx_bytes" }, /* includes Ethernet FCS CRC */
645 /* version 3 stats */
651 struct nv_ethtool_stats {
652 u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
656 u64 tx_late_collision;
658 u64 tx_carrier_errors;
659 u64 tx_excess_deferral;
663 u64 rx_late_collision;
665 u64 rx_frame_too_long;
668 u64 rx_frame_align_error;
673 u64 rx_packets; /* should be ifconfig->rx_packets */
677 /* version 2 stats */
679 u64 tx_packets; /* should be ifconfig->tx_packets */
680 u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */
685 /* version 3 stats */
691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
696 #define NV_TEST_COUNT_BASE 3
697 #define NV_TEST_COUNT_EXTENDED 4
699 static const struct nv_ethtool_str nv_etests_str[] = {
700 { "link (online/offline)" },
701 { "register (offline) " },
702 { "interrupt (offline) " },
703 { "loopback (offline) " }
706 struct register_test {
711 static const struct register_test nv_registers_test[] = {
712 { NvRegUnknownSetupReg6, 0x01 },
713 { NvRegMisc1, 0x03c },
714 { NvRegOffloadConfig, 0x03ff },
715 { NvRegMulticastAddrA, 0xffffffff },
716 { NvRegTxWatermark, 0x0ff },
717 { NvRegWakeUpFlags, 0x07777 },
724 unsigned int dma_len:31;
725 unsigned int dma_single:1;
726 struct ring_desc_ex *first_tx_desc;
727 struct nv_skb_map *next_tx_ctx;
732 * All hardware access under netdev_priv(dev)->lock, except the performance
734 * - rx is (pseudo-) lockless: it relies on the single-threading provided
735 * by the arch code for interrupts.
736 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
737 * needs netdev_priv(dev)->lock :-(
738 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
740 * Hardware stats updates are protected by hwstats_lock:
741 * - updated by nv_do_stats_poll (timer). This is meant to avoid
742 * integer wraparound in the NIC stats registers, at low frequency
744 * - updated by nv_get_ethtool_stats + nv_get_stats64
746 * Software stats are accessed only through 64b synchronization points
747 * and are not subject to other synchronization techniques (single
748 * update thread on the TX or RX paths).
751 /* in dev: base, irq */
755 struct net_device *dev;
756 struct napi_struct napi;
758 /* hardware stats are updated in syscall and timer */
759 spinlock_t hwstats_lock;
760 struct nv_ethtool_stats estats;
769 unsigned int phy_oui;
770 unsigned int phy_model;
771 unsigned int phy_rev;
777 /* General data: RO fields */
778 dma_addr_t ring_addr;
779 struct pci_dev *pci_dev;
795 /* rx specific fields.
796 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
798 union ring_type get_rx, put_rx, first_rx, last_rx;
799 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
800 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
801 struct nv_skb_map *rx_skb;
803 union ring_type rx_ring;
804 unsigned int rx_buf_sz;
805 unsigned int pkt_limit;
806 struct timer_list oom_kick;
807 struct timer_list nic_poll;
808 struct timer_list stats_poll;
812 /* RX software stats */
813 struct u64_stats_sync swstats_rx_syncp;
815 u64 stat_rx_bytes; /* not always available in HW */
816 u64 stat_rx_missed_errors;
819 /* media detection workaround.
820 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
823 unsigned long link_timeout;
825 * tx specific fields.
827 union ring_type get_tx, put_tx, first_tx, last_tx;
828 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
829 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
830 struct nv_skb_map *tx_skb;
832 union ring_type tx_ring;
836 u32 tx_pkts_in_progress;
837 struct nv_skb_map *tx_change_owner;
838 struct nv_skb_map *tx_end_flip;
841 /* TX software stats */
842 struct u64_stats_sync swstats_tx_syncp;
843 u64 stat_tx_packets; /* not always available in HW */
847 /* msi/msi-x fields */
849 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
854 /* power saved state */
855 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
857 /* for different msi-x irq type */
858 char name_rx[IFNAMSIZ + 3]; /* -rx */
859 char name_tx[IFNAMSIZ + 3]; /* -tx */
860 char name_other[IFNAMSIZ + 6]; /* -other */
864 * Maximum number of loops until we assume that a bit in the irq mask
865 * is stuck. Overridable with module param.
867 static int max_interrupt_work = 4;
870 * Optimization can be either throuput mode or cpu mode
872 * Throughput Mode: Every tx and rx packet will generate an interrupt.
873 * CPU Mode: Interrupts are controlled by a timer.
876 NV_OPTIMIZATION_MODE_THROUGHPUT,
877 NV_OPTIMIZATION_MODE_CPU,
878 NV_OPTIMIZATION_MODE_DYNAMIC
880 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
883 * Poll interval for timer irq
885 * This interval determines how frequent an interrupt is generated.
886 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
887 * Min = 0, and Max = 65535
889 static int poll_interval = -1;
898 static int msi = NV_MSI_INT_ENABLED;
904 NV_MSIX_INT_DISABLED,
907 static int msix = NV_MSIX_INT_ENABLED;
913 NV_DMA_64BIT_DISABLED,
916 static int dma_64bit = NV_DMA_64BIT_ENABLED;
919 * Debug output control for tx_timeout
921 static bool debug_tx_timeout = false;
924 * Crossover Detection
925 * Realtek 8201 phy + some OEM boards do not work properly.
928 NV_CROSSOVER_DETECTION_DISABLED,
929 NV_CROSSOVER_DETECTION_ENABLED
931 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
934 * Power down phy when interface is down (persists through reboot;
935 * older Linux and other OSes may not power it up again)
937 static int phy_power_down;
939 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
941 return netdev_priv(dev);
944 static inline u8 __iomem *get_hwbase(struct net_device *dev)
946 return ((struct fe_priv *)netdev_priv(dev))->base;
949 static inline void pci_push(u8 __iomem *base)
951 /* force out pending posted writes */
955 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
957 return le32_to_cpu(prd->flaglen)
958 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
961 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
963 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
966 static bool nv_optimized(struct fe_priv *np)
968 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
973 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
974 int delay, int delaymax)
976 u8 __iomem *base = get_hwbase(dev);
984 } while ((readl(base + offset) & mask) != target);
988 #define NV_SETUP_RX_RING 0x01
989 #define NV_SETUP_TX_RING 0x02
991 static inline u32 dma_low(dma_addr_t addr)
996 static inline u32 dma_high(dma_addr_t addr)
998 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
1001 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1003 struct fe_priv *np = get_nvpriv(dev);
1004 u8 __iomem *base = get_hwbase(dev);
1006 if (!nv_optimized(np)) {
1007 if (rxtx_flags & NV_SETUP_RX_RING)
1008 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1009 if (rxtx_flags & NV_SETUP_TX_RING)
1010 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1012 if (rxtx_flags & NV_SETUP_RX_RING) {
1013 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1014 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1016 if (rxtx_flags & NV_SETUP_TX_RING) {
1017 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1018 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1023 static void free_rings(struct net_device *dev)
1025 struct fe_priv *np = get_nvpriv(dev);
1027 if (!nv_optimized(np)) {
1028 if (np->rx_ring.orig)
1029 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1030 np->rx_ring.orig, np->ring_addr);
1033 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1034 np->rx_ring.ex, np->ring_addr);
1040 static int using_multi_irqs(struct net_device *dev)
1042 struct fe_priv *np = get_nvpriv(dev);
1044 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1045 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1046 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1052 static void nv_txrx_gate(struct net_device *dev, bool gate)
1054 struct fe_priv *np = get_nvpriv(dev);
1055 u8 __iomem *base = get_hwbase(dev);
1058 if (!np->mac_in_use &&
1059 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1060 powerstate = readl(base + NvRegPowerState2);
1062 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1064 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1065 writel(powerstate, base + NvRegPowerState2);
1069 static void nv_enable_irq(struct net_device *dev)
1071 struct fe_priv *np = get_nvpriv(dev);
1073 if (!using_multi_irqs(dev)) {
1074 if (np->msi_flags & NV_MSI_X_ENABLED)
1075 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1077 enable_irq(np->pci_dev->irq);
1079 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1080 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1081 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1085 static void nv_disable_irq(struct net_device *dev)
1087 struct fe_priv *np = get_nvpriv(dev);
1089 if (!using_multi_irqs(dev)) {
1090 if (np->msi_flags & NV_MSI_X_ENABLED)
1091 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1093 disable_irq(np->pci_dev->irq);
1095 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1096 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1097 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1101 /* In MSIX mode, a write to irqmask behaves as XOR */
1102 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1104 u8 __iomem *base = get_hwbase(dev);
1106 writel(mask, base + NvRegIrqMask);
1109 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1111 struct fe_priv *np = get_nvpriv(dev);
1112 u8 __iomem *base = get_hwbase(dev);
1114 if (np->msi_flags & NV_MSI_X_ENABLED) {
1115 writel(mask, base + NvRegIrqMask);
1117 if (np->msi_flags & NV_MSI_ENABLED)
1118 writel(0, base + NvRegMSIIrqMask);
1119 writel(0, base + NvRegIrqMask);
1123 static void nv_napi_enable(struct net_device *dev)
1125 struct fe_priv *np = get_nvpriv(dev);
1127 napi_enable(&np->napi);
1130 static void nv_napi_disable(struct net_device *dev)
1132 struct fe_priv *np = get_nvpriv(dev);
1134 napi_disable(&np->napi);
1137 #define MII_READ (-1)
1138 /* mii_rw: read/write a register on the PHY.
1140 * Caller must guarantee serialization
1142 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1144 u8 __iomem *base = get_hwbase(dev);
1148 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1150 reg = readl(base + NvRegMIIControl);
1151 if (reg & NVREG_MIICTL_INUSE) {
1152 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1153 udelay(NV_MIIBUSY_DELAY);
1156 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1157 if (value != MII_READ) {
1158 writel(value, base + NvRegMIIData);
1159 reg |= NVREG_MIICTL_WRITE;
1161 writel(reg, base + NvRegMIIControl);
1163 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1164 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1166 } else if (value != MII_READ) {
1167 /* it was a write operation - fewer failures are detectable */
1169 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1172 retval = readl(base + NvRegMIIData);
1178 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1180 struct fe_priv *np = netdev_priv(dev);
1182 unsigned int tries = 0;
1184 miicontrol = BMCR_RESET | bmcr_setup;
1185 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1188 /* wait for 500ms */
1191 /* must wait till reset is deasserted */
1192 while (miicontrol & BMCR_RESET) {
1193 usleep_range(10000, 20000);
1194 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1195 /* FIXME: 100 tries seem excessive */
1202 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1204 static const struct {
1208 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1209 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1210 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1211 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1212 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1213 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1214 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1218 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1219 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1226 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1229 u8 __iomem *base = get_hwbase(dev);
1230 u32 powerstate = readl(base + NvRegPowerState2);
1232 /* need to perform hw phy reset */
1233 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1234 writel(powerstate, base + NvRegPowerState2);
1237 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1238 writel(powerstate, base + NvRegPowerState2);
1241 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1242 reg |= PHY_REALTEK_INIT9;
1243 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1245 if (mii_rw(dev, np->phyaddr,
1246 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1248 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1249 if (!(reg & PHY_REALTEK_INIT11)) {
1250 reg |= PHY_REALTEK_INIT11;
1251 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1254 if (mii_rw(dev, np->phyaddr,
1255 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1261 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1265 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1266 phy_reserved = mii_rw(dev, np->phyaddr,
1267 PHY_REALTEK_INIT_REG6, MII_READ);
1268 phy_reserved |= PHY_REALTEK_INIT7;
1269 if (mii_rw(dev, np->phyaddr,
1270 PHY_REALTEK_INIT_REG6, phy_reserved))
1277 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1281 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1282 if (mii_rw(dev, np->phyaddr,
1283 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1285 phy_reserved = mii_rw(dev, np->phyaddr,
1286 PHY_REALTEK_INIT_REG2, MII_READ);
1287 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1288 phy_reserved |= PHY_REALTEK_INIT3;
1289 if (mii_rw(dev, np->phyaddr,
1290 PHY_REALTEK_INIT_REG2, phy_reserved))
1292 if (mii_rw(dev, np->phyaddr,
1293 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1300 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1305 if (phyinterface & PHY_RGMII) {
1306 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1307 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1308 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1309 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1311 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1312 phy_reserved |= PHY_CICADA_INIT5;
1313 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1316 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1317 phy_reserved |= PHY_CICADA_INIT6;
1318 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1324 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1328 if (mii_rw(dev, np->phyaddr,
1329 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1331 if (mii_rw(dev, np->phyaddr,
1332 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1334 phy_reserved = mii_rw(dev, np->phyaddr,
1335 PHY_VITESSE_INIT_REG4, MII_READ);
1336 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1338 phy_reserved = mii_rw(dev, np->phyaddr,
1339 PHY_VITESSE_INIT_REG3, MII_READ);
1340 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1341 phy_reserved |= PHY_VITESSE_INIT3;
1342 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1344 if (mii_rw(dev, np->phyaddr,
1345 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1347 if (mii_rw(dev, np->phyaddr,
1348 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1350 phy_reserved = mii_rw(dev, np->phyaddr,
1351 PHY_VITESSE_INIT_REG4, MII_READ);
1352 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1353 phy_reserved |= PHY_VITESSE_INIT3;
1354 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1356 phy_reserved = mii_rw(dev, np->phyaddr,
1357 PHY_VITESSE_INIT_REG3, MII_READ);
1358 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1360 if (mii_rw(dev, np->phyaddr,
1361 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1363 if (mii_rw(dev, np->phyaddr,
1364 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1366 phy_reserved = mii_rw(dev, np->phyaddr,
1367 PHY_VITESSE_INIT_REG4, MII_READ);
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1370 phy_reserved = mii_rw(dev, np->phyaddr,
1371 PHY_VITESSE_INIT_REG3, MII_READ);
1372 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1373 phy_reserved |= PHY_VITESSE_INIT8;
1374 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1376 if (mii_rw(dev, np->phyaddr,
1377 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1379 if (mii_rw(dev, np->phyaddr,
1380 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1386 static int phy_init(struct net_device *dev)
1388 struct fe_priv *np = get_nvpriv(dev);
1389 u8 __iomem *base = get_hwbase(dev);
1391 u32 mii_status, mii_control, mii_control_1000, reg;
1393 /* phy errata for E3016 phy */
1394 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1395 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1396 reg &= ~PHY_MARVELL_E3016_INITMASK;
1397 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1398 netdev_info(dev, "%s: phy write to errata reg failed\n",
1399 pci_name(np->pci_dev));
1403 if (np->phy_oui == PHY_OUI_REALTEK) {
1404 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1405 np->phy_rev == PHY_REV_REALTEK_8211B) {
1406 if (init_realtek_8211b(dev, np)) {
1407 netdev_info(dev, "%s: phy init failed\n",
1408 pci_name(np->pci_dev));
1411 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1412 np->phy_rev == PHY_REV_REALTEK_8211C) {
1413 if (init_realtek_8211c(dev, np)) {
1414 netdev_info(dev, "%s: phy init failed\n",
1415 pci_name(np->pci_dev));
1418 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1419 if (init_realtek_8201(dev, np)) {
1420 netdev_info(dev, "%s: phy init failed\n",
1421 pci_name(np->pci_dev));
1427 /* set advertise register */
1428 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1429 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1430 ADVERTISE_100HALF | ADVERTISE_100FULL |
1431 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1432 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1433 netdev_info(dev, "%s: phy write to advertise failed\n",
1434 pci_name(np->pci_dev));
1438 /* get phy interface type */
1439 phyinterface = readl(base + NvRegPhyInterface);
1441 /* see if gigabit phy */
1442 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1443 if (mii_status & PHY_GIGABIT) {
1444 np->gigabit = PHY_GIGABIT;
1445 mii_control_1000 = mii_rw(dev, np->phyaddr,
1446 MII_CTRL1000, MII_READ);
1447 mii_control_1000 &= ~ADVERTISE_1000HALF;
1448 if (phyinterface & PHY_RGMII)
1449 mii_control_1000 |= ADVERTISE_1000FULL;
1451 mii_control_1000 &= ~ADVERTISE_1000FULL;
1453 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1454 netdev_info(dev, "%s: phy init failed\n",
1455 pci_name(np->pci_dev));
1461 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1462 mii_control |= BMCR_ANENABLE;
1464 if (np->phy_oui == PHY_OUI_REALTEK &&
1465 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1466 np->phy_rev == PHY_REV_REALTEK_8211C) {
1467 /* start autoneg since we already performed hw reset above */
1468 mii_control |= BMCR_ANRESTART;
1469 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1470 netdev_info(dev, "%s: phy init failed\n",
1471 pci_name(np->pci_dev));
1476 * (certain phys need bmcr to be setup with reset)
1478 if (phy_reset(dev, mii_control)) {
1479 netdev_info(dev, "%s: phy reset failed\n",
1480 pci_name(np->pci_dev));
1485 /* phy vendor specific configuration */
1486 if ((np->phy_oui == PHY_OUI_CICADA)) {
1487 if (init_cicada(dev, np, phyinterface)) {
1488 netdev_info(dev, "%s: phy init failed\n",
1489 pci_name(np->pci_dev));
1492 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1493 if (init_vitesse(dev, np)) {
1494 netdev_info(dev, "%s: phy init failed\n",
1495 pci_name(np->pci_dev));
1498 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1499 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1500 np->phy_rev == PHY_REV_REALTEK_8211B) {
1501 /* reset could have cleared these out, set them back */
1502 if (init_realtek_8211b(dev, np)) {
1503 netdev_info(dev, "%s: phy init failed\n",
1504 pci_name(np->pci_dev));
1507 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1508 if (init_realtek_8201(dev, np) ||
1509 init_realtek_8201_cross(dev, np)) {
1510 netdev_info(dev, "%s: phy init failed\n",
1511 pci_name(np->pci_dev));
1517 /* some phys clear out pause advertisement on reset, set it back */
1518 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1520 /* restart auto negotiation, power down phy */
1521 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1522 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1524 mii_control |= BMCR_PDOWN;
1525 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1531 static void nv_start_rx(struct net_device *dev)
1533 struct fe_priv *np = netdev_priv(dev);
1534 u8 __iomem *base = get_hwbase(dev);
1535 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1537 /* Already running? Stop it. */
1538 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1539 rx_ctrl &= ~NVREG_RCVCTL_START;
1540 writel(rx_ctrl, base + NvRegReceiverControl);
1543 writel(np->linkspeed, base + NvRegLinkSpeed);
1545 rx_ctrl |= NVREG_RCVCTL_START;
1547 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1548 writel(rx_ctrl, base + NvRegReceiverControl);
1552 static void nv_stop_rx(struct net_device *dev)
1554 struct fe_priv *np = netdev_priv(dev);
1555 u8 __iomem *base = get_hwbase(dev);
1556 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1558 if (!np->mac_in_use)
1559 rx_ctrl &= ~NVREG_RCVCTL_START;
1561 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1562 writel(rx_ctrl, base + NvRegReceiverControl);
1563 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1564 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1565 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1568 udelay(NV_RXSTOP_DELAY2);
1569 if (!np->mac_in_use)
1570 writel(0, base + NvRegLinkSpeed);
1573 static void nv_start_tx(struct net_device *dev)
1575 struct fe_priv *np = netdev_priv(dev);
1576 u8 __iomem *base = get_hwbase(dev);
1577 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1579 tx_ctrl |= NVREG_XMITCTL_START;
1581 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1582 writel(tx_ctrl, base + NvRegTransmitterControl);
1586 static void nv_stop_tx(struct net_device *dev)
1588 struct fe_priv *np = netdev_priv(dev);
1589 u8 __iomem *base = get_hwbase(dev);
1590 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1592 if (!np->mac_in_use)
1593 tx_ctrl &= ~NVREG_XMITCTL_START;
1595 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1596 writel(tx_ctrl, base + NvRegTransmitterControl);
1597 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1598 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1599 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1602 udelay(NV_TXSTOP_DELAY2);
1603 if (!np->mac_in_use)
1604 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1605 base + NvRegTransmitPoll);
1608 static void nv_start_rxtx(struct net_device *dev)
1614 static void nv_stop_rxtx(struct net_device *dev)
1620 static void nv_txrx_reset(struct net_device *dev)
1622 struct fe_priv *np = netdev_priv(dev);
1623 u8 __iomem *base = get_hwbase(dev);
1625 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1627 udelay(NV_TXRX_RESET_DELAY);
1628 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1632 static void nv_mac_reset(struct net_device *dev)
1634 struct fe_priv *np = netdev_priv(dev);
1635 u8 __iomem *base = get_hwbase(dev);
1636 u32 temp1, temp2, temp3;
1638 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1641 /* save registers since they will be cleared on reset */
1642 temp1 = readl(base + NvRegMacAddrA);
1643 temp2 = readl(base + NvRegMacAddrB);
1644 temp3 = readl(base + NvRegTransmitPoll);
1646 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1648 udelay(NV_MAC_RESET_DELAY);
1649 writel(0, base + NvRegMacReset);
1651 udelay(NV_MAC_RESET_DELAY);
1653 /* restore saved registers */
1654 writel(temp1, base + NvRegMacAddrA);
1655 writel(temp2, base + NvRegMacAddrB);
1656 writel(temp3, base + NvRegTransmitPoll);
1658 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1662 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1663 static void nv_update_stats(struct net_device *dev)
1665 struct fe_priv *np = netdev_priv(dev);
1666 u8 __iomem *base = get_hwbase(dev);
1668 /* If it happens that this is run in top-half context, then
1669 * replace the spin_lock of hwstats_lock with
1670 * spin_lock_irqsave() in calling functions. */
1671 WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1672 assert_spin_locked(&np->hwstats_lock);
1674 /* query hardware */
1675 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1676 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1677 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1678 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1679 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1680 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1681 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1682 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1683 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1684 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1685 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1686 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1687 np->estats.rx_runt += readl(base + NvRegRxRunt);
1688 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1689 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1690 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1691 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1692 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1693 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1694 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1695 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1696 np->estats.rx_packets =
1697 np->estats.rx_unicast +
1698 np->estats.rx_multicast +
1699 np->estats.rx_broadcast;
1700 np->estats.rx_errors_total =
1701 np->estats.rx_crc_errors +
1702 np->estats.rx_over_errors +
1703 np->estats.rx_frame_error +
1704 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1705 np->estats.rx_late_collision +
1706 np->estats.rx_runt +
1707 np->estats.rx_frame_too_long;
1708 np->estats.tx_errors_total =
1709 np->estats.tx_late_collision +
1710 np->estats.tx_fifo_errors +
1711 np->estats.tx_carrier_errors +
1712 np->estats.tx_excess_deferral +
1713 np->estats.tx_retry_error;
1715 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1716 np->estats.tx_deferral += readl(base + NvRegTxDef);
1717 np->estats.tx_packets += readl(base + NvRegTxFrame);
1718 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1719 np->estats.tx_pause += readl(base + NvRegTxPause);
1720 np->estats.rx_pause += readl(base + NvRegRxPause);
1721 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1722 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1725 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1726 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1727 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1728 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1733 * nv_get_stats64: dev->ndo_get_stats64 function
1734 * Get latest stats value from the nic.
1735 * Called with read_lock(&dev_base_lock) held for read -
1736 * only synchronized against unregister_netdevice.
1738 static struct rtnl_link_stats64*
1739 nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1740 __acquires(&netdev_priv(dev)->hwstats_lock)
1741 __releases(&netdev_priv(dev)->hwstats_lock)
1743 struct fe_priv *np = netdev_priv(dev);
1744 unsigned int syncp_start;
1747 * Note: because HW stats are not always available and for
1748 * consistency reasons, the following ifconfig stats are
1749 * managed by software: rx_bytes, tx_bytes, rx_packets and
1750 * tx_packets. The related hardware stats reported by ethtool
1751 * should be equivalent to these ifconfig stats, with 4
1752 * additional bytes per packet (Ethernet FCS CRC), except for
1753 * tx_packets when TSO kicks in.
1756 /* software stats */
1758 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_rx_syncp);
1759 storage->rx_packets = np->stat_rx_packets;
1760 storage->rx_bytes = np->stat_rx_bytes;
1761 storage->rx_dropped = np->stat_rx_dropped;
1762 storage->rx_missed_errors = np->stat_rx_missed_errors;
1763 } while (u64_stats_fetch_retry_bh(&np->swstats_rx_syncp, syncp_start));
1766 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_tx_syncp);
1767 storage->tx_packets = np->stat_tx_packets;
1768 storage->tx_bytes = np->stat_tx_bytes;
1769 storage->tx_dropped = np->stat_tx_dropped;
1770 } while (u64_stats_fetch_retry_bh(&np->swstats_tx_syncp, syncp_start));
1772 /* If the nic supports hw counters then retrieve latest values */
1773 if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1774 spin_lock_bh(&np->hwstats_lock);
1776 nv_update_stats(dev);
1779 storage->rx_errors = np->estats.rx_errors_total;
1780 storage->tx_errors = np->estats.tx_errors_total;
1782 /* meaningful only when NIC supports stats v3 */
1783 storage->multicast = np->estats.rx_multicast;
1785 /* detailed rx_errors */
1786 storage->rx_length_errors = np->estats.rx_length_error;
1787 storage->rx_over_errors = np->estats.rx_over_errors;
1788 storage->rx_crc_errors = np->estats.rx_crc_errors;
1789 storage->rx_frame_errors = np->estats.rx_frame_align_error;
1790 storage->rx_fifo_errors = np->estats.rx_drop_frame;
1792 /* detailed tx_errors */
1793 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1794 storage->tx_fifo_errors = np->estats.tx_fifo_errors;
1796 spin_unlock_bh(&np->hwstats_lock);
1803 * nv_alloc_rx: fill rx ring entries.
1804 * Return 1 if the allocations for the skbs failed and the
1805 * rx engine is without Available descriptors
1807 static int nv_alloc_rx(struct net_device *dev)
1809 struct fe_priv *np = netdev_priv(dev);
1810 struct ring_desc *less_rx;
1812 less_rx = np->get_rx.orig;
1813 if (less_rx-- == np->first_rx.orig)
1814 less_rx = np->last_rx.orig;
1816 while (np->put_rx.orig != less_rx) {
1817 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1819 np->put_rx_ctx->skb = skb;
1820 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1823 PCI_DMA_FROMDEVICE);
1824 if (pci_dma_mapping_error(np->pci_dev,
1825 np->put_rx_ctx->dma)) {
1827 goto packet_dropped;
1829 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1830 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1832 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1833 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1834 np->put_rx.orig = np->first_rx.orig;
1835 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1836 np->put_rx_ctx = np->first_rx_ctx;
1839 u64_stats_update_begin(&np->swstats_rx_syncp);
1840 np->stat_rx_dropped++;
1841 u64_stats_update_end(&np->swstats_rx_syncp);
1848 static int nv_alloc_rx_optimized(struct net_device *dev)
1850 struct fe_priv *np = netdev_priv(dev);
1851 struct ring_desc_ex *less_rx;
1853 less_rx = np->get_rx.ex;
1854 if (less_rx-- == np->first_rx.ex)
1855 less_rx = np->last_rx.ex;
1857 while (np->put_rx.ex != less_rx) {
1858 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1860 np->put_rx_ctx->skb = skb;
1861 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1864 PCI_DMA_FROMDEVICE);
1865 if (pci_dma_mapping_error(np->pci_dev,
1866 np->put_rx_ctx->dma)) {
1868 goto packet_dropped;
1870 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1871 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1872 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1874 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1875 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1876 np->put_rx.ex = np->first_rx.ex;
1877 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1878 np->put_rx_ctx = np->first_rx_ctx;
1881 u64_stats_update_begin(&np->swstats_rx_syncp);
1882 np->stat_rx_dropped++;
1883 u64_stats_update_end(&np->swstats_rx_syncp);
1890 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1891 static void nv_do_rx_refill(unsigned long data)
1893 struct net_device *dev = (struct net_device *) data;
1894 struct fe_priv *np = netdev_priv(dev);
1896 /* Just reschedule NAPI rx processing */
1897 napi_schedule(&np->napi);
1900 static void nv_init_rx(struct net_device *dev)
1902 struct fe_priv *np = netdev_priv(dev);
1905 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1907 if (!nv_optimized(np))
1908 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1910 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1911 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1912 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1914 for (i = 0; i < np->rx_ring_size; i++) {
1915 if (!nv_optimized(np)) {
1916 np->rx_ring.orig[i].flaglen = 0;
1917 np->rx_ring.orig[i].buf = 0;
1919 np->rx_ring.ex[i].flaglen = 0;
1920 np->rx_ring.ex[i].txvlan = 0;
1921 np->rx_ring.ex[i].bufhigh = 0;
1922 np->rx_ring.ex[i].buflow = 0;
1924 np->rx_skb[i].skb = NULL;
1925 np->rx_skb[i].dma = 0;
1929 static void nv_init_tx(struct net_device *dev)
1931 struct fe_priv *np = netdev_priv(dev);
1934 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1936 if (!nv_optimized(np))
1937 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1939 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1940 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1941 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1942 netdev_reset_queue(np->dev);
1943 np->tx_pkts_in_progress = 0;
1944 np->tx_change_owner = NULL;
1945 np->tx_end_flip = NULL;
1948 for (i = 0; i < np->tx_ring_size; i++) {
1949 if (!nv_optimized(np)) {
1950 np->tx_ring.orig[i].flaglen = 0;
1951 np->tx_ring.orig[i].buf = 0;
1953 np->tx_ring.ex[i].flaglen = 0;
1954 np->tx_ring.ex[i].txvlan = 0;
1955 np->tx_ring.ex[i].bufhigh = 0;
1956 np->tx_ring.ex[i].buflow = 0;
1958 np->tx_skb[i].skb = NULL;
1959 np->tx_skb[i].dma = 0;
1960 np->tx_skb[i].dma_len = 0;
1961 np->tx_skb[i].dma_single = 0;
1962 np->tx_skb[i].first_tx_desc = NULL;
1963 np->tx_skb[i].next_tx_ctx = NULL;
1967 static int nv_init_ring(struct net_device *dev)
1969 struct fe_priv *np = netdev_priv(dev);
1974 if (!nv_optimized(np))
1975 return nv_alloc_rx(dev);
1977 return nv_alloc_rx_optimized(dev);
1980 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1983 if (tx_skb->dma_single)
1984 pci_unmap_single(np->pci_dev, tx_skb->dma,
1988 pci_unmap_page(np->pci_dev, tx_skb->dma,
1995 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1997 nv_unmap_txskb(np, tx_skb);
1999 dev_kfree_skb_any(tx_skb->skb);
2006 static void nv_drain_tx(struct net_device *dev)
2008 struct fe_priv *np = netdev_priv(dev);
2011 for (i = 0; i < np->tx_ring_size; i++) {
2012 if (!nv_optimized(np)) {
2013 np->tx_ring.orig[i].flaglen = 0;
2014 np->tx_ring.orig[i].buf = 0;
2016 np->tx_ring.ex[i].flaglen = 0;
2017 np->tx_ring.ex[i].txvlan = 0;
2018 np->tx_ring.ex[i].bufhigh = 0;
2019 np->tx_ring.ex[i].buflow = 0;
2021 if (nv_release_txskb(np, &np->tx_skb[i])) {
2022 u64_stats_update_begin(&np->swstats_tx_syncp);
2023 np->stat_tx_dropped++;
2024 u64_stats_update_end(&np->swstats_tx_syncp);
2026 np->tx_skb[i].dma = 0;
2027 np->tx_skb[i].dma_len = 0;
2028 np->tx_skb[i].dma_single = 0;
2029 np->tx_skb[i].first_tx_desc = NULL;
2030 np->tx_skb[i].next_tx_ctx = NULL;
2032 np->tx_pkts_in_progress = 0;
2033 np->tx_change_owner = NULL;
2034 np->tx_end_flip = NULL;
2037 static void nv_drain_rx(struct net_device *dev)
2039 struct fe_priv *np = netdev_priv(dev);
2042 for (i = 0; i < np->rx_ring_size; i++) {
2043 if (!nv_optimized(np)) {
2044 np->rx_ring.orig[i].flaglen = 0;
2045 np->rx_ring.orig[i].buf = 0;
2047 np->rx_ring.ex[i].flaglen = 0;
2048 np->rx_ring.ex[i].txvlan = 0;
2049 np->rx_ring.ex[i].bufhigh = 0;
2050 np->rx_ring.ex[i].buflow = 0;
2053 if (np->rx_skb[i].skb) {
2054 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2055 (skb_end_pointer(np->rx_skb[i].skb) -
2056 np->rx_skb[i].skb->data),
2057 PCI_DMA_FROMDEVICE);
2058 dev_kfree_skb(np->rx_skb[i].skb);
2059 np->rx_skb[i].skb = NULL;
2064 static void nv_drain_rxtx(struct net_device *dev)
2070 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2072 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2075 static void nv_legacybackoff_reseed(struct net_device *dev)
2077 u8 __iomem *base = get_hwbase(dev);
2082 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2083 get_random_bytes(&low, sizeof(low));
2084 reg |= low & NVREG_SLOTTIME_MASK;
2086 /* Need to stop tx before change takes effect.
2087 * Caller has already gained np->lock.
2089 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2093 writel(reg, base + NvRegSlotTime);
2099 /* Gear Backoff Seeds */
2100 #define BACKOFF_SEEDSET_ROWS 8
2101 #define BACKOFF_SEEDSET_LFSRS 15
2103 /* Known Good seed sets */
2104 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2105 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2106 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2107 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2108 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2109 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2110 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2111 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2112 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2114 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2115 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2116 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2117 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2118 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2119 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2120 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2121 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2122 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2124 static void nv_gear_backoff_reseed(struct net_device *dev)
2126 u8 __iomem *base = get_hwbase(dev);
2127 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2128 u32 temp, seedset, combinedSeed;
2131 /* Setup seed for free running LFSR */
2132 /* We are going to read the time stamp counter 3 times
2133 and swizzle bits around to increase randomness */
2134 get_random_bytes(&miniseed1, sizeof(miniseed1));
2135 miniseed1 &= 0x0fff;
2139 get_random_bytes(&miniseed2, sizeof(miniseed2));
2140 miniseed2 &= 0x0fff;
2143 miniseed2_reversed =
2144 ((miniseed2 & 0xF00) >> 8) |
2145 (miniseed2 & 0x0F0) |
2146 ((miniseed2 & 0x00F) << 8);
2148 get_random_bytes(&miniseed3, sizeof(miniseed3));
2149 miniseed3 &= 0x0fff;
2152 miniseed3_reversed =
2153 ((miniseed3 & 0xF00) >> 8) |
2154 (miniseed3 & 0x0F0) |
2155 ((miniseed3 & 0x00F) << 8);
2157 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2158 (miniseed2 ^ miniseed3_reversed);
2160 /* Seeds can not be zero */
2161 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2162 combinedSeed |= 0x08;
2163 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2164 combinedSeed |= 0x8000;
2166 /* No need to disable tx here */
2167 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2168 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2169 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2170 writel(temp, base + NvRegBackOffControl);
2172 /* Setup seeds for all gear LFSRs. */
2173 get_random_bytes(&seedset, sizeof(seedset));
2174 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2175 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2176 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2177 temp |= main_seedset[seedset][i-1] & 0x3ff;
2178 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2179 writel(temp, base + NvRegBackOffControl);
2184 * nv_start_xmit: dev->hard_start_xmit function
2185 * Called with netif_tx_lock held.
2187 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2189 struct fe_priv *np = netdev_priv(dev);
2191 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2192 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2196 u32 size = skb_headlen(skb);
2197 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2199 struct ring_desc *put_tx;
2200 struct ring_desc *start_tx;
2201 struct ring_desc *prev_tx;
2202 struct nv_skb_map *prev_tx_ctx;
2203 unsigned long flags;
2205 /* add fragments to entries count */
2206 for (i = 0; i < fragments; i++) {
2207 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2209 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2210 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2213 spin_lock_irqsave(&np->lock, flags);
2214 empty_slots = nv_get_empty_tx_slots(np);
2215 if (unlikely(empty_slots <= entries)) {
2216 netif_stop_queue(dev);
2218 spin_unlock_irqrestore(&np->lock, flags);
2219 return NETDEV_TX_BUSY;
2221 spin_unlock_irqrestore(&np->lock, flags);
2223 start_tx = put_tx = np->put_tx.orig;
2225 /* setup the header buffer */
2228 prev_tx_ctx = np->put_tx_ctx;
2229 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2230 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2232 if (pci_dma_mapping_error(np->pci_dev,
2233 np->put_tx_ctx->dma)) {
2234 /* on DMA mapping error - drop the packet */
2236 u64_stats_update_begin(&np->swstats_tx_syncp);
2237 np->stat_tx_dropped++;
2238 u64_stats_update_end(&np->swstats_tx_syncp);
2239 return NETDEV_TX_OK;
2241 np->put_tx_ctx->dma_len = bcnt;
2242 np->put_tx_ctx->dma_single = 1;
2243 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2244 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2246 tx_flags = np->tx_flags;
2249 if (unlikely(put_tx++ == np->last_tx.orig))
2250 put_tx = np->first_tx.orig;
2251 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2252 np->put_tx_ctx = np->first_tx_ctx;
2255 /* setup the fragments */
2256 for (i = 0; i < fragments; i++) {
2257 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2258 u32 frag_size = skb_frag_size(frag);
2263 prev_tx_ctx = np->put_tx_ctx;
2264 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2265 np->put_tx_ctx->dma = skb_frag_dma_map(
2270 np->put_tx_ctx->dma_len = bcnt;
2271 np->put_tx_ctx->dma_single = 0;
2272 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2273 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2277 if (unlikely(put_tx++ == np->last_tx.orig))
2278 put_tx = np->first_tx.orig;
2279 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2280 np->put_tx_ctx = np->first_tx_ctx;
2281 } while (frag_size);
2284 /* set last fragment flag */
2285 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2287 /* save skb in this slot's context area */
2288 prev_tx_ctx->skb = skb;
2290 if (skb_is_gso(skb))
2291 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2293 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2294 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2296 spin_lock_irqsave(&np->lock, flags);
2299 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2301 netdev_sent_queue(np->dev, skb->len);
2303 skb_tx_timestamp(skb);
2305 np->put_tx.orig = put_tx;
2307 spin_unlock_irqrestore(&np->lock, flags);
2309 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2310 return NETDEV_TX_OK;
2313 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2314 struct net_device *dev)
2316 struct fe_priv *np = netdev_priv(dev);
2319 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2323 u32 size = skb_headlen(skb);
2324 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2326 struct ring_desc_ex *put_tx;
2327 struct ring_desc_ex *start_tx;
2328 struct ring_desc_ex *prev_tx;
2329 struct nv_skb_map *prev_tx_ctx;
2330 struct nv_skb_map *start_tx_ctx;
2331 unsigned long flags;
2333 /* add fragments to entries count */
2334 for (i = 0; i < fragments; i++) {
2335 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2337 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2338 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2341 spin_lock_irqsave(&np->lock, flags);
2342 empty_slots = nv_get_empty_tx_slots(np);
2343 if (unlikely(empty_slots <= entries)) {
2344 netif_stop_queue(dev);
2346 spin_unlock_irqrestore(&np->lock, flags);
2347 return NETDEV_TX_BUSY;
2349 spin_unlock_irqrestore(&np->lock, flags);
2351 start_tx = put_tx = np->put_tx.ex;
2352 start_tx_ctx = np->put_tx_ctx;
2354 /* setup the header buffer */
2357 prev_tx_ctx = np->put_tx_ctx;
2358 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2359 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2361 if (pci_dma_mapping_error(np->pci_dev,
2362 np->put_tx_ctx->dma)) {
2363 /* on DMA mapping error - drop the packet */
2365 u64_stats_update_begin(&np->swstats_tx_syncp);
2366 np->stat_tx_dropped++;
2367 u64_stats_update_end(&np->swstats_tx_syncp);
2368 return NETDEV_TX_OK;
2370 np->put_tx_ctx->dma_len = bcnt;
2371 np->put_tx_ctx->dma_single = 1;
2372 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2373 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2374 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2376 tx_flags = NV_TX2_VALID;
2379 if (unlikely(put_tx++ == np->last_tx.ex))
2380 put_tx = np->first_tx.ex;
2381 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2382 np->put_tx_ctx = np->first_tx_ctx;
2385 /* setup the fragments */
2386 for (i = 0; i < fragments; i++) {
2387 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2388 u32 frag_size = skb_frag_size(frag);
2393 prev_tx_ctx = np->put_tx_ctx;
2394 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2395 np->put_tx_ctx->dma = skb_frag_dma_map(
2400 np->put_tx_ctx->dma_len = bcnt;
2401 np->put_tx_ctx->dma_single = 0;
2402 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2403 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2404 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2408 if (unlikely(put_tx++ == np->last_tx.ex))
2409 put_tx = np->first_tx.ex;
2410 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2411 np->put_tx_ctx = np->first_tx_ctx;
2412 } while (frag_size);
2415 /* set last fragment flag */
2416 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2418 /* save skb in this slot's context area */
2419 prev_tx_ctx->skb = skb;
2421 if (skb_is_gso(skb))
2422 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2424 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2425 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2428 if (vlan_tx_tag_present(skb))
2429 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2430 vlan_tx_tag_get(skb));
2432 start_tx->txvlan = 0;
2434 spin_lock_irqsave(&np->lock, flags);
2437 /* Limit the number of outstanding tx. Setup all fragments, but
2438 * do not set the VALID bit on the first descriptor. Save a pointer
2439 * to that descriptor and also for next skb_map element.
2442 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2443 if (!np->tx_change_owner)
2444 np->tx_change_owner = start_tx_ctx;
2446 /* remove VALID bit */
2447 tx_flags &= ~NV_TX2_VALID;
2448 start_tx_ctx->first_tx_desc = start_tx;
2449 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2450 np->tx_end_flip = np->put_tx_ctx;
2452 np->tx_pkts_in_progress++;
2457 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2459 netdev_sent_queue(np->dev, skb->len);
2461 skb_tx_timestamp(skb);
2463 np->put_tx.ex = put_tx;
2465 spin_unlock_irqrestore(&np->lock, flags);
2467 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2468 return NETDEV_TX_OK;
2471 static inline void nv_tx_flip_ownership(struct net_device *dev)
2473 struct fe_priv *np = netdev_priv(dev);
2475 np->tx_pkts_in_progress--;
2476 if (np->tx_change_owner) {
2477 np->tx_change_owner->first_tx_desc->flaglen |=
2478 cpu_to_le32(NV_TX2_VALID);
2479 np->tx_pkts_in_progress++;
2481 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2482 if (np->tx_change_owner == np->tx_end_flip)
2483 np->tx_change_owner = NULL;
2485 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2490 * nv_tx_done: check for completed packets, release the skbs.
2492 * Caller must own np->lock.
2494 static int nv_tx_done(struct net_device *dev, int limit)
2496 struct fe_priv *np = netdev_priv(dev);
2499 struct ring_desc *orig_get_tx = np->get_tx.orig;
2500 unsigned int bytes_compl = 0;
2502 while ((np->get_tx.orig != np->put_tx.orig) &&
2503 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2504 (tx_work < limit)) {
2506 nv_unmap_txskb(np, np->get_tx_ctx);
2508 if (np->desc_ver == DESC_VER_1) {
2509 if (flags & NV_TX_LASTPACKET) {
2510 if (flags & NV_TX_ERROR) {
2511 if ((flags & NV_TX_RETRYERROR)
2512 && !(flags & NV_TX_RETRYCOUNT_MASK))
2513 nv_legacybackoff_reseed(dev);
2515 u64_stats_update_begin(&np->swstats_tx_syncp);
2516 np->stat_tx_packets++;
2517 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2518 u64_stats_update_end(&np->swstats_tx_syncp);
2520 bytes_compl += np->get_tx_ctx->skb->len;
2521 dev_kfree_skb_any(np->get_tx_ctx->skb);
2522 np->get_tx_ctx->skb = NULL;
2526 if (flags & NV_TX2_LASTPACKET) {
2527 if (flags & NV_TX2_ERROR) {
2528 if ((flags & NV_TX2_RETRYERROR)
2529 && !(flags & NV_TX2_RETRYCOUNT_MASK))
2530 nv_legacybackoff_reseed(dev);
2532 u64_stats_update_begin(&np->swstats_tx_syncp);
2533 np->stat_tx_packets++;
2534 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2535 u64_stats_update_end(&np->swstats_tx_syncp);
2537 bytes_compl += np->get_tx_ctx->skb->len;
2538 dev_kfree_skb_any(np->get_tx_ctx->skb);
2539 np->get_tx_ctx->skb = NULL;
2543 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2544 np->get_tx.orig = np->first_tx.orig;
2545 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2546 np->get_tx_ctx = np->first_tx_ctx;
2549 netdev_completed_queue(np->dev, tx_work, bytes_compl);
2551 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2553 netif_wake_queue(dev);
2558 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2560 struct fe_priv *np = netdev_priv(dev);
2563 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2564 unsigned long bytes_cleaned = 0;
2566 while ((np->get_tx.ex != np->put_tx.ex) &&
2567 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2568 (tx_work < limit)) {
2570 nv_unmap_txskb(np, np->get_tx_ctx);
2572 if (flags & NV_TX2_LASTPACKET) {
2573 if (flags & NV_TX2_ERROR) {
2574 if ((flags & NV_TX2_RETRYERROR)
2575 && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2576 if (np->driver_data & DEV_HAS_GEAR_MODE)
2577 nv_gear_backoff_reseed(dev);
2579 nv_legacybackoff_reseed(dev);
2582 u64_stats_update_begin(&np->swstats_tx_syncp);
2583 np->stat_tx_packets++;
2584 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2585 u64_stats_update_end(&np->swstats_tx_syncp);
2588 bytes_cleaned += np->get_tx_ctx->skb->len;
2589 dev_kfree_skb_any(np->get_tx_ctx->skb);
2590 np->get_tx_ctx->skb = NULL;
2594 nv_tx_flip_ownership(dev);
2597 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2598 np->get_tx.ex = np->first_tx.ex;
2599 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2600 np->get_tx_ctx = np->first_tx_ctx;
2603 netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2605 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2607 netif_wake_queue(dev);
2613 * nv_tx_timeout: dev->tx_timeout function
2614 * Called with netif_tx_lock held.
2616 static void nv_tx_timeout(struct net_device *dev)
2618 struct fe_priv *np = netdev_priv(dev);
2619 u8 __iomem *base = get_hwbase(dev);
2621 union ring_type put_tx;
2624 if (np->msi_flags & NV_MSI_X_ENABLED)
2625 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2627 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2629 netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2631 if (unlikely(debug_tx_timeout)) {
2634 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2635 netdev_info(dev, "Dumping tx registers\n");
2636 for (i = 0; i <= np->register_size; i += 32) {
2638 "%3x: %08x %08x %08x %08x "
2639 "%08x %08x %08x %08x\n",
2641 readl(base + i + 0), readl(base + i + 4),
2642 readl(base + i + 8), readl(base + i + 12),
2643 readl(base + i + 16), readl(base + i + 20),
2644 readl(base + i + 24), readl(base + i + 28));
2646 netdev_info(dev, "Dumping tx ring\n");
2647 for (i = 0; i < np->tx_ring_size; i += 4) {
2648 if (!nv_optimized(np)) {
2650 "%03x: %08x %08x // %08x %08x "
2651 "// %08x %08x // %08x %08x\n",
2653 le32_to_cpu(np->tx_ring.orig[i].buf),
2654 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2655 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2656 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2657 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2658 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2659 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2660 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2663 "%03x: %08x %08x %08x "
2664 "// %08x %08x %08x "
2665 "// %08x %08x %08x "
2666 "// %08x %08x %08x\n",
2668 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2669 le32_to_cpu(np->tx_ring.ex[i].buflow),
2670 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2671 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2672 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2673 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2674 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2675 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2676 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2677 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2678 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2679 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2684 spin_lock_irq(&np->lock);
2686 /* 1) stop tx engine */
2689 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2690 saved_tx_limit = np->tx_limit;
2691 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2692 np->tx_stop = 0; /* prevent waking tx queue */
2693 if (!nv_optimized(np))
2694 nv_tx_done(dev, np->tx_ring_size);
2696 nv_tx_done_optimized(dev, np->tx_ring_size);
2698 /* save current HW position */
2699 if (np->tx_change_owner)
2700 put_tx.ex = np->tx_change_owner->first_tx_desc;
2702 put_tx = np->put_tx;
2704 /* 3) clear all tx state */
2708 /* 4) restore state to current HW position */
2709 np->get_tx = np->put_tx = put_tx;
2710 np->tx_limit = saved_tx_limit;
2712 /* 5) restart tx engine */
2714 netif_wake_queue(dev);
2715 spin_unlock_irq(&np->lock);
2719 * Called when the nic notices a mismatch between the actual data len on the
2720 * wire and the len indicated in the 802 header
2722 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2724 int hdrlen; /* length of the 802 header */
2725 int protolen; /* length as stored in the proto field */
2727 /* 1) calculate len according to header */
2728 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2729 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2732 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2735 if (protolen > ETH_DATA_LEN)
2736 return datalen; /* Value in proto field not a len, no checks possible */
2739 /* consistency checks: */
2740 if (datalen > ETH_ZLEN) {
2741 if (datalen >= protolen) {
2742 /* more data on wire than in 802 header, trim of
2747 /* less data on wire than mentioned in header.
2748 * Discard the packet.
2753 /* short packet. Accept only if 802 values are also short */
2754 if (protolen > ETH_ZLEN) {
2761 static int nv_rx_process(struct net_device *dev, int limit)
2763 struct fe_priv *np = netdev_priv(dev);
2766 struct sk_buff *skb;
2769 while ((np->get_rx.orig != np->put_rx.orig) &&
2770 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2771 (rx_work < limit)) {
2774 * the packet is for us - immediately tear down the pci mapping.
2775 * TODO: check if a prefetch of the first cacheline improves
2778 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2779 np->get_rx_ctx->dma_len,
2780 PCI_DMA_FROMDEVICE);
2781 skb = np->get_rx_ctx->skb;
2782 np->get_rx_ctx->skb = NULL;
2784 /* look at what we actually got: */
2785 if (np->desc_ver == DESC_VER_1) {
2786 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2787 len = flags & LEN_MASK_V1;
2788 if (unlikely(flags & NV_RX_ERROR)) {
2789 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2790 len = nv_getlen(dev, skb->data, len);
2796 /* framing errors are soft errors */
2797 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2798 if (flags & NV_RX_SUBSTRACT1)
2801 /* the rest are hard errors */
2803 if (flags & NV_RX_MISSEDFRAME) {
2804 u64_stats_update_begin(&np->swstats_rx_syncp);
2805 np->stat_rx_missed_errors++;
2806 u64_stats_update_end(&np->swstats_rx_syncp);
2817 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2818 len = flags & LEN_MASK_V2;
2819 if (unlikely(flags & NV_RX2_ERROR)) {
2820 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2821 len = nv_getlen(dev, skb->data, len);
2827 /* framing errors are soft errors */
2828 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2829 if (flags & NV_RX2_SUBSTRACT1)
2832 /* the rest are hard errors */
2838 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2839 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2840 skb->ip_summed = CHECKSUM_UNNECESSARY;
2846 /* got a valid packet - forward it to the network core */
2848 skb->protocol = eth_type_trans(skb, dev);
2849 napi_gro_receive(&np->napi, skb);
2850 u64_stats_update_begin(&np->swstats_rx_syncp);
2851 np->stat_rx_packets++;
2852 np->stat_rx_bytes += len;
2853 u64_stats_update_end(&np->swstats_rx_syncp);
2855 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2856 np->get_rx.orig = np->first_rx.orig;
2857 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2858 np->get_rx_ctx = np->first_rx_ctx;
2866 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2868 struct fe_priv *np = netdev_priv(dev);
2872 struct sk_buff *skb;
2875 while ((np->get_rx.ex != np->put_rx.ex) &&
2876 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2877 (rx_work < limit)) {
2880 * the packet is for us - immediately tear down the pci mapping.
2881 * TODO: check if a prefetch of the first cacheline improves
2884 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2885 np->get_rx_ctx->dma_len,
2886 PCI_DMA_FROMDEVICE);
2887 skb = np->get_rx_ctx->skb;
2888 np->get_rx_ctx->skb = NULL;
2890 /* look at what we actually got: */
2891 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2892 len = flags & LEN_MASK_V2;
2893 if (unlikely(flags & NV_RX2_ERROR)) {
2894 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2895 len = nv_getlen(dev, skb->data, len);
2901 /* framing errors are soft errors */
2902 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2903 if (flags & NV_RX2_SUBSTRACT1)
2906 /* the rest are hard errors */
2913 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2914 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2915 skb->ip_summed = CHECKSUM_UNNECESSARY;
2917 /* got a valid packet - forward it to the network core */
2919 skb->protocol = eth_type_trans(skb, dev);
2920 prefetch(skb->data);
2922 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2925 * There's need to check for NETIF_F_HW_VLAN_RX here.
2926 * Even if vlan rx accel is disabled,
2927 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2929 if (dev->features & NETIF_F_HW_VLAN_RX &&
2930 vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2931 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2933 __vlan_hwaccel_put_tag(skb, vid);
2935 napi_gro_receive(&np->napi, skb);
2936 u64_stats_update_begin(&np->swstats_rx_syncp);
2937 np->stat_rx_packets++;
2938 np->stat_rx_bytes += len;
2939 u64_stats_update_end(&np->swstats_rx_syncp);
2944 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2945 np->get_rx.ex = np->first_rx.ex;
2946 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2947 np->get_rx_ctx = np->first_rx_ctx;
2955 static void set_bufsize(struct net_device *dev)
2957 struct fe_priv *np = netdev_priv(dev);
2959 if (dev->mtu <= ETH_DATA_LEN)
2960 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2962 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2966 * nv_change_mtu: dev->change_mtu function
2967 * Called with dev_base_lock held for read.
2969 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2971 struct fe_priv *np = netdev_priv(dev);
2974 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2980 /* return early if the buffer sizes will not change */
2981 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2983 if (old_mtu == new_mtu)
2986 /* synchronized against open : rtnl_lock() held by caller */
2987 if (netif_running(dev)) {
2988 u8 __iomem *base = get_hwbase(dev);
2990 * It seems that the nic preloads valid ring entries into an
2991 * internal buffer. The procedure for flushing everything is
2992 * guessed, there is probably a simpler approach.
2993 * Changing the MTU is a rare event, it shouldn't matter.
2995 nv_disable_irq(dev);
2996 nv_napi_disable(dev);
2997 netif_tx_lock_bh(dev);
2998 netif_addr_lock(dev);
2999 spin_lock(&np->lock);
3003 /* drain rx queue */
3005 /* reinit driver view of the rx queue */
3007 if (nv_init_ring(dev)) {
3008 if (!np->in_shutdown)
3009 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3011 /* reinit nic view of the rx queue */
3012 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3013 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3014 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3015 base + NvRegRingSizes);
3017 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3020 /* restart rx engine */
3022 spin_unlock(&np->lock);
3023 netif_addr_unlock(dev);
3024 netif_tx_unlock_bh(dev);
3025 nv_napi_enable(dev);
3031 static void nv_copy_mac_to_hw(struct net_device *dev)
3033 u8 __iomem *base = get_hwbase(dev);
3036 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3037 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3038 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3040 writel(mac[0], base + NvRegMacAddrA);
3041 writel(mac[1], base + NvRegMacAddrB);
3045 * nv_set_mac_address: dev->set_mac_address function
3046 * Called with rtnl_lock() held.
3048 static int nv_set_mac_address(struct net_device *dev, void *addr)
3050 struct fe_priv *np = netdev_priv(dev);
3051 struct sockaddr *macaddr = (struct sockaddr *)addr;
3053 if (!is_valid_ether_addr(macaddr->sa_data))
3054 return -EADDRNOTAVAIL;
3056 /* synchronized against open : rtnl_lock() held by caller */
3057 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3058 dev->addr_assign_type &= ~NET_ADDR_RANDOM;
3060 if (netif_running(dev)) {
3061 netif_tx_lock_bh(dev);
3062 netif_addr_lock(dev);
3063 spin_lock_irq(&np->lock);
3065 /* stop rx engine */
3068 /* set mac address */
3069 nv_copy_mac_to_hw(dev);
3071 /* restart rx engine */
3073 spin_unlock_irq(&np->lock);
3074 netif_addr_unlock(dev);
3075 netif_tx_unlock_bh(dev);
3077 nv_copy_mac_to_hw(dev);
3083 * nv_set_multicast: dev->set_multicast function
3084 * Called with netif_tx_lock held.
3086 static void nv_set_multicast(struct net_device *dev)
3088 struct fe_priv *np = netdev_priv(dev);
3089 u8 __iomem *base = get_hwbase(dev);
3092 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3094 memset(addr, 0, sizeof(addr));
3095 memset(mask, 0, sizeof(mask));
3097 if (dev->flags & IFF_PROMISC) {
3098 pff |= NVREG_PFF_PROMISC;
3100 pff |= NVREG_PFF_MYADDR;
3102 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3106 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3107 if (dev->flags & IFF_ALLMULTI) {
3108 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3110 struct netdev_hw_addr *ha;
3112 netdev_for_each_mc_addr(ha, dev) {
3113 unsigned char *hw_addr = ha->addr;
3116 a = le32_to_cpu(*(__le32 *) hw_addr);
3117 b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3124 addr[0] = alwaysOn[0];
3125 addr[1] = alwaysOn[1];
3126 mask[0] = alwaysOn[0] | alwaysOff[0];
3127 mask[1] = alwaysOn[1] | alwaysOff[1];
3129 mask[0] = NVREG_MCASTMASKA_NONE;
3130 mask[1] = NVREG_MCASTMASKB_NONE;
3133 addr[0] |= NVREG_MCASTADDRA_FORCE;
3134 pff |= NVREG_PFF_ALWAYS;
3135 spin_lock_irq(&np->lock);
3137 writel(addr[0], base + NvRegMulticastAddrA);
3138 writel(addr[1], base + NvRegMulticastAddrB);
3139 writel(mask[0], base + NvRegMulticastMaskA);
3140 writel(mask[1], base + NvRegMulticastMaskB);
3141 writel(pff, base + NvRegPacketFilterFlags);
3143 spin_unlock_irq(&np->lock);
3146 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3148 struct fe_priv *np = netdev_priv(dev);
3149 u8 __iomem *base = get_hwbase(dev);
3151 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3153 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3154 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3155 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3156 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3157 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3159 writel(pff, base + NvRegPacketFilterFlags);
3162 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3163 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3164 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3165 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3166 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3167 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3168 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3169 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3170 /* limit the number of tx pause frames to a default of 8 */
3171 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3173 writel(pause_enable, base + NvRegTxPauseFrame);
3174 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3175 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3177 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3178 writel(regmisc, base + NvRegMisc1);
3183 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3185 struct fe_priv *np = netdev_priv(dev);
3186 u8 __iomem *base = get_hwbase(dev);
3190 np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3191 np->duplex = duplex;
3193 /* see if gigabit phy */
3194 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3195 if (mii_status & PHY_GIGABIT) {
3196 np->gigabit = PHY_GIGABIT;
3197 phyreg = readl(base + NvRegSlotTime);
3198 phyreg &= ~(0x3FF00);
3199 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3200 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3201 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3202 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3203 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3204 phyreg |= NVREG_SLOTTIME_1000_FULL;
3205 writel(phyreg, base + NvRegSlotTime);
3208 phyreg = readl(base + NvRegPhyInterface);
3209 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3210 if (np->duplex == 0)
3212 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3214 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3215 NVREG_LINKSPEED_1000)
3217 writel(phyreg, base + NvRegPhyInterface);
3219 if (phyreg & PHY_RGMII) {
3220 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3221 NVREG_LINKSPEED_1000)
3222 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3224 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3226 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3228 writel(txreg, base + NvRegTxDeferral);
3230 if (np->desc_ver == DESC_VER_1) {
3231 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3233 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3234 NVREG_LINKSPEED_1000)
3235 txreg = NVREG_TX_WM_DESC2_3_1000;
3237 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3239 writel(txreg, base + NvRegTxWatermark);
3241 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3244 writel(np->linkspeed, base + NvRegLinkSpeed);
3251 * nv_update_linkspeed - Setup the MAC according to the link partner
3252 * @dev: Network device to be configured
3254 * The function queries the PHY and checks if there is a link partner.
3255 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3256 * set to 10 MBit HD.
3258 * The function returns 0 if there is no link partner and 1 if there is
3259 * a good link partner.
3261 static int nv_update_linkspeed(struct net_device *dev)
3263 struct fe_priv *np = netdev_priv(dev);
3264 u8 __iomem *base = get_hwbase(dev);
3267 int adv_lpa, adv_pause, lpa_pause;
3268 int newls = np->linkspeed;
3269 int newdup = np->duplex;
3273 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3277 /* If device loopback is enabled, set carrier on and enable max link
3280 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3281 if (bmcr & BMCR_LOOPBACK) {
3282 if (netif_running(dev)) {
3283 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3284 if (!netif_carrier_ok(dev))
3285 netif_carrier_on(dev);
3290 /* BMSR_LSTATUS is latched, read it twice:
3291 * we want the current value.
3293 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3294 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3296 if (!(mii_status & BMSR_LSTATUS)) {
3297 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3303 if (np->autoneg == 0) {
3304 if (np->fixed_mode & LPA_100FULL) {
3305 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3307 } else if (np->fixed_mode & LPA_100HALF) {
3308 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3310 } else if (np->fixed_mode & LPA_10FULL) {
3311 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3314 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3320 /* check auto negotiation is complete */
3321 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3322 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3323 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3329 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3330 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3333 if (np->gigabit == PHY_GIGABIT) {
3334 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3335 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3337 if ((control_1000 & ADVERTISE_1000FULL) &&
3338 (status_1000 & LPA_1000FULL)) {
3339 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3345 /* FIXME: handle parallel detection properly */
3346 adv_lpa = lpa & adv;
3347 if (adv_lpa & LPA_100FULL) {
3348 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3350 } else if (adv_lpa & LPA_100HALF) {
3351 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3353 } else if (adv_lpa & LPA_10FULL) {
3354 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3356 } else if (adv_lpa & LPA_10HALF) {
3357 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3360 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3365 if (np->duplex == newdup && np->linkspeed == newls)
3368 np->duplex = newdup;
3369 np->linkspeed = newls;
3371 /* The transmitter and receiver must be restarted for safe update */
3372 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3373 txrxFlags |= NV_RESTART_TX;
3376 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3377 txrxFlags |= NV_RESTART_RX;
3381 if (np->gigabit == PHY_GIGABIT) {
3382 phyreg = readl(base + NvRegSlotTime);
3383 phyreg &= ~(0x3FF00);
3384 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3385 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3386 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3387 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3388 phyreg |= NVREG_SLOTTIME_1000_FULL;
3389 writel(phyreg, base + NvRegSlotTime);
3392 phyreg = readl(base + NvRegPhyInterface);
3393 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3394 if (np->duplex == 0)
3396 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3398 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3400 writel(phyreg, base + NvRegPhyInterface);
3402 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3403 if (phyreg & PHY_RGMII) {
3404 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3405 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3407 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3408 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3409 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3411 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3413 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3417 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3418 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3420 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3422 writel(txreg, base + NvRegTxDeferral);
3424 if (np->desc_ver == DESC_VER_1) {
3425 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3427 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3428 txreg = NVREG_TX_WM_DESC2_3_1000;
3430 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3432 writel(txreg, base + NvRegTxWatermark);
3434 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3437 writel(np->linkspeed, base + NvRegLinkSpeed);
3441 /* setup pause frame */
3442 if (netif_running(dev) && (np->duplex != 0)) {
3443 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3444 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3445 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3447 switch (adv_pause) {
3448 case ADVERTISE_PAUSE_CAP:
3449 if (lpa_pause & LPA_PAUSE_CAP) {
3450 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3451 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3452 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3455 case ADVERTISE_PAUSE_ASYM:
3456 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3457 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3459 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3460 if (lpa_pause & LPA_PAUSE_CAP) {
3461 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3462 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3463 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3465 if (lpa_pause == LPA_PAUSE_ASYM)
3466 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3470 pause_flags = np->pause_flags;
3473 nv_update_pause(dev, pause_flags);
3475 if (txrxFlags & NV_RESTART_TX)
3477 if (txrxFlags & NV_RESTART_RX)
3483 static void nv_linkchange(struct net_device *dev)
3485 if (nv_update_linkspeed(dev)) {
3486 if (!netif_carrier_ok(dev)) {
3487 netif_carrier_on(dev);
3488 netdev_info(dev, "link up\n");
3489 nv_txrx_gate(dev, false);
3493 if (netif_carrier_ok(dev)) {
3494 netif_carrier_off(dev);
3495 netdev_info(dev, "link down\n");
3496 nv_txrx_gate(dev, true);
3502 static void nv_link_irq(struct net_device *dev)
3504 u8 __iomem *base = get_hwbase(dev);
3507 miistat = readl(base + NvRegMIIStatus);
3508 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3510 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3514 static void nv_msi_workaround(struct fe_priv *np)
3517 /* Need to toggle the msi irq mask within the ethernet device,
3518 * otherwise, future interrupts will not be detected.
3520 if (np->msi_flags & NV_MSI_ENABLED) {
3521 u8 __iomem *base = np->base;
3523 writel(0, base + NvRegMSIIrqMask);
3524 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3528 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3530 struct fe_priv *np = netdev_priv(dev);
3532 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3533 if (total_work > NV_DYNAMIC_THRESHOLD) {
3534 /* transition to poll based interrupts */
3535 np->quiet_count = 0;
3536 if (np->irqmask != NVREG_IRQMASK_CPU) {
3537 np->irqmask = NVREG_IRQMASK_CPU;
3541 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3544 /* reached a period of low activity, switch
3545 to per tx/rx packet interrupts */
3546 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3547 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3556 static irqreturn_t nv_nic_irq(int foo, void *data)
3558 struct net_device *dev = (struct net_device *) data;
3559 struct fe_priv *np = netdev_priv(dev);
3560 u8 __iomem *base = get_hwbase(dev);
3562 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3563 np->events = readl(base + NvRegIrqStatus);
3564 writel(np->events, base + NvRegIrqStatus);
3566 np->events = readl(base + NvRegMSIXIrqStatus);
3567 writel(np->events, base + NvRegMSIXIrqStatus);
3569 if (!(np->events & np->irqmask))
3572 nv_msi_workaround(np);
3574 if (napi_schedule_prep(&np->napi)) {
3576 * Disable further irq's (msix not enabled with napi)
3578 writel(0, base + NvRegIrqMask);
3579 __napi_schedule(&np->napi);
3585 /* All _optimized functions are used to help increase performance
3586 * (reduce CPU and increase throughput). They use descripter version 3,
3587 * compiler directives, and reduce memory accesses.
3589 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3591 struct net_device *dev = (struct net_device *) data;
3592 struct fe_priv *np = netdev_priv(dev);
3593 u8 __iomem *base = get_hwbase(dev);
3595 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3596 np->events = readl(base + NvRegIrqStatus);
3597 writel(np->events, base + NvRegIrqStatus);
3599 np->events = readl(base + NvRegMSIXIrqStatus);
3600 writel(np->events, base + NvRegMSIXIrqStatus);
3602 if (!(np->events & np->irqmask))
3605 nv_msi_workaround(np);
3607 if (napi_schedule_prep(&np->napi)) {
3609 * Disable further irq's (msix not enabled with napi)
3611 writel(0, base + NvRegIrqMask);
3612 __napi_schedule(&np->napi);
3618 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3620 struct net_device *dev = (struct net_device *) data;
3621 struct fe_priv *np = netdev_priv(dev);
3622 u8 __iomem *base = get_hwbase(dev);
3625 unsigned long flags;
3628 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3629 writel(events, base + NvRegMSIXIrqStatus);
3630 netdev_dbg(dev, "tx irq events: %08x\n", events);
3631 if (!(events & np->irqmask))
3634 spin_lock_irqsave(&np->lock, flags);
3635 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3636 spin_unlock_irqrestore(&np->lock, flags);
3638 if (unlikely(i > max_interrupt_work)) {
3639 spin_lock_irqsave(&np->lock, flags);
3640 /* disable interrupts on the nic */
3641 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3644 if (!np->in_shutdown) {
3645 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3646 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3648 spin_unlock_irqrestore(&np->lock, flags);
3649 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3656 return IRQ_RETVAL(i);
3659 static int nv_napi_poll(struct napi_struct *napi, int budget)
3661 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3662 struct net_device *dev = np->dev;
3663 u8 __iomem *base = get_hwbase(dev);
3664 unsigned long flags;
3666 int rx_count, tx_work = 0, rx_work = 0;
3669 if (!nv_optimized(np)) {
3670 spin_lock_irqsave(&np->lock, flags);
3671 tx_work += nv_tx_done(dev, np->tx_ring_size);
3672 spin_unlock_irqrestore(&np->lock, flags);
3674 rx_count = nv_rx_process(dev, budget - rx_work);
3675 retcode = nv_alloc_rx(dev);
3677 spin_lock_irqsave(&np->lock, flags);
3678 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3679 spin_unlock_irqrestore(&np->lock, flags);
3681 rx_count = nv_rx_process_optimized(dev,
3683 retcode = nv_alloc_rx_optimized(dev);
3685 } while (retcode == 0 &&
3686 rx_count > 0 && (rx_work += rx_count) < budget);
3689 spin_lock_irqsave(&np->lock, flags);
3690 if (!np->in_shutdown)
3691 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3692 spin_unlock_irqrestore(&np->lock, flags);
3695 nv_change_interrupt_mode(dev, tx_work + rx_work);
3697 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3698 spin_lock_irqsave(&np->lock, flags);
3700 spin_unlock_irqrestore(&np->lock, flags);
3702 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3703 spin_lock_irqsave(&np->lock, flags);
3705 spin_unlock_irqrestore(&np->lock, flags);
3706 np->link_timeout = jiffies + LINK_TIMEOUT;
3708 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3709 spin_lock_irqsave(&np->lock, flags);
3710 if (!np->in_shutdown) {
3711 np->nic_poll_irq = np->irqmask;
3712 np->recover_error = 1;
3713 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3715 spin_unlock_irqrestore(&np->lock, flags);
3716 napi_complete(napi);
3720 if (rx_work < budget) {
3721 /* re-enable interrupts
3722 (msix not enabled in napi) */
3723 napi_complete(napi);
3725 writel(np->irqmask, base + NvRegIrqMask);
3730 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3732 struct net_device *dev = (struct net_device *) data;
3733 struct fe_priv *np = netdev_priv(dev);
3734 u8 __iomem *base = get_hwbase(dev);
3737 unsigned long flags;
3740 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3741 writel(events, base + NvRegMSIXIrqStatus);
3742 netdev_dbg(dev, "rx irq events: %08x\n", events);
3743 if (!(events & np->irqmask))
3746 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3747 if (unlikely(nv_alloc_rx_optimized(dev))) {
3748 spin_lock_irqsave(&np->lock, flags);
3749 if (!np->in_shutdown)
3750 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3751 spin_unlock_irqrestore(&np->lock, flags);
3755 if (unlikely(i > max_interrupt_work)) {
3756 spin_lock_irqsave(&np->lock, flags);
3757 /* disable interrupts on the nic */
3758 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3761 if (!np->in_shutdown) {
3762 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3763 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3765 spin_unlock_irqrestore(&np->lock, flags);
3766 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3772 return IRQ_RETVAL(i);
3775 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3777 struct net_device *dev = (struct net_device *) data;
3778 struct fe_priv *np = netdev_priv(dev);
3779 u8 __iomem *base = get_hwbase(dev);
3782 unsigned long flags;
3785 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3786 writel(events, base + NvRegMSIXIrqStatus);
3787 netdev_dbg(dev, "irq events: %08x\n", events);
3788 if (!(events & np->irqmask))
3791 /* check tx in case we reached max loop limit in tx isr */
3792 spin_lock_irqsave(&np->lock, flags);
3793 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3794 spin_unlock_irqrestore(&np->lock, flags);
3796 if (events & NVREG_IRQ_LINK) {
3797 spin_lock_irqsave(&np->lock, flags);
3799 spin_unlock_irqrestore(&np->lock, flags);
3801 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3802 spin_lock_irqsave(&np->lock, flags);
3804 spin_unlock_irqrestore(&np->lock, flags);
3805 np->link_timeout = jiffies + LINK_TIMEOUT;
3807 if (events & NVREG_IRQ_RECOVER_ERROR) {
3808 spin_lock_irqsave(&np->lock, flags);
3809 /* disable interrupts on the nic */
3810 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3813 if (!np->in_shutdown) {
3814 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3815 np->recover_error = 1;
3816 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3818 spin_unlock_irqrestore(&np->lock, flags);
3821 if (unlikely(i > max_interrupt_work)) {
3822 spin_lock_irqsave(&np->lock, flags);
3823 /* disable interrupts on the nic */
3824 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3827 if (!np->in_shutdown) {
3828 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3829 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3831 spin_unlock_irqrestore(&np->lock, flags);
3832 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3839 return IRQ_RETVAL(i);
3842 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3844 struct net_device *dev = (struct net_device *) data;
3845 struct fe_priv *np = netdev_priv(dev);
3846 u8 __iomem *base = get_hwbase(dev);
3849 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3850 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3851 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3853 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3854 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3857 if (!(events & NVREG_IRQ_TIMER))
3858 return IRQ_RETVAL(0);
3860 nv_msi_workaround(np);
3862 spin_lock(&np->lock);
3864 spin_unlock(&np->lock);
3866 return IRQ_RETVAL(1);
3869 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3871 u8 __iomem *base = get_hwbase(dev);
3875 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3876 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3877 * the remaining 8 interrupts.
3879 for (i = 0; i < 8; i++) {
3880 if ((irqmask >> i) & 0x1)
3881 msixmap |= vector << (i << 2);
3883 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3886 for (i = 0; i < 8; i++) {
3887 if ((irqmask >> (i + 8)) & 0x1)
3888 msixmap |= vector << (i << 2);
3890 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3893 static int nv_request_irq(struct net_device *dev, int intr_test)
3895 struct fe_priv *np = get_nvpriv(dev);
3896 u8 __iomem *base = get_hwbase(dev);
3899 irqreturn_t (*handler)(int foo, void *data);
3902 handler = nv_nic_irq_test;
3904 if (nv_optimized(np))
3905 handler = nv_nic_irq_optimized;
3907 handler = nv_nic_irq;
3910 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3911 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3912 np->msi_x_entry[i].entry = i;
3913 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3915 np->msi_flags |= NV_MSI_X_ENABLED;
3916 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3917 /* Request irq for rx handling */
3918 sprintf(np->name_rx, "%s-rx", dev->name);
3919 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3920 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3922 "request_irq failed for rx %d\n",
3924 pci_disable_msix(np->pci_dev);
3925 np->msi_flags &= ~NV_MSI_X_ENABLED;
3928 /* Request irq for tx handling */
3929 sprintf(np->name_tx, "%s-tx", dev->name);
3930 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3931 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3933 "request_irq failed for tx %d\n",
3935 pci_disable_msix(np->pci_dev);
3936 np->msi_flags &= ~NV_MSI_X_ENABLED;
3939 /* Request irq for link and timer handling */
3940 sprintf(np->name_other, "%s-other", dev->name);
3941 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3942 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3944 "request_irq failed for link %d\n",
3946 pci_disable_msix(np->pci_dev);
3947 np->msi_flags &= ~NV_MSI_X_ENABLED;
3950 /* map interrupts to their respective vector */
3951 writel(0, base + NvRegMSIXMap0);
3952 writel(0, base + NvRegMSIXMap1);
3953 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3954 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3955 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3957 /* Request irq for all interrupts */
3958 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3960 "request_irq failed %d\n",
3962 pci_disable_msix(np->pci_dev);
3963 np->msi_flags &= ~NV_MSI_X_ENABLED;
3967 /* map interrupts to vector 0 */
3968 writel(0, base + NvRegMSIXMap0);
3969 writel(0, base + NvRegMSIXMap1);
3971 netdev_info(dev, "MSI-X enabled\n");
3974 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3975 ret = pci_enable_msi(np->pci_dev);
3977 np->msi_flags |= NV_MSI_ENABLED;
3978 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3979 netdev_info(dev, "request_irq failed %d\n",
3981 pci_disable_msi(np->pci_dev);
3982 np->msi_flags &= ~NV_MSI_ENABLED;
3986 /* map interrupts to vector 0 */
3987 writel(0, base + NvRegMSIMap0);
3988 writel(0, base + NvRegMSIMap1);
3989 /* enable msi vector 0 */
3990 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3991 netdev_info(dev, "MSI enabled\n");
3995 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4002 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4004 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4009 static void nv_free_irq(struct net_device *dev)
4011 struct fe_priv *np = get_nvpriv(dev);
4014 if (np->msi_flags & NV_MSI_X_ENABLED) {
4015 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
4016 free_irq(np->msi_x_entry[i].vector, dev);
4017 pci_disable_msix(np->pci_dev);
4018 np->msi_flags &= ~NV_MSI_X_ENABLED;
4020 free_irq(np->pci_dev->irq, dev);
4021 if (np->msi_flags & NV_MSI_ENABLED) {
4022 pci_disable_msi(np->pci_dev);
4023 np->msi_flags &= ~NV_MSI_ENABLED;
4028 static void nv_do_nic_poll(unsigned long data)
4030 struct net_device *dev = (struct net_device *) data;
4031 struct fe_priv *np = netdev_priv(dev);
4032 u8 __iomem *base = get_hwbase(dev);
4036 * First disable irq(s) and then
4037 * reenable interrupts on the nic, we have to do this before calling
4038 * nv_nic_irq because that may decide to do otherwise
4041 if (!using_multi_irqs(dev)) {
4042 if (np->msi_flags & NV_MSI_X_ENABLED)
4043 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4045 disable_irq_lockdep(np->pci_dev->irq);
4048 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4049 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4050 mask |= NVREG_IRQ_RX_ALL;
4052 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4053 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4054 mask |= NVREG_IRQ_TX_ALL;
4056 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4057 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4058 mask |= NVREG_IRQ_OTHER;
4061 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4063 if (np->recover_error) {
4064 np->recover_error = 0;
4065 netdev_info(dev, "MAC in recoverable error state\n");
4066 if (netif_running(dev)) {
4067 netif_tx_lock_bh(dev);
4068 netif_addr_lock(dev);
4069 spin_lock(&np->lock);
4072 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4075 /* drain rx queue */
4077 /* reinit driver view of the rx queue */
4079 if (nv_init_ring(dev)) {
4080 if (!np->in_shutdown)
4081 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4083 /* reinit nic view of the rx queue */
4084 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4085 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4086 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4087 base + NvRegRingSizes);
4089 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4091 /* clear interrupts */
4092 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4093 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4095 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4097 /* restart rx engine */
4099 spin_unlock(&np->lock);
4100 netif_addr_unlock(dev);
4101 netif_tx_unlock_bh(dev);
4105 writel(mask, base + NvRegIrqMask);
4108 if (!using_multi_irqs(dev)) {
4109 np->nic_poll_irq = 0;
4110 if (nv_optimized(np))
4111 nv_nic_irq_optimized(0, dev);
4114 if (np->msi_flags & NV_MSI_X_ENABLED)
4115 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4117 enable_irq_lockdep(np->pci_dev->irq);
4119 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4120 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4121 nv_nic_irq_rx(0, dev);
4122 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4124 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4125 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4126 nv_nic_irq_tx(0, dev);
4127 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4129 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4130 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4131 nv_nic_irq_other(0, dev);
4132 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4138 #ifdef CONFIG_NET_POLL_CONTROLLER
4139 static void nv_poll_controller(struct net_device *dev)
4141 nv_do_nic_poll((unsigned long) dev);
4145 static void nv_do_stats_poll(unsigned long data)
4146 __acquires(&netdev_priv(dev)->hwstats_lock)
4147 __releases(&netdev_priv(dev)->hwstats_lock)
4149 struct net_device *dev = (struct net_device *) data;
4150 struct fe_priv *np = netdev_priv(dev);
4152 /* If lock is currently taken, the stats are being refreshed
4153 * and hence fresh enough */
4154 if (spin_trylock(&np->hwstats_lock)) {
4155 nv_update_stats(dev);
4156 spin_unlock(&np->hwstats_lock);
4159 if (!np->in_shutdown)
4160 mod_timer(&np->stats_poll,
4161 round_jiffies(jiffies + STATS_INTERVAL));
4164 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4166 struct fe_priv *np = netdev_priv(dev);
4167 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4168 strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4169 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4172 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4174 struct fe_priv *np = netdev_priv(dev);
4175 wolinfo->supported = WAKE_MAGIC;
4177 spin_lock_irq(&np->lock);
4179 wolinfo->wolopts = WAKE_MAGIC;
4180 spin_unlock_irq(&np->lock);
4183 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4185 struct fe_priv *np = netdev_priv(dev);
4186 u8 __iomem *base = get_hwbase(dev);
4189 if (wolinfo->wolopts == 0) {
4191 } else if (wolinfo->wolopts & WAKE_MAGIC) {
4193 flags = NVREG_WAKEUPFLAGS_ENABLE;
4195 if (netif_running(dev)) {
4196 spin_lock_irq(&np->lock);
4197 writel(flags, base + NvRegWakeUpFlags);
4198 spin_unlock_irq(&np->lock);
4200 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4204 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4206 struct fe_priv *np = netdev_priv(dev);
4210 spin_lock_irq(&np->lock);
4211 ecmd->port = PORT_MII;
4212 if (!netif_running(dev)) {
4213 /* We do not track link speed / duplex setting if the
4214 * interface is disabled. Force a link check */
4215 if (nv_update_linkspeed(dev)) {
4216 if (!netif_carrier_ok(dev))
4217 netif_carrier_on(dev);
4219 if (netif_carrier_ok(dev))
4220 netif_carrier_off(dev);
4224 if (netif_carrier_ok(dev)) {
4225 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4226 case NVREG_LINKSPEED_10:
4229 case NVREG_LINKSPEED_100:
4232 case NVREG_LINKSPEED_1000:
4239 ecmd->duplex = DUPLEX_HALF;
4241 ecmd->duplex = DUPLEX_FULL;
4246 ethtool_cmd_speed_set(ecmd, speed);
4247 ecmd->autoneg = np->autoneg;
4249 ecmd->advertising = ADVERTISED_MII;
4251 ecmd->advertising |= ADVERTISED_Autoneg;
4252 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4253 if (adv & ADVERTISE_10HALF)
4254 ecmd->advertising |= ADVERTISED_10baseT_Half;
4255 if (adv & ADVERTISE_10FULL)
4256 ecmd->advertising |= ADVERTISED_10baseT_Full;
4257 if (adv & ADVERTISE_100HALF)
4258 ecmd->advertising |= ADVERTISED_100baseT_Half;
4259 if (adv & ADVERTISE_100FULL)
4260 ecmd->advertising |= ADVERTISED_100baseT_Full;
4261 if (np->gigabit == PHY_GIGABIT) {
4262 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4263 if (adv & ADVERTISE_1000FULL)
4264 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4267 ecmd->supported = (SUPPORTED_Autoneg |
4268 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4269 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4271 if (np->gigabit == PHY_GIGABIT)
4272 ecmd->supported |= SUPPORTED_1000baseT_Full;
4274 ecmd->phy_address = np->phyaddr;
4275 ecmd->transceiver = XCVR_EXTERNAL;
4277 /* ignore maxtxpkt, maxrxpkt for now */
4278 spin_unlock_irq(&np->lock);
4282 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4284 struct fe_priv *np = netdev_priv(dev);
4285 u32 speed = ethtool_cmd_speed(ecmd);
4287 if (ecmd->port != PORT_MII)
4289 if (ecmd->transceiver != XCVR_EXTERNAL)
4291 if (ecmd->phy_address != np->phyaddr) {
4292 /* TODO: support switching between multiple phys. Should be
4293 * trivial, but not enabled due to lack of test hardware. */
4296 if (ecmd->autoneg == AUTONEG_ENABLE) {
4299 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4300 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4301 if (np->gigabit == PHY_GIGABIT)
4302 mask |= ADVERTISED_1000baseT_Full;
4304 if ((ecmd->advertising & mask) == 0)
4307 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4308 /* Note: autonegotiation disable, speed 1000 intentionally
4309 * forbidden - no one should need that. */
4311 if (speed != SPEED_10 && speed != SPEED_100)
4313 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4319 netif_carrier_off(dev);
4320 if (netif_running(dev)) {
4321 unsigned long flags;
4323 nv_disable_irq(dev);
4324 netif_tx_lock_bh(dev);
4325 netif_addr_lock(dev);
4326 /* with plain spinlock lockdep complains */
4327 spin_lock_irqsave(&np->lock, flags);
4330 * this can take some time, and interrupts are disabled
4331 * due to spin_lock_irqsave, but let's hope no daemon
4332 * is going to change the settings very often...
4334 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4335 * + some minor delays, which is up to a second approximately
4338 spin_unlock_irqrestore(&np->lock, flags);
4339 netif_addr_unlock(dev);
4340 netif_tx_unlock_bh(dev);
4343 if (ecmd->autoneg == AUTONEG_ENABLE) {
4348 /* advertise only what has been requested */
4349 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4350 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4351 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4352 adv |= ADVERTISE_10HALF;
4353 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4354 adv |= ADVERTISE_10FULL;
4355 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4356 adv |= ADVERTISE_100HALF;
4357 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4358 adv |= ADVERTISE_100FULL;
4359 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4360 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4361 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4362 adv |= ADVERTISE_PAUSE_ASYM;
4363 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4365 if (np->gigabit == PHY_GIGABIT) {
4366 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4367 adv &= ~ADVERTISE_1000FULL;
4368 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4369 adv |= ADVERTISE_1000FULL;
4370 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4373 if (netif_running(dev))
4374 netdev_info(dev, "link down\n");
4375 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4376 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4377 bmcr |= BMCR_ANENABLE;
4378 /* reset the phy in order for settings to stick,
4379 * and cause autoneg to start */
4380 if (phy_reset(dev, bmcr)) {
4381 netdev_info(dev, "phy reset failed\n");
4385 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4386 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4393 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4394 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4395 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4396 adv |= ADVERTISE_10HALF;
4397 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4398 adv |= ADVERTISE_10FULL;
4399 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4400 adv |= ADVERTISE_100HALF;
4401 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4402 adv |= ADVERTISE_100FULL;
4403 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4404 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4405 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4406 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4408 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4409 adv |= ADVERTISE_PAUSE_ASYM;
4410 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4412 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4413 np->fixed_mode = adv;
4415 if (np->gigabit == PHY_GIGABIT) {
4416 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4417 adv &= ~ADVERTISE_1000FULL;
4418 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4421 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4422 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4423 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4424 bmcr |= BMCR_FULLDPLX;
4425 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4426 bmcr |= BMCR_SPEED100;
4427 if (np->phy_oui == PHY_OUI_MARVELL) {
4428 /* reset the phy in order for forced mode settings to stick */
4429 if (phy_reset(dev, bmcr)) {
4430 netdev_info(dev, "phy reset failed\n");
4434 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4435 if (netif_running(dev)) {
4436 /* Wait a bit and then reconfigure the nic. */
4443 if (netif_running(dev)) {
4451 #define FORCEDETH_REGS_VER 1
4453 static int nv_get_regs_len(struct net_device *dev)
4455 struct fe_priv *np = netdev_priv(dev);
4456 return np->register_size;
4459 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4461 struct fe_priv *np = netdev_priv(dev);
4462 u8 __iomem *base = get_hwbase(dev);
4466 regs->version = FORCEDETH_REGS_VER;
4467 spin_lock_irq(&np->lock);
4468 for (i = 0; i < np->register_size/sizeof(u32); i++)
4469 rbuf[i] = readl(base + i*sizeof(u32));
4470 spin_unlock_irq(&np->lock);
4473 static int nv_nway_reset(struct net_device *dev)
4475 struct fe_priv *np = netdev_priv(dev);
4481 netif_carrier_off(dev);
4482 if (netif_running(dev)) {
4483 nv_disable_irq(dev);
4484 netif_tx_lock_bh(dev);
4485 netif_addr_lock(dev);
4486 spin_lock(&np->lock);
4489 spin_unlock(&np->lock);
4490 netif_addr_unlock(dev);
4491 netif_tx_unlock_bh(dev);
4492 netdev_info(dev, "link down\n");
4495 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4496 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4497 bmcr |= BMCR_ANENABLE;
4498 /* reset the phy in order for settings to stick*/
4499 if (phy_reset(dev, bmcr)) {
4500 netdev_info(dev, "phy reset failed\n");
4504 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4505 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4508 if (netif_running(dev)) {
4520 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4522 struct fe_priv *np = netdev_priv(dev);
4524 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4525 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4527 ring->rx_pending = np->rx_ring_size;
4528 ring->tx_pending = np->tx_ring_size;
4531 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4533 struct fe_priv *np = netdev_priv(dev);
4534 u8 __iomem *base = get_hwbase(dev);
4535 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4536 dma_addr_t ring_addr;
4538 if (ring->rx_pending < RX_RING_MIN ||
4539 ring->tx_pending < TX_RING_MIN ||
4540 ring->rx_mini_pending != 0 ||
4541 ring->rx_jumbo_pending != 0 ||
4542 (np->desc_ver == DESC_VER_1 &&
4543 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4544 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4545 (np->desc_ver != DESC_VER_1 &&
4546 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4547 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4551 /* allocate new rings */
4552 if (!nv_optimized(np)) {
4553 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4554 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4557 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4558 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4561 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4562 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4563 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4564 /* fall back to old rings */
4565 if (!nv_optimized(np)) {
4567 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4568 rxtx_ring, ring_addr);
4571 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4572 rxtx_ring, ring_addr);
4580 if (netif_running(dev)) {
4581 nv_disable_irq(dev);
4582 nv_napi_disable(dev);
4583 netif_tx_lock_bh(dev);
4584 netif_addr_lock(dev);
4585 spin_lock(&np->lock);
4595 /* set new values */
4596 np->rx_ring_size = ring->rx_pending;
4597 np->tx_ring_size = ring->tx_pending;
4599 if (!nv_optimized(np)) {
4600 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4601 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4603 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4604 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4606 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4607 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4608 np->ring_addr = ring_addr;
4610 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4611 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4613 if (netif_running(dev)) {
4614 /* reinit driver view of the queues */
4616 if (nv_init_ring(dev)) {
4617 if (!np->in_shutdown)
4618 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4621 /* reinit nic view of the queues */
4622 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4623 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4624 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4625 base + NvRegRingSizes);
4627 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4630 /* restart engines */
4632 spin_unlock(&np->lock);
4633 netif_addr_unlock(dev);
4634 netif_tx_unlock_bh(dev);
4635 nv_napi_enable(dev);
4643 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4645 struct fe_priv *np = netdev_priv(dev);
4647 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4648 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4649 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4652 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4654 struct fe_priv *np = netdev_priv(dev);
4657 if ((!np->autoneg && np->duplex == 0) ||
4658 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4659 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4662 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4663 netdev_info(dev, "hardware does not support tx pause frames\n");
4667 netif_carrier_off(dev);
4668 if (netif_running(dev)) {
4669 nv_disable_irq(dev);
4670 netif_tx_lock_bh(dev);
4671 netif_addr_lock(dev);
4672 spin_lock(&np->lock);
4675 spin_unlock(&np->lock);
4676 netif_addr_unlock(dev);
4677 netif_tx_unlock_bh(dev);
4680 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4681 if (pause->rx_pause)
4682 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4683 if (pause->tx_pause)
4684 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4686 if (np->autoneg && pause->autoneg) {
4687 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4689 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4690 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4691 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4692 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4693 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4694 adv |= ADVERTISE_PAUSE_ASYM;
4695 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4697 if (netif_running(dev))
4698 netdev_info(dev, "link down\n");
4699 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4700 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4701 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4703 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4704 if (pause->rx_pause)
4705 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4706 if (pause->tx_pause)
4707 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4709 if (!netif_running(dev))
4710 nv_update_linkspeed(dev);
4712 nv_update_pause(dev, np->pause_flags);
4715 if (netif_running(dev)) {
4722 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4724 struct fe_priv *np = netdev_priv(dev);
4725 unsigned long flags;
4727 int err, retval = 0;
4729 spin_lock_irqsave(&np->lock, flags);
4730 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4731 if (features & NETIF_F_LOOPBACK) {
4732 if (miicontrol & BMCR_LOOPBACK) {
4733 spin_unlock_irqrestore(&np->lock, flags);
4734 netdev_info(dev, "Loopback already enabled\n");
4737 nv_disable_irq(dev);
4738 /* Turn on loopback mode */
4739 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4740 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4743 spin_unlock_irqrestore(&np->lock, flags);
4746 if (netif_running(dev)) {
4747 /* Force 1000 Mbps full-duplex */
4748 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4751 netif_carrier_on(dev);
4753 spin_unlock_irqrestore(&np->lock, flags);
4755 "Internal PHY loopback mode enabled.\n");
4758 if (!(miicontrol & BMCR_LOOPBACK)) {
4759 spin_unlock_irqrestore(&np->lock, flags);
4760 netdev_info(dev, "Loopback already disabled\n");
4763 nv_disable_irq(dev);
4764 /* Turn off loopback */
4765 spin_unlock_irqrestore(&np->lock, flags);
4766 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4770 spin_lock_irqsave(&np->lock, flags);
4772 spin_unlock_irqrestore(&np->lock, flags);
4777 static netdev_features_t nv_fix_features(struct net_device *dev,
4778 netdev_features_t features)
4780 /* vlan is dependent on rx checksum offload */
4781 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4782 features |= NETIF_F_RXCSUM;
4787 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4789 struct fe_priv *np = get_nvpriv(dev);
4791 spin_lock_irq(&np->lock);
4793 if (features & NETIF_F_HW_VLAN_RX)
4794 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4796 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4798 if (features & NETIF_F_HW_VLAN_TX)
4799 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4801 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4803 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4805 spin_unlock_irq(&np->lock);
4808 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4810 struct fe_priv *np = netdev_priv(dev);
4811 u8 __iomem *base = get_hwbase(dev);
4812 netdev_features_t changed = dev->features ^ features;
4815 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4816 retval = nv_set_loopback(dev, features);
4821 if (changed & NETIF_F_RXCSUM) {
4822 spin_lock_irq(&np->lock);
4824 if (features & NETIF_F_RXCSUM)
4825 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4827 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4829 if (netif_running(dev))
4830 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4832 spin_unlock_irq(&np->lock);
4835 if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4836 nv_vlan_mode(dev, features);
4841 static int nv_get_sset_count(struct net_device *dev, int sset)
4843 struct fe_priv *np = netdev_priv(dev);
4847 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4848 return NV_TEST_COUNT_EXTENDED;
4850 return NV_TEST_COUNT_BASE;
4852 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4853 return NV_DEV_STATISTICS_V3_COUNT;
4854 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4855 return NV_DEV_STATISTICS_V2_COUNT;
4856 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4857 return NV_DEV_STATISTICS_V1_COUNT;
4865 static void nv_get_ethtool_stats(struct net_device *dev,
4866 struct ethtool_stats *estats, u64 *buffer)
4867 __acquires(&netdev_priv(dev)->hwstats_lock)
4868 __releases(&netdev_priv(dev)->hwstats_lock)
4870 struct fe_priv *np = netdev_priv(dev);
4872 spin_lock_bh(&np->hwstats_lock);
4873 nv_update_stats(dev);
4874 memcpy(buffer, &np->estats,
4875 nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4876 spin_unlock_bh(&np->hwstats_lock);
4879 static int nv_link_test(struct net_device *dev)
4881 struct fe_priv *np = netdev_priv(dev);
4884 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4885 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4887 /* check phy link status */
4888 if (!(mii_status & BMSR_LSTATUS))
4894 static int nv_register_test(struct net_device *dev)
4896 u8 __iomem *base = get_hwbase(dev);
4898 u32 orig_read, new_read;
4901 orig_read = readl(base + nv_registers_test[i].reg);
4903 /* xor with mask to toggle bits */
4904 orig_read ^= nv_registers_test[i].mask;
4906 writel(orig_read, base + nv_registers_test[i].reg);
4908 new_read = readl(base + nv_registers_test[i].reg);
4910 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4913 /* restore original value */
4914 orig_read ^= nv_registers_test[i].mask;
4915 writel(orig_read, base + nv_registers_test[i].reg);
4917 } while (nv_registers_test[++i].reg != 0);
4922 static int nv_interrupt_test(struct net_device *dev)
4924 struct fe_priv *np = netdev_priv(dev);
4925 u8 __iomem *base = get_hwbase(dev);
4928 u32 save_msi_flags, save_poll_interval = 0;
4930 if (netif_running(dev)) {
4931 /* free current irq */
4933 save_poll_interval = readl(base+NvRegPollingInterval);
4936 /* flag to test interrupt handler */
4939 /* setup test irq */
4940 save_msi_flags = np->msi_flags;
4941 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4942 np->msi_flags |= 0x001; /* setup 1 vector */
4943 if (nv_request_irq(dev, 1))
4946 /* setup timer interrupt */
4947 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4948 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4950 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4952 /* wait for at least one interrupt */
4955 spin_lock_irq(&np->lock);
4957 /* flag should be set within ISR */
4958 testcnt = np->intr_test;
4962 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4963 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4964 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4966 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4968 spin_unlock_irq(&np->lock);
4972 np->msi_flags = save_msi_flags;
4974 if (netif_running(dev)) {
4975 writel(save_poll_interval, base + NvRegPollingInterval);
4976 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4977 /* restore original irq */
4978 if (nv_request_irq(dev, 0))
4985 static int nv_loopback_test(struct net_device *dev)
4987 struct fe_priv *np = netdev_priv(dev);
4988 u8 __iomem *base = get_hwbase(dev);
4989 struct sk_buff *tx_skb, *rx_skb;
4990 dma_addr_t test_dma_addr;
4991 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4993 int len, i, pkt_len;
4995 u32 filter_flags = 0;
4996 u32 misc1_flags = 0;
4999 if (netif_running(dev)) {
5000 nv_disable_irq(dev);
5001 filter_flags = readl(base + NvRegPacketFilterFlags);
5002 misc1_flags = readl(base + NvRegMisc1);
5007 /* reinit driver view of the rx queue */
5011 /* setup hardware for loopback */
5012 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5013 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5015 /* reinit nic view of the rx queue */
5016 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5017 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5018 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5019 base + NvRegRingSizes);
5022 /* restart rx engine */
5025 /* setup packet for tx */
5026 pkt_len = ETH_DATA_LEN;
5027 tx_skb = netdev_alloc_skb(dev, pkt_len);
5029 netdev_err(dev, "netdev_alloc_skb() failed during loopback test\n");
5033 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5034 skb_tailroom(tx_skb),
5035 PCI_DMA_FROMDEVICE);
5036 if (pci_dma_mapping_error(np->pci_dev,
5038 dev_kfree_skb_any(tx_skb);
5041 pkt_data = skb_put(tx_skb, pkt_len);
5042 for (i = 0; i < pkt_len; i++)
5043 pkt_data[i] = (u8)(i & 0xff);
5045 if (!nv_optimized(np)) {
5046 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5047 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5049 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5050 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5051 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5053 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5054 pci_push(get_hwbase(dev));
5058 /* check for rx of the packet */
5059 if (!nv_optimized(np)) {
5060 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5061 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5064 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5065 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5068 if (flags & NV_RX_AVAIL) {
5070 } else if (np->desc_ver == DESC_VER_1) {
5071 if (flags & NV_RX_ERROR)
5074 if (flags & NV_RX2_ERROR)
5079 if (len != pkt_len) {
5082 rx_skb = np->rx_skb[0].skb;
5083 for (i = 0; i < pkt_len; i++) {
5084 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5092 pci_unmap_single(np->pci_dev, test_dma_addr,
5093 (skb_end_pointer(tx_skb) - tx_skb->data),
5095 dev_kfree_skb_any(tx_skb);
5100 /* drain rx queue */
5103 if (netif_running(dev)) {
5104 writel(misc1_flags, base + NvRegMisc1);
5105 writel(filter_flags, base + NvRegPacketFilterFlags);
5112 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5114 struct fe_priv *np = netdev_priv(dev);
5115 u8 __iomem *base = get_hwbase(dev);
5117 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5119 if (!nv_link_test(dev)) {
5120 test->flags |= ETH_TEST_FL_FAILED;
5124 if (test->flags & ETH_TEST_FL_OFFLINE) {
5125 if (netif_running(dev)) {
5126 netif_stop_queue(dev);
5127 nv_napi_disable(dev);
5128 netif_tx_lock_bh(dev);
5129 netif_addr_lock(dev);
5130 spin_lock_irq(&np->lock);
5131 nv_disable_hw_interrupts(dev, np->irqmask);
5132 if (!(np->msi_flags & NV_MSI_X_ENABLED))
5133 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5135 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5139 /* drain rx queue */
5141 spin_unlock_irq(&np->lock);
5142 netif_addr_unlock(dev);
5143 netif_tx_unlock_bh(dev);
5146 if (!nv_register_test(dev)) {
5147 test->flags |= ETH_TEST_FL_FAILED;
5151 result = nv_interrupt_test(dev);
5153 test->flags |= ETH_TEST_FL_FAILED;
5161 if (!nv_loopback_test(dev)) {
5162 test->flags |= ETH_TEST_FL_FAILED;
5166 if (netif_running(dev)) {
5167 /* reinit driver view of the rx queue */
5169 if (nv_init_ring(dev)) {
5170 if (!np->in_shutdown)
5171 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5173 /* reinit nic view of the rx queue */
5174 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5175 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5176 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5177 base + NvRegRingSizes);
5179 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5181 /* restart rx engine */
5183 netif_start_queue(dev);
5184 nv_napi_enable(dev);
5185 nv_enable_hw_interrupts(dev, np->irqmask);
5190 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5192 switch (stringset) {
5194 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5197 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5202 static const struct ethtool_ops ops = {
5203 .get_drvinfo = nv_get_drvinfo,
5204 .get_link = ethtool_op_get_link,
5205 .get_wol = nv_get_wol,
5206 .set_wol = nv_set_wol,
5207 .get_settings = nv_get_settings,
5208 .set_settings = nv_set_settings,
5209 .get_regs_len = nv_get_regs_len,
5210 .get_regs = nv_get_regs,
5211 .nway_reset = nv_nway_reset,
5212 .get_ringparam = nv_get_ringparam,
5213 .set_ringparam = nv_set_ringparam,
5214 .get_pauseparam = nv_get_pauseparam,
5215 .set_pauseparam = nv_set_pauseparam,
5216 .get_strings = nv_get_strings,
5217 .get_ethtool_stats = nv_get_ethtool_stats,
5218 .get_sset_count = nv_get_sset_count,
5219 .self_test = nv_self_test,
5220 .get_ts_info = ethtool_op_get_ts_info,
5223 /* The mgmt unit and driver use a semaphore to access the phy during init */
5224 static int nv_mgmt_acquire_sema(struct net_device *dev)
5226 struct fe_priv *np = netdev_priv(dev);
5227 u8 __iomem *base = get_hwbase(dev);
5229 u32 tx_ctrl, mgmt_sema;
5231 for (i = 0; i < 10; i++) {
5232 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5233 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5238 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5241 for (i = 0; i < 2; i++) {
5242 tx_ctrl = readl(base + NvRegTransmitterControl);
5243 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5244 writel(tx_ctrl, base + NvRegTransmitterControl);
5246 /* verify that semaphore was acquired */
5247 tx_ctrl = readl(base + NvRegTransmitterControl);
5248 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5249 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5259 static void nv_mgmt_release_sema(struct net_device *dev)
5261 struct fe_priv *np = netdev_priv(dev);
5262 u8 __iomem *base = get_hwbase(dev);
5265 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5266 if (np->mgmt_sema) {
5267 tx_ctrl = readl(base + NvRegTransmitterControl);
5268 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5269 writel(tx_ctrl, base + NvRegTransmitterControl);
5275 static int nv_mgmt_get_version(struct net_device *dev)
5277 struct fe_priv *np = netdev_priv(dev);
5278 u8 __iomem *base = get_hwbase(dev);
5279 u32 data_ready = readl(base + NvRegTransmitterControl);
5280 u32 data_ready2 = 0;
5281 unsigned long start;
5284 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5285 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5287 while (time_before(jiffies, start + 5*HZ)) {
5288 data_ready2 = readl(base + NvRegTransmitterControl);
5289 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5293 schedule_timeout_uninterruptible(1);
5296 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5299 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5304 static int nv_open(struct net_device *dev)
5306 struct fe_priv *np = netdev_priv(dev);
5307 u8 __iomem *base = get_hwbase(dev);
5313 mii_rw(dev, np->phyaddr, MII_BMCR,
5314 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5316 nv_txrx_gate(dev, false);
5317 /* erase previous misconfiguration */
5318 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5320 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5321 writel(0, base + NvRegMulticastAddrB);
5322 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5323 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5324 writel(0, base + NvRegPacketFilterFlags);
5326 writel(0, base + NvRegTransmitterControl);
5327 writel(0, base + NvRegReceiverControl);
5329 writel(0, base + NvRegAdapterControl);
5331 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5332 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5334 /* initialize descriptor rings */
5336 oom = nv_init_ring(dev);
5338 writel(0, base + NvRegLinkSpeed);
5339 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5341 writel(0, base + NvRegUnknownSetupReg6);
5343 np->in_shutdown = 0;
5346 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5347 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5348 base + NvRegRingSizes);
5350 writel(np->linkspeed, base + NvRegLinkSpeed);
5351 if (np->desc_ver == DESC_VER_1)
5352 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5354 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5355 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5356 writel(np->vlanctl_bits, base + NvRegVlanControl);
5358 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5359 if (reg_delay(dev, NvRegUnknownSetupReg5,
5360 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5361 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5363 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5365 writel(0, base + NvRegMIIMask);
5366 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5367 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5369 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5370 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5371 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5372 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5374 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5376 get_random_bytes(&low, sizeof(low));
5377 low &= NVREG_SLOTTIME_MASK;
5378 if (np->desc_ver == DESC_VER_1) {
5379 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5381 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5382 /* setup legacy backoff */
5383 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5385 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5386 nv_gear_backoff_reseed(dev);
5389 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5390 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5391 if (poll_interval == -1) {
5392 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5393 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5395 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5397 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5398 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5399 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5400 base + NvRegAdapterControl);
5401 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5402 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5404 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5406 i = readl(base + NvRegPowerState);
5407 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5408 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5412 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5414 nv_disable_hw_interrupts(dev, np->irqmask);
5416 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5417 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5420 if (nv_request_irq(dev, 0))
5423 /* ask for interrupts */
5424 nv_enable_hw_interrupts(dev, np->irqmask);
5426 spin_lock_irq(&np->lock);
5427 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5428 writel(0, base + NvRegMulticastAddrB);
5429 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5430 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5431 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5432 /* One manual link speed update: Interrupts are enabled, future link
5433 * speed changes cause interrupts and are handled by nv_link_irq().
5437 miistat = readl(base + NvRegMIIStatus);
5438 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5440 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5443 ret = nv_update_linkspeed(dev);
5445 netif_start_queue(dev);
5446 nv_napi_enable(dev);
5449 netif_carrier_on(dev);
5451 netdev_info(dev, "no link during initialization\n");
5452 netif_carrier_off(dev);
5455 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5457 /* start statistics timer */
5458 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5459 mod_timer(&np->stats_poll,
5460 round_jiffies(jiffies + STATS_INTERVAL));
5462 spin_unlock_irq(&np->lock);
5464 /* If the loopback feature was set while the device was down, make sure
5465 * that it's set correctly now.
5467 if (dev->features & NETIF_F_LOOPBACK)
5468 nv_set_loopback(dev, dev->features);
5476 static int nv_close(struct net_device *dev)
5478 struct fe_priv *np = netdev_priv(dev);
5481 spin_lock_irq(&np->lock);
5482 np->in_shutdown = 1;
5483 spin_unlock_irq(&np->lock);
5484 nv_napi_disable(dev);
5485 synchronize_irq(np->pci_dev->irq);
5487 del_timer_sync(&np->oom_kick);
5488 del_timer_sync(&np->nic_poll);
5489 del_timer_sync(&np->stats_poll);
5491 netif_stop_queue(dev);
5492 spin_lock_irq(&np->lock);
5493 nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */
5497 /* disable interrupts on the nic or we will lock up */
5498 base = get_hwbase(dev);
5499 nv_disable_hw_interrupts(dev, np->irqmask);
5502 spin_unlock_irq(&np->lock);
5508 if (np->wolenabled || !phy_power_down) {
5509 nv_txrx_gate(dev, false);
5510 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5513 /* power down phy */
5514 mii_rw(dev, np->phyaddr, MII_BMCR,
5515 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5516 nv_txrx_gate(dev, true);
5519 /* FIXME: power down nic */
5524 static const struct net_device_ops nv_netdev_ops = {
5525 .ndo_open = nv_open,
5526 .ndo_stop = nv_close,
5527 .ndo_get_stats64 = nv_get_stats64,
5528 .ndo_start_xmit = nv_start_xmit,
5529 .ndo_tx_timeout = nv_tx_timeout,
5530 .ndo_change_mtu = nv_change_mtu,
5531 .ndo_fix_features = nv_fix_features,
5532 .ndo_set_features = nv_set_features,
5533 .ndo_validate_addr = eth_validate_addr,
5534 .ndo_set_mac_address = nv_set_mac_address,
5535 .ndo_set_rx_mode = nv_set_multicast,
5536 #ifdef CONFIG_NET_POLL_CONTROLLER
5537 .ndo_poll_controller = nv_poll_controller,
5541 static const struct net_device_ops nv_netdev_ops_optimized = {
5542 .ndo_open = nv_open,
5543 .ndo_stop = nv_close,
5544 .ndo_get_stats64 = nv_get_stats64,
5545 .ndo_start_xmit = nv_start_xmit_optimized,
5546 .ndo_tx_timeout = nv_tx_timeout,
5547 .ndo_change_mtu = nv_change_mtu,
5548 .ndo_fix_features = nv_fix_features,
5549 .ndo_set_features = nv_set_features,
5550 .ndo_validate_addr = eth_validate_addr,
5551 .ndo_set_mac_address = nv_set_mac_address,
5552 .ndo_set_rx_mode = nv_set_multicast,
5553 #ifdef CONFIG_NET_POLL_CONTROLLER
5554 .ndo_poll_controller = nv_poll_controller,
5558 static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5560 struct net_device *dev;
5565 u32 powerstate, txreg;
5566 u32 phystate_orig = 0, phystate;
5567 int phyinitialized = 0;
5568 static int printed_version;
5570 if (!printed_version++)
5571 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5574 dev = alloc_etherdev(sizeof(struct fe_priv));
5579 np = netdev_priv(dev);
5581 np->pci_dev = pci_dev;
5582 spin_lock_init(&np->lock);
5583 spin_lock_init(&np->hwstats_lock);
5584 SET_NETDEV_DEV(dev, &pci_dev->dev);
5586 init_timer(&np->oom_kick);
5587 np->oom_kick.data = (unsigned long) dev;
5588 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5589 init_timer(&np->nic_poll);
5590 np->nic_poll.data = (unsigned long) dev;
5591 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5592 init_timer_deferrable(&np->stats_poll);
5593 np->stats_poll.data = (unsigned long) dev;
5594 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5596 err = pci_enable_device(pci_dev);
5600 pci_set_master(pci_dev);
5602 err = pci_request_regions(pci_dev, DRV_NAME);
5606 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5607 np->register_size = NV_PCI_REGSZ_VER3;
5608 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5609 np->register_size = NV_PCI_REGSZ_VER2;
5611 np->register_size = NV_PCI_REGSZ_VER1;
5615 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5616 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5617 pci_resource_len(pci_dev, i) >= np->register_size) {
5618 addr = pci_resource_start(pci_dev, i);
5622 if (i == DEVICE_COUNT_RESOURCE) {
5623 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5627 /* copy of driver data */
5628 np->driver_data = id->driver_data;
5629 /* copy of device id */
5630 np->device_id = id->device;
5632 /* handle different descriptor versions */
5633 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5634 /* packet format 3: supports 40-bit addressing */
5635 np->desc_ver = DESC_VER_3;
5636 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5638 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5639 dev_info(&pci_dev->dev,
5640 "64-bit DMA failed, using 32-bit addressing\n");
5642 dev->features |= NETIF_F_HIGHDMA;
5643 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5644 dev_info(&pci_dev->dev,
5645 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5648 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5649 /* packet format 2: supports jumbo frames */
5650 np->desc_ver = DESC_VER_2;
5651 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5653 /* original packet format */
5654 np->desc_ver = DESC_VER_1;
5655 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5658 np->pkt_limit = NV_PKTLIMIT_1;
5659 if (id->driver_data & DEV_HAS_LARGEDESC)
5660 np->pkt_limit = NV_PKTLIMIT_2;
5662 if (id->driver_data & DEV_HAS_CHECKSUM) {
5663 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5664 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5665 NETIF_F_TSO | NETIF_F_RXCSUM;
5668 np->vlanctl_bits = 0;
5669 if (id->driver_data & DEV_HAS_VLAN) {
5670 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5671 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5674 dev->features |= dev->hw_features;
5676 /* Add loopback capability to the device. */
5677 dev->hw_features |= NETIF_F_LOOPBACK;
5679 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5680 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5681 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5682 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5683 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5687 np->base = ioremap(addr, np->register_size);
5691 np->rx_ring_size = RX_RING_DEFAULT;
5692 np->tx_ring_size = TX_RING_DEFAULT;
5694 if (!nv_optimized(np)) {
5695 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5696 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5698 if (!np->rx_ring.orig)
5700 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5702 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5703 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5705 if (!np->rx_ring.ex)
5707 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5709 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5710 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5711 if (!np->rx_skb || !np->tx_skb)
5714 if (!nv_optimized(np))
5715 dev->netdev_ops = &nv_netdev_ops;
5717 dev->netdev_ops = &nv_netdev_ops_optimized;
5719 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5720 SET_ETHTOOL_OPS(dev, &ops);
5721 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5723 pci_set_drvdata(pci_dev, dev);
5725 /* read the mac address */
5726 base = get_hwbase(dev);
5727 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5728 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5730 /* check the workaround bit for correct mac address order */
5731 txreg = readl(base + NvRegTransmitPoll);
5732 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5733 /* mac address is already in correct order */
5734 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5735 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5736 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5737 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5738 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5739 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5740 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5741 /* mac address is already in correct order */
5742 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5743 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5744 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5745 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5746 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5747 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5749 * Set orig mac address back to the reversed version.
5750 * This flag will be cleared during low power transition.
5751 * Therefore, we should always put back the reversed address.
5753 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5754 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5755 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5757 /* need to reverse mac address to correct order */
5758 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5759 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5760 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5761 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5762 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5763 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5764 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5765 dev_dbg(&pci_dev->dev,
5766 "%s: set workaround bit for reversed mac addr\n",
5769 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5771 if (!is_valid_ether_addr(dev->perm_addr)) {
5773 * Bad mac address. At least one bios sets the mac address
5774 * to 01:23:45:67:89:ab
5776 dev_err(&pci_dev->dev,
5777 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5779 eth_hw_addr_random(dev);
5780 dev_err(&pci_dev->dev,
5781 "Using random MAC address: %pM\n", dev->dev_addr);
5784 /* set mac address */
5785 nv_copy_mac_to_hw(dev);
5788 writel(0, base + NvRegWakeUpFlags);
5790 device_set_wakeup_enable(&pci_dev->dev, false);
5792 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5794 /* take phy and nic out of low power mode */
5795 powerstate = readl(base + NvRegPowerState2);
5796 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5797 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5798 pci_dev->revision >= 0xA3)
5799 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5800 writel(powerstate, base + NvRegPowerState2);
5803 if (np->desc_ver == DESC_VER_1)
5804 np->tx_flags = NV_TX_VALID;
5806 np->tx_flags = NV_TX2_VALID;
5809 if ((id->driver_data & DEV_HAS_MSI) && msi)
5810 np->msi_flags |= NV_MSI_CAPABLE;
5812 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5813 /* msix has had reported issues when modifying irqmask
5814 as in the case of napi, therefore, disable for now
5817 np->msi_flags |= NV_MSI_X_CAPABLE;
5821 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5822 np->irqmask = NVREG_IRQMASK_CPU;
5823 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5824 np->msi_flags |= 0x0001;
5825 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5826 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5827 /* start off in throughput mode */
5828 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5829 /* remove support for msix mode */
5830 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5832 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5833 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5834 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5835 np->msi_flags |= 0x0003;
5838 if (id->driver_data & DEV_NEED_TIMERIRQ)
5839 np->irqmask |= NVREG_IRQ_TIMER;
5840 if (id->driver_data & DEV_NEED_LINKTIMER) {
5841 np->need_linktimer = 1;
5842 np->link_timeout = jiffies + LINK_TIMEOUT;
5844 np->need_linktimer = 0;
5847 /* Limit the number of tx's outstanding for hw bug */
5848 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5850 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5851 pci_dev->revision >= 0xA2)
5855 /* clear phy state and temporarily halt phy interrupts */
5856 writel(0, base + NvRegMIIMask);
5857 phystate = readl(base + NvRegAdapterControl);
5858 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5860 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5861 writel(phystate, base + NvRegAdapterControl);
5863 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5865 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5866 /* management unit running on the mac? */
5867 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5868 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5869 nv_mgmt_acquire_sema(dev) &&
5870 nv_mgmt_get_version(dev)) {
5872 if (np->mgmt_version > 0)
5873 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5874 /* management unit setup the phy already? */
5875 if (np->mac_in_use &&
5876 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5877 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5878 /* phy is inited by mgmt unit */
5881 /* we need to init the phy */
5886 /* find a suitable phy */
5887 for (i = 1; i <= 32; i++) {
5889 int phyaddr = i & 0x1F;
5891 spin_lock_irq(&np->lock);
5892 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5893 spin_unlock_irq(&np->lock);
5894 if (id1 < 0 || id1 == 0xffff)
5896 spin_lock_irq(&np->lock);
5897 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5898 spin_unlock_irq(&np->lock);
5899 if (id2 < 0 || id2 == 0xffff)
5902 np->phy_model = id2 & PHYID2_MODEL_MASK;
5903 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5904 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5905 np->phyaddr = phyaddr;
5906 np->phy_oui = id1 | id2;
5908 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5909 if (np->phy_oui == PHY_OUI_REALTEK2)
5910 np->phy_oui = PHY_OUI_REALTEK;
5911 /* Setup phy revision for Realtek */
5912 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5913 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5918 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5922 if (!phyinitialized) {
5926 /* see if it is a gigabit phy */
5927 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5928 if (mii_status & PHY_GIGABIT)
5929 np->gigabit = PHY_GIGABIT;
5932 /* set default link speed settings */
5933 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5937 err = register_netdev(dev);
5939 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5943 netif_carrier_off(dev);
5945 /* Some NICs freeze when TX pause is enabled while NIC is
5946 * down, and this stays across warm reboots. The sequence
5947 * below should be enough to recover from that state.
5949 nv_update_pause(dev, 0);
5953 if (id->driver_data & DEV_HAS_VLAN)
5954 nv_vlan_mode(dev, dev->features);
5956 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5957 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5959 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5960 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5961 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5963 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5965 dev->features & (NETIF_F_LOOPBACK) ?
5967 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5968 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5969 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5970 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5971 np->need_linktimer ? "lnktim " : "",
5972 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5973 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5980 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5981 pci_set_drvdata(pci_dev, NULL);
5985 iounmap(get_hwbase(dev));
5987 pci_release_regions(pci_dev);
5989 pci_disable_device(pci_dev);
5996 static void nv_restore_phy(struct net_device *dev)
5998 struct fe_priv *np = netdev_priv(dev);
5999 u16 phy_reserved, mii_control;
6001 if (np->phy_oui == PHY_OUI_REALTEK &&
6002 np->phy_model == PHY_MODEL_REALTEK_8201 &&
6003 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6004 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6005 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6006 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6007 phy_reserved |= PHY_REALTEK_INIT8;
6008 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6009 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6011 /* restart auto negotiation */
6012 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6013 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6014 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6018 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6020 struct net_device *dev = pci_get_drvdata(pci_dev);
6021 struct fe_priv *np = netdev_priv(dev);
6022 u8 __iomem *base = get_hwbase(dev);
6024 /* special op: write back the misordered MAC address - otherwise
6025 * the next nv_probe would see a wrong address.
6027 writel(np->orig_mac[0], base + NvRegMacAddrA);
6028 writel(np->orig_mac[1], base + NvRegMacAddrB);
6029 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6030 base + NvRegTransmitPoll);
6033 static void nv_remove(struct pci_dev *pci_dev)
6035 struct net_device *dev = pci_get_drvdata(pci_dev);
6037 unregister_netdev(dev);
6039 nv_restore_mac_addr(pci_dev);
6041 /* restore any phy related changes */
6042 nv_restore_phy(dev);
6044 nv_mgmt_release_sema(dev);
6046 /* free all structures */
6048 iounmap(get_hwbase(dev));
6049 pci_release_regions(pci_dev);
6050 pci_disable_device(pci_dev);
6052 pci_set_drvdata(pci_dev, NULL);
6055 #ifdef CONFIG_PM_SLEEP
6056 static int nv_suspend(struct device *device)
6058 struct pci_dev *pdev = to_pci_dev(device);
6059 struct net_device *dev = pci_get_drvdata(pdev);
6060 struct fe_priv *np = netdev_priv(dev);
6061 u8 __iomem *base = get_hwbase(dev);
6064 if (netif_running(dev)) {
6068 netif_device_detach(dev);
6070 /* save non-pci configuration space */
6071 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6072 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6077 static int nv_resume(struct device *device)
6079 struct pci_dev *pdev = to_pci_dev(device);
6080 struct net_device *dev = pci_get_drvdata(pdev);
6081 struct fe_priv *np = netdev_priv(dev);
6082 u8 __iomem *base = get_hwbase(dev);
6085 /* restore non-pci configuration space */
6086 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6087 writel(np->saved_config_space[i], base+i*sizeof(u32));
6089 if (np->driver_data & DEV_NEED_MSI_FIX)
6090 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6092 /* restore phy state, including autoneg */
6095 netif_device_attach(dev);
6096 if (netif_running(dev)) {
6098 nv_set_multicast(dev);
6103 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6104 #define NV_PM_OPS (&nv_pm_ops)
6107 #define NV_PM_OPS NULL
6108 #endif /* CONFIG_PM_SLEEP */
6111 static void nv_shutdown(struct pci_dev *pdev)
6113 struct net_device *dev = pci_get_drvdata(pdev);
6114 struct fe_priv *np = netdev_priv(dev);
6116 if (netif_running(dev))
6120 * Restore the MAC so a kernel started by kexec won't get confused.
6121 * If we really go for poweroff, we must not restore the MAC,
6122 * otherwise the MAC for WOL will be reversed at least on some boards.
6124 if (system_state != SYSTEM_POWER_OFF)
6125 nv_restore_mac_addr(pdev);
6127 pci_disable_device(pdev);
6129 * Apparently it is not possible to reinitialise from D3 hot,
6130 * only put the device into D3 if we really go for poweroff.
6132 if (system_state == SYSTEM_POWER_OFF) {
6133 pci_wake_from_d3(pdev, np->wolenabled);
6134 pci_set_power_state(pdev, PCI_D3hot);
6138 #define nv_shutdown NULL
6139 #endif /* CONFIG_PM */
6141 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6142 { /* nForce Ethernet Controller */
6143 PCI_DEVICE(0x10DE, 0x01C3),
6144 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6146 { /* nForce2 Ethernet Controller */
6147 PCI_DEVICE(0x10DE, 0x0066),
6148 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6150 { /* nForce3 Ethernet Controller */
6151 PCI_DEVICE(0x10DE, 0x00D6),
6152 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6154 { /* nForce3 Ethernet Controller */
6155 PCI_DEVICE(0x10DE, 0x0086),
6156 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6158 { /* nForce3 Ethernet Controller */
6159 PCI_DEVICE(0x10DE, 0x008C),
6160 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6162 { /* nForce3 Ethernet Controller */
6163 PCI_DEVICE(0x10DE, 0x00E6),
6164 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6166 { /* nForce3 Ethernet Controller */
6167 PCI_DEVICE(0x10DE, 0x00DF),
6168 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6170 { /* CK804 Ethernet Controller */
6171 PCI_DEVICE(0x10DE, 0x0056),
6172 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6174 { /* CK804 Ethernet Controller */
6175 PCI_DEVICE(0x10DE, 0x0057),
6176 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6178 { /* MCP04 Ethernet Controller */
6179 PCI_DEVICE(0x10DE, 0x0037),
6180 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6182 { /* MCP04 Ethernet Controller */
6183 PCI_DEVICE(0x10DE, 0x0038),
6184 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6186 { /* MCP51 Ethernet Controller */
6187 PCI_DEVICE(0x10DE, 0x0268),
6188 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6190 { /* MCP51 Ethernet Controller */
6191 PCI_DEVICE(0x10DE, 0x0269),
6192 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6194 { /* MCP55 Ethernet Controller */
6195 PCI_DEVICE(0x10DE, 0x0372),
6196 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6198 { /* MCP55 Ethernet Controller */
6199 PCI_DEVICE(0x10DE, 0x0373),
6200 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6202 { /* MCP61 Ethernet Controller */
6203 PCI_DEVICE(0x10DE, 0x03E5),
6204 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6206 { /* MCP61 Ethernet Controller */
6207 PCI_DEVICE(0x10DE, 0x03E6),
6208 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6210 { /* MCP61 Ethernet Controller */
6211 PCI_DEVICE(0x10DE, 0x03EE),
6212 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6214 { /* MCP61 Ethernet Controller */
6215 PCI_DEVICE(0x10DE, 0x03EF),
6216 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6218 { /* MCP65 Ethernet Controller */
6219 PCI_DEVICE(0x10DE, 0x0450),
6220 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6222 { /* MCP65 Ethernet Controller */
6223 PCI_DEVICE(0x10DE, 0x0451),
6224 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6226 { /* MCP65 Ethernet Controller */
6227 PCI_DEVICE(0x10DE, 0x0452),
6228 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6230 { /* MCP65 Ethernet Controller */
6231 PCI_DEVICE(0x10DE, 0x0453),
6232 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6234 { /* MCP67 Ethernet Controller */
6235 PCI_DEVICE(0x10DE, 0x054C),
6236 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6238 { /* MCP67 Ethernet Controller */
6239 PCI_DEVICE(0x10DE, 0x054D),
6240 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6242 { /* MCP67 Ethernet Controller */
6243 PCI_DEVICE(0x10DE, 0x054E),
6244 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6246 { /* MCP67 Ethernet Controller */
6247 PCI_DEVICE(0x10DE, 0x054F),
6248 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6250 { /* MCP73 Ethernet Controller */
6251 PCI_DEVICE(0x10DE, 0x07DC),
6252 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6254 { /* MCP73 Ethernet Controller */
6255 PCI_DEVICE(0x10DE, 0x07DD),
6256 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6258 { /* MCP73 Ethernet Controller */
6259 PCI_DEVICE(0x10DE, 0x07DE),
6260 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6262 { /* MCP73 Ethernet Controller */
6263 PCI_DEVICE(0x10DE, 0x07DF),
6264 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6266 { /* MCP77 Ethernet Controller */
6267 PCI_DEVICE(0x10DE, 0x0760),
6268 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6270 { /* MCP77 Ethernet Controller */
6271 PCI_DEVICE(0x10DE, 0x0761),
6272 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6274 { /* MCP77 Ethernet Controller */
6275 PCI_DEVICE(0x10DE, 0x0762),
6276 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6278 { /* MCP77 Ethernet Controller */
6279 PCI_DEVICE(0x10DE, 0x0763),
6280 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6282 { /* MCP79 Ethernet Controller */
6283 PCI_DEVICE(0x10DE, 0x0AB0),
6284 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6286 { /* MCP79 Ethernet Controller */
6287 PCI_DEVICE(0x10DE, 0x0AB1),
6288 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6290 { /* MCP79 Ethernet Controller */
6291 PCI_DEVICE(0x10DE, 0x0AB2),
6292 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6294 { /* MCP79 Ethernet Controller */
6295 PCI_DEVICE(0x10DE, 0x0AB3),
6296 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6298 { /* MCP89 Ethernet Controller */
6299 PCI_DEVICE(0x10DE, 0x0D7D),
6300 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6305 static struct pci_driver driver = {
6307 .id_table = pci_tbl,
6309 .remove = nv_remove,
6310 .shutdown = nv_shutdown,
6311 .driver.pm = NV_PM_OPS,
6314 static int __init init_nic(void)
6316 return pci_register_driver(&driver);
6319 static void __exit exit_nic(void)
6321 pci_unregister_driver(&driver);
6324 module_param(max_interrupt_work, int, 0);
6325 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6326 module_param(optimization_mode, int, 0);
6327 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6328 module_param(poll_interval, int, 0);
6329 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6330 module_param(msi, int, 0);
6331 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6332 module_param(msix, int, 0);
6333 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6334 module_param(dma_64bit, int, 0);
6335 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6336 module_param(phy_cross, int, 0);
6337 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6338 module_param(phy_power_down, int, 0);
6339 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6340 module_param(debug_tx_timeout, bool, 0);
6341 MODULE_PARM_DESC(debug_tx_timeout,
6342 "Dump tx related registers and ring when tx_timeout happens");
6344 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6345 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6346 MODULE_LICENSE("GPL");
6348 MODULE_DEVICE_TABLE(pci, pci_tbl);
6350 module_init(init_nic);
6351 module_exit(exit_nic);