2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qla3xxx for copyright and licensing details.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/kthread.h>
23 #include <linux/interrupt.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
28 #include <linux/if_arp.h>
29 #include <linux/if_ether.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/rtnetlink.h>
35 #include <linux/if_vlan.h>
36 #include <linux/delay.h>
38 #include <linux/prefetch.h>
42 #define DRV_NAME "qla3xxx"
43 #define DRV_STRING "QLogic ISP3XXX Network Driver"
44 #define DRV_VERSION "v2.03.00-k5"
46 static const char ql3xxx_driver_name[] = DRV_NAME;
47 static const char ql3xxx_driver_version[] = DRV_VERSION;
49 #define TIMED_OUT_MSG \
50 "Timed out waiting for management port to get free before issuing command\n"
52 MODULE_AUTHOR("QLogic Corporation");
53 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
54 MODULE_LICENSE("GPL");
55 MODULE_VERSION(DRV_VERSION);
57 static const u32 default_msg
58 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
59 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
61 static int debug = -1; /* defaults above */
62 module_param(debug, int, 0);
63 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
66 module_param(msi, int, 0);
67 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
69 static DEFINE_PCI_DEVICE_TABLE(ql3xxx_pci_tbl) = {
70 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
71 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
72 /* required last entry */
76 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
79 * These are the known PHY's which are used
81 enum PHY_DEVICE_TYPE {
88 struct PHY_DEVICE_INFO {
89 const enum PHY_DEVICE_TYPE phyDevice;
95 static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
96 {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
97 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
98 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
103 * Caller must take hw_lock.
105 static int ql_sem_spinlock(struct ql3_adapter *qdev,
106 u32 sem_mask, u32 sem_bits)
108 struct ql3xxx_port_registers __iomem *port_regs =
109 qdev->mem_map_registers;
111 unsigned int seconds = 3;
114 writel((sem_mask | sem_bits),
115 &port_regs->CommonRegs.semaphoreReg);
116 value = readl(&port_regs->CommonRegs.semaphoreReg);
117 if ((value & (sem_mask >> 16)) == sem_bits)
124 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
126 struct ql3xxx_port_registers __iomem *port_regs =
127 qdev->mem_map_registers;
128 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
129 readl(&port_regs->CommonRegs.semaphoreReg);
132 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
134 struct ql3xxx_port_registers __iomem *port_regs =
135 qdev->mem_map_registers;
138 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
139 value = readl(&port_regs->CommonRegs.semaphoreReg);
140 return ((value & (sem_mask >> 16)) == sem_bits);
144 * Caller holds hw_lock.
146 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
154 if (ql_sem_lock(qdev,
156 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
158 netdev_printk(KERN_DEBUG, qdev->ndev,
159 "driver lock acquired\n");
164 netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
168 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
170 struct ql3xxx_port_registers __iomem *port_regs =
171 qdev->mem_map_registers;
173 writel(((ISP_CONTROL_NP_MASK << 16) | page),
174 &port_regs->CommonRegs.ispControlStatus);
175 readl(&port_regs->CommonRegs.ispControlStatus);
176 qdev->current_page = page;
179 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
182 unsigned long hw_flags;
184 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
186 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
191 static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
196 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
199 unsigned long hw_flags;
201 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
203 if (qdev->current_page != 0)
204 ql_set_register_page(qdev, 0);
207 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
211 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
213 if (qdev->current_page != 0)
214 ql_set_register_page(qdev, 0);
218 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
219 u32 __iomem *reg, u32 value)
221 unsigned long hw_flags;
223 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
226 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
229 static void ql_write_common_reg(struct ql3_adapter *qdev,
230 u32 __iomem *reg, u32 value)
236 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
237 u32 __iomem *reg, u32 value)
244 static void ql_write_page0_reg(struct ql3_adapter *qdev,
245 u32 __iomem *reg, u32 value)
247 if (qdev->current_page != 0)
248 ql_set_register_page(qdev, 0);
254 * Caller holds hw_lock. Only called during init.
256 static void ql_write_page1_reg(struct ql3_adapter *qdev,
257 u32 __iomem *reg, u32 value)
259 if (qdev->current_page != 1)
260 ql_set_register_page(qdev, 1);
266 * Caller holds hw_lock. Only called during init.
268 static void ql_write_page2_reg(struct ql3_adapter *qdev,
269 u32 __iomem *reg, u32 value)
271 if (qdev->current_page != 2)
272 ql_set_register_page(qdev, 2);
277 static void ql_disable_interrupts(struct ql3_adapter *qdev)
279 struct ql3xxx_port_registers __iomem *port_regs =
280 qdev->mem_map_registers;
282 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
283 (ISP_IMR_ENABLE_INT << 16));
287 static void ql_enable_interrupts(struct ql3_adapter *qdev)
289 struct ql3xxx_port_registers __iomem *port_regs =
290 qdev->mem_map_registers;
292 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
293 ((0xff << 16) | ISP_IMR_ENABLE_INT));
297 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
298 struct ql_rcv_buf_cb *lrg_buf_cb)
302 lrg_buf_cb->next = NULL;
304 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
305 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
307 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
308 qdev->lrg_buf_free_tail = lrg_buf_cb;
311 if (!lrg_buf_cb->skb) {
312 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
313 qdev->lrg_buffer_len);
314 if (unlikely(!lrg_buf_cb->skb)) {
315 netdev_err(qdev->ndev, "failed netdev_alloc_skb()\n");
316 qdev->lrg_buf_skb_check++;
319 * We save some space to copy the ethhdr from first
322 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
323 map = pci_map_single(qdev->pdev,
324 lrg_buf_cb->skb->data,
325 qdev->lrg_buffer_len -
328 err = pci_dma_mapping_error(qdev->pdev, map);
330 netdev_err(qdev->ndev,
331 "PCI mapping failed with error: %d\n",
333 dev_kfree_skb(lrg_buf_cb->skb);
334 lrg_buf_cb->skb = NULL;
336 qdev->lrg_buf_skb_check++;
340 lrg_buf_cb->buf_phy_addr_low =
341 cpu_to_le32(LS_64BITS(map));
342 lrg_buf_cb->buf_phy_addr_high =
343 cpu_to_le32(MS_64BITS(map));
344 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
345 dma_unmap_len_set(lrg_buf_cb, maplen,
346 qdev->lrg_buffer_len -
351 qdev->lrg_buf_free_count++;
354 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
357 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
359 if (lrg_buf_cb != NULL) {
360 qdev->lrg_buf_free_head = lrg_buf_cb->next;
361 if (qdev->lrg_buf_free_head == NULL)
362 qdev->lrg_buf_free_tail = NULL;
363 qdev->lrg_buf_free_count--;
369 static u32 addrBits = EEPROM_NO_ADDR_BITS;
370 static u32 dataBits = EEPROM_NO_DATA_BITS;
372 static void fm93c56a_deselect(struct ql3_adapter *qdev);
373 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
374 unsigned short *value);
377 * Caller holds hw_lock.
379 static void fm93c56a_select(struct ql3_adapter *qdev)
381 struct ql3xxx_port_registers __iomem *port_regs =
382 qdev->mem_map_registers;
383 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
385 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
386 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
387 ql_write_nvram_reg(qdev, spir,
388 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
392 * Caller holds hw_lock.
394 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
400 struct ql3xxx_port_registers __iomem *port_regs =
401 qdev->mem_map_registers;
402 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
404 /* Clock in a zero, then do the start bit */
405 ql_write_nvram_reg(qdev, spir,
406 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
407 AUBURN_EEPROM_DO_1));
408 ql_write_nvram_reg(qdev, spir,
409 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
410 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
411 ql_write_nvram_reg(qdev, spir,
412 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
413 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
415 mask = 1 << (FM93C56A_CMD_BITS - 1);
416 /* Force the previous data bit to be different */
417 previousBit = 0xffff;
418 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
419 dataBit = (cmd & mask)
421 : AUBURN_EEPROM_DO_0;
422 if (previousBit != dataBit) {
423 /* If the bit changed, change the DO state to match */
424 ql_write_nvram_reg(qdev, spir,
426 qdev->eeprom_cmd_data | dataBit));
427 previousBit = dataBit;
429 ql_write_nvram_reg(qdev, spir,
430 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
431 dataBit | AUBURN_EEPROM_CLK_RISE));
432 ql_write_nvram_reg(qdev, spir,
433 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
434 dataBit | AUBURN_EEPROM_CLK_FALL));
438 mask = 1 << (addrBits - 1);
439 /* Force the previous data bit to be different */
440 previousBit = 0xffff;
441 for (i = 0; i < addrBits; i++) {
442 dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
443 : AUBURN_EEPROM_DO_0;
444 if (previousBit != dataBit) {
446 * If the bit changed, then change the DO state to
449 ql_write_nvram_reg(qdev, spir,
451 qdev->eeprom_cmd_data | dataBit));
452 previousBit = dataBit;
454 ql_write_nvram_reg(qdev, spir,
455 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
456 dataBit | AUBURN_EEPROM_CLK_RISE));
457 ql_write_nvram_reg(qdev, spir,
458 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
459 dataBit | AUBURN_EEPROM_CLK_FALL));
460 eepromAddr = eepromAddr << 1;
465 * Caller holds hw_lock.
467 static void fm93c56a_deselect(struct ql3_adapter *qdev)
469 struct ql3xxx_port_registers __iomem *port_regs =
470 qdev->mem_map_registers;
471 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
473 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
474 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
478 * Caller holds hw_lock.
480 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
485 struct ql3xxx_port_registers __iomem *port_regs =
486 qdev->mem_map_registers;
487 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
489 /* Read the data bits */
490 /* The first bit is a dummy. Clock right over it. */
491 for (i = 0; i < dataBits; i++) {
492 ql_write_nvram_reg(qdev, spir,
493 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
494 AUBURN_EEPROM_CLK_RISE);
495 ql_write_nvram_reg(qdev, spir,
496 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
497 AUBURN_EEPROM_CLK_FALL);
498 dataBit = (ql_read_common_reg(qdev, spir) &
499 AUBURN_EEPROM_DI_1) ? 1 : 0;
500 data = (data << 1) | dataBit;
506 * Caller holds hw_lock.
508 static void eeprom_readword(struct ql3_adapter *qdev,
509 u32 eepromAddr, unsigned short *value)
511 fm93c56a_select(qdev);
512 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
513 fm93c56a_datain(qdev, value);
514 fm93c56a_deselect(qdev);
517 static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
519 __le16 *p = (__le16 *)ndev->dev_addr;
520 p[0] = cpu_to_le16(addr[0]);
521 p[1] = cpu_to_le16(addr[1]);
522 p[2] = cpu_to_le16(addr[2]);
525 static int ql_get_nvram_params(struct ql3_adapter *qdev)
530 unsigned long hw_flags;
532 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
534 pEEPROMData = (u16 *)&qdev->nvram_data;
535 qdev->eeprom_cmd_data = 0;
536 if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
537 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
539 pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
540 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
544 for (index = 0; index < EEPROM_SIZE; index++) {
545 eeprom_readword(qdev, index, pEEPROMData);
546 checksum += *pEEPROMData;
549 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
552 netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
558 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
562 static const u32 PHYAddr[2] = {
563 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
566 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
568 struct ql3xxx_port_registers __iomem *port_regs =
569 qdev->mem_map_registers;
574 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
575 if (!(temp & MAC_MII_STATUS_BSY))
583 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
585 struct ql3xxx_port_registers __iomem *port_regs =
586 qdev->mem_map_registers;
589 if (qdev->numPorts > 1) {
590 /* Auto scan will cycle through multiple ports */
591 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
593 scanControl = MAC_MII_CONTROL_SC;
597 * Scan register 1 of PHY/PETBI,
598 * Set up to scan both devices
599 * The autoscan starts from the first register, completes
600 * the last one before rolling over to the first
602 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
603 PHYAddr[0] | MII_SCAN_REGISTER);
605 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
607 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
610 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
613 struct ql3xxx_port_registers __iomem *port_regs =
614 qdev->mem_map_registers;
616 /* See if scan mode is enabled before we turn it off */
617 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
618 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
619 /* Scan is enabled */
622 /* Scan is disabled */
627 * When disabling scan mode you must first change the MII register
630 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
631 PHYAddr[0] | MII_SCAN_REGISTER);
633 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
634 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
635 MAC_MII_CONTROL_RC) << 16));
640 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
641 u16 regAddr, u16 value, u32 phyAddr)
643 struct ql3xxx_port_registers __iomem *port_regs =
644 qdev->mem_map_registers;
647 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
649 if (ql_wait_for_mii_ready(qdev)) {
650 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
654 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
657 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
659 /* Wait for write to complete 9/10/04 SJP */
660 if (ql_wait_for_mii_ready(qdev)) {
661 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
666 ql_mii_enable_scan_mode(qdev);
671 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
672 u16 *value, u32 phyAddr)
674 struct ql3xxx_port_registers __iomem *port_regs =
675 qdev->mem_map_registers;
679 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
681 if (ql_wait_for_mii_ready(qdev)) {
682 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
686 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
689 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
690 (MAC_MII_CONTROL_RC << 16));
692 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
693 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
695 /* Wait for the read to complete */
696 if (ql_wait_for_mii_ready(qdev)) {
697 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
701 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
705 ql_mii_enable_scan_mode(qdev);
710 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
712 struct ql3xxx_port_registers __iomem *port_regs =
713 qdev->mem_map_registers;
715 ql_mii_disable_scan_mode(qdev);
717 if (ql_wait_for_mii_ready(qdev)) {
718 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
722 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
723 qdev->PHYAddr | regAddr);
725 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
727 /* Wait for write to complete. */
728 if (ql_wait_for_mii_ready(qdev)) {
729 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
733 ql_mii_enable_scan_mode(qdev);
738 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
741 struct ql3xxx_port_registers __iomem *port_regs =
742 qdev->mem_map_registers;
744 ql_mii_disable_scan_mode(qdev);
746 if (ql_wait_for_mii_ready(qdev)) {
747 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
752 qdev->PHYAddr | regAddr);
754 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
755 (MAC_MII_CONTROL_RC << 16));
757 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
758 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
760 /* Wait for the read to complete */
761 if (ql_wait_for_mii_ready(qdev)) {
762 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
766 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
769 ql_mii_enable_scan_mode(qdev);
774 static void ql_petbi_reset(struct ql3_adapter *qdev)
776 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
779 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
783 /* Enable Auto-negotiation sense */
784 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®);
785 reg |= PETBI_TBI_AUTO_SENSE;
786 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
788 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
789 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
791 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
792 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
793 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
797 static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
799 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
800 PHYAddr[qdev->mac_index]);
803 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
807 /* Enable Auto-negotiation sense */
808 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®,
809 PHYAddr[qdev->mac_index]);
810 reg |= PETBI_TBI_AUTO_SENSE;
811 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
812 PHYAddr[qdev->mac_index]);
814 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
815 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
816 PHYAddr[qdev->mac_index]);
818 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
819 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
820 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
821 PHYAddr[qdev->mac_index]);
824 static void ql_petbi_init(struct ql3_adapter *qdev)
826 ql_petbi_reset(qdev);
827 ql_petbi_start_neg(qdev);
830 static void ql_petbi_init_ex(struct ql3_adapter *qdev)
832 ql_petbi_reset_ex(qdev);
833 ql_petbi_start_neg_ex(qdev);
836 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
840 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0)
843 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
846 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
848 netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
849 /* power down device bit 11 = 1 */
850 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
851 /* enable diagnostic mode bit 2 = 1 */
852 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
853 /* 1000MB amplitude adjust (see Agere errata) */
854 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
855 /* 1000MB amplitude adjust (see Agere errata) */
856 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
857 /* 100MB amplitude adjust (see Agere errata) */
858 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
859 /* 100MB amplitude adjust (see Agere errata) */
860 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
861 /* 10MB amplitude adjust (see Agere errata) */
862 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
863 /* 10MB amplitude adjust (see Agere errata) */
864 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
865 /* point to hidden reg 0x2806 */
866 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
867 /* Write new PHYAD w/bit 5 set */
868 ql_mii_write_reg_ex(qdev, 0x11,
869 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
871 * Disable diagnostic mode bit 2 = 0
872 * Power up device bit 11 = 0
873 * Link up (on) and activity (blink)
875 ql_mii_write_reg(qdev, 0x12, 0x840a);
876 ql_mii_write_reg(qdev, 0x00, 0x1140);
877 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
880 static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
881 u16 phyIdReg0, u16 phyIdReg1)
883 enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
888 if (phyIdReg0 == 0xffff)
891 if (phyIdReg1 == 0xffff)
894 /* oui is split between two registers */
895 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
897 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
899 /* Scan table for this PHY */
900 for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
901 if ((oui == PHY_DEVICES[i].phyIdOUI) &&
902 (model == PHY_DEVICES[i].phyIdModel)) {
903 netdev_info(qdev->ndev, "Phy: %s\n",
904 PHY_DEVICES[i].name);
905 result = PHY_DEVICES[i].phyDevice;
913 static int ql_phy_get_speed(struct ql3_adapter *qdev)
917 switch (qdev->phyType) {
918 case PHY_AGERE_ET1011C: {
919 if (ql_mii_read_reg(qdev, 0x1A, ®) < 0)
922 reg = (reg >> 8) & 3;
926 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
929 reg = (((reg & 0x18) >> 3) & 3);
944 static int ql_is_full_dup(struct ql3_adapter *qdev)
948 switch (qdev->phyType) {
949 case PHY_AGERE_ET1011C: {
950 if (ql_mii_read_reg(qdev, 0x1A, ®))
953 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
955 case PHY_VITESSE_VSC8211:
957 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
959 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
964 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
968 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0)
971 return (reg & PHY_NEG_PAUSE) != 0;
974 static int PHY_Setup(struct ql3_adapter *qdev)
978 bool agereAddrChangeNeeded = false;
982 /* Determine the PHY we are using by reading the ID's */
983 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1);
985 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
989 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2);
991 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
995 /* Check if we have a Agere PHY */
996 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
998 /* Determine which MII address we should be using
999 determined by the index of the card */
1000 if (qdev->mac_index == 0)
1001 miiAddr = MII_AGERE_ADDR_1;
1003 miiAddr = MII_AGERE_ADDR_2;
1005 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr);
1007 netdev_err(qdev->ndev,
1008 "Could not read from reg PHY_ID_0_REG after Agere detected\n");
1012 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr);
1014 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
1018 /* We need to remember to initialize the Agere PHY */
1019 agereAddrChangeNeeded = true;
1022 /* Determine the particular PHY we have on board to apply
1023 PHY specific initializations */
1024 qdev->phyType = getPhyType(qdev, reg1, reg2);
1026 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1027 /* need this here so address gets changed */
1028 phyAgereSpecificInit(qdev, miiAddr);
1029 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1030 netdev_err(qdev->ndev, "PHY is unknown\n");
1038 * Caller holds hw_lock.
1040 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1042 struct ql3xxx_port_registers __iomem *port_regs =
1043 qdev->mem_map_registers;
1047 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1049 value = (MAC_CONFIG_REG_PE << 16);
1051 if (qdev->mac_index)
1052 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1054 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1058 * Caller holds hw_lock.
1060 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1062 struct ql3xxx_port_registers __iomem *port_regs =
1063 qdev->mem_map_registers;
1067 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1069 value = (MAC_CONFIG_REG_SR << 16);
1071 if (qdev->mac_index)
1072 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1074 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1078 * Caller holds hw_lock.
1080 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1082 struct ql3xxx_port_registers __iomem *port_regs =
1083 qdev->mem_map_registers;
1087 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1089 value = (MAC_CONFIG_REG_GM << 16);
1091 if (qdev->mac_index)
1092 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1094 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1098 * Caller holds hw_lock.
1100 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1102 struct ql3xxx_port_registers __iomem *port_regs =
1103 qdev->mem_map_registers;
1107 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1109 value = (MAC_CONFIG_REG_FD << 16);
1111 if (qdev->mac_index)
1112 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1114 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1118 * Caller holds hw_lock.
1120 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1122 struct ql3xxx_port_registers __iomem *port_regs =
1123 qdev->mem_map_registers;
1128 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1129 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1131 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1133 if (qdev->mac_index)
1134 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1136 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1140 * Caller holds hw_lock.
1142 static int ql_is_fiber(struct ql3_adapter *qdev)
1144 struct ql3xxx_port_registers __iomem *port_regs =
1145 qdev->mem_map_registers;
1149 switch (qdev->mac_index) {
1151 bitToCheck = PORT_STATUS_SM0;
1154 bitToCheck = PORT_STATUS_SM1;
1158 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1159 return (temp & bitToCheck) != 0;
1162 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1165 ql_mii_read_reg(qdev, 0x00, ®);
1166 return (reg & 0x1000) != 0;
1170 * Caller holds hw_lock.
1172 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1174 struct ql3xxx_port_registers __iomem *port_regs =
1175 qdev->mem_map_registers;
1179 switch (qdev->mac_index) {
1181 bitToCheck = PORT_STATUS_AC0;
1184 bitToCheck = PORT_STATUS_AC1;
1188 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1189 if (temp & bitToCheck) {
1190 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
1193 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1198 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1200 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1202 if (ql_is_fiber(qdev))
1203 return ql_is_petbi_neg_pause(qdev);
1205 return ql_is_phy_neg_pause(qdev);
1208 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1210 struct ql3xxx_port_registers __iomem *port_regs =
1211 qdev->mem_map_registers;
1215 switch (qdev->mac_index) {
1217 bitToCheck = PORT_STATUS_AE0;
1220 bitToCheck = PORT_STATUS_AE1;
1223 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1224 return (temp & bitToCheck) != 0;
1227 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1229 if (ql_is_fiber(qdev))
1232 return ql_phy_get_speed(qdev);
1235 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1237 if (ql_is_fiber(qdev))
1240 return ql_is_full_dup(qdev);
1244 * Caller holds hw_lock.
1246 static int ql_link_down_detect(struct ql3_adapter *qdev)
1248 struct ql3xxx_port_registers __iomem *port_regs =
1249 qdev->mem_map_registers;
1253 switch (qdev->mac_index) {
1255 bitToCheck = ISP_CONTROL_LINK_DN_0;
1258 bitToCheck = ISP_CONTROL_LINK_DN_1;
1263 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1264 return (temp & bitToCheck) != 0;
1268 * Caller holds hw_lock.
1270 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1272 struct ql3xxx_port_registers __iomem *port_regs =
1273 qdev->mem_map_registers;
1275 switch (qdev->mac_index) {
1277 ql_write_common_reg(qdev,
1278 &port_regs->CommonRegs.ispControlStatus,
1279 (ISP_CONTROL_LINK_DN_0) |
1280 (ISP_CONTROL_LINK_DN_0 << 16));
1284 ql_write_common_reg(qdev,
1285 &port_regs->CommonRegs.ispControlStatus,
1286 (ISP_CONTROL_LINK_DN_1) |
1287 (ISP_CONTROL_LINK_DN_1 << 16));
1298 * Caller holds hw_lock.
1300 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1302 struct ql3xxx_port_registers __iomem *port_regs =
1303 qdev->mem_map_registers;
1307 switch (qdev->mac_index) {
1309 bitToCheck = PORT_STATUS_F1_ENABLED;
1312 bitToCheck = PORT_STATUS_F3_ENABLED;
1318 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1319 if (temp & bitToCheck) {
1320 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1321 "not link master\n");
1325 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1329 static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1331 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1332 PHYAddr[qdev->mac_index]);
1335 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1338 u16 portConfiguration;
1340 if (qdev->phyType == PHY_AGERE_ET1011C)
1341 ql_mii_write_reg(qdev, 0x13, 0x0000);
1342 /* turn off external loopback */
1344 if (qdev->mac_index == 0)
1346 qdev->nvram_data.macCfg_port0.portConfiguration;
1349 qdev->nvram_data.macCfg_port1.portConfiguration;
1351 /* Some HBA's in the field are set to 0 and they need to
1352 be reinterpreted with a default value */
1353 if (portConfiguration == 0)
1354 portConfiguration = PORT_CONFIG_DEFAULT;
1356 /* Set the 1000 advertisements */
1357 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®,
1358 PHYAddr[qdev->mac_index]);
1359 reg &= ~PHY_GIG_ALL_PARAMS;
1361 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1362 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1363 reg |= PHY_GIG_ADV_1000F;
1365 reg |= PHY_GIG_ADV_1000H;
1368 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1369 PHYAddr[qdev->mac_index]);
1371 /* Set the 10/100 & pause negotiation advertisements */
1372 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®,
1373 PHYAddr[qdev->mac_index]);
1374 reg &= ~PHY_NEG_ALL_PARAMS;
1376 if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1377 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1379 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1380 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1381 reg |= PHY_NEG_ADV_100F;
1383 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1384 reg |= PHY_NEG_ADV_10F;
1387 if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1388 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1389 reg |= PHY_NEG_ADV_100H;
1391 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1392 reg |= PHY_NEG_ADV_10H;
1395 if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
1398 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1399 PHYAddr[qdev->mac_index]);
1401 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
1403 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1404 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1405 PHYAddr[qdev->mac_index]);
1408 static void ql_phy_init_ex(struct ql3_adapter *qdev)
1410 ql_phy_reset_ex(qdev);
1412 ql_phy_start_neg_ex(qdev);
1416 * Caller holds hw_lock.
1418 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1420 struct ql3xxx_port_registers __iomem *port_regs =
1421 qdev->mem_map_registers;
1423 u32 temp, linkState;
1425 switch (qdev->mac_index) {
1427 bitToCheck = PORT_STATUS_UP0;
1430 bitToCheck = PORT_STATUS_UP1;
1434 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1435 if (temp & bitToCheck)
1438 linkState = LS_DOWN;
1443 static int ql_port_start(struct ql3_adapter *qdev)
1445 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1446 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1448 netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
1452 if (ql_is_fiber(qdev)) {
1453 ql_petbi_init(qdev);
1456 ql_phy_init_ex(qdev);
1459 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1463 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1466 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1467 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1471 if (!ql_auto_neg_error(qdev)) {
1472 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1473 /* configure the MAC */
1474 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1475 "Configuring link\n");
1476 ql_mac_cfg_soft_reset(qdev, 1);
1477 ql_mac_cfg_gig(qdev,
1481 ql_mac_cfg_full_dup(qdev,
1484 ql_mac_cfg_pause(qdev,
1487 ql_mac_cfg_soft_reset(qdev, 0);
1489 /* enable the MAC */
1490 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1492 ql_mac_enable(qdev, 1);
1495 qdev->port_link_state = LS_UP;
1496 netif_start_queue(qdev->ndev);
1497 netif_carrier_on(qdev->ndev);
1498 netif_info(qdev, link, qdev->ndev,
1499 "Link is up at %d Mbps, %s duplex\n",
1500 ql_get_link_speed(qdev),
1501 ql_is_link_full_dup(qdev) ? "full" : "half");
1503 } else { /* Remote error detected */
1505 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1506 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1507 "Remote error detected. Calling ql_port_start()\n");
1509 * ql_port_start() is shared code and needs
1510 * to lock the PHY on it's own.
1512 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1513 if (ql_port_start(qdev)) /* Restart port */
1518 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1522 static void ql_link_state_machine_work(struct work_struct *work)
1524 struct ql3_adapter *qdev =
1525 container_of(work, struct ql3_adapter, link_state_work.work);
1527 u32 curr_link_state;
1528 unsigned long hw_flags;
1530 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1532 curr_link_state = ql_get_link_state(qdev);
1534 if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
1535 netif_info(qdev, link, qdev->ndev,
1536 "Reset in progress, skip processing link state\n");
1538 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1540 /* Restart timer on 2 second interval. */
1541 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1546 switch (qdev->port_link_state) {
1548 if (test_bit(QL_LINK_MASTER, &qdev->flags))
1549 ql_port_start(qdev);
1550 qdev->port_link_state = LS_DOWN;
1554 if (curr_link_state == LS_UP) {
1555 netif_info(qdev, link, qdev->ndev, "Link is up\n");
1556 if (ql_is_auto_neg_complete(qdev))
1557 ql_finish_auto_neg(qdev);
1559 if (qdev->port_link_state == LS_UP)
1560 ql_link_down_detect_clear(qdev);
1562 qdev->port_link_state = LS_UP;
1568 * See if the link is currently down or went down and came
1571 if (curr_link_state == LS_DOWN) {
1572 netif_info(qdev, link, qdev->ndev, "Link is down\n");
1573 qdev->port_link_state = LS_DOWN;
1575 if (ql_link_down_detect(qdev))
1576 qdev->port_link_state = LS_DOWN;
1579 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1581 /* Restart timer on 2 second interval. */
1582 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1586 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1588 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1590 if (ql_this_adapter_controls_port(qdev))
1591 set_bit(QL_LINK_MASTER, &qdev->flags);
1593 clear_bit(QL_LINK_MASTER, &qdev->flags);
1597 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1599 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1601 ql_mii_enable_scan_mode(qdev);
1603 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1604 if (ql_this_adapter_controls_port(qdev))
1605 ql_petbi_init_ex(qdev);
1607 if (ql_this_adapter_controls_port(qdev))
1608 ql_phy_init_ex(qdev);
1613 * MII_Setup needs to be called before taking the PHY out of reset
1614 * so that the management interface clock speed can be set properly.
1615 * It would be better if we had a way to disable MDC until after the
1616 * PHY is out of reset, but we don't have that capability.
1618 static int ql_mii_setup(struct ql3_adapter *qdev)
1621 struct ql3xxx_port_registers __iomem *port_regs =
1622 qdev->mem_map_registers;
1624 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1625 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1629 if (qdev->device_id == QL3032_DEVICE_ID)
1630 ql_write_page0_reg(qdev,
1631 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1633 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1634 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1636 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1637 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1639 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1643 #define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
1646 #define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
1647 SUPPORTED_10baseT_Full | \
1648 SUPPORTED_100baseT_Half | \
1649 SUPPORTED_100baseT_Full | \
1650 SUPPORTED_1000baseT_Half | \
1651 SUPPORTED_1000baseT_Full | \
1652 SUPPORTED_Autoneg | \
1655 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1657 if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1658 return SUPPORTED_OPTICAL_MODES;
1660 return SUPPORTED_TP_MODES;
1663 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1666 unsigned long hw_flags;
1667 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1668 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1669 (QL_RESOURCE_BITS_BASE_CODE |
1670 (qdev->mac_index) * 2) << 7)) {
1671 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1674 status = ql_is_auto_cfg(qdev);
1675 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1676 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1680 static u32 ql_get_speed(struct ql3_adapter *qdev)
1683 unsigned long hw_flags;
1684 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1685 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1686 (QL_RESOURCE_BITS_BASE_CODE |
1687 (qdev->mac_index) * 2) << 7)) {
1688 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1691 status = ql_get_link_speed(qdev);
1692 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1693 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1697 static int ql_get_full_dup(struct ql3_adapter *qdev)
1700 unsigned long hw_flags;
1701 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1702 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1703 (QL_RESOURCE_BITS_BASE_CODE |
1704 (qdev->mac_index) * 2) << 7)) {
1705 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1708 status = ql_is_link_full_dup(qdev);
1709 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1710 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1714 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1716 struct ql3_adapter *qdev = netdev_priv(ndev);
1718 ecmd->transceiver = XCVR_INTERNAL;
1719 ecmd->supported = ql_supported_modes(qdev);
1721 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1722 ecmd->port = PORT_FIBRE;
1724 ecmd->port = PORT_TP;
1725 ecmd->phy_address = qdev->PHYAddr;
1727 ecmd->advertising = ql_supported_modes(qdev);
1728 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1729 ethtool_cmd_speed_set(ecmd, ql_get_speed(qdev));
1730 ecmd->duplex = ql_get_full_dup(qdev);
1734 static void ql_get_drvinfo(struct net_device *ndev,
1735 struct ethtool_drvinfo *drvinfo)
1737 struct ql3_adapter *qdev = netdev_priv(ndev);
1738 strlcpy(drvinfo->driver, ql3xxx_driver_name, sizeof(drvinfo->driver));
1739 strlcpy(drvinfo->version, ql3xxx_driver_version,
1740 sizeof(drvinfo->version));
1741 strlcpy(drvinfo->bus_info, pci_name(qdev->pdev),
1742 sizeof(drvinfo->bus_info));
1743 drvinfo->regdump_len = 0;
1744 drvinfo->eedump_len = 0;
1747 static u32 ql_get_msglevel(struct net_device *ndev)
1749 struct ql3_adapter *qdev = netdev_priv(ndev);
1750 return qdev->msg_enable;
1753 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1755 struct ql3_adapter *qdev = netdev_priv(ndev);
1756 qdev->msg_enable = value;
1759 static void ql_get_pauseparam(struct net_device *ndev,
1760 struct ethtool_pauseparam *pause)
1762 struct ql3_adapter *qdev = netdev_priv(ndev);
1763 struct ql3xxx_port_registers __iomem *port_regs =
1764 qdev->mem_map_registers;
1767 if (qdev->mac_index == 0)
1768 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1770 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1772 pause->autoneg = ql_get_auto_cfg_status(qdev);
1773 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1774 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1777 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1778 .get_settings = ql_get_settings,
1779 .get_drvinfo = ql_get_drvinfo,
1780 .get_link = ethtool_op_get_link,
1781 .get_msglevel = ql_get_msglevel,
1782 .set_msglevel = ql_set_msglevel,
1783 .get_pauseparam = ql_get_pauseparam,
1786 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1788 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1792 while (lrg_buf_cb) {
1793 if (!lrg_buf_cb->skb) {
1795 netdev_alloc_skb(qdev->ndev,
1796 qdev->lrg_buffer_len);
1797 if (unlikely(!lrg_buf_cb->skb)) {
1798 netdev_printk(KERN_DEBUG, qdev->ndev,
1799 "Failed netdev_alloc_skb()\n");
1803 * We save some space to copy the ethhdr from
1806 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1807 map = pci_map_single(qdev->pdev,
1808 lrg_buf_cb->skb->data,
1809 qdev->lrg_buffer_len -
1811 PCI_DMA_FROMDEVICE);
1813 err = pci_dma_mapping_error(qdev->pdev, map);
1815 netdev_err(qdev->ndev,
1816 "PCI mapping failed with error: %d\n",
1818 dev_kfree_skb(lrg_buf_cb->skb);
1819 lrg_buf_cb->skb = NULL;
1824 lrg_buf_cb->buf_phy_addr_low =
1825 cpu_to_le32(LS_64BITS(map));
1826 lrg_buf_cb->buf_phy_addr_high =
1827 cpu_to_le32(MS_64BITS(map));
1828 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1829 dma_unmap_len_set(lrg_buf_cb, maplen,
1830 qdev->lrg_buffer_len -
1832 --qdev->lrg_buf_skb_check;
1833 if (!qdev->lrg_buf_skb_check)
1837 lrg_buf_cb = lrg_buf_cb->next;
1843 * Caller holds hw_lock.
1845 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1847 struct ql3xxx_port_registers __iomem *port_regs =
1848 qdev->mem_map_registers;
1850 if (qdev->small_buf_release_cnt >= 16) {
1851 while (qdev->small_buf_release_cnt >= 16) {
1852 qdev->small_buf_q_producer_index++;
1854 if (qdev->small_buf_q_producer_index ==
1856 qdev->small_buf_q_producer_index = 0;
1857 qdev->small_buf_release_cnt -= 8;
1860 writel(qdev->small_buf_q_producer_index,
1861 &port_regs->CommonRegs.rxSmallQProducerIndex);
1866 * Caller holds hw_lock.
1868 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1870 struct bufq_addr_element *lrg_buf_q_ele;
1872 struct ql_rcv_buf_cb *lrg_buf_cb;
1873 struct ql3xxx_port_registers __iomem *port_regs =
1874 qdev->mem_map_registers;
1876 if ((qdev->lrg_buf_free_count >= 8) &&
1877 (qdev->lrg_buf_release_cnt >= 16)) {
1879 if (qdev->lrg_buf_skb_check)
1880 if (!ql_populate_free_queue(qdev))
1883 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1885 while ((qdev->lrg_buf_release_cnt >= 16) &&
1886 (qdev->lrg_buf_free_count >= 8)) {
1888 for (i = 0; i < 8; i++) {
1890 ql_get_from_lrg_buf_free_list(qdev);
1891 lrg_buf_q_ele->addr_high =
1892 lrg_buf_cb->buf_phy_addr_high;
1893 lrg_buf_q_ele->addr_low =
1894 lrg_buf_cb->buf_phy_addr_low;
1897 qdev->lrg_buf_release_cnt--;
1900 qdev->lrg_buf_q_producer_index++;
1902 if (qdev->lrg_buf_q_producer_index ==
1903 qdev->num_lbufq_entries)
1904 qdev->lrg_buf_q_producer_index = 0;
1906 if (qdev->lrg_buf_q_producer_index ==
1907 (qdev->num_lbufq_entries - 1)) {
1908 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1912 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1913 writel(qdev->lrg_buf_q_producer_index,
1914 &port_regs->CommonRegs.rxLargeQProducerIndex);
1918 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1919 struct ob_mac_iocb_rsp *mac_rsp)
1921 struct ql_tx_buf_cb *tx_cb;
1924 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1925 netdev_warn(qdev->ndev,
1926 "Frame too short but it was padded and sent\n");
1929 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1931 /* Check the transmit response flags for any errors */
1932 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1933 netdev_err(qdev->ndev,
1934 "Frame too short to be legal, frame not sent\n");
1936 qdev->ndev->stats.tx_errors++;
1937 goto frame_not_sent;
1940 if (tx_cb->seg_count == 0) {
1941 netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
1942 mac_rsp->transaction_id);
1944 qdev->ndev->stats.tx_errors++;
1945 goto invalid_seg_count;
1948 pci_unmap_single(qdev->pdev,
1949 dma_unmap_addr(&tx_cb->map[0], mapaddr),
1950 dma_unmap_len(&tx_cb->map[0], maplen),
1953 if (tx_cb->seg_count) {
1954 for (i = 1; i < tx_cb->seg_count; i++) {
1955 pci_unmap_page(qdev->pdev,
1956 dma_unmap_addr(&tx_cb->map[i],
1958 dma_unmap_len(&tx_cb->map[i], maplen),
1962 qdev->ndev->stats.tx_packets++;
1963 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
1966 dev_kfree_skb_irq(tx_cb->skb);
1970 atomic_inc(&qdev->tx_count);
1973 static void ql_get_sbuf(struct ql3_adapter *qdev)
1975 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1976 qdev->small_buf_index = 0;
1977 qdev->small_buf_release_cnt++;
1980 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1982 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1983 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1984 qdev->lrg_buf_release_cnt++;
1985 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1986 qdev->lrg_buf_index = 0;
1991 * The difference between 3022 and 3032 for inbound completions:
1992 * 3022 uses two buffers per completion. The first buffer contains
1993 * (some) header info, the second the remainder of the headers plus
1994 * the data. For this chip we reserve some space at the top of the
1995 * receive buffer so that the header info in buffer one can be
1996 * prepended to the buffer two. Buffer two is the sent up while
1997 * buffer one is returned to the hardware to be reused.
1998 * 3032 receives all of it's data and headers in one buffer for a
1999 * simpler process. 3032 also supports checksum verification as
2000 * can be seen in ql_process_macip_rx_intr().
2002 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2003 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2005 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2006 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2007 struct sk_buff *skb;
2008 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2011 * Get the inbound address list (small buffer).
2015 if (qdev->device_id == QL3022_DEVICE_ID)
2016 lrg_buf_cb1 = ql_get_lbuf(qdev);
2018 /* start of second buffer */
2019 lrg_buf_cb2 = ql_get_lbuf(qdev);
2020 skb = lrg_buf_cb2->skb;
2022 qdev->ndev->stats.rx_packets++;
2023 qdev->ndev->stats.rx_bytes += length;
2025 skb_put(skb, length);
2026 pci_unmap_single(qdev->pdev,
2027 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2028 dma_unmap_len(lrg_buf_cb2, maplen),
2029 PCI_DMA_FROMDEVICE);
2030 prefetch(skb->data);
2031 skb_checksum_none_assert(skb);
2032 skb->protocol = eth_type_trans(skb, qdev->ndev);
2034 netif_receive_skb(skb);
2035 lrg_buf_cb2->skb = NULL;
2037 if (qdev->device_id == QL3022_DEVICE_ID)
2038 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2039 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2042 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2043 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2045 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2046 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2047 struct sk_buff *skb1 = NULL, *skb2;
2048 struct net_device *ndev = qdev->ndev;
2049 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2053 * Get the inbound address list (small buffer).
2058 if (qdev->device_id == QL3022_DEVICE_ID) {
2059 /* start of first buffer on 3022 */
2060 lrg_buf_cb1 = ql_get_lbuf(qdev);
2061 skb1 = lrg_buf_cb1->skb;
2063 if (*((u16 *) skb1->data) != 0xFFFF)
2064 size += VLAN_ETH_HLEN - ETH_HLEN;
2067 /* start of second buffer */
2068 lrg_buf_cb2 = ql_get_lbuf(qdev);
2069 skb2 = lrg_buf_cb2->skb;
2071 skb_put(skb2, length); /* Just the second buffer length here. */
2072 pci_unmap_single(qdev->pdev,
2073 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2074 dma_unmap_len(lrg_buf_cb2, maplen),
2075 PCI_DMA_FROMDEVICE);
2076 prefetch(skb2->data);
2078 skb_checksum_none_assert(skb2);
2079 if (qdev->device_id == QL3022_DEVICE_ID) {
2081 * Copy the ethhdr from first buffer to second. This
2082 * is necessary for 3022 IP completions.
2084 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2085 skb_push(skb2, size), size);
2087 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2089 (IB_IP_IOCB_RSP_3032_ICE |
2090 IB_IP_IOCB_RSP_3032_CE)) {
2092 "%s: Bad checksum for this %s packet, checksum = %x\n",
2094 ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2095 "TCP" : "UDP"), checksum);
2096 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2097 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2098 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2099 skb2->ip_summed = CHECKSUM_UNNECESSARY;
2102 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2104 netif_receive_skb(skb2);
2105 ndev->stats.rx_packets++;
2106 ndev->stats.rx_bytes += length;
2107 lrg_buf_cb2->skb = NULL;
2109 if (qdev->device_id == QL3022_DEVICE_ID)
2110 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2111 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2114 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2115 int *tx_cleaned, int *rx_cleaned, int work_to_do)
2117 struct net_rsp_iocb *net_rsp;
2118 struct net_device *ndev = qdev->ndev;
2121 /* While there are entries in the completion queue. */
2122 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2123 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
2125 net_rsp = qdev->rsp_current;
2128 * Fix 4032 chip's undocumented "feature" where bit-8 is set
2129 * if the inbound completion is for a VLAN.
2131 if (qdev->device_id == QL3032_DEVICE_ID)
2132 net_rsp->opcode &= 0x7f;
2133 switch (net_rsp->opcode) {
2135 case OPCODE_OB_MAC_IOCB_FN0:
2136 case OPCODE_OB_MAC_IOCB_FN2:
2137 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2142 case OPCODE_IB_MAC_IOCB:
2143 case OPCODE_IB_3032_MAC_IOCB:
2144 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2149 case OPCODE_IB_IP_IOCB:
2150 case OPCODE_IB_3032_IP_IOCB:
2151 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2156 u32 *tmp = (u32 *)net_rsp;
2158 "Hit default case, not handled!\n"
2159 " dropping the packet, opcode = %x\n"
2160 "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2162 (unsigned long int)tmp[0],
2163 (unsigned long int)tmp[1],
2164 (unsigned long int)tmp[2],
2165 (unsigned long int)tmp[3]);
2169 qdev->rsp_consumer_index++;
2171 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2172 qdev->rsp_consumer_index = 0;
2173 qdev->rsp_current = qdev->rsp_q_virt_addr;
2175 qdev->rsp_current++;
2178 work_done = *tx_cleaned + *rx_cleaned;
2184 static int ql_poll(struct napi_struct *napi, int budget)
2186 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2187 int rx_cleaned = 0, tx_cleaned = 0;
2188 unsigned long hw_flags;
2189 struct ql3xxx_port_registers __iomem *port_regs =
2190 qdev->mem_map_registers;
2192 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
2194 if (tx_cleaned + rx_cleaned != budget) {
2195 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2196 __napi_complete(napi);
2197 ql_update_small_bufq_prod_index(qdev);
2198 ql_update_lrg_bufq_prod_index(qdev);
2199 writel(qdev->rsp_consumer_index,
2200 &port_regs->CommonRegs.rspQConsumerIndex);
2201 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2203 ql_enable_interrupts(qdev);
2205 return tx_cleaned + rx_cleaned;
2208 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2211 struct net_device *ndev = dev_id;
2212 struct ql3_adapter *qdev = netdev_priv(ndev);
2213 struct ql3xxx_port_registers __iomem *port_regs =
2214 qdev->mem_map_registers;
2219 value = ql_read_common_reg_l(qdev,
2220 &port_regs->CommonRegs.ispControlStatus);
2222 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2223 spin_lock(&qdev->adapter_lock);
2224 netif_stop_queue(qdev->ndev);
2225 netif_carrier_off(qdev->ndev);
2226 ql_disable_interrupts(qdev);
2227 qdev->port_link_state = LS_DOWN;
2228 set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
2230 if (value & ISP_CONTROL_FE) {
2235 ql_read_page0_reg_l(qdev,
2236 &port_regs->PortFatalErrStatus);
2238 "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2240 set_bit(QL_RESET_START, &qdev->flags) ;
2243 * Soft Reset Requested.
2245 set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
2247 "Another function issued a reset to the chip. ISR value = %x\n",
2250 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2251 spin_unlock(&qdev->adapter_lock);
2252 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2253 ql_disable_interrupts(qdev);
2254 if (likely(napi_schedule_prep(&qdev->napi)))
2255 __napi_schedule(&qdev->napi);
2259 return IRQ_RETVAL(handled);
2263 * Get the total number of segments needed for the given number of fragments.
2264 * This is necessary because outbound address lists (OAL) will be used when
2265 * more than two frags are given. Each address list has 5 addr/len pairs.
2266 * The 5th pair in each OAL is used to point to the next OAL if more frags
2267 * are coming. That is why the frags:segment count ratio is not linear.
2269 static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
2271 if (qdev->device_id == QL3022_DEVICE_ID)
2276 else if (frags <= 6)
2278 else if (frags <= 10)
2280 else if (frags <= 14)
2282 else if (frags <= 18)
2287 static void ql_hw_csum_setup(const struct sk_buff *skb,
2288 struct ob_mac_iocb_req *mac_iocb_ptr)
2290 const struct iphdr *ip = ip_hdr(skb);
2292 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2293 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2295 if (ip->protocol == IPPROTO_TCP) {
2296 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2297 OB_3032MAC_IOCB_REQ_IC;
2299 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2300 OB_3032MAC_IOCB_REQ_IC;
2306 * Map the buffers for this transmit.
2307 * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2309 static int ql_send_map(struct ql3_adapter *qdev,
2310 struct ob_mac_iocb_req *mac_iocb_ptr,
2311 struct ql_tx_buf_cb *tx_cb,
2312 struct sk_buff *skb)
2315 struct oal_entry *oal_entry;
2316 int len = skb_headlen(skb);
2319 int completed_segs, i;
2320 int seg_cnt, seg = 0;
2321 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2323 seg_cnt = tx_cb->seg_count;
2325 * Map the skb buffer first.
2327 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2329 err = pci_dma_mapping_error(qdev->pdev, map);
2331 netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
2334 return NETDEV_TX_BUSY;
2337 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2338 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2339 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2340 oal_entry->len = cpu_to_le32(len);
2341 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2342 dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
2346 /* Terminate the last segment. */
2347 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2348 return NETDEV_TX_OK;
2351 for (completed_segs = 0;
2352 completed_segs < frag_cnt;
2353 completed_segs++, seg++) {
2354 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2357 * Check for continuation requirements.
2358 * It's strange but necessary.
2359 * Continuation entry points to outbound address list.
2361 if ((seg == 2 && seg_cnt > 3) ||
2362 (seg == 7 && seg_cnt > 8) ||
2363 (seg == 12 && seg_cnt > 13) ||
2364 (seg == 17 && seg_cnt > 18)) {
2365 map = pci_map_single(qdev->pdev, oal,
2369 err = pci_dma_mapping_error(qdev->pdev, map);
2371 netdev_err(qdev->ndev,
2372 "PCI mapping outbound address list with error: %d\n",
2377 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2378 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2379 oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2381 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2382 dma_unmap_len_set(&tx_cb->map[seg], maplen,
2383 sizeof(struct oal));
2384 oal_entry = (struct oal_entry *)oal;
2389 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
2392 err = dma_mapping_error(&qdev->pdev->dev, map);
2394 netdev_err(qdev->ndev,
2395 "PCI mapping frags failed with error: %d\n",
2400 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2401 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2402 oal_entry->len = cpu_to_le32(skb_frag_size(frag));
2403 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2404 dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
2406 /* Terminate the last segment. */
2407 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2408 return NETDEV_TX_OK;
2411 /* A PCI mapping failed and now we will need to back out
2412 * We need to traverse through the oal's and associated pages which
2413 * have been mapped and now we must unmap them to clean up properly
2417 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2419 for (i = 0; i < completed_segs; i++, seg++) {
2423 * Check for continuation requirements.
2424 * It's strange but necessary.
2427 if ((seg == 2 && seg_cnt > 3) ||
2428 (seg == 7 && seg_cnt > 8) ||
2429 (seg == 12 && seg_cnt > 13) ||
2430 (seg == 17 && seg_cnt > 18)) {
2431 pci_unmap_single(qdev->pdev,
2432 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2433 dma_unmap_len(&tx_cb->map[seg], maplen),
2439 pci_unmap_page(qdev->pdev,
2440 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2441 dma_unmap_len(&tx_cb->map[seg], maplen),
2445 pci_unmap_single(qdev->pdev,
2446 dma_unmap_addr(&tx_cb->map[0], mapaddr),
2447 dma_unmap_addr(&tx_cb->map[0], maplen),
2450 return NETDEV_TX_BUSY;
2455 * The difference between 3022 and 3032 sends:
2456 * 3022 only supports a simple single segment transmission.
2457 * 3032 supports checksumming and scatter/gather lists (fragments).
2458 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2459 * in the IOCB plus a chain of outbound address lists (OAL) that
2460 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2461 * will be used to point to an OAL when more ALP entries are required.
2462 * The IOCB is always the top of the chain followed by one or more
2463 * OALs (when necessary).
2465 static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2466 struct net_device *ndev)
2468 struct ql3_adapter *qdev = netdev_priv(ndev);
2469 struct ql3xxx_port_registers __iomem *port_regs =
2470 qdev->mem_map_registers;
2471 struct ql_tx_buf_cb *tx_cb;
2472 u32 tot_len = skb->len;
2473 struct ob_mac_iocb_req *mac_iocb_ptr;
2475 if (unlikely(atomic_read(&qdev->tx_count) < 2))
2476 return NETDEV_TX_BUSY;
2478 tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2479 tx_cb->seg_count = ql_get_seg_count(qdev,
2480 skb_shinfo(skb)->nr_frags);
2481 if (tx_cb->seg_count == -1) {
2482 netdev_err(ndev, "%s: invalid segment count!\n", __func__);
2483 return NETDEV_TX_OK;
2486 mac_iocb_ptr = tx_cb->queue_entry;
2487 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2488 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2489 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2490 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2491 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2492 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2494 if (qdev->device_id == QL3032_DEVICE_ID &&
2495 skb->ip_summed == CHECKSUM_PARTIAL)
2496 ql_hw_csum_setup(skb, mac_iocb_ptr);
2498 if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
2499 netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
2500 return NETDEV_TX_BUSY;
2504 qdev->req_producer_index++;
2505 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2506 qdev->req_producer_index = 0;
2508 ql_write_common_reg_l(qdev,
2509 &port_regs->CommonRegs.reqQProducerIndex,
2510 qdev->req_producer_index);
2512 netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2513 "tx queued, slot %d, len %d\n",
2514 qdev->req_producer_index, skb->len);
2516 atomic_dec(&qdev->tx_count);
2517 return NETDEV_TX_OK;
2520 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2523 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2525 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2527 /* The barrier is required to ensure request and response queue
2528 * addr writes to the registers.
2532 qdev->req_q_virt_addr =
2533 pci_alloc_consistent(qdev->pdev,
2534 (size_t) qdev->req_q_size,
2535 &qdev->req_q_phy_addr);
2537 if ((qdev->req_q_virt_addr == NULL) ||
2538 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2539 netdev_err(qdev->ndev, "reqQ failed\n");
2543 qdev->rsp_q_virt_addr =
2544 pci_alloc_consistent(qdev->pdev,
2545 (size_t) qdev->rsp_q_size,
2546 &qdev->rsp_q_phy_addr);
2548 if ((qdev->rsp_q_virt_addr == NULL) ||
2549 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2550 netdev_err(qdev->ndev, "rspQ allocation failed\n");
2551 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2552 qdev->req_q_virt_addr,
2553 qdev->req_q_phy_addr);
2557 set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2562 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2564 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
2565 netdev_info(qdev->ndev, "Already done\n");
2569 pci_free_consistent(qdev->pdev,
2571 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2573 qdev->req_q_virt_addr = NULL;
2575 pci_free_consistent(qdev->pdev,
2577 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2579 qdev->rsp_q_virt_addr = NULL;
2581 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2584 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2586 /* Create Large Buffer Queue */
2587 qdev->lrg_buf_q_size =
2588 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2589 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2590 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2592 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2595 kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),
2597 if (qdev->lrg_buf == NULL) {
2598 netdev_err(qdev->ndev, "qdev->lrg_buf alloc failed\n");
2602 qdev->lrg_buf_q_alloc_virt_addr =
2603 pci_alloc_consistent(qdev->pdev,
2604 qdev->lrg_buf_q_alloc_size,
2605 &qdev->lrg_buf_q_alloc_phy_addr);
2607 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2608 netdev_err(qdev->ndev, "lBufQ failed\n");
2611 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2612 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2614 /* Create Small Buffer Queue */
2615 qdev->small_buf_q_size =
2616 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2617 if (qdev->small_buf_q_size < PAGE_SIZE)
2618 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2620 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2622 qdev->small_buf_q_alloc_virt_addr =
2623 pci_alloc_consistent(qdev->pdev,
2624 qdev->small_buf_q_alloc_size,
2625 &qdev->small_buf_q_alloc_phy_addr);
2627 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2628 netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
2629 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2630 qdev->lrg_buf_q_alloc_virt_addr,
2631 qdev->lrg_buf_q_alloc_phy_addr);
2635 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2636 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2637 set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2641 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2643 if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
2644 netdev_info(qdev->ndev, "Already done\n");
2647 kfree(qdev->lrg_buf);
2648 pci_free_consistent(qdev->pdev,
2649 qdev->lrg_buf_q_alloc_size,
2650 qdev->lrg_buf_q_alloc_virt_addr,
2651 qdev->lrg_buf_q_alloc_phy_addr);
2653 qdev->lrg_buf_q_virt_addr = NULL;
2655 pci_free_consistent(qdev->pdev,
2656 qdev->small_buf_q_alloc_size,
2657 qdev->small_buf_q_alloc_virt_addr,
2658 qdev->small_buf_q_alloc_phy_addr);
2660 qdev->small_buf_q_virt_addr = NULL;
2662 clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2665 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2668 struct bufq_addr_element *small_buf_q_entry;
2670 /* Currently we allocate on one of memory and use it for smallbuffers */
2671 qdev->small_buf_total_size =
2672 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2673 QL_SMALL_BUFFER_SIZE);
2675 qdev->small_buf_virt_addr =
2676 pci_alloc_consistent(qdev->pdev,
2677 qdev->small_buf_total_size,
2678 &qdev->small_buf_phy_addr);
2680 if (qdev->small_buf_virt_addr == NULL) {
2681 netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
2685 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2686 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2688 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2690 /* Initialize the small buffer queue. */
2691 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2692 small_buf_q_entry->addr_high =
2693 cpu_to_le32(qdev->small_buf_phy_addr_high);
2694 small_buf_q_entry->addr_low =
2695 cpu_to_le32(qdev->small_buf_phy_addr_low +
2696 (i * QL_SMALL_BUFFER_SIZE));
2697 small_buf_q_entry++;
2699 qdev->small_buf_index = 0;
2700 set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
2704 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2706 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
2707 netdev_info(qdev->ndev, "Already done\n");
2710 if (qdev->small_buf_virt_addr != NULL) {
2711 pci_free_consistent(qdev->pdev,
2712 qdev->small_buf_total_size,
2713 qdev->small_buf_virt_addr,
2714 qdev->small_buf_phy_addr);
2716 qdev->small_buf_virt_addr = NULL;
2720 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2723 struct ql_rcv_buf_cb *lrg_buf_cb;
2725 for (i = 0; i < qdev->num_large_buffers; i++) {
2726 lrg_buf_cb = &qdev->lrg_buf[i];
2727 if (lrg_buf_cb->skb) {
2728 dev_kfree_skb(lrg_buf_cb->skb);
2729 pci_unmap_single(qdev->pdev,
2730 dma_unmap_addr(lrg_buf_cb, mapaddr),
2731 dma_unmap_len(lrg_buf_cb, maplen),
2732 PCI_DMA_FROMDEVICE);
2733 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2740 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2743 struct ql_rcv_buf_cb *lrg_buf_cb;
2744 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2746 for (i = 0; i < qdev->num_large_buffers; i++) {
2747 lrg_buf_cb = &qdev->lrg_buf[i];
2748 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2749 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2752 qdev->lrg_buf_index = 0;
2753 qdev->lrg_buf_skb_check = 0;
2756 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2759 struct ql_rcv_buf_cb *lrg_buf_cb;
2760 struct sk_buff *skb;
2764 for (i = 0; i < qdev->num_large_buffers; i++) {
2765 skb = netdev_alloc_skb(qdev->ndev,
2766 qdev->lrg_buffer_len);
2767 if (unlikely(!skb)) {
2768 /* Better luck next round */
2769 netdev_err(qdev->ndev,
2770 "large buff alloc failed for %d bytes at index %d\n",
2771 qdev->lrg_buffer_len * 2, i);
2772 ql_free_large_buffers(qdev);
2776 lrg_buf_cb = &qdev->lrg_buf[i];
2777 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2778 lrg_buf_cb->index = i;
2779 lrg_buf_cb->skb = skb;
2781 * We save some space to copy the ethhdr from first
2784 skb_reserve(skb, QL_HEADER_SPACE);
2785 map = pci_map_single(qdev->pdev,
2787 qdev->lrg_buffer_len -
2789 PCI_DMA_FROMDEVICE);
2791 err = pci_dma_mapping_error(qdev->pdev, map);
2793 netdev_err(qdev->ndev,
2794 "PCI mapping failed with error: %d\n",
2796 ql_free_large_buffers(qdev);
2800 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2801 dma_unmap_len_set(lrg_buf_cb, maplen,
2802 qdev->lrg_buffer_len -
2804 lrg_buf_cb->buf_phy_addr_low =
2805 cpu_to_le32(LS_64BITS(map));
2806 lrg_buf_cb->buf_phy_addr_high =
2807 cpu_to_le32(MS_64BITS(map));
2813 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2815 struct ql_tx_buf_cb *tx_cb;
2818 tx_cb = &qdev->tx_buf[0];
2819 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2826 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2828 struct ql_tx_buf_cb *tx_cb;
2830 struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
2832 /* Create free list of transmit buffers */
2833 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2835 tx_cb = &qdev->tx_buf[i];
2837 tx_cb->queue_entry = req_q_curr;
2839 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2840 if (tx_cb->oal == NULL)
2846 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2848 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2849 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2850 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2851 } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2853 * Bigger buffers, so less of them.
2855 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2856 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2858 netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n",
2859 qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
2862 qdev->num_large_buffers =
2863 qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2864 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2865 qdev->max_frame_size =
2866 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2869 * First allocate a page of shared memory and use it for shadow
2870 * locations of Network Request Queue Consumer Address Register and
2871 * Network Completion Queue Producer Index Register
2873 qdev->shadow_reg_virt_addr =
2874 pci_alloc_consistent(qdev->pdev,
2875 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2877 if (qdev->shadow_reg_virt_addr != NULL) {
2878 qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
2879 qdev->req_consumer_index_phy_addr_high =
2880 MS_64BITS(qdev->shadow_reg_phy_addr);
2881 qdev->req_consumer_index_phy_addr_low =
2882 LS_64BITS(qdev->shadow_reg_phy_addr);
2884 qdev->prsp_producer_index =
2885 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2886 qdev->rsp_producer_index_phy_addr_high =
2887 qdev->req_consumer_index_phy_addr_high;
2888 qdev->rsp_producer_index_phy_addr_low =
2889 qdev->req_consumer_index_phy_addr_low + 8;
2891 netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
2895 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2896 netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
2900 if (ql_alloc_buffer_queues(qdev) != 0) {
2901 netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
2902 goto err_buffer_queues;
2905 if (ql_alloc_small_buffers(qdev) != 0) {
2906 netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
2907 goto err_small_buffers;
2910 if (ql_alloc_large_buffers(qdev) != 0) {
2911 netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
2912 goto err_small_buffers;
2915 /* Initialize the large buffer queue. */
2916 ql_init_large_buffers(qdev);
2917 if (ql_create_send_free_list(qdev))
2920 qdev->rsp_current = qdev->rsp_q_virt_addr;
2924 ql_free_send_free_list(qdev);
2926 ql_free_buffer_queues(qdev);
2928 ql_free_net_req_rsp_queues(qdev);
2930 pci_free_consistent(qdev->pdev,
2932 qdev->shadow_reg_virt_addr,
2933 qdev->shadow_reg_phy_addr);
2938 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2940 ql_free_send_free_list(qdev);
2941 ql_free_large_buffers(qdev);
2942 ql_free_small_buffers(qdev);
2943 ql_free_buffer_queues(qdev);
2944 ql_free_net_req_rsp_queues(qdev);
2945 if (qdev->shadow_reg_virt_addr != NULL) {
2946 pci_free_consistent(qdev->pdev,
2948 qdev->shadow_reg_virt_addr,
2949 qdev->shadow_reg_phy_addr);
2950 qdev->shadow_reg_virt_addr = NULL;
2954 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2956 struct ql3xxx_local_ram_registers __iomem *local_ram =
2957 (void __iomem *)qdev->mem_map_registers;
2959 if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2960 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2964 ql_write_page2_reg(qdev,
2965 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2967 ql_write_page2_reg(qdev,
2968 &local_ram->maxBufletCount,
2969 qdev->nvram_data.bufletCount);
2971 ql_write_page2_reg(qdev,
2972 &local_ram->freeBufletThresholdLow,
2973 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2974 (qdev->nvram_data.tcpWindowThreshold0));
2976 ql_write_page2_reg(qdev,
2977 &local_ram->freeBufletThresholdHigh,
2978 qdev->nvram_data.tcpWindowThreshold50);
2980 ql_write_page2_reg(qdev,
2981 &local_ram->ipHashTableBase,
2982 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2983 qdev->nvram_data.ipHashTableBaseLo);
2984 ql_write_page2_reg(qdev,
2985 &local_ram->ipHashTableCount,
2986 qdev->nvram_data.ipHashTableSize);
2987 ql_write_page2_reg(qdev,
2988 &local_ram->tcpHashTableBase,
2989 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2990 qdev->nvram_data.tcpHashTableBaseLo);
2991 ql_write_page2_reg(qdev,
2992 &local_ram->tcpHashTableCount,
2993 qdev->nvram_data.tcpHashTableSize);
2994 ql_write_page2_reg(qdev,
2995 &local_ram->ncbBase,
2996 (qdev->nvram_data.ncbTableBaseHi << 16) |
2997 qdev->nvram_data.ncbTableBaseLo);
2998 ql_write_page2_reg(qdev,
2999 &local_ram->maxNcbCount,
3000 qdev->nvram_data.ncbTableSize);
3001 ql_write_page2_reg(qdev,
3002 &local_ram->drbBase,
3003 (qdev->nvram_data.drbTableBaseHi << 16) |
3004 qdev->nvram_data.drbTableBaseLo);
3005 ql_write_page2_reg(qdev,
3006 &local_ram->maxDrbCount,
3007 qdev->nvram_data.drbTableSize);
3008 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3012 static int ql_adapter_initialize(struct ql3_adapter *qdev)
3015 struct ql3xxx_port_registers __iomem *port_regs =
3016 qdev->mem_map_registers;
3017 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3018 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3019 (void __iomem *)port_regs;
3023 if (ql_mii_setup(qdev))
3026 /* Bring out PHY out of reset */
3027 ql_write_common_reg(qdev, spir,
3028 (ISP_SERIAL_PORT_IF_WE |
3029 (ISP_SERIAL_PORT_IF_WE << 16)));
3030 /* Give the PHY time to come out of reset. */
3032 qdev->port_link_state = LS_DOWN;
3033 netif_carrier_off(qdev->ndev);
3035 /* V2 chip fix for ARS-39168. */
3036 ql_write_common_reg(qdev, spir,
3037 (ISP_SERIAL_PORT_IF_SDE |
3038 (ISP_SERIAL_PORT_IF_SDE << 16)));
3040 /* Request Queue Registers */
3041 *((u32 *)(qdev->preq_consumer_index)) = 0;
3042 atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
3043 qdev->req_producer_index = 0;
3045 ql_write_page1_reg(qdev,
3046 &hmem_regs->reqConsumerIndexAddrHigh,
3047 qdev->req_consumer_index_phy_addr_high);
3048 ql_write_page1_reg(qdev,
3049 &hmem_regs->reqConsumerIndexAddrLow,
3050 qdev->req_consumer_index_phy_addr_low);
3052 ql_write_page1_reg(qdev,
3053 &hmem_regs->reqBaseAddrHigh,
3054 MS_64BITS(qdev->req_q_phy_addr));
3055 ql_write_page1_reg(qdev,
3056 &hmem_regs->reqBaseAddrLow,
3057 LS_64BITS(qdev->req_q_phy_addr));
3058 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3060 /* Response Queue Registers */
3061 *((__le16 *) (qdev->prsp_producer_index)) = 0;
3062 qdev->rsp_consumer_index = 0;
3063 qdev->rsp_current = qdev->rsp_q_virt_addr;
3065 ql_write_page1_reg(qdev,
3066 &hmem_regs->rspProducerIndexAddrHigh,
3067 qdev->rsp_producer_index_phy_addr_high);
3069 ql_write_page1_reg(qdev,
3070 &hmem_regs->rspProducerIndexAddrLow,
3071 qdev->rsp_producer_index_phy_addr_low);
3073 ql_write_page1_reg(qdev,
3074 &hmem_regs->rspBaseAddrHigh,
3075 MS_64BITS(qdev->rsp_q_phy_addr));
3077 ql_write_page1_reg(qdev,
3078 &hmem_regs->rspBaseAddrLow,
3079 LS_64BITS(qdev->rsp_q_phy_addr));
3081 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3083 /* Large Buffer Queue */
3084 ql_write_page1_reg(qdev,
3085 &hmem_regs->rxLargeQBaseAddrHigh,
3086 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3088 ql_write_page1_reg(qdev,
3089 &hmem_regs->rxLargeQBaseAddrLow,
3090 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3092 ql_write_page1_reg(qdev,
3093 &hmem_regs->rxLargeQLength,
3094 qdev->num_lbufq_entries);
3096 ql_write_page1_reg(qdev,
3097 &hmem_regs->rxLargeBufferLength,
3098 qdev->lrg_buffer_len);
3100 /* Small Buffer Queue */
3101 ql_write_page1_reg(qdev,
3102 &hmem_regs->rxSmallQBaseAddrHigh,
3103 MS_64BITS(qdev->small_buf_q_phy_addr));
3105 ql_write_page1_reg(qdev,
3106 &hmem_regs->rxSmallQBaseAddrLow,
3107 LS_64BITS(qdev->small_buf_q_phy_addr));
3109 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3110 ql_write_page1_reg(qdev,
3111 &hmem_regs->rxSmallBufferLength,
3112 QL_SMALL_BUFFER_SIZE);
3114 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3115 qdev->small_buf_release_cnt = 8;
3116 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3117 qdev->lrg_buf_release_cnt = 8;
3118 qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
3119 qdev->small_buf_index = 0;
3120 qdev->lrg_buf_index = 0;
3121 qdev->lrg_buf_free_count = 0;
3122 qdev->lrg_buf_free_head = NULL;
3123 qdev->lrg_buf_free_tail = NULL;
3125 ql_write_common_reg(qdev,
3126 &port_regs->CommonRegs.
3127 rxSmallQProducerIndex,
3128 qdev->small_buf_q_producer_index);
3129 ql_write_common_reg(qdev,
3130 &port_regs->CommonRegs.
3131 rxLargeQProducerIndex,
3132 qdev->lrg_buf_q_producer_index);
3135 * Find out if the chip has already been initialized. If it has, then
3136 * we skip some of the initialization.
3138 clear_bit(QL_LINK_MASTER, &qdev->flags);
3139 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3140 if ((value & PORT_STATUS_IC) == 0) {
3142 /* Chip has not been configured yet, so let it rip. */
3143 if (ql_init_misc_registers(qdev)) {
3148 value = qdev->nvram_data.tcpMaxWindowSize;
3149 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3151 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3153 if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3154 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3159 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3160 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3161 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3162 16) | (INTERNAL_CHIP_SD |
3163 INTERNAL_CHIP_WE)));
3164 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3167 if (qdev->mac_index)
3168 ql_write_page0_reg(qdev,
3169 &port_regs->mac1MaxFrameLengthReg,
3170 qdev->max_frame_size);
3172 ql_write_page0_reg(qdev,
3173 &port_regs->mac0MaxFrameLengthReg,
3174 qdev->max_frame_size);
3176 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3177 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3184 ql_init_scan_mode(qdev);
3185 ql_get_phy_owner(qdev);
3187 /* Load the MAC Configuration */
3189 /* Program lower 32 bits of the MAC address */
3190 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3191 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3192 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3193 ((qdev->ndev->dev_addr[2] << 24)
3194 | (qdev->ndev->dev_addr[3] << 16)
3195 | (qdev->ndev->dev_addr[4] << 8)
3196 | qdev->ndev->dev_addr[5]));
3198 /* Program top 16 bits of the MAC address */
3199 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3200 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3201 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3202 ((qdev->ndev->dev_addr[0] << 8)
3203 | qdev->ndev->dev_addr[1]));
3205 /* Enable Primary MAC */
3206 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3207 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3208 MAC_ADDR_INDIRECT_PTR_REG_PE));
3210 /* Clear Primary and Secondary IP addresses */
3211 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3212 ((IP_ADDR_INDEX_REG_MASK << 16) |
3213 (qdev->mac_index << 2)));
3214 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3216 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3217 ((IP_ADDR_INDEX_REG_MASK << 16) |
3218 ((qdev->mac_index << 2) + 1)));
3219 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3221 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3223 /* Indicate Configuration Complete */
3224 ql_write_page0_reg(qdev,
3225 &port_regs->portControl,
3226 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3229 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3230 if (value & PORT_STATUS_IC)
3232 spin_unlock_irq(&qdev->hw_lock);
3234 spin_lock_irq(&qdev->hw_lock);
3238 netdev_err(qdev->ndev, "Hw Initialization timeout\n");
3243 /* Enable Ethernet Function */
3244 if (qdev->device_id == QL3032_DEVICE_ID) {
3246 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3247 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3248 QL3032_PORT_CONTROL_ET);
3249 ql_write_page0_reg(qdev, &port_regs->functionControl,
3250 ((value << 16) | value));
3253 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3255 ql_write_page0_reg(qdev, &port_regs->portControl,
3256 ((value << 16) | value));
3265 * Caller holds hw_lock.
3267 static int ql_adapter_reset(struct ql3_adapter *qdev)
3269 struct ql3xxx_port_registers __iomem *port_regs =
3270 qdev->mem_map_registers;
3275 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3276 clear_bit(QL_RESET_DONE, &qdev->flags);
3279 * Issue soft reset to chip.
3281 netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
3282 ql_write_common_reg(qdev,
3283 &port_regs->CommonRegs.ispControlStatus,
3284 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3286 /* Wait 3 seconds for reset to complete. */
3287 netdev_printk(KERN_DEBUG, qdev->ndev,
3288 "Wait 10 milliseconds for reset to complete\n");
3290 /* Wait until the firmware tells us the Soft Reset is done */
3294 ql_read_common_reg(qdev,
3295 &port_regs->CommonRegs.ispControlStatus);
3296 if ((value & ISP_CONTROL_SR) == 0)
3300 } while ((--max_wait_time));
3303 * Also, make sure that the Network Reset Interrupt bit has been
3304 * cleared after the soft reset has taken place.
3307 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3308 if (value & ISP_CONTROL_RI) {
3309 netdev_printk(KERN_DEBUG, qdev->ndev,
3310 "clearing RI after reset\n");
3311 ql_write_common_reg(qdev,
3312 &port_regs->CommonRegs.
3314 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3317 if (max_wait_time == 0) {
3318 /* Issue Force Soft Reset */
3319 ql_write_common_reg(qdev,
3320 &port_regs->CommonRegs.
3322 ((ISP_CONTROL_FSR << 16) |
3325 * Wait until the firmware tells us the Force Soft Reset is
3330 value = ql_read_common_reg(qdev,
3331 &port_regs->CommonRegs.
3333 if ((value & ISP_CONTROL_FSR) == 0)
3336 } while ((--max_wait_time));
3338 if (max_wait_time == 0)
3341 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3342 set_bit(QL_RESET_DONE, &qdev->flags);
3346 static void ql_set_mac_info(struct ql3_adapter *qdev)
3348 struct ql3xxx_port_registers __iomem *port_regs =
3349 qdev->mem_map_registers;
3350 u32 value, port_status;
3353 /* Get the function number */
3355 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3356 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3357 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3358 switch (value & ISP_CONTROL_FN_MASK) {
3359 case ISP_CONTROL_FN0_NET:
3360 qdev->mac_index = 0;
3361 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3362 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3363 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3364 if (port_status & PORT_STATUS_SM0)
3365 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3367 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3370 case ISP_CONTROL_FN1_NET:
3371 qdev->mac_index = 1;
3372 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3373 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3374 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3375 if (port_status & PORT_STATUS_SM1)
3376 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3378 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3381 case ISP_CONTROL_FN0_SCSI:
3382 case ISP_CONTROL_FN1_SCSI:
3384 netdev_printk(KERN_DEBUG, qdev->ndev,
3385 "Invalid function number, ispControlStatus = 0x%x\n",
3389 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3392 static void ql_display_dev_info(struct net_device *ndev)
3394 struct ql3_adapter *qdev = netdev_priv(ndev);
3395 struct pci_dev *pdev = qdev->pdev;
3398 "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3399 DRV_NAME, qdev->index, qdev->chip_rev_id,
3400 qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
3402 netdev_info(ndev, "%s Interface\n",
3403 test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
3406 * Print PCI bus width/type.
3408 netdev_info(ndev, "Bus interface is %s %s\n",
3409 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3410 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3412 netdev_info(ndev, "mem IO base address adjusted = 0x%p\n",
3413 qdev->mem_map_registers);
3414 netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
3416 netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
3419 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3421 struct net_device *ndev = qdev->ndev;
3424 netif_stop_queue(ndev);
3425 netif_carrier_off(ndev);
3427 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3428 clear_bit(QL_LINK_MASTER, &qdev->flags);
3430 ql_disable_interrupts(qdev);
3432 free_irq(qdev->pdev->irq, ndev);
3434 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3435 netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
3436 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3437 pci_disable_msi(qdev->pdev);
3440 del_timer_sync(&qdev->adapter_timer);
3442 napi_disable(&qdev->napi);
3446 unsigned long hw_flags;
3448 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3449 if (ql_wait_for_drvr_lock(qdev)) {
3450 soft_reset = ql_adapter_reset(qdev);
3452 netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
3456 "Releasing driver lock via chip reset\n");
3459 "Could not acquire driver lock to do reset!\n");
3462 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3464 ql_free_mem_resources(qdev);
3468 static int ql_adapter_up(struct ql3_adapter *qdev)
3470 struct net_device *ndev = qdev->ndev;
3472 unsigned long irq_flags = IRQF_SHARED;
3473 unsigned long hw_flags;
3475 if (ql_alloc_mem_resources(qdev)) {
3476 netdev_err(ndev, "Unable to allocate buffers\n");
3481 if (pci_enable_msi(qdev->pdev)) {
3483 "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
3486 netdev_info(ndev, "MSI Enabled...\n");
3487 set_bit(QL_MSI_ENABLED, &qdev->flags);
3488 irq_flags &= ~IRQF_SHARED;
3492 err = request_irq(qdev->pdev->irq, ql3xxx_isr,
3493 irq_flags, ndev->name, ndev);
3496 "Failed to reserve interrupt %d - already in use\n",
3501 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3503 err = ql_wait_for_drvr_lock(qdev);
3505 err = ql_adapter_initialize(qdev);
3507 netdev_err(ndev, "Unable to initialize adapter\n");
3510 netdev_err(ndev, "Releasing driver lock\n");
3511 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3513 netdev_err(ndev, "Could not acquire driver lock\n");
3517 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3519 set_bit(QL_ADAPTER_UP, &qdev->flags);
3521 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3523 napi_enable(&qdev->napi);
3524 ql_enable_interrupts(qdev);
3528 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3530 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3531 free_irq(qdev->pdev->irq, ndev);
3533 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3534 netdev_info(ndev, "calling pci_disable_msi()\n");
3535 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3536 pci_disable_msi(qdev->pdev);
3541 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3543 if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
3544 netdev_err(qdev->ndev,
3545 "Driver up/down cycle failed, closing device\n");
3547 dev_close(qdev->ndev);
3554 static int ql3xxx_close(struct net_device *ndev)
3556 struct ql3_adapter *qdev = netdev_priv(ndev);
3559 * Wait for device to recover from a reset.
3560 * (Rarely happens, but possible.)
3562 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3565 ql_adapter_down(qdev, QL_DO_RESET);
3569 static int ql3xxx_open(struct net_device *ndev)
3571 struct ql3_adapter *qdev = netdev_priv(ndev);
3572 return ql_adapter_up(qdev);
3575 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3577 struct ql3_adapter *qdev = netdev_priv(ndev);
3578 struct ql3xxx_port_registers __iomem *port_regs =
3579 qdev->mem_map_registers;
3580 struct sockaddr *addr = p;
3581 unsigned long hw_flags;
3583 if (netif_running(ndev))
3586 if (!is_valid_ether_addr(addr->sa_data))
3587 return -EADDRNOTAVAIL;
3589 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3591 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3592 /* Program lower 32 bits of the MAC address */
3593 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3594 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3595 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3596 ((ndev->dev_addr[2] << 24) | (ndev->
3597 dev_addr[3] << 16) |
3598 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3600 /* Program top 16 bits of the MAC address */
3601 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3602 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3603 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3604 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3605 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3610 static void ql3xxx_tx_timeout(struct net_device *ndev)
3612 struct ql3_adapter *qdev = netdev_priv(ndev);
3614 netdev_err(ndev, "Resetting...\n");
3616 * Stop the queues, we've got a problem.
3618 netif_stop_queue(ndev);
3621 * Wake up the worker to process this event.
3623 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3626 static void ql_reset_work(struct work_struct *work)
3628 struct ql3_adapter *qdev =
3629 container_of(work, struct ql3_adapter, reset_work.work);
3630 struct net_device *ndev = qdev->ndev;
3632 struct ql_tx_buf_cb *tx_cb;
3633 int max_wait_time, i;
3634 struct ql3xxx_port_registers __iomem *port_regs =
3635 qdev->mem_map_registers;
3636 unsigned long hw_flags;
3638 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START), &qdev->flags)) {
3639 clear_bit(QL_LINK_MASTER, &qdev->flags);
3642 * Loop through the active list and return the skb.
3644 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3646 tx_cb = &qdev->tx_buf[i];
3648 netdev_printk(KERN_DEBUG, ndev,
3649 "Freeing lost SKB\n");
3650 pci_unmap_single(qdev->pdev,
3651 dma_unmap_addr(&tx_cb->map[0],
3653 dma_unmap_len(&tx_cb->map[0], maplen),
3655 for (j = 1; j < tx_cb->seg_count; j++) {
3656 pci_unmap_page(qdev->pdev,
3657 dma_unmap_addr(&tx_cb->map[j],
3659 dma_unmap_len(&tx_cb->map[j],
3663 dev_kfree_skb(tx_cb->skb);
3668 netdev_err(ndev, "Clearing NRI after reset\n");
3669 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3670 ql_write_common_reg(qdev,
3671 &port_regs->CommonRegs.
3673 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3675 * Wait the for Soft Reset to Complete.
3679 value = ql_read_common_reg(qdev,
3680 &port_regs->CommonRegs.
3683 if ((value & ISP_CONTROL_SR) == 0) {
3684 netdev_printk(KERN_DEBUG, ndev,
3685 "reset completed\n");
3689 if (value & ISP_CONTROL_RI) {
3690 netdev_printk(KERN_DEBUG, ndev,
3691 "clearing NRI after reset\n");
3692 ql_write_common_reg(qdev,
3697 16) | ISP_CONTROL_RI));
3700 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3702 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3703 } while (--max_wait_time);
3704 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3706 if (value & ISP_CONTROL_SR) {
3709 * Set the reset flags and clear the board again.
3710 * Nothing else to do...
3713 "Timed out waiting for reset to complete\n");
3714 netdev_err(ndev, "Do a reset\n");
3715 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3716 clear_bit(QL_RESET_START, &qdev->flags);
3717 ql_cycle_adapter(qdev, QL_DO_RESET);
3721 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3722 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3723 clear_bit(QL_RESET_START, &qdev->flags);
3724 ql_cycle_adapter(qdev, QL_NO_RESET);
3728 static void ql_tx_timeout_work(struct work_struct *work)
3730 struct ql3_adapter *qdev =
3731 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3733 ql_cycle_adapter(qdev, QL_DO_RESET);
3736 static void ql_get_board_info(struct ql3_adapter *qdev)
3738 struct ql3xxx_port_registers __iomem *port_regs =
3739 qdev->mem_map_registers;
3742 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3744 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3745 if (value & PORT_STATUS_64)
3746 qdev->pci_width = 64;
3748 qdev->pci_width = 32;
3749 if (value & PORT_STATUS_X)
3753 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3756 static void ql3xxx_timer(unsigned long ptr)
3758 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3759 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3762 static const struct net_device_ops ql3xxx_netdev_ops = {
3763 .ndo_open = ql3xxx_open,
3764 .ndo_start_xmit = ql3xxx_send,
3765 .ndo_stop = ql3xxx_close,
3766 .ndo_change_mtu = eth_change_mtu,
3767 .ndo_validate_addr = eth_validate_addr,
3768 .ndo_set_mac_address = ql3xxx_set_mac_address,
3769 .ndo_tx_timeout = ql3xxx_tx_timeout,
3772 static int ql3xxx_probe(struct pci_dev *pdev,
3773 const struct pci_device_id *pci_entry)
3775 struct net_device *ndev = NULL;
3776 struct ql3_adapter *qdev = NULL;
3777 static int cards_found;
3778 int uninitialized_var(pci_using_dac), err;
3780 err = pci_enable_device(pdev);
3782 pr_err("%s cannot enable PCI device\n", pci_name(pdev));
3786 err = pci_request_regions(pdev, DRV_NAME);
3788 pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
3789 goto err_out_disable_pdev;
3792 pci_set_master(pdev);
3794 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3796 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3797 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3799 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3803 pr_err("%s no usable DMA configuration\n", pci_name(pdev));
3804 goto err_out_free_regions;
3807 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3810 goto err_out_free_regions;
3813 SET_NETDEV_DEV(ndev, &pdev->dev);
3815 pci_set_drvdata(pdev, ndev);
3817 qdev = netdev_priv(ndev);
3818 qdev->index = cards_found;
3821 qdev->device_id = pci_entry->device;
3822 qdev->port_link_state = LS_DOWN;
3826 qdev->msg_enable = netif_msg_init(debug, default_msg);
3829 ndev->features |= NETIF_F_HIGHDMA;
3830 if (qdev->device_id == QL3032_DEVICE_ID)
3831 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3833 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
3834 if (!qdev->mem_map_registers) {
3835 pr_err("%s: cannot map device registers\n", pci_name(pdev));
3837 goto err_out_free_ndev;
3840 spin_lock_init(&qdev->adapter_lock);
3841 spin_lock_init(&qdev->hw_lock);
3843 /* Set driver entry points */
3844 ndev->netdev_ops = &ql3xxx_netdev_ops;
3845 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3846 ndev->watchdog_timeo = 5 * HZ;
3848 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
3850 ndev->irq = pdev->irq;
3852 /* make sure the EEPROM is good */
3853 if (ql_get_nvram_params(qdev)) {
3854 pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3855 __func__, qdev->index);
3857 goto err_out_iounmap;
3860 ql_set_mac_info(qdev);
3862 /* Validate and set parameters */
3863 if (qdev->mac_index) {
3864 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3865 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
3867 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3868 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
3870 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3872 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3874 /* Record PCI bus information. */
3875 ql_get_board_info(qdev);
3878 * Set the Maximum Memory Read Byte Count value. We do this to handle
3882 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3884 err = register_netdev(ndev);
3886 pr_err("%s: cannot register net device\n", pci_name(pdev));
3887 goto err_out_iounmap;
3890 /* we're going to reset, so assume we have no link for now */
3892 netif_carrier_off(ndev);
3893 netif_stop_queue(ndev);
3895 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3896 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3897 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3898 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
3900 init_timer(&qdev->adapter_timer);
3901 qdev->adapter_timer.function = ql3xxx_timer;
3902 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3903 qdev->adapter_timer.data = (unsigned long)qdev;
3906 pr_alert("%s\n", DRV_STRING);
3907 pr_alert("Driver name: %s, Version: %s\n",
3908 DRV_NAME, DRV_VERSION);
3910 ql_display_dev_info(ndev);
3916 iounmap(qdev->mem_map_registers);
3919 err_out_free_regions:
3920 pci_release_regions(pdev);
3921 err_out_disable_pdev:
3922 pci_disable_device(pdev);
3923 pci_set_drvdata(pdev, NULL);
3928 static void ql3xxx_remove(struct pci_dev *pdev)
3930 struct net_device *ndev = pci_get_drvdata(pdev);
3931 struct ql3_adapter *qdev = netdev_priv(ndev);
3933 unregister_netdev(ndev);
3935 ql_disable_interrupts(qdev);
3937 if (qdev->workqueue) {
3938 cancel_delayed_work(&qdev->reset_work);
3939 cancel_delayed_work(&qdev->tx_timeout_work);
3940 destroy_workqueue(qdev->workqueue);
3941 qdev->workqueue = NULL;
3944 iounmap(qdev->mem_map_registers);
3945 pci_release_regions(pdev);
3946 pci_set_drvdata(pdev, NULL);
3950 static struct pci_driver ql3xxx_driver = {
3953 .id_table = ql3xxx_pci_tbl,
3954 .probe = ql3xxx_probe,
3955 .remove = ql3xxx_remove,
3958 module_pci_driver(ql3xxx_driver);