drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/aer.h>
  15
  16 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
  17 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
  18 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
  19                                       struct qlcnic_cmd_args *);
  20 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
  21 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
  22 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
  23                                                       pci_channel_state_t);
  24 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
  25 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
  26 static void qlcnic_83xx_io_resume(struct pci_dev *);
  27 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
  28 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
  29 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
  30 static int qlcnic_83xx_shutdown(struct pci_dev *);
  31 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
  32
  33 #define RSS_HASHTYPE_IP_TCP             0x3
  34 #define QLC_83XX_FW_MBX_CMD             0
  35 #define QLC_SKIP_INACTIVE_PCI_REGS      7
  36
  37 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  38         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  39         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  40         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  41         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  42         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  43         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  44         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  45         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  46         {QLCNIC_CMD_SET_MTU, 3, 1},
  47         {QLCNIC_CMD_READ_PHY, 4, 2},
  48         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  49         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  50         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  51         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  52         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  53         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  54         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  55         {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
  56         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  57         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  58         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  59         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  60         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  61         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  62         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  63         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  64         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  65         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  66         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  67         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  68         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
  69         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
  70         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
  71         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
  72         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
  73         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
  74         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
  75         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
  76         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
  77         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
  78         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
  79         {QLCNIC_CMD_IDC_ACK, 5, 1},
  80         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
  81         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
  82         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
  83         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
  84         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
  85         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
  86         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
  87         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
  88         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  89         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
  90 };
  91
  92 const u32 qlcnic_83xx_ext_reg_tbl[] = {
  93         0x38CC,         /* Global Reset */
  94         0x38F0,         /* Wildcard */
  95         0x38FC,         /* Informant */
  96         0x3038,         /* Host MBX ctrl */
  97         0x303C,         /* FW MBX ctrl */
  98         0x355C,         /* BOOT LOADER ADDRESS REG */
  99         0x3560,         /* BOOT LOADER SIZE REG */
 100         0x3564,         /* FW IMAGE ADDR REG */
 101         0x1000,         /* MBX intr enable */
 102         0x1200,         /* Default Intr mask */
 103         0x1204,         /* Default Interrupt ID */
 104         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
 105         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
 106         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
 107         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
 108         0x3790,         /* QLC_83XX_IDC_CTRL */
 109         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
 110         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
 111         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
 112         0x37A0,         /* QLC_83XX_IDC_PF_0 */
 113         0x37A4,         /* QLC_83XX_IDC_PF_1 */
 114         0x37A8,         /* QLC_83XX_IDC_PF_2 */
 115         0x37AC,         /* QLC_83XX_IDC_PF_3 */
 116         0x37B0,         /* QLC_83XX_IDC_PF_4 */
 117         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 118         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 119         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 120         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 121         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 122         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 123         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 124         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 125         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 126         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 127         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 128         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 129         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 130         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 131         0x37F4,         /* QLC_83XX_VNIC_STATE */
 132         0x3868,         /* QLC_83XX_DRV_LOCK */
 133         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 134         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 135         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 136 };
 137
 138 const u32 qlcnic_83xx_reg_tbl[] = {
 139         0x34A8,         /* PEG_HALT_STAT1 */
 140         0x34AC,         /* PEG_HALT_STAT2 */
 141         0x34B0,         /* FW_HEARTBEAT */
 142         0x3500,         /* FLASH LOCK_ID */
 143         0x3528,         /* FW_CAPABILITIES */
 144         0x3538,         /* Driver active, DRV_REG0 */
 145         0x3540,         /* Device state, DRV_REG1 */
 146         0x3544,         /* Driver state, DRV_REG2 */
 147         0x3548,         /* Driver scratch, DRV_REG3 */
 148         0x354C,         /* Device partiton info, DRV_REG4 */
 149         0x3524,         /* Driver IDC ver, DRV_REG5 */
 150         0x3550,         /* FW_VER_MAJOR */
 151         0x3554,         /* FW_VER_MINOR */
 152         0x3558,         /* FW_VER_SUB */
 153         0x359C,         /* NPAR STATE */
 154         0x35FC,         /* FW_IMG_VALID */
 155         0x3650,         /* CMD_PEG_STATE */
 156         0x373C,         /* RCV_PEG_STATE */
 157         0x37B4,         /* ASIC TEMP */
 158         0x356C,         /* FW API */
 159         0x3570,         /* DRV OP MODE */
 160         0x3850,         /* FLASH LOCK */
 161         0x3854,         /* FLASH UNLOCK */
 162 };
 163
 164 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 165         .read_crb                       = qlcnic_83xx_read_crb,
 166         .write_crb                      = qlcnic_83xx_write_crb,
 167         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 168         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 169         .get_mac_address                = qlcnic_83xx_get_mac_address,
 170         .setup_intr                     = qlcnic_83xx_setup_intr,
 171         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 172         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 173         .get_func_no                    = qlcnic_83xx_get_func_no,
 174         .api_lock                       = qlcnic_83xx_cam_lock,
 175         .api_unlock                     = qlcnic_83xx_cam_unlock,
 176         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 177         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 178         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 179         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 180         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 181         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 182         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 183         .setup_link_event               = qlcnic_83xx_setup_link_event,
 184         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 185         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 186         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 187         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 188         .napi_enable                    = qlcnic_83xx_napi_enable,
 189         .napi_disable                   = qlcnic_83xx_napi_disable,
 190         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 191         .config_rss                     = qlcnic_83xx_config_rss,
 192         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 193         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 194         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 195         .get_board_info                 = qlcnic_83xx_get_port_info,
 196         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 197         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 198         .io_error_detected              = qlcnic_83xx_io_error_detected,
 199         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 200         .io_resume                      = qlcnic_83xx_io_resume,
 201         .get_beacon_state               = qlcnic_83xx_get_beacon_state,
 202 };
 203
 204 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 205         .config_bridged_mode    = qlcnic_config_bridged_mode,
 206         .config_led             = qlcnic_config_led,
 207         .request_reset          = qlcnic_83xx_idc_request_reset,
 208         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 209         .napi_add               = qlcnic_83xx_napi_add,
 210         .napi_del               = qlcnic_83xx_napi_del,
 211         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 212         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 213         .shutdown               = qlcnic_83xx_shutdown,
 214         .resume                 = qlcnic_83xx_resume,
 215 };
 216
 217 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 218 {
 219         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 220         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 221         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 222 }
 223
 224 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 225 {
 226         u32 fw_major, fw_minor, fw_build;
 227         struct pci_dev *pdev = adapter->pdev;
 228
 229         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 230         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 231         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 232         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 233
 234         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 235                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 236
 237         return adapter->fw_version;
 238 }
 239
 240 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 241 {
 242         void __iomem *base;
 243         u32 val;
 244
 245         base = adapter->ahw->pci_base0 +
 246                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 247         writel(addr, base);
 248         val = readl(base);
 249         if (val != addr)
 250                 return -EIO;
 251
 252         return 0;
 253 }
 254
 255 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 256                                 int *err)
 257 {
 258         struct qlcnic_hardware_context *ahw = adapter->ahw;
 259
 260         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 261         if (!*err) {
 262                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 263         } else {
 264                 dev_err(&adapter->pdev->dev,
 265                         "%s failed, addr = 0x%lx\n", __func__, addr);
 266                 return -EIO;
 267         }
 268 }
 269
 270 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 271                                  u32 data)
 272 {
 273         int err;
 274         struct qlcnic_hardware_context *ahw = adapter->ahw;
 275
 276         err = __qlcnic_set_win_base(adapter, (u32) addr);
 277         if (!err) {
 278                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 279                 return 0;
 280         } else {
 281                 dev_err(&adapter->pdev->dev,
 282                         "%s failed, addr = 0x%x data = 0x%x\n",
 283                         __func__, (int)addr, data);
 284                 return err;
 285         }
 286 }
 287
 288 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 289 {
 290         int err, i, num_msix;
 291         struct qlcnic_hardware_context *ahw = adapter->ahw;
 292
 293         num_msix = adapter->drv_sds_rings;
 294
 295         /* account for AEN interrupt MSI-X based interrupts */
 296         num_msix += 1;
 297
 298         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 299                 num_msix += adapter->drv_tx_rings;
 300
 301         err = qlcnic_enable_msix(adapter, num_msix);
 302         if (err == -ENOMEM)
 303                 return err;
 304         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 305                 num_msix = adapter->ahw->num_msix;
 306         else {
 307                 if (qlcnic_sriov_vf_check(adapter))
 308                         return -EINVAL;
 309                 num_msix = 1;
 310                 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
 311         }
 312         /* setup interrupt mapping table for fw */
 313         ahw->intr_tbl = vzalloc(num_msix *
 314                                 sizeof(struct qlcnic_intrpt_config));
 315         if (!ahw->intr_tbl)
 316                 return -ENOMEM;
 317         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 318                 /* MSI-X enablement failed, use legacy interrupt */
 319                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 320                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 321                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 322                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 323                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 324         }
 325
 326         for (i = 0; i < num_msix; i++) {
 327                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 328                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 329                 else
 330                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 331                 ahw->intr_tbl[i].id = i;
 332                 ahw->intr_tbl[i].src = 0;
 333         }
 334         return 0;
 335 }
 336
 337 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 338 {
 339         writel(0, adapter->tgt_mask_reg);
 340 }
 341
 342 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 343 {
 344         if (adapter->tgt_mask_reg)
 345                 writel(1, adapter->tgt_mask_reg);
 346 }
 347
 348 /* Enable MSI-x and INT-x interrupts */
 349 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 350                              struct qlcnic_host_sds_ring *sds_ring)
 351 {
 352         writel(0, sds_ring->crb_intr_mask);
 353 }
 354
 355 /* Disable MSI-x and INT-x interrupts */
 356 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 357                               struct qlcnic_host_sds_ring *sds_ring)
 358 {
 359         writel(1, sds_ring->crb_intr_mask);
 360 }
 361
 362 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 363                                                     *adapter)
 364 {
 365         u32 mask;
 366
 367         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 368          * source register. We could be here before contexts are created
 369          * and sds_ring->crb_intr_mask has not been initialized, calculate
 370          * BAR offset for Interrupt Source Register
 371          */
 372         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 373         writel(0, adapter->ahw->pci_base0 + mask);
 374 }
 375
 376 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 377 {
 378         u32 mask;
 379
 380         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 381         writel(1, adapter->ahw->pci_base0 + mask);
 382         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 383 }
 384
 385 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 386                                      struct qlcnic_cmd_args *cmd)
 387 {
 388         int i;
 389
 390         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 391                 return;
 392
 393         for (i = 0; i < cmd->rsp.num; i++)
 394                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 395 }
 396
 397 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 398 {
 399         u32 intr_val;
 400         struct qlcnic_hardware_context *ahw = adapter->ahw;
 401         int retries = 0;
 402
 403         intr_val = readl(adapter->tgt_status_reg);
 404
 405         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 406                 return IRQ_NONE;
 407
 408         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 409                 adapter->stats.spurious_intr++;
 410                 return IRQ_NONE;
 411         }
 412         /* The barrier is required to ensure writes to the registers */
 413         wmb();
 414
 415         /* clear the interrupt trigger control register */
 416         writel(0, adapter->isr_int_vec);
 417         intr_val = readl(adapter->isr_int_vec);
 418         do {
 419                 intr_val = readl(adapter->tgt_status_reg);
 420                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 421                         break;
 422                 retries++;
 423         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 424                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 425
 426         return IRQ_HANDLED;
 427 }
 428
 429 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 430 {
 431         atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
 432         complete(&mbx->completion);
 433 }
 434
 435 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 436 {
 437         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 438         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 439         unsigned long flags;
 440
 441         spin_lock_irqsave(&mbx->aen_lock, flags);
 442         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 443         if (!(resp & QLCNIC_SET_OWNER))
 444                 goto out;
 445
 446         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 447         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 448                 __qlcnic_83xx_process_aen(adapter);
 449         } else {
 450                 if (atomic_read(&mbx->rsp_status) != rsp_status)
 451                         qlcnic_83xx_notify_mbx_response(mbx);
 452         }
 453 out:
 454         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 455         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 456 }
 457
 458 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 459 {
 460         struct qlcnic_adapter *adapter = data;
 461         struct qlcnic_host_sds_ring *sds_ring;
 462         struct qlcnic_hardware_context *ahw = adapter->ahw;
 463
 464         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 465                 return IRQ_NONE;
 466
 467         qlcnic_83xx_poll_process_aen(adapter);
 468
 469         if (ahw->diag_test) {
 470                 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
 471                         ahw->diag_cnt++;
 472                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 473                 return IRQ_HANDLED;
 474         }
 475
 476         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 477                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 478         } else {
 479                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 480                 napi_schedule(&sds_ring->napi);
 481         }
 482
 483         return IRQ_HANDLED;
 484 }
 485
 486 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 487 {
 488         struct qlcnic_host_sds_ring *sds_ring = data;
 489         struct qlcnic_adapter *adapter = sds_ring->adapter;
 490
 491         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 492                 goto done;
 493
 494         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 495                 return IRQ_NONE;
 496
 497 done:
 498         adapter->ahw->diag_cnt++;
 499         qlcnic_83xx_enable_intr(adapter, sds_ring);
 500
 501         return IRQ_HANDLED;
 502 }
 503
 504 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 505 {
 506         u32 num_msix;
 507
 508         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 509                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 510
 511         qlcnic_83xx_disable_mbx_intr(adapter);
 512
 513         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 514                 num_msix = adapter->ahw->num_msix - 1;
 515         else
 516                 num_msix = 0;
 517
 518         msleep(20);
 519
 520         if (adapter->msix_entries) {
 521                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 522                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 523         }
 524 }
 525
 526 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 527 {
 528         irq_handler_t handler;
 529         u32 val;
 530         int err = 0;
 531         unsigned long flags = 0;
 532
 533         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 534             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 535                 flags |= IRQF_SHARED;
 536
 537         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 538                 handler = qlcnic_83xx_handle_aen;
 539                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 540                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 541                 if (err) {
 542                         dev_err(&adapter->pdev->dev,
 543                                 "failed to register MBX interrupt\n");
 544                         return err;
 545                 }
 546         } else {
 547                 handler = qlcnic_83xx_intr;
 548                 val = adapter->msix_entries[0].vector;
 549                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 550                 if (err) {
 551                         dev_err(&adapter->pdev->dev,
 552                                 "failed to register INTx interrupt\n");
 553                         return err;
 554                 }
 555                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 556         }
 557
 558         /* Enable mailbox interrupt */
 559         qlcnic_83xx_enable_mbx_interrupt(adapter);
 560
 561         return err;
 562 }
 563
 564 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 565 {
 566         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 567         adapter->ahw->pci_func = (val >> 24) & 0xff;
 568 }
 569
 570 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 571 {
 572         void __iomem *addr;
 573         u32 val, limit = 0;
 574
 575         struct qlcnic_hardware_context *ahw = adapter->ahw;
 576
 577         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 578         do {
 579                 val = readl(addr);
 580                 if (val) {
 581                         /* write the function number to register */
 582                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 583                                             ahw->pci_func);
 584                         return 0;
 585                 }
 586                 usleep_range(1000, 2000);
 587         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 588
 589         return -EIO;
 590 }
 591
 592 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 593 {
 594         void __iomem *addr;
 595         u32 val;
 596         struct qlcnic_hardware_context *ahw = adapter->ahw;
 597
 598         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 599         val = readl(addr);
 600 }
 601
 602 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 603                           loff_t offset, size_t size)
 604 {
 605         int ret = 0;
 606         u32 data;
 607
 608         if (qlcnic_api_lock(adapter)) {
 609                 dev_err(&adapter->pdev->dev,
 610                         "%s: failed to acquire lock. addr offset 0x%x\n",
 611                         __func__, (u32)offset);
 612                 return;
 613         }
 614
 615         data = QLCRD32(adapter, (u32) offset, &ret);
 616         qlcnic_api_unlock(adapter);
 617
 618         if (ret == -EIO) {
 619                 dev_err(&adapter->pdev->dev,
 620                         "%s: failed. addr offset 0x%x\n",
 621                         __func__, (u32)offset);
 622                 return;
 623         }
 624         memcpy(buf, &data, size);
 625 }
 626
 627 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 628                            loff_t offset, size_t size)
 629 {
 630         u32 data;
 631
 632         memcpy(&data, buf, size);
 633         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 634 }
 635
 636 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 637 {
 638         int status;
 639
 640         status = qlcnic_83xx_get_port_config(adapter);
 641         if (status) {
 642                 dev_err(&adapter->pdev->dev,
 643                         "Get Port Info failed\n");
 644         } else {
 645                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 646                         adapter->ahw->port_type = QLCNIC_XGBE;
 647                 else
 648                         adapter->ahw->port_type = QLCNIC_GBE;
 649
 650                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 651                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 652         }
 653         return status;
 654 }
 655
 656 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 657 {
 658         struct qlcnic_hardware_context *ahw = adapter->ahw;
 659         u16 act_pci_fn = ahw->total_nic_func;
 660         u16 count;
 661
 662         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 663         if (act_pci_fn <= 2)
 664                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 665                          act_pci_fn;
 666         else
 667                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 668                          act_pci_fn;
 669         ahw->max_uc_count = count;
 670 }
 671
 672 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 673 {
 674         u32 val;
 675
 676         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 677                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 678         else
 679                 val = BIT_2;
 680
 681         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 682         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 683 }
 684
 685 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 686                           const struct pci_device_id *ent)
 687 {
 688         u32 op_mode, priv_level;
 689         struct qlcnic_hardware_context *ahw = adapter->ahw;
 690
 691         ahw->fw_hal_version = 2;
 692         qlcnic_get_func_no(adapter);
 693
 694         if (qlcnic_sriov_vf_check(adapter)) {
 695                 qlcnic_sriov_vf_set_ops(adapter);
 696                 return;
 697         }
 698
 699         /* Determine function privilege level */
 700         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 701         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 702                 priv_level = QLCNIC_MGMT_FUNC;
 703         else
 704                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 705                                                          ahw->pci_func);
 706
 707         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 708                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 709                 dev_info(&adapter->pdev->dev,
 710                          "HAL Version: %d Non Privileged function\n",
 711                          ahw->fw_hal_version);
 712                 adapter->nic_ops = &qlcnic_vf_ops;
 713         } else {
 714                 if (pci_find_ext_capability(adapter->pdev,
 715                                             PCI_EXT_CAP_ID_SRIOV))
 716                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 717                 adapter->nic_ops = &qlcnic_83xx_ops;
 718         }
 719 }
 720
 721 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 722                                         u32 data[]);
 723 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 724                                             u32 data[]);
 725
 726 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 727                      struct qlcnic_cmd_args *cmd)
 728 {
 729         int i;
 730
 731         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 732                 return;
 733
 734         dev_info(&adapter->pdev->dev,
 735                  "Host MBX regs(%d)\n", cmd->req.num);
 736         for (i = 0; i < cmd->req.num; i++) {
 737                 if (i && !(i % 8))
 738                         pr_info("\n");
 739                 pr_info("%08x ", cmd->req.arg[i]);
 740         }
 741         pr_info("\n");
 742         dev_info(&adapter->pdev->dev,
 743                  "FW MBX regs(%d)\n", cmd->rsp.num);
 744         for (i = 0; i < cmd->rsp.num; i++) {
 745                 if (i && !(i % 8))
 746                         pr_info("\n");
 747                 pr_info("%08x ", cmd->rsp.arg[i]);
 748         }
 749         pr_info("\n");
 750 }
 751
 752 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 753                                                 struct qlcnic_cmd_args *cmd)
 754 {
 755         struct qlcnic_hardware_context *ahw = adapter->ahw;
 756         int opcode = LSW(cmd->req.arg[0]);
 757         unsigned long max_loops;
 758
 759         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 760
 761         for (; max_loops; max_loops--) {
 762                 if (atomic_read(&cmd->rsp_status) ==
 763                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 764                         return;
 765
 766                 udelay(1);
 767         }
 768
 769         dev_err(&adapter->pdev->dev,
 770                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 771                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 772         flush_workqueue(ahw->mailbox->work_q);
 773         return;
 774 }
 775
 776 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 777                           struct qlcnic_cmd_args *cmd)
 778 {
 779         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 780         struct qlcnic_hardware_context *ahw = adapter->ahw;
 781         int cmd_type, err, opcode;
 782         unsigned long timeout;
 783
 784         if (!mbx)
 785                 return -EIO;
 786
 787         opcode = LSW(cmd->req.arg[0]);
 788         cmd_type = cmd->type;
 789         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 790         if (err) {
 791                 dev_err(&adapter->pdev->dev,
 792                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 793                         __func__, opcode, cmd->type, ahw->pci_func,
 794                         ahw->op_mode);
 795                 return err;
 796         }
 797
 798         switch (cmd_type) {
 799         case QLC_83XX_MBX_CMD_WAIT:
 800                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 801                         dev_err(&adapter->pdev->dev,
 802                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 803                                 __func__, opcode, cmd_type, ahw->pci_func,
 804                                 ahw->op_mode);
 805                         flush_workqueue(mbx->work_q);
 806                 }
 807                 break;
 808         case QLC_83XX_MBX_CMD_NO_WAIT:
 809                 return 0;
 810         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 811                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 812                 break;
 813         default:
 814                 dev_err(&adapter->pdev->dev,
 815                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 816                         __func__, opcode, cmd_type, ahw->pci_func,
 817                         ahw->op_mode);
 818                 qlcnic_83xx_detach_mailbox_work(adapter);
 819         }
 820
 821         return cmd->rsp_opcode;
 822 }
 823
 824 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 825                                struct qlcnic_adapter *adapter, u32 type)
 826 {
 827         int i, size;
 828         u32 temp;
 829         const struct qlcnic_mailbox_metadata *mbx_tbl;
 830
 831         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 832         mbx_tbl = qlcnic_83xx_mbx_tbl;
 833         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 834         for (i = 0; i < size; i++) {
 835                 if (type == mbx_tbl[i].cmd) {
 836                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 837                         mbx->req.num = mbx_tbl[i].in_args;
 838                         mbx->rsp.num = mbx_tbl[i].out_args;
 839                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 840                                                GFP_ATOMIC);
 841                         if (!mbx->req.arg)
 842                                 return -ENOMEM;
 843                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 844                                                GFP_ATOMIC);
 845                         if (!mbx->rsp.arg) {
 846                                 kfree(mbx->req.arg);
 847                                 mbx->req.arg = NULL;
 848                                 return -ENOMEM;
 849                         }
 850                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 851                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 852                         temp = adapter->ahw->fw_hal_version << 29;
 853                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 854                         mbx->cmd_op = type;
 855                         return 0;
 856                 }
 857         }
 858         return -EINVAL;
 859 }
 860
 861 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 862 {
 863         struct qlcnic_adapter *adapter;
 864         struct qlcnic_cmd_args cmd;
 865         int i, err = 0;
 866
 867         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 868         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 869         if (err)
 870                 return;
 871
 872         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 873                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 874
 875         err = qlcnic_issue_cmd(adapter, &cmd);
 876         if (err)
 877                 dev_info(&adapter->pdev->dev,
 878                          "%s: Mailbox IDC ACK failed.\n", __func__);
 879         qlcnic_free_mbx_args(&cmd);
 880 }
 881
 882 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 883                                             u32 data[])
 884 {
 885         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 886                 QLCNIC_MBX_RSP(data[0]));
 887         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 888         return;
 889 }
 890
 891 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 892 {
 893         struct qlcnic_hardware_context *ahw = adapter->ahw;
 894         u32 event[QLC_83XX_MBX_AEN_CNT];
 895         int i;
 896
 897         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 898                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 899
 900         switch (QLCNIC_MBX_RSP(event[0])) {
 901
 902         case QLCNIC_MBX_LINK_EVENT:
 903                 qlcnic_83xx_handle_link_aen(adapter, event);
 904                 break;
 905         case QLCNIC_MBX_COMP_EVENT:
 906                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 907                 break;
 908         case QLCNIC_MBX_REQUEST_EVENT:
 909                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 910                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 911                 queue_delayed_work(adapter->qlcnic_wq,
 912                                    &adapter->idc_aen_work, 0);
 913                 break;
 914         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 915                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 916                 break;
 917         case QLCNIC_MBX_BC_EVENT:
 918                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 919                 break;
 920         case QLCNIC_MBX_SFP_INSERT_EVENT:
 921                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 922                          QLCNIC_MBX_RSP(event[0]));
 923                 break;
 924         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 925                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
 926                          QLCNIC_MBX_RSP(event[0]));
 927                 break;
 928         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
 929                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
 930                 break;
 931         default:
 932                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
 933                         QLCNIC_MBX_RSP(event[0]));
 934                 break;
 935         }
 936
 937         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 938 }
 939
 940 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 941 {
 942         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 943         struct qlcnic_hardware_context *ahw = adapter->ahw;
 944         struct qlcnic_mailbox *mbx = ahw->mailbox;
 945         unsigned long flags;
 946
 947         spin_lock_irqsave(&mbx->aen_lock, flags);
 948         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 949         if (resp & QLCNIC_SET_OWNER) {
 950                 event = readl(QLCNIC_MBX_FW(ahw, 0));
 951                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 952                         __qlcnic_83xx_process_aen(adapter);
 953                 } else {
 954                         if (atomic_read(&mbx->rsp_status) != rsp_status)
 955                                 qlcnic_83xx_notify_mbx_response(mbx);
 956                 }
 957         }
 958         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 959 }
 960
 961 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
 962 {
 963         struct qlcnic_adapter *adapter;
 964
 965         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
 966
 967         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 968                 return;
 969
 970         qlcnic_83xx_process_aen(adapter);
 971         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
 972                            (HZ / 10));
 973 }
 974
 975 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
 976 {
 977         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 978                 return;
 979
 980         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
 981         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
 982 }
 983
 984 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
 985 {
 986         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 987                 return;
 988         cancel_delayed_work_sync(&adapter->mbx_poll_work);
 989 }
 990
 991 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
 992 {
 993         int index, i, err, sds_mbx_size;
 994         u32 *buf, intrpt_id, intr_mask;
 995         u16 context_id;
 996         u8 num_sds;
 997         struct qlcnic_cmd_args cmd;
 998         struct qlcnic_host_sds_ring *sds;
 999         struct qlcnic_sds_mbx sds_mbx;
1000         struct qlcnic_add_rings_mbx_out *mbx_out;
1001         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1002         struct qlcnic_hardware_context *ahw = adapter->ahw;
1003
1004         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1005         context_id = recv_ctx->context_id;
1006         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
1007         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1008                                     QLCNIC_CMD_ADD_RCV_RINGS);
1009         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1010
1011         /* set up status rings, mbx 2-81 */
1012         index = 2;
1013         for (i = 8; i < adapter->drv_sds_rings; i++) {
1014                 memset(&sds_mbx, 0, sds_mbx_size);
1015                 sds = &recv_ctx->sds_rings[i];
1016                 sds->consumer = 0;
1017                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1018                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1019                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1020                 sds_mbx.sds_ring_size = sds->num_desc;
1021
1022                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1023                         intrpt_id = ahw->intr_tbl[i].id;
1024                 else
1025                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1026
1027                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1028                         sds_mbx.intrpt_id = intrpt_id;
1029                 else
1030                         sds_mbx.intrpt_id = 0xffff;
1031                 sds_mbx.intrpt_val = 0;
1032                 buf = &cmd.req.arg[index];
1033                 memcpy(buf, &sds_mbx, sds_mbx_size);
1034                 index += sds_mbx_size / sizeof(u32);
1035         }
1036
1037         /* send the mailbox command */
1038         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1039         if (err) {
1040                 dev_err(&adapter->pdev->dev,
1041                         "Failed to add rings %d\n", err);
1042                 goto out;
1043         }
1044
1045         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1046         index = 0;
1047         /* status descriptor ring */
1048         for (i = 8; i < adapter->drv_sds_rings; i++) {
1049                 sds = &recv_ctx->sds_rings[i];
1050                 sds->crb_sts_consumer = ahw->pci_base0 +
1051                                         mbx_out->host_csmr[index];
1052                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1053                         intr_mask = ahw->intr_tbl[i].src;
1054                 else
1055                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1056
1057                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1058                 index++;
1059         }
1060 out:
1061         qlcnic_free_mbx_args(&cmd);
1062         return err;
1063 }
1064
1065 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1066 {
1067         int err;
1068         u32 temp = 0;
1069         struct qlcnic_cmd_args cmd;
1070         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1071
1072         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1073                 return;
1074
1075         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1076                 cmd.req.arg[0] |= (0x3 << 29);
1077
1078         if (qlcnic_sriov_pf_check(adapter))
1079                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1080
1081         cmd.req.arg[1] = recv_ctx->context_id | temp;
1082         err = qlcnic_issue_cmd(adapter, &cmd);
1083         if (err)
1084                 dev_err(&adapter->pdev->dev,
1085                         "Failed to destroy rx ctx in firmware\n");
1086
1087         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1088         qlcnic_free_mbx_args(&cmd);
1089 }
1090
1091 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1092 {
1093         int i, err, index, sds_mbx_size, rds_mbx_size;
1094         u8 num_sds, num_rds;
1095         u32 *buf, intrpt_id, intr_mask, cap = 0;
1096         struct qlcnic_host_sds_ring *sds;
1097         struct qlcnic_host_rds_ring *rds;
1098         struct qlcnic_sds_mbx sds_mbx;
1099         struct qlcnic_rds_mbx rds_mbx;
1100         struct qlcnic_cmd_args cmd;
1101         struct qlcnic_rcv_mbx_out *mbx_out;
1102         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1103         struct qlcnic_hardware_context *ahw = adapter->ahw;
1104         num_rds = adapter->max_rds_rings;
1105
1106         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1107                 num_sds = adapter->drv_sds_rings;
1108         else
1109                 num_sds = QLCNIC_MAX_SDS_RINGS;
1110
1111         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1112         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1113         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1114
1115         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1116                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1117
1118         /* set mailbox hdr and capabilities */
1119         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1120                                     QLCNIC_CMD_CREATE_RX_CTX);
1121         if (err)
1122                 return err;
1123
1124         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1125                 cmd.req.arg[0] |= (0x3 << 29);
1126
1127         cmd.req.arg[1] = cap;
1128         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1129                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1130
1131         if (qlcnic_sriov_pf_check(adapter))
1132                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1133                                                          &cmd.req.arg[6]);
1134         /* set up status rings, mbx 8-57/87 */
1135         index = QLC_83XX_HOST_SDS_MBX_IDX;
1136         for (i = 0; i < num_sds; i++) {
1137                 memset(&sds_mbx, 0, sds_mbx_size);
1138                 sds = &recv_ctx->sds_rings[i];
1139                 sds->consumer = 0;
1140                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1141                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1142                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1143                 sds_mbx.sds_ring_size = sds->num_desc;
1144                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1145                         intrpt_id = ahw->intr_tbl[i].id;
1146                 else
1147                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1148                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1149                         sds_mbx.intrpt_id = intrpt_id;
1150                 else
1151                         sds_mbx.intrpt_id = 0xffff;
1152                 sds_mbx.intrpt_val = 0;
1153                 buf = &cmd.req.arg[index];
1154                 memcpy(buf, &sds_mbx, sds_mbx_size);
1155                 index += sds_mbx_size / sizeof(u32);
1156         }
1157         /* set up receive rings, mbx 88-111/135 */
1158         index = QLCNIC_HOST_RDS_MBX_IDX;
1159         rds = &recv_ctx->rds_rings[0];
1160         rds->producer = 0;
1161         memset(&rds_mbx, 0, rds_mbx_size);
1162         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1163         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1164         rds_mbx.reg_ring_sz = rds->dma_size;
1165         rds_mbx.reg_ring_len = rds->num_desc;
1166         /* Jumbo ring */
1167         rds = &recv_ctx->rds_rings[1];
1168         rds->producer = 0;
1169         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1170         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1171         rds_mbx.jmb_ring_sz = rds->dma_size;
1172         rds_mbx.jmb_ring_len = rds->num_desc;
1173         buf = &cmd.req.arg[index];
1174         memcpy(buf, &rds_mbx, rds_mbx_size);
1175
1176         /* send the mailbox command */
1177         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1178         if (err) {
1179                 dev_err(&adapter->pdev->dev,
1180                         "Failed to create Rx ctx in firmware%d\n", err);
1181                 goto out;
1182         }
1183         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1184         recv_ctx->context_id = mbx_out->ctx_id;
1185         recv_ctx->state = mbx_out->state;
1186         recv_ctx->virt_port = mbx_out->vport_id;
1187         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1188                  recv_ctx->context_id, recv_ctx->state);
1189         /* Receive descriptor ring */
1190         /* Standard ring */
1191         rds = &recv_ctx->rds_rings[0];
1192         rds->crb_rcv_producer = ahw->pci_base0 +
1193                                 mbx_out->host_prod[0].reg_buf;
1194         /* Jumbo ring */
1195         rds = &recv_ctx->rds_rings[1];
1196         rds->crb_rcv_producer = ahw->pci_base0 +
1197                                 mbx_out->host_prod[0].jmb_buf;
1198         /* status descriptor ring */
1199         for (i = 0; i < num_sds; i++) {
1200                 sds = &recv_ctx->sds_rings[i];
1201                 sds->crb_sts_consumer = ahw->pci_base0 +
1202                                         mbx_out->host_csmr[i];
1203                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1204                         intr_mask = ahw->intr_tbl[i].src;
1205                 else
1206                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1207                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1208         }
1209
1210         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1211                 err = qlcnic_83xx_add_rings(adapter);
1212 out:
1213         qlcnic_free_mbx_args(&cmd);
1214         return err;
1215 }
1216
1217 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1218                             struct qlcnic_host_tx_ring *tx_ring)
1219 {
1220         struct qlcnic_cmd_args cmd;
1221         u32 temp = 0;
1222
1223         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1224                 return;
1225
1226         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1227                 cmd.req.arg[0] |= (0x3 << 29);
1228
1229         if (qlcnic_sriov_pf_check(adapter))
1230                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1231
1232         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1233         if (qlcnic_issue_cmd(adapter, &cmd))
1234                 dev_err(&adapter->pdev->dev,
1235                         "Failed to destroy tx ctx in firmware\n");
1236         qlcnic_free_mbx_args(&cmd);
1237 }
1238
1239 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1240                               struct qlcnic_host_tx_ring *tx, int ring)
1241 {
1242         int err;
1243         u16 msix_id;
1244         u32 *buf, intr_mask, temp = 0;
1245         struct qlcnic_cmd_args cmd;
1246         struct qlcnic_tx_mbx mbx;
1247         struct qlcnic_tx_mbx_out *mbx_out;
1248         struct qlcnic_hardware_context *ahw = adapter->ahw;
1249         u32 msix_vector;
1250
1251         /* Reset host resources */
1252         tx->producer = 0;
1253         tx->sw_consumer = 0;
1254         *(tx->hw_consumer) = 0;
1255
1256         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1257
1258         /* setup mailbox inbox registerss */
1259         mbx.phys_addr_low = LSD(tx->phys_addr);
1260         mbx.phys_addr_high = MSD(tx->phys_addr);
1261         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1262         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1263         mbx.size = tx->num_desc;
1264         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1265                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1266                         msix_vector = adapter->drv_sds_rings + ring;
1267                 else
1268                         msix_vector = adapter->drv_sds_rings - 1;
1269                 msix_id = ahw->intr_tbl[msix_vector].id;
1270         } else {
1271                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1272         }
1273
1274         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1275                 mbx.intr_id = msix_id;
1276         else
1277                 mbx.intr_id = 0xffff;
1278         mbx.src = 0;
1279
1280         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1281         if (err)
1282                 return err;
1283
1284         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1285                 cmd.req.arg[0] |= (0x3 << 29);
1286
1287         if (qlcnic_sriov_pf_check(adapter))
1288                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1289
1290         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1291         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1292
1293         buf = &cmd.req.arg[6];
1294         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1295         /* send the mailbox command*/
1296         err = qlcnic_issue_cmd(adapter, &cmd);
1297         if (err) {
1298                 dev_err(&adapter->pdev->dev,
1299                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1300                 goto out;
1301         }
1302         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1303         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1304         tx->ctx_id = mbx_out->ctx_id;
1305         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1306             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1307                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1308                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1309         }
1310         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1311                  tx->ctx_id, mbx_out->state);
1312 out:
1313         qlcnic_free_mbx_args(&cmd);
1314         return err;
1315 }
1316
1317 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1318                                       u8 num_sds_ring)
1319 {
1320         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1321         struct qlcnic_host_sds_ring *sds_ring;
1322         struct qlcnic_host_rds_ring *rds_ring;
1323         u16 adapter_state = adapter->is_up;
1324         u8 ring;
1325         int ret;
1326
1327         netif_device_detach(netdev);
1328
1329         if (netif_running(netdev))
1330                 __qlcnic_down(adapter, netdev);
1331
1332         qlcnic_detach(adapter);
1333
1334         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1335         adapter->ahw->diag_test = test;
1336         adapter->ahw->linkup = 0;
1337
1338         ret = qlcnic_attach(adapter);
1339         if (ret) {
1340                 netif_device_attach(netdev);
1341                 return ret;
1342         }
1343
1344         ret = qlcnic_fw_create_ctx(adapter);
1345         if (ret) {
1346                 qlcnic_detach(adapter);
1347                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1348                         adapter->drv_sds_rings = num_sds_ring;
1349                         qlcnic_attach(adapter);
1350                 }
1351                 netif_device_attach(netdev);
1352                 return ret;
1353         }
1354
1355         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1356                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1357                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1358         }
1359
1360         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1361                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1362                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1363                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1364                 }
1365         }
1366
1367         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1368                 adapter->ahw->loopback_state = 0;
1369                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1370         }
1371
1372         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1373         return 0;
1374 }
1375
1376 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1377                                       u8 drv_sds_rings)
1378 {
1379         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1380         struct qlcnic_host_sds_ring *sds_ring;
1381         int ring;
1382
1383         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1384         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1385                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1386                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1387                         if (adapter->flags & QLCNIC_MSIX_ENABLED)
1388                                 qlcnic_83xx_disable_intr(adapter, sds_ring);
1389                 }
1390         }
1391
1392         qlcnic_fw_destroy_ctx(adapter);
1393         qlcnic_detach(adapter);
1394
1395         adapter->ahw->diag_test = 0;
1396         adapter->drv_sds_rings = drv_sds_rings;
1397
1398         if (qlcnic_attach(adapter))
1399                 goto out;
1400
1401         if (netif_running(netdev))
1402                 __qlcnic_up(adapter, netdev);
1403
1404 out:
1405         netif_device_attach(netdev);
1406 }
1407
1408 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1409 {
1410         struct qlcnic_hardware_context *ahw = adapter->ahw;
1411         struct qlcnic_cmd_args cmd;
1412         u8 beacon_state;
1413         int err = 0;
1414
1415         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1416         if (!err) {
1417                 err = qlcnic_issue_cmd(adapter, &cmd);
1418                 if (!err) {
1419                         beacon_state = cmd.rsp.arg[4];
1420                         if (beacon_state == QLCNIC_BEACON_DISABLE)
1421                                 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1422                         else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1423                                 ahw->beacon_state = QLC_83XX_BEACON_ON;
1424                 }
1425         } else {
1426                 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1427                            err);
1428         }
1429
1430         qlcnic_free_mbx_args(&cmd);
1431
1432         return;
1433 }
1434
1435 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1436                            u32 beacon)
1437 {
1438         struct qlcnic_cmd_args cmd;
1439         u32 mbx_in;
1440         int i, status = 0;
1441
1442         if (state) {
1443                 /* Get LED configuration */
1444                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1445                                                QLCNIC_CMD_GET_LED_CONFIG);
1446                 if (status)
1447                         return status;
1448
1449                 status = qlcnic_issue_cmd(adapter, &cmd);
1450                 if (status) {
1451                         dev_err(&adapter->pdev->dev,
1452                                 "Get led config failed.\n");
1453                         goto mbx_err;
1454                 } else {
1455                         for (i = 0; i < 4; i++)
1456                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1457                 }
1458                 qlcnic_free_mbx_args(&cmd);
1459                 /* Set LED Configuration */
1460                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1461                           LSW(QLC_83XX_LED_CONFIG);
1462                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1463                                                QLCNIC_CMD_SET_LED_CONFIG);
1464                 if (status)
1465                         return status;
1466
1467                 cmd.req.arg[1] = mbx_in;
1468                 cmd.req.arg[2] = mbx_in;
1469                 cmd.req.arg[3] = mbx_in;
1470                 if (beacon)
1471                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1472                 status = qlcnic_issue_cmd(adapter, &cmd);
1473                 if (status) {
1474                         dev_err(&adapter->pdev->dev,
1475                                 "Set led config failed.\n");
1476                 }
1477 mbx_err:
1478                 qlcnic_free_mbx_args(&cmd);
1479                 return status;
1480
1481         } else {
1482                 /* Restoring default LED configuration */
1483                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1484                                                QLCNIC_CMD_SET_LED_CONFIG);
1485                 if (status)
1486                         return status;
1487
1488                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1489                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1490                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1491                 if (beacon)
1492                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1493                 status = qlcnic_issue_cmd(adapter, &cmd);
1494                 if (status)
1495                         dev_err(&adapter->pdev->dev,
1496                                 "Restoring led config failed.\n");
1497                 qlcnic_free_mbx_args(&cmd);
1498                 return status;
1499         }
1500 }
1501
1502 int  qlcnic_83xx_set_led(struct net_device *netdev,
1503                          enum ethtool_phys_id_state state)
1504 {
1505         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1506         int err = -EIO, active = 1;
1507
1508         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1509                 netdev_warn(netdev,
1510                             "LED test is not supported in non-privileged mode\n");
1511                 return -EOPNOTSUPP;
1512         }
1513
1514         switch (state) {
1515         case ETHTOOL_ID_ACTIVE:
1516                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1517                         return -EBUSY;
1518
1519                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1520                         break;
1521
1522                 err = qlcnic_83xx_config_led(adapter, active, 0);
1523                 if (err)
1524                         netdev_err(netdev, "Failed to set LED blink state\n");
1525                 break;
1526         case ETHTOOL_ID_INACTIVE:
1527                 active = 0;
1528
1529                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1530                         break;
1531
1532                 err = qlcnic_83xx_config_led(adapter, active, 0);
1533                 if (err)
1534                         netdev_err(netdev, "Failed to reset LED blink state\n");
1535                 break;
1536
1537         default:
1538                 return -EINVAL;
1539         }
1540
1541         if (!active || err)
1542                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1543
1544         return err;
1545 }
1546
1547 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1548 {
1549         struct qlcnic_cmd_args cmd;
1550         int status;
1551
1552         if (qlcnic_sriov_vf_check(adapter))
1553                 return;
1554
1555         if (enable)
1556                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1557                                                QLCNIC_CMD_INIT_NIC_FUNC);
1558         else
1559                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1560                                                QLCNIC_CMD_STOP_NIC_FUNC);
1561
1562         if (status)
1563                 return;
1564
1565         cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1566
1567         if (adapter->dcb)
1568                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1569
1570         status = qlcnic_issue_cmd(adapter, &cmd);
1571         if (status)
1572                 dev_err(&adapter->pdev->dev,
1573                         "Failed to %s in NIC IDC function event.\n",
1574                         (enable ? "register" : "unregister"));
1575
1576         qlcnic_free_mbx_args(&cmd);
1577 }
1578
1579 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1580 {
1581         struct qlcnic_cmd_args cmd;
1582         int err;
1583
1584         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1585         if (err)
1586                 return err;
1587
1588         cmd.req.arg[1] = adapter->ahw->port_config;
1589         err = qlcnic_issue_cmd(adapter, &cmd);
1590         if (err)
1591                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1592         qlcnic_free_mbx_args(&cmd);
1593         return err;
1594 }
1595
1596 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1597 {
1598         struct qlcnic_cmd_args cmd;
1599         int err;
1600
1601         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1602         if (err)
1603                 return err;
1604
1605         err = qlcnic_issue_cmd(adapter, &cmd);
1606         if (err)
1607                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1608         else
1609                 adapter->ahw->port_config = cmd.rsp.arg[1];
1610         qlcnic_free_mbx_args(&cmd);
1611         return err;
1612 }
1613
1614 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1615 {
1616         int err;
1617         u32 temp;
1618         struct qlcnic_cmd_args cmd;
1619
1620         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1621         if (err)
1622                 return err;
1623
1624         temp = adapter->recv_ctx->context_id << 16;
1625         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1626         err = qlcnic_issue_cmd(adapter, &cmd);
1627         if (err)
1628                 dev_info(&adapter->pdev->dev,
1629                          "Setup linkevent mailbox failed\n");
1630         qlcnic_free_mbx_args(&cmd);
1631         return err;
1632 }
1633
1634 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1635                                                  u32 *interface_id)
1636 {
1637         if (qlcnic_sriov_pf_check(adapter)) {
1638                 qlcnic_alloc_lb_filters_mem(adapter);
1639                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1640                 adapter->rx_mac_learn = 1;
1641         } else {
1642                 if (!qlcnic_sriov_vf_check(adapter))
1643                         *interface_id = adapter->recv_ctx->context_id << 16;
1644         }
1645 }
1646
1647 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1648 {
1649         struct qlcnic_cmd_args *cmd = NULL;
1650         u32 temp = 0;
1651         int err;
1652
1653         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1654                 return -EIO;
1655
1656         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1657         if (!cmd)
1658                 return -ENOMEM;
1659
1660         err = qlcnic_alloc_mbx_args(cmd, adapter,
1661                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1662         if (err)
1663                 goto out;
1664
1665         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1666         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1667
1668         if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1669                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1670
1671         cmd->req.arg[1] = mode | temp;
1672         err = qlcnic_issue_cmd(adapter, cmd);
1673         if (!err)
1674                 return err;
1675
1676         qlcnic_free_mbx_args(cmd);
1677
1678 out:
1679         kfree(cmd);
1680         return err;
1681 }
1682
1683 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1684 {
1685         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1686         struct qlcnic_hardware_context *ahw = adapter->ahw;
1687         u8 drv_sds_rings = adapter->drv_sds_rings;
1688         u8 drv_tx_rings = adapter->drv_tx_rings;
1689         int ret = 0, loop = 0;
1690
1691         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1692                 netdev_warn(netdev,
1693                             "Loopback test not supported in non privileged mode\n");
1694                 return -ENOTSUPP;
1695         }
1696
1697         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1698                 netdev_info(netdev, "Device is resetting\n");
1699                 return -EBUSY;
1700         }
1701
1702         if (qlcnic_get_diag_lock(adapter)) {
1703                 netdev_info(netdev, "Device is in diagnostics mode\n");
1704                 return -EBUSY;
1705         }
1706
1707         netdev_info(netdev, "%s loopback test in progress\n",
1708                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1709
1710         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1711                                          drv_sds_rings);
1712         if (ret)
1713                 goto fail_diag_alloc;
1714
1715         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1716         if (ret)
1717                 goto free_diag_res;
1718
1719         /* Poll for link up event before running traffic */
1720         do {
1721                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1722
1723                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1724                         netdev_info(netdev,
1725                                     "Device is resetting, free LB test resources\n");
1726                         ret = -EBUSY;
1727                         goto free_diag_res;
1728                 }
1729                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1730                         netdev_info(netdev,
1731                                     "Firmware didn't sent link up event to loopback request\n");
1732                         ret = -ETIMEDOUT;
1733                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1734                         goto free_diag_res;
1735                 }
1736         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1737
1738         ret = qlcnic_do_lb_test(adapter, mode);
1739
1740         qlcnic_83xx_clear_lb_mode(adapter, mode);
1741
1742 free_diag_res:
1743         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1744
1745 fail_diag_alloc:
1746         adapter->drv_sds_rings = drv_sds_rings;
1747         adapter->drv_tx_rings = drv_tx_rings;
1748         qlcnic_release_diag_lock(adapter);
1749         return ret;
1750 }
1751
1752 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1753                                              u32 *max_wait_count)
1754 {
1755         struct qlcnic_hardware_context *ahw = adapter->ahw;
1756         int temp;
1757
1758         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1759                     ahw->extend_lb_time);
1760         temp = ahw->extend_lb_time * 1000;
1761         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1762         ahw->extend_lb_time = 0;
1763 }
1764
1765 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1766 {
1767         struct qlcnic_hardware_context *ahw = adapter->ahw;
1768         struct net_device *netdev = adapter->netdev;
1769         u32 config, max_wait_count;
1770         int status = 0, loop = 0;
1771
1772         ahw->extend_lb_time = 0;
1773         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1774         status = qlcnic_83xx_get_port_config(adapter);
1775         if (status)
1776                 return status;
1777
1778         config = ahw->port_config;
1779
1780         /* Check if port is already in loopback mode */
1781         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1782             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1783                 netdev_err(netdev,
1784                            "Port already in Loopback mode.\n");
1785                 return -EINPROGRESS;
1786         }
1787
1788         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1789
1790         if (mode == QLCNIC_ILB_MODE)
1791                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1792         if (mode == QLCNIC_ELB_MODE)
1793                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1794
1795         status = qlcnic_83xx_set_port_config(adapter);
1796         if (status) {
1797                 netdev_err(netdev,
1798                            "Failed to Set Loopback Mode = 0x%x.\n",
1799                            ahw->port_config);
1800                 ahw->port_config = config;
1801                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1802                 return status;
1803         }
1804
1805         /* Wait for Link and IDC Completion AEN */
1806         do {
1807                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1808
1809                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1810                         netdev_info(netdev,
1811                                     "Device is resetting, free LB test resources\n");
1812                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1813                         return -EBUSY;
1814                 }
1815
1816                 if (ahw->extend_lb_time)
1817                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1818                                                          &max_wait_count);
1819
1820                 if (loop++ > max_wait_count) {
1821                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1822                                    __func__);
1823                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1824                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1825                         return -ETIMEDOUT;
1826                 }
1827         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1828
1829         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1830                                   QLCNIC_MAC_ADD);
1831         return status;
1832 }
1833
1834 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1835 {
1836         struct qlcnic_hardware_context *ahw = adapter->ahw;
1837         u32 config = ahw->port_config, max_wait_count;
1838         struct net_device *netdev = adapter->netdev;
1839         int status = 0, loop = 0;
1840
1841         ahw->extend_lb_time = 0;
1842         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1843         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1844         if (mode == QLCNIC_ILB_MODE)
1845                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1846         if (mode == QLCNIC_ELB_MODE)
1847                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1848
1849         status = qlcnic_83xx_set_port_config(adapter);
1850         if (status) {
1851                 netdev_err(netdev,
1852                            "Failed to Clear Loopback Mode = 0x%x.\n",
1853                            ahw->port_config);
1854                 ahw->port_config = config;
1855                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1856                 return status;
1857         }
1858
1859         /* Wait for Link and IDC Completion AEN */
1860         do {
1861                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1862
1863                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1864                         netdev_info(netdev,
1865                                     "Device is resetting, free LB test resources\n");
1866                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1867                         return -EBUSY;
1868                 }
1869
1870                 if (ahw->extend_lb_time)
1871                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1872                                                          &max_wait_count);
1873
1874                 if (loop++ > max_wait_count) {
1875                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1876                                    __func__);
1877                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1878                         return -ETIMEDOUT;
1879                 }
1880         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1881
1882         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1883                                   QLCNIC_MAC_DEL);
1884         return status;
1885 }
1886
1887 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1888                                                 u32 *interface_id)
1889 {
1890         if (qlcnic_sriov_pf_check(adapter)) {
1891                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1892         } else {
1893                 if (!qlcnic_sriov_vf_check(adapter))
1894                         *interface_id = adapter->recv_ctx->context_id << 16;
1895         }
1896 }
1897
1898 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1899                                int mode)
1900 {
1901         int err;
1902         u32 temp = 0, temp_ip;
1903         struct qlcnic_cmd_args cmd;
1904
1905         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1906                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1907         if (err)
1908                 return;
1909
1910         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1911
1912         if (mode == QLCNIC_IP_UP)
1913                 cmd.req.arg[1] = 1 | temp;
1914         else
1915                 cmd.req.arg[1] = 2 | temp;
1916
1917         /*
1918          * Adapter needs IP address in network byte order.
1919          * But hardware mailbox registers go through writel(), hence IP address
1920          * gets swapped on big endian architecture.
1921          * To negate swapping of writel() on big endian architecture
1922          * use swab32(value).
1923          */
1924
1925         temp_ip = swab32(ntohl(ip));
1926         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1927         err = qlcnic_issue_cmd(adapter, &cmd);
1928         if (err != QLCNIC_RCODE_SUCCESS)
1929                 dev_err(&adapter->netdev->dev,
1930                         "could not notify %s IP 0x%x request\n",
1931                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1932
1933         qlcnic_free_mbx_args(&cmd);
1934 }
1935
1936 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1937 {
1938         int err;
1939         u32 temp, arg1;
1940         struct qlcnic_cmd_args cmd;
1941         int lro_bit_mask;
1942
1943         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1944
1945         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1946                 return 0;
1947
1948         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1949         if (err)
1950                 return err;
1951
1952         temp = adapter->recv_ctx->context_id << 16;
1953         arg1 = lro_bit_mask | temp;
1954         cmd.req.arg[1] = arg1;
1955
1956         err = qlcnic_issue_cmd(adapter, &cmd);
1957         if (err)
1958                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1959         qlcnic_free_mbx_args(&cmd);
1960
1961         return err;
1962 }
1963
1964 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1965 {
1966         int err;
1967         u32 word;
1968         struct qlcnic_cmd_args cmd;
1969         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1970                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1971                             0x255b0ec26d5a56daULL };
1972
1973         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1974         if (err)
1975                 return err;
1976         /*
1977          * RSS request:
1978          * bits 3-0: Rsvd
1979          *      5-4: hash_type_ipv4
1980          *      7-6: hash_type_ipv6
1981          *        8: enable
1982          *        9: use indirection table
1983          *    16-31: indirection table mask
1984          */
1985         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1986                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1987                 ((u32)(enable & 0x1) << 8) |
1988                 ((0x7ULL) << 16);
1989         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1990         cmd.req.arg[2] = word;
1991         memcpy(&cmd.req.arg[4], key, sizeof(key));
1992
1993         err = qlcnic_issue_cmd(adapter, &cmd);
1994
1995         if (err)
1996                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1997         qlcnic_free_mbx_args(&cmd);
1998
1999         return err;
2000
2001 }
2002
2003 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2004                                                  u32 *interface_id)
2005 {
2006         if (qlcnic_sriov_pf_check(adapter)) {
2007                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2008         } else {
2009                 if (!qlcnic_sriov_vf_check(adapter))
2010                         *interface_id = adapter->recv_ctx->context_id << 16;
2011         }
2012 }
2013
2014 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2015                                    u16 vlan_id, u8 op)
2016 {
2017         struct qlcnic_cmd_args *cmd = NULL;
2018         struct qlcnic_macvlan_mbx mv;
2019         u32 *buf, temp = 0;
2020         int err;
2021
2022         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2023                 return -EIO;
2024
2025         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2026         if (!cmd)
2027                 return -ENOMEM;
2028
2029         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2030         if (err)
2031                 goto out;
2032
2033         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2034
2035         if (vlan_id)
2036                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2037                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2038
2039         cmd->req.arg[1] = op | (1 << 8);
2040         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2041         cmd->req.arg[1] |= temp;
2042         mv.vlan = vlan_id;
2043         mv.mac_addr0 = addr[0];
2044         mv.mac_addr1 = addr[1];
2045         mv.mac_addr2 = addr[2];
2046         mv.mac_addr3 = addr[3];
2047         mv.mac_addr4 = addr[4];
2048         mv.mac_addr5 = addr[5];
2049         buf = &cmd->req.arg[2];
2050         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2051         err = qlcnic_issue_cmd(adapter, cmd);
2052         if (!err)
2053                 return err;
2054
2055         qlcnic_free_mbx_args(cmd);
2056 out:
2057         kfree(cmd);
2058         return err;
2059 }
2060
2061 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2062                                   u16 vlan_id)
2063 {
2064         u8 mac[ETH_ALEN];
2065         memcpy(&mac, addr, ETH_ALEN);
2066         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2067 }
2068
2069 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2070                                       u8 type, struct qlcnic_cmd_args *cmd)
2071 {
2072         switch (type) {
2073         case QLCNIC_SET_STATION_MAC:
2074         case QLCNIC_SET_FAC_DEF_MAC:
2075                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2076                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2077                 break;
2078         }
2079         cmd->req.arg[1] = type;
2080 }
2081
2082 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2083                                 u8 function)
2084 {
2085         int err, i;
2086         struct qlcnic_cmd_args cmd;
2087         u32 mac_low, mac_high;
2088
2089         function = 0;
2090         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2091         if (err)
2092                 return err;
2093
2094         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2095         err = qlcnic_issue_cmd(adapter, &cmd);
2096
2097         if (err == QLCNIC_RCODE_SUCCESS) {
2098                 mac_low = cmd.rsp.arg[1];
2099                 mac_high = cmd.rsp.arg[2];
2100
2101                 for (i = 0; i < 2; i++)
2102                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2103                 for (i = 2; i < 6; i++)
2104                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2105         } else {
2106                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2107                         err);
2108                 err = -EIO;
2109         }
2110         qlcnic_free_mbx_args(&cmd);
2111         return err;
2112 }
2113
2114 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2115 {
2116         int err;
2117         u16 temp;
2118         struct qlcnic_cmd_args cmd;
2119         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2120
2121         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2122                 return;
2123
2124         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2125         if (err)
2126                 return;
2127
2128         if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2129                 temp = adapter->recv_ctx->context_id;
2130                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2131                 temp = coal->rx_time_us;
2132                 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2133         } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2134                 temp = adapter->tx_ring->ctx_id;
2135                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2136                 temp = coal->tx_time_us;
2137                 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2138         }
2139         cmd.req.arg[3] = coal->flag;
2140         err = qlcnic_issue_cmd(adapter, &cmd);
2141         if (err != QLCNIC_RCODE_SUCCESS)
2142                 dev_info(&adapter->pdev->dev,
2143                          "Failed to send interrupt coalescence parameters\n");
2144         qlcnic_free_mbx_args(&cmd);
2145 }
2146
2147 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2148                                         u32 data[])
2149 {
2150         struct qlcnic_hardware_context *ahw = adapter->ahw;
2151         u8 link_status, duplex;
2152         /* link speed */
2153         link_status = LSB(data[3]) & 1;
2154         if (link_status) {
2155                 ahw->link_speed = MSW(data[2]);
2156                 duplex = LSB(MSW(data[3]));
2157                 if (duplex)
2158                         ahw->link_duplex = DUPLEX_FULL;
2159                 else
2160                         ahw->link_duplex = DUPLEX_HALF;
2161         } else {
2162                 ahw->link_speed = SPEED_UNKNOWN;
2163                 ahw->link_duplex = DUPLEX_UNKNOWN;
2164         }
2165
2166         ahw->link_autoneg = MSB(MSW(data[3]));
2167         ahw->module_type = MSB(LSW(data[3]));
2168         ahw->has_link_events = 1;
2169         ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2170         qlcnic_advert_link_change(adapter, link_status);
2171 }
2172
2173 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2174 {
2175         struct qlcnic_adapter *adapter = data;
2176         struct qlcnic_mailbox *mbx;
2177         u32 mask, resp, event;
2178         unsigned long flags;
2179
2180         mbx = adapter->ahw->mailbox;
2181         spin_lock_irqsave(&mbx->aen_lock, flags);
2182         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2183         if (!(resp & QLCNIC_SET_OWNER))
2184                 goto out;
2185
2186         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2187         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2188                 __qlcnic_83xx_process_aen(adapter);
2189         else
2190                 qlcnic_83xx_notify_mbx_response(mbx);
2191
2192 out:
2193         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2194         writel(0, adapter->ahw->pci_base0 + mask);
2195         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2196         return IRQ_HANDLED;
2197 }
2198
2199 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2200                              struct qlcnic_info *nic)
2201 {
2202         int i, err = -EIO;
2203         struct qlcnic_cmd_args cmd;
2204
2205         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2206                 dev_err(&adapter->pdev->dev,
2207                         "%s: Error, invoked by non management func\n",
2208                         __func__);
2209                 return err;
2210         }
2211
2212         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2213         if (err)
2214                 return err;
2215
2216         cmd.req.arg[1] = (nic->pci_func << 16);
2217         cmd.req.arg[2] = 0x1 << 16;
2218         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2219         cmd.req.arg[4] = nic->capabilities;
2220         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2221         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2222         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2223         for (i = 8; i < 32; i++)
2224                 cmd.req.arg[i] = 0;
2225
2226         err = qlcnic_issue_cmd(adapter, &cmd);
2227
2228         if (err != QLCNIC_RCODE_SUCCESS) {
2229                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2230                         err);
2231                 err = -EIO;
2232         }
2233
2234         qlcnic_free_mbx_args(&cmd);
2235
2236         return err;
2237 }
2238
2239 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2240                              struct qlcnic_info *npar_info, u8 func_id)
2241 {
2242         int err;
2243         u32 temp;
2244         u8 op = 0;
2245         struct qlcnic_cmd_args cmd;
2246         struct qlcnic_hardware_context *ahw = adapter->ahw;
2247
2248         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2249         if (err)
2250                 return err;
2251
2252         if (func_id != ahw->pci_func) {
2253                 temp = func_id << 16;
2254                 cmd.req.arg[1] = op | BIT_31 | temp;
2255         } else {
2256                 cmd.req.arg[1] = ahw->pci_func << 16;
2257         }
2258         err = qlcnic_issue_cmd(adapter, &cmd);
2259         if (err) {
2260                 dev_info(&adapter->pdev->dev,
2261                          "Failed to get nic info %d\n", err);
2262                 goto out;
2263         }
2264
2265         npar_info->op_type = cmd.rsp.arg[1];
2266         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2267         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2268         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2269         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2270         npar_info->capabilities = cmd.rsp.arg[4];
2271         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2272         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2273         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2274         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2275         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2276         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2277         if (cmd.rsp.arg[8] & 0x1)
2278                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2279         if (cmd.rsp.arg[8] & 0x10000) {
2280                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2281                 npar_info->max_linkspeed_reg_offset = temp;
2282         }
2283
2284         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2285                sizeof(ahw->extra_capability));
2286
2287 out:
2288         qlcnic_free_mbx_args(&cmd);
2289         return err;
2290 }
2291
2292 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2293                              u16 *nic, u16 *fcoe, u16 *iscsi)
2294 {
2295         struct device *dev = &adapter->pdev->dev;
2296         int err = 0;
2297
2298         switch (type) {
2299         case QLCNIC_TYPE_NIC:
2300                 (*nic)++;
2301                 break;
2302         case QLCNIC_TYPE_FCOE:
2303                 (*fcoe)++;
2304                 break;
2305         case QLCNIC_TYPE_ISCSI:
2306                 (*iscsi)++;
2307                 break;
2308         default:
2309                 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2310                         __func__, type);
2311                 err = -EIO;
2312         }
2313
2314         return err;
2315 }
2316
2317 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2318                              struct qlcnic_pci_info *pci_info)
2319 {
2320         struct qlcnic_hardware_context *ahw = adapter->ahw;
2321         struct device *dev = &adapter->pdev->dev;
2322         u16 nic = 0, fcoe = 0, iscsi = 0;
2323         struct qlcnic_cmd_args cmd;
2324         int i, err = 0, j = 0;
2325         u32 temp;
2326
2327         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2328         if (err)
2329                 return err;
2330
2331         err = qlcnic_issue_cmd(adapter, &cmd);
2332
2333         ahw->total_nic_func = 0;
2334         if (err == QLCNIC_RCODE_SUCCESS) {
2335                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2336                 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2337                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2338                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2339                         i++;
2340                         if (!pci_info->active) {
2341                                 i += QLC_SKIP_INACTIVE_PCI_REGS;
2342                                 continue;
2343                         }
2344                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2345                         err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2346                                                        &nic, &fcoe, &iscsi);
2347                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2348                         pci_info->default_port = temp;
2349                         i++;
2350                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2351                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2352                         pci_info->tx_max_bw = temp;
2353                         i = i + 2;
2354                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2355                         i++;
2356                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2357                         i = i + 3;
2358                 }
2359         } else {
2360                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2361                 err = -EIO;
2362         }
2363
2364         ahw->total_nic_func = nic;
2365         ahw->total_pci_func = nic + fcoe + iscsi;
2366         if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2367                 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2368                         __func__, ahw->total_nic_func, ahw->total_pci_func);
2369                 err = -EIO;
2370         }
2371         qlcnic_free_mbx_args(&cmd);
2372
2373         return err;
2374 }
2375
2376 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2377 {
2378         int i, index, err;
2379         u8 max_ints;
2380         u32 val, temp, type;
2381         struct qlcnic_cmd_args cmd;
2382
2383         max_ints = adapter->ahw->num_msix - 1;
2384         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2385         if (err)
2386                 return err;
2387
2388         cmd.req.arg[1] = max_ints;
2389
2390         if (qlcnic_sriov_vf_check(adapter))
2391                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2392
2393         for (i = 0, index = 2; i < max_ints; i++) {
2394                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2395                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2396                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2397                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2398                 cmd.req.arg[index++] = val;
2399         }
2400         err = qlcnic_issue_cmd(adapter, &cmd);
2401         if (err) {
2402                 dev_err(&adapter->pdev->dev,
2403                         "Failed to configure interrupts 0x%x\n", err);
2404                 goto out;
2405         }
2406
2407         max_ints = cmd.rsp.arg[1];
2408         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2409                 val = cmd.rsp.arg[index];
2410                 if (LSB(val)) {
2411                         dev_info(&adapter->pdev->dev,
2412                                  "Can't configure interrupt %d\n",
2413                                  adapter->ahw->intr_tbl[i].id);
2414                         continue;
2415                 }
2416                 if (op_type) {
2417                         adapter->ahw->intr_tbl[i].id = MSW(val);
2418                         adapter->ahw->intr_tbl[i].enabled = 1;
2419                         temp = cmd.rsp.arg[index + 1];
2420                         adapter->ahw->intr_tbl[i].src = temp;
2421                 } else {
2422                         adapter->ahw->intr_tbl[i].id = i;
2423                         adapter->ahw->intr_tbl[i].enabled = 0;
2424                         adapter->ahw->intr_tbl[i].src = 0;
2425                 }
2426         }
2427 out:
2428         qlcnic_free_mbx_args(&cmd);
2429         return err;
2430 }
2431
2432 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2433 {
2434         int id, timeout = 0;
2435         u32 status = 0;
2436
2437         while (status == 0) {
2438                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2439                 if (status)
2440                         break;
2441
2442                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2443                         id = QLC_SHARED_REG_RD32(adapter,
2444                                                  QLCNIC_FLASH_LOCK_OWNER);
2445                         dev_err(&adapter->pdev->dev,
2446                                 "%s: failed, lock held by %d\n", __func__, id);
2447                         return -EIO;
2448                 }
2449                 usleep_range(1000, 2000);
2450         }
2451
2452         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2453         return 0;
2454 }
2455
2456 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2457 {
2458         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2459         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2460 }
2461
2462 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2463                                       u32 flash_addr, u8 *p_data,
2464                                       int count)
2465 {
2466         u32 word, range, flash_offset, addr = flash_addr, ret;
2467         ulong indirect_add, direct_window;
2468         int i, err = 0;
2469
2470         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2471         if (addr & 0x3) {
2472                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2473                 return -EIO;
2474         }
2475
2476         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2477                                      (addr));
2478
2479         range = flash_offset + (count * sizeof(u32));
2480         /* Check if data is spread across multiple sectors */
2481         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2482
2483                 /* Multi sector read */
2484                 for (i = 0; i < count; i++) {
2485                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2486                         ret = QLCRD32(adapter, indirect_add, &err);
2487                         if (err == -EIO)
2488                                 return err;
2489
2490                         word = ret;
2491                         *(u32 *)p_data  = word;
2492                         p_data = p_data + 4;
2493                         addr = addr + 4;
2494                         flash_offset = flash_offset + 4;
2495
2496                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2497                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2498                                 /* This write is needed once for each sector */
2499                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2500                                                              direct_window,
2501                                                              (addr));
2502                                 flash_offset = 0;
2503                         }
2504                 }
2505         } else {
2506                 /* Single sector read */
2507                 for (i = 0; i < count; i++) {
2508                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2509                         ret = QLCRD32(adapter, indirect_add, &err);
2510                         if (err == -EIO)
2511                                 return err;
2512
2513                         word = ret;
2514                         *(u32 *)p_data  = word;
2515                         p_data = p_data + 4;
2516                         addr = addr + 4;
2517                 }
2518         }
2519
2520         return 0;
2521 }
2522
2523 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2524 {
2525         u32 status;
2526         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2527         int err = 0;
2528
2529         do {
2530                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2531                 if (err == -EIO)
2532                         return err;
2533
2534                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2535                     QLC_83XX_FLASH_STATUS_READY)
2536                         break;
2537
2538                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2539         } while (--retries);
2540
2541         if (!retries)
2542                 return -EIO;
2543
2544         return 0;
2545 }
2546
2547 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2548 {
2549         int ret;
2550         u32 cmd;
2551         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2552         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2553                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2554         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2555                                      adapter->ahw->fdt.write_enable_bits);
2556         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2557                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2558         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2559         if (ret)
2560                 return -EIO;
2561
2562         return 0;
2563 }
2564
2565 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2566 {
2567         int ret;
2568
2569         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2570                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2571                                      adapter->ahw->fdt.write_statusreg_cmd));
2572         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2573                                      adapter->ahw->fdt.write_disable_bits);
2574         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2575                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2576         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2577         if (ret)
2578                 return -EIO;
2579
2580         return 0;
2581 }
2582
2583 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2584 {
2585         int ret, err = 0;
2586         u32 mfg_id;
2587
2588         if (qlcnic_83xx_lock_flash(adapter))
2589                 return -EIO;
2590
2591         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2592                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2593         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2594                                      QLC_83XX_FLASH_READ_CTRL);
2595         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2596         if (ret) {
2597                 qlcnic_83xx_unlock_flash(adapter);
2598                 return -EIO;
2599         }
2600
2601         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2602         if (err == -EIO) {
2603                 qlcnic_83xx_unlock_flash(adapter);
2604                 return err;
2605         }
2606
2607         adapter->flash_mfg_id = (mfg_id & 0xFF);
2608         qlcnic_83xx_unlock_flash(adapter);
2609
2610         return 0;
2611 }
2612
2613 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2614 {
2615         int count, fdt_size, ret = 0;
2616
2617         fdt_size = sizeof(struct qlcnic_fdt);
2618         count = fdt_size / sizeof(u32);
2619
2620         if (qlcnic_83xx_lock_flash(adapter))
2621                 return -EIO;
2622
2623         memset(&adapter->ahw->fdt, 0, fdt_size);
2624         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2625                                                 (u8 *)&adapter->ahw->fdt,
2626                                                 count);
2627
2628         qlcnic_83xx_unlock_flash(adapter);
2629         return ret;
2630 }
2631
2632 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2633                                    u32 sector_start_addr)
2634 {
2635         u32 reversed_addr, addr1, addr2, cmd;
2636         int ret = -EIO;
2637
2638         if (qlcnic_83xx_lock_flash(adapter) != 0)
2639                 return -EIO;
2640
2641         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2642                 ret = qlcnic_83xx_enable_flash_write(adapter);
2643                 if (ret) {
2644                         qlcnic_83xx_unlock_flash(adapter);
2645                         dev_err(&adapter->pdev->dev,
2646                                 "%s failed at %d\n",
2647                                 __func__, __LINE__);
2648                         return ret;
2649                 }
2650         }
2651
2652         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2653         if (ret) {
2654                 qlcnic_83xx_unlock_flash(adapter);
2655                 dev_err(&adapter->pdev->dev,
2656                         "%s: failed at %d\n", __func__, __LINE__);
2657                 return -EIO;
2658         }
2659
2660         addr1 = (sector_start_addr & 0xFF) << 16;
2661         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2662         reversed_addr = addr1 | addr2;
2663
2664         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2665                                      reversed_addr);
2666         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2667         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2668                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2669         else
2670                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2671                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2672         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2673                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2674
2675         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2676         if (ret) {
2677                 qlcnic_83xx_unlock_flash(adapter);
2678                 dev_err(&adapter->pdev->dev,
2679                         "%s: failed at %d\n", __func__, __LINE__);
2680                 return -EIO;
2681         }
2682
2683         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2684                 ret = qlcnic_83xx_disable_flash_write(adapter);
2685                 if (ret) {
2686                         qlcnic_83xx_unlock_flash(adapter);
2687                         dev_err(&adapter->pdev->dev,
2688                                 "%s: failed at %d\n", __func__, __LINE__);
2689                         return ret;
2690                 }
2691         }
2692
2693         qlcnic_83xx_unlock_flash(adapter);
2694
2695         return 0;
2696 }
2697
2698 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2699                               u32 *p_data)
2700 {
2701         int ret = -EIO;
2702         u32 addr1 = 0x00800000 | (addr >> 2);
2703
2704         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2705         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2706         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2707                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2708         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2709         if (ret) {
2710                 dev_err(&adapter->pdev->dev,
2711                         "%s: failed at %d\n", __func__, __LINE__);
2712                 return -EIO;
2713         }
2714
2715         return 0;
2716 }
2717
2718 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2719                                  u32 *p_data, int count)
2720 {
2721         u32 temp;
2722         int ret = -EIO, err = 0;
2723
2724         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2725             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2726                 dev_err(&adapter->pdev->dev,
2727                         "%s: Invalid word count\n", __func__);
2728                 return -EIO;
2729         }
2730
2731         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2732         if (err == -EIO)
2733                 return err;
2734
2735         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2736                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2737         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2738                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2739
2740         /* First DWORD write */
2741         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2742         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2743                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2744         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2745         if (ret) {
2746                 dev_err(&adapter->pdev->dev,
2747                         "%s: failed at %d\n", __func__, __LINE__);
2748                 return -EIO;
2749         }
2750
2751         count--;
2752         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2753                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2754         /* Second to N-1 DWORD writes */
2755         while (count != 1) {
2756                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2757                                              *p_data++);
2758                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2759                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2760                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2761                 if (ret) {
2762                         dev_err(&adapter->pdev->dev,
2763                                 "%s: failed at %d\n", __func__, __LINE__);
2764                         return -EIO;
2765                 }
2766                 count--;
2767         }
2768
2769         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2770                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2771                                      (addr >> 2));
2772         /* Last DWORD write */
2773         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2774         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2775                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2776         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2777         if (ret) {
2778                 dev_err(&adapter->pdev->dev,
2779                         "%s: failed at %d\n", __func__, __LINE__);
2780                 return -EIO;
2781         }
2782
2783         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2784         if (err == -EIO)
2785                 return err;
2786
2787         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2788                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2789                         __func__, __LINE__);
2790                 /* Operation failed, clear error bit */
2791                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2792                 if (err == -EIO)
2793                         return err;
2794
2795                 qlcnic_83xx_wrt_reg_indirect(adapter,
2796                                              QLC_83XX_FLASH_SPI_CONTROL,
2797                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2798         }
2799
2800         return 0;
2801 }
2802
2803 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2804 {
2805         u32 val, id;
2806
2807         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2808
2809         /* Check if recovery need to be performed by the calling function */
2810         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2811                 val = val & ~0x3F;
2812                 val = val | ((adapter->portnum << 2) |
2813                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2814                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2815                 dev_info(&adapter->pdev->dev,
2816                          "%s: lock recovery initiated\n", __func__);
2817                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2818                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2819                 id = ((val >> 2) & 0xF);
2820                 if (id == adapter->portnum) {
2821                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2822                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2823                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2824                         /* Force release the lock */
2825                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2826                         /* Clear recovery bits */
2827                         val = val & ~0x3F;
2828                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2829                         dev_info(&adapter->pdev->dev,
2830                                  "%s: lock recovery completed\n", __func__);
2831                 } else {
2832                         dev_info(&adapter->pdev->dev,
2833                                  "%s: func %d to resume lock recovery process\n",
2834                                  __func__, id);
2835                 }
2836         } else {
2837                 dev_info(&adapter->pdev->dev,
2838                          "%s: lock recovery initiated by other functions\n",
2839                          __func__);
2840         }
2841 }
2842
2843 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2844 {
2845         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2846         int max_attempt = 0;
2847
2848         while (status == 0) {
2849                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2850                 if (status)
2851                         break;
2852
2853                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2854                 i++;
2855
2856                 if (i == 1)
2857                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2858
2859                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2860                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2861                         if (val == temp) {
2862                                 id = val & 0xFF;
2863                                 dev_info(&adapter->pdev->dev,
2864                                          "%s: lock to be recovered from %d\n",
2865                                          __func__, id);
2866                                 qlcnic_83xx_recover_driver_lock(adapter);
2867                                 i = 0;
2868                                 max_attempt++;
2869                         } else {
2870                                 dev_err(&adapter->pdev->dev,
2871                                         "%s: failed to get lock\n", __func__);
2872                                 return -EIO;
2873                         }
2874                 }
2875
2876                 /* Force exit from while loop after few attempts */
2877                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2878                         dev_err(&adapter->pdev->dev,
2879                                 "%s: failed to get lock\n", __func__);
2880                         return -EIO;
2881                 }
2882         }
2883
2884         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2885         lock_alive_counter = val >> 8;
2886         lock_alive_counter++;
2887         val = lock_alive_counter << 8 | adapter->portnum;
2888         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2889
2890         return 0;
2891 }
2892
2893 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2894 {
2895         u32 val, lock_alive_counter, id;
2896
2897         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2898         id = val & 0xFF;
2899         lock_alive_counter = val >> 8;
2900
2901         if (id != adapter->portnum)
2902                 dev_err(&adapter->pdev->dev,
2903                         "%s:Warning func %d is unlocking lock owned by %d\n",
2904                         __func__, adapter->portnum, id);
2905
2906         val = (lock_alive_counter << 8) | 0xFF;
2907         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2908         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2909 }
2910
2911 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2912                                 u32 *data, u32 count)
2913 {
2914         int i, j, ret = 0;
2915         u32 temp;
2916         int err = 0;
2917
2918         /* Check alignment */
2919         if (addr & 0xF)
2920                 return -EIO;
2921
2922         mutex_lock(&adapter->ahw->mem_lock);
2923         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2924
2925         for (i = 0; i < count; i++, addr += 16) {
2926                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2927                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2928                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2929                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2930                         mutex_unlock(&adapter->ahw->mem_lock);
2931                         return -EIO;
2932                 }
2933
2934                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2935                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2936                                              *data++);
2937                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2938                                              *data++);
2939                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2940                                              *data++);
2941                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2942                                              *data++);
2943                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2944                                              QLCNIC_TA_WRITE_ENABLE);
2945                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2946                                              QLCNIC_TA_WRITE_START);
2947
2948                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2949                         temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2950                         if (err == -EIO) {
2951                                 mutex_unlock(&adapter->ahw->mem_lock);
2952                                 return err;
2953                         }
2954
2955                         if ((temp & TA_CTL_BUSY) == 0)
2956                                 break;
2957                 }
2958
2959                 /* Status check failure */
2960                 if (j >= MAX_CTL_CHECK) {
2961                         printk_ratelimited(KERN_WARNING
2962                                            "MS memory write failed\n");
2963                         mutex_unlock(&adapter->ahw->mem_lock);
2964                         return -EIO;
2965                 }
2966         }
2967
2968         mutex_unlock(&adapter->ahw->mem_lock);
2969
2970         return ret;
2971 }
2972
2973 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2974                              u8 *p_data, int count)
2975 {
2976         u32 word, addr = flash_addr, ret;
2977         ulong  indirect_addr;
2978         int i, err = 0;
2979
2980         if (qlcnic_83xx_lock_flash(adapter) != 0)
2981                 return -EIO;
2982
2983         if (addr & 0x3) {
2984                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2985                 qlcnic_83xx_unlock_flash(adapter);
2986                 return -EIO;
2987         }
2988
2989         for (i = 0; i < count; i++) {
2990                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2991                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
2992                                                  (addr))) {
2993                         qlcnic_83xx_unlock_flash(adapter);
2994                         return -EIO;
2995                 }
2996
2997                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2998                 ret = QLCRD32(adapter, indirect_addr, &err);
2999                 if (err == -EIO)
3000                         return err;
3001
3002                 word = ret;
3003                 *(u32 *)p_data  = word;
3004                 p_data = p_data + 4;
3005                 addr = addr + 4;
3006         }
3007
3008         qlcnic_83xx_unlock_flash(adapter);
3009
3010         return 0;
3011 }
3012
3013 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3014 {
3015         u8 pci_func;
3016         int err;
3017         u32 config = 0, state;
3018         struct qlcnic_cmd_args cmd;
3019         struct qlcnic_hardware_context *ahw = adapter->ahw;
3020
3021         if (qlcnic_sriov_vf_check(adapter))
3022                 pci_func = adapter->portnum;
3023         else
3024                 pci_func = ahw->pci_func;
3025
3026         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3027         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3028                 dev_info(&adapter->pdev->dev, "link state down\n");
3029                 return config;
3030         }
3031
3032         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3033         if (err)
3034                 return err;
3035
3036         err = qlcnic_issue_cmd(adapter, &cmd);
3037         if (err) {
3038                 dev_info(&adapter->pdev->dev,
3039                          "Get Link Status Command failed: 0x%x\n", err);
3040                 goto out;
3041         } else {
3042                 config = cmd.rsp.arg[1];
3043                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3044                 case QLC_83XX_10M_LINK:
3045                         ahw->link_speed = SPEED_10;
3046                         break;
3047                 case QLC_83XX_100M_LINK:
3048                         ahw->link_speed = SPEED_100;
3049                         break;
3050                 case QLC_83XX_1G_LINK:
3051                         ahw->link_speed = SPEED_1000;
3052                         break;
3053                 case QLC_83XX_10G_LINK:
3054                         ahw->link_speed = SPEED_10000;
3055                         break;
3056                 default:
3057                         ahw->link_speed = 0;
3058                         break;
3059                 }
3060                 config = cmd.rsp.arg[3];
3061                 if (QLC_83XX_SFP_PRESENT(config)) {
3062                         switch (ahw->module_type) {
3063                         case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3064                         case LINKEVENT_MODULE_OPTICAL_SRLR:
3065                         case LINKEVENT_MODULE_OPTICAL_LRM:
3066                         case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3067                                 ahw->supported_type = PORT_FIBRE;
3068                                 break;
3069                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3070                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3071                         case LINKEVENT_MODULE_TWINAX:
3072                                 ahw->supported_type = PORT_TP;
3073                                 break;
3074                         default:
3075                                 ahw->supported_type = PORT_OTHER;
3076                         }
3077                 }
3078                 if (config & 1)
3079                         err = 1;
3080         }
3081 out:
3082         qlcnic_free_mbx_args(&cmd);
3083         return config;
3084 }
3085
3086 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3087                              struct ethtool_cmd *ecmd)
3088 {
3089         u32 config = 0;
3090         int status = 0;
3091         struct qlcnic_hardware_context *ahw = adapter->ahw;
3092
3093         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3094                 /* Get port configuration info */
3095                 status = qlcnic_83xx_get_port_info(adapter);
3096                 /* Get Link Status related info */
3097                 config = qlcnic_83xx_test_link(adapter);
3098                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3099         }
3100
3101         /* hard code until there is a way to get it from flash */
3102         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3103
3104         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3105                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3106                 ecmd->duplex = ahw->link_duplex;
3107                 ecmd->autoneg = ahw->link_autoneg;
3108         } else {
3109                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3110                 ecmd->duplex = DUPLEX_UNKNOWN;
3111                 ecmd->autoneg = AUTONEG_DISABLE;
3112         }
3113
3114         if (ahw->port_type == QLCNIC_XGBE) {
3115                 ecmd->supported = SUPPORTED_10000baseT_Full;
3116                 ecmd->advertising = ADVERTISED_10000baseT_Full;
3117         } else {
3118                 ecmd->supported = (SUPPORTED_10baseT_Half |
3119                                    SUPPORTED_10baseT_Full |
3120                                    SUPPORTED_100baseT_Half |
3121                                    SUPPORTED_100baseT_Full |
3122                                    SUPPORTED_1000baseT_Half |
3123                                    SUPPORTED_1000baseT_Full);
3124                 ecmd->advertising = (ADVERTISED_100baseT_Half |
3125                                      ADVERTISED_100baseT_Full |
3126                                      ADVERTISED_1000baseT_Half |
3127                                      ADVERTISED_1000baseT_Full);
3128         }
3129
3130         switch (ahw->supported_type) {
3131         case PORT_FIBRE:
3132                 ecmd->supported |= SUPPORTED_FIBRE;
3133                 ecmd->advertising |= ADVERTISED_FIBRE;
3134                 ecmd->port = PORT_FIBRE;
3135                 ecmd->transceiver = XCVR_EXTERNAL;
3136                 break;
3137         case PORT_TP:
3138                 ecmd->supported |= SUPPORTED_TP;
3139                 ecmd->advertising |= ADVERTISED_TP;
3140                 ecmd->port = PORT_TP;
3141                 ecmd->transceiver = XCVR_INTERNAL;
3142                 break;
3143         default:
3144                 ecmd->supported |= SUPPORTED_FIBRE;
3145                 ecmd->advertising |= ADVERTISED_FIBRE;
3146                 ecmd->port = PORT_OTHER;
3147                 ecmd->transceiver = XCVR_EXTERNAL;
3148                 break;
3149         }
3150         ecmd->phy_address = ahw->physical_port;
3151         return status;
3152 }
3153
3154 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3155                              struct ethtool_cmd *ecmd)
3156 {
3157         int status = 0;
3158         u32 config = adapter->ahw->port_config;
3159
3160         if (ecmd->autoneg)
3161                 adapter->ahw->port_config |= BIT_15;
3162
3163         switch (ethtool_cmd_speed(ecmd)) {
3164         case SPEED_10:
3165                 adapter->ahw->port_config |= BIT_8;
3166                 break;
3167         case SPEED_100:
3168                 adapter->ahw->port_config |= BIT_9;
3169                 break;
3170         case SPEED_1000:
3171                 adapter->ahw->port_config |= BIT_10;
3172                 break;
3173         case SPEED_10000:
3174                 adapter->ahw->port_config |= BIT_11;
3175                 break;
3176         default:
3177                 return -EINVAL;
3178         }
3179
3180         status = qlcnic_83xx_set_port_config(adapter);
3181         if (status) {
3182                 dev_info(&adapter->pdev->dev,
3183                          "Failed to Set Link Speed and autoneg.\n");
3184                 adapter->ahw->port_config = config;
3185         }
3186         return status;
3187 }
3188
3189 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3190                                           u64 *data, int index)
3191 {
3192         u32 low, hi;
3193         u64 val;
3194
3195         low = cmd->rsp.arg[index];
3196         hi = cmd->rsp.arg[index + 1];
3197         val = (((u64) low) | (((u64) hi) << 32));
3198         *data++ = val;
3199         return data;
3200 }
3201
3202 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3203                                    struct qlcnic_cmd_args *cmd, u64 *data,
3204                                    int type, int *ret)
3205 {
3206         int err, k, total_regs;
3207
3208         *ret = 0;
3209         err = qlcnic_issue_cmd(adapter, cmd);
3210         if (err != QLCNIC_RCODE_SUCCESS) {
3211                 dev_info(&adapter->pdev->dev,
3212                          "Error in get statistics mailbox command\n");
3213                 *ret = -EIO;
3214                 return data;
3215         }
3216         total_regs = cmd->rsp.num;
3217         switch (type) {
3218         case QLC_83XX_STAT_MAC:
3219                 /* fill in MAC tx counters */
3220                 for (k = 2; k < 28; k += 2)
3221                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3222                 /* skip 24 bytes of reserved area */
3223                 /* fill in MAC rx counters */
3224                 for (k += 6; k < 60; k += 2)
3225                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3226                 /* skip 24 bytes of reserved area */
3227                 /* fill in MAC rx frame stats */
3228                 for (k += 6; k < 80; k += 2)
3229                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3230                 /* fill in eSwitch stats */
3231                 for (; k < total_regs; k += 2)
3232                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3233                 break;
3234         case QLC_83XX_STAT_RX:
3235                 for (k = 2; k < 8; k += 2)
3236                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3237                 /* skip 8 bytes of reserved data */
3238                 for (k += 2; k < 24; k += 2)
3239                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3240                 /* skip 8 bytes containing RE1FBQ error data */
3241                 for (k += 2; k < total_regs; k += 2)
3242                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3243                 break;
3244         case QLC_83XX_STAT_TX:
3245                 for (k = 2; k < 10; k += 2)
3246                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3247                 /* skip 8 bytes of reserved data */
3248                 for (k += 2; k < total_regs; k += 2)
3249                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3250                 break;
3251         default:
3252                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3253                 *ret = -EIO;
3254         }
3255         return data;
3256 }
3257
3258 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3259 {
3260         struct qlcnic_cmd_args cmd;
3261         struct net_device *netdev = adapter->netdev;
3262         int ret = 0;
3263
3264         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3265         if (ret)
3266                 return;
3267         /* Get Tx stats */
3268         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3269         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3270         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3271                                       QLC_83XX_STAT_TX, &ret);
3272         if (ret) {
3273                 netdev_err(netdev, "Error getting Tx stats\n");
3274                 goto out;
3275         }
3276         /* Get MAC stats */
3277         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3278         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3279         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3280         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3281                                       QLC_83XX_STAT_MAC, &ret);
3282         if (ret) {
3283                 netdev_err(netdev, "Error getting MAC stats\n");
3284                 goto out;
3285         }
3286         /* Get Rx stats */
3287         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3288         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3289         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3290         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3291                                       QLC_83XX_STAT_RX, &ret);
3292         if (ret)
3293                 netdev_err(netdev, "Error getting Rx stats\n");
3294 out:
3295         qlcnic_free_mbx_args(&cmd);
3296 }
3297
3298 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3299 {
3300         u32 major, minor, sub;
3301
3302         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3303         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3304         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3305
3306         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3307                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3308                          __func__);
3309                 return 1;
3310         }
3311         return 0;
3312 }
3313
3314 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3315 {
3316         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3317                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3318                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3319                 sizeof(*adapter->ahw->reg_tbl));
3320 }
3321
3322 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3323 {
3324         int i, j = 0;
3325
3326         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3327              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3328                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3329
3330         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3331                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3332         return i;
3333 }
3334
3335 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3336 {
3337         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3338         struct qlcnic_hardware_context *ahw = adapter->ahw;
3339         struct qlcnic_cmd_args cmd;
3340         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3341         u8 drv_tx_rings = adapter->drv_tx_rings;
3342         u32 data;
3343         u16 intrpt_id, id;
3344         int ret;
3345
3346         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3347                 netdev_info(netdev, "Device is resetting\n");
3348                 return -EBUSY;
3349         }
3350
3351         if (qlcnic_get_diag_lock(adapter)) {
3352                 netdev_info(netdev, "Device in diagnostics mode\n");
3353                 return -EBUSY;
3354         }
3355
3356         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3357                                          drv_sds_rings);
3358         if (ret)
3359                 goto fail_diag_irq;
3360
3361         ahw->diag_cnt = 0;
3362         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3363         if (ret)
3364                 goto fail_diag_irq;
3365
3366         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3367                 intrpt_id = ahw->intr_tbl[0].id;
3368         else
3369                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3370
3371         cmd.req.arg[1] = 1;
3372         cmd.req.arg[2] = intrpt_id;
3373         cmd.req.arg[3] = BIT_0;
3374
3375         ret = qlcnic_issue_cmd(adapter, &cmd);
3376         data = cmd.rsp.arg[2];
3377         id = LSW(data);
3378         val = LSB(MSW(data));
3379         if (id != intrpt_id)
3380                 dev_info(&adapter->pdev->dev,
3381                          "Interrupt generated: 0x%x, requested:0x%x\n",
3382                          id, intrpt_id);
3383         if (val)
3384                 dev_err(&adapter->pdev->dev,
3385                          "Interrupt test error: 0x%x\n", val);
3386         if (ret)
3387                 goto done;
3388
3389         msleep(20);
3390         ret = !ahw->diag_cnt;
3391
3392 done:
3393         qlcnic_free_mbx_args(&cmd);
3394         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3395
3396 fail_diag_irq:
3397         adapter->drv_sds_rings = drv_sds_rings;
3398         adapter->drv_tx_rings = drv_tx_rings;
3399         qlcnic_release_diag_lock(adapter);
3400         return ret;
3401 }
3402
3403 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3404                                 struct ethtool_pauseparam *pause)
3405 {
3406         struct qlcnic_hardware_context *ahw = adapter->ahw;
3407         int status = 0;
3408         u32 config;
3409
3410         status = qlcnic_83xx_get_port_config(adapter);
3411         if (status) {
3412                 dev_err(&adapter->pdev->dev,
3413                         "%s: Get Pause Config failed\n", __func__);
3414                 return;
3415         }
3416         config = ahw->port_config;
3417         if (config & QLC_83XX_CFG_STD_PAUSE) {
3418                 switch (MSW(config)) {
3419                 case QLC_83XX_TX_PAUSE:
3420                         pause->tx_pause = 1;
3421                         break;
3422                 case QLC_83XX_RX_PAUSE:
3423                         pause->rx_pause = 1;
3424                         break;
3425                 case QLC_83XX_TX_RX_PAUSE:
3426                 default:
3427                         /* Backward compatibility for existing
3428                          * flash definitions
3429                          */
3430                         pause->tx_pause = 1;
3431                         pause->rx_pause = 1;
3432                 }
3433         }
3434
3435         if (QLC_83XX_AUTONEG(config))
3436                 pause->autoneg = 1;
3437 }
3438
3439 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3440                                struct ethtool_pauseparam *pause)
3441 {
3442         struct qlcnic_hardware_context *ahw = adapter->ahw;
3443         int status = 0;
3444         u32 config;
3445
3446         status = qlcnic_83xx_get_port_config(adapter);
3447         if (status) {
3448                 dev_err(&adapter->pdev->dev,
3449                         "%s: Get Pause Config failed.\n", __func__);
3450                 return status;
3451         }
3452         config = ahw->port_config;
3453
3454         if (ahw->port_type == QLCNIC_GBE) {
3455                 if (pause->autoneg)
3456                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3457                 if (!pause->autoneg)
3458                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3459         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3460                 return -EOPNOTSUPP;
3461         }
3462
3463         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3464                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3465
3466         if (pause->rx_pause && pause->tx_pause) {
3467                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3468         } else if (pause->rx_pause && !pause->tx_pause) {
3469                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3470                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3471         } else if (pause->tx_pause && !pause->rx_pause) {
3472                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3473                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3474         } else if (!pause->rx_pause && !pause->tx_pause) {
3475                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3476                                       QLC_83XX_CFG_STD_PAUSE);
3477         }
3478         status = qlcnic_83xx_set_port_config(adapter);
3479         if (status) {
3480                 dev_err(&adapter->pdev->dev,
3481                         "%s: Set Pause Config failed.\n", __func__);
3482                 ahw->port_config = config;
3483         }
3484         return status;
3485 }
3486
3487 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3488 {
3489         int ret, err = 0;
3490         u32 temp;
3491
3492         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3493                                      QLC_83XX_FLASH_OEM_READ_SIG);
3494         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3495                                      QLC_83XX_FLASH_READ_CTRL);
3496         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3497         if (ret)
3498                 return -EIO;
3499
3500         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3501         if (err == -EIO)
3502                 return err;
3503
3504         return temp & 0xFF;
3505 }
3506
3507 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3508 {
3509         int status;
3510
3511         status = qlcnic_83xx_read_flash_status_reg(adapter);
3512         if (status == -EIO) {
3513                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3514                          __func__);
3515                 return 1;
3516         }
3517         return 0;
3518 }
3519
3520 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3521 {
3522         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3523         struct net_device *netdev = adapter->netdev;
3524         int retval;
3525
3526         netif_device_detach(netdev);
3527         qlcnic_cancel_idc_work(adapter);
3528
3529         if (netif_running(netdev))
3530                 qlcnic_down(adapter, netdev);
3531
3532         qlcnic_83xx_disable_mbx_intr(adapter);
3533         cancel_delayed_work_sync(&adapter->idc_aen_work);
3534
3535         retval = pci_save_state(pdev);
3536         if (retval)
3537                 return retval;
3538
3539         return 0;
3540 }
3541
3542 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3543 {
3544         struct qlcnic_hardware_context *ahw = adapter->ahw;
3545         struct qlc_83xx_idc *idc = &ahw->idc;
3546         int err = 0;
3547
3548         err = qlcnic_83xx_idc_init(adapter);
3549         if (err)
3550                 return err;
3551
3552         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3553                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3554                         qlcnic_83xx_set_vnic_opmode(adapter);
3555                 } else {
3556                         err = qlcnic_83xx_check_vnic_state(adapter);
3557                         if (err)
3558                                 return err;
3559                 }
3560         }
3561
3562         err = qlcnic_83xx_idc_reattach_driver(adapter);
3563         if (err)
3564                 return err;
3565
3566         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3567                              idc->delay);
3568         return err;
3569 }
3570
3571 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3572 {
3573         reinit_completion(&mbx->completion);
3574         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3575 }
3576
3577 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3578 {
3579         if (!mbx)
3580                 return;
3581
3582         destroy_workqueue(mbx->work_q);
3583         kfree(mbx);
3584 }
3585
3586 static inline void
3587 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3588                                   struct qlcnic_cmd_args *cmd)
3589 {
3590         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3591
3592         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3593                 qlcnic_free_mbx_args(cmd);
3594                 kfree(cmd);
3595                 return;
3596         }
3597         complete(&cmd->completion);
3598 }
3599
3600 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3601 {
3602         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3603         struct list_head *head = &mbx->cmd_q;
3604         struct qlcnic_cmd_args *cmd = NULL;
3605
3606         spin_lock(&mbx->queue_lock);
3607
3608         while (!list_empty(head)) {
3609                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3610                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3611                          __func__, cmd->cmd_op);
3612                 list_del(&cmd->list);
3613                 mbx->num_cmds--;
3614                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3615         }
3616
3617         spin_unlock(&mbx->queue_lock);
3618 }
3619
3620 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3621 {
3622         struct qlcnic_hardware_context *ahw = adapter->ahw;
3623         struct qlcnic_mailbox *mbx = ahw->mailbox;
3624         u32 host_mbx_ctrl;
3625
3626         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3627                 return -EBUSY;
3628
3629         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3630         if (host_mbx_ctrl) {
3631                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3632                 ahw->idc.collect_dump = 1;
3633                 return -EIO;
3634         }
3635
3636         return 0;
3637 }
3638
3639 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3640                                               u8 issue_cmd)
3641 {
3642         if (issue_cmd)
3643                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3644         else
3645                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3646 }
3647
3648 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3649                                         struct qlcnic_cmd_args *cmd)
3650 {
3651         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3652
3653         spin_lock(&mbx->queue_lock);
3654
3655         list_del(&cmd->list);
3656         mbx->num_cmds--;
3657
3658         spin_unlock(&mbx->queue_lock);
3659
3660         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3661 }
3662
3663 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3664                                        struct qlcnic_cmd_args *cmd)
3665 {
3666         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3667         struct qlcnic_hardware_context *ahw = adapter->ahw;
3668         int i, j;
3669
3670         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3671                 mbx_cmd = cmd->req.arg[0];
3672                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3673                 for (i = 1; i < cmd->req.num; i++)
3674                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3675         } else {
3676                 fw_hal_version = ahw->fw_hal_version;
3677                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3678                 total_size = cmd->pay_size + hdr_size;
3679                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3680                 mbx_cmd = tmp | fw_hal_version << 29;
3681                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3682
3683                 /* Back channel specific operations bits */
3684                 mbx_cmd = 0x1 | 1 << 4;
3685
3686                 if (qlcnic_sriov_pf_check(adapter))
3687                         mbx_cmd |= cmd->func_num << 5;
3688
3689                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3690
3691                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3692                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3693                 for (j = 0; j < cmd->pay_size; j++, i++)
3694                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3695         }
3696 }
3697
3698 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3699 {
3700         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3701
3702         if (!mbx)
3703                 return;
3704
3705         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3706         complete(&mbx->completion);
3707         cancel_work_sync(&mbx->work);
3708         flush_workqueue(mbx->work_q);
3709         qlcnic_83xx_flush_mbx_queue(adapter);
3710 }
3711
3712 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3713                                        struct qlcnic_cmd_args *cmd,
3714                                        unsigned long *timeout)
3715 {
3716         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3717
3718         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3719                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3720                 init_completion(&cmd->completion);
3721                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3722
3723                 spin_lock(&mbx->queue_lock);
3724
3725                 list_add_tail(&cmd->list, &mbx->cmd_q);
3726                 mbx->num_cmds++;
3727                 cmd->total_cmds = mbx->num_cmds;
3728                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3729                 queue_work(mbx->work_q, &mbx->work);
3730
3731                 spin_unlock(&mbx->queue_lock);
3732
3733                 return 0;
3734         }
3735
3736         return -EBUSY;
3737 }
3738
3739 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3740                                        struct qlcnic_cmd_args *cmd)
3741 {
3742         u8 mac_cmd_rcode;
3743         u32 fw_data;
3744
3745         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3746                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3747                 mac_cmd_rcode = (u8)fw_data;
3748                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3749                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3750                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3751                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3752                         return QLCNIC_RCODE_SUCCESS;
3753                 }
3754         }
3755
3756         return -EINVAL;
3757 }
3758
3759 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3760                                        struct qlcnic_cmd_args *cmd)
3761 {
3762         struct qlcnic_hardware_context *ahw = adapter->ahw;
3763         struct device *dev = &adapter->pdev->dev;
3764         u8 mbx_err_code;
3765         u32 fw_data;
3766
3767         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3768         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3769         qlcnic_83xx_get_mbx_data(adapter, cmd);
3770
3771         switch (mbx_err_code) {
3772         case QLCNIC_MBX_RSP_OK:
3773         case QLCNIC_MBX_PORT_RSP_OK:
3774                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3775                 break;
3776         default:
3777                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3778                         break;
3779
3780                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3781                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3782                         ahw->op_mode, mbx_err_code);
3783                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3784                 qlcnic_dump_mbx(adapter, cmd);
3785         }
3786
3787         return;
3788 }
3789
3790 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
3791 {
3792         struct qlcnic_hardware_context *ahw = adapter->ahw;
3793         u32 offset;
3794
3795         offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
3796         dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
3797                  readl(ahw->pci_base0 + offset),
3798                  QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
3799                  QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
3800                  QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
3801 }
3802
3803 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3804 {
3805         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3806                                                   work);
3807         struct qlcnic_adapter *adapter = mbx->adapter;
3808         struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3809         struct device *dev = &adapter->pdev->dev;
3810         atomic_t *rsp_status = &mbx->rsp_status;
3811         struct list_head *head = &mbx->cmd_q;
3812         struct qlcnic_hardware_context *ahw;
3813         struct qlcnic_cmd_args *cmd = NULL;
3814
3815         ahw = adapter->ahw;
3816
3817         while (true) {
3818                 if (qlcnic_83xx_check_mbx_status(adapter)) {
3819                         qlcnic_83xx_flush_mbx_queue(adapter);
3820                         return;
3821                 }
3822
3823                 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3824
3825                 spin_lock(&mbx->queue_lock);
3826
3827                 if (list_empty(head)) {
3828                         spin_unlock(&mbx->queue_lock);
3829                         return;
3830                 }
3831                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3832
3833                 spin_unlock(&mbx->queue_lock);
3834
3835                 mbx_ops->encode_cmd(adapter, cmd);
3836                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3837
3838                 if (wait_for_completion_timeout(&mbx->completion,
3839                                                 QLC_83XX_MBX_TIMEOUT)) {
3840                         mbx_ops->decode_resp(adapter, cmd);
3841                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3842                 } else {
3843                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3844                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3845                                 ahw->op_mode);
3846                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3847                         qlcnic_dump_mailbox_registers(adapter);
3848                         qlcnic_83xx_get_mbx_data(adapter, cmd);
3849                         qlcnic_dump_mbx(adapter, cmd);
3850                         qlcnic_83xx_idc_request_reset(adapter,
3851                                                       QLCNIC_FORCE_FW_DUMP_KEY);
3852                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3853                 }
3854                 mbx_ops->dequeue_cmd(adapter, cmd);
3855         }
3856 }
3857
3858 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3859         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
3860         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
3861         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
3862         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
3863         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
3864 };
3865
3866 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3867 {
3868         struct qlcnic_hardware_context *ahw = adapter->ahw;
3869         struct qlcnic_mailbox *mbx;
3870
3871         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3872         if (!ahw->mailbox)
3873                 return -ENOMEM;
3874
3875         mbx = ahw->mailbox;
3876         mbx->ops = &qlcnic_83xx_mbx_ops;
3877         mbx->adapter = adapter;
3878
3879         spin_lock_init(&mbx->queue_lock);
3880         spin_lock_init(&mbx->aen_lock);
3881         INIT_LIST_HEAD(&mbx->cmd_q);
3882         init_completion(&mbx->completion);
3883
3884         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3885         if (mbx->work_q == NULL) {
3886                 kfree(mbx);
3887                 return -ENOMEM;
3888         }
3889
3890         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3891         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3892         return 0;
3893 }
3894
3895 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3896                                                       pci_channel_state_t state)
3897 {
3898         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3899
3900         if (state == pci_channel_io_perm_failure)
3901                 return PCI_ERS_RESULT_DISCONNECT;
3902
3903         if (state == pci_channel_io_normal)
3904                 return PCI_ERS_RESULT_RECOVERED;
3905
3906         set_bit(__QLCNIC_AER, &adapter->state);
3907         set_bit(__QLCNIC_RESETTING, &adapter->state);
3908
3909         qlcnic_83xx_aer_stop_poll_work(adapter);
3910
3911         pci_save_state(pdev);
3912         pci_disable_device(pdev);
3913
3914         return PCI_ERS_RESULT_NEED_RESET;
3915 }
3916
3917 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3918 {
3919         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3920         int err = 0;
3921
3922         pdev->error_state = pci_channel_io_normal;
3923         err = pci_enable_device(pdev);
3924         if (err)
3925                 goto disconnect;
3926
3927         pci_set_power_state(pdev, PCI_D0);
3928         pci_set_master(pdev);
3929         pci_restore_state(pdev);
3930
3931         err = qlcnic_83xx_aer_reset(adapter);
3932         if (err == 0)
3933                 return PCI_ERS_RESULT_RECOVERED;
3934 disconnect:
3935         clear_bit(__QLCNIC_AER, &adapter->state);
3936         clear_bit(__QLCNIC_RESETTING, &adapter->state);
3937         return PCI_ERS_RESULT_DISCONNECT;
3938 }
3939
3940 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3941 {
3942         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3943
3944         pci_cleanup_aer_uncorrect_error_status(pdev);
3945         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3946                 qlcnic_83xx_aer_start_poll_work(adapter);
3947 }