2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #ifndef __QLCNIC_83XX_HW_H
9 #define __QLCNIC_83XX_HW_H
11 #include <linux/types.h>
12 #include <linux/etherdevice.h>
13 #include "qlcnic_hw.h"
15 /* Directly mapped registers */
16 #define QLC_83XX_CRB_WIN_BASE 0x3800
17 #define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4))
18 #define QLC_83XX_SEM_LOCK_BASE 0x3840
19 #define QLC_83XX_SEM_UNLOCK_BASE 0x3844
20 #define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8))
21 #define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
22 #define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
23 #define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
24 #define QLC_83XX_LINK_SPEED_FACTOR 10
25 #define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
26 #define QLC_83XX_INTX_PTR 0x38C0
27 #define QLC_83XX_INTX_TRGR 0x38C4
28 #define QLC_83XX_INTX_MASK 0x38C8
30 #define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100
31 #define QLC_83XX_DRV_LOCK_WAIT_DELAY 20
32 #define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1
33 #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2
34 #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3
35 #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200
36 #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3
38 #define QLC_83XX_NO_NIC_RESOURCE 0x5
39 #define QLC_83XX_MAC_PRESENT 0xC
40 #define QLC_83XX_MAC_ABSENT 0xD
43 #define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024)
45 /* PEG status definitions */
46 #define QLC_83XX_CMDPEG_COMPLETE 0xff01
47 #define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30)
48 #define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31)
49 #define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF)
50 #define QLC_83XX_LEGACY_INTX_MAX_RETRY 100
51 #define QLC_83XX_LEGACY_INTX_DELAY 4
52 #define QLC_83XX_REG_DESC 1
53 #define QLC_83XX_LRO_DESC 2
54 #define QLC_83XX_CTRL_DESC 3
55 #define QLC_83XX_FW_CAPABILITY_TSO BIT_6
56 #define QLC_83XX_FW_CAP_LRO_MSS BIT_17
57 #define QLC_83XX_HOST_RDS_MODE_UNIQUE 0
58 #define QLC_83XX_HOST_SDS_MBX_IDX 8
60 #define QLCNIC_HOST_RDS_MBX_IDX 88
61 #define QLCNIC_MAX_RING_SETS 8
63 /* Pause control registers */
64 #define QLC_83XX_SRE_SHIM_REG 0x0D200284
65 #define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4
66 #define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4
67 #define QLC_83XX_PORT0_TC_MC_REG 0x0B200388
68 #define QLC_83XX_PORT1_TC_MC_REG 0x0B201388
69 #define QLC_83XX_PORT0_TC_STATS 0x0B20039C
70 #define QLC_83XX_PORT1_TC_STATS 0x0B20139C
71 #define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704
72 #define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704
74 /* Peg PC status registers */
75 #define QLC_83XX_CRB_PEG_NET_0 0x3400003c
76 #define QLC_83XX_CRB_PEG_NET_1 0x3410003c
77 #define QLC_83XX_CRB_PEG_NET_2 0x3420003c
78 #define QLC_83XX_CRB_PEG_NET_3 0x3430003c
79 #define QLC_83XX_CRB_PEG_NET_4 0x34b0003c
81 /* Firmware image definitions */
82 #define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000
83 #define QLC_83XX_FW_FILE_NAME "83xx_fw.bin"
84 #define QLC_83XX_BOOT_FROM_FLASH 0
85 #define QLC_83XX_BOOT_FROM_FILE 0x12345678
87 #define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16
89 struct qlcnic_intrpt_config {
96 struct qlcnic_macvlan_mbx {
97 #if defined(__LITTLE_ENDIAN)
105 #elif defined(__BIG_ENDIAN)
116 struct qlc_83xx_fw_info {
117 const struct firmware *fw;
118 u16 major_fw_version;
125 struct qlc_83xx_reset {
126 struct qlc_83xx_reset_hdr *hdr;
130 u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
139 #define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1
140 #define QLC_83XX_IDC_GRACEFULL_RESET 0x2
141 #define QLC_83XX_IDC_TIMESTAMP 0
142 #define QLC_83XX_IDC_DURATION 1
143 #define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30
144 #define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10
145 #define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10
146 #define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20
147 #define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ)
148 #define QLC_83XX_IDC_FW_FAIL_THRESH 2
149 #define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8
150 #define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16
151 #define QLC_83XX_IDC_MAJOR_VERSION 1
152 #define QLC_83XX_IDC_MINOR_VERSION 0
153 #define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020
155 struct qlcnic_adapter;
156 struct qlc_83xx_idc {
157 int (*state_entry) (struct qlcnic_adapter *);
160 unsigned long status;
171 #define QLCNIC_MBX_RSP(reg) LSW(reg)
172 #define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF)
173 #define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F)
174 #define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4))
175 #define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4))
177 /* Mailbox process AEN count */
178 #define QLC_83XX_IDC_COMP_AEN 3
179 #define QLC_83XX_MBX_AEN_CNT 5
180 #define QLC_83XX_MODULE_LOADED 1
181 #define QLC_83XX_MBX_READY 2
182 #define QLC_83XX_MBX_AEN_ACK 3
183 #define QLC_83XX_SFP_PRESENT(data) ((data) & 3)
184 #define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3)
185 #define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F)
186 #define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16))
187 #define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10)
188 #define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11)
189 #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
190 #define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7)
191 #define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3)
192 #define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7)
193 #define QLC_83XX_LINK_FEC(data) ((data) & BIT_12)
194 #define QLC_83XX_LINK_EEE(data) ((data) & BIT_13)
195 #define QLC_83XX_DCBX(data) (((data) >> 28) & 7)
196 #define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
197 #define QLC_83XX_CFG_STD_PAUSE (1 << 5)
198 #define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20)
199 #define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20)
200 #define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20)
201 #define QLC_83XX_ENABLE_AUTONEG (1 << 15)
202 #define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1)
203 #define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1)
204 #define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1)
206 /* LED configuration settings */
207 #define QLC_83XX_ENABLE_BEACON 0xe
208 #define QLC_83XX_LED_RATE 0xff
209 #define QLC_83XX_LED_ACT (1 << 10)
210 #define QLC_83XX_LED_MOD (0 << 13)
211 #define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
214 #define QLC_83XX_10M_LINK 1
215 #define QLC_83XX_100M_LINK 2
216 #define QLC_83XX_1G_LINK 3
217 #define QLC_83XX_10G_LINK 4
218 #define QLC_83XX_STAT_TX 3
219 #define QLC_83XX_STAT_RX 2
220 #define QLC_83XX_STAT_MAC 1
221 #define QLC_83XX_TX_STAT_REGS 14
222 #define QLC_83XX_RX_STAT_REGS 40
223 #define QLC_83XX_MAC_STAT_REGS 80
225 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
226 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
227 #define QLC_83XX_DEFAULT_OPMODE 0x55555555
228 #define QLC_83XX_PRIVLEGED_FUNC 0x1
229 #define QLC_83XX_VIRTUAL_FUNC 0x2
231 #define QLC_83XX_LB_MAX_FILTERS 2048
232 #define QLC_83XX_LB_BUCKET_SIZE 256
233 #define QLC_83XX_MINIMUM_VECTOR 3
235 #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000)
236 #define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20)
237 #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
238 #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
239 #define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400)
240 #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000)
241 #define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000)
242 #define QLC_83XX_VIRTUAL_NIC_MODE 0xFF
243 #define QLC_83XX_DEFAULT_MODE 0x0
244 #define QLCNIC_BRDTYPE_83XX_10G 0x0083
246 #define QLC_83XX_FLASH_SPI_STATUS 0x2808E010
247 #define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014
248 #define QLC_83XX_FLASH_STATUS 0x42100004
249 #define QLC_83XX_FLASH_CONTROL 0x42110004
250 #define QLC_83XX_FLASH_ADDR 0x42110008
251 #define QLC_83XX_FLASH_WRDATA 0x4211000C
252 #define QLC_83XX_FLASH_RDDATA 0x42110018
253 #define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030
254 #define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
255 #define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
256 #define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda
257 #define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca
258 #define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
259 #define QLC_83XX_FLASH_STATUS_READY 0x6
260 #define QLC_83XX_FLASH_BULK_WRITE_MIN 2
261 #define QLC_83XX_FLASH_BULK_WRITE_MAX 64
262 #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1
263 #define QLC_83XX_ERASE_MODE 1
264 #define QLC_83XX_WRITE_MODE 2
265 #define QLC_83XX_BULK_WRITE_MODE 3
266 #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100
267 #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300
268 #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F
269 #define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8
270 #define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101
271 #define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005
272 #define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000
273 #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001
274 #define QLC_83XX_FLASH_WRDATA_DEF 0x0
275 #define QLC_83XX_FLASH_READ_CTRL 0x3F
276 #define QLC_83XX_FLASH_SPI_CTRL 0x4
277 #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2
278 #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5
279 #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D
280 #define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
281 #define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F
282 #define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D
283 #define QLC_83xx_FLASH_MAX_WAIT_USEC 100
284 #define QLC_83XX_FLASH_LOCK_TIMEOUT 10000
286 /* Additional registers in 83xx */
287 enum qlc_83xx_ext_regs {
288 QLCNIC_GLOBAL_RESET = 0,
291 QLCNIC_HOST_MBX_CTRL,
293 QLCNIC_BOOTLOADER_ADDR,
294 QLCNIC_BOOTLOADER_SIZE,
295 QLCNIC_FW_IMAGE_ADDR,
296 QLCNIC_MBX_INTR_ENBL,
299 QLC_83XX_IDC_MAJ_VERSION,
300 QLC_83XX_IDC_DEV_STATE,
301 QLC_83XX_IDC_DRV_PRESENCE,
302 QLC_83XX_IDC_DRV_ACK,
304 QLC_83XX_IDC_DRV_AUDIT,
305 QLC_83XX_IDC_MIN_VERSION,
306 QLC_83XX_RECOVER_DRV_LOCK,
323 QLC_83XX_IDC_DEV_PARTITION_INFO_1,
324 QLC_83XX_IDC_DEV_PARTITION_INFO_2,
325 QLC_83XX_DRV_OP_MODE,
329 QLC_83XX_DRV_LOCK_ID,
334 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
335 int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
336 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8);
337 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
338 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
339 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
340 int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
341 void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
342 void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
343 void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
344 void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
345 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong);
346 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
347 void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []);
348 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
349 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
350 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
351 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
352 int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
353 int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *);
354 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, __le16);
355 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
356 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
357 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int);
359 int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
360 void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
361 void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
362 void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
363 int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
364 void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
365 int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
366 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
367 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
368 struct qlcnic_host_tx_ring *, int);
369 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
370 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
371 void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
372 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
373 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8);
374 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *);
375 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
376 struct qlcnic_cmd_args *);
377 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
378 struct qlcnic_adapter *, u32);
379 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
380 void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
381 struct qlcnic_info *);
382 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *);
383 irqreturn_t qlcnic_83xx_handle_aen(int, void *);
384 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
385 void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *);
386 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
387 irqreturn_t qlcnic_83xx_intr(int, void *);
388 irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
389 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *,
390 struct qlcnic_host_sds_ring *);
391 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *,
392 struct qlcnic_host_sds_ring *);
393 void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
394 const struct pci_device_id *);
395 void qlcnic_83xx_process_aen(struct qlcnic_adapter *);
396 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
397 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
398 int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8);
399 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *);
400 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
401 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
402 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
403 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
404 void qlcnic_83xx_idc_aen_work(struct work_struct *);
405 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
407 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
408 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
409 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
410 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
411 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
412 int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
413 int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
414 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
415 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
416 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int);
417 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *,
419 int qlcnic_83xx_init(struct qlcnic_adapter *);
420 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *);
421 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev);
422 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *);
423 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *);
424 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *);
425 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32);
426 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *);
427 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *);
428 int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *);
429 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32);
430 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *);
431 int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int);
432 int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int);
433 int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *);
434 int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *,
435 struct qlcnic_info *, u8);
436 int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *);
438 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *);
439 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data);
440 int qlcnic_83xx_get_settings(struct qlcnic_adapter *);
441 int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
442 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *,
443 struct ethtool_pauseparam *);
444 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *,
445 struct ethtool_pauseparam *);
446 int qlcnic_83xx_test_link(struct qlcnic_adapter *);
447 int qlcnic_83xx_reg_test(struct qlcnic_adapter *);
448 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *);
449 int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *);
450 int qlcnic_83xx_loopback_test(struct net_device *, u8);
451 int qlcnic_83xx_interrupt_test(struct net_device *);
452 int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state);
453 int qlcnic_83xx_flash_test(struct qlcnic_adapter *);