2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #ifndef __QLCNIC_83XX_HW_H
9 #define __QLCNIC_83XX_HW_H
11 #include <linux/types.h>
12 #include <linux/etherdevice.h>
13 #include "qlcnic_hw.h"
15 #define QLCNIC_83XX_BAR0_LENGTH 0x4000
17 /* Directly mapped registers */
18 #define QLC_83XX_CRB_WIN_BASE 0x3800
19 #define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4))
20 #define QLC_83XX_SEM_LOCK_BASE 0x3840
21 #define QLC_83XX_SEM_UNLOCK_BASE 0x3844
22 #define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8))
23 #define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
24 #define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
25 #define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
26 #define QLC_83XX_LINK_SPEED_FACTOR 10
27 #define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
28 #define QLC_83XX_INTX_PTR 0x38C0
29 #define QLC_83XX_INTX_TRGR 0x38C4
30 #define QLC_83XX_INTX_MASK 0x38C8
32 #define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100
33 #define QLC_83XX_DRV_LOCK_WAIT_DELAY 20
34 #define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1
35 #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2
36 #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3
37 #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200
38 #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3
40 #define QLC_83XX_NO_NIC_RESOURCE 0x5
41 #define QLC_83XX_MAC_PRESENT 0xC
42 #define QLC_83XX_MAC_ABSENT 0xD
45 #define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024)
47 /* PEG status definitions */
48 #define QLC_83XX_CMDPEG_COMPLETE 0xff01
49 #define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30)
50 #define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31)
51 #define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF)
52 #define QLC_83XX_LEGACY_INTX_MAX_RETRY 100
53 #define QLC_83XX_LEGACY_INTX_DELAY 4
54 #define QLC_83XX_REG_DESC 1
55 #define QLC_83XX_LRO_DESC 2
56 #define QLC_83XX_CTRL_DESC 3
57 #define QLC_83XX_FW_CAPABILITY_TSO BIT_6
58 #define QLC_83XX_FW_CAP_LRO_MSS BIT_17
59 #define QLC_83XX_HOST_RDS_MODE_UNIQUE 0
60 #define QLC_83XX_HOST_SDS_MBX_IDX 8
62 #define QLCNIC_HOST_RDS_MBX_IDX 88
63 #define QLCNIC_MAX_RING_SETS 8
65 /* Pause control registers */
66 #define QLC_83XX_SRE_SHIM_REG 0x0D200284
67 #define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4
68 #define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4
69 #define QLC_83XX_PORT0_TC_MC_REG 0x0B200388
70 #define QLC_83XX_PORT1_TC_MC_REG 0x0B201388
71 #define QLC_83XX_PORT0_TC_STATS 0x0B20039C
72 #define QLC_83XX_PORT1_TC_STATS 0x0B20139C
73 #define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704
74 #define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704
76 /* Peg PC status registers */
77 #define QLC_83XX_CRB_PEG_NET_0 0x3400003c
78 #define QLC_83XX_CRB_PEG_NET_1 0x3410003c
79 #define QLC_83XX_CRB_PEG_NET_2 0x3420003c
80 #define QLC_83XX_CRB_PEG_NET_3 0x3430003c
81 #define QLC_83XX_CRB_PEG_NET_4 0x34b0003c
83 /* Firmware image definitions */
84 #define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000
85 #define QLC_83XX_FW_FILE_NAME "83xx_fw.bin"
86 #define QLC_83XX_BOOT_FROM_FLASH 0
87 #define QLC_83XX_BOOT_FROM_FILE 0x12345678
89 #define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16
91 /* status descriptor mailbox data
92 * @phy_addr_{low|high}: physical address of buffer
93 * @sds_ring_size: buffer size
94 * @intrpt_id: interrupt id
95 * @intrpt_val: source of interrupt
97 struct qlcnic_sds_mbx {
101 #if defined(__LITTLE_ENDIAN)
108 #elif defined(__BIG_ENDIAN)
119 /* receive descriptor buffer data
120 * phy_addr_reg_{low|high}: physical address of regular buffer
121 * phy_addr_jmb_{low|high}: physical address of jumbo buffer
122 * reg_ring_sz: size of regular buffer
123 * reg_ring_len: no. of entries in regular buffer
124 * jmb_ring_len: no. of entries in jumbo buffer
125 * jmb_ring_sz: size of jumbo buffer
127 struct qlcnic_rds_mbx {
128 u32 phy_addr_reg_low;
129 u32 phy_addr_reg_high;
130 u32 phy_addr_jmb_low;
131 u32 phy_addr_jmb_high;
132 #if defined(__LITTLE_ENDIAN)
137 #elif defined(__BIG_ENDIAN)
145 /* host producers for regular and jumbo rings */
146 struct __host_producer_mbx {
151 /* Receive context mailbox data outbox registers
152 * @state: state of the context
153 * @vport_id: virtual port id
154 * @context_id: receive context id
155 * @num_pci_func: number of pci functions of the port
156 * @phy_port: physical port id
158 struct qlcnic_rcv_mbx_out {
159 #if defined(__LITTLE_ENDIAN)
167 #elif defined(__BIG_ENDIAN)
176 u32 host_csmr[QLCNIC_MAX_RING_SETS];
177 struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS];
180 struct qlcnic_add_rings_mbx_out {
181 #if defined(__LITTLE_ENDIAN)
185 #elif defined(__BIG_ENDIAN)
190 u32 host_csmr[QLCNIC_MAX_RING_SETS];
191 struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS];
194 /* Transmit context mailbox inbox registers
195 * @phys_addr_{low|high}: DMA address of the transmit buffer
196 * @cnsmr_index_{low|high}: host consumer index
197 * @size: legth of transmit buffer ring
198 * @intr_id: interrput id
199 * @src: src of interrupt
201 struct qlcnic_tx_mbx {
205 u32 cnsmr_index_high;
206 #if defined(__LITTLE_ENDIAN)
211 #elif defined(__BIG_ENDIAN)
219 /* Transmit context mailbox outbox registers
220 * @host_prod: host producer index
221 * @ctx_id: transmit context id
222 * @state: state of the transmit context
225 struct qlcnic_tx_mbx_out {
227 #if defined(__LITTLE_ENDIAN)
231 #elif defined(__BIG_ENDIAN)
238 struct qlcnic_intrpt_config {
245 struct qlcnic_macvlan_mbx {
246 #if defined(__LITTLE_ENDIAN)
254 #elif defined(__BIG_ENDIAN)
265 struct qlc_83xx_fw_info {
266 const struct firmware *fw;
267 u16 major_fw_version;
274 struct qlc_83xx_reset {
275 struct qlc_83xx_reset_hdr *hdr;
279 u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
288 #define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1
289 #define QLC_83XX_IDC_GRACEFULL_RESET 0x2
290 #define QLC_83XX_IDC_TIMESTAMP 0
291 #define QLC_83XX_IDC_DURATION 1
292 #define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30
293 #define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10
294 #define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10
295 #define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20
296 #define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ)
297 #define QLC_83XX_IDC_FW_FAIL_THRESH 2
298 #define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8
299 #define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16
300 #define QLC_83XX_IDC_MAJOR_VERSION 1
301 #define QLC_83XX_IDC_MINOR_VERSION 0
302 #define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020
304 struct qlcnic_adapter;
305 struct qlc_83xx_idc {
306 int (*state_entry) (struct qlcnic_adapter *);
309 unsigned long status;
320 #define QLCNIC_MBX_RSP(reg) LSW(reg)
321 #define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF)
322 #define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F)
323 #define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4))
324 #define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4))
326 /* Mailbox process AEN count */
327 #define QLC_83XX_IDC_COMP_AEN 3
328 #define QLC_83XX_MBX_AEN_CNT 5
329 #define QLC_83XX_MODULE_LOADED 1
330 #define QLC_83XX_MBX_READY 2
331 #define QLC_83XX_MBX_AEN_ACK 3
332 #define QLC_83XX_SFP_PRESENT(data) ((data) & 3)
333 #define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3)
334 #define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F)
335 #define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16))
336 #define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10)
337 #define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11)
338 #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
339 #define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7)
340 #define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3)
341 #define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7)
342 #define QLC_83XX_LINK_FEC(data) ((data) & BIT_12)
343 #define QLC_83XX_LINK_EEE(data) ((data) & BIT_13)
344 #define QLC_83XX_DCBX(data) (((data) >> 28) & 7)
345 #define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
346 #define QLC_83XX_CFG_STD_PAUSE (1 << 5)
347 #define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20)
348 #define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20)
349 #define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20)
350 #define QLC_83XX_ENABLE_AUTONEG (1 << 15)
351 #define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1)
352 #define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1)
353 #define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1)
355 /* LED configuration settings */
356 #define QLC_83XX_ENABLE_BEACON 0xe
357 #define QLC_83XX_LED_RATE 0xff
358 #define QLC_83XX_LED_ACT (1 << 10)
359 #define QLC_83XX_LED_MOD (0 << 13)
360 #define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
363 #define QLC_83XX_10M_LINK 1
364 #define QLC_83XX_100M_LINK 2
365 #define QLC_83XX_1G_LINK 3
366 #define QLC_83XX_10G_LINK 4
367 #define QLC_83XX_STAT_TX 3
368 #define QLC_83XX_STAT_RX 2
369 #define QLC_83XX_STAT_MAC 1
370 #define QLC_83XX_TX_STAT_REGS 14
371 #define QLC_83XX_RX_STAT_REGS 40
372 #define QLC_83XX_MAC_STAT_REGS 80
374 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
375 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
376 #define QLC_83XX_DEFAULT_OPMODE 0x55555555
377 #define QLC_83XX_PRIVLEGED_FUNC 0x1
378 #define QLC_83XX_VIRTUAL_FUNC 0x2
380 #define QLC_83XX_LB_MAX_FILTERS 2048
381 #define QLC_83XX_LB_BUCKET_SIZE 256
382 #define QLC_83XX_MINIMUM_VECTOR 3
384 #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000)
385 #define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20)
386 #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
387 #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
388 #define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400)
389 #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000)
390 #define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000)
391 #define QLC_83XX_VIRTUAL_NIC_MODE 0xFF
392 #define QLC_83XX_DEFAULT_MODE 0x0
393 #define QLC_83XX_SRIOV_MODE 0x1
394 #define QLCNIC_BRDTYPE_83XX_10G 0x0083
396 #define QLC_83XX_FLASH_SPI_STATUS 0x2808E010
397 #define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014
398 #define QLC_83XX_FLASH_STATUS 0x42100004
399 #define QLC_83XX_FLASH_CONTROL 0x42110004
400 #define QLC_83XX_FLASH_ADDR 0x42110008
401 #define QLC_83XX_FLASH_WRDATA 0x4211000C
402 #define QLC_83XX_FLASH_RDDATA 0x42110018
403 #define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030
404 #define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
405 #define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
406 #define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda
407 #define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca
408 #define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
409 #define QLC_83XX_FLASH_STATUS_READY 0x6
410 #define QLC_83XX_FLASH_WRITE_MIN 2
411 #define QLC_83XX_FLASH_WRITE_MAX 64
412 #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1
413 #define QLC_83XX_ERASE_MODE 1
414 #define QLC_83XX_WRITE_MODE 2
415 #define QLC_83XX_BULK_WRITE_MODE 3
416 #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100
417 #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300
418 #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F
419 #define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8
420 #define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101
421 #define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005
422 #define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000
423 #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001
424 #define QLC_83XX_FLASH_WRDATA_DEF 0x0
425 #define QLC_83XX_FLASH_READ_CTRL 0x3F
426 #define QLC_83XX_FLASH_SPI_CTRL 0x4
427 #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2
428 #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5
429 #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D
430 #define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
431 #define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F
432 #define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D
433 #define QLC_83xx_FLASH_MAX_WAIT_USEC 100
434 #define QLC_83XX_FLASH_LOCK_TIMEOUT 10000
436 /* Additional registers in 83xx */
437 enum qlc_83xx_ext_regs {
438 QLCNIC_GLOBAL_RESET = 0,
441 QLCNIC_HOST_MBX_CTRL,
443 QLCNIC_BOOTLOADER_ADDR,
444 QLCNIC_BOOTLOADER_SIZE,
445 QLCNIC_FW_IMAGE_ADDR,
446 QLCNIC_MBX_INTR_ENBL,
449 QLC_83XX_IDC_MAJ_VERSION,
450 QLC_83XX_IDC_DEV_STATE,
451 QLC_83XX_IDC_DRV_PRESENCE,
452 QLC_83XX_IDC_DRV_ACK,
454 QLC_83XX_IDC_DRV_AUDIT,
455 QLC_83XX_IDC_MIN_VERSION,
456 QLC_83XX_RECOVER_DRV_LOCK,
473 QLC_83XX_IDC_DEV_PARTITION_INFO_1,
474 QLC_83XX_IDC_DEV_PARTITION_INFO_2,
475 QLC_83XX_DRV_OP_MODE,
479 QLC_83XX_DRV_LOCK_ID,
484 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
485 int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
486 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8);
487 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
488 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
489 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
490 int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
491 void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
492 void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
493 void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
494 void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
495 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong);
496 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
497 void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []);
498 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
499 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
500 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
501 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
502 int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
503 int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *);
504 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, __le16);
505 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
506 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
507 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int);
509 int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
510 void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
511 void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
512 void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
513 int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
514 void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
515 int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
516 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
517 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
518 struct qlcnic_host_tx_ring *, int);
519 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *);
520 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *,
521 struct qlcnic_host_tx_ring *);
522 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
523 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
524 void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
525 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
526 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8);
527 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *);
528 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
529 struct qlcnic_cmd_args *);
530 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
531 struct qlcnic_adapter *, u32);
532 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
533 void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
534 struct qlcnic_info *);
535 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *);
536 irqreturn_t qlcnic_83xx_handle_aen(int, void *);
537 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
538 void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *);
539 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
540 irqreturn_t qlcnic_83xx_intr(int, void *);
541 irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
542 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *,
543 struct qlcnic_host_sds_ring *);
544 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *,
545 struct qlcnic_host_sds_ring *);
546 void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
547 const struct pci_device_id *);
548 void qlcnic_83xx_process_aen(struct qlcnic_adapter *);
549 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
550 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
551 int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8);
552 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *);
553 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
554 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
555 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
556 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
557 void qlcnic_83xx_idc_aen_work(struct work_struct *);
558 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
560 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
561 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
562 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
563 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
564 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
565 int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
566 int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
567 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
568 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
569 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int);
570 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *,
572 int qlcnic_83xx_init(struct qlcnic_adapter *, int);
573 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *);
574 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev);
575 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *);
576 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *);
577 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *);
578 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32);
579 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *);
580 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *);
581 int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *);
582 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32);
583 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *);
584 int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int);
585 int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int);
586 int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *);
587 int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *,
588 struct qlcnic_info *, u8);
589 int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *);
591 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *);
592 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data);
593 int qlcnic_83xx_get_settings(struct qlcnic_adapter *);
594 int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
595 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *,
596 struct ethtool_pauseparam *);
597 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *,
598 struct ethtool_pauseparam *);
599 int qlcnic_83xx_test_link(struct qlcnic_adapter *);
600 int qlcnic_83xx_reg_test(struct qlcnic_adapter *);
601 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *);
602 int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *);
603 int qlcnic_83xx_loopback_test(struct net_device *, u8);
604 int qlcnic_83xx_interrupt_test(struct net_device *);
605 int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state);
606 int qlcnic_83xx_flash_test(struct qlcnic_adapter *);
607 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *);
608 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *);
609 u32 qlcnic_83xx_mac_rcode(struct qlcnic_adapter *);
610 u32 qlcnic_83xx_mbx_poll(struct qlcnic_adapter *);