drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  29 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  30 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  31
  32 /* Template header */
  33 struct qlc_83xx_reset_hdr {
  34 #if defined(__LITTLE_ENDIAN)
  35         u16     version;
  36         u16     signature;
  37         u16     size;
  38         u16     entries;
  39         u16     hdr_size;
  40         u16     checksum;
  41         u16     init_offset;
  42         u16     start_offset;
  43 #elif defined(__BIG_ENDIAN)
  44         u16     signature;
  45         u16     version;
  46         u16     entries;
  47         u16     size;
  48         u16     checksum;
  49         u16     hdr_size;
  50         u16     start_offset;
  51         u16     init_offset;
  52 #endif
  53 } __packed;
  54
  55 /* Command entry header. */
  56 struct qlc_83xx_entry_hdr {
  57 #if defined(__LITTLE_ENDIAN)
  58         u16     cmd;
  59         u16     size;
  60         u16     count;
  61         u16     delay;
  62 #elif defined(__BIG_ENDIAN)
  63         u16     size;
  64         u16     cmd;
  65         u16     delay;
  66         u16     count;
  67 #endif
  68 } __packed;
  69
  70 /* Generic poll command */
  71 struct qlc_83xx_poll {
  72         u32     mask;
  73         u32     status;
  74 } __packed;
  75
  76 /* Read modify write command */
  77 struct qlc_83xx_rmw {
  78         u32     mask;
  79         u32     xor_value;
  80         u32     or_value;
  81 #if defined(__LITTLE_ENDIAN)
  82         u8      shl;
  83         u8      shr;
  84         u8      index_a;
  85         u8      rsvd;
  86 #elif defined(__BIG_ENDIAN)
  87         u8      rsvd;
  88         u8      index_a;
  89         u8      shr;
  90         u8      shl;
  91 #endif
  92 } __packed;
  93
  94 /* Generic command with 2 DWORD */
  95 struct qlc_83xx_entry {
  96         u32 arg1;
  97         u32 arg2;
  98 } __packed;
  99
 100 /* Generic command with 4 DWORD */
 101 struct qlc_83xx_quad_entry {
 102         u32 dr_addr;
 103         u32 dr_value;
 104         u32 ar_addr;
 105         u32 ar_value;
 106 } __packed;
 107 static const char *const qlc_83xx_idc_states[] = {
 108         "Unknown",
 109         "Cold",
 110         "Init",
 111         "Ready",
 112         "Need Reset",
 113         "Need Quiesce",
 114         "Failed",
 115         "Quiesce"
 116 };
 117
 118 static int
 119 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 120 {
 121         u32 val;
 122
 123         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 124         if ((val & 0xFFFF))
 125                 return 1;
 126         else
 127                 return 0;
 128 }
 129
 130 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 131 {
 132         u32 cur, prev;
 133         cur = adapter->ahw->idc.curr_state;
 134         prev = adapter->ahw->idc.prev_state;
 135
 136         dev_info(&adapter->pdev->dev,
 137                  "current state  = %s,  prev state = %s\n",
 138                  adapter->ahw->idc.name[cur],
 139                  adapter->ahw->idc.name[prev]);
 140 }
 141
 142 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 143                                             u8 mode, int lock)
 144 {
 145         u32 val;
 146         int seconds;
 147
 148         if (lock) {
 149                 if (qlcnic_83xx_lock_driver(adapter))
 150                         return -EBUSY;
 151         }
 152
 153         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 154         val |= (adapter->portnum & 0xf);
 155         val |= mode << 7;
 156         if (mode)
 157                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 158         else
 159                 seconds = jiffies / HZ;
 160
 161         val |= seconds << 8;
 162         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 163         adapter->ahw->idc.sec_counter = jiffies / HZ;
 164
 165         if (lock)
 166                 qlcnic_83xx_unlock_driver(adapter);
 167
 168         return 0;
 169 }
 170
 171 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 172 {
 173         u32 val;
 174
 175         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 176         val = val & ~(0x3 << (adapter->portnum * 2));
 177         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 178         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 179 }
 180
 181 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 182                                                 int lock)
 183 {
 184         u32 val;
 185
 186         if (lock) {
 187                 if (qlcnic_83xx_lock_driver(adapter))
 188                         return -EBUSY;
 189         }
 190
 191         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 192         val = val & ~0xFF;
 193         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 194         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 195
 196         if (lock)
 197                 qlcnic_83xx_unlock_driver(adapter);
 198
 199         return 0;
 200 }
 201
 202 static int
 203 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 204                                         int status, int lock)
 205 {
 206         u32 val;
 207
 208         if (lock) {
 209                 if (qlcnic_83xx_lock_driver(adapter))
 210                         return -EBUSY;
 211         }
 212
 213         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 214
 215         if (status)
 216                 val = val | (1 << adapter->portnum);
 217         else
 218                 val = val & ~(1 << adapter->portnum);
 219
 220         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 221         qlcnic_83xx_idc_update_minor_version(adapter);
 222
 223         if (lock)
 224                 qlcnic_83xx_unlock_driver(adapter);
 225
 226         return 0;
 227 }
 228
 229 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 230 {
 231         u32 val;
 232         u8 version;
 233
 234         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 235         version = val & 0xFF;
 236
 237         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 238                 dev_info(&adapter->pdev->dev,
 239                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 240                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 241                 return -EIO;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 248                                            int lock)
 249 {
 250         u32 val;
 251
 252         if (lock) {
 253                 if (qlcnic_83xx_lock_driver(adapter))
 254                         return -EBUSY;
 255         }
 256
 257         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 258         /* Clear gracefull reset bit */
 259         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 260         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 261         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 262
 263         if (lock)
 264                 qlcnic_83xx_unlock_driver(adapter);
 265
 266         return 0;
 267 }
 268
 269 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 270                                               int flag, int lock)
 271 {
 272         u32 val;
 273
 274         if (lock) {
 275                 if (qlcnic_83xx_lock_driver(adapter))
 276                         return -EBUSY;
 277         }
 278
 279         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 280         if (flag)
 281                 val = val | (1 << adapter->portnum);
 282         else
 283                 val = val & ~(1 << adapter->portnum);
 284         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 285
 286         if (lock)
 287                 qlcnic_83xx_unlock_driver(adapter);
 288
 289         return 0;
 290 }
 291
 292 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 293                                          int time_limit)
 294 {
 295         u64 seconds;
 296
 297         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 298         if (seconds <= time_limit)
 299                 return 0;
 300         else
 301                 return -EBUSY;
 302 }
 303
 304 /**
 305  * qlcnic_83xx_idc_check_reset_ack_reg
 306  *
 307  * @adapter: adapter structure
 308  *
 309  * Check ACK wait limit and clear the functions which failed to ACK
 310  *
 311  * Return 0 if all functions have acknowledged the reset request.
 312  **/
 313 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 314 {
 315         int timeout;
 316         u32 ack, presence, val;
 317
 318         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 319         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 320         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 321         dev_info(&adapter->pdev->dev,
 322                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 323         if (!((ack & presence) == presence)) {
 324                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 325                         /* Clear functions which failed to ACK */
 326                         dev_info(&adapter->pdev->dev,
 327                                  "%s: ACK wait exceeds time limit\n", __func__);
 328                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 329                         val = val & ~(ack ^ presence);
 330                         if (qlcnic_83xx_lock_driver(adapter))
 331                                 return -EBUSY;
 332                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 333                         dev_info(&adapter->pdev->dev,
 334                                  "%s: updated drv presence reg = 0x%x\n",
 335                                  __func__, val);
 336                         qlcnic_83xx_unlock_driver(adapter);
 337                         return 0;
 338
 339                 } else {
 340                         return 1;
 341                 }
 342         } else {
 343                 dev_info(&adapter->pdev->dev,
 344                          "%s: Reset ACK received from all functions\n",
 345                          __func__);
 346                 return 0;
 347         }
 348 }
 349
 350 /**
 351  * qlcnic_83xx_idc_tx_soft_reset
 352  *
 353  * @adapter: adapter structure
 354  *
 355  * Handle context deletion and recreation request from transmit routine
 356  *
 357  * Returns -EBUSY  or Success (0)
 358  *
 359  **/
 360 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 361 {
 362         struct net_device *netdev = adapter->netdev;
 363
 364         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 365                 return -EBUSY;
 366
 367         netif_device_detach(netdev);
 368         qlcnic_down(adapter, netdev);
 369         qlcnic_up(adapter, netdev);
 370         netif_device_attach(netdev);
 371         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 372         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 373
 374         adapter->netdev->trans_start = jiffies;
 375
 376         return 0;
 377 }
 378
 379 /**
 380  * qlcnic_83xx_idc_detach_driver
 381  *
 382  * @adapter: adapter structure
 383  * Detach net interface, stop TX and cleanup resources before the HW reset.
 384  * Returns: None
 385  *
 386  **/
 387 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 388 {
 389         int i;
 390         struct net_device *netdev = adapter->netdev;
 391
 392         netif_device_detach(netdev);
 393
 394         /* Disable mailbox interrupt */
 395         qlcnic_83xx_disable_mbx_intr(adapter);
 396         qlcnic_down(adapter, netdev);
 397         for (i = 0; i < adapter->ahw->num_msix; i++) {
 398                 adapter->ahw->intr_tbl[i].id = i;
 399                 adapter->ahw->intr_tbl[i].enabled = 0;
 400                 adapter->ahw->intr_tbl[i].src = 0;
 401         }
 402
 403         if (qlcnic_sriov_pf_check(adapter))
 404                 qlcnic_sriov_pf_reset(adapter);
 405 }
 406
 407 /**
 408  * qlcnic_83xx_idc_attach_driver
 409  *
 410  * @adapter: adapter structure
 411  *
 412  * Re-attach and re-enable net interface
 413  * Returns: None
 414  *
 415  **/
 416 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 417 {
 418         struct net_device *netdev = adapter->netdev;
 419
 420         if (netif_running(netdev)) {
 421                 if (qlcnic_up(adapter, netdev))
 422                         goto done;
 423                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 424         }
 425 done:
 426         netif_device_attach(netdev);
 427         if (netif_running(netdev)) {
 428                 netif_carrier_on(netdev);
 429                 netif_wake_queue(netdev);
 430         }
 431 }
 432
 433 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 434                                               int lock)
 435 {
 436         if (lock) {
 437                 if (qlcnic_83xx_lock_driver(adapter))
 438                         return -EBUSY;
 439         }
 440
 441         qlcnic_83xx_idc_clear_registers(adapter, 0);
 442         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 443         if (lock)
 444                 qlcnic_83xx_unlock_driver(adapter);
 445
 446         qlcnic_83xx_idc_log_state_history(adapter);
 447         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 448
 449         return 0;
 450 }
 451
 452 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 453                                             int lock)
 454 {
 455         if (lock) {
 456                 if (qlcnic_83xx_lock_driver(adapter))
 457                         return -EBUSY;
 458         }
 459
 460         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 461
 462         if (lock)
 463                 qlcnic_83xx_unlock_driver(adapter);
 464
 465         return 0;
 466 }
 467
 468 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 469                                               int lock)
 470 {
 471         if (lock) {
 472                 if (qlcnic_83xx_lock_driver(adapter))
 473                         return -EBUSY;
 474         }
 475
 476         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 477                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 478
 479         if (lock)
 480                 qlcnic_83xx_unlock_driver(adapter);
 481
 482         return 0;
 483 }
 484
 485 static int
 486 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 487 {
 488         if (lock) {
 489                 if (qlcnic_83xx_lock_driver(adapter))
 490                         return -EBUSY;
 491         }
 492
 493         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 494                QLC_83XX_IDC_DEV_NEED_RESET);
 495
 496         if (lock)
 497                 qlcnic_83xx_unlock_driver(adapter);
 498
 499         return 0;
 500 }
 501
 502 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 503                                              int lock)
 504 {
 505         if (lock) {
 506                 if (qlcnic_83xx_lock_driver(adapter))
 507                         return -EBUSY;
 508         }
 509
 510         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 511         if (lock)
 512                 qlcnic_83xx_unlock_driver(adapter);
 513
 514         return 0;
 515 }
 516
 517 /**
 518  * qlcnic_83xx_idc_find_reset_owner_id
 519  *
 520  * @adapter: adapter structure
 521  *
 522  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 523  * Within the same class, function with lowest PCI ID assumes ownership
 524  *
 525  * Returns: reset owner id or failure indication (-EIO)
 526  *
 527  **/
 528 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 529 {
 530         u32 reg, reg1, reg2, i, j, owner, class;
 531
 532         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 533         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 534         owner = QLCNIC_TYPE_NIC;
 535         i = 0;
 536         j = 0;
 537         reg = reg1;
 538
 539         do {
 540                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 541                 if (class == owner)
 542                         break;
 543                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 544                         reg = reg2;
 545                         j = 0;
 546                 } else {
 547                         j++;
 548                 }
 549
 550                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 551                         if (owner == QLCNIC_TYPE_NIC)
 552                                 owner = QLCNIC_TYPE_ISCSI;
 553                         else if (owner == QLCNIC_TYPE_ISCSI)
 554                                 owner = QLCNIC_TYPE_FCOE;
 555                         else if (owner == QLCNIC_TYPE_FCOE)
 556                                 return -EIO;
 557                         reg = reg1;
 558                         j = 0;
 559                         i = 0;
 560                 }
 561         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 562
 563         return i;
 564 }
 565
 566 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 567 {
 568         int ret = 0;
 569
 570         ret = qlcnic_83xx_restart_hw(adapter);
 571
 572         if (ret) {
 573                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 574         } else {
 575                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 576                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 577         }
 578
 579         return ret;
 580 }
 581
 582 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 583 {
 584         u32 status;
 585
 586         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 587
 588         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 589                 dev_err(&adapter->pdev->dev,
 590                         "peg halt status1=0x%x\n", status);
 591                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 592                         dev_err(&adapter->pdev->dev,
 593                                 "On board active cooling fan failed. "
 594                                 "Device has been halted.\n");
 595                         dev_err(&adapter->pdev->dev,
 596                                 "Replace the adapter.\n");
 597                         return -EIO;
 598                 }
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 605 {
 606         int err;
 607
 608         /* register for NIC IDC AEN Events */
 609         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 610
 611         err = qlcnic_sriov_pf_reinit(adapter);
 612         if (err)
 613                 return err;
 614
 615         qlcnic_83xx_enable_mbx_intrpt(adapter);
 616
 617         if (qlcnic_83xx_configure_opmode(adapter)) {
 618                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 619                 return -EIO;
 620         }
 621
 622         if (adapter->nic_ops->init_driver(adapter)) {
 623                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 624                 return -EIO;
 625         }
 626
 627         qlcnic_83xx_idc_attach_driver(adapter);
 628
 629         return 0;
 630 }
 631
 632 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 633 {
 634         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 635         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 636         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 637         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 638         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 639         adapter->ahw->idc.quiesce_req = 0;
 640         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 641         adapter->ahw->idc.err_code = 0;
 642         adapter->ahw->idc.collect_dump = 0;
 643 }
 644
 645 /**
 646  * qlcnic_83xx_idc_ready_state_entry
 647  *
 648  * @adapter: adapter structure
 649  *
 650  * Perform ready state initialization, this routine will get invoked only
 651  * once from READY state.
 652  *
 653  * Returns: Error code or Success(0)
 654  *
 655  **/
 656 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 657 {
 658         struct qlcnic_hardware_context *ahw = adapter->ahw;
 659
 660         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 661                 qlcnic_83xx_idc_update_idc_params(adapter);
 662                 /* Re-attach the device if required */
 663                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 664                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 665                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 666                                 return -EIO;
 667                 }
 668         }
 669
 670         return 0;
 671 }
 672
 673 /**
 674  * qlcnic_83xx_idc_vnic_pf_entry
 675  *
 676  * @adapter: adapter structure
 677  *
 678  * Ensure vNIC mode privileged function starts only after vNIC mode is
 679  * enabled by management function.
 680  * If vNIC mode is ready, start initialization.
 681  *
 682  * Returns: -EIO or 0
 683  *
 684  **/
 685 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 686 {
 687         u32 state;
 688         struct qlcnic_hardware_context *ahw = adapter->ahw;
 689
 690         /* Privileged function waits till mgmt function enables VNIC mode */
 691         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 692         if (state != QLCNIC_DEV_NPAR_OPER) {
 693                 if (!ahw->idc.vnic_wait_limit--) {
 694                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 695                         return -EIO;
 696                 }
 697                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 698                 return -EIO;
 699
 700         } else {
 701                 /* Perform one time initialization from ready state */
 702                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 703                         qlcnic_83xx_idc_update_idc_params(adapter);
 704
 705                         /* If the previous state is UNKNOWN, device will be
 706                            already attached properly by Init routine*/
 707                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 708                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 709                                         return -EIO;
 710                         }
 711                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 712                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 713                 }
 714         }
 715
 716         return 0;
 717 }
 718
 719 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 720 {
 721         adapter->ahw->idc.err_code = -EIO;
 722         dev_err(&adapter->pdev->dev,
 723                 "%s: Device in unknown state\n", __func__);
 724         return 0;
 725 }
 726
 727 /**
 728  * qlcnic_83xx_idc_cold_state
 729  *
 730  * @adapter: adapter structure
 731  *
 732  * If HW is up and running device will enter READY state.
 733  * If firmware image from host needs to be loaded, device is
 734  * forced to start with the file firmware image.
 735  *
 736  * Returns: Error code or Success(0)
 737  *
 738  **/
 739 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 740 {
 741         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 742         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 743
 744         if (qlcnic_load_fw_file) {
 745                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 746         } else {
 747                 if (qlcnic_83xx_check_hw_status(adapter)) {
 748                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 749                         return -EIO;
 750                 } else {
 751                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 752                 }
 753         }
 754         return 0;
 755 }
 756
 757 /**
 758  * qlcnic_83xx_idc_init_state
 759  *
 760  * @adapter: adapter structure
 761  *
 762  * Reset owner will restart the device from this state.
 763  * Device will enter failed state if it remains
 764  * in this state for more than DEV_INIT time limit.
 765  *
 766  * Returns: Error code or Success(0)
 767  *
 768  **/
 769 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 770 {
 771         int timeout, ret = 0;
 772         u32 owner;
 773
 774         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 775         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 776                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 777                 if (adapter->ahw->pci_func == owner)
 778                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 779         } else {
 780                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 781                 return ret;
 782         }
 783
 784         return ret;
 785 }
 786
 787 /**
 788  * qlcnic_83xx_idc_ready_state
 789  *
 790  * @adapter: adapter structure
 791  *
 792  * Perform IDC protocol specicifed actions after monitoring device state and
 793  * events.
 794  *
 795  * Returns: Error code or Success(0)
 796  *
 797  **/
 798 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 799 {
 800         u32 val;
 801         struct qlcnic_hardware_context *ahw = adapter->ahw;
 802         int ret = 0;
 803
 804         /* Perform NIC configuration based ready state entry actions */
 805         if (ahw->idc.state_entry(adapter))
 806                 return -EIO;
 807
 808         if (qlcnic_check_temp(adapter)) {
 809                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 810                         qlcnic_83xx_idc_check_fan_failure(adapter);
 811                         dev_err(&adapter->pdev->dev,
 812                                 "Error: device temperature %d above limits\n",
 813                                 adapter->ahw->temp);
 814                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 815                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 816                         qlcnic_83xx_idc_detach_driver(adapter);
 817                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 818                         return -EIO;
 819                 }
 820         }
 821
 822         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 823         ret = qlcnic_83xx_check_heartbeat(adapter);
 824         if (ret) {
 825                 adapter->flags |= QLCNIC_FW_HANG;
 826                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 827                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 828                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 829                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 830                 }
 831                 return -EIO;
 832         }
 833
 834         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 835                 /* Move to need reset state and prepare for reset */
 836                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 837                 return ret;
 838         }
 839
 840         /* Check for soft reset request */
 841         if (ahw->reset_context &&
 842             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 843                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 844                 return ret;
 845         }
 846
 847         /* Move to need quiesce state if requested */
 848         if (adapter->ahw->idc.quiesce_req) {
 849                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 850                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 851                 return ret;
 852         }
 853
 854         return ret;
 855 }
 856
 857 /**
 858  * qlcnic_83xx_idc_need_reset_state
 859  *
 860  * @adapter: adapter structure
 861  *
 862  * Device will remain in this state until:
 863  *      Reset request ACK's are recieved from all the functions
 864  *      Wait time exceeds max time limit
 865  *
 866  * Returns: Error code or Success(0)
 867  *
 868  **/
 869 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 870 {
 871         int ret = 0;
 872
 873         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 874                 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 875                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 876                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 877                 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 878                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 879                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 880                 qlcnic_83xx_idc_detach_driver(adapter);
 881         }
 882
 883         /* Check ACK from other functions */
 884         ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 885         if (ret) {
 886                 dev_info(&adapter->pdev->dev,
 887                          "%s: Waiting for reset ACK\n", __func__);
 888                 return 0;
 889         }
 890
 891         /* Transit to INIT state and restart the HW */
 892         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 893
 894         return ret;
 895 }
 896
 897 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 898 {
 899         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 900         return 0;
 901 }
 902
 903 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 904 {
 905         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 906         adapter->ahw->idc.err_code = -EIO;
 907
 908         return 0;
 909 }
 910
 911 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 912 {
 913         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 914         return 0;
 915 }
 916
 917 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 918                                                 u32 state)
 919 {
 920         u32 cur, prev, next;
 921
 922         cur = adapter->ahw->idc.curr_state;
 923         prev = adapter->ahw->idc.prev_state;
 924         next = state;
 925
 926         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 927             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 928                 dev_err(&adapter->pdev->dev,
 929                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 930                         __func__, cur, prev, state);
 931                 return 1;
 932         }
 933
 934         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 935             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 936                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 937                     (next != QLC_83XX_IDC_DEV_READY)) {
 938                         dev_err(&adapter->pdev->dev,
 939                                 "%s: failed, cur %d prev %d next %d\n",
 940                                 __func__, cur, prev, next);
 941                         return 1;
 942                 }
 943         }
 944
 945         if (next == QLC_83XX_IDC_DEV_INIT) {
 946                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 947                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 948                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 949                         dev_err(&adapter->pdev->dev,
 950                                 "%s: failed, cur %d prev %d next %d\n",
 951                                 __func__, cur, prev, next);
 952                         return 1;
 953                 }
 954         }
 955
 956         return 0;
 957 }
 958
 959 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
 960 {
 961         if (adapter->fhash.fnum)
 962                 qlcnic_prune_lb_filters(adapter);
 963 }
 964
 965 /**
 966  * qlcnic_83xx_idc_poll_dev_state
 967  *
 968  * @work: kernel work queue structure used to schedule the function
 969  *
 970  * Poll device state periodically and perform state specific
 971  * actions defined by Inter Driver Communication (IDC) protocol.
 972  *
 973  * Returns: None
 974  *
 975  **/
 976 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
 977 {
 978         struct qlcnic_adapter *adapter;
 979         u32 state;
 980
 981         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
 982         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
 983
 984         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
 985                 qlcnic_83xx_idc_log_state_history(adapter);
 986                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
 987         } else {
 988                 adapter->ahw->idc.curr_state = state;
 989         }
 990
 991         switch (adapter->ahw->idc.curr_state) {
 992         case QLC_83XX_IDC_DEV_READY:
 993                 qlcnic_83xx_idc_ready_state(adapter);
 994                 break;
 995         case QLC_83XX_IDC_DEV_NEED_RESET:
 996                 qlcnic_83xx_idc_need_reset_state(adapter);
 997                 break;
 998         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
 999                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1000                 break;
1001         case QLC_83XX_IDC_DEV_FAILED:
1002                 qlcnic_83xx_idc_failed_state(adapter);
1003                 return;
1004         case QLC_83XX_IDC_DEV_INIT:
1005                 qlcnic_83xx_idc_init_state(adapter);
1006                 break;
1007         case QLC_83XX_IDC_DEV_QUISCENT:
1008                 qlcnic_83xx_idc_quiesce_state(adapter);
1009                 break;
1010         default:
1011                 qlcnic_83xx_idc_unknown_state(adapter);
1012                 return;
1013         }
1014         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1015         qlcnic_83xx_periodic_tasks(adapter);
1016
1017         /* Re-schedule the function */
1018         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1019                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1020                                      adapter->ahw->idc.delay);
1021 }
1022
1023 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1024 {
1025         u32 idc_params, val;
1026
1027         if (qlcnic_83xx_lockless_flash_read32(adapter,
1028                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1029                                               (u8 *)&idc_params, 1)) {
1030                 dev_info(&adapter->pdev->dev,
1031                          "%s:failed to get IDC params from flash\n", __func__);
1032                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1033                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1034         } else {
1035                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1036                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1037         }
1038
1039         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1040         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1041         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1042         adapter->ahw->idc.err_code = 0;
1043         adapter->ahw->idc.collect_dump = 0;
1044         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1045
1046         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1047         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1048         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1049
1050         /* Check if reset recovery is disabled */
1051         if (!qlcnic_auto_fw_reset) {
1052                 /* Propagate do not reset request to other functions */
1053                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1054                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1055                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1056         }
1057 }
1058
1059 static int
1060 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1061 {
1062         u32 state, val;
1063
1064         if (qlcnic_83xx_lock_driver(adapter))
1065                 return -EIO;
1066
1067         /* Clear driver lock register */
1068         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1069         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1070                 qlcnic_83xx_unlock_driver(adapter);
1071                 return -EIO;
1072         }
1073
1074         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1075         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1076                 qlcnic_83xx_unlock_driver(adapter);
1077                 return -EIO;
1078         }
1079
1080         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1081                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1082                        QLC_83XX_IDC_DEV_COLD);
1083                 state = QLC_83XX_IDC_DEV_COLD;
1084         }
1085
1086         adapter->ahw->idc.curr_state = state;
1087         /* First to load function should cold boot the device */
1088         if (state == QLC_83XX_IDC_DEV_COLD)
1089                 qlcnic_83xx_idc_cold_state_handler(adapter);
1090
1091         /* Check if reset recovery is enabled */
1092         if (qlcnic_auto_fw_reset) {
1093                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1094                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1095                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1096         }
1097
1098         qlcnic_83xx_unlock_driver(adapter);
1099
1100         return 0;
1101 }
1102
1103 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1104 {
1105         int ret = -EIO;
1106
1107         qlcnic_83xx_setup_idc_parameters(adapter);
1108
1109         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1110                 return ret;
1111
1112         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1113                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1114                         return -EIO;
1115         } else {
1116                 if (qlcnic_83xx_idc_check_major_version(adapter))
1117                         return -EIO;
1118         }
1119
1120         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1121
1122         return 0;
1123 }
1124
1125 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1126 {
1127         int id;
1128         u32 val;
1129
1130         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1131                 usleep_range(10000, 11000);
1132
1133         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1134         id = id & 0xFF;
1135
1136         if (id == adapter->portnum) {
1137                 dev_err(&adapter->pdev->dev,
1138                         "%s: wait for lock recovery.. %d\n", __func__, id);
1139                 msleep(20);
1140                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1141                 id = id & 0xFF;
1142         }
1143
1144         /* Clear driver presence bit */
1145         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1146         val = val & ~(1 << adapter->portnum);
1147         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1148         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1149         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1150
1151         cancel_delayed_work_sync(&adapter->fw_work);
1152 }
1153
1154 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1155 {
1156         u32 val;
1157
1158         if (qlcnic_83xx_lock_driver(adapter)) {
1159                 dev_err(&adapter->pdev->dev,
1160                         "%s:failed, please retry\n", __func__);
1161                 return;
1162         }
1163
1164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1165         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1166             !qlcnic_auto_fw_reset) {
1167                 dev_err(&adapter->pdev->dev,
1168                         "%s:failed, device in non reset mode\n", __func__);
1169                 qlcnic_83xx_unlock_driver(adapter);
1170                 return;
1171         }
1172
1173         if (key == QLCNIC_FORCE_FW_RESET) {
1174                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1175                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1176                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1177         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1178                 adapter->ahw->idc.collect_dump = 1;
1179         }
1180
1181         qlcnic_83xx_unlock_driver(adapter);
1182         return;
1183 }
1184
1185 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1186 {
1187         u8 *p_cache;
1188         u32 src, size;
1189         u64 dest;
1190         int ret = -EIO;
1191
1192         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1193         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1194         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1195
1196         /* alignment check */
1197         if (size & 0xF)
1198                 size = (size + 16) & ~0xF;
1199
1200         p_cache = kzalloc(size, GFP_KERNEL);
1201         if (p_cache == NULL)
1202                 return -ENOMEM;
1203
1204         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1205                                                 size / sizeof(u32));
1206         if (ret) {
1207                 kfree(p_cache);
1208                 return ret;
1209         }
1210         /* 16 byte write to MS memory */
1211         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1212                                           size / 16);
1213         if (ret) {
1214                 kfree(p_cache);
1215                 return ret;
1216         }
1217         kfree(p_cache);
1218
1219         return ret;
1220 }
1221
1222 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1223 {
1224         u32 dest, *p_cache;
1225         u64 addr;
1226         u8 data[16];
1227         size_t size;
1228         int i, ret = -EIO;
1229
1230         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1231         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1232         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1233         addr = (u64)dest;
1234
1235         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1236                                           (u32 *)p_cache, size / 16);
1237         if (ret) {
1238                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1239                 release_firmware(adapter->ahw->fw_info.fw);
1240                 adapter->ahw->fw_info.fw = NULL;
1241                 return -EIO;
1242         }
1243
1244         /* alignment check */
1245         if (adapter->ahw->fw_info.fw->size & 0xF) {
1246                 addr = dest + size;
1247                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1248                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1249                 for (; i < 16; i++)
1250                         data[i] = 0;
1251                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1252                                                   (u32 *)data, 1);
1253                 if (ret) {
1254                         dev_err(&adapter->pdev->dev,
1255                                 "MS memory write failed\n");
1256                         release_firmware(adapter->ahw->fw_info.fw);
1257                         adapter->ahw->fw_info.fw = NULL;
1258                         return -EIO;
1259                 }
1260         }
1261         release_firmware(adapter->ahw->fw_info.fw);
1262         adapter->ahw->fw_info.fw = NULL;
1263
1264         return 0;
1265 }
1266
1267 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1268 {
1269         int i, j;
1270         u32 val = 0, val1 = 0, reg = 0;
1271
1272         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1273         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1274
1275         for (j = 0; j < 2; j++) {
1276                 if (j == 0) {
1277                         dev_info(&adapter->pdev->dev,
1278                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1279                         reg = QLC_83XX_PORT0_THRESHOLD;
1280                 } else if (j == 1) {
1281                         dev_info(&adapter->pdev->dev,
1282                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1283                         reg = QLC_83XX_PORT1_THRESHOLD;
1284                 }
1285                 for (i = 0; i < 8; i++) {
1286                         val = QLCRD32(adapter, reg + (i * 0x4));
1287                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1288                 }
1289                 dev_info(&adapter->pdev->dev, "\n");
1290         }
1291
1292         for (j = 0; j < 2; j++) {
1293                 if (j == 0) {
1294                         dev_info(&adapter->pdev->dev,
1295                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1296                         reg = QLC_83XX_PORT0_TC_MC_REG;
1297                 } else if (j == 1) {
1298                         dev_info(&adapter->pdev->dev,
1299                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1300                         reg = QLC_83XX_PORT1_TC_MC_REG;
1301                 }
1302                 for (i = 0; i < 4; i++) {
1303                         val = QLCRD32(adapter, reg + (i * 0x4));
1304                          dev_info(&adapter->pdev->dev, "0x%x  ", val);
1305                 }
1306                 dev_info(&adapter->pdev->dev, "\n");
1307         }
1308
1309         for (j = 0; j < 2; j++) {
1310                 if (j == 0) {
1311                         dev_info(&adapter->pdev->dev,
1312                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1313                         reg = QLC_83XX_PORT0_TC_STATS;
1314                 } else if (j == 1) {
1315                         dev_info(&adapter->pdev->dev,
1316                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1317                         reg = QLC_83XX_PORT1_TC_STATS;
1318                 }
1319                 for (i = 7; i >= 0; i--) {
1320                         val = QLCRD32(adapter, reg);
1321                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1322                         QLCWR32(adapter, reg, (val | (i << 29)));
1323                         val = QLCRD32(adapter, reg);
1324                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1325                 }
1326                 dev_info(&adapter->pdev->dev, "\n");
1327         }
1328
1329         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1330         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1331         dev_info(&adapter->pdev->dev,
1332                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1333                  val, val1);
1334 }
1335
1336
1337 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1338 {
1339         u32 reg = 0, i, j;
1340
1341         if (qlcnic_83xx_lock_driver(adapter)) {
1342                 dev_err(&adapter->pdev->dev,
1343                         "%s:failed to acquire driver lock\n", __func__);
1344                 return;
1345         }
1346
1347         qlcnic_83xx_dump_pause_control_regs(adapter);
1348         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1349
1350         for (j = 0; j < 2; j++) {
1351                 if (j == 0)
1352                         reg = QLC_83XX_PORT0_THRESHOLD;
1353                 else if (j == 1)
1354                         reg = QLC_83XX_PORT1_THRESHOLD;
1355
1356                 for (i = 0; i < 8; i++)
1357                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1358         }
1359
1360         for (j = 0; j < 2; j++) {
1361                 if (j == 0)
1362                         reg = QLC_83XX_PORT0_TC_MC_REG;
1363                 else if (j == 1)
1364                         reg = QLC_83XX_PORT1_TC_MC_REG;
1365
1366                 for (i = 0; i < 4; i++)
1367                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1368         }
1369
1370         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1371         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1372         dev_info(&adapter->pdev->dev,
1373                  "Disabled pause frames successfully on all ports\n");
1374         qlcnic_83xx_unlock_driver(adapter);
1375 }
1376
1377 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1378 {
1379         u32 heartbeat, peg_status;
1380         int retries, ret = -EIO;
1381
1382         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1383         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1384                                                QLCNIC_PEG_ALIVE_COUNTER);
1385
1386         do {
1387                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1388                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1389                                                 QLCNIC_PEG_ALIVE_COUNTER);
1390                 if (heartbeat != p_dev->heartbeat) {
1391                         ret = QLCNIC_RCODE_SUCCESS;
1392                         break;
1393                 }
1394         } while (--retries);
1395
1396         if (ret) {
1397                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1398                 qlcnic_83xx_disable_pause_frames(p_dev);
1399                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1400                                                  QLCNIC_PEG_HALT_STATUS1);
1401                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1402                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1403                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1404                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1405                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1406                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1407                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1408                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1409                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1410                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1411                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1412
1413                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1414                         dev_err(&p_dev->pdev->dev,
1415                                 "Device is being reset err code 0x00006700.\n");
1416         }
1417
1418         return ret;
1419 }
1420
1421 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1422 {
1423         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1424         u32 val;
1425
1426         do {
1427                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1428                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1429                         return 0;
1430                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1431         } while (--retries);
1432
1433         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1434         return -EIO;
1435 }
1436
1437 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1438 {
1439         int err;
1440
1441         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1442         if (err)
1443                 return err;
1444
1445         err = qlcnic_83xx_check_heartbeat(p_dev);
1446         if (err)
1447                 return err;
1448
1449         return err;
1450 }
1451
1452 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1453                                 int duration, u32 mask, u32 status)
1454 {
1455         u32 value;
1456         int timeout_error;
1457         u8 retries;
1458
1459         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1460         retries = duration / 10;
1461
1462         do {
1463                 if ((value & mask) != status) {
1464                         timeout_error = 1;
1465                         msleep(duration / 10);
1466                         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1467                 } else {
1468                         timeout_error = 0;
1469                         break;
1470                 }
1471         } while (retries--);
1472
1473         if (timeout_error) {
1474                 p_dev->ahw->reset.seq_error++;
1475                 dev_err(&p_dev->pdev->dev,
1476                         "%s: Timeout Err, entry_num = %d\n",
1477                         __func__, p_dev->ahw->reset.seq_index);
1478                 dev_err(&p_dev->pdev->dev,
1479                         "0x%08x 0x%08x 0x%08x\n",
1480                         value, mask, status);
1481         }
1482
1483         return timeout_error;
1484 }
1485
1486 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1487 {
1488         u32 sum = 0;
1489         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1490         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1491
1492         while (count-- > 0)
1493                 sum += *buff++;
1494
1495         while (sum >> 16)
1496                 sum = (sum & 0xFFFF) + (sum >> 16);
1497
1498         if (~sum) {
1499                 return 0;
1500         } else {
1501                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1502                 return -1;
1503         }
1504 }
1505
1506 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1507 {
1508         u8 *p_buff;
1509         u32 addr, count;
1510         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1511
1512         ahw->reset.seq_error = 0;
1513         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1514         if (p_dev->ahw->reset.buff == NULL)
1515                 return -ENOMEM;
1516
1517         p_buff = p_dev->ahw->reset.buff;
1518         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1519         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1520
1521         /* Copy template header from flash */
1522         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1523                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1524                 return -EIO;
1525         }
1526         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1527         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1528         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1529         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1530
1531         /* Copy rest of the template */
1532         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1533                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1534                 return -EIO;
1535         }
1536
1537         if (qlcnic_83xx_reset_template_checksum(p_dev))
1538                 return -EIO;
1539         /* Get Stop, Start and Init command offsets */
1540         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1541         ahw->reset.start_offset = ahw->reset.buff +
1542                                   ahw->reset.hdr->start_offset;
1543         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1544         return 0;
1545 }
1546
1547 /* Read Write HW register command */
1548 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1549                                            u32 raddr, u32 waddr)
1550 {
1551         int value;
1552
1553         value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1554         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1555 }
1556
1557 /* Read Modify Write HW register command */
1558 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1559                                     u32 raddr, u32 waddr,
1560                                     struct qlc_83xx_rmw *p_rmw_hdr)
1561 {
1562         int value;
1563
1564         if (p_rmw_hdr->index_a)
1565                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1566         else
1567                 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1568
1569         value &= p_rmw_hdr->mask;
1570         value <<= p_rmw_hdr->shl;
1571         value >>= p_rmw_hdr->shr;
1572         value |= p_rmw_hdr->or_value;
1573         value ^= p_rmw_hdr->xor_value;
1574         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1575 }
1576
1577 /* Write HW register command */
1578 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1579                                    struct qlc_83xx_entry_hdr *p_hdr)
1580 {
1581         int i;
1582         struct qlc_83xx_entry *entry;
1583
1584         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1585                                           sizeof(struct qlc_83xx_entry_hdr));
1586
1587         for (i = 0; i < p_hdr->count; i++, entry++) {
1588                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1589                                              entry->arg2);
1590                 if (p_hdr->delay)
1591                         udelay((u32)(p_hdr->delay));
1592         }
1593 }
1594
1595 /* Read and Write instruction */
1596 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1597                                         struct qlc_83xx_entry_hdr *p_hdr)
1598 {
1599         int i;
1600         struct qlc_83xx_entry *entry;
1601
1602         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1603                                           sizeof(struct qlc_83xx_entry_hdr));
1604
1605         for (i = 0; i < p_hdr->count; i++, entry++) {
1606                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1607                                                entry->arg2);
1608                 if (p_hdr->delay)
1609                         udelay((u32)(p_hdr->delay));
1610         }
1611 }
1612
1613 /* Poll HW register command */
1614 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1615                                   struct qlc_83xx_entry_hdr *p_hdr)
1616 {
1617         long delay;
1618         struct qlc_83xx_entry *entry;
1619         struct qlc_83xx_poll *poll;
1620         int i;
1621         unsigned long arg1, arg2;
1622
1623         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1624                                         sizeof(struct qlc_83xx_entry_hdr));
1625
1626         entry = (struct qlc_83xx_entry *)((char *)poll +
1627                                           sizeof(struct qlc_83xx_poll));
1628         delay = (long)p_hdr->delay;
1629
1630         if (!delay) {
1631                 for (i = 0; i < p_hdr->count; i++, entry++)
1632                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1633                                              delay, poll->mask,
1634                                              poll->status);
1635         } else {
1636                 for (i = 0; i < p_hdr->count; i++, entry++) {
1637                         arg1 = entry->arg1;
1638                         arg2 = entry->arg2;
1639                         if (delay) {
1640                                 if (qlcnic_83xx_poll_reg(p_dev,
1641                                                          arg1, delay,
1642                                                          poll->mask,
1643                                                          poll->status)){
1644                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1645                                                                     arg1);
1646                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1647                                                                     arg2);
1648                                 }
1649                         }
1650                 }
1651         }
1652 }
1653
1654 /* Poll and write HW register command */
1655 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1656                                         struct qlc_83xx_entry_hdr *p_hdr)
1657 {
1658         int i;
1659         long delay;
1660         struct qlc_83xx_quad_entry *entry;
1661         struct qlc_83xx_poll *poll;
1662
1663         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1664                                         sizeof(struct qlc_83xx_entry_hdr));
1665         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1666                                                sizeof(struct qlc_83xx_poll));
1667         delay = (long)p_hdr->delay;
1668
1669         for (i = 0; i < p_hdr->count; i++, entry++) {
1670                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1671                                              entry->dr_value);
1672                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1673                                              entry->ar_value);
1674                 if (delay)
1675                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1676                                              poll->mask, poll->status);
1677         }
1678 }
1679
1680 /* Read Modify Write register command */
1681 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1682                                           struct qlc_83xx_entry_hdr *p_hdr)
1683 {
1684         int i;
1685         struct qlc_83xx_entry *entry;
1686         struct qlc_83xx_rmw *rmw_hdr;
1687
1688         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1689                                           sizeof(struct qlc_83xx_entry_hdr));
1690
1691         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1692                                           sizeof(struct qlc_83xx_rmw));
1693
1694         for (i = 0; i < p_hdr->count; i++, entry++) {
1695                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1696                                         entry->arg2, rmw_hdr);
1697                 if (p_hdr->delay)
1698                         udelay((u32)(p_hdr->delay));
1699         }
1700 }
1701
1702 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1703 {
1704         if (p_hdr->delay)
1705                 mdelay((u32)((long)p_hdr->delay));
1706 }
1707
1708 /* Read and poll register command */
1709 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1710                                        struct qlc_83xx_entry_hdr *p_hdr)
1711 {
1712         long delay;
1713         int index, i, j;
1714         struct qlc_83xx_quad_entry *entry;
1715         struct qlc_83xx_poll *poll;
1716         unsigned long addr;
1717
1718         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1719                                         sizeof(struct qlc_83xx_entry_hdr));
1720
1721         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1722                                                sizeof(struct qlc_83xx_poll));
1723         delay = (long)p_hdr->delay;
1724
1725         for (i = 0; i < p_hdr->count; i++, entry++) {
1726                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1727                                              entry->ar_value);
1728                 if (delay) {
1729                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1730                                                   poll->mask, poll->status)){
1731                                 index = p_dev->ahw->reset.array_index;
1732                                 addr = entry->dr_addr;
1733                                 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1734                                 p_dev->ahw->reset.array[index++] = j;
1735
1736                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1737                                         p_dev->ahw->reset.array_index = 1;
1738                         }
1739                 }
1740         }
1741 }
1742
1743 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1744 {
1745         p_dev->ahw->reset.seq_end = 1;
1746 }
1747
1748 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1749 {
1750         p_dev->ahw->reset.template_end = 1;
1751         if (p_dev->ahw->reset.seq_error == 0)
1752                 dev_err(&p_dev->pdev->dev,
1753                         "HW restart process completed successfully.\n");
1754         else
1755                 dev_err(&p_dev->pdev->dev,
1756                         "HW restart completed with timeout errors.\n");
1757 }
1758
1759 /**
1760 * qlcnic_83xx_exec_template_cmd
1761 *
1762 * @p_dev: adapter structure
1763 * @p_buff: Poiter to instruction template
1764 *
1765 * Template provides instructions to stop, restart and initalize firmware.
1766 * These instructions are abstracted as a series of read, write and
1767 * poll operations on hardware registers. Register information and operation
1768 * specifics are not exposed to the driver. Driver reads the template from
1769 * flash and executes the instructions located at pre-defined offsets.
1770 *
1771 * Returns: None
1772 * */
1773 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1774                                           char *p_buff)
1775 {
1776         int index, entries;
1777         struct qlc_83xx_entry_hdr *p_hdr;
1778         char *entry = p_buff;
1779
1780         p_dev->ahw->reset.seq_end = 0;
1781         p_dev->ahw->reset.template_end = 0;
1782         entries = p_dev->ahw->reset.hdr->entries;
1783         index = p_dev->ahw->reset.seq_index;
1784
1785         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1786                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1787
1788                 switch (p_hdr->cmd) {
1789                 case QLC_83XX_OPCODE_NOP:
1790                         break;
1791                 case QLC_83XX_OPCODE_WRITE_LIST:
1792                         qlcnic_83xx_write_list(p_dev, p_hdr);
1793                         break;
1794                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1795                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1796                         break;
1797                 case QLC_83XX_OPCODE_POLL_LIST:
1798                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1799                         break;
1800                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1801                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1802                         break;
1803                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1804                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1805                         break;
1806                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1807                         qlcnic_83xx_pause(p_hdr);
1808                         break;
1809                 case QLC_83XX_OPCODE_SEQ_END:
1810                         qlcnic_83xx_seq_end(p_dev);
1811                         break;
1812                 case QLC_83XX_OPCODE_TMPL_END:
1813                         qlcnic_83xx_template_end(p_dev);
1814                         break;
1815                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1816                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1817                         break;
1818                 default:
1819                         dev_err(&p_dev->pdev->dev,
1820                                 "%s: Unknown opcode 0x%04x in template %d\n",
1821                                 __func__, p_hdr->cmd, index);
1822                         break;
1823                 }
1824                 entry += p_hdr->size;
1825         }
1826         p_dev->ahw->reset.seq_index = index;
1827 }
1828
1829 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1830 {
1831         p_dev->ahw->reset.seq_index = 0;
1832
1833         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1834         if (p_dev->ahw->reset.seq_end != 1)
1835                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1836 }
1837
1838 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1839 {
1840         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1841         if (p_dev->ahw->reset.template_end != 1)
1842                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1843 }
1844
1845 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1846 {
1847         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1848         if (p_dev->ahw->reset.seq_end != 1)
1849                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1850 }
1851
1852 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1853 {
1854         int err = -EIO;
1855
1856         if (request_firmware(&adapter->ahw->fw_info.fw,
1857                              QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1858                 dev_err(&adapter->pdev->dev,
1859                         "No file FW image, loading flash FW image.\n");
1860                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1861                                     QLC_83XX_BOOT_FROM_FLASH);
1862         } else {
1863                 if (qlcnic_83xx_copy_fw_file(adapter))
1864                         return err;
1865                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1866                                     QLC_83XX_BOOT_FROM_FILE);
1867         }
1868
1869         return 0;
1870 }
1871
1872 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1873 {
1874         u32 val;
1875         int err = -EIO;
1876
1877         qlcnic_83xx_stop_hw(adapter);
1878
1879         /* Collect FW register dump if required */
1880         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1881         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1882                 qlcnic_dump_fw(adapter);
1883         qlcnic_83xx_init_hw(adapter);
1884
1885         if (qlcnic_83xx_copy_bootloader(adapter))
1886                 return err;
1887         /* Boot either flash image or firmware image from host file system */
1888         if (qlcnic_load_fw_file) {
1889                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1890                         return err;
1891         } else {
1892                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1893                                     QLC_83XX_BOOT_FROM_FLASH);
1894         }
1895
1896         qlcnic_83xx_start_hw(adapter);
1897         if (qlcnic_83xx_check_hw_status(adapter))
1898                 return -EIO;
1899
1900         return 0;
1901 }
1902
1903 /**
1904 * qlcnic_83xx_config_default_opmode
1905 *
1906 * @adapter: adapter structure
1907 *
1908 * Configure default driver operating mode
1909 *
1910 * Returns: Error code or Success(0)
1911 * */
1912 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1913 {
1914         u32 op_mode;
1915         struct qlcnic_hardware_context *ahw = adapter->ahw;
1916
1917         qlcnic_get_func_no(adapter);
1918         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1919
1920         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1921                 op_mode = QLC_83XX_DEFAULT_OPMODE;
1922
1923         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1924                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1925                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1926         } else {
1927                 return -EIO;
1928         }
1929
1930         return 0;
1931 }
1932
1933 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1934 {
1935         int err;
1936         struct qlcnic_info nic_info;
1937         struct qlcnic_hardware_context *ahw = adapter->ahw;
1938
1939         memset(&nic_info, 0, sizeof(struct qlcnic_info));
1940         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1941         if (err)
1942                 return -EIO;
1943
1944         ahw->physical_port = (u8) nic_info.phys_port;
1945         ahw->switch_mode = nic_info.switch_mode;
1946         ahw->max_tx_ques = nic_info.max_tx_ques;
1947         ahw->max_rx_ques = nic_info.max_rx_ques;
1948         ahw->capabilities = nic_info.capabilities;
1949         ahw->max_mac_filters = nic_info.max_mac_filters;
1950         ahw->max_mtu = nic_info.max_mtu;
1951
1952         /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
1953          * set in case device is SRIOV capable. VNIC and SRIOV are mutually
1954          * exclusive. So in case of sriov capable device load driver in
1955          * default mode
1956          */
1957         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
1958                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1959                 return ahw->nic_mode;
1960         }
1961
1962         if (ahw->capabilities & BIT_23)
1963                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1964         else
1965                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1966
1967         return ahw->nic_mode;
1968 }
1969
1970 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
1971 {
1972         int ret;
1973
1974         ret = qlcnic_83xx_get_nic_configuration(adapter);
1975         if (ret == -EIO)
1976                 return -EIO;
1977
1978         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
1979                 if (qlcnic_83xx_config_vnic_opmode(adapter))
1980                         return -EIO;
1981         } else if (ret == QLC_83XX_DEFAULT_MODE) {
1982                 if (qlcnic_83xx_config_default_opmode(adapter))
1983                         return -EIO;
1984         }
1985
1986         return 0;
1987 }
1988
1989 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
1990 {
1991         struct qlcnic_hardware_context *ahw = adapter->ahw;
1992
1993         if (ahw->port_type == QLCNIC_XGBE) {
1994                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
1995                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
1996                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1997                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1998
1999         } else if (ahw->port_type == QLCNIC_GBE) {
2000                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2001                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2002                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2003                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2004         }
2005         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2006         adapter->max_rds_rings = MAX_RDS_RINGS;
2007 }
2008
2009 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2010 {
2011         int err = -EIO;
2012
2013         qlcnic_83xx_get_minidump_template(adapter);
2014         if (qlcnic_83xx_get_port_info(adapter))
2015                 return err;
2016
2017         qlcnic_83xx_config_buff_descriptors(adapter);
2018         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2019         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2020
2021         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2022                  adapter->ahw->fw_hal_version);
2023
2024         return 0;
2025 }
2026
2027 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2028 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2029 {
2030         struct qlcnic_cmd_args cmd;
2031         u32 presence_mask, audit_mask;
2032         int status;
2033
2034         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2035         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2036
2037         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2038                 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2039                 cmd.req.arg[1] = BIT_31;
2040                 status = qlcnic_issue_cmd(adapter, &cmd);
2041                 if (status)
2042                         dev_err(&adapter->pdev->dev,
2043                                 "Failed to clean up the function resources\n");
2044                 qlcnic_free_mbx_args(&cmd);
2045         }
2046 }
2047
2048 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2049 {
2050         struct qlcnic_hardware_context *ahw = adapter->ahw;
2051
2052         if (qlcnic_sriov_vf_check(adapter))
2053                 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2054
2055         if (qlcnic_83xx_check_hw_status(adapter))
2056                 return -EIO;
2057
2058         /* Initilaize 83xx mailbox spinlock */
2059         spin_lock_init(&ahw->mbx_lock);
2060
2061         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2062         qlcnic_83xx_clear_function_resources(adapter);
2063
2064         /* register for NIC IDC AEN Events */
2065         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2066
2067         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2068                 qlcnic_83xx_read_flash_mfg_id(adapter);
2069
2070         if (qlcnic_83xx_idc_init(adapter))
2071                 return -EIO;
2072
2073         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2074         if (qlcnic_83xx_configure_opmode(adapter))
2075                 return -EIO;
2076
2077         /* Perform operating mode specific initialization */
2078         if (adapter->nic_ops->init_driver(adapter))
2079                 return -EIO;
2080
2081         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2082
2083         /* Periodically monitor device status */
2084         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2085
2086         return adapter->ahw->idc.err_code;
2087 }