2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include "qlcnic_sriov.h"
10 #include "qlcnic_hw.h"
12 /* Reset template definitions */
13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101
17 #define QLC_83XX_OPCODE_NOP 0x0000
18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004
21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24 #define QLC_83XX_OPCODE_SEQ_END 0x0040
25 #define QLC_83XX_OPCODE_TMPL_END 0x0080
26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
28 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
29 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
30 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
33 struct qlc_83xx_reset_hdr {
34 #if defined(__LITTLE_ENDIAN)
43 #elif defined(__BIG_ENDIAN)
55 /* Command entry header. */
56 struct qlc_83xx_entry_hdr {
57 #if defined(__LITTLE_ENDIAN)
62 #elif defined(__BIG_ENDIAN)
70 /* Generic poll command */
71 struct qlc_83xx_poll {
76 /* Read modify write command */
81 #if defined(__LITTLE_ENDIAN)
86 #elif defined(__BIG_ENDIAN)
94 /* Generic command with 2 DWORD */
95 struct qlc_83xx_entry {
100 /* Generic command with 4 DWORD */
101 struct qlc_83xx_quad_entry {
107 static const char *const qlc_83xx_idc_states[] = {
119 enum qlcnic_83xx_states {
120 QLC_83XX_IDC_DEV_UNKNOWN,
121 QLC_83XX_IDC_DEV_COLD,
122 QLC_83XX_IDC_DEV_INIT,
123 QLC_83XX_IDC_DEV_READY,
124 QLC_83XX_IDC_DEV_NEED_RESET,
125 QLC_83XX_IDC_DEV_NEED_QUISCENT,
126 QLC_83XX_IDC_DEV_FAILED,
127 QLC_83XX_IDC_DEV_QUISCENT
131 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
135 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
142 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
145 cur = adapter->ahw->idc.curr_state;
146 prev = adapter->ahw->idc.prev_state;
148 dev_info(&adapter->pdev->dev,
149 "current state = %s, prev state = %s\n",
150 adapter->ahw->idc.name[cur],
151 adapter->ahw->idc.name[prev]);
154 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
161 if (qlcnic_83xx_lock_driver(adapter))
165 val = adapter->portnum & 0xf;
168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
170 seconds = jiffies / HZ;
173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
174 adapter->ahw->idc.sec_counter = jiffies / HZ;
177 qlcnic_83xx_unlock_driver(adapter);
182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
187 val = val & ~(0x3 << (adapter->portnum * 2));
188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
198 if (qlcnic_83xx_lock_driver(adapter))
202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
204 val = val | QLC_83XX_IDC_MAJOR_VERSION;
205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
208 qlcnic_83xx_unlock_driver(adapter);
214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
215 int status, int lock)
220 if (qlcnic_83xx_lock_driver(adapter))
224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
227 val = val | (1 << adapter->portnum);
229 val = val & ~(1 << adapter->portnum);
231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
232 qlcnic_83xx_idc_update_minor_version(adapter);
235 qlcnic_83xx_unlock_driver(adapter);
240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
246 version = val & 0xFF;
248 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
249 dev_info(&adapter->pdev->dev,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
264 if (qlcnic_83xx_lock_driver(adapter))
268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
269 /* Clear gracefull reset bit */
270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
275 qlcnic_83xx_unlock_driver(adapter);
280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
286 if (qlcnic_83xx_lock_driver(adapter))
290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
292 val = val | (1 << adapter->portnum);
294 val = val & ~(1 << adapter->portnum);
295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
298 qlcnic_83xx_unlock_driver(adapter);
303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
309 if (seconds <= time_limit)
316 * qlcnic_83xx_idc_check_reset_ack_reg
318 * @adapter: adapter structure
320 * Check ACK wait limit and clear the functions which failed to ACK
322 * Return 0 if all functions have acknowledged the reset request.
324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
327 u32 ack, presence, val;
329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
332 dev_info(&adapter->pdev->dev,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
334 if (!((ack & presence) == presence)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter->pdev->dev,
338 "%s: ACK wait exceeds time limit\n", __func__);
339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
340 val = val & ~(ack ^ presence);
341 if (qlcnic_83xx_lock_driver(adapter))
343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
344 dev_info(&adapter->pdev->dev,
345 "%s: updated drv presence reg = 0x%x\n",
347 qlcnic_83xx_unlock_driver(adapter);
354 dev_info(&adapter->pdev->dev,
355 "%s: Reset ACK received from all functions\n",
362 * qlcnic_83xx_idc_tx_soft_reset
364 * @adapter: adapter structure
366 * Handle context deletion and recreation request from transmit routine
368 * Returns -EBUSY or Success (0)
371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
373 struct net_device *netdev = adapter->netdev;
375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
378 netif_device_detach(netdev);
379 qlcnic_down(adapter, netdev);
380 qlcnic_up(adapter, netdev);
381 netif_device_attach(netdev);
382 clear_bit(__QLCNIC_RESETTING, &adapter->state);
383 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
385 adapter->netdev->trans_start = jiffies;
391 * qlcnic_83xx_idc_detach_driver
393 * @adapter: adapter structure
394 * Detach net interface, stop TX and cleanup resources before the HW reset.
398 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
401 struct net_device *netdev = adapter->netdev;
403 netif_device_detach(netdev);
404 /* Disable mailbox interrupt */
405 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
406 qlcnic_down(adapter, netdev);
407 for (i = 0; i < adapter->ahw->num_msix; i++) {
408 adapter->ahw->intr_tbl[i].id = i;
409 adapter->ahw->intr_tbl[i].enabled = 0;
410 adapter->ahw->intr_tbl[i].src = 0;
415 * qlcnic_83xx_idc_attach_driver
417 * @adapter: adapter structure
419 * Re-attach and re-enable net interface
423 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
425 struct net_device *netdev = adapter->netdev;
427 if (netif_running(netdev)) {
428 if (qlcnic_up(adapter, netdev))
430 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
433 netif_device_attach(netdev);
434 if (netif_running(netdev)) {
435 netif_carrier_on(netdev);
436 netif_wake_queue(netdev);
440 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
444 if (qlcnic_83xx_lock_driver(adapter))
448 qlcnic_83xx_idc_clear_registers(adapter, 0);
449 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
451 qlcnic_83xx_unlock_driver(adapter);
453 qlcnic_83xx_idc_log_state_history(adapter);
454 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
459 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
463 if (qlcnic_83xx_lock_driver(adapter))
467 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
470 qlcnic_83xx_unlock_driver(adapter);
475 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
479 if (qlcnic_83xx_lock_driver(adapter))
483 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
484 QLC_83XX_IDC_DEV_NEED_QUISCENT);
487 qlcnic_83xx_unlock_driver(adapter);
493 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
496 if (qlcnic_83xx_lock_driver(adapter))
500 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
501 QLC_83XX_IDC_DEV_NEED_RESET);
504 qlcnic_83xx_unlock_driver(adapter);
509 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
513 if (qlcnic_83xx_lock_driver(adapter))
517 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
519 qlcnic_83xx_unlock_driver(adapter);
525 * qlcnic_83xx_idc_find_reset_owner_id
527 * @adapter: adapter structure
529 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
530 * Within the same class, function with lowest PCI ID assumes ownership
532 * Returns: reset owner id or failure indication (-EIO)
535 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
537 u32 reg, reg1, reg2, i, j, owner, class;
539 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
540 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
541 owner = QLCNIC_TYPE_NIC;
547 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
550 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
557 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
558 if (owner == QLCNIC_TYPE_NIC)
559 owner = QLCNIC_TYPE_ISCSI;
560 else if (owner == QLCNIC_TYPE_ISCSI)
561 owner = QLCNIC_TYPE_FCOE;
562 else if (owner == QLCNIC_TYPE_FCOE)
568 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
573 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
577 ret = qlcnic_83xx_restart_hw(adapter);
580 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
582 qlcnic_83xx_idc_clear_registers(adapter, lock);
583 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
589 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
593 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
595 if (status & QLCNIC_RCODE_FATAL_ERROR) {
596 dev_err(&adapter->pdev->dev,
597 "peg halt status1=0x%x\n", status);
598 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
599 dev_err(&adapter->pdev->dev,
600 "On board active cooling fan failed. "
601 "Device has been halted.\n");
602 dev_err(&adapter->pdev->dev,
603 "Replace the adapter.\n");
611 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
613 /* register for NIC IDC AEN Events */
614 qlcnic_83xx_register_nic_idc_func(adapter, 1);
616 qlcnic_83xx_enable_mbx_intrpt(adapter);
618 if (qlcnic_83xx_configure_opmode(adapter)) {
619 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
623 if (adapter->nic_ops->init_driver(adapter)) {
624 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
628 qlcnic_83xx_idc_attach_driver(adapter);
633 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
635 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
636 clear_bit(__QLCNIC_RESETTING, &adapter->state);
637 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
638 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
639 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
640 adapter->ahw->idc.quiesce_req = 0;
641 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
642 adapter->ahw->idc.err_code = 0;
643 adapter->ahw->idc.collect_dump = 0;
647 * qlcnic_83xx_idc_ready_state_entry
649 * @adapter: adapter structure
651 * Perform ready state initialization, this routine will get invoked only
652 * once from READY state.
654 * Returns: Error code or Success(0)
657 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
659 struct qlcnic_hardware_context *ahw = adapter->ahw;
661 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
662 qlcnic_83xx_idc_update_idc_params(adapter);
663 /* Re-attach the device if required */
664 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
665 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
666 if (qlcnic_83xx_idc_reattach_driver(adapter))
675 * qlcnic_83xx_idc_vnic_pf_entry
677 * @adapter: adapter structure
679 * Ensure vNIC mode privileged function starts only after vNIC mode is
680 * enabled by management function.
681 * If vNIC mode is ready, start initialization.
686 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
689 struct qlcnic_hardware_context *ahw = adapter->ahw;
691 /* Privileged function waits till mgmt function enables VNIC mode */
692 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
693 if (state != QLCNIC_DEV_NPAR_OPER) {
694 if (!ahw->idc.vnic_wait_limit--) {
695 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
698 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
702 /* Perform one time initialization from ready state */
703 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
704 qlcnic_83xx_idc_update_idc_params(adapter);
706 /* If the previous state is UNKNOWN, device will be
707 already attached properly by Init routine*/
708 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
709 if (qlcnic_83xx_idc_reattach_driver(adapter))
712 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
713 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
720 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
722 adapter->ahw->idc.err_code = -EIO;
723 dev_err(&adapter->pdev->dev,
724 "%s: Device in unknown state\n", __func__);
729 * qlcnic_83xx_idc_cold_state
731 * @adapter: adapter structure
733 * If HW is up and running device will enter READY state.
734 * If firmware image from host needs to be loaded, device is
735 * forced to start with the file firmware image.
737 * Returns: Error code or Success(0)
740 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
742 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
743 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
745 if (qlcnic_load_fw_file) {
746 qlcnic_83xx_idc_restart_hw(adapter, 0);
748 if (qlcnic_83xx_check_hw_status(adapter)) {
749 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
752 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
759 * qlcnic_83xx_idc_init_state
761 * @adapter: adapter structure
763 * Reset owner will restart the device from this state.
764 * Device will enter failed state if it remains
765 * in this state for more than DEV_INIT time limit.
767 * Returns: Error code or Success(0)
770 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
772 int timeout, ret = 0;
775 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
776 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
777 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
778 if (adapter->ahw->pci_func == owner)
779 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
781 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
789 * qlcnic_83xx_idc_ready_state
791 * @adapter: adapter structure
793 * Perform IDC protocol specicifed actions after monitoring device state and
796 * Returns: Error code or Success(0)
799 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
802 struct qlcnic_hardware_context *ahw = adapter->ahw;
805 /* Perform NIC configuration based ready state entry actions */
806 if (ahw->idc.state_entry(adapter))
809 if (qlcnic_check_temp(adapter)) {
810 if (ahw->temp == QLCNIC_TEMP_PANIC) {
811 qlcnic_83xx_idc_check_fan_failure(adapter);
812 dev_err(&adapter->pdev->dev,
813 "Error: device temperature %d above limits\n",
815 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
816 set_bit(__QLCNIC_RESETTING, &adapter->state);
817 qlcnic_83xx_idc_detach_driver(adapter);
818 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
823 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
824 ret = qlcnic_83xx_check_heartbeat(adapter);
826 adapter->flags |= QLCNIC_FW_HANG;
827 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
828 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
829 set_bit(__QLCNIC_RESETTING, &adapter->state);
830 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
835 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
836 /* Move to need reset state and prepare for reset */
837 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
841 /* Check for soft reset request */
842 if (ahw->reset_context &&
843 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
844 qlcnic_83xx_idc_tx_soft_reset(adapter);
848 /* Move to need quiesce state if requested */
849 if (adapter->ahw->idc.quiesce_req) {
850 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
851 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
859 * qlcnic_83xx_idc_need_reset_state
861 * @adapter: adapter structure
863 * Device will remain in this state until:
864 * Reset request ACK's are recieved from all the functions
865 * Wait time exceeds max time limit
867 * Returns: Error code or Success(0)
870 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
874 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
875 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
876 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
877 set_bit(__QLCNIC_RESETTING, &adapter->state);
878 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
879 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
880 qlcnic_83xx_disable_vnic_mode(adapter, 1);
881 qlcnic_83xx_idc_detach_driver(adapter);
884 /* Check ACK from other functions */
885 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
887 dev_info(&adapter->pdev->dev,
888 "%s: Waiting for reset ACK\n", __func__);
892 /* Transit to INIT state and restart the HW */
893 qlcnic_83xx_idc_enter_init_state(adapter, 1);
898 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
900 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
904 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
906 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
907 adapter->ahw->idc.err_code = -EIO;
912 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
914 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
918 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
923 cur = adapter->ahw->idc.curr_state;
924 prev = adapter->ahw->idc.prev_state;
927 if ((next < QLC_83XX_IDC_DEV_COLD) ||
928 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
929 dev_err(&adapter->pdev->dev,
930 "%s: curr %d, prev %d, next state %d is invalid\n",
931 __func__, cur, prev, state);
935 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
936 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
937 if ((next != QLC_83XX_IDC_DEV_COLD) &&
938 (next != QLC_83XX_IDC_DEV_READY)) {
939 dev_err(&adapter->pdev->dev,
940 "%s: failed, cur %d prev %d next %d\n",
941 __func__, cur, prev, next);
946 if (next == QLC_83XX_IDC_DEV_INIT) {
947 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
948 (prev != QLC_83XX_IDC_DEV_COLD) &&
949 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
950 dev_err(&adapter->pdev->dev,
951 "%s: failed, cur %d prev %d next %d\n",
952 __func__, cur, prev, next);
960 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
962 if (adapter->fhash.fnum)
963 qlcnic_prune_lb_filters(adapter);
967 * qlcnic_83xx_idc_poll_dev_state
969 * @work: kernel work queue structure used to schedule the function
971 * Poll device state periodically and perform state specific
972 * actions defined by Inter Driver Communication (IDC) protocol.
977 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
979 struct qlcnic_adapter *adapter;
982 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
983 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
985 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
986 qlcnic_83xx_idc_log_state_history(adapter);
987 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
989 adapter->ahw->idc.curr_state = state;
992 switch (adapter->ahw->idc.curr_state) {
993 case QLC_83XX_IDC_DEV_READY:
994 qlcnic_83xx_idc_ready_state(adapter);
996 case QLC_83XX_IDC_DEV_NEED_RESET:
997 qlcnic_83xx_idc_need_reset_state(adapter);
999 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1000 qlcnic_83xx_idc_need_quiesce_state(adapter);
1002 case QLC_83XX_IDC_DEV_FAILED:
1003 qlcnic_83xx_idc_failed_state(adapter);
1005 case QLC_83XX_IDC_DEV_INIT:
1006 qlcnic_83xx_idc_init_state(adapter);
1008 case QLC_83XX_IDC_DEV_QUISCENT:
1009 qlcnic_83xx_idc_quiesce_state(adapter);
1012 qlcnic_83xx_idc_unknown_state(adapter);
1015 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1016 qlcnic_83xx_periodic_tasks(adapter);
1018 /* Re-schedule the function */
1019 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1020 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1021 adapter->ahw->idc.delay);
1024 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1026 u32 idc_params, val;
1028 if (qlcnic_83xx_lockless_flash_read32(adapter,
1029 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1030 (u8 *)&idc_params, 1)) {
1031 dev_info(&adapter->pdev->dev,
1032 "%s:failed to get IDC params from flash\n", __func__);
1033 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1034 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1036 adapter->dev_init_timeo = idc_params & 0xFFFF;
1037 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1040 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1041 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1042 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1043 adapter->ahw->idc.err_code = 0;
1044 adapter->ahw->idc.collect_dump = 0;
1045 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1047 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1048 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1049 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1051 /* Check if reset recovery is disabled */
1052 if (!qlcnic_auto_fw_reset) {
1053 /* Propagate do not reset request to other functions */
1054 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1055 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1056 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1061 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1065 if (qlcnic_83xx_lock_driver(adapter))
1068 /* Clear driver lock register */
1069 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1070 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1071 qlcnic_83xx_unlock_driver(adapter);
1075 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1076 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1077 qlcnic_83xx_unlock_driver(adapter);
1081 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1082 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1083 QLC_83XX_IDC_DEV_COLD);
1084 state = QLC_83XX_IDC_DEV_COLD;
1087 adapter->ahw->idc.curr_state = state;
1088 /* First to load function should cold boot the device */
1089 if (state == QLC_83XX_IDC_DEV_COLD)
1090 qlcnic_83xx_idc_cold_state_handler(adapter);
1092 /* Check if reset recovery is enabled */
1093 if (qlcnic_auto_fw_reset) {
1094 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1095 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1096 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1099 qlcnic_83xx_unlock_driver(adapter);
1104 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1108 qlcnic_83xx_setup_idc_parameters(adapter);
1110 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1113 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1114 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1117 if (qlcnic_83xx_idc_check_major_version(adapter))
1121 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1126 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1131 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1132 usleep_range(10000, 11000);
1134 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1137 if (id == adapter->portnum) {
1138 dev_err(&adapter->pdev->dev,
1139 "%s: wait for lock recovery.. %d\n", __func__, id);
1141 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1145 /* Clear driver presence bit */
1146 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1147 val = val & ~(1 << adapter->portnum);
1148 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1149 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1150 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1152 cancel_delayed_work_sync(&adapter->fw_work);
1155 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1159 if (qlcnic_83xx_lock_driver(adapter)) {
1160 dev_err(&adapter->pdev->dev,
1161 "%s:failed, please retry\n", __func__);
1165 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1166 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1167 !qlcnic_auto_fw_reset) {
1168 dev_err(&adapter->pdev->dev,
1169 "%s:failed, device in non reset mode\n", __func__);
1170 qlcnic_83xx_unlock_driver(adapter);
1174 if (key == QLCNIC_FORCE_FW_RESET) {
1175 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1176 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1177 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1178 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1179 adapter->ahw->idc.collect_dump = 1;
1182 qlcnic_83xx_unlock_driver(adapter);
1186 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1193 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1194 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1195 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1197 /* alignment check */
1199 size = (size + 16) & ~0xF;
1201 p_cache = kzalloc(size, GFP_KERNEL);
1202 if (p_cache == NULL)
1205 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1206 size / sizeof(u32));
1211 /* 16 byte write to MS memory */
1212 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1223 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1231 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1232 size = (adapter->ahw->fw_info.fw->size & ~0xF);
1233 p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1236 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1237 (u32 *)p_cache, size / 16);
1239 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1240 release_firmware(adapter->ahw->fw_info.fw);
1241 adapter->ahw->fw_info.fw = NULL;
1245 /* alignment check */
1246 if (adapter->ahw->fw_info.fw->size & 0xF) {
1248 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1249 data[i] = adapter->ahw->fw_info.fw->data[size + i];
1252 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1255 dev_err(&adapter->pdev->dev,
1256 "MS memory write failed\n");
1257 release_firmware(adapter->ahw->fw_info.fw);
1258 adapter->ahw->fw_info.fw = NULL;
1262 release_firmware(adapter->ahw->fw_info.fw);
1263 adapter->ahw->fw_info.fw = NULL;
1268 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1271 u32 val = 0, val1 = 0, reg = 0;
1273 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1274 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1276 for (j = 0; j < 2; j++) {
1278 dev_info(&adapter->pdev->dev,
1279 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1280 reg = QLC_83XX_PORT0_THRESHOLD;
1281 } else if (j == 1) {
1282 dev_info(&adapter->pdev->dev,
1283 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1284 reg = QLC_83XX_PORT1_THRESHOLD;
1286 for (i = 0; i < 8; i++) {
1287 val = QLCRD32(adapter, reg + (i * 0x4));
1288 dev_info(&adapter->pdev->dev, "0x%x ", val);
1290 dev_info(&adapter->pdev->dev, "\n");
1293 for (j = 0; j < 2; j++) {
1295 dev_info(&adapter->pdev->dev,
1296 "Port 0 RxB TC Max Cell Registers[4..1]:");
1297 reg = QLC_83XX_PORT0_TC_MC_REG;
1298 } else if (j == 1) {
1299 dev_info(&adapter->pdev->dev,
1300 "Port 1 RxB TC Max Cell Registers[4..1]:");
1301 reg = QLC_83XX_PORT1_TC_MC_REG;
1303 for (i = 0; i < 4; i++) {
1304 val = QLCRD32(adapter, reg + (i * 0x4));
1305 dev_info(&adapter->pdev->dev, "0x%x ", val);
1307 dev_info(&adapter->pdev->dev, "\n");
1310 for (j = 0; j < 2; j++) {
1312 dev_info(&adapter->pdev->dev,
1313 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1314 reg = QLC_83XX_PORT0_TC_STATS;
1315 } else if (j == 1) {
1316 dev_info(&adapter->pdev->dev,
1317 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1318 reg = QLC_83XX_PORT1_TC_STATS;
1320 for (i = 7; i >= 0; i--) {
1321 val = QLCRD32(adapter, reg);
1322 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1323 QLCWR32(adapter, reg, (val | (i << 29)));
1324 val = QLCRD32(adapter, reg);
1325 dev_info(&adapter->pdev->dev, "0x%x ", val);
1327 dev_info(&adapter->pdev->dev, "\n");
1330 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1331 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1332 dev_info(&adapter->pdev->dev,
1333 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1338 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1342 if (qlcnic_83xx_lock_driver(adapter)) {
1343 dev_err(&adapter->pdev->dev,
1344 "%s:failed to acquire driver lock\n", __func__);
1348 qlcnic_83xx_dump_pause_control_regs(adapter);
1349 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1351 for (j = 0; j < 2; j++) {
1353 reg = QLC_83XX_PORT0_THRESHOLD;
1355 reg = QLC_83XX_PORT1_THRESHOLD;
1357 for (i = 0; i < 8; i++)
1358 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1361 for (j = 0; j < 2; j++) {
1363 reg = QLC_83XX_PORT0_TC_MC_REG;
1365 reg = QLC_83XX_PORT1_TC_MC_REG;
1367 for (i = 0; i < 4; i++)
1368 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1371 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1372 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1373 dev_info(&adapter->pdev->dev,
1374 "Disabled pause frames successfully on all ports\n");
1375 qlcnic_83xx_unlock_driver(adapter);
1378 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1380 u32 heartbeat, peg_status;
1381 int retries, ret = -EIO;
1383 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1384 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1385 QLCNIC_PEG_ALIVE_COUNTER);
1388 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1389 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1390 QLCNIC_PEG_ALIVE_COUNTER);
1391 if (heartbeat != p_dev->heartbeat) {
1392 ret = QLCNIC_RCODE_SUCCESS;
1395 } while (--retries);
1398 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1399 qlcnic_83xx_disable_pause_frames(p_dev);
1400 peg_status = QLC_SHARED_REG_RD32(p_dev,
1401 QLCNIC_PEG_HALT_STATUS1);
1402 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1403 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1404 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1405 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1406 "PEG_NET_4_PC: 0x%x\n", peg_status,
1407 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1408 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1409 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1410 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1411 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1412 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1414 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1415 dev_err(&p_dev->pdev->dev,
1416 "Device is being reset err code 0x00006700.\n");
1422 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1424 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1428 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1429 if (val == QLC_83XX_CMDPEG_COMPLETE)
1431 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1432 } while (--retries);
1434 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1438 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1442 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1446 err = qlcnic_83xx_check_heartbeat(p_dev);
1453 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1454 int duration, u32 mask, u32 status)
1460 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1461 retries = duration / 10;
1464 if ((value & mask) != status) {
1466 msleep(duration / 10);
1467 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1472 } while (retries--);
1474 if (timeout_error) {
1475 p_dev->ahw->reset.seq_error++;
1476 dev_err(&p_dev->pdev->dev,
1477 "%s: Timeout Err, entry_num = %d\n",
1478 __func__, p_dev->ahw->reset.seq_index);
1479 dev_err(&p_dev->pdev->dev,
1480 "0x%08x 0x%08x 0x%08x\n",
1481 value, mask, status);
1484 return timeout_error;
1487 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1490 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1491 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1497 sum = (sum & 0xFFFF) + (sum >> 16);
1502 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1507 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1511 struct qlcnic_hardware_context *ahw = p_dev->ahw;
1513 ahw->reset.seq_error = 0;
1514 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1515 if (p_dev->ahw->reset.buff == NULL)
1518 p_buff = p_dev->ahw->reset.buff;
1519 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1520 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1522 /* Copy template header from flash */
1523 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1524 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1527 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1528 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1529 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1530 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1532 /* Copy rest of the template */
1533 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1534 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1538 if (qlcnic_83xx_reset_template_checksum(p_dev))
1540 /* Get Stop, Start and Init command offsets */
1541 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1542 ahw->reset.start_offset = ahw->reset.buff +
1543 ahw->reset.hdr->start_offset;
1544 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1548 /* Read Write HW register command */
1549 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1550 u32 raddr, u32 waddr)
1554 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1555 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1558 /* Read Modify Write HW register command */
1559 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1560 u32 raddr, u32 waddr,
1561 struct qlc_83xx_rmw *p_rmw_hdr)
1565 if (p_rmw_hdr->index_a)
1566 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1568 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1570 value &= p_rmw_hdr->mask;
1571 value <<= p_rmw_hdr->shl;
1572 value >>= p_rmw_hdr->shr;
1573 value |= p_rmw_hdr->or_value;
1574 value ^= p_rmw_hdr->xor_value;
1575 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1578 /* Write HW register command */
1579 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1580 struct qlc_83xx_entry_hdr *p_hdr)
1583 struct qlc_83xx_entry *entry;
1585 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1586 sizeof(struct qlc_83xx_entry_hdr));
1588 for (i = 0; i < p_hdr->count; i++, entry++) {
1589 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1592 udelay((u32)(p_hdr->delay));
1596 /* Read and Write instruction */
1597 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1598 struct qlc_83xx_entry_hdr *p_hdr)
1601 struct qlc_83xx_entry *entry;
1603 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1604 sizeof(struct qlc_83xx_entry_hdr));
1606 for (i = 0; i < p_hdr->count; i++, entry++) {
1607 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1610 udelay((u32)(p_hdr->delay));
1614 /* Poll HW register command */
1615 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1616 struct qlc_83xx_entry_hdr *p_hdr)
1619 struct qlc_83xx_entry *entry;
1620 struct qlc_83xx_poll *poll;
1622 unsigned long arg1, arg2;
1624 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1625 sizeof(struct qlc_83xx_entry_hdr));
1627 entry = (struct qlc_83xx_entry *)((char *)poll +
1628 sizeof(struct qlc_83xx_poll));
1629 delay = (long)p_hdr->delay;
1632 for (i = 0; i < p_hdr->count; i++, entry++)
1633 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1637 for (i = 0; i < p_hdr->count; i++, entry++) {
1641 if (qlcnic_83xx_poll_reg(p_dev,
1645 qlcnic_83xx_rd_reg_indirect(p_dev,
1647 qlcnic_83xx_rd_reg_indirect(p_dev,
1655 /* Poll and write HW register command */
1656 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1657 struct qlc_83xx_entry_hdr *p_hdr)
1661 struct qlc_83xx_quad_entry *entry;
1662 struct qlc_83xx_poll *poll;
1664 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1665 sizeof(struct qlc_83xx_entry_hdr));
1666 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1667 sizeof(struct qlc_83xx_poll));
1668 delay = (long)p_hdr->delay;
1670 for (i = 0; i < p_hdr->count; i++, entry++) {
1671 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1673 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1676 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1677 poll->mask, poll->status);
1681 /* Read Modify Write register command */
1682 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1683 struct qlc_83xx_entry_hdr *p_hdr)
1686 struct qlc_83xx_entry *entry;
1687 struct qlc_83xx_rmw *rmw_hdr;
1689 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1690 sizeof(struct qlc_83xx_entry_hdr));
1692 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1693 sizeof(struct qlc_83xx_rmw));
1695 for (i = 0; i < p_hdr->count; i++, entry++) {
1696 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1697 entry->arg2, rmw_hdr);
1699 udelay((u32)(p_hdr->delay));
1703 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1706 mdelay((u32)((long)p_hdr->delay));
1709 /* Read and poll register command */
1710 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1711 struct qlc_83xx_entry_hdr *p_hdr)
1715 struct qlc_83xx_quad_entry *entry;
1716 struct qlc_83xx_poll *poll;
1719 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1720 sizeof(struct qlc_83xx_entry_hdr));
1722 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1723 sizeof(struct qlc_83xx_poll));
1724 delay = (long)p_hdr->delay;
1726 for (i = 0; i < p_hdr->count; i++, entry++) {
1727 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1730 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1731 poll->mask, poll->status)){
1732 index = p_dev->ahw->reset.array_index;
1733 addr = entry->dr_addr;
1734 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1735 p_dev->ahw->reset.array[index++] = j;
1737 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1738 p_dev->ahw->reset.array_index = 1;
1744 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1746 p_dev->ahw->reset.seq_end = 1;
1749 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1751 p_dev->ahw->reset.template_end = 1;
1752 if (p_dev->ahw->reset.seq_error == 0)
1753 dev_err(&p_dev->pdev->dev,
1754 "HW restart process completed successfully.\n");
1756 dev_err(&p_dev->pdev->dev,
1757 "HW restart completed with timeout errors.\n");
1761 * qlcnic_83xx_exec_template_cmd
1763 * @p_dev: adapter structure
1764 * @p_buff: Poiter to instruction template
1766 * Template provides instructions to stop, restart and initalize firmware.
1767 * These instructions are abstracted as a series of read, write and
1768 * poll operations on hardware registers. Register information and operation
1769 * specifics are not exposed to the driver. Driver reads the template from
1770 * flash and executes the instructions located at pre-defined offsets.
1774 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1778 struct qlc_83xx_entry_hdr *p_hdr;
1779 char *entry = p_buff;
1781 p_dev->ahw->reset.seq_end = 0;
1782 p_dev->ahw->reset.template_end = 0;
1783 entries = p_dev->ahw->reset.hdr->entries;
1784 index = p_dev->ahw->reset.seq_index;
1786 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1787 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1789 switch (p_hdr->cmd) {
1790 case QLC_83XX_OPCODE_NOP:
1792 case QLC_83XX_OPCODE_WRITE_LIST:
1793 qlcnic_83xx_write_list(p_dev, p_hdr);
1795 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1796 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1798 case QLC_83XX_OPCODE_POLL_LIST:
1799 qlcnic_83xx_poll_list(p_dev, p_hdr);
1801 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1802 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1804 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1805 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1807 case QLC_83XX_OPCODE_SEQ_PAUSE:
1808 qlcnic_83xx_pause(p_hdr);
1810 case QLC_83XX_OPCODE_SEQ_END:
1811 qlcnic_83xx_seq_end(p_dev);
1813 case QLC_83XX_OPCODE_TMPL_END:
1814 qlcnic_83xx_template_end(p_dev);
1816 case QLC_83XX_OPCODE_POLL_READ_LIST:
1817 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1820 dev_err(&p_dev->pdev->dev,
1821 "%s: Unknown opcode 0x%04x in template %d\n",
1822 __func__, p_hdr->cmd, index);
1825 entry += p_hdr->size;
1827 p_dev->ahw->reset.seq_index = index;
1830 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1832 p_dev->ahw->reset.seq_index = 0;
1834 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1835 if (p_dev->ahw->reset.seq_end != 1)
1836 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1839 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1841 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1842 if (p_dev->ahw->reset.template_end != 1)
1843 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1846 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1848 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1849 if (p_dev->ahw->reset.seq_end != 1)
1850 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1853 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1857 if (request_firmware(&adapter->ahw->fw_info.fw,
1858 QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1859 dev_err(&adapter->pdev->dev,
1860 "No file FW image, loading flash FW image.\n");
1861 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1862 QLC_83XX_BOOT_FROM_FLASH);
1864 if (qlcnic_83xx_copy_fw_file(adapter))
1866 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1867 QLC_83XX_BOOT_FROM_FILE);
1873 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1878 qlcnic_83xx_stop_hw(adapter);
1880 /* Collect FW register dump if required */
1881 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1882 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1883 qlcnic_dump_fw(adapter);
1884 qlcnic_83xx_init_hw(adapter);
1886 if (qlcnic_83xx_copy_bootloader(adapter))
1888 /* Boot either flash image or firmware image from host file system */
1889 if (qlcnic_load_fw_file) {
1890 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1893 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1894 QLC_83XX_BOOT_FROM_FLASH);
1897 qlcnic_83xx_start_hw(adapter);
1898 if (qlcnic_83xx_check_hw_status(adapter))
1905 * qlcnic_83xx_config_default_opmode
1907 * @adapter: adapter structure
1909 * Configure default driver operating mode
1911 * Returns: Error code or Success(0)
1913 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1916 struct qlcnic_hardware_context *ahw = adapter->ahw;
1918 qlcnic_get_func_no(adapter);
1919 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1921 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1922 op_mode = QLC_83XX_DEFAULT_OPMODE;
1924 if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1925 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1926 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1934 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1937 struct qlcnic_info nic_info;
1938 struct qlcnic_hardware_context *ahw = adapter->ahw;
1940 memset(&nic_info, 0, sizeof(struct qlcnic_info));
1941 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1945 ahw->physical_port = (u8) nic_info.phys_port;
1946 ahw->switch_mode = nic_info.switch_mode;
1947 ahw->max_tx_ques = nic_info.max_tx_ques;
1948 ahw->max_rx_ques = nic_info.max_rx_ques;
1949 ahw->capabilities = nic_info.capabilities;
1950 ahw->max_mac_filters = nic_info.max_mac_filters;
1951 ahw->max_mtu = nic_info.max_mtu;
1953 /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
1954 * set in case device is SRIOV capable. VNIC and SRIOV are mutually
1955 * exclusive. So in case of sriov capable device load driver in
1958 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
1959 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1960 return ahw->nic_mode;
1963 if (ahw->capabilities & BIT_23)
1964 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1966 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1968 return ahw->nic_mode;
1971 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
1975 ret = qlcnic_83xx_get_nic_configuration(adapter);
1979 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
1980 if (qlcnic_83xx_config_vnic_opmode(adapter))
1982 } else if (ret == QLC_83XX_DEFAULT_MODE) {
1983 if (qlcnic_83xx_config_default_opmode(adapter))
1990 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
1992 struct qlcnic_hardware_context *ahw = adapter->ahw;
1994 if (ahw->port_type == QLCNIC_XGBE) {
1995 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
1996 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
1997 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1998 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2000 } else if (ahw->port_type == QLCNIC_GBE) {
2001 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2002 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2003 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2004 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2006 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2007 adapter->max_rds_rings = MAX_RDS_RINGS;
2010 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2014 qlcnic_83xx_get_minidump_template(adapter);
2015 if (qlcnic_83xx_get_port_info(adapter))
2018 qlcnic_83xx_config_buff_descriptors(adapter);
2019 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2020 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2022 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2023 adapter->ahw->fw_hal_version);
2028 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2029 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2031 struct qlcnic_cmd_args cmd;
2032 u32 presence_mask, audit_mask;
2035 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2036 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2038 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2039 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2040 cmd.req.arg[1] = BIT_31;
2041 status = qlcnic_issue_cmd(adapter, &cmd);
2043 dev_err(&adapter->pdev->dev,
2044 "Failed to clean up the function resources\n");
2045 qlcnic_free_mbx_args(&cmd);
2049 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2051 struct qlcnic_hardware_context *ahw = adapter->ahw;
2053 if (qlcnic_sriov_vf_check(adapter))
2054 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2056 if (qlcnic_83xx_check_hw_status(adapter))
2059 /* Initilaize 83xx mailbox spinlock */
2060 spin_lock_init(&ahw->mbx_lock);
2062 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2063 qlcnic_83xx_clear_function_resources(adapter);
2065 /* register for NIC IDC AEN Events */
2066 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2068 if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2069 qlcnic_83xx_read_flash_mfg_id(adapter);
2071 if (qlcnic_83xx_idc_init(adapter))
2074 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2075 if (qlcnic_83xx_configure_opmode(adapter))
2078 /* Perform operating mode specific initialization */
2079 if (adapter->nic_ops->init_driver(adapter))
2082 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2084 /* Periodically monitor device status */
2085 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2087 return adapter->ahw->idc.err_code;